opcodes/ChangeLog

   1 2020-07-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
   4         MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
   5         MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
   6         MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
   7         enumerators.
   8         (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
   9         EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
  10         EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
  11         EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
  12         (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
  13         EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
  14         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
  15         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
  16         these, respectively.
  17         * i386-dis-evex-len.h: Adjust comments.
  18         * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
  19         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
  20         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
  21         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
  22         MOD_EVEX_0F385B_P_2_W_1 table entries.
  23         * i386-dis-evex-w.h: Reference mod_table[] for
  24         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
  25         EVEX_W_0F385B_P_2.
  26
  27 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  28
  29         * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
  30         vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
  31         EXymm.
  32         (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
  33         Likewise. Mark 256-bit entries invalid.
  34
  35 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  36
  37         * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
  38         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
  39         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
  40         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
  41         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
  42         PREFIX_EVEX_0F382B): Delete.
  43         (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
  44         EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
  45         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
  46         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
  47         EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
  48         to ...
  49         (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
  50         EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
  51         EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
  52         EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
  53         respectively.
  54         * i386-dis-evex.h (evex_table): Reference VEX_W table entries
  55         for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
  56         0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
  57         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
  58         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
  59         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
  60         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
  61         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
  62         PREFIX_EVEX_0F382B): Remove table entries.
  63         * i386-dis-evex-w.h: Reference VEX table entries for opcodes
  64         0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
  65         0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
  66
  67 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  68
  69         * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
  70         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
  71         enumerators.
  72         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
  73         EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
  74         EVEX_LEN_0F3A01_P_2_W_1 table entries.
  75         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
  76         entries.
  77
  78 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  79
  80         * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
  81         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
  82         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
  83         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
  84         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
  85         EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
  86         EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
  87         EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
  88         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
  89         entries.
  90
  91 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
  94         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
  95         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
  96         respectively.
  97         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
  98         entries.
  99         * i386-dis-evex.h (evex_table): Reference VEX table entry for
 100         opcode 0F3A1D.
 101         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
 102         entry.
 103         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
 104
 105 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 106
 107         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
 108         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 109         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
 110         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
 111         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 112         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
 113         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
 114         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
 115         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 116         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
 117         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
 118         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
 119         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
 120         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
 121         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
 122         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
 123         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
 124         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
 125         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
 126         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
 127         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
 128         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
 129         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
 130         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
 131         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
 132         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
 133         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
 134         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
 135         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
 136         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
 137         (prefix_table): Add EXxEVexR to FMA table entries.
 138         (OP_Rounding): Move abort() invocation.
 139         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
 140         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
 141         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
 142         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
 143         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
 144         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
 145         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
 146         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
 147         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
 148         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
 149         0F3ACE, 0F3ACF.
 150         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
 151         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 152         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
 153         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
 154         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 155         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
 156         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
 157         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
 158         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 159         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
 160         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
 161         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
 162         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
 163         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
 164         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
 165         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
 166         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
 167         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
 168         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
 169         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
 170         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
 171         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
 172         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
 173         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
 174         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
 175         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
 176         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
 177         Delete table entries.
 178         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
 179         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
 180         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
 181         Likewise.
 182
 183 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 184
 185         * i386-dis.c (EXqScalarS): Delete.
 186         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
 187         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
 188
 189 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 190
 191         * i386-dis.c (safe-ctype.h): Include.
 192         (EXdScalar, EXqScalar): Delete.
 193         (d_scalar_mode, q_scalar_mode): Delete.
 194         (prefix_table, vex_len_table): Use EXxmm_md in place of
 195         EXdScalar and EXxmm_mq in place of EXqScalar.
 196         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
 197         d_scalar_mode and q_scalar_mode.
 198         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
 199         (vmovsd): Use EXxmm_mq.
 200
 201 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
 202
 203         PR 26204
 204         * arc-dis.c: Fix spelling mistake.
 205         * po/opcodes.pot: Regenerate.
 206
 207 2020-07-06  Nick Clifton  <nickc@redhat.com>
 208
 209         * po/pt_BR.po: Updated Brazilian Portugugese translation.
 210         * po/uk.po: Updated Ukranian translation.
 211
 212 2020-07-04  Nick Clifton  <nickc@redhat.com>
 213
 214         * configure: Regenerate.
 215         * po/opcodes.pot: Regenerate.
 216
 217 2020-07-04  Nick Clifton  <nickc@redhat.com>
 218
 219         Binutils 2.35 branch created.
 220
 221 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
 222
 223         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
 224         * i386-opc.h (VexSwapSources): New.
 225         (i386_opcode_modifier): Add vexswapsources.
 226         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
 227         with two source operands swapped.
 228         * i386-tbl.h: Regenerated.
 229
 230 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
 231
 232         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
 233         unprivileged CSR can also be initialized.
 234
 235 2020-06-29  Alan Modra  <amodra@gmail.com>
 236
 237         * arm-dis.c: Use C style comments.
 238         * cr16-opc.c: Likewise.
 239         * ft32-dis.c: Likewise.
 240         * moxie-opc.c: Likewise.
 241         * tic54x-dis.c: Likewise.
 242         * s12z-opc.c: Remove useless comment.
 243         * xgate-dis.c: Likewise.
 244
 245 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 246
 247         * i386-opc.tbl: Add a blank line.
 248
 249 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 250
 251         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
 252         (VecSIB128): Renamed to ...
 253         (VECSIB128): This.
 254         (VecSIB256): Renamed to ...
 255         (VECSIB256): This.
 256         (VecSIB512): Renamed to ...
 257         (VECSIB512): This.
 258         (VecSIB): Renamed to ...
 259         (SIB): This.
 260         (i386_opcode_modifier): Replace vecsib with sib.
 261         * i386-opc.tbl (VecSIB128): New.
 262         (VecSIB256): Likewise.
 263         (VecSIB512): Likewise.
 264         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
 265         and VecSIB512, respectively.
 266
 267 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 268
 269         * i386-dis.c: Adjust description of I macro.
 270         (x86_64_table): Drop use of I.
 271         (float_mem): Replace use of I.
 272         (putop): Remove handling of I. Adjust setting/clearing of "alt".
 273
 274 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 275
 276         * i386-dis.c: (print_insn): Avoid straight assignment to
 277         priv.orig_sizeflag when processing -M sub-options.
 278
 279 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 280
 281         * i386-dis.c: Adjust description of J macro.
 282         (dis386, x86_64_table, mod_table): Replace J.
 283         (putop): Remove handling of J.
 284
 285 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 286
 287         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
 288
 289 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 290
 291         * i386-dis.c: Adjust description of "LQ" macro.
 292         (dis386_twobyte): Use LQ for sysret.
 293         (putop): Adjust handling of LQ.
 294
 295 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
 296
 297         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
 298         * riscv-dis.c: Include elfxx-riscv.h.
 299
 300 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
 301
 302         * i386-dis.c (prefix_table): Revert the last vmgexit change.
 303
 304 2020-06-17  Lili Cui  <lili.cui@intel.com>
 305
 306         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
 307
 308 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
 309
 310         PR gas/26115
 311         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
 312         * i386-opc.tbl: Likewise.
 313         * i386-tbl.h: Regenerated.
 314
 315 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
 316
 317         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
 318
 319 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
 320
 321         * aarch64-opc.c (SYSREG): New macro for describing system registers.
 322         (SR_CORE): Likewise.
 323         (SR_FEAT): Likewise.
 324         (SR_RNG): Likewise.
 325         (SR_V8_1): Likewise.
 326         (SR_V8_2): Likewise.
 327         (SR_V8_3): Likewise.
 328         (SR_V8_4): Likewise.
 329         (SR_PAN): Likewise.
 330         (SR_RAS): Likewise.
 331         (SR_SSBS): Likewise.
 332         (SR_SVE): Likewise.
 333         (SR_ID_PFR2): Likewise.
 334         (SR_PROFILE): Likewise.
 335         (SR_MEMTAG): Likewise.
 336         (SR_SCXTNUM): Likewise.
 337         (aarch64_sys_regs): Refactor to store feature information in the table.
 338         (aarch64_sys_reg_supported_p): Collapse logic for system registers
 339         that now describe their own features.
 340         (aarch64_pstatefield_supported_p): Likewise.
 341
 342 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 343
 344         * i386-dis.c (prefix_table): Fix a typo in comments.
 345
 346 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 347
 348         * i386-dis.c (rex_ignored): Delete.
 349         (ckprefix): Drop rex_ignored initialization.
 350         (get_valid_dis386): Drop setting of rex_ignored.
 351         (print_insn): Drop checking of rex_ignored. Don't record data
 352         size prefix as used with VEX-and-alike encodings.
 353
 354 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 355
 356         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 357         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 358         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 359         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 360         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 361         VEX_0F12, and VEX_0F16.
 362         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 363         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 364         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 365         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 366         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 367         MOD_VEX_0F16_PREFIX_2 entries.
 368
 369 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 370
 371         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 372         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 373         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 374         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 375         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 376         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 377         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 378         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 379         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 380         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 381         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 382         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 383         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 384         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 385         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 386         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 387         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 388         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 389         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 390         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 391         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 392         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 393         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 394         EVEX_W_0FC6_P_2): Delete.
 395         (print_insn): Add EVEX.W vs embedded prefix consistency check
 396         to prefix validation.
 397         * i386-dis-evex.h (evex_table): Don't further descend for
 398         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 399         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 400         and 0F2B.
 401         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 402         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 403         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 404         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 405         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 406         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 407         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 408         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 409         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 410         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 411         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 412         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 413         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 414         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 415         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 416         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 417         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 418         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 419         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 420         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 421         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 422         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 423         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 424         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 425         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 426         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 427         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 428
 429 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 430
 431         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 432         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 433         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 434         vmovmskpX.
 435         (print_insn): Drop pointless check against bad_opcode. Split
 436         prefix validation into legacy and VEX-and-alike parts.
 437         (putop): Re-work 'X' macro handling.
 438
 439 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 440
 441         * i386-dis.c (MOD_0F51): Rename to ...
 442         (MOD_0F50): ... this.
 443
 444 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 445
 446         * arm-dis.c (arm_opcodes): Add dfb.
 447         (thumb32_opcodes): Add dfb.
 448
 449 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 450
 451         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 452
 453 2020-06-06  Alan Modra  <amodra@gmail.com>
 454
 455         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 456
 457 2020-06-05  Alan Modra  <amodra@gmail.com>
 458
 459         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 460         size is large enough.
 461
 462 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 463
 464         * disassemble.c (disassemble_init_for_target): Set endian_code for
 465         bpf targets.
 466         * bpf-desc.c: Regenerate.
 467         * bpf-opc.c: Likewise.
 468         * bpf-dis.c: Likewise.
 469
 470 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 471
 472         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 473         (cgen_put_insn_value): Likewise.
 474         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 475         * cgen-dis.in (print_insn): Likewise.
 476         * cgen-ibld.in (insert_1): Likewise.
 477         (insert_1): Likewise.
 478         (insert_insn_normal): Likewise.
 479         (extract_1): Likewise.
 480         * bpf-dis.c: Regenerate.
 481         * bpf-ibld.c: Likewise.
 482         * bpf-ibld.c: Likewise.
 483         * cgen-dis.in: Likewise.
 484         * cgen-ibld.in: Likewise.
 485         * cgen-opc.c: Likewise.
 486         * epiphany-dis.c: Likewise.
 487         * epiphany-ibld.c: Likewise.
 488         * fr30-dis.c: Likewise.
 489         * fr30-ibld.c: Likewise.
 490         * frv-dis.c: Likewise.
 491         * frv-ibld.c: Likewise.
 492         * ip2k-dis.c: Likewise.
 493         * ip2k-ibld.c: Likewise.
 494         * iq2000-dis.c: Likewise.
 495         * iq2000-ibld.c: Likewise.
 496         * lm32-dis.c: Likewise.
 497         * lm32-ibld.c: Likewise.
 498         * m32c-dis.c: Likewise.
 499         * m32c-ibld.c: Likewise.
 500         * m32r-dis.c: Likewise.
 501         * m32r-ibld.c: Likewise.
 502         * mep-dis.c: Likewise.
 503         * mep-ibld.c: Likewise.
 504         * mt-dis.c: Likewise.
 505         * mt-ibld.c: Likewise.
 506         * or1k-dis.c: Likewise.
 507         * or1k-ibld.c: Likewise.
 508         * xc16x-dis.c: Likewise.
 509         * xc16x-ibld.c: Likewise.
 510         * xstormy16-dis.c: Likewise.
 511         * xstormy16-ibld.c: Likewise.
 512
 513 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 514
 515         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 516         (print_insn_): Handle instruction endian.
 517         * bpf-dis.c: Regenerate.
 518         * bpf-desc.c: Regenerate.
 519         * epiphany-dis.c: Likewise.
 520         * epiphany-desc.c: Likewise.
 521         * fr30-dis.c: Likewise.
 522         * fr30-desc.c: Likewise.
 523         * frv-dis.c: Likewise.
 524         * frv-desc.c: Likewise.
 525         * ip2k-dis.c: Likewise.
 526         * ip2k-desc.c: Likewise.
 527         * iq2000-dis.c: Likewise.
 528         * iq2000-desc.c: Likewise.
 529         * lm32-dis.c: Likewise.
 530         * lm32-desc.c: Likewise.
 531         * m32c-dis.c: Likewise.
 532         * m32c-desc.c: Likewise.
 533         * m32r-dis.c: Likewise.
 534         * m32r-desc.c: Likewise.
 535         * mep-dis.c: Likewise.
 536         * mep-desc.c: Likewise.
 537         * mt-dis.c: Likewise.
 538         * mt-desc.c: Likewise.
 539         * or1k-dis.c: Likewise.
 540         * or1k-desc.c: Likewise.
 541         * xc16x-dis.c: Likewise.
 542         * xc16x-desc.c: Likewise.
 543         * xstormy16-dis.c: Likewise.
 544         * xstormy16-desc.c: Likewise.
 545
 546 2020-06-03  Nick Clifton  <nickc@redhat.com>
 547
 548         * po/sr.po: Updated Serbian translation.
 549
 550 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 551
 552         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 553         (riscv_get_priv_spec_class): Likewise.
 554
 555 2020-06-01  Alan Modra  <amodra@gmail.com>
 556
 557         * bpf-desc.c: Regenerate.
 558
 559 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 560             David Faust <david.faust@oracle.com>
 561
 562         * bpf-desc.c: Regenerate.
 563         * bpf-opc.h: Likewise.
 564         * bpf-opc.c: Likewise.
 565         * bpf-dis.c: Likewise.
 566
 567 2020-05-28  Alan Modra  <amodra@gmail.com>
 568
 569         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 570         values.
 571
 572 2020-05-28  Alan Modra  <amodra@gmail.com>
 573
 574         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 575         immediates.
 576         (print_insn_ns32k): Revert last change.
 577
 578 2020-05-28  Nick Clifton  <nickc@redhat.com>
 579
 580         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 581         static.
 582
 583 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 584
 585         Fix extraction of signed constants in nios2 disassembler (again).
 586
 587         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 588         extractions of signed fields.
 589
 590 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 591
 592         * s390-opc.txt: Relocate vector load/store instructions with
 593         additional alignment parameter and change architecture level
 594         constraint from z14 to z13.
 595
 596 2020-05-21  Alan Modra  <amodra@gmail.com>
 597
 598         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 599         * sparc-dis.c: Likewise.
 600         * tic4x-dis.c: Likewise.
 601         * xtensa-dis.c: Likewise.
 602         * bpf-desc.c: Regenerate.
 603         * epiphany-desc.c: Regenerate.
 604         * fr30-desc.c: Regenerate.
 605         * frv-desc.c: Regenerate.
 606         * ip2k-desc.c: Regenerate.
 607         * iq2000-desc.c: Regenerate.
 608         * lm32-desc.c: Regenerate.
 609         * m32c-desc.c: Regenerate.
 610         * m32r-desc.c: Regenerate.
 611         * mep-asm.c: Regenerate.
 612         * mep-desc.c: Regenerate.
 613         * mt-desc.c: Regenerate.
 614         * or1k-desc.c: Regenerate.
 615         * xc16x-desc.c: Regenerate.
 616         * xstormy16-desc.c: Regenerate.
 617
 618 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 619
 620         * riscv-opc.c (riscv_ext_version_table): The table used to store
 621         all information about the supported spec and the corresponding ISA
 622         versions.  Currently, only Zicsr is supported to verify the
 623         correctness of Z sub extension settings.  Others will be supported
 624         in the future patches.
 625         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 626         classes and the corresponding strings.
 627         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 628         spec class by giving a ISA spec string.
 629         * riscv-opc.c (struct priv_spec_t): New structure.
 630         (struct priv_spec_t priv_specs): List for all supported privilege spec
 631         classes and the corresponding strings.
 632         (riscv_get_priv_spec_class): New function.  Get the corresponding
 633         privilege spec class by giving a spec string.
 634         (riscv_get_priv_spec_name): New function.  Get the corresponding
 635         privilege spec string by giving a CSR version class.
 636         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 637         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 638         according to the chosen version.  Build a hash table riscv_csr_hash to
 639         store the valid CSR for the chosen pirv verison.  Dump the direct
 640         CSR address rather than it's name if it is invalid.
 641         (parse_riscv_dis_option_without_args): New function.  Parse the options
 642         without arguments.
 643         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 644         parse the options without arguments first, and then handle the options
 645         with arguments.  Add the new option -Mpriv-spec, which has argument.
 646         * riscv-dis.c (print_riscv_disassembler_options): Add description
 647         about the new OBJDUMP option.
 648
 649 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 650
 651         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 652         WC values on POWER10 sync, dcbf  and wait instructions.
 653         (insert_pl, extract_pl): New functions.
 654         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 655         (LS3): New , 3-bit L for sync.
 656         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 657         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 658         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 659         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 660         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 661         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 662         <wait>: Enable PL operand on POWER10.
 663         <dcbf>: Enable L3OPT operand on POWER10.
 664         <sync>: Enable SC2 operand on POWER10.
 665
 666 2020-05-19  Stafford Horne  <shorne@gmail.com>
 667
 668         PR 25184
 669         * or1k-asm.c: Regenerate.
 670         * or1k-desc.c: Regenerate.
 671         * or1k-desc.h: Regenerate.
 672         * or1k-dis.c: Regenerate.
 673         * or1k-ibld.c: Regenerate.
 674         * or1k-opc.c: Regenerate.
 675         * or1k-opc.h: Regenerate.
 676         * or1k-opinst.c: Regenerate.
 677
 678 2020-05-11  Alan Modra  <amodra@gmail.com>
 679
 680         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 681         xsmaxcqp, xsmincqp.
 682
 683 2020-05-11  Alan Modra  <amodra@gmail.com>
 684
 685         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 686         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 687
 688 2020-05-11  Alan Modra  <amodra@gmail.com>
 689
 690         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 691
 692 2020-05-11  Alan Modra  <amodra@gmail.com>
 693
 694         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 695         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 696
 697 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 698
 699         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 700         mnemonics.
 701
 702 2020-05-11  Alan Modra  <amodra@gmail.com>
 703
 704         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 705         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 706         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 707         (prefix_opcodes): Add xxeval.
 708
 709 2020-05-11  Alan Modra  <amodra@gmail.com>
 710
 711         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 712         xxgenpcvwm, xxgenpcvdm.
 713
 714 2020-05-11  Alan Modra  <amodra@gmail.com>
 715
 716         * ppc-opc.c (MP, VXVAM_MASK): Define.
 717         (VXVAPS_MASK): Use VXVA_MASK.
 718         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 719         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 720         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 721         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 722
 723 2020-05-11  Alan Modra  <amodra@gmail.com>
 724             Peter Bergner  <bergner@linux.ibm.com>
 725
 726         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 727         New functions.
 728         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 729         YMSK2, XA6a, XA6ap, XB6a entries.
 730         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 731         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 732         (PPCVSX4): Define.
 733         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 734         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 735         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 736         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 737         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 738         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 739         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 740         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 741         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 742         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 743         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 744         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 745         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 746         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 747
 748 2020-05-11  Alan Modra  <amodra@gmail.com>
 749
 750         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 751         (insert_xts, extract_xts): New functions.
 752         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 753         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 754         (VXRC_MASK, VXSH_MASK): Define.
 755         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 756         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 757         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 758         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 759         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 760         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 761         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 762
 763 2020-05-11  Alan Modra  <amodra@gmail.com>
 764
 765         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 766         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 767         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 768         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 769         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 770
 771 2020-05-11  Alan Modra  <amodra@gmail.com>
 772
 773         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 774         (XTP, DQXP, DQXP_MASK): Define.
 775         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 776         (prefix_opcodes): Add plxvp and pstxvp.
 777
 778 2020-05-11  Alan Modra  <amodra@gmail.com>
 779
 780         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 781         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 782         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 783
 784 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 785
 786         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 787
 788 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 789
 790         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 791         (L1OPT): Define.
 792         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 793
 794 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 795
 796         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 797
 798 2020-05-11  Alan Modra  <amodra@gmail.com>
 799
 800         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 801
 802 2020-05-11  Alan Modra  <amodra@gmail.com>
 803
 804         * ppc-dis.c (ppc_opts): Add "power10" entry.
 805         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 806         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 807
 808 2020-05-11  Nick Clifton  <nickc@redhat.com>
 809
 810         * po/fr.po: Updated French translation.
 811
 812 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 813
 814         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 815         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 816         (operand_general_constraint_met_p): validate
 817         AARCH64_OPND_UNDEFINED.
 818         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 819         for FLD_imm16_2.
 820         * aarch64-asm-2.c: Regenerated.
 821         * aarch64-dis-2.c: Regenerated.
 822         * aarch64-opc-2.c: Regenerated.
 823
 824 2020-04-29  Nick Clifton  <nickc@redhat.com>
 825
 826         PR 22699
 827         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 828         and SETRC insns.
 829
 830 2020-04-29  Nick Clifton  <nickc@redhat.com>
 831
 832         * po/sv.po: Updated Swedish translation.
 833
 834 2020-04-29  Nick Clifton  <nickc@redhat.com>
 835
 836         PR 22699
 837         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 838         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 839         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 840         IMM0_8U case.
 841
 842 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 843
 844         PR 25848
 845         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 846         cmpi only on m68020up and cpu32.
 847
 848 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 849
 850         * aarch64-asm.c (aarch64_ins_none): New.
 851         * aarch64-asm.h (ins_none): New declaration.
 852         * aarch64-dis.c (aarch64_ext_none): New.
 853         * aarch64-dis.h (ext_none): New declaration.
 854         * aarch64-opc.c (aarch64_print_operand): Update case for
 855         AARCH64_OPND_BARRIER_PSB.
 856         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 857         (AARCH64_OPERANDS): Update inserter/extracter for
 858         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 859         * aarch64-asm-2.c: Regenerated.
 860         * aarch64-dis-2.c: Regenerated.
 861         * aarch64-opc-2.c: Regenerated.
 862
 863 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 864
 865         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 866         (aarch64_feature_ras, RAS): Likewise.
 867         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 868         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 869         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 870         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 871         * aarch64-asm-2.c: Regenerated.
 872         * aarch64-dis-2.c: Regenerated.
 873         * aarch64-opc-2.c: Regenerated.
 874
 875 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 876
 877         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 878         (print_insn_neon): Support disassembly of conditional
 879         instructions.
 880
 881 2020-02-16  David Faust  <david.faust@oracle.com>
 882
 883         * bpf-desc.c: Regenerate.
 884         * bpf-desc.h: Likewise.
 885         * bpf-opc.c: Regenerate.
 886         * bpf-opc.h: Likewise.
 887
 888 2020-04-07  Lili Cui  <lili.cui@intel.com>
 889
 890         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 891         (prefix_table): New instructions (see prefixes above).
 892         (rm_table): Likewise
 893         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 894         CPU_ANY_TSXLDTRK_FLAGS.
 895         (cpu_flags): Add CpuTSXLDTRK.
 896         * i386-opc.h (enum): Add CpuTSXLDTRK.
 897         (i386_cpu_flags): Add cputsxldtrk.
 898         * i386-opc.tbl: Add XSUSPLDTRK insns.
 899         * i386-init.h: Regenerate.
 900         * i386-tbl.h: Likewise.
 901
 902 2020-04-02  Lili Cui  <lili.cui@intel.com>
 903
 904         * i386-dis.c (prefix_table): New instructions serialize.
 905         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 906         CPU_ANY_SERIALIZE_FLAGS.
 907         (cpu_flags): Add CpuSERIALIZE.
 908         * i386-opc.h (enum): Add CpuSERIALIZE.
 909         (i386_cpu_flags): Add cpuserialize.
 910         * i386-opc.tbl: Add SERIALIZE insns.
 911         * i386-init.h: Regenerate.
 912         * i386-tbl.h: Likewise.
 913
 914 2020-03-26  Alan Modra  <amodra@gmail.com>
 915
 916         * disassemble.h (opcodes_assert): Declare.
 917         (OPCODES_ASSERT): Define.
 918         * disassemble.c: Don't include assert.h.  Include opintl.h.
 919         (opcodes_assert): New function.
 920         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 921         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 922         calculate maxlen.  Omit insn decoding when insn length exceeds
 923         maxlen.  Exit from nibble loop when looking for E, before
 924         accessing next data byte.  Move processing of E outside loop.
 925         Replace tests of maxlen in loop with assertions.
 926
 927 2020-03-26  Alan Modra  <amodra@gmail.com>
 928
 929         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 930
 931 2020-03-25  Alan Modra  <amodra@gmail.com>
 932
 933         * z80-dis.c (suffix): Init mybuf.
 934
 935 2020-03-22  Alan Modra  <amodra@gmail.com>
 936
 937         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 938         successflly read from section.
 939
 940 2020-03-22  Alan Modra  <amodra@gmail.com>
 941
 942         * arc-dis.c (find_format): Use ISO C string concatenation rather
 943         than line continuation within a string.  Don't access needs_limm
 944         before testing opcode != NULL.
 945
 946 2020-03-22  Alan Modra  <amodra@gmail.com>
 947
 948         * ns32k-dis.c (print_insn_arg): Update comment.
 949         (print_insn_ns32k): Reduce size of index_offset array, and
 950         initialize, passing -1 to print_insn_arg for args that are not
 951         an index.  Don't exit arg loop early.  Abort on bad arg number.
 952
 953 2020-03-22  Alan Modra  <amodra@gmail.com>
 954
 955         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 956         * s12z-opc.c: Formatting.
 957         (operands_f): Return an int.
 958         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 959         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 960         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 961         (exg_sex_discrim): Likewise.
 962         (create_immediate_operand, create_bitfield_operand),
 963         (create_register_operand_with_size, create_register_all_operand),
 964         (create_register_all16_operand, create_simple_memory_operand),
 965         (create_memory_operand, create_memory_auto_operand): Don't
 966         segfault on malloc failure.
 967         (z_ext24_decode): Return an int status, negative on fail, zero
 968         on success.
 969         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 970         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 971         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 972         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 973         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 974         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 975         (loop_primitive_decode, shift_decode, psh_pul_decode),
 976         (bit_field_decode): Similarly.
 977         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 978         to return value, update callers.
 979         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 980         Don't segfault on NULL operand.
 981         (decode_operation): Return OP_INVALID on first fail.
 982         (decode_s12z): Check all reads, returning -1 on fail.
 983
 984 2020-03-20  Alan Modra  <amodra@gmail.com>
 985
 986         * metag-dis.c (print_insn_metag): Don't ignore status from
 987         read_memory_func.
 988
 989 2020-03-20  Alan Modra  <amodra@gmail.com>
 990
 991         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 992         Initialize parts of buffer not written when handling a possible
 993         2-byte insn at end of section.  Don't attempt decoding of such
 994         an insn by the 4-byte machinery.
 995
 996 2020-03-20  Alan Modra  <amodra@gmail.com>
 997
 998         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 999         partially filled buffer.  Prevent lookup of 4-byte insns when
1000         only VLE 2-byte insns are possible due to section size.  Print
1001         ".word" rather than ".long" for 2-byte leftovers.
1002
1003 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
1004
1005         PR 25641
1006         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1007
1008 2020-03-13  Jan Beulich  <jbeulich@suse.com>
1009
1010         * i386-dis.c (X86_64_0D): Rename to ...
1011         (X86_64_0E): ... this.
1012
1013 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1014
1015         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1016         * Makefile.in: Regenerated.
1017
1018 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1019
1020         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1021         3-operand pseudos.
1022         * i386-tbl.h: Re-generate.
1023
1024 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1025
1026         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1027         vprot*, vpsha*, and vpshl*.
1028         * i386-tbl.h: Re-generate.
1029
1030 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1031
1032         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1033         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1034         * i386-tbl.h: Re-generate.
1035
1036 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1037
1038         * i386-gen.c (set_bitfield): Ignore zero-length field names.
1039         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1040         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1041         * i386-tbl.h: Re-generate.
1042
1043 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1044
1045         * i386-gen.c (struct template_arg, struct template_instance,
1046         struct template_param, struct template, templates,
1047         parse_template, expand_templates): New.
1048         (process_i386_opcodes): Various local variables moved to
1049         expand_templates. Call parse_template and expand_templates.
1050         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1051         * i386-tbl.h: Re-generate.
1052
1053 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1054
1055         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1056         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1057         register and memory source templates. Replace VexW= by VexW*
1058         where applicable.
1059         * i386-tbl.h: Re-generate.
1060
1061 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1062
1063         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1064         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1065         * i386-tbl.h: Re-generate.
1066
1067 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1068
1069         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1070         * i386-tbl.h: Re-generate.
1071
1072 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1073
1074         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1075         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1076         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1077         VexW0 on SSE2AVX variants.
1078         (vmovq): Drop NoRex64 from XMM/XMM variants.
1079         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1080         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1081         applicable use VexW0.
1082         * i386-tbl.h: Re-generate.
1083
1084 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1085
1086         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1087         * i386-opc.h (Rex64): Delete.
1088         (struct i386_opcode_modifier): Remove rex64 field.
1089         * i386-opc.tbl (crc32): Drop Rex64.
1090         Replace Rex64 with Size64 everywhere else.
1091         * i386-tbl.h: Re-generate.
1092
1093 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1094
1095         * i386-dis.c (OP_E_memory): Exclude recording of used address
1096         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1097         addressed memory operands for MPX insns.
1098
1099 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1100
1101         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1102         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1103         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1104         (ptwrite): Split into non-64-bit and 64-bit forms.
1105         * i386-tbl.h: Re-generate.
1106
1107 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1108
1109         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1110         template.
1111         * i386-tbl.h: Re-generate.
1112
1113 2020-03-04  Jan Beulich  <jbeulich@suse.com>
1114
1115         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1116         (prefix_table): Move vmmcall here. Add vmgexit.
1117         (rm_table): Replace vmmcall entry by prefix_table[] escape.
1118         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1119         (cpu_flags): Add CpuSEV_ES entry.
1120         * i386-opc.h (CpuSEV_ES): New.
1121         (union i386_cpu_flags): Add cpusev_es field.
1122         * i386-opc.tbl (vmgexit): New.
1123         * i386-init.h, i386-tbl.h: Re-generate.
1124
1125 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1126
1127         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1128         with MnemonicSize.
1129         * i386-opc.h (IGNORESIZE): New.
1130         (DEFAULTSIZE): Likewise.
1131         (IgnoreSize): Removed.
1132         (DefaultSize): Likewise.
1133         (MnemonicSize): New.
1134         (i386_opcode_modifier): Replace ignoresize/defaultsize with
1135         mnemonicsize.
1136         * i386-opc.tbl (IgnoreSize): New.
1137         (DefaultSize): Likewise.
1138         * i386-tbl.h: Regenerated.
1139
1140 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1141
1142         PR 25627
1143         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1144         instructions.
1145
1146 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1147
1148         PR gas/25622
1149         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1150         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1151         * i386-tbl.h: Regenerated.
1152
1153 2020-02-26  Alan Modra  <amodra@gmail.com>
1154
1155         * aarch64-asm.c: Indent labels correctly.
1156         * aarch64-dis.c: Likewise.
1157         * aarch64-gen.c: Likewise.
1158         * aarch64-opc.c: Likewise.
1159         * alpha-dis.c: Likewise.
1160         * i386-dis.c: Likewise.
1161         * nds32-asm.c: Likewise.
1162         * nfp-dis.c: Likewise.
1163         * visium-dis.c: Likewise.
1164
1165 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
1166
1167         * arc-regs.h (int_vector_base): Make it available for all ARC
1168         CPUs.
1169
1170 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
1171
1172         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1173         changed.
1174
1175 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
1176
1177         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1178         c.mv/c.li if rs1 is zero.
1179
1180 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
1181
1182         * i386-gen.c (cpu_flag_init): Replace CpuABM with
1183         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
1184         CPU_POPCNT_FLAGS.
1185         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
1186         * i386-opc.h (CpuABM): Removed.
1187         (CpuPOPCNT): New.
1188         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
1189         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1190         popcnt.  Remove CpuABM from lzcnt.
1191         * i386-init.h: Regenerated.
1192         * i386-tbl.h: Likewise.
1193
1194 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1195
1196         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1197         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1198         VexW1 instead of open-coding them.
1199         * i386-tbl.h: Re-generate.
1200
1201 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1202
1203         * i386-opc.tbl (AddrPrefixOpReg): Define.
1204         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1205         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1206         templates. Drop NoRex64.
1207         * i386-tbl.h: Re-generate.
1208
1209 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1210
1211         PR gas/6518
1212         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1213         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1214         into Intel syntax instance (with Unpsecified) and AT&T one
1215         (without).
1216         (vcvtneps2bf16): Likewise, along with folding the two so far
1217         separate ones.
1218         * i386-tbl.h: Re-generate.
1219
1220 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1221
1222         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1223         CPU_ANY_SSE4A_FLAGS.
1224
1225 2020-02-17  Alan Modra  <amodra@gmail.com>
1226
1227         * i386-gen.c (cpu_flag_init): Correct last change.
1228
1229 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1230
1231         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
1232         CPU_ANY_SSE4_FLAGS.
1233
1234 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
1235
1236         * i386-opc.tbl (movsx): Remove Intel syntax comments.
1237         (movzx): Likewise.
1238
1239 2020-02-14  Jan Beulich  <jbeulich@suse.com>
1240
1241         PR gas/25438
1242         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1243         destination for Cpu64-only variant.
1244         (movzx): Fold patterns.
1245         * i386-tbl.h: Re-generate.
1246
1247 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1248
1249         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1250         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1251         CPU_ANY_SSE4_FLAGS entry.
1252         * i386-init.h: Re-generate.
1253
1254 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1255
1256         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1257         with Unspecified, making the present one AT&T syntax only.
1258         * i386-tbl.h: Re-generate.
1259
1260 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1261
1262         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1263         * i386-tbl.h: Re-generate.
1264
1265 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1266
1267         PR gas/24546
1268         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1269         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1270         Amd64 and Intel64 templates.
1271         (call, jmp): Likewise for far indirect variants. Dro
1272         Unspecified.
1273         * i386-tbl.h: Re-generate.
1274
1275 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1276
1277         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1278         * i386-opc.h (ShortForm): Delete.
1279         (struct i386_opcode_modifier): Remove shortform field.
1280         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1281         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1282         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1283         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1284         Drop ShortForm.
1285         * i386-tbl.h: Re-generate.
1286
1287 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1288
1289         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1290         fucompi): Drop ShortForm from operand-less templates.
1291         * i386-tbl.h: Re-generate.
1292
1293 2020-02-11  Alan Modra  <amodra@gmail.com>
1294
1295         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1296         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1297         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1298         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1299         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1300
1301 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1302
1303         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1304         (cde_opcodes): Add VCX* instructions.
1305
1306 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1307             Matthew Malcomson  <matthew.malcomson@arm.com>
1308
1309         * arm-dis.c (struct cdeopcode32): New.
1310         (CDE_OPCODE): New macro.
1311         (cde_opcodes): New disassembly table.
1312         (regnames): New option to table.
1313         (cde_coprocs): New global variable.
1314         (print_insn_cde): New
1315         (print_insn_thumb32): Use print_insn_cde.
1316         (parse_arm_disassembler_options): Parse coprocN args.
1317
1318 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1319
1320         PR gas/25516
1321         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1322         with ISA64.
1323         * i386-opc.h (AMD64): Removed.
1324         (Intel64): Likewose.
1325         (AMD64): New.
1326         (INTEL64): Likewise.
1327         (INTEL64ONLY): Likewise.
1328         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1329         * i386-opc.tbl (Amd64): New.
1330         (Intel64): Likewise.
1331         (Intel64Only): Likewise.
1332         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1333         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1334         * i386-tbl.h: Regenerated.
1335
1336 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1337
1338         PR 25469
1339         * z80-dis.c: Add support for GBZ80 opcodes.
1340
1341 2020-02-04  Alan Modra  <amodra@gmail.com>
1342
1343         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1344
1345 2020-02-03  Alan Modra  <amodra@gmail.com>
1346
1347         * m32c-ibld.c: Regenerate.
1348
1349 2020-02-01  Alan Modra  <amodra@gmail.com>
1350
1351         * frv-ibld.c: Regenerate.
1352
1353 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1354
1355         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1356         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1357         (OP_E_memory): Replace xmm_mdq_mode case label by
1358         vex_scalar_w_dq_mode one.
1359         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1360
1361 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1362
1363         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1364         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1365         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1366         (intel_operand_size): Drop vex_w_dq_mode case label.
1367
1368 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1369
1370         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1371         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1372
1373 2020-01-30  Alan Modra  <amodra@gmail.com>
1374
1375         * m32c-ibld.c: Regenerate.
1376
1377 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1378
1379         * bpf-opc.c: Regenerate.
1380
1381 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1382
1383         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1384         (dis386): Use them to replace C2/C3 table entries.
1385         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1386         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1387         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1388         * i386-tbl.h: Re-generate.
1389
1390 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1391
1392         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1393         forms.
1394         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1395         DefaultSize.
1396         * i386-tbl.h: Re-generate.
1397
1398 2020-01-30  Alan Modra  <amodra@gmail.com>
1399
1400         * tic4x-dis.c (tic4x_dp): Make unsigned.
1401
1402 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1403             Jan Beulich  <jbeulich@suse.com>
1404
1405         PR binutils/25445
1406         * i386-dis.c (MOVSXD_Fixup): New function.
1407         (movsxd_mode): New enum.
1408         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1409         (intel_operand_size): Handle movsxd_mode.
1410         (OP_E_register): Likewise.
1411         (OP_G): Likewise.
1412         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1413         register on movsxd.  Add movsxd with 16-bit destination register
1414         for AMD64 and Intel64 ISAs.
1415         * i386-tbl.h: Regenerated.
1416
1417 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1418
1419         PR 25403
1420         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1421         * aarch64-asm-2.c: Regenerate
1422         * aarch64-dis-2.c: Likewise.
1423         * aarch64-opc-2.c: Likewise.
1424
1425 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1426
1427         * i386-opc.tbl (sysret): Drop DefaultSize.
1428         * i386-tbl.h: Re-generate.
1429
1430 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1431
1432         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1433         Dword.
1434         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1435         * i386-tbl.h: Re-generate.
1436
1437 2020-01-20  Nick Clifton  <nickc@redhat.com>
1438
1439         * po/de.po: Updated German translation.
1440         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1441         * po/uk.po: Updated Ukranian translation.
1442
1443 2020-01-20  Alan Modra  <amodra@gmail.com>
1444
1445         * hppa-dis.c (fput_const): Remove useless cast.
1446
1447 2020-01-20  Alan Modra  <amodra@gmail.com>
1448
1449         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1450
1451 2020-01-18  Nick Clifton  <nickc@redhat.com>
1452
1453         * configure: Regenerate.
1454         * po/opcodes.pot: Regenerate.
1455
1456 2020-01-18  Nick Clifton  <nickc@redhat.com>
1457
1458         Binutils 2.34 branch created.
1459
1460 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1461
1462         * opintl.h: Fix spelling error (seperate).
1463
1464 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1465
1466         * i386-opc.tbl: Add {vex} pseudo prefix.
1467         * i386-tbl.h: Regenerated.
1468
1469 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1470
1471         PR 25376
1472         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1473         (neon_opcodes): Likewise.
1474         (select_arm_features): Make sure we enable MVE bits when selecting
1475         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1476         any architecture.
1477
1478 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1479
1480         * i386-opc.tbl: Drop stale comment from XOP section.
1481
1482 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1483
1484         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1485         (extractps): Add VexWIG to SSE2AVX forms.
1486         * i386-tbl.h: Re-generate.
1487
1488 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1489
1490         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1491         Size64 from and use VexW1 on SSE2AVX forms.
1492         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1493         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1494         * i386-tbl.h: Re-generate.
1495
1496 2020-01-15  Alan Modra  <amodra@gmail.com>
1497
1498         * tic4x-dis.c (tic4x_version): Make unsigned long.
1499         (optab, optab_special, registernames): New file scope vars.
1500         (tic4x_print_register): Set up registernames rather than
1501         malloc'd registertable.
1502         (tic4x_disassemble): Delete optable and optable_special.  Use
1503         optab and optab_special instead.  Throw away old optab,
1504         optab_special and registernames when info->mach changes.
1505
1506 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1507
1508         PR 25377
1509         * z80-dis.c (suffix): Use .db instruction to generate double
1510         prefix.
1511
1512 2020-01-14  Alan Modra  <amodra@gmail.com>
1513
1514         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1515         values to unsigned before shifting.
1516
1517 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1518
1519         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1520         flow instructions.
1521         (print_insn_thumb16, print_insn_thumb32): Likewise.
1522         (print_insn): Initialize the insn info.
1523         * i386-dis.c (print_insn): Initialize the insn info fields, and
1524         detect jumps.
1525
1526 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1527
1528         * arc-opc.c (C_NE): Make it required.
1529
1530 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1531
1532         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1533         reserved register name.
1534
1535 2020-01-13  Alan Modra  <amodra@gmail.com>
1536
1537         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1538         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1539
1540 2020-01-13  Alan Modra  <amodra@gmail.com>
1541
1542         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1543         result of wasm_read_leb128 in a uint64_t and check that bits
1544         are not lost when copying to other locals.  Use uint32_t for
1545         most locals.  Use PRId64 when printing int64_t.
1546
1547 2020-01-13  Alan Modra  <amodra@gmail.com>
1548
1549         * score-dis.c: Formatting.
1550         * score7-dis.c: Formatting.
1551
1552 2020-01-13  Alan Modra  <amodra@gmail.com>
1553
1554         * score-dis.c (print_insn_score48): Use unsigned variables for
1555         unsigned values.  Don't left shift negative values.
1556         (print_insn_score32): Likewise.
1557         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1558
1559 2020-01-13  Alan Modra  <amodra@gmail.com>
1560
1561         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1562
1563 2020-01-13  Alan Modra  <amodra@gmail.com>
1564
1565         * fr30-ibld.c: Regenerate.
1566
1567 2020-01-13  Alan Modra  <amodra@gmail.com>
1568
1569         * xgate-dis.c (print_insn): Don't left shift signed value.
1570         (ripBits): Formatting, use 1u.
1571
1572 2020-01-10  Alan Modra  <amodra@gmail.com>
1573
1574         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1575         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1576
1577 2020-01-10  Alan Modra  <amodra@gmail.com>
1578
1579         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1580         and XRREG value earlier to avoid a shift with negative exponent.
1581         * m10200-dis.c (disassemble): Similarly.
1582
1583 2020-01-09  Nick Clifton  <nickc@redhat.com>
1584
1585         PR 25224
1586         * z80-dis.c (ld_ii_ii): Use correct cast.
1587
1588 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1589
1590         PR 25224
1591         * z80-dis.c (ld_ii_ii): Use character constant when checking
1592         opcode byte value.
1593
1594 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1595
1596         * i386-dis.c (SEP_Fixup): New.
1597         (SEP): Define.
1598         (dis386_twobyte): Use it for sysenter/sysexit.
1599         (enum x86_64_isa): Change amd64 enumerator to value 1.
1600         (OP_J): Compare isa64 against intel64 instead of amd64.
1601         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1602         forms.
1603         * i386-tbl.h: Re-generate.
1604
1605 2020-01-08  Alan Modra  <amodra@gmail.com>
1606
1607         * z8k-dis.c: Include libiberty.h
1608         (instr_data_s): Make max_fetched unsigned.
1609         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1610         Don't exceed byte_info bounds.
1611         (output_instr): Make num_bytes unsigned.
1612         (unpack_instr): Likewise for nibl_count and loop.
1613         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1614         idx unsigned.
1615         * z8k-opc.h: Regenerate.
1616
1617 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1618
1619         * arc-tbl.h (llock): Use 'LLOCK' as class.
1620         (llockd): Likewise.
1621         (scond): Use 'SCOND' as class.
1622         (scondd): Likewise.
1623         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1624         (scondd): Likewise.
1625
1626 2020-01-06  Alan Modra  <amodra@gmail.com>
1627
1628         * m32c-ibld.c: Regenerate.
1629
1630 2020-01-06  Alan Modra  <amodra@gmail.com>
1631
1632         PR 25344
1633         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1634         Peek at next byte to prevent recursion on repeated prefix bytes.
1635         Ensure uninitialised "mybuf" is not accessed.
1636         (print_insn_z80): Don't zero n_fetch and n_used here,..
1637         (print_insn_z80_buf): ..do it here instead.
1638
1639 2020-01-04  Alan Modra  <amodra@gmail.com>
1640
1641         * m32r-ibld.c: Regenerate.
1642
1643 2020-01-04  Alan Modra  <amodra@gmail.com>
1644
1645         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1646
1647 2020-01-04  Alan Modra  <amodra@gmail.com>
1648
1649         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1650
1651 2020-01-04  Alan Modra  <amodra@gmail.com>
1652
1653         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1654
1655 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1656
1657         * aarch64-tbl.h (aarch64_opcode_table): Use
1658         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1659
1660 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1661
1662         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1663         forms of SUDOT and USDOT.
1664
1665 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1666
1667         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1668         uzip{1,2}.
1669         * opcodes/aarch64-dis-2.c: Re-generate.
1670
1671 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1672
1673         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1674         FMMLA encoding.
1675         * opcodes/aarch64-dis-2.c: Re-generate.
1676
1677 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1678
1679         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1680
1681 2020-01-01  Alan Modra  <amodra@gmail.com>
1682
1683         Update year range in copyright notice of all files.
1684
1685 For older changes see ChangeLog-2019
1686 \f
1687 Copyright (C) 2020 Free Software Foundation, Inc.
1688
1689 Copying and distribution of this file, with or without modification,
1690 are permitted in any medium without royalty provided the copyright
1691 notice and this notice are preserved.
1692
1693 Local Variables:
1694 mode: change-log
1695 left-margin: 8
1696 fill-column: 74
1697 version-control: never
1698 End: