opcodes/ChangeLog

   1 2019-12-17  Alan Modra  <amodra@gmail.com>
   2
   3         * bpf-ibld.c: Regenerate.
   4
   5 2019-12-16  Alan Modra  <amodra@gmail.com>
   6
   7         * aarch64-dis.c (sign_extend): Return uint64_t.  Rewrite without
   8         conditional.
   9         (aarch64_ext_imm): Avoid signed overflow.
  10
  11 2019-12-16  Alan Modra  <amodra@gmail.com>
  12
  13         * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
  14
  15 2019-12-16  Alan Modra  <amodra@gmail.com>
  16
  17         * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
  18
  19 2019-12-16  Alan Modra  <amodra@gmail.com>
  20
  21         * xstormy16-ibld.c: Regenerate.
  22
  23 2019-12-16  Alan Modra  <amodra@gmail.com>
  24
  25         * score-dis.c (print_insn_score16): Move rpush/rpop imm field
  26         value adjustment so that it doesn't affect reg field too.
  27
  28 2019-12-16  Alan Modra  <amodra@gmail.com>
  29
  30         * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
  31         (get_number_of_operands, getargtype, getbits, getregname),
  32         (getcopregname, getprocregname, gettrapstring, getcinvstring),
  33         (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
  34         (powerof2, match_opcode, make_instruction, print_arguments),
  35         (print_arg): Delete forward declarations, moving static to..
  36         (getregname, getcopregname, getregliststring): ..these definitions.
  37         (build_mask): Return unsigned int mask.
  38         (match_opcode): Use unsigned int vars.
  39
  40 2019-12-16  Alan Modra  <amodra@gmail.com>
  41
  42         * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
  43
  44 2019-12-16  Alan Modra  <amodra@gmail.com>
  45
  46         * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
  47         (struct objdump_disasm_info): Delete.
  48         (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
  49         N32_IMMS to unsigned before shifting left.
  50
  51 2019-12-16  Alan Modra  <amodra@gmail.com>
  52
  53         * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
  54         (print_insn_moxie): Remove unnecessary cast.
  55
  56 2019-12-12  Alan Modra  <amodra@gmail.com>
  57
  58         * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
  59         mask.
  60
  61 2019-12-11  Alan Modra  <amodra@gmail.com>
  62
  63         * arc-dis.c (BITS): Don't truncate high bits with shifts.
  64         * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
  65         * tic54x-dis.c (print_instruction): Likewise.
  66         * tilegx-opc.c (parse_insn_tilegx): Likewise.
  67         * tilepro-opc.c (parse_insn_tilepro): Likewise.
  68         * visium-dis.c (disassem_class0): Likewise.
  69         * pdp11-dis.c (sign_extend): Likewise.
  70         (SIGN_BITS): Delete.
  71         * epiphany-ibld.c: Regenerate.
  72         * lm32-ibld.c: Regenerate.
  73         * m32c-ibld.c: Regenerate.
  74
  75 2019-12-11  Alan Modra  <amodra@gmail.com>
  76
  77         * ns32k-dis.c (sign_extend): Correct last patch.
  78
  79 2019-12-11  Alan Modra  <amodra@gmail.com>
  80
  81         * vax-dis.c (NEXTLONG): Avoid signed overflow.
  82
  83 2019-12-11  Alan Modra  <amodra@gmail.com>
  84
  85         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
  86         sign extend using shifts.
  87
  88 2019-12-11  Alan Modra  <amodra@gmail.com>
  89
  90         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
  91
  92 2019-12-11  Alan Modra  <amodra@gmail.com>
  93
  94         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
  95         on NULL registertable entry.
  96         (tic4x_hash_opcode): Use unsigned arithmetic.
  97
  98 2019-12-11  Alan Modra  <amodra@gmail.com>
  99
 100         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
 101
 102 2019-12-11  Alan Modra  <amodra@gmail.com>
 103
 104         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
 105         (bit_extract_simple, sign_extend): Likewise.
 106
 107 2019-12-11  Alan Modra  <amodra@gmail.com>
 108
 109         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
 110
 111 2019-12-11  Alan Modra  <amodra@gmail.com>
 112
 113         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
 114
 115 2019-12-11  Alan Modra  <amodra@gmail.com>
 116
 117         * m68k-dis.c (COERCE32): Cast value first.
 118         (NEXTLONG, NEXTULONG): Avoid signed overflow.
 119
 120 2019-12-11  Alan Modra  <amodra@gmail.com>
 121
 122         * h8300-dis.c (extract_immediate): Avoid signed overflow.
 123         (bfd_h8_disassemble): Likewise.
 124
 125 2019-12-11  Alan Modra  <amodra@gmail.com>
 126
 127         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
 128         past end of operands array.
 129
 130 2019-12-11  Alan Modra  <amodra@gmail.com>
 131
 132         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
 133         overflow when collecting bytes of a number.
 134
 135 2019-12-11  Alan Modra  <amodra@gmail.com>
 136
 137         * cris-dis.c (print_with_operands): Avoid signed integer
 138         overflow when collecting bytes of a 32-bit integer.
 139
 140 2019-12-11  Alan Modra  <amodra@gmail.com>
 141
 142         * cr16-dis.c (EXTRACT, SBM): Rewrite.
 143         (cr16_match_opcode): Delete duplicate bcond test.
 144
 145 2019-12-11  Alan Modra  <amodra@gmail.com>
 146
 147         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
 148         (SIGNBIT): New.
 149         (MASKBITS, SIGNEXTEND): Rewrite.
 150         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
 151         unsigned arithmetic, instead assign result of SIGNEXTEND back
 152         to x.
 153         (fmtconst_val): Use 1u in shift expression.
 154
 155 2019-12-11  Alan Modra  <amodra@gmail.com>
 156
 157         * arc-dis.c (find_format_from_table): Use ull constant when
 158         shifting by up to 32.
 159
 160 2019-12-11  Alan Modra  <amodra@gmail.com>
 161
 162         PR 25270
 163         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
 164         false when field is zero for sve_size_tsz_bhs.
 165
 166 2019-12-11  Alan Modra  <amodra@gmail.com>
 167
 168         * epiphany-ibld.c: Regenerate.
 169
 170 2019-12-10  Alan Modra  <amodra@gmail.com>
 171
 172         PR 24960
 173         * disassemble.c (disassemble_free_target): New function.
 174
 175 2019-12-10  Alan Modra  <amodra@gmail.com>
 176
 177         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 178         * disassemble.c (disassemble_init_for_target): Likewise.
 179         * bpf-dis.c: Regenerate.
 180         * epiphany-dis.c: Regenerate.
 181         * fr30-dis.c: Regenerate.
 182         * frv-dis.c: Regenerate.
 183         * ip2k-dis.c: Regenerate.
 184         * iq2000-dis.c: Regenerate.
 185         * lm32-dis.c: Regenerate.
 186         * m32c-dis.c: Regenerate.
 187         * m32r-dis.c: Regenerate.
 188         * mep-dis.c: Regenerate.
 189         * mt-dis.c: Regenerate.
 190         * or1k-dis.c: Regenerate.
 191         * xc16x-dis.c: Regenerate.
 192         * xstormy16-dis.c: Regenerate.
 193
 194 2019-12-10  Alan Modra  <amodra@gmail.com>
 195
 196         * ppc-dis.c (private): Delete variable.
 197         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 198         (powerpc_init_dialect): Don't use global private.
 199
 200 2019-12-10  Alan Modra  <amodra@gmail.com>
 201
 202         * s12z-opc.c: Formatting.
 203
 204 2019-12-08  Alan Modra  <amodra@gmail.com>
 205
 206         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 207         registers.
 208
 209 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 210
 211         * aarch64-tbl.h (aarch64_feature_crypto,
 212         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 213         CRYPTO_V8_2_INSN): Delete.
 214
 215 2019-12-05  Alan Modra  <amodra@gmail.com>
 216
 217         PR 25249
 218         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 219         (struct string_buf): New.
 220         (strbuf): New function.
 221         (get_field): Use strbuf rather than strdup of local temp.
 222         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 223         (get_field_rfsl, get_field_imm15): Likewise.
 224         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 225         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 226         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 227         get_field functions.
 228
 229 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 230
 231         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 232         * i386-tbl.h: Re-generate.
 233
 234 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 235
 236         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 237
 238 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 239
 240         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 241         forms.
 242         (xbegin): Drop DefaultSize.
 243         * i386-tbl.h: Re-generate.
 244
 245 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 246
 247         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 248         Change the coproc CRC conditions to use the extension
 249         feature set, second word, base on ARM_EXT2_CRC.
 250
 251 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 254         * i386-tbl.h: Re-generate.
 255
 256 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 259         JumpInterSegment, and JumpAbsolute entries.
 260         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 261         JUMP_ABSOLUTE): Define.
 262         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 263         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 264         fields.
 265         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 266         JumpInterSegment): Define.
 267         * i386-tbl.h: Re-generate.
 268
 269 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 270
 271         * i386-gen.c (operand_type_init): Remove
 272         OPERAND_TYPE_JUMPABSOLUTE entry.
 273         (opcode_modifiers): Add JumpAbsolute entry.
 274         (operand_types): Remove JumpAbsolute entry.
 275         * i386-opc.h (JumpAbsolute): Move between enums.
 276         (struct i386_opcode_modifier): Add jumpabsolute field.
 277         (union i386_operand_type): Remove jumpabsolute field.
 278         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 279         * i386-init.h, i386-tbl.h: Re-generate.
 280
 281 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 282
 283         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 284         (operand_types): Remove AnySize entry.
 285         * i386-opc.h (AnySize): Move between enums.
 286         (struct i386_opcode_modifier): Add anysize field.
 287         (OTUnused): Un-comment.
 288         (union i386_operand_type): Remove anysize field.
 289         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 290         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 291         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 292         AnySize.
 293         * i386-tbl.h: Re-generate.
 294
 295 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 296
 297         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 298         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 299         use the floating point register (FPR).
 300
 301 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 302
 303         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 304         cmode 1101.
 305         (is_mve_encoding_conflict): Update cmode conflict checks for
 306         MVE_VMVN_IMM.
 307
 308 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 309
 310         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 311         entry.
 312         (operand_types): Remove EsSeg entry.
 313         (main): Replace stale use of OTMax.
 314         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 315         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 316         (EsSeg): Delete.
 317         (OTUnused): Comment out.
 318         (union i386_operand_type): Remove esseg field.
 319         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 320         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 321         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 322         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 323         * i386-init.h, i386-tbl.h: Re-generate.
 324
 325 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 326
 327         * i386-gen.c (operand_instances): Add RegB entry.
 328         * i386-opc.h (enum operand_instance): Add RegB.
 329         * i386-opc.tbl (RegC, RegD, RegB): Define.
 330         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 331         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 332         monitorx, mwaitx): Drop ImmExt and convert encodings
 333         accordingly.
 334         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 335         (edx, rdx): Add Instance=RegD.
 336         (ebx, rbx): Add Instance=RegB.
 337         * i386-tbl.h: Re-generate.
 338
 339 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 340
 341         * i386-gen.c (operand_type_init): Adjust
 342         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 343         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 344         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 345         (operand_instances): New.
 346         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 347         (output_operand_type): New parameter "instance". Process it.
 348         (process_i386_operand_type): New local variable "instance".
 349         (main): Adjust static assertions.
 350         * i386-opc.h (INSTANCE_WIDTH): Define.
 351         (enum operand_instance): New.
 352         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 353         (union i386_operand_type): Replace acc, inoutportreg, and
 354         shiftcount by instance.
 355         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 356         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 357         Add Instance=.
 358         * i386-init.h, i386-tbl.h: Re-generate.
 359
 360 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 361
 362         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 363         smaxp/sminp entries' "tied_operand" field to 2.
 364
 365 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 366
 367         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 368         "index" local variable by that of the already existing "num".
 369
 370 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 371
 372         PR gas/25167
 373         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 374         * i386-tbl.h: Regenerated.
 375
 376 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 377
 378         * i386-gen.c (operand_type_init): Add Class= to
 379         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 380         OPERAND_TYPE_REGBND entry.
 381         (operand_classes): Add RegMask and RegBND entries.
 382         (operand_types): Drop RegMask and RegBND entry.
 383         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 384         (RegMask, RegBND): Delete.
 385         (union i386_operand_type): Remove regmask and regbnd fields.
 386         * i386-opc.tbl (RegMask, RegBND): Define.
 387         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 388         Class=RegBND.
 389         * i386-init.h, i386-tbl.h: Re-generate.
 390
 391 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 392
 393         * i386-gen.c (operand_type_init): Add Class= to
 394         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 395         OPERAND_TYPE_REGZMM entries.
 396         (operand_classes): Add RegMMX and RegSIMD entries.
 397         (operand_types): Drop RegMMX and RegSIMD entries.
 398         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 399         (RegMMX, RegSIMD): Delete.
 400         (union i386_operand_type): Remove regmmx and regsimd fields.
 401         * i386-opc.tbl (RegMMX): Define.
 402         (RegXMM, RegYMM, RegZMM): Add Class=.
 403         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 404         Class=RegSIMD.
 405         * i386-init.h, i386-tbl.h: Re-generate.
 406
 407 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 408
 409         * i386-gen.c (operand_type_init): Add Class= to
 410         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 411         entries.
 412         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 413         (operand_types): Drop Control, Debug, and Test entries.
 414         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 415         (Control, Debug, Test): Delete.
 416         (union i386_operand_type): Remove control, debug, and test
 417         fields.
 418         * i386-opc.tbl (Control, Debug, Test): Define.
 419         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 420         Class=RegDR, and Test by Class=RegTR.
 421         * i386-init.h, i386-tbl.h: Re-generate.
 422
 423 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 424
 425         * i386-gen.c (operand_type_init): Add Class= to
 426         OPERAND_TYPE_SREG entry.
 427         (operand_classes): Add SReg entry.
 428         (operand_types): Drop SReg entry.
 429         * i386-opc.h (enum operand_class): Add SReg.
 430         (SReg): Delete.
 431         (union i386_operand_type): Remove sreg field.
 432         * i386-opc.tbl (SReg): Define.
 433         * i386-reg.tbl: Replace SReg by Class=SReg.
 434         * i386-init.h, i386-tbl.h: Re-generate.
 435
 436 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 437
 438         * i386-gen.c (operand_type_init): Add Class=. New
 439         OPERAND_TYPE_ANYIMM entry.
 440         (operand_classes): New.
 441         (operand_types): Drop Reg entry.
 442         (output_operand_type): New parameter "class". Process it.
 443         (process_i386_operand_type): New local variable "class".
 444         (main): Adjust static assertions.
 445         * i386-opc.h (CLASS_WIDTH): Define.
 446         (enum operand_class): New.
 447         (Reg): Replace by Class. Adjust comment.
 448         (union i386_operand_type): Replace reg by class.
 449         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 450         Class=.
 451         * i386-reg.tbl: Replace Reg by Class=Reg.
 452         * i386-init.h: Re-generate.
 453
 454 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 455
 456         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 457         (aarch64_opcode_table): Add data gathering hint mnemonic.
 458         * opcodes/aarch64-dis-2.c: Account for new instruction.
 459
 460 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 461
 462         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 463
 464
 465 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 466
 467         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 468         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 469         aarch64_feature_f64mm): New feature sets.
 470         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 471         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 472         instructions.
 473         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 474         macros.
 475         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 476         (OP_SVE_QQQ): New qualifier.
 477         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 478         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 479         the movprfx constraint.
 480         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 481         (aarch64_opcode_table): Define new instructions smmla,
 482         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 483         uzip{1/2}, trn{1/2}.
 484         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 485         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 486         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 487         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 488         Account for new instructions.
 489         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 490         S4x32 operand.
 491         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 492
 493 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 494 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 495
 496         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 497         Armv8.6-A.
 498         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 499         (neon_opcodes): Add bfloat SIMD instructions.
 500         (print_insn_coprocessor): Add new control character %b to print
 501         condition code without checking cp_num.
 502         (print_insn_neon): Account for BFloat16 instructions that have no
 503         special top-byte handling.
 504
 505 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 506 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 507
 508         * arm-dis.c (print_insn_coprocessor,
 509         print_insn_generic_coprocessor): Create wrapper functions around
 510         the implementation of the print_insn_coprocessor control codes.
 511         (print_insn_coprocessor_1): Original print_insn_coprocessor
 512         function that now takes which array to look at as an argument.
 513         (print_insn_arm): Use both print_insn_coprocessor and
 514         print_insn_generic_coprocessor.
 515         (print_insn_thumb32): As above.
 516
 517 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 518 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 519
 520         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 521         in reglane special case.
 522         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 523         aarch64_find_next_opcode): Account for new instructions.
 524         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 525         in reglane special case.
 526         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 527         new AARCH64_OPND_QLF_S_2H qualifier.
 528         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 529         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 530         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 531         sets.
 532         (BFLOAT_SVE, BFLOAT): New feature set macros.
 533         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 534         instructions.
 535         (aarch64_opcode_table): Define new instructions bfdot,
 536         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 537         bfcvtn2, bfcvt.
 538
 539 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 540 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 541
 542         * aarch64-tbl.h (ARMV8_6): New macro.
 543
 544 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 545
 546         * i386-dis.c (prefix_table): Add mcommit.
 547         (rm_table): Add rdpru.
 548         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 549         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 550         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 551         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 552         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 553         * i386-opc.tbl (mcommit, rdpru): New.
 554         * i386-init.h, i386-tbl.h: Re-generate.
 555
 556 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 557
 558         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 559         "names32" instead.
 560         (OP_Monitor): Drop local variable "op1_names", re-purpose
 561         "names" for it instead, and replace former "names" uses by
 562         "names32" ones.
 563
 564 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 565
 566         PR/gas 25167
 567         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 568         operand-less forms.
 569         * opcodes/i386-tbl.h: Re-generate.
 570
 571 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 572
 573         * i386-dis.c (OP_Mwaitx): Delete.
 574         (prefix_table): Use OP_Mwait for mwaitx entry.
 575         (OP_Mwait): Also handle mwaitx.
 576
 577 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 578
 579         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 580         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 581         (prefix_table): Add respective entries.
 582         (rm_table): Link to those entries.
 583
 584 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 585
 586         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 587         (REG_0F1C_P_0_MOD_0): ... this.
 588         (REG_0F1E_MOD_3): Rename to ...
 589         (REG_0F1E_P_1_MOD_3): ... this.
 590         (RM_0F01_REG_5): Rename to ...
 591         (RM_0F01_REG_5_MOD_3): ... this.
 592         (RM_0F01_REG_7): Rename to ...
 593         (RM_0F01_REG_7_MOD_3): ... this.
 594         (RM_0F1E_MOD_3_REG_7): Rename to ...
 595         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 596         (RM_0FAE_REG_6): Rename to ...
 597         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 598         (RM_0FAE_REG_7): Rename to ...
 599         (RM_0FAE_REG_7_MOD_3): ... this.
 600         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 601         (PREFIX_0F01_REG_5_MOD_0): ... this.
 602         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 603         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 604         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 605         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 606         (PREFIX_0FAE_REG_0): Rename to ...
 607         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 608         (PREFIX_0FAE_REG_1): Rename to ...
 609         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 610         (PREFIX_0FAE_REG_2): Rename to ...
 611         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 612         (PREFIX_0FAE_REG_3): Rename to ...
 613         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 614         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 615         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 616         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 617         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 618         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 619         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 620         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 621         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 622         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 623         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 624         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 625         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 626         (PREFIX_0FAE_REG_7): Rename to ...
 627         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 628         (PREFIX_MOD_0_0FC3): Rename to ...
 629         (PREFIX_0FC3_MOD_0): ... this.
 630         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 631         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 632         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 633         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 634         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 635         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 636         (reg_table, prefix_table, mod_table, rm_table): Adjust
 637         accordingly.
 638
 639 2019-11-04  Nick Clifton  <nickc@redhat.com>
 640
 641         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 642         of a v850 system register.  Move the v850_sreg_names array into
 643         this function.
 644         (get_v850_reg_name): Likewise for ordinary register names.
 645         (get_v850_vreg_name): Likewise for vector register names.
 646         (get_v850_cc_name): Likewise for condition codes.
 647         * get_v850_float_cc_name): Likewise for floating point condition
 648         codes.
 649         (get_v850_cacheop_name): Likewise for cache-ops.
 650         (get_v850_prefop_name): Likewise for pref-ops.
 651         (disassemble): Use the new accessor functions.
 652
 653 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 654
 655         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 656         immediate for the writeback form of ldraa/ldrab if it is 0.
 657         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 658         * aarch64-opc-2.c: Regenerated.
 659
 660 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 661
 662         * i386-gen.c (operand_type_shorthands): Delete.
 663         (operand_type_init): Expand previous shorthands.
 664         (set_bitfield_from_shorthand): Rename back to ...
 665         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 666         of operand_type_init[].
 667         (set_bitfield): Adjust call to the above function.
 668         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 669         RegXMM, RegYMM, RegZMM): Define.
 670         * i386-reg.tbl: Expand prior shorthands.
 671
 672 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 673
 674         * i386-gen.c (output_i386_opcode): Change order of fields
 675         emitted to output.
 676         * i386-opc.h (struct insn_template): Move operands field.
 677         Convert extension_opcode field to unsigned short.
 678         * i386-tbl.h: Re-generate.
 679
 680 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 681
 682         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 683         of W.
 684         * i386-opc.h (W): Extend comment.
 685         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 686         general purpose variants not allowing for byte operands.
 687         * i386-tbl.h: Re-generate.
 688
 689 2019-10-29  Nick Clifton  <nickc@redhat.com>
 690
 691         * tic30-dis.c (print_branch): Correct size of operand array.
 692
 693 2019-10-29  Nick Clifton  <nickc@redhat.com>
 694
 695         * d30v-dis.c (print_insn): Check that operand index is valid
 696         before attempting to access the operands array.
 697
 698 2019-10-29  Nick Clifton  <nickc@redhat.com>
 699
 700         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 701         locating the bit to be tested.
 702
 703 2019-10-29  Nick Clifton  <nickc@redhat.com>
 704
 705         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 706         values.
 707         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 708         (print_insn_s12z):  Check for illegal size values.
 709
 710 2019-10-28  Nick Clifton  <nickc@redhat.com>
 711
 712         * csky-dis.c (csky_chars_to_number): Check for a negative
 713         count. Use an unsigned integer to construct the return value.
 714
 715 2019-10-28  Nick Clifton  <nickc@redhat.com>
 716
 717         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 718         operand buffer.  Set value to 15 not 13.
 719         (get_register_operand): Use OPERAND_BUFFER_LEN.
 720         (get_indirect_operand): Likewise.
 721         (print_two_operand): Likewise.
 722         (print_three_operand): Likewise.
 723         (print_oar_insn): Likewise.
 724
 725 2019-10-28  Nick Clifton  <nickc@redhat.com>
 726
 727         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 728         (bit_extract_simple): Likewise.
 729         (bit_copy): Likewise.
 730         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 731         index_offset array are not accessed.
 732
 733 2019-10-28  Nick Clifton  <nickc@redhat.com>
 734
 735         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 736         operand.
 737
 738 2019-10-25  Nick Clifton  <nickc@redhat.com>
 739
 740         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 741         access to opcodes.op array element.
 742
 743 2019-10-23  Nick Clifton  <nickc@redhat.com>
 744
 745         * rx-dis.c (get_register_name): Fix spelling typo in error
 746         message.
 747         (get_condition_name, get_flag_name, get_double_register_name)
 748         (get_double_register_high_name, get_double_register_low_name)
 749         (get_double_control_register_name, get_double_condition_name)
 750         (get_opsize_name, get_size_name): Likewise.
 751
 752 2019-10-22  Nick Clifton  <nickc@redhat.com>
 753
 754         * rx-dis.c (get_size_name): New function.  Provides safe
 755         access to name array.
 756         (get_opsize_name): Likewise.
 757         (print_insn_rx): Use the accessor functions.
 758
 759 2019-10-16  Nick Clifton  <nickc@redhat.com>
 760
 761         * rx-dis.c (get_register_name): New function.  Provides safe
 762         access to name array.
 763         (get_condition_name, get_flag_name, get_double_register_name)
 764         (get_double_register_high_name, get_double_register_low_name)
 765         (get_double_control_register_name, get_double_condition_name):
 766         Likewise.
 767         (print_insn_rx): Use the accessor functions.
 768
 769 2019-10-09  Nick Clifton  <nickc@redhat.com>
 770
 771         PR 25041
 772         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 773         instructions.
 774
 775 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 776
 777         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 778         (cmpsd): Likewise. Move EsSeg to other operand.
 779         * opcodes/i386-tbl.h: Re-generate.
 780
 781 2019-09-23  Alan Modra  <amodra@gmail.com>
 782
 783         * m68k-dis.c: Include cpu-m68k.h
 784
 785 2019-09-23  Alan Modra  <amodra@gmail.com>
 786
 787         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 788         "elf/mips.h" earlier.
 789
 790 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 791
 792         PR gas/25012
 793         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 794         with SReg operand.
 795         * i386-tbl.h: Re-generate.
 796
 797 2019-09-18  Alan Modra  <amodra@gmail.com>
 798
 799         * arc-ext.c: Update throughout for bfd section macro changes.
 800
 801 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 802
 803         * Makefile.in: Re-generate.
 804         * configure: Re-generate.
 805
 806 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 807
 808         * riscv-opc.c (riscv_opcodes): Change subset field
 809         to insn_class field for all instructions.
 810         (riscv_insn_types): Likewise.
 811
 812 2019-09-16  Phil Blundell  <pb@pbcl.net>
 813
 814         * configure: Regenerated.
 815
 816 2019-09-10  Miod Vallat  <miod@online.fr>
 817
 818         PR 24982
 819         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 820
 821 2019-09-09  Phil Blundell  <pb@pbcl.net>
 822
 823         binutils 2.33 branch created.
 824
 825 2019-09-03  Nick Clifton  <nickc@redhat.com>
 826
 827         PR 24961
 828         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 829         greater than zero before indexing via (bufcnt -1).
 830
 831 2019-09-03  Nick Clifton  <nickc@redhat.com>
 832
 833         PR 24958
 834         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 835         (MAX_SPEC_REG_NAME_LEN): Define.
 836         (struct mmix_dis_info): Use defined constants for array lengths.
 837         (get_reg_name): New function.
 838         (get_sprec_reg_name): New function.
 839         (print_insn_mmix): Use new functions.
 840
 841 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 842
 843         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 844         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 845         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 846
 847 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 848
 849         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 850         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 851         (aarch64_sys_reg_supported_p): Update checks for the above.
 852
 853 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 854
 855         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 856         cases MVE_SQRSHRL and MVE_UQRSHLL.
 857         (print_insn_mve): Add case for specifier 'k' to check
 858         specific bit of the instruction.
 859
 860 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 861
 862         PR 24854
 863         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 864         encountering an unknown machine type.
 865         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 866         cases return -1 rather than calling abort.
 867
 868 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 869
 870         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 871         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 872         IgnoreSize.
 873         * i386-tbl.h: Re-generate.
 874
 875 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 876
 877         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 878         instructions.
 879
 880 2019-07-30  Mel Chen <mel.chen@sifive.com>
 881
 882         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 883         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 884
 885         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 886         fscsr.
 887
 888 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 889
 890         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 891         and MPY class instructions.
 892         (parse_option): Add nps400 option.
 893         (print_arc_disassembler_options): Add nps400 info.
 894
 895 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 896
 897         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 898         (bspop): Likewise.
 899         (modapp): Likewise.
 900         * arc-opc.c (RAD_CHK): Add.
 901         * arc-tbl.h: Regenerate.
 902
 903 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 904
 905         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 906         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 907
 908 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 909
 910         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 911         instructions as UNPREDICTABLE.
 912
 913 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 914
 915         * bpf-desc.c: Regenerated.
 916
 917 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 918
 919         * i386-gen.c (static_assert): Define.
 920         (main): Use it.
 921         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 922         (Opcode_Modifier_Num): ... this.
 923         (Mem): Delete.
 924
 925 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 926
 927         * i386-gen.c (operand_types): Move RegMem ...
 928         (opcode_modifiers): ... here.
 929         * i386-opc.h (RegMem): Move to opcode modifer enum.
 930         (union i386_operand_type): Move regmem field ...
 931         (struct i386_opcode_modifier): ... here.
 932         * i386-opc.tbl (RegMem): Define.
 933         (mov, movq): Move RegMem on segment, control, debug, and test
 934         register flavors.
 935         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 936         to non-SSE2AVX flavor.
 937         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 938         Move RegMem on register only flavors. Drop IgnoreSize from
 939         legacy encoding flavors.
 940         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 941         flavors.
 942         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 943         register only flavors.
 944         (vmovd): Move RegMem and drop IgnoreSize on register only
 945         flavor. Change opcode and operand order to store form.
 946         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 947
 948 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 949
 950         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 951         entries.
 952         * i386-opc.h (SReg2, SReg3): Replace by ...
 953         (SReg): ... this.
 954         (union i386_operand_type): Replace sreg fields.
 955         * i386-opc.tbl (mov, ): Use SReg.
 956         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 957         register flavors.
 958         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 959         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 960
 961 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 962
 963         * bpf-desc.c: Regenerate.
 964         * bpf-opc.c: Likewise.
 965         * bpf-opc.h: Likewise.
 966
 967 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 968
 969         * bpf-desc.c: Regenerate.
 970         * bpf-opc.c: Likewise.
 971
 972 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 973
 974         * arm-dis.c (print_insn_coprocessor): Rename index to
 975         index_operand.
 976
 977 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 978
 979         * riscv-opc.c (riscv_insn_types): Add r4 type.
 980
 981         * riscv-opc.c (riscv_insn_types): Add b and j type.
 982
 983         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 984         format for sb type and correct s type.
 985
 986 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 987
 988         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 989         SVE FMOV alias of FCPY.
 990
 991 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 992
 993         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 994         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 995
 996 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 997
 998         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 999         registers in an instruction prefixed by MOVPRFX.
1000
1001 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
1002
1003         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1004         sve_size_13 icode to account for variant behaviour of
1005         pmull{t,b}.
1006         * aarch64-dis-2.c: Regenerate.
1007         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1008         sve_size_13 icode to account for variant behaviour of
1009         pmull{t,b}.
1010         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1011         (OP_SVE_VVV_Q_D): Add new qualifier.
1012         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1013         (struct aarch64_opcode): Split pmull{t,b} into those requiring
1014         AES and those not.
1015
1016 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1017
1018         * opcodes/i386-gen.c (operand_type_init): Remove
1019         OPERAND_TYPE_VEC_IMM4 entry.
1020         (operand_types): Remove Vec_Imm4.
1021         * opcodes/i386-opc.h (Vec_Imm4): Delete.
1022         (union i386_operand_type): Remove vec_imm4.
1023         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1024         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1025
1026 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1027
1028         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1029         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1030         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1031         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1032         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1033         monitorx, mwaitx): Drop ImmExt from operand-less forms.
1034         * i386-tbl.h: Re-generate.
1035
1036 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1037
1038         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1039         register operands.
1040         * i386-tbl.h: Re-generate.
1041
1042 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1043
1044         * i386-opc.tbl (C): New.
1045         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1046         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1047         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1048         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1049         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1050         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1051         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1052         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1053         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1054         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1055         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1056         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1057         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1058         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1059         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1060         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1061         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1062         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1063         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1064         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1065         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1066         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1067         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1068         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1069         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1070         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1071         flavors.
1072         * i386-tbl.h: Re-generate.
1073
1074 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1075
1076         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1077         register operands.
1078         * i386-tbl.h: Re-generate.
1079
1080 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1081
1082         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1083         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1084         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1085         * i386-tbl.h: Re-generate.
1086
1087 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1088
1089         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1090         Disp8MemShift from register only templates.
1091         * i386-tbl.h: Re-generate.
1092
1093 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1094
1095         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1096         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1097         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1098         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1099         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1100         EVEX_W_0F11_P_3_M_1): Delete.
1101         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1102         EVEX_W_0F11_P_3): New.
1103         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1104         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1105         MOD_EVEX_0F11_PREFIX_3 table entries.
1106         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1107         PREFIX_EVEX_0F11 table entries.
1108         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1109         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1110         EVEX_W_0F11_P_3_M_{0,1} table entries.
1111
1112 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1113
1114         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1115         Delete.
1116
1117 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1118
1119         PR binutils/24719
1120         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1121         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1122         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1123         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1124         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1125         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1126         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1127         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1128         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1129         PREFIX_EVEX_0F38C6_REG_6 entries.
1130         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1131         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1132         EVEX_W_0F38C7_R_6_P_2 entries.
1133         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1134         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1135         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1136         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1137         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1138         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1139         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1140
1141 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1142
1143         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1144         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1145         VEX_LEN_0F2D_P_3): Delete.
1146         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1147         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1148         (prefix_table): ... here.
1149
1150 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1151
1152         * i386-dis.c (Iq): Delete.
1153         (Id): New.
1154         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1155         TBM insns.
1156         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1157         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1158         (OP_E_memory): Also honor needindex when deciding whether an
1159         address size prefix needs printing.
1160         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1161
1162 2019-06-26  Jim Wilson  <jimw@sifive.com>
1163
1164         PR binutils/24739
1165         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1166         Set info->display_endian to info->endian_code.
1167
1168 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1169
1170         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1171         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1172         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1173         OPERAND_TYPE_ACC64 entries.
1174         * i386-init.h: Re-generate.
1175
1176 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1177
1178         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1179         Delete.
1180         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1181         of dqa_mode.
1182         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1183         entries here.
1184         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1185         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1186
1187 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1188
1189         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1190         variables.
1191
1192 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1193
1194         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1195         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1196         movnti.
1197         * i386-opc.tbl (movnti): Add IgnoreSize.
1198         * i386-tbl.h: Re-generate.
1199
1200 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1201
1202         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1203         * i386-tbl.h: Re-generate.
1204
1205 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1206
1207         * i386-dis-evex.h: Break into ...
1208         * i386-dis-evex-len.h: New file.
1209         * i386-dis-evex-mod.h: Likewise.
1210         * i386-dis-evex-prefix.h: Likewise.
1211         * i386-dis-evex-reg.h: Likewise.
1212         * i386-dis-evex-w.h: Likewise.
1213         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1214         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1215         i386-dis-evex-mod.h.
1216
1217 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1218
1219         PR binutils/24700
1220         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1221         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1222         EVEX_W_0F385B_P_2.
1223         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1224         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1225         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1226         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1227         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1228         EVEX_LEN_0F385B_P_2_W_1.
1229         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1230         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1231         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1232         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1233         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1234         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1235         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1236         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1237         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1238         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1239
1240 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1241
1242         PR binutils/24691
1243         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1244         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1245         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1246         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1247         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1248         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1249         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1250         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1251         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1252         EVEX_LEN_0F3A43_P_2_W_1.
1253         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1254         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1255         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1256         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1257         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1258         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1259         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1260         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1261         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1262         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1263         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1264         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1265
1266 2019-06-14  Nick Clifton  <nickc@redhat.com>
1267
1268         * po/fr.po; Updated French translation.
1269
1270 2019-06-13  Stafford Horne  <shorne@gmail.com>
1271
1272         * or1k-asm.c: Regenerated.
1273         * or1k-desc.c: Regenerated.
1274         * or1k-desc.h: Regenerated.
1275         * or1k-dis.c: Regenerated.
1276         * or1k-ibld.c: Regenerated.
1277         * or1k-opc.c: Regenerated.
1278         * or1k-opc.h: Regenerated.
1279         * or1k-opinst.c: Regenerated.
1280
1281 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1282
1283         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1284
1285 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1286
1287         PR binutils/24633
1288         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1289         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1290         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1291         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1292         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1293         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1294         EVEX_LEN_0F3A1B_P_2_W_1.
1295         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1296         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1297         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1298         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1299         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1300         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1301         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1302         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1303
1304 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1305
1306         PR binutils/24626
1307         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1308         EVEX.vvvv when disassembling VEX and EVEX instructions.
1309         (OP_VEX): Set vex.register_specifier to 0 after readding
1310         vex.register_specifier.
1311         (OP_Vex_2src_1): Likewise.
1312         (OP_Vex_2src_2): Likewise.
1313         (OP_LWP_E): Likewise.
1314         (OP_EX_Vex): Don't check vex.register_specifier.
1315         (OP_XMM_Vex): Likewise.
1316
1317 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1318             Lili Cui  <lili.cui@intel.com>
1319
1320         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1321         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1322         instructions.
1323         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1324         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1325         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1326         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1327         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1328         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1329         * i386-init.h: Regenerated.
1330         * i386-tbl.h: Likewise.
1331
1332 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1333             Lili Cui  <lili.cui@intel.com>
1334
1335         * doc/c-i386.texi: Document enqcmd.
1336         * testsuite/gas/i386/enqcmd-intel.d: New file.
1337         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1338         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1339         * testsuite/gas/i386/enqcmd.d: Likewise.
1340         * testsuite/gas/i386/enqcmd.s: Likewise.
1341         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1342         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1343         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1344         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1345         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1346         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1347         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1348         and x86-64-enqcmd.
1349
1350 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1351
1352         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1353
1354 2019-06-03  Alan Modra  <amodra@gmail.com>
1355
1356         * ppc-dis.c (prefix_opcd_indices): Correct size.
1357
1358 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1359
1360         PR gas/24625
1361         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1362         Disp8ShiftVL.
1363         * i386-tbl.h: Regenerated.
1364
1365 2019-05-24  Alan Modra  <amodra@gmail.com>
1366
1367         * po/POTFILES.in: Regenerate.
1368
1369 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1370             Alan Modra  <amodra@gmail.com>
1371
1372         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1373         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1374         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1375         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1376         XTOP>): Define and add entries.
1377         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1378         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1379         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1380         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1381
1382 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1383             Alan Modra  <amodra@gmail.com>
1384
1385         * ppc-dis.c (ppc_opts): Add "future" entry.
1386         (PREFIX_OPCD_SEGS): Define.
1387         (prefix_opcd_indices): New array.
1388         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1389         (lookup_prefix): New function.
1390         (print_insn_powerpc): Handle 64-bit prefix instructions.
1391         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1392         (PMRR, POWERXX): Define.
1393         (prefix_opcodes): New instruction table.
1394         (prefix_num_opcodes): New constant.
1395
1396 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1397
1398         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1399         * configure: Regenerated.
1400         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1401         and cpu/bpf.opc.
1402         (HFILES): Add bpf-desc.h and bpf-opc.h.
1403         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1404         bpf-ibld.c and bpf-opc.c.
1405         (BPF_DEPS): Define.
1406         * Makefile.in: Regenerated.
1407         * disassemble.c (ARCH_bpf): Define.
1408         (disassembler): Add case for bfd_arch_bpf.
1409         (disassemble_init_for_target): Likewise.
1410         (enum epbf_isa_attr): Define.
1411         * disassemble.h: extern print_insn_bpf.
1412         * bpf-asm.c: Generated.
1413         * bpf-opc.h: Likewise.
1414         * bpf-opc.c: Likewise.
1415         * bpf-ibld.c: Likewise.
1416         * bpf-dis.c: Likewise.
1417         * bpf-desc.h: Likewise.
1418         * bpf-desc.c: Likewise.
1419
1420 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1421
1422         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1423         and VMSR with the new operands.
1424
1425 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1426
1427         * arm-dis.c (enum mve_instructions): New enum
1428         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1429         and cneg.
1430         (mve_opcodes): New instructions as above.
1431         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1432         csneg and csel.
1433         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1434
1435 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1436
1437         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1438         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1439         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1440         uqshl, urshrl and urshr.
1441         (is_mve_okay_in_it): Add new instructions to TRUE list.
1442         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1443         (print_insn_mve): Updated to accept new %j,
1444         %<bitfield>m and %<bitfield>n patterns.
1445
1446 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1447
1448         * mips-opc.c (mips_builtin_opcodes): Change source register
1449         constraint for DAUI.
1450
1451 2019-05-20  Nick Clifton  <nickc@redhat.com>
1452
1453         * po/fr.po: Updated French translation.
1454
1455 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1456             Michael Collison <michael.collison@arm.com>
1457
1458         * arm-dis.c (thumb32_opcodes): Add new instructions.
1459         (enum mve_instructions): Likewise.
1460         (enum mve_undefined): Add new reasons.
1461         (is_mve_encoding_conflict): Handle new instructions.
1462         (is_mve_undefined): Likewise.
1463         (is_mve_unpredictable): Likewise.
1464         (print_mve_undefined): Likewise.
1465         (print_mve_size): Likewise.
1466
1467 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1468             Michael Collison <michael.collison@arm.com>
1469
1470         * arm-dis.c (thumb32_opcodes): Add new instructions.
1471         (enum mve_instructions): Likewise.
1472         (is_mve_encoding_conflict): Handle new instructions.
1473         (is_mve_undefined): Likewise.
1474         (is_mve_unpredictable): Likewise.
1475         (print_mve_size): Likewise.
1476
1477 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1478             Michael Collison <michael.collison@arm.com>
1479
1480         * arm-dis.c (thumb32_opcodes): Add new instructions.
1481         (enum mve_instructions): Likewise.
1482         (is_mve_encoding_conflict): Likewise.
1483         (is_mve_unpredictable): Likewise.
1484         (print_mve_size): Likewise.
1485
1486 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1487             Michael Collison <michael.collison@arm.com>
1488
1489         * arm-dis.c (thumb32_opcodes): Add new instructions.
1490         (enum mve_instructions): Likewise.
1491         (is_mve_encoding_conflict): Handle new instructions.
1492         (is_mve_undefined): Likewise.
1493         (is_mve_unpredictable): Likewise.
1494         (print_mve_size): Likewise.
1495
1496 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1497             Michael Collison <michael.collison@arm.com>
1498
1499         * arm-dis.c (thumb32_opcodes): Add new instructions.
1500         (enum mve_instructions): Likewise.
1501         (is_mve_encoding_conflict): Handle new instructions.
1502         (is_mve_undefined): Likewise.
1503         (is_mve_unpredictable): Likewise.
1504         (print_mve_size): Likewise.
1505         (print_insn_mve): Likewise.
1506
1507 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1508             Michael Collison <michael.collison@arm.com>
1509
1510         * arm-dis.c (thumb32_opcodes): Add new instructions.
1511         (print_insn_thumb32): Handle new instructions.
1512
1513 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1514             Michael Collison <michael.collison@arm.com>
1515
1516         * arm-dis.c (enum mve_instructions): Add new instructions.
1517         (enum mve_undefined): Add new reasons.
1518         (is_mve_encoding_conflict): Handle new instructions.
1519         (is_mve_undefined): Likewise.
1520         (is_mve_unpredictable): Likewise.
1521         (print_mve_undefined): Likewise.
1522         (print_mve_size): Likewise.
1523         (print_mve_shift_n): Likewise.
1524         (print_insn_mve): Likewise.
1525
1526 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1527             Michael Collison <michael.collison@arm.com>
1528
1529         * arm-dis.c (enum mve_instructions): Add new instructions.
1530         (is_mve_encoding_conflict): Handle new instructions.
1531         (is_mve_unpredictable): Likewise.
1532         (print_mve_rotate): Likewise.
1533         (print_mve_size): Likewise.
1534         (print_insn_mve): Likewise.
1535
1536 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1537             Michael Collison <michael.collison@arm.com>
1538
1539         * arm-dis.c (enum mve_instructions): Add new instructions.
1540         (is_mve_encoding_conflict): Handle new instructions.
1541         (is_mve_unpredictable): Likewise.
1542         (print_mve_size): Likewise.
1543         (print_insn_mve): Likewise.
1544
1545 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1546             Michael Collison <michael.collison@arm.com>
1547
1548         * arm-dis.c (enum mve_instructions): Add new instructions.
1549         (enum mve_undefined): Add new reasons.
1550         (is_mve_encoding_conflict): Handle new instructions.
1551         (is_mve_undefined): Likewise.
1552         (is_mve_unpredictable): Likewise.
1553         (print_mve_undefined): Likewise.
1554         (print_mve_size): Likewise.
1555         (print_insn_mve): Likewise.
1556
1557 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1558             Michael Collison <michael.collison@arm.com>
1559
1560         * arm-dis.c (enum mve_instructions): Add new instructions.
1561         (is_mve_encoding_conflict): Handle new instructions.
1562         (is_mve_undefined): Likewise.
1563         (is_mve_unpredictable): Likewise.
1564         (print_mve_size): Likewise.
1565         (print_insn_mve): Likewise.
1566
1567 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1568             Michael Collison <michael.collison@arm.com>
1569
1570         * arm-dis.c (enum mve_instructions): Add new instructions.
1571         (enum mve_unpredictable): Add new reasons.
1572         (enum mve_undefined): Likewise.
1573         (is_mve_okay_in_it): Handle new isntructions.
1574         (is_mve_encoding_conflict): Likewise.
1575         (is_mve_undefined): Likewise.
1576         (is_mve_unpredictable): Likewise.
1577         (print_mve_vmov_index): Likewise.
1578         (print_simd_imm8): Likewise.
1579         (print_mve_undefined): Likewise.
1580         (print_mve_unpredictable): Likewise.
1581         (print_mve_size): Likewise.
1582         (print_insn_mve): Likewise.
1583
1584 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1585             Michael Collison <michael.collison@arm.com>
1586
1587         * arm-dis.c (enum mve_instructions): Add new instructions.
1588         (enum mve_unpredictable): Add new reasons.
1589         (enum mve_undefined): Likewise.
1590         (is_mve_encoding_conflict): Handle new instructions.
1591         (is_mve_undefined): Likewise.
1592         (is_mve_unpredictable): Likewise.
1593         (print_mve_undefined): Likewise.
1594         (print_mve_unpredictable): Likewise.
1595         (print_mve_rounding_mode): Likewise.
1596         (print_mve_vcvt_size): Likewise.
1597         (print_mve_size): Likewise.
1598         (print_insn_mve): Likewise.
1599
1600 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1601             Michael Collison <michael.collison@arm.com>
1602
1603         * arm-dis.c (enum mve_instructions): Add new instructions.
1604         (enum mve_unpredictable): Add new reasons.
1605         (enum mve_undefined): Likewise.
1606         (is_mve_undefined): Handle new instructions.
1607         (is_mve_unpredictable): Likewise.
1608         (print_mve_undefined): Likewise.
1609         (print_mve_unpredictable): Likewise.
1610         (print_mve_size): Likewise.
1611         (print_insn_mve): Likewise.
1612
1613 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1614             Michael Collison <michael.collison@arm.com>
1615
1616         * arm-dis.c (enum mve_instructions): Add new instructions.
1617         (enum mve_undefined): Add new reasons.
1618         (insns): Add new instructions.
1619         (is_mve_encoding_conflict):
1620         (print_mve_vld_str_addr): New print function.
1621         (is_mve_undefined): Handle new instructions.
1622         (is_mve_unpredictable): Likewise.
1623         (print_mve_undefined): Likewise.
1624         (print_mve_size): Likewise.
1625         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1626         (print_insn_mve):  Handle new operands.
1627
1628 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1629             Michael Collison <michael.collison@arm.com>
1630
1631         * arm-dis.c (enum mve_instructions): Add new instructions.
1632         (enum mve_unpredictable): Add new reasons.
1633         (is_mve_encoding_conflict): Handle new instructions.
1634         (is_mve_unpredictable): Likewise.
1635         (mve_opcodes): Add new instructions.
1636         (print_mve_unpredictable): Handle new reasons.
1637         (print_mve_register_blocks): New print function.
1638         (print_mve_size): Handle new instructions.
1639         (print_insn_mve): Likewise.
1640
1641 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1642             Michael Collison <michael.collison@arm.com>
1643
1644         * arm-dis.c (enum mve_instructions): Add new instructions.
1645         (enum mve_unpredictable): Add new reasons.
1646         (enum mve_undefined): Likewise.
1647         (is_mve_encoding_conflict): Handle new instructions.
1648         (is_mve_undefined): Likewise.
1649         (is_mve_unpredictable): Likewise.
1650         (coprocessor_opcodes): Move NEON VDUP from here...
1651         (neon_opcodes): ... to here.
1652         (mve_opcodes): Add new instructions.
1653         (print_mve_undefined):  Handle new reasons.
1654         (print_mve_unpredictable): Likewise.
1655         (print_mve_size): Handle new instructions.
1656         (print_insn_neon): Handle vdup.
1657         (print_insn_mve): Handle new operands.
1658
1659 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1660             Michael Collison <michael.collison@arm.com>
1661
1662         * arm-dis.c (enum mve_instructions): Add new instructions.
1663         (enum mve_unpredictable): Add new values.
1664         (mve_opcodes): Add new instructions.
1665         (vec_condnames): New array with vector conditions.
1666         (mve_predicatenames): New array with predicate suffixes.
1667         (mve_vec_sizename): New array with vector sizes.
1668         (enum vpt_pred_state): New enum with vector predication states.
1669         (struct vpt_block): New struct type for vpt blocks.
1670         (vpt_block_state): Global struct to keep track of state.
1671         (mve_extract_pred_mask): New helper function.
1672         (num_instructions_vpt_block): Likewise.
1673         (mark_outside_vpt_block): Likewise.
1674         (mark_inside_vpt_block): Likewise.
1675         (invert_next_predicate_state): Likewise.
1676         (update_next_predicate_state): Likewise.
1677         (update_vpt_block_state): Likewise.
1678         (is_vpt_instruction): Likewise.
1679         (is_mve_encoding_conflict): Add entries for new instructions.
1680         (is_mve_unpredictable): Likewise.
1681         (print_mve_unpredictable): Handle new cases.
1682         (print_instruction_predicate): Likewise.
1683         (print_mve_size): New function.
1684         (print_vec_condition): New function.
1685         (print_insn_mve): Handle vpt blocks and new print operands.
1686
1687 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1688
1689         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1690         8, 14 and 15 for Armv8.1-M Mainline.
1691
1692 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1693             Michael Collison <michael.collison@arm.com>
1694
1695         * arm-dis.c (enum mve_instructions): New enum.
1696         (enum mve_unpredictable): Likewise.
1697         (enum mve_undefined): Likewise.
1698         (struct mopcode32): New struct.
1699         (is_mve_okay_in_it): New function.
1700         (is_mve_architecture): Likewise.
1701         (arm_decode_field): Likewise.
1702         (arm_decode_field_multiple): Likewise.
1703         (is_mve_encoding_conflict): Likewise.
1704         (is_mve_undefined): Likewise.
1705         (is_mve_unpredictable): Likewise.
1706         (print_mve_undefined): Likewise.
1707         (print_mve_unpredictable): Likewise.
1708         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1709         (print_insn_mve): New function.
1710         (print_insn_thumb32): Handle MVE architecture.
1711         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1712
1713 2019-05-10  Nick Clifton  <nickc@redhat.com>
1714
1715         PR 24538
1716         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1717         end of the table prematurely.
1718
1719 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1720
1721         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1722         macros for R6.
1723
1724 2019-05-11  Alan Modra  <amodra@gmail.com>
1725
1726         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1727         when -Mraw is in effect.
1728
1729 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1730
1731         * aarch64-dis-2.c: Regenerate.
1732         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1733         (OP_SVE_BBB): New variant set.
1734         (OP_SVE_DDDD): New variant set.
1735         (OP_SVE_HHH): New variant set.
1736         (OP_SVE_HHHU): New variant set.
1737         (OP_SVE_SSS): New variant set.
1738         (OP_SVE_SSSU): New variant set.
1739         (OP_SVE_SHH): New variant set.
1740         (OP_SVE_SBBU): New variant set.
1741         (OP_SVE_DSS): New variant set.
1742         (OP_SVE_DHHU): New variant set.
1743         (OP_SVE_VMV_HSD_BHS): New variant set.
1744         (OP_SVE_VVU_HSD_BHS): New variant set.
1745         (OP_SVE_VVVU_SD_BH): New variant set.
1746         (OP_SVE_VVVU_BHSD): New variant set.
1747         (OP_SVE_VVV_QHD_DBS): New variant set.
1748         (OP_SVE_VVV_HSD_BHS): New variant set.
1749         (OP_SVE_VVV_HSD_BHS2): New variant set.
1750         (OP_SVE_VVV_BHS_HSD): New variant set.
1751         (OP_SVE_VV_BHS_HSD): New variant set.
1752         (OP_SVE_VVV_SD): New variant set.
1753         (OP_SVE_VVU_BHS_HSD): New variant set.
1754         (OP_SVE_VZVV_SD): New variant set.
1755         (OP_SVE_VZVV_BH): New variant set.
1756         (OP_SVE_VZV_SD): New variant set.
1757         (aarch64_opcode_table): Add sve2 instructions.
1758
1759 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1760
1761         * aarch64-asm-2.c: Regenerated.
1762         * aarch64-dis-2.c: Regenerated.
1763         * aarch64-opc-2.c: Regenerated.
1764         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1765         for SVE_SHLIMM_UNPRED_22.
1766         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1767         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1768         operand.
1769
1770 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1771
1772         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1773         sve_size_tsz_bhs iclass encode.
1774         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1775         sve_size_tsz_bhs iclass decode.
1776
1777 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1778
1779         * aarch64-asm-2.c: Regenerated.
1780         * aarch64-dis-2.c: Regenerated.
1781         * aarch64-opc-2.c: Regenerated.
1782         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1783         for SVE_Zm4_11_INDEX.
1784         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1785         (fields): Handle SVE_i2h field.
1786         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1787         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1788
1789 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1790
1791         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1792         sve_shift_tsz_bhsd iclass encode.
1793         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1794         sve_shift_tsz_bhsd iclass decode.
1795
1796 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1797
1798         * aarch64-asm-2.c: Regenerated.
1799         * aarch64-dis-2.c: Regenerated.
1800         * aarch64-opc-2.c: Regenerated.
1801         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1802         (aarch64_encode_variant_using_iclass): Handle
1803         sve_shift_tsz_hsd iclass encode.
1804         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1805         sve_shift_tsz_hsd iclass decode.
1806         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1807         for SVE_SHRIMM_UNPRED_22.
1808         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1809         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1810         operand.
1811
1812 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1813
1814         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1815         sve_size_013 iclass encode.
1816         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1817         sve_size_013 iclass decode.
1818
1819 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1820
1821         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1822         sve_size_bh iclass encode.
1823         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1824         sve_size_bh iclass decode.
1825
1826 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1827
1828         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1829         sve_size_sd2 iclass encode.
1830         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1831         sve_size_sd2 iclass decode.
1832         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1833         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1834
1835 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1836
1837         * aarch64-asm-2.c: Regenerated.
1838         * aarch64-dis-2.c: Regenerated.
1839         * aarch64-opc-2.c: Regenerated.
1840         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1841         for SVE_ADDR_ZX.
1842         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1843         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1844
1845 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1846
1847         * aarch64-asm-2.c: Regenerated.
1848         * aarch64-dis-2.c: Regenerated.
1849         * aarch64-opc-2.c: Regenerated.
1850         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1851         for SVE_Zm3_11_INDEX.
1852         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1853         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1854         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1855         fields.
1856         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1857
1858 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1859
1860         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1861         sve_size_hsd2 iclass encode.
1862         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1863         sve_size_hsd2 iclass decode.
1864         * aarch64-opc.c (fields): Handle SVE_size field.
1865         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1866
1867 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1868
1869         * aarch64-asm-2.c: Regenerated.
1870         * aarch64-dis-2.c: Regenerated.
1871         * aarch64-opc-2.c: Regenerated.
1872         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1873         for SVE_IMM_ROT3.
1874         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1875         (fields): Handle SVE_rot3 field.
1876         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1877         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1878
1879 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1880
1881         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1882         instructions.
1883
1884 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1885
1886         * aarch64-tbl.h
1887         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1888         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1889         aarch64_feature_sve2bitperm): New feature sets.
1890         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1891         for feature set addresses.
1892         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1893         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1894
1895 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1896             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1897
1898         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1899         argument and set ASE_EVA_R6 appropriately.
1900         (set_default_mips_dis_options): Pass ISA to above.
1901         (parse_mips_dis_option): Likewise.
1902         * mips-opc.c (EVAR6): New macro.
1903         (mips_builtin_opcodes): Add llwpe, scwpe.
1904
1905 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1906
1907         * aarch64-asm-2.c: Regenerated.
1908         * aarch64-dis-2.c: Regenerated.
1909         * aarch64-opc-2.c: Regenerated.
1910         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1911         AARCH64_OPND_TME_UIMM16.
1912         (aarch64_print_operand): Likewise.
1913         * aarch64-tbl.h (QL_IMM_NIL): New.
1914         (TME): New.
1915         (_TME_INSN): New.
1916         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1917
1918 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1919
1920         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1921
1922 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1923             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1924
1925         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1926
1927 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1928
1929         * s12z-opc.h: Add extern "C" bracketing to help
1930         users who wish to use this interface in c++ code.
1931
1932 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1933
1934         * s12z-opc.c (bm_decode): Handle bit map operations with the
1935         "reserved0" mode.
1936
1937 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1938
1939         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1940         specifier.  Add entries for VLDR and VSTR of system registers.
1941         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1942         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1943         of %J and %K format specifier.
1944
1945 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1946
1947         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1948         Add new entries for VSCCLRM instruction.
1949         (print_insn_coprocessor): Handle new %C format control code.
1950
1951 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1952
1953         * arm-dis.c (enum isa): New enum.
1954         (struct sopcode32): New structure.
1955         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1956         set isa field of all current entries to ANY.
1957         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1958         Only match an entry if its isa field allows the current mode.
1959
1960 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1961
1962         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1963         CLRM.
1964         (print_insn_thumb32): Add logic to print %n CLRM register list.
1965
1966 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1967
1968         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1969         and %Q patterns.
1970
1971 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1972
1973         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1974         (print_insn_thumb32): Edit the switch case for %Z.
1975
1976 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1977
1978         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1979
1980 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1981
1982         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1983
1984 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1985
1986         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1987
1988 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1989
1990         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1991         Arm register with r13 and r15 unpredictable.
1992         (thumb32_opcodes): New instructions for bfx and bflx.
1993
1994 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1995
1996         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1997
1998 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1999
2000         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2001
2002 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2003
2004         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2005
2006 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2007
2008         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2009
2010 2019-04-12  John Darrington <john@darrington.wattle.id.au>
2011
2012         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2013         "optr". ("operator" is a reserved word in c++).
2014
2015 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2016
2017         * aarch64-opc.c (aarch64_print_operand): Add case for
2018         AARCH64_OPND_Rt_SP.
2019         (verify_constraints): Likewise.
2020         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2021         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2022         to accept Rt|SP as first operand.
2023         (AARCH64_OPERANDS): Add new Rt_SP.
2024         * aarch64-asm-2.c: Regenerated.
2025         * aarch64-dis-2.c: Regenerated.
2026         * aarch64-opc-2.c: Regenerated.
2027
2028 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2029
2030         * aarch64-asm-2.c: Regenerated.
2031         * aarch64-dis-2.c: Likewise.
2032         * aarch64-opc-2.c: Likewise.
2033         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2034
2035 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
2036
2037         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2038
2039 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
2040
2041         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2042         * i386-init.h: Regenerated.
2043
2044 2019-04-07  Alan Modra  <amodra@gmail.com>
2045
2046         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2047         op_separator to control printing of spaces, comma and parens
2048         rather than need_comma, need_paren and spaces vars.
2049
2050 2019-04-07  Alan Modra  <amodra@gmail.com>
2051
2052         PR 24421
2053         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2054         (print_insn_neon, print_insn_arm): Likewise.
2055
2056 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
2057
2058         * i386-dis-evex.h (evex_table): Updated to support BF16
2059         instructions.
2060         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2061         and EVEX_W_0F3872_P_3.
2062         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2063         (cpu_flags): Add bitfield for CpuAVX512_BF16.
2064         * i386-opc.h (enum): Add CpuAVX512_BF16.
2065         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2066         * i386-opc.tbl: Add AVX512 BF16 instructions.
2067         * i386-init.h: Regenerated.
2068         * i386-tbl.h: Likewise.
2069
2070 2019-04-05  Alan Modra  <amodra@gmail.com>
2071
2072         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2073         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2074         to favour printing of "-" branch hint when using the "y" bit.
2075         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2076
2077 2019-04-05  Alan Modra  <amodra@gmail.com>
2078
2079         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2080         opcode until first operand is output.
2081
2082 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2083
2084         PR gas/24349
2085         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2086         (valid_bo_post_v2): Add support for 'at' branch hints.
2087         (insert_bo): Only error on branch on ctr.
2088         (get_bo_hint_mask): New function.
2089         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2090         for inserting 'at' branch hints.
2091         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2092         for extracting 'at' branch hints.
2093         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2094         (BOE): Delete operand.
2095         (BOM, BOP): New operands.
2096         (RM): Update value.
2097         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2098         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2099         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2100         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2101         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2102         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2103         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2104         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2105         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2106         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2107         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2108         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2109         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2110         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2111         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2112         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2113         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2114         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2115         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2116         bttarl+>: New extended mnemonics.
2117
2118 2019-03-28  Alan Modra  <amodra@gmail.com>
2119
2120         PR 24390
2121         * ppc-opc.c (BTF): Define.
2122         (powerpc_opcodes): Use for mtfsb*.
2123         * ppc-dis.c (print_insn_powerpc): Print fields with both
2124         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2125
2126 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2127
2128         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2129         (mapping_symbol_for_insn): Implement new algorithm.
2130         (print_insn): Remove duplicate code.
2131
2132 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2133
2134         * aarch64-dis.c (print_insn_aarch64):
2135         Implement override.
2136
2137 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2138
2139         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2140         order.
2141
2142 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2143
2144         * aarch64-dis.c (last_stop_offset): New.
2145         (print_insn_aarch64): Use stop_offset.
2146
2147 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2148
2149         PR gas/24359
2150         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2151         CPU_ANY_AVX2_FLAGS.
2152         * i386-init.h: Regenerated.
2153
2154 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2155
2156         PR gas/24348
2157         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2158         vmovdqu16, vmovdqu32 and vmovdqu64.
2159         * i386-tbl.h: Regenerated.
2160
2161 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2162
2163         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2164         from vstrszb, vstrszh, and vstrszf.
2165
2166 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2167
2168         * s390-opc.txt: Add instruction descriptions.
2169
2170 2019-02-08  Jim Wilson  <jimw@sifive.com>
2171
2172         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2173         <bne>: Likewise.
2174
2175 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2176
2177         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2178
2179 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2180
2181         PR binutils/23212
2182         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2183         * aarch64-opc.c (verify_elem_sd): New.
2184         (fields): Add FLD_sz entr.
2185         * aarch64-tbl.h (_SIMD_INSN): New.
2186         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2187         fmulx scalar and vector by element isns.
2188
2189 2019-02-07  Nick Clifton  <nickc@redhat.com>
2190
2191         * po/sv.po: Updated Swedish translation.
2192
2193 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2194
2195         * s390-mkopc.c (main): Accept arch13 as cpu string.
2196         * s390-opc.c: Add new instruction formats and instruction opcode
2197         masks.
2198         * s390-opc.txt: Add new arch13 instructions.
2199
2200 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2201
2202         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2203         (aarch64_opcode): Change encoding for stg, stzg
2204         st2g and st2zg.
2205         * aarch64-asm-2.c: Regenerated.
2206         * aarch64-dis-2.c: Regenerated.
2207         * aarch64-opc-2.c: Regenerated.
2208
2209 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2210
2211         * aarch64-asm-2.c: Regenerated.
2212         * aarch64-dis-2.c: Likewise.
2213         * aarch64-opc-2.c: Likewise.
2214         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2215
2216 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2217             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2218
2219         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2220         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2221         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2222         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2223         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2224         case for ldstgv_indexed.
2225         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2226         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2227         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2228         * aarch64-asm-2.c: Regenerated.
2229         * aarch64-dis-2.c: Regenerated.
2230         * aarch64-opc-2.c: Regenerated.
2231
2232 2019-01-23  Nick Clifton  <nickc@redhat.com>
2233
2234         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2235
2236 2019-01-21  Nick Clifton  <nickc@redhat.com>
2237
2238         * po/de.po: Updated German translation.
2239         * po/uk.po: Updated Ukranian translation.
2240
2241 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2242         * mips-dis.c (mips_arch_choices): Fix typo in
2243         gs464, gs464e and gs264e descriptors.
2244
2245 2019-01-19  Nick Clifton  <nickc@redhat.com>
2246
2247         * configure: Regenerate.
2248         * po/opcodes.pot: Regenerate.
2249
2250 2018-06-24  Nick Clifton  <nickc@redhat.com>
2251
2252         2.32 branch created.
2253
2254 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2255
2256         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2257         if it is null.
2258         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2259         zero.
2260
2261 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2262
2263         * configure: Regenerate.
2264
2265 2019-01-07  Alan Modra  <amodra@gmail.com>
2266
2267         * configure: Regenerate.
2268         * po/POTFILES.in: Regenerate.
2269
2270 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2271
2272         * s12z-opc.c: New file.
2273         * s12z-opc.h: New file.
2274         * s12z-dis.c: Removed all code not directly related to display
2275         of instructions.  Used the interface provided by the new files
2276         instead.
2277         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2278         * Makefile.in: Regenerate.
2279         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2280         * configure: Regenerate.
2281
2282 2019-01-01  Alan Modra  <amodra@gmail.com>
2283
2284         Update year range in copyright notice of all files.
2285
2286 For older changes see ChangeLog-2018
2287 \f
2288 Copyright (C) 2019 Free Software Foundation, Inc.
2289
2290 Copying and distribution of this file, with or without modification,
2291 are permitted in any medium without royalty provided the copyright
2292 notice and this notice are preserved.
2293
2294 Local Variables:
2295 mode: change-log
2296 left-margin: 8
2297 fill-column: 74
2298 version-control: never
2299 End: