opcodes/ChangeLog

   1 2019-12-16  Alan Modra  <amodra@gmail.com>
   2
   3         * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
   4         (struct objdump_disasm_info): Delete.
   5         (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
   6         N32_IMMS to unsigned before shifting left.
   7
   8 2019-12-16  Alan Modra  <amodra@gmail.com>
   9
  10         * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
  11         (print_insn_moxie): Remove unnecessary cast.
  12
  13 2019-12-12  Alan Modra  <amodra@gmail.com>
  14
  15         * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
  16         mask.
  17
  18 2019-12-11  Alan Modra  <amodra@gmail.com>
  19
  20         * arc-dis.c (BITS): Don't truncate high bits with shifts.
  21         * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
  22         * tic54x-dis.c (print_instruction): Likewise.
  23         * tilegx-opc.c (parse_insn_tilegx): Likewise.
  24         * tilepro-opc.c (parse_insn_tilepro): Likewise.
  25         * visium-dis.c (disassem_class0): Likewise.
  26         * pdp11-dis.c (sign_extend): Likewise.
  27         (SIGN_BITS): Delete.
  28         * epiphany-ibld.c: Regenerate.
  29         * lm32-ibld.c: Regenerate.
  30         * m32c-ibld.c: Regenerate.
  31
  32 2019-12-11  Alan Modra  <amodra@gmail.com>
  33
  34         * ns32k-dis.c (sign_extend): Correct last patch.
  35
  36 2019-12-11  Alan Modra  <amodra@gmail.com>
  37
  38         * vax-dis.c (NEXTLONG): Avoid signed overflow.
  39
  40 2019-12-11  Alan Modra  <amodra@gmail.com>
  41
  42         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
  43         sign extend using shifts.
  44
  45 2019-12-11  Alan Modra  <amodra@gmail.com>
  46
  47         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
  48
  49 2019-12-11  Alan Modra  <amodra@gmail.com>
  50
  51         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
  52         on NULL registertable entry.
  53         (tic4x_hash_opcode): Use unsigned arithmetic.
  54
  55 2019-12-11  Alan Modra  <amodra@gmail.com>
  56
  57         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
  58
  59 2019-12-11  Alan Modra  <amodra@gmail.com>
  60
  61         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
  62         (bit_extract_simple, sign_extend): Likewise.
  63
  64 2019-12-11  Alan Modra  <amodra@gmail.com>
  65
  66         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
  67
  68 2019-12-11  Alan Modra  <amodra@gmail.com>
  69
  70         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
  71
  72 2019-12-11  Alan Modra  <amodra@gmail.com>
  73
  74         * m68k-dis.c (COERCE32): Cast value first.
  75         (NEXTLONG, NEXTULONG): Avoid signed overflow.
  76
  77 2019-12-11  Alan Modra  <amodra@gmail.com>
  78
  79         * h8300-dis.c (extract_immediate): Avoid signed overflow.
  80         (bfd_h8_disassemble): Likewise.
  81
  82 2019-12-11  Alan Modra  <amodra@gmail.com>
  83
  84         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
  85         past end of operands array.
  86
  87 2019-12-11  Alan Modra  <amodra@gmail.com>
  88
  89         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
  90         overflow when collecting bytes of a number.
  91
  92 2019-12-11  Alan Modra  <amodra@gmail.com>
  93
  94         * cris-dis.c (print_with_operands): Avoid signed integer
  95         overflow when collecting bytes of a 32-bit integer.
  96
  97 2019-12-11  Alan Modra  <amodra@gmail.com>
  98
  99         * cr16-dis.c (EXTRACT, SBM): Rewrite.
 100         (cr16_match_opcode): Delete duplicate bcond test.
 101
 102 2019-12-11  Alan Modra  <amodra@gmail.com>
 103
 104         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
 105         (SIGNBIT): New.
 106         (MASKBITS, SIGNEXTEND): Rewrite.
 107         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
 108         unsigned arithmetic, instead assign result of SIGNEXTEND back
 109         to x.
 110         (fmtconst_val): Use 1u in shift expression.
 111
 112 2019-12-11  Alan Modra  <amodra@gmail.com>
 113
 114         * arc-dis.c (find_format_from_table): Use ull constant when
 115         shifting by up to 32.
 116
 117 2019-12-11  Alan Modra  <amodra@gmail.com>
 118
 119         PR 25270
 120         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
 121         false when field is zero for sve_size_tsz_bhs.
 122
 123 2019-12-11  Alan Modra  <amodra@gmail.com>
 124
 125         * epiphany-ibld.c: Regenerate.
 126
 127 2019-12-10  Alan Modra  <amodra@gmail.com>
 128
 129         PR 24960
 130         * disassemble.c (disassemble_free_target): New function.
 131
 132 2019-12-10  Alan Modra  <amodra@gmail.com>
 133
 134         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 135         * disassemble.c (disassemble_init_for_target): Likewise.
 136         * bpf-dis.c: Regenerate.
 137         * epiphany-dis.c: Regenerate.
 138         * fr30-dis.c: Regenerate.
 139         * frv-dis.c: Regenerate.
 140         * ip2k-dis.c: Regenerate.
 141         * iq2000-dis.c: Regenerate.
 142         * lm32-dis.c: Regenerate.
 143         * m32c-dis.c: Regenerate.
 144         * m32r-dis.c: Regenerate.
 145         * mep-dis.c: Regenerate.
 146         * mt-dis.c: Regenerate.
 147         * or1k-dis.c: Regenerate.
 148         * xc16x-dis.c: Regenerate.
 149         * xstormy16-dis.c: Regenerate.
 150
 151 2019-12-10  Alan Modra  <amodra@gmail.com>
 152
 153         * ppc-dis.c (private): Delete variable.
 154         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 155         (powerpc_init_dialect): Don't use global private.
 156
 157 2019-12-10  Alan Modra  <amodra@gmail.com>
 158
 159         * s12z-opc.c: Formatting.
 160
 161 2019-12-08  Alan Modra  <amodra@gmail.com>
 162
 163         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 164         registers.
 165
 166 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 167
 168         * aarch64-tbl.h (aarch64_feature_crypto,
 169         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 170         CRYPTO_V8_2_INSN): Delete.
 171
 172 2019-12-05  Alan Modra  <amodra@gmail.com>
 173
 174         PR 25249
 175         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 176         (struct string_buf): New.
 177         (strbuf): New function.
 178         (get_field): Use strbuf rather than strdup of local temp.
 179         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 180         (get_field_rfsl, get_field_imm15): Likewise.
 181         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 182         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 183         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 184         get_field functions.
 185
 186 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 187
 188         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 189         * i386-tbl.h: Re-generate.
 190
 191 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 194
 195 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 196
 197         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 198         forms.
 199         (xbegin): Drop DefaultSize.
 200         * i386-tbl.h: Re-generate.
 201
 202 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 203
 204         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 205         Change the coproc CRC conditions to use the extension
 206         feature set, second word, base on ARM_EXT2_CRC.
 207
 208 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 209
 210         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 211         * i386-tbl.h: Re-generate.
 212
 213 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 214
 215         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 216         JumpInterSegment, and JumpAbsolute entries.
 217         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 218         JUMP_ABSOLUTE): Define.
 219         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 220         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 221         fields.
 222         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 223         JumpInterSegment): Define.
 224         * i386-tbl.h: Re-generate.
 225
 226 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 227
 228         * i386-gen.c (operand_type_init): Remove
 229         OPERAND_TYPE_JUMPABSOLUTE entry.
 230         (opcode_modifiers): Add JumpAbsolute entry.
 231         (operand_types): Remove JumpAbsolute entry.
 232         * i386-opc.h (JumpAbsolute): Move between enums.
 233         (struct i386_opcode_modifier): Add jumpabsolute field.
 234         (union i386_operand_type): Remove jumpabsolute field.
 235         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 236         * i386-init.h, i386-tbl.h: Re-generate.
 237
 238 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 239
 240         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 241         (operand_types): Remove AnySize entry.
 242         * i386-opc.h (AnySize): Move between enums.
 243         (struct i386_opcode_modifier): Add anysize field.
 244         (OTUnused): Un-comment.
 245         (union i386_operand_type): Remove anysize field.
 246         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 247         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 248         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 249         AnySize.
 250         * i386-tbl.h: Re-generate.
 251
 252 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 253
 254         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 255         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 256         use the floating point register (FPR).
 257
 258 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 259
 260         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 261         cmode 1101.
 262         (is_mve_encoding_conflict): Update cmode conflict checks for
 263         MVE_VMVN_IMM.
 264
 265 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 266
 267         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 268         entry.
 269         (operand_types): Remove EsSeg entry.
 270         (main): Replace stale use of OTMax.
 271         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 272         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 273         (EsSeg): Delete.
 274         (OTUnused): Comment out.
 275         (union i386_operand_type): Remove esseg field.
 276         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 277         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 278         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 279         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 280         * i386-init.h, i386-tbl.h: Re-generate.
 281
 282 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 283
 284         * i386-gen.c (operand_instances): Add RegB entry.
 285         * i386-opc.h (enum operand_instance): Add RegB.
 286         * i386-opc.tbl (RegC, RegD, RegB): Define.
 287         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 288         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 289         monitorx, mwaitx): Drop ImmExt and convert encodings
 290         accordingly.
 291         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 292         (edx, rdx): Add Instance=RegD.
 293         (ebx, rbx): Add Instance=RegB.
 294         * i386-tbl.h: Re-generate.
 295
 296 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 297
 298         * i386-gen.c (operand_type_init): Adjust
 299         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 300         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 301         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 302         (operand_instances): New.
 303         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 304         (output_operand_type): New parameter "instance". Process it.
 305         (process_i386_operand_type): New local variable "instance".
 306         (main): Adjust static assertions.
 307         * i386-opc.h (INSTANCE_WIDTH): Define.
 308         (enum operand_instance): New.
 309         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 310         (union i386_operand_type): Replace acc, inoutportreg, and
 311         shiftcount by instance.
 312         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 313         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 314         Add Instance=.
 315         * i386-init.h, i386-tbl.h: Re-generate.
 316
 317 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 318
 319         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 320         smaxp/sminp entries' "tied_operand" field to 2.
 321
 322 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 323
 324         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 325         "index" local variable by that of the already existing "num".
 326
 327 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 328
 329         PR gas/25167
 330         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 331         * i386-tbl.h: Regenerated.
 332
 333 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 334
 335         * i386-gen.c (operand_type_init): Add Class= to
 336         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 337         OPERAND_TYPE_REGBND entry.
 338         (operand_classes): Add RegMask and RegBND entries.
 339         (operand_types): Drop RegMask and RegBND entry.
 340         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 341         (RegMask, RegBND): Delete.
 342         (union i386_operand_type): Remove regmask and regbnd fields.
 343         * i386-opc.tbl (RegMask, RegBND): Define.
 344         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 345         Class=RegBND.
 346         * i386-init.h, i386-tbl.h: Re-generate.
 347
 348 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 349
 350         * i386-gen.c (operand_type_init): Add Class= to
 351         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 352         OPERAND_TYPE_REGZMM entries.
 353         (operand_classes): Add RegMMX and RegSIMD entries.
 354         (operand_types): Drop RegMMX and RegSIMD entries.
 355         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 356         (RegMMX, RegSIMD): Delete.
 357         (union i386_operand_type): Remove regmmx and regsimd fields.
 358         * i386-opc.tbl (RegMMX): Define.
 359         (RegXMM, RegYMM, RegZMM): Add Class=.
 360         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 361         Class=RegSIMD.
 362         * i386-init.h, i386-tbl.h: Re-generate.
 363
 364 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 365
 366         * i386-gen.c (operand_type_init): Add Class= to
 367         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 368         entries.
 369         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 370         (operand_types): Drop Control, Debug, and Test entries.
 371         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 372         (Control, Debug, Test): Delete.
 373         (union i386_operand_type): Remove control, debug, and test
 374         fields.
 375         * i386-opc.tbl (Control, Debug, Test): Define.
 376         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 377         Class=RegDR, and Test by Class=RegTR.
 378         * i386-init.h, i386-tbl.h: Re-generate.
 379
 380 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 381
 382         * i386-gen.c (operand_type_init): Add Class= to
 383         OPERAND_TYPE_SREG entry.
 384         (operand_classes): Add SReg entry.
 385         (operand_types): Drop SReg entry.
 386         * i386-opc.h (enum operand_class): Add SReg.
 387         (SReg): Delete.
 388         (union i386_operand_type): Remove sreg field.
 389         * i386-opc.tbl (SReg): Define.
 390         * i386-reg.tbl: Replace SReg by Class=SReg.
 391         * i386-init.h, i386-tbl.h: Re-generate.
 392
 393 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 394
 395         * i386-gen.c (operand_type_init): Add Class=. New
 396         OPERAND_TYPE_ANYIMM entry.
 397         (operand_classes): New.
 398         (operand_types): Drop Reg entry.
 399         (output_operand_type): New parameter "class". Process it.
 400         (process_i386_operand_type): New local variable "class".
 401         (main): Adjust static assertions.
 402         * i386-opc.h (CLASS_WIDTH): Define.
 403         (enum operand_class): New.
 404         (Reg): Replace by Class. Adjust comment.
 405         (union i386_operand_type): Replace reg by class.
 406         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 407         Class=.
 408         * i386-reg.tbl: Replace Reg by Class=Reg.
 409         * i386-init.h: Re-generate.
 410
 411 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 412
 413         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 414         (aarch64_opcode_table): Add data gathering hint mnemonic.
 415         * opcodes/aarch64-dis-2.c: Account for new instruction.
 416
 417 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 418
 419         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 420
 421
 422 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 423
 424         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 425         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 426         aarch64_feature_f64mm): New feature sets.
 427         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 428         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 429         instructions.
 430         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 431         macros.
 432         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 433         (OP_SVE_QQQ): New qualifier.
 434         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 435         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 436         the movprfx constraint.
 437         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 438         (aarch64_opcode_table): Define new instructions smmla,
 439         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 440         uzip{1/2}, trn{1/2}.
 441         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 442         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 443         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 444         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 445         Account for new instructions.
 446         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 447         S4x32 operand.
 448         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 449
 450 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 451 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 452
 453         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 454         Armv8.6-A.
 455         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 456         (neon_opcodes): Add bfloat SIMD instructions.
 457         (print_insn_coprocessor): Add new control character %b to print
 458         condition code without checking cp_num.
 459         (print_insn_neon): Account for BFloat16 instructions that have no
 460         special top-byte handling.
 461
 462 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 463 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 464
 465         * arm-dis.c (print_insn_coprocessor,
 466         print_insn_generic_coprocessor): Create wrapper functions around
 467         the implementation of the print_insn_coprocessor control codes.
 468         (print_insn_coprocessor_1): Original print_insn_coprocessor
 469         function that now takes which array to look at as an argument.
 470         (print_insn_arm): Use both print_insn_coprocessor and
 471         print_insn_generic_coprocessor.
 472         (print_insn_thumb32): As above.
 473
 474 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 475 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 476
 477         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 478         in reglane special case.
 479         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 480         aarch64_find_next_opcode): Account for new instructions.
 481         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 482         in reglane special case.
 483         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 484         new AARCH64_OPND_QLF_S_2H qualifier.
 485         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 486         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 487         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 488         sets.
 489         (BFLOAT_SVE, BFLOAT): New feature set macros.
 490         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 491         instructions.
 492         (aarch64_opcode_table): Define new instructions bfdot,
 493         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 494         bfcvtn2, bfcvt.
 495
 496 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 497 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 498
 499         * aarch64-tbl.h (ARMV8_6): New macro.
 500
 501 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 502
 503         * i386-dis.c (prefix_table): Add mcommit.
 504         (rm_table): Add rdpru.
 505         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 506         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 507         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 508         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 509         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 510         * i386-opc.tbl (mcommit, rdpru): New.
 511         * i386-init.h, i386-tbl.h: Re-generate.
 512
 513 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 514
 515         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 516         "names32" instead.
 517         (OP_Monitor): Drop local variable "op1_names", re-purpose
 518         "names" for it instead, and replace former "names" uses by
 519         "names32" ones.
 520
 521 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 522
 523         PR/gas 25167
 524         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 525         operand-less forms.
 526         * opcodes/i386-tbl.h: Re-generate.
 527
 528 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 529
 530         * i386-dis.c (OP_Mwaitx): Delete.
 531         (prefix_table): Use OP_Mwait for mwaitx entry.
 532         (OP_Mwait): Also handle mwaitx.
 533
 534 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 535
 536         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 537         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 538         (prefix_table): Add respective entries.
 539         (rm_table): Link to those entries.
 540
 541 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 542
 543         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 544         (REG_0F1C_P_0_MOD_0): ... this.
 545         (REG_0F1E_MOD_3): Rename to ...
 546         (REG_0F1E_P_1_MOD_3): ... this.
 547         (RM_0F01_REG_5): Rename to ...
 548         (RM_0F01_REG_5_MOD_3): ... this.
 549         (RM_0F01_REG_7): Rename to ...
 550         (RM_0F01_REG_7_MOD_3): ... this.
 551         (RM_0F1E_MOD_3_REG_7): Rename to ...
 552         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 553         (RM_0FAE_REG_6): Rename to ...
 554         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 555         (RM_0FAE_REG_7): Rename to ...
 556         (RM_0FAE_REG_7_MOD_3): ... this.
 557         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 558         (PREFIX_0F01_REG_5_MOD_0): ... this.
 559         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 560         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 561         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 562         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 563         (PREFIX_0FAE_REG_0): Rename to ...
 564         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 565         (PREFIX_0FAE_REG_1): Rename to ...
 566         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 567         (PREFIX_0FAE_REG_2): Rename to ...
 568         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 569         (PREFIX_0FAE_REG_3): Rename to ...
 570         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 571         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 572         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 573         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 574         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 575         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 576         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 577         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 578         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 579         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 580         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 581         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 582         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 583         (PREFIX_0FAE_REG_7): Rename to ...
 584         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 585         (PREFIX_MOD_0_0FC3): Rename to ...
 586         (PREFIX_0FC3_MOD_0): ... this.
 587         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 588         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 589         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 590         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 591         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 592         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 593         (reg_table, prefix_table, mod_table, rm_table): Adjust
 594         accordingly.
 595
 596 2019-11-04  Nick Clifton  <nickc@redhat.com>
 597
 598         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 599         of a v850 system register.  Move the v850_sreg_names array into
 600         this function.
 601         (get_v850_reg_name): Likewise for ordinary register names.
 602         (get_v850_vreg_name): Likewise for vector register names.
 603         (get_v850_cc_name): Likewise for condition codes.
 604         * get_v850_float_cc_name): Likewise for floating point condition
 605         codes.
 606         (get_v850_cacheop_name): Likewise for cache-ops.
 607         (get_v850_prefop_name): Likewise for pref-ops.
 608         (disassemble): Use the new accessor functions.
 609
 610 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 611
 612         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 613         immediate for the writeback form of ldraa/ldrab if it is 0.
 614         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 615         * aarch64-opc-2.c: Regenerated.
 616
 617 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 618
 619         * i386-gen.c (operand_type_shorthands): Delete.
 620         (operand_type_init): Expand previous shorthands.
 621         (set_bitfield_from_shorthand): Rename back to ...
 622         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 623         of operand_type_init[].
 624         (set_bitfield): Adjust call to the above function.
 625         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 626         RegXMM, RegYMM, RegZMM): Define.
 627         * i386-reg.tbl: Expand prior shorthands.
 628
 629 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 630
 631         * i386-gen.c (output_i386_opcode): Change order of fields
 632         emitted to output.
 633         * i386-opc.h (struct insn_template): Move operands field.
 634         Convert extension_opcode field to unsigned short.
 635         * i386-tbl.h: Re-generate.
 636
 637 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 638
 639         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 640         of W.
 641         * i386-opc.h (W): Extend comment.
 642         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 643         general purpose variants not allowing for byte operands.
 644         * i386-tbl.h: Re-generate.
 645
 646 2019-10-29  Nick Clifton  <nickc@redhat.com>
 647
 648         * tic30-dis.c (print_branch): Correct size of operand array.
 649
 650 2019-10-29  Nick Clifton  <nickc@redhat.com>
 651
 652         * d30v-dis.c (print_insn): Check that operand index is valid
 653         before attempting to access the operands array.
 654
 655 2019-10-29  Nick Clifton  <nickc@redhat.com>
 656
 657         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 658         locating the bit to be tested.
 659
 660 2019-10-29  Nick Clifton  <nickc@redhat.com>
 661
 662         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 663         values.
 664         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 665         (print_insn_s12z):  Check for illegal size values.
 666
 667 2019-10-28  Nick Clifton  <nickc@redhat.com>
 668
 669         * csky-dis.c (csky_chars_to_number): Check for a negative
 670         count. Use an unsigned integer to construct the return value.
 671
 672 2019-10-28  Nick Clifton  <nickc@redhat.com>
 673
 674         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 675         operand buffer.  Set value to 15 not 13.
 676         (get_register_operand): Use OPERAND_BUFFER_LEN.
 677         (get_indirect_operand): Likewise.
 678         (print_two_operand): Likewise.
 679         (print_three_operand): Likewise.
 680         (print_oar_insn): Likewise.
 681
 682 2019-10-28  Nick Clifton  <nickc@redhat.com>
 683
 684         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 685         (bit_extract_simple): Likewise.
 686         (bit_copy): Likewise.
 687         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 688         index_offset array are not accessed.
 689
 690 2019-10-28  Nick Clifton  <nickc@redhat.com>
 691
 692         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 693         operand.
 694
 695 2019-10-25  Nick Clifton  <nickc@redhat.com>
 696
 697         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 698         access to opcodes.op array element.
 699
 700 2019-10-23  Nick Clifton  <nickc@redhat.com>
 701
 702         * rx-dis.c (get_register_name): Fix spelling typo in error
 703         message.
 704         (get_condition_name, get_flag_name, get_double_register_name)
 705         (get_double_register_high_name, get_double_register_low_name)
 706         (get_double_control_register_name, get_double_condition_name)
 707         (get_opsize_name, get_size_name): Likewise.
 708
 709 2019-10-22  Nick Clifton  <nickc@redhat.com>
 710
 711         * rx-dis.c (get_size_name): New function.  Provides safe
 712         access to name array.
 713         (get_opsize_name): Likewise.
 714         (print_insn_rx): Use the accessor functions.
 715
 716 2019-10-16  Nick Clifton  <nickc@redhat.com>
 717
 718         * rx-dis.c (get_register_name): New function.  Provides safe
 719         access to name array.
 720         (get_condition_name, get_flag_name, get_double_register_name)
 721         (get_double_register_high_name, get_double_register_low_name)
 722         (get_double_control_register_name, get_double_condition_name):
 723         Likewise.
 724         (print_insn_rx): Use the accessor functions.
 725
 726 2019-10-09  Nick Clifton  <nickc@redhat.com>
 727
 728         PR 25041
 729         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 730         instructions.
 731
 732 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 733
 734         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 735         (cmpsd): Likewise. Move EsSeg to other operand.
 736         * opcodes/i386-tbl.h: Re-generate.
 737
 738 2019-09-23  Alan Modra  <amodra@gmail.com>
 739
 740         * m68k-dis.c: Include cpu-m68k.h
 741
 742 2019-09-23  Alan Modra  <amodra@gmail.com>
 743
 744         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 745         "elf/mips.h" earlier.
 746
 747 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 748
 749         PR gas/25012
 750         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 751         with SReg operand.
 752         * i386-tbl.h: Re-generate.
 753
 754 2019-09-18  Alan Modra  <amodra@gmail.com>
 755
 756         * arc-ext.c: Update throughout for bfd section macro changes.
 757
 758 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 759
 760         * Makefile.in: Re-generate.
 761         * configure: Re-generate.
 762
 763 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 764
 765         * riscv-opc.c (riscv_opcodes): Change subset field
 766         to insn_class field for all instructions.
 767         (riscv_insn_types): Likewise.
 768
 769 2019-09-16  Phil Blundell  <pb@pbcl.net>
 770
 771         * configure: Regenerated.
 772
 773 2019-09-10  Miod Vallat  <miod@online.fr>
 774
 775         PR 24982
 776         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 777
 778 2019-09-09  Phil Blundell  <pb@pbcl.net>
 779
 780         binutils 2.33 branch created.
 781
 782 2019-09-03  Nick Clifton  <nickc@redhat.com>
 783
 784         PR 24961
 785         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 786         greater than zero before indexing via (bufcnt -1).
 787
 788 2019-09-03  Nick Clifton  <nickc@redhat.com>
 789
 790         PR 24958
 791         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 792         (MAX_SPEC_REG_NAME_LEN): Define.
 793         (struct mmix_dis_info): Use defined constants for array lengths.
 794         (get_reg_name): New function.
 795         (get_sprec_reg_name): New function.
 796         (print_insn_mmix): Use new functions.
 797
 798 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 799
 800         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 801         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 802         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 803
 804 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 805
 806         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 807         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 808         (aarch64_sys_reg_supported_p): Update checks for the above.
 809
 810 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 811
 812         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 813         cases MVE_SQRSHRL and MVE_UQRSHLL.
 814         (print_insn_mve): Add case for specifier 'k' to check
 815         specific bit of the instruction.
 816
 817 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 818
 819         PR 24854
 820         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 821         encountering an unknown machine type.
 822         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 823         cases return -1 rather than calling abort.
 824
 825 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 826
 827         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 828         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 829         IgnoreSize.
 830         * i386-tbl.h: Re-generate.
 831
 832 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 833
 834         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 835         instructions.
 836
 837 2019-07-30  Mel Chen <mel.chen@sifive.com>
 838
 839         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 840         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 841
 842         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 843         fscsr.
 844
 845 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 846
 847         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 848         and MPY class instructions.
 849         (parse_option): Add nps400 option.
 850         (print_arc_disassembler_options): Add nps400 info.
 851
 852 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 853
 854         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 855         (bspop): Likewise.
 856         (modapp): Likewise.
 857         * arc-opc.c (RAD_CHK): Add.
 858         * arc-tbl.h: Regenerate.
 859
 860 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 861
 862         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 863         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 864
 865 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 866
 867         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 868         instructions as UNPREDICTABLE.
 869
 870 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 871
 872         * bpf-desc.c: Regenerated.
 873
 874 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 875
 876         * i386-gen.c (static_assert): Define.
 877         (main): Use it.
 878         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 879         (Opcode_Modifier_Num): ... this.
 880         (Mem): Delete.
 881
 882 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 883
 884         * i386-gen.c (operand_types): Move RegMem ...
 885         (opcode_modifiers): ... here.
 886         * i386-opc.h (RegMem): Move to opcode modifer enum.
 887         (union i386_operand_type): Move regmem field ...
 888         (struct i386_opcode_modifier): ... here.
 889         * i386-opc.tbl (RegMem): Define.
 890         (mov, movq): Move RegMem on segment, control, debug, and test
 891         register flavors.
 892         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 893         to non-SSE2AVX flavor.
 894         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 895         Move RegMem on register only flavors. Drop IgnoreSize from
 896         legacy encoding flavors.
 897         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 898         flavors.
 899         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 900         register only flavors.
 901         (vmovd): Move RegMem and drop IgnoreSize on register only
 902         flavor. Change opcode and operand order to store form.
 903         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 904
 905 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 906
 907         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 908         entries.
 909         * i386-opc.h (SReg2, SReg3): Replace by ...
 910         (SReg): ... this.
 911         (union i386_operand_type): Replace sreg fields.
 912         * i386-opc.tbl (mov, ): Use SReg.
 913         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 914         register flavors.
 915         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 916         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 917
 918 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 919
 920         * bpf-desc.c: Regenerate.
 921         * bpf-opc.c: Likewise.
 922         * bpf-opc.h: Likewise.
 923
 924 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 925
 926         * bpf-desc.c: Regenerate.
 927         * bpf-opc.c: Likewise.
 928
 929 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 930
 931         * arm-dis.c (print_insn_coprocessor): Rename index to
 932         index_operand.
 933
 934 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 935
 936         * riscv-opc.c (riscv_insn_types): Add r4 type.
 937
 938         * riscv-opc.c (riscv_insn_types): Add b and j type.
 939
 940         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 941         format for sb type and correct s type.
 942
 943 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 944
 945         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 946         SVE FMOV alias of FCPY.
 947
 948 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 949
 950         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 951         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 952
 953 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 954
 955         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 956         registers in an instruction prefixed by MOVPRFX.
 957
 958 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 959
 960         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 961         sve_size_13 icode to account for variant behaviour of
 962         pmull{t,b}.
 963         * aarch64-dis-2.c: Regenerate.
 964         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 965         sve_size_13 icode to account for variant behaviour of
 966         pmull{t,b}.
 967         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 968         (OP_SVE_VVV_Q_D): Add new qualifier.
 969         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 970         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 971         AES and those not.
 972
 973 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 974
 975         * opcodes/i386-gen.c (operand_type_init): Remove
 976         OPERAND_TYPE_VEC_IMM4 entry.
 977         (operand_types): Remove Vec_Imm4.
 978         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 979         (union i386_operand_type): Remove vec_imm4.
 980         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 981         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 982
 983 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 984
 985         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 986         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 987         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 988         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 989         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 990         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 991         * i386-tbl.h: Re-generate.
 992
 993 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 994
 995         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 996         register operands.
 997         * i386-tbl.h: Re-generate.
 998
 999 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1000
1001         * i386-opc.tbl (C): New.
1002         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1003         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1004         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1005         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1006         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1007         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1008         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1009         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1010         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1011         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1012         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1013         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1014         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1015         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1016         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1017         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1018         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1019         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1020         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1021         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1022         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1023         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1024         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1025         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1026         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1027         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1028         flavors.
1029         * i386-tbl.h: Re-generate.
1030
1031 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1032
1033         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1034         register operands.
1035         * i386-tbl.h: Re-generate.
1036
1037 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1038
1039         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1040         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1041         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1042         * i386-tbl.h: Re-generate.
1043
1044 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1045
1046         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1047         Disp8MemShift from register only templates.
1048         * i386-tbl.h: Re-generate.
1049
1050 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1051
1052         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1053         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1054         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1055         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1056         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1057         EVEX_W_0F11_P_3_M_1): Delete.
1058         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1059         EVEX_W_0F11_P_3): New.
1060         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1061         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1062         MOD_EVEX_0F11_PREFIX_3 table entries.
1063         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1064         PREFIX_EVEX_0F11 table entries.
1065         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1066         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1067         EVEX_W_0F11_P_3_M_{0,1} table entries.
1068
1069 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1070
1071         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1072         Delete.
1073
1074 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1075
1076         PR binutils/24719
1077         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1078         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1079         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1080         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1081         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1082         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1083         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1084         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1085         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1086         PREFIX_EVEX_0F38C6_REG_6 entries.
1087         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1088         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1089         EVEX_W_0F38C7_R_6_P_2 entries.
1090         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1091         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1092         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1093         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1094         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1095         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1096         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1097
1098 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1099
1100         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1101         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1102         VEX_LEN_0F2D_P_3): Delete.
1103         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1104         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1105         (prefix_table): ... here.
1106
1107 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1108
1109         * i386-dis.c (Iq): Delete.
1110         (Id): New.
1111         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1112         TBM insns.
1113         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1114         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1115         (OP_E_memory): Also honor needindex when deciding whether an
1116         address size prefix needs printing.
1117         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1118
1119 2019-06-26  Jim Wilson  <jimw@sifive.com>
1120
1121         PR binutils/24739
1122         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1123         Set info->display_endian to info->endian_code.
1124
1125 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1126
1127         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1128         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1129         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1130         OPERAND_TYPE_ACC64 entries.
1131         * i386-init.h: Re-generate.
1132
1133 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1134
1135         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1136         Delete.
1137         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1138         of dqa_mode.
1139         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1140         entries here.
1141         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1142         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1143
1144 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1145
1146         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1147         variables.
1148
1149 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1150
1151         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1152         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1153         movnti.
1154         * i386-opc.tbl (movnti): Add IgnoreSize.
1155         * i386-tbl.h: Re-generate.
1156
1157 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1158
1159         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1160         * i386-tbl.h: Re-generate.
1161
1162 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1163
1164         * i386-dis-evex.h: Break into ...
1165         * i386-dis-evex-len.h: New file.
1166         * i386-dis-evex-mod.h: Likewise.
1167         * i386-dis-evex-prefix.h: Likewise.
1168         * i386-dis-evex-reg.h: Likewise.
1169         * i386-dis-evex-w.h: Likewise.
1170         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1171         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1172         i386-dis-evex-mod.h.
1173
1174 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1175
1176         PR binutils/24700
1177         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1178         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1179         EVEX_W_0F385B_P_2.
1180         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1181         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1182         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1183         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1184         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1185         EVEX_LEN_0F385B_P_2_W_1.
1186         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1187         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1188         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1189         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1190         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1191         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1192         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1193         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1194         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1195         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1196
1197 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1198
1199         PR binutils/24691
1200         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1201         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1202         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1203         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1204         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1205         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1206         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1207         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1208         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1209         EVEX_LEN_0F3A43_P_2_W_1.
1210         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1211         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1212         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1213         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1214         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1215         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1216         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1217         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1218         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1219         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1220         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1221         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1222
1223 2019-06-14  Nick Clifton  <nickc@redhat.com>
1224
1225         * po/fr.po; Updated French translation.
1226
1227 2019-06-13  Stafford Horne  <shorne@gmail.com>
1228
1229         * or1k-asm.c: Regenerated.
1230         * or1k-desc.c: Regenerated.
1231         * or1k-desc.h: Regenerated.
1232         * or1k-dis.c: Regenerated.
1233         * or1k-ibld.c: Regenerated.
1234         * or1k-opc.c: Regenerated.
1235         * or1k-opc.h: Regenerated.
1236         * or1k-opinst.c: Regenerated.
1237
1238 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1239
1240         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1241
1242 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1243
1244         PR binutils/24633
1245         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1246         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1247         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1248         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1249         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1250         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1251         EVEX_LEN_0F3A1B_P_2_W_1.
1252         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1253         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1254         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1255         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1256         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1257         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1258         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1259         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1260
1261 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1262
1263         PR binutils/24626
1264         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1265         EVEX.vvvv when disassembling VEX and EVEX instructions.
1266         (OP_VEX): Set vex.register_specifier to 0 after readding
1267         vex.register_specifier.
1268         (OP_Vex_2src_1): Likewise.
1269         (OP_Vex_2src_2): Likewise.
1270         (OP_LWP_E): Likewise.
1271         (OP_EX_Vex): Don't check vex.register_specifier.
1272         (OP_XMM_Vex): Likewise.
1273
1274 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1275             Lili Cui  <lili.cui@intel.com>
1276
1277         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1278         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1279         instructions.
1280         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1281         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1282         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1283         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1284         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1285         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1286         * i386-init.h: Regenerated.
1287         * i386-tbl.h: Likewise.
1288
1289 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1290             Lili Cui  <lili.cui@intel.com>
1291
1292         * doc/c-i386.texi: Document enqcmd.
1293         * testsuite/gas/i386/enqcmd-intel.d: New file.
1294         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1295         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1296         * testsuite/gas/i386/enqcmd.d: Likewise.
1297         * testsuite/gas/i386/enqcmd.s: Likewise.
1298         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1299         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1300         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1301         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1302         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1303         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1304         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1305         and x86-64-enqcmd.
1306
1307 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1308
1309         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1310
1311 2019-06-03  Alan Modra  <amodra@gmail.com>
1312
1313         * ppc-dis.c (prefix_opcd_indices): Correct size.
1314
1315 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1316
1317         PR gas/24625
1318         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1319         Disp8ShiftVL.
1320         * i386-tbl.h: Regenerated.
1321
1322 2019-05-24  Alan Modra  <amodra@gmail.com>
1323
1324         * po/POTFILES.in: Regenerate.
1325
1326 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1327             Alan Modra  <amodra@gmail.com>
1328
1329         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1330         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1331         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1332         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1333         XTOP>): Define and add entries.
1334         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1335         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1336         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1337         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1338
1339 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1340             Alan Modra  <amodra@gmail.com>
1341
1342         * ppc-dis.c (ppc_opts): Add "future" entry.
1343         (PREFIX_OPCD_SEGS): Define.
1344         (prefix_opcd_indices): New array.
1345         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1346         (lookup_prefix): New function.
1347         (print_insn_powerpc): Handle 64-bit prefix instructions.
1348         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1349         (PMRR, POWERXX): Define.
1350         (prefix_opcodes): New instruction table.
1351         (prefix_num_opcodes): New constant.
1352
1353 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1354
1355         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1356         * configure: Regenerated.
1357         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1358         and cpu/bpf.opc.
1359         (HFILES): Add bpf-desc.h and bpf-opc.h.
1360         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1361         bpf-ibld.c and bpf-opc.c.
1362         (BPF_DEPS): Define.
1363         * Makefile.in: Regenerated.
1364         * disassemble.c (ARCH_bpf): Define.
1365         (disassembler): Add case for bfd_arch_bpf.
1366         (disassemble_init_for_target): Likewise.
1367         (enum epbf_isa_attr): Define.
1368         * disassemble.h: extern print_insn_bpf.
1369         * bpf-asm.c: Generated.
1370         * bpf-opc.h: Likewise.
1371         * bpf-opc.c: Likewise.
1372         * bpf-ibld.c: Likewise.
1373         * bpf-dis.c: Likewise.
1374         * bpf-desc.h: Likewise.
1375         * bpf-desc.c: Likewise.
1376
1377 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1378
1379         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1380         and VMSR with the new operands.
1381
1382 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1383
1384         * arm-dis.c (enum mve_instructions): New enum
1385         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1386         and cneg.
1387         (mve_opcodes): New instructions as above.
1388         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1389         csneg and csel.
1390         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1391
1392 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1393
1394         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1395         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1396         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1397         uqshl, urshrl and urshr.
1398         (is_mve_okay_in_it): Add new instructions to TRUE list.
1399         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1400         (print_insn_mve): Updated to accept new %j,
1401         %<bitfield>m and %<bitfield>n patterns.
1402
1403 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1404
1405         * mips-opc.c (mips_builtin_opcodes): Change source register
1406         constraint for DAUI.
1407
1408 2019-05-20  Nick Clifton  <nickc@redhat.com>
1409
1410         * po/fr.po: Updated French translation.
1411
1412 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1413             Michael Collison <michael.collison@arm.com>
1414
1415         * arm-dis.c (thumb32_opcodes): Add new instructions.
1416         (enum mve_instructions): Likewise.
1417         (enum mve_undefined): Add new reasons.
1418         (is_mve_encoding_conflict): Handle new instructions.
1419         (is_mve_undefined): Likewise.
1420         (is_mve_unpredictable): Likewise.
1421         (print_mve_undefined): Likewise.
1422         (print_mve_size): Likewise.
1423
1424 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1425             Michael Collison <michael.collison@arm.com>
1426
1427         * arm-dis.c (thumb32_opcodes): Add new instructions.
1428         (enum mve_instructions): Likewise.
1429         (is_mve_encoding_conflict): Handle new instructions.
1430         (is_mve_undefined): Likewise.
1431         (is_mve_unpredictable): Likewise.
1432         (print_mve_size): Likewise.
1433
1434 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1435             Michael Collison <michael.collison@arm.com>
1436
1437         * arm-dis.c (thumb32_opcodes): Add new instructions.
1438         (enum mve_instructions): Likewise.
1439         (is_mve_encoding_conflict): Likewise.
1440         (is_mve_unpredictable): Likewise.
1441         (print_mve_size): Likewise.
1442
1443 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1444             Michael Collison <michael.collison@arm.com>
1445
1446         * arm-dis.c (thumb32_opcodes): Add new instructions.
1447         (enum mve_instructions): Likewise.
1448         (is_mve_encoding_conflict): Handle new instructions.
1449         (is_mve_undefined): Likewise.
1450         (is_mve_unpredictable): Likewise.
1451         (print_mve_size): Likewise.
1452
1453 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1454             Michael Collison <michael.collison@arm.com>
1455
1456         * arm-dis.c (thumb32_opcodes): Add new instructions.
1457         (enum mve_instructions): Likewise.
1458         (is_mve_encoding_conflict): Handle new instructions.
1459         (is_mve_undefined): Likewise.
1460         (is_mve_unpredictable): Likewise.
1461         (print_mve_size): Likewise.
1462         (print_insn_mve): Likewise.
1463
1464 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1465             Michael Collison <michael.collison@arm.com>
1466
1467         * arm-dis.c (thumb32_opcodes): Add new instructions.
1468         (print_insn_thumb32): Handle new instructions.
1469
1470 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1471             Michael Collison <michael.collison@arm.com>
1472
1473         * arm-dis.c (enum mve_instructions): Add new instructions.
1474         (enum mve_undefined): Add new reasons.
1475         (is_mve_encoding_conflict): Handle new instructions.
1476         (is_mve_undefined): Likewise.
1477         (is_mve_unpredictable): Likewise.
1478         (print_mve_undefined): Likewise.
1479         (print_mve_size): Likewise.
1480         (print_mve_shift_n): Likewise.
1481         (print_insn_mve): Likewise.
1482
1483 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1484             Michael Collison <michael.collison@arm.com>
1485
1486         * arm-dis.c (enum mve_instructions): Add new instructions.
1487         (is_mve_encoding_conflict): Handle new instructions.
1488         (is_mve_unpredictable): Likewise.
1489         (print_mve_rotate): Likewise.
1490         (print_mve_size): Likewise.
1491         (print_insn_mve): Likewise.
1492
1493 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1494             Michael Collison <michael.collison@arm.com>
1495
1496         * arm-dis.c (enum mve_instructions): Add new instructions.
1497         (is_mve_encoding_conflict): Handle new instructions.
1498         (is_mve_unpredictable): Likewise.
1499         (print_mve_size): Likewise.
1500         (print_insn_mve): Likewise.
1501
1502 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1503             Michael Collison <michael.collison@arm.com>
1504
1505         * arm-dis.c (enum mve_instructions): Add new instructions.
1506         (enum mve_undefined): Add new reasons.
1507         (is_mve_encoding_conflict): Handle new instructions.
1508         (is_mve_undefined): Likewise.
1509         (is_mve_unpredictable): Likewise.
1510         (print_mve_undefined): Likewise.
1511         (print_mve_size): Likewise.
1512         (print_insn_mve): Likewise.
1513
1514 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1515             Michael Collison <michael.collison@arm.com>
1516
1517         * arm-dis.c (enum mve_instructions): Add new instructions.
1518         (is_mve_encoding_conflict): Handle new instructions.
1519         (is_mve_undefined): Likewise.
1520         (is_mve_unpredictable): Likewise.
1521         (print_mve_size): Likewise.
1522         (print_insn_mve): Likewise.
1523
1524 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1525             Michael Collison <michael.collison@arm.com>
1526
1527         * arm-dis.c (enum mve_instructions): Add new instructions.
1528         (enum mve_unpredictable): Add new reasons.
1529         (enum mve_undefined): Likewise.
1530         (is_mve_okay_in_it): Handle new isntructions.
1531         (is_mve_encoding_conflict): Likewise.
1532         (is_mve_undefined): Likewise.
1533         (is_mve_unpredictable): Likewise.
1534         (print_mve_vmov_index): Likewise.
1535         (print_simd_imm8): Likewise.
1536         (print_mve_undefined): Likewise.
1537         (print_mve_unpredictable): Likewise.
1538         (print_mve_size): Likewise.
1539         (print_insn_mve): Likewise.
1540
1541 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1542             Michael Collison <michael.collison@arm.com>
1543
1544         * arm-dis.c (enum mve_instructions): Add new instructions.
1545         (enum mve_unpredictable): Add new reasons.
1546         (enum mve_undefined): Likewise.
1547         (is_mve_encoding_conflict): Handle new instructions.
1548         (is_mve_undefined): Likewise.
1549         (is_mve_unpredictable): Likewise.
1550         (print_mve_undefined): Likewise.
1551         (print_mve_unpredictable): Likewise.
1552         (print_mve_rounding_mode): Likewise.
1553         (print_mve_vcvt_size): Likewise.
1554         (print_mve_size): Likewise.
1555         (print_insn_mve): Likewise.
1556
1557 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1558             Michael Collison <michael.collison@arm.com>
1559
1560         * arm-dis.c (enum mve_instructions): Add new instructions.
1561         (enum mve_unpredictable): Add new reasons.
1562         (enum mve_undefined): Likewise.
1563         (is_mve_undefined): Handle new instructions.
1564         (is_mve_unpredictable): Likewise.
1565         (print_mve_undefined): Likewise.
1566         (print_mve_unpredictable): Likewise.
1567         (print_mve_size): Likewise.
1568         (print_insn_mve): Likewise.
1569
1570 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1571             Michael Collison <michael.collison@arm.com>
1572
1573         * arm-dis.c (enum mve_instructions): Add new instructions.
1574         (enum mve_undefined): Add new reasons.
1575         (insns): Add new instructions.
1576         (is_mve_encoding_conflict):
1577         (print_mve_vld_str_addr): New print function.
1578         (is_mve_undefined): Handle new instructions.
1579         (is_mve_unpredictable): Likewise.
1580         (print_mve_undefined): Likewise.
1581         (print_mve_size): Likewise.
1582         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1583         (print_insn_mve):  Handle new operands.
1584
1585 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1586             Michael Collison <michael.collison@arm.com>
1587
1588         * arm-dis.c (enum mve_instructions): Add new instructions.
1589         (enum mve_unpredictable): Add new reasons.
1590         (is_mve_encoding_conflict): Handle new instructions.
1591         (is_mve_unpredictable): Likewise.
1592         (mve_opcodes): Add new instructions.
1593         (print_mve_unpredictable): Handle new reasons.
1594         (print_mve_register_blocks): New print function.
1595         (print_mve_size): Handle new instructions.
1596         (print_insn_mve): Likewise.
1597
1598 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1599             Michael Collison <michael.collison@arm.com>
1600
1601         * arm-dis.c (enum mve_instructions): Add new instructions.
1602         (enum mve_unpredictable): Add new reasons.
1603         (enum mve_undefined): Likewise.
1604         (is_mve_encoding_conflict): Handle new instructions.
1605         (is_mve_undefined): Likewise.
1606         (is_mve_unpredictable): Likewise.
1607         (coprocessor_opcodes): Move NEON VDUP from here...
1608         (neon_opcodes): ... to here.
1609         (mve_opcodes): Add new instructions.
1610         (print_mve_undefined):  Handle new reasons.
1611         (print_mve_unpredictable): Likewise.
1612         (print_mve_size): Handle new instructions.
1613         (print_insn_neon): Handle vdup.
1614         (print_insn_mve): Handle new operands.
1615
1616 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1617             Michael Collison <michael.collison@arm.com>
1618
1619         * arm-dis.c (enum mve_instructions): Add new instructions.
1620         (enum mve_unpredictable): Add new values.
1621         (mve_opcodes): Add new instructions.
1622         (vec_condnames): New array with vector conditions.
1623         (mve_predicatenames): New array with predicate suffixes.
1624         (mve_vec_sizename): New array with vector sizes.
1625         (enum vpt_pred_state): New enum with vector predication states.
1626         (struct vpt_block): New struct type for vpt blocks.
1627         (vpt_block_state): Global struct to keep track of state.
1628         (mve_extract_pred_mask): New helper function.
1629         (num_instructions_vpt_block): Likewise.
1630         (mark_outside_vpt_block): Likewise.
1631         (mark_inside_vpt_block): Likewise.
1632         (invert_next_predicate_state): Likewise.
1633         (update_next_predicate_state): Likewise.
1634         (update_vpt_block_state): Likewise.
1635         (is_vpt_instruction): Likewise.
1636         (is_mve_encoding_conflict): Add entries for new instructions.
1637         (is_mve_unpredictable): Likewise.
1638         (print_mve_unpredictable): Handle new cases.
1639         (print_instruction_predicate): Likewise.
1640         (print_mve_size): New function.
1641         (print_vec_condition): New function.
1642         (print_insn_mve): Handle vpt blocks and new print operands.
1643
1644 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1645
1646         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1647         8, 14 and 15 for Armv8.1-M Mainline.
1648
1649 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1650             Michael Collison <michael.collison@arm.com>
1651
1652         * arm-dis.c (enum mve_instructions): New enum.
1653         (enum mve_unpredictable): Likewise.
1654         (enum mve_undefined): Likewise.
1655         (struct mopcode32): New struct.
1656         (is_mve_okay_in_it): New function.
1657         (is_mve_architecture): Likewise.
1658         (arm_decode_field): Likewise.
1659         (arm_decode_field_multiple): Likewise.
1660         (is_mve_encoding_conflict): Likewise.
1661         (is_mve_undefined): Likewise.
1662         (is_mve_unpredictable): Likewise.
1663         (print_mve_undefined): Likewise.
1664         (print_mve_unpredictable): Likewise.
1665         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1666         (print_insn_mve): New function.
1667         (print_insn_thumb32): Handle MVE architecture.
1668         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1669
1670 2019-05-10  Nick Clifton  <nickc@redhat.com>
1671
1672         PR 24538
1673         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1674         end of the table prematurely.
1675
1676 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1677
1678         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1679         macros for R6.
1680
1681 2019-05-11  Alan Modra  <amodra@gmail.com>
1682
1683         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1684         when -Mraw is in effect.
1685
1686 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1687
1688         * aarch64-dis-2.c: Regenerate.
1689         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1690         (OP_SVE_BBB): New variant set.
1691         (OP_SVE_DDDD): New variant set.
1692         (OP_SVE_HHH): New variant set.
1693         (OP_SVE_HHHU): New variant set.
1694         (OP_SVE_SSS): New variant set.
1695         (OP_SVE_SSSU): New variant set.
1696         (OP_SVE_SHH): New variant set.
1697         (OP_SVE_SBBU): New variant set.
1698         (OP_SVE_DSS): New variant set.
1699         (OP_SVE_DHHU): New variant set.
1700         (OP_SVE_VMV_HSD_BHS): New variant set.
1701         (OP_SVE_VVU_HSD_BHS): New variant set.
1702         (OP_SVE_VVVU_SD_BH): New variant set.
1703         (OP_SVE_VVVU_BHSD): New variant set.
1704         (OP_SVE_VVV_QHD_DBS): New variant set.
1705         (OP_SVE_VVV_HSD_BHS): New variant set.
1706         (OP_SVE_VVV_HSD_BHS2): New variant set.
1707         (OP_SVE_VVV_BHS_HSD): New variant set.
1708         (OP_SVE_VV_BHS_HSD): New variant set.
1709         (OP_SVE_VVV_SD): New variant set.
1710         (OP_SVE_VVU_BHS_HSD): New variant set.
1711         (OP_SVE_VZVV_SD): New variant set.
1712         (OP_SVE_VZVV_BH): New variant set.
1713         (OP_SVE_VZV_SD): New variant set.
1714         (aarch64_opcode_table): Add sve2 instructions.
1715
1716 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1717
1718         * aarch64-asm-2.c: Regenerated.
1719         * aarch64-dis-2.c: Regenerated.
1720         * aarch64-opc-2.c: Regenerated.
1721         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1722         for SVE_SHLIMM_UNPRED_22.
1723         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1724         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1725         operand.
1726
1727 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1728
1729         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1730         sve_size_tsz_bhs iclass encode.
1731         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1732         sve_size_tsz_bhs iclass decode.
1733
1734 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1735
1736         * aarch64-asm-2.c: Regenerated.
1737         * aarch64-dis-2.c: Regenerated.
1738         * aarch64-opc-2.c: Regenerated.
1739         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1740         for SVE_Zm4_11_INDEX.
1741         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1742         (fields): Handle SVE_i2h field.
1743         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1744         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1745
1746 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1747
1748         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1749         sve_shift_tsz_bhsd iclass encode.
1750         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1751         sve_shift_tsz_bhsd iclass decode.
1752
1753 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1754
1755         * aarch64-asm-2.c: Regenerated.
1756         * aarch64-dis-2.c: Regenerated.
1757         * aarch64-opc-2.c: Regenerated.
1758         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1759         (aarch64_encode_variant_using_iclass): Handle
1760         sve_shift_tsz_hsd iclass encode.
1761         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1762         sve_shift_tsz_hsd iclass decode.
1763         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1764         for SVE_SHRIMM_UNPRED_22.
1765         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1766         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1767         operand.
1768
1769 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1770
1771         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1772         sve_size_013 iclass encode.
1773         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1774         sve_size_013 iclass decode.
1775
1776 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1777
1778         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1779         sve_size_bh iclass encode.
1780         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1781         sve_size_bh iclass decode.
1782
1783 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1784
1785         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1786         sve_size_sd2 iclass encode.
1787         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1788         sve_size_sd2 iclass decode.
1789         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1790         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1791
1792 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1793
1794         * aarch64-asm-2.c: Regenerated.
1795         * aarch64-dis-2.c: Regenerated.
1796         * aarch64-opc-2.c: Regenerated.
1797         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1798         for SVE_ADDR_ZX.
1799         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1800         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1801
1802 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1803
1804         * aarch64-asm-2.c: Regenerated.
1805         * aarch64-dis-2.c: Regenerated.
1806         * aarch64-opc-2.c: Regenerated.
1807         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1808         for SVE_Zm3_11_INDEX.
1809         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1810         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1811         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1812         fields.
1813         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1814
1815 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1816
1817         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1818         sve_size_hsd2 iclass encode.
1819         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1820         sve_size_hsd2 iclass decode.
1821         * aarch64-opc.c (fields): Handle SVE_size field.
1822         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1823
1824 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1825
1826         * aarch64-asm-2.c: Regenerated.
1827         * aarch64-dis-2.c: Regenerated.
1828         * aarch64-opc-2.c: Regenerated.
1829         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1830         for SVE_IMM_ROT3.
1831         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1832         (fields): Handle SVE_rot3 field.
1833         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1834         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1835
1836 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1837
1838         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1839         instructions.
1840
1841 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1842
1843         * aarch64-tbl.h
1844         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1845         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1846         aarch64_feature_sve2bitperm): New feature sets.
1847         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1848         for feature set addresses.
1849         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1850         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1851
1852 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1853             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1854
1855         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1856         argument and set ASE_EVA_R6 appropriately.
1857         (set_default_mips_dis_options): Pass ISA to above.
1858         (parse_mips_dis_option): Likewise.
1859         * mips-opc.c (EVAR6): New macro.
1860         (mips_builtin_opcodes): Add llwpe, scwpe.
1861
1862 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1863
1864         * aarch64-asm-2.c: Regenerated.
1865         * aarch64-dis-2.c: Regenerated.
1866         * aarch64-opc-2.c: Regenerated.
1867         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1868         AARCH64_OPND_TME_UIMM16.
1869         (aarch64_print_operand): Likewise.
1870         * aarch64-tbl.h (QL_IMM_NIL): New.
1871         (TME): New.
1872         (_TME_INSN): New.
1873         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1874
1875 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1876
1877         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1878
1879 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1880             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1881
1882         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1883
1884 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1885
1886         * s12z-opc.h: Add extern "C" bracketing to help
1887         users who wish to use this interface in c++ code.
1888
1889 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1890
1891         * s12z-opc.c (bm_decode): Handle bit map operations with the
1892         "reserved0" mode.
1893
1894 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1895
1896         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1897         specifier.  Add entries for VLDR and VSTR of system registers.
1898         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1899         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1900         of %J and %K format specifier.
1901
1902 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1903
1904         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1905         Add new entries for VSCCLRM instruction.
1906         (print_insn_coprocessor): Handle new %C format control code.
1907
1908 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1909
1910         * arm-dis.c (enum isa): New enum.
1911         (struct sopcode32): New structure.
1912         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1913         set isa field of all current entries to ANY.
1914         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1915         Only match an entry if its isa field allows the current mode.
1916
1917 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1918
1919         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1920         CLRM.
1921         (print_insn_thumb32): Add logic to print %n CLRM register list.
1922
1923 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1924
1925         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1926         and %Q patterns.
1927
1928 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1929
1930         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1931         (print_insn_thumb32): Edit the switch case for %Z.
1932
1933 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1934
1935         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1936
1937 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1938
1939         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1940
1941 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1942
1943         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1944
1945 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1946
1947         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1948         Arm register with r13 and r15 unpredictable.
1949         (thumb32_opcodes): New instructions for bfx and bflx.
1950
1951 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1952
1953         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1954
1955 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1956
1957         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1958
1959 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1960
1961         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1962
1963 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1964
1965         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1966
1967 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1968
1969         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1970         "optr". ("operator" is a reserved word in c++).
1971
1972 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1973
1974         * aarch64-opc.c (aarch64_print_operand): Add case for
1975         AARCH64_OPND_Rt_SP.
1976         (verify_constraints): Likewise.
1977         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1978         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1979         to accept Rt|SP as first operand.
1980         (AARCH64_OPERANDS): Add new Rt_SP.
1981         * aarch64-asm-2.c: Regenerated.
1982         * aarch64-dis-2.c: Regenerated.
1983         * aarch64-opc-2.c: Regenerated.
1984
1985 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1986
1987         * aarch64-asm-2.c: Regenerated.
1988         * aarch64-dis-2.c: Likewise.
1989         * aarch64-opc-2.c: Likewise.
1990         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1991
1992 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1993
1994         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1995
1996 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1997
1998         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1999         * i386-init.h: Regenerated.
2000
2001 2019-04-07  Alan Modra  <amodra@gmail.com>
2002
2003         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2004         op_separator to control printing of spaces, comma and parens
2005         rather than need_comma, need_paren and spaces vars.
2006
2007 2019-04-07  Alan Modra  <amodra@gmail.com>
2008
2009         PR 24421
2010         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2011         (print_insn_neon, print_insn_arm): Likewise.
2012
2013 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
2014
2015         * i386-dis-evex.h (evex_table): Updated to support BF16
2016         instructions.
2017         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2018         and EVEX_W_0F3872_P_3.
2019         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2020         (cpu_flags): Add bitfield for CpuAVX512_BF16.
2021         * i386-opc.h (enum): Add CpuAVX512_BF16.
2022         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2023         * i386-opc.tbl: Add AVX512 BF16 instructions.
2024         * i386-init.h: Regenerated.
2025         * i386-tbl.h: Likewise.
2026
2027 2019-04-05  Alan Modra  <amodra@gmail.com>
2028
2029         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2030         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2031         to favour printing of "-" branch hint when using the "y" bit.
2032         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2033
2034 2019-04-05  Alan Modra  <amodra@gmail.com>
2035
2036         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2037         opcode until first operand is output.
2038
2039 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2040
2041         PR gas/24349
2042         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2043         (valid_bo_post_v2): Add support for 'at' branch hints.
2044         (insert_bo): Only error on branch on ctr.
2045         (get_bo_hint_mask): New function.
2046         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2047         for inserting 'at' branch hints.
2048         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2049         for extracting 'at' branch hints.
2050         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2051         (BOE): Delete operand.
2052         (BOM, BOP): New operands.
2053         (RM): Update value.
2054         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2055         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2056         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2057         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2058         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2059         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2060         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2061         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2062         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2063         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2064         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2065         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2066         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2067         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2068         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2069         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2070         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2071         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2072         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2073         bttarl+>: New extended mnemonics.
2074
2075 2019-03-28  Alan Modra  <amodra@gmail.com>
2076
2077         PR 24390
2078         * ppc-opc.c (BTF): Define.
2079         (powerpc_opcodes): Use for mtfsb*.
2080         * ppc-dis.c (print_insn_powerpc): Print fields with both
2081         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2082
2083 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2084
2085         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2086         (mapping_symbol_for_insn): Implement new algorithm.
2087         (print_insn): Remove duplicate code.
2088
2089 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2090
2091         * aarch64-dis.c (print_insn_aarch64):
2092         Implement override.
2093
2094 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2095
2096         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2097         order.
2098
2099 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2100
2101         * aarch64-dis.c (last_stop_offset): New.
2102         (print_insn_aarch64): Use stop_offset.
2103
2104 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2105
2106         PR gas/24359
2107         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2108         CPU_ANY_AVX2_FLAGS.
2109         * i386-init.h: Regenerated.
2110
2111 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2112
2113         PR gas/24348
2114         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2115         vmovdqu16, vmovdqu32 and vmovdqu64.
2116         * i386-tbl.h: Regenerated.
2117
2118 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2119
2120         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2121         from vstrszb, vstrszh, and vstrszf.
2122
2123 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2124
2125         * s390-opc.txt: Add instruction descriptions.
2126
2127 2019-02-08  Jim Wilson  <jimw@sifive.com>
2128
2129         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2130         <bne>: Likewise.
2131
2132 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2133
2134         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2135
2136 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2137
2138         PR binutils/23212
2139         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2140         * aarch64-opc.c (verify_elem_sd): New.
2141         (fields): Add FLD_sz entr.
2142         * aarch64-tbl.h (_SIMD_INSN): New.
2143         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2144         fmulx scalar and vector by element isns.
2145
2146 2019-02-07  Nick Clifton  <nickc@redhat.com>
2147
2148         * po/sv.po: Updated Swedish translation.
2149
2150 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2151
2152         * s390-mkopc.c (main): Accept arch13 as cpu string.
2153         * s390-opc.c: Add new instruction formats and instruction opcode
2154         masks.
2155         * s390-opc.txt: Add new arch13 instructions.
2156
2157 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2158
2159         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2160         (aarch64_opcode): Change encoding for stg, stzg
2161         st2g and st2zg.
2162         * aarch64-asm-2.c: Regenerated.
2163         * aarch64-dis-2.c: Regenerated.
2164         * aarch64-opc-2.c: Regenerated.
2165
2166 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2167
2168         * aarch64-asm-2.c: Regenerated.
2169         * aarch64-dis-2.c: Likewise.
2170         * aarch64-opc-2.c: Likewise.
2171         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2172
2173 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2174             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2175
2176         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2177         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2178         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2179         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2180         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2181         case for ldstgv_indexed.
2182         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2183         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2184         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2185         * aarch64-asm-2.c: Regenerated.
2186         * aarch64-dis-2.c: Regenerated.
2187         * aarch64-opc-2.c: Regenerated.
2188
2189 2019-01-23  Nick Clifton  <nickc@redhat.com>
2190
2191         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2192
2193 2019-01-21  Nick Clifton  <nickc@redhat.com>
2194
2195         * po/de.po: Updated German translation.
2196         * po/uk.po: Updated Ukranian translation.
2197
2198 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2199         * mips-dis.c (mips_arch_choices): Fix typo in
2200         gs464, gs464e and gs264e descriptors.
2201
2202 2019-01-19  Nick Clifton  <nickc@redhat.com>
2203
2204         * configure: Regenerate.
2205         * po/opcodes.pot: Regenerate.
2206
2207 2018-06-24  Nick Clifton  <nickc@redhat.com>
2208
2209         2.32 branch created.
2210
2211 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2212
2213         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2214         if it is null.
2215         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2216         zero.
2217
2218 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2219
2220         * configure: Regenerate.
2221
2222 2019-01-07  Alan Modra  <amodra@gmail.com>
2223
2224         * configure: Regenerate.
2225         * po/POTFILES.in: Regenerate.
2226
2227 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2228
2229         * s12z-opc.c: New file.
2230         * s12z-opc.h: New file.
2231         * s12z-dis.c: Removed all code not directly related to display
2232         of instructions.  Used the interface provided by the new files
2233         instead.
2234         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2235         * Makefile.in: Regenerate.
2236         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2237         * configure: Regenerate.
2238
2239 2019-01-01  Alan Modra  <amodra@gmail.com>
2240
2241         Update year range in copyright notice of all files.
2242
2243 For older changes see ChangeLog-2018
2244 \f
2245 Copyright (C) 2019 Free Software Foundation, Inc.
2246
2247 Copying and distribution of this file, with or without modification,
2248 are permitted in any medium without royalty provided the copyright
2249 notice and this notice are preserved.
2250
2251 Local Variables:
2252 mode: change-log
2253 left-margin: 8
2254 fill-column: 74
2255 version-control: never
2256 End: