opcodes/ChangeLog

   1 2019-12-17  Alan Modra  <amodra@gmail.com>
   2
   3         * tic80-dis.c: Delete file.
   4         * tic80-opc.c: Delete file.
   5         * disassemble.c: Remove tic80 support.
   6         * disassemble.h: Likewise.
   7         * Makefile.am: Likewise.
   8         * configure.ac: Likewise.
   9         * Makefile.in: Regenerate.
  10         * configure: Regenerate.
  11         * po/POTFILES.in: Regenerate.
  12
  13 2019-12-17  Alan Modra  <amodra@gmail.com>
  14
  15         * bpf-ibld.c: Regenerate.
  16
  17 2019-12-16  Alan Modra  <amodra@gmail.com>
  18
  19         * aarch64-dis.c (sign_extend): Return uint64_t.  Rewrite without
  20         conditional.
  21         (aarch64_ext_imm): Avoid signed overflow.
  22
  23 2019-12-16  Alan Modra  <amodra@gmail.com>
  24
  25         * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
  26
  27 2019-12-16  Alan Modra  <amodra@gmail.com>
  28
  29         * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
  30
  31 2019-12-16  Alan Modra  <amodra@gmail.com>
  32
  33         * xstormy16-ibld.c: Regenerate.
  34
  35 2019-12-16  Alan Modra  <amodra@gmail.com>
  36
  37         * score-dis.c (print_insn_score16): Move rpush/rpop imm field
  38         value adjustment so that it doesn't affect reg field too.
  39
  40 2019-12-16  Alan Modra  <amodra@gmail.com>
  41
  42         * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
  43         (get_number_of_operands, getargtype, getbits, getregname),
  44         (getcopregname, getprocregname, gettrapstring, getcinvstring),
  45         (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
  46         (powerof2, match_opcode, make_instruction, print_arguments),
  47         (print_arg): Delete forward declarations, moving static to..
  48         (getregname, getcopregname, getregliststring): ..these definitions.
  49         (build_mask): Return unsigned int mask.
  50         (match_opcode): Use unsigned int vars.
  51
  52 2019-12-16  Alan Modra  <amodra@gmail.com>
  53
  54         * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
  55
  56 2019-12-16  Alan Modra  <amodra@gmail.com>
  57
  58         * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
  59         (struct objdump_disasm_info): Delete.
  60         (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
  61         N32_IMMS to unsigned before shifting left.
  62
  63 2019-12-16  Alan Modra  <amodra@gmail.com>
  64
  65         * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
  66         (print_insn_moxie): Remove unnecessary cast.
  67
  68 2019-12-12  Alan Modra  <amodra@gmail.com>
  69
  70         * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
  71         mask.
  72
  73 2019-12-11  Alan Modra  <amodra@gmail.com>
  74
  75         * arc-dis.c (BITS): Don't truncate high bits with shifts.
  76         * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
  77         * tic54x-dis.c (print_instruction): Likewise.
  78         * tilegx-opc.c (parse_insn_tilegx): Likewise.
  79         * tilepro-opc.c (parse_insn_tilepro): Likewise.
  80         * visium-dis.c (disassem_class0): Likewise.
  81         * pdp11-dis.c (sign_extend): Likewise.
  82         (SIGN_BITS): Delete.
  83         * epiphany-ibld.c: Regenerate.
  84         * lm32-ibld.c: Regenerate.
  85         * m32c-ibld.c: Regenerate.
  86
  87 2019-12-11  Alan Modra  <amodra@gmail.com>
  88
  89         * ns32k-dis.c (sign_extend): Correct last patch.
  90
  91 2019-12-11  Alan Modra  <amodra@gmail.com>
  92
  93         * vax-dis.c (NEXTLONG): Avoid signed overflow.
  94
  95 2019-12-11  Alan Modra  <amodra@gmail.com>
  96
  97         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
  98         sign extend using shifts.
  99
 100 2019-12-11  Alan Modra  <amodra@gmail.com>
 101
 102         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
 103
 104 2019-12-11  Alan Modra  <amodra@gmail.com>
 105
 106         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
 107         on NULL registertable entry.
 108         (tic4x_hash_opcode): Use unsigned arithmetic.
 109
 110 2019-12-11  Alan Modra  <amodra@gmail.com>
 111
 112         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
 113
 114 2019-12-11  Alan Modra  <amodra@gmail.com>
 115
 116         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
 117         (bit_extract_simple, sign_extend): Likewise.
 118
 119 2019-12-11  Alan Modra  <amodra@gmail.com>
 120
 121         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
 122
 123 2019-12-11  Alan Modra  <amodra@gmail.com>
 124
 125         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
 126
 127 2019-12-11  Alan Modra  <amodra@gmail.com>
 128
 129         * m68k-dis.c (COERCE32): Cast value first.
 130         (NEXTLONG, NEXTULONG): Avoid signed overflow.
 131
 132 2019-12-11  Alan Modra  <amodra@gmail.com>
 133
 134         * h8300-dis.c (extract_immediate): Avoid signed overflow.
 135         (bfd_h8_disassemble): Likewise.
 136
 137 2019-12-11  Alan Modra  <amodra@gmail.com>
 138
 139         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
 140         past end of operands array.
 141
 142 2019-12-11  Alan Modra  <amodra@gmail.com>
 143
 144         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
 145         overflow when collecting bytes of a number.
 146
 147 2019-12-11  Alan Modra  <amodra@gmail.com>
 148
 149         * cris-dis.c (print_with_operands): Avoid signed integer
 150         overflow when collecting bytes of a 32-bit integer.
 151
 152 2019-12-11  Alan Modra  <amodra@gmail.com>
 153
 154         * cr16-dis.c (EXTRACT, SBM): Rewrite.
 155         (cr16_match_opcode): Delete duplicate bcond test.
 156
 157 2019-12-11  Alan Modra  <amodra@gmail.com>
 158
 159         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
 160         (SIGNBIT): New.
 161         (MASKBITS, SIGNEXTEND): Rewrite.
 162         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
 163         unsigned arithmetic, instead assign result of SIGNEXTEND back
 164         to x.
 165         (fmtconst_val): Use 1u in shift expression.
 166
 167 2019-12-11  Alan Modra  <amodra@gmail.com>
 168
 169         * arc-dis.c (find_format_from_table): Use ull constant when
 170         shifting by up to 32.
 171
 172 2019-12-11  Alan Modra  <amodra@gmail.com>
 173
 174         PR 25270
 175         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
 176         false when field is zero for sve_size_tsz_bhs.
 177
 178 2019-12-11  Alan Modra  <amodra@gmail.com>
 179
 180         * epiphany-ibld.c: Regenerate.
 181
 182 2019-12-10  Alan Modra  <amodra@gmail.com>
 183
 184         PR 24960
 185         * disassemble.c (disassemble_free_target): New function.
 186
 187 2019-12-10  Alan Modra  <amodra@gmail.com>
 188
 189         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 190         * disassemble.c (disassemble_init_for_target): Likewise.
 191         * bpf-dis.c: Regenerate.
 192         * epiphany-dis.c: Regenerate.
 193         * fr30-dis.c: Regenerate.
 194         * frv-dis.c: Regenerate.
 195         * ip2k-dis.c: Regenerate.
 196         * iq2000-dis.c: Regenerate.
 197         * lm32-dis.c: Regenerate.
 198         * m32c-dis.c: Regenerate.
 199         * m32r-dis.c: Regenerate.
 200         * mep-dis.c: Regenerate.
 201         * mt-dis.c: Regenerate.
 202         * or1k-dis.c: Regenerate.
 203         * xc16x-dis.c: Regenerate.
 204         * xstormy16-dis.c: Regenerate.
 205
 206 2019-12-10  Alan Modra  <amodra@gmail.com>
 207
 208         * ppc-dis.c (private): Delete variable.
 209         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 210         (powerpc_init_dialect): Don't use global private.
 211
 212 2019-12-10  Alan Modra  <amodra@gmail.com>
 213
 214         * s12z-opc.c: Formatting.
 215
 216 2019-12-08  Alan Modra  <amodra@gmail.com>
 217
 218         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 219         registers.
 220
 221 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 222
 223         * aarch64-tbl.h (aarch64_feature_crypto,
 224         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 225         CRYPTO_V8_2_INSN): Delete.
 226
 227 2019-12-05  Alan Modra  <amodra@gmail.com>
 228
 229         PR 25249
 230         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 231         (struct string_buf): New.
 232         (strbuf): New function.
 233         (get_field): Use strbuf rather than strdup of local temp.
 234         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 235         (get_field_rfsl, get_field_imm15): Likewise.
 236         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 237         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 238         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 239         get_field functions.
 240
 241 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 242
 243         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 244         * i386-tbl.h: Re-generate.
 245
 246 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 247
 248         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 249
 250 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 251
 252         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 253         forms.
 254         (xbegin): Drop DefaultSize.
 255         * i386-tbl.h: Re-generate.
 256
 257 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 258
 259         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 260         Change the coproc CRC conditions to use the extension
 261         feature set, second word, base on ARM_EXT2_CRC.
 262
 263 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 264
 265         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 266         * i386-tbl.h: Re-generate.
 267
 268 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 269
 270         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 271         JumpInterSegment, and JumpAbsolute entries.
 272         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 273         JUMP_ABSOLUTE): Define.
 274         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 275         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 276         fields.
 277         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 278         JumpInterSegment): Define.
 279         * i386-tbl.h: Re-generate.
 280
 281 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 282
 283         * i386-gen.c (operand_type_init): Remove
 284         OPERAND_TYPE_JUMPABSOLUTE entry.
 285         (opcode_modifiers): Add JumpAbsolute entry.
 286         (operand_types): Remove JumpAbsolute entry.
 287         * i386-opc.h (JumpAbsolute): Move between enums.
 288         (struct i386_opcode_modifier): Add jumpabsolute field.
 289         (union i386_operand_type): Remove jumpabsolute field.
 290         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 291         * i386-init.h, i386-tbl.h: Re-generate.
 292
 293 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 294
 295         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 296         (operand_types): Remove AnySize entry.
 297         * i386-opc.h (AnySize): Move between enums.
 298         (struct i386_opcode_modifier): Add anysize field.
 299         (OTUnused): Un-comment.
 300         (union i386_operand_type): Remove anysize field.
 301         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 302         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 303         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 304         AnySize.
 305         * i386-tbl.h: Re-generate.
 306
 307 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 308
 309         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 310         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 311         use the floating point register (FPR).
 312
 313 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 314
 315         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 316         cmode 1101.
 317         (is_mve_encoding_conflict): Update cmode conflict checks for
 318         MVE_VMVN_IMM.
 319
 320 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 321
 322         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 323         entry.
 324         (operand_types): Remove EsSeg entry.
 325         (main): Replace stale use of OTMax.
 326         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 327         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 328         (EsSeg): Delete.
 329         (OTUnused): Comment out.
 330         (union i386_operand_type): Remove esseg field.
 331         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 332         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 333         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 334         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 335         * i386-init.h, i386-tbl.h: Re-generate.
 336
 337 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 338
 339         * i386-gen.c (operand_instances): Add RegB entry.
 340         * i386-opc.h (enum operand_instance): Add RegB.
 341         * i386-opc.tbl (RegC, RegD, RegB): Define.
 342         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 343         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 344         monitorx, mwaitx): Drop ImmExt and convert encodings
 345         accordingly.
 346         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 347         (edx, rdx): Add Instance=RegD.
 348         (ebx, rbx): Add Instance=RegB.
 349         * i386-tbl.h: Re-generate.
 350
 351 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 352
 353         * i386-gen.c (operand_type_init): Adjust
 354         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 355         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 356         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 357         (operand_instances): New.
 358         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 359         (output_operand_type): New parameter "instance". Process it.
 360         (process_i386_operand_type): New local variable "instance".
 361         (main): Adjust static assertions.
 362         * i386-opc.h (INSTANCE_WIDTH): Define.
 363         (enum operand_instance): New.
 364         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 365         (union i386_operand_type): Replace acc, inoutportreg, and
 366         shiftcount by instance.
 367         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 368         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 369         Add Instance=.
 370         * i386-init.h, i386-tbl.h: Re-generate.
 371
 372 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 373
 374         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 375         smaxp/sminp entries' "tied_operand" field to 2.
 376
 377 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 378
 379         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 380         "index" local variable by that of the already existing "num".
 381
 382 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 383
 384         PR gas/25167
 385         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 386         * i386-tbl.h: Regenerated.
 387
 388 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 389
 390         * i386-gen.c (operand_type_init): Add Class= to
 391         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 392         OPERAND_TYPE_REGBND entry.
 393         (operand_classes): Add RegMask and RegBND entries.
 394         (operand_types): Drop RegMask and RegBND entry.
 395         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 396         (RegMask, RegBND): Delete.
 397         (union i386_operand_type): Remove regmask and regbnd fields.
 398         * i386-opc.tbl (RegMask, RegBND): Define.
 399         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 400         Class=RegBND.
 401         * i386-init.h, i386-tbl.h: Re-generate.
 402
 403 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 404
 405         * i386-gen.c (operand_type_init): Add Class= to
 406         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 407         OPERAND_TYPE_REGZMM entries.
 408         (operand_classes): Add RegMMX and RegSIMD entries.
 409         (operand_types): Drop RegMMX and RegSIMD entries.
 410         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 411         (RegMMX, RegSIMD): Delete.
 412         (union i386_operand_type): Remove regmmx and regsimd fields.
 413         * i386-opc.tbl (RegMMX): Define.
 414         (RegXMM, RegYMM, RegZMM): Add Class=.
 415         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 416         Class=RegSIMD.
 417         * i386-init.h, i386-tbl.h: Re-generate.
 418
 419 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 420
 421         * i386-gen.c (operand_type_init): Add Class= to
 422         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 423         entries.
 424         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 425         (operand_types): Drop Control, Debug, and Test entries.
 426         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 427         (Control, Debug, Test): Delete.
 428         (union i386_operand_type): Remove control, debug, and test
 429         fields.
 430         * i386-opc.tbl (Control, Debug, Test): Define.
 431         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 432         Class=RegDR, and Test by Class=RegTR.
 433         * i386-init.h, i386-tbl.h: Re-generate.
 434
 435 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 436
 437         * i386-gen.c (operand_type_init): Add Class= to
 438         OPERAND_TYPE_SREG entry.
 439         (operand_classes): Add SReg entry.
 440         (operand_types): Drop SReg entry.
 441         * i386-opc.h (enum operand_class): Add SReg.
 442         (SReg): Delete.
 443         (union i386_operand_type): Remove sreg field.
 444         * i386-opc.tbl (SReg): Define.
 445         * i386-reg.tbl: Replace SReg by Class=SReg.
 446         * i386-init.h, i386-tbl.h: Re-generate.
 447
 448 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 449
 450         * i386-gen.c (operand_type_init): Add Class=. New
 451         OPERAND_TYPE_ANYIMM entry.
 452         (operand_classes): New.
 453         (operand_types): Drop Reg entry.
 454         (output_operand_type): New parameter "class". Process it.
 455         (process_i386_operand_type): New local variable "class".
 456         (main): Adjust static assertions.
 457         * i386-opc.h (CLASS_WIDTH): Define.
 458         (enum operand_class): New.
 459         (Reg): Replace by Class. Adjust comment.
 460         (union i386_operand_type): Replace reg by class.
 461         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 462         Class=.
 463         * i386-reg.tbl: Replace Reg by Class=Reg.
 464         * i386-init.h: Re-generate.
 465
 466 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 467
 468         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 469         (aarch64_opcode_table): Add data gathering hint mnemonic.
 470         * opcodes/aarch64-dis-2.c: Account for new instruction.
 471
 472 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 473
 474         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 475
 476
 477 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 478
 479         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 480         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 481         aarch64_feature_f64mm): New feature sets.
 482         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 483         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 484         instructions.
 485         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 486         macros.
 487         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 488         (OP_SVE_QQQ): New qualifier.
 489         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 490         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 491         the movprfx constraint.
 492         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 493         (aarch64_opcode_table): Define new instructions smmla,
 494         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 495         uzip{1/2}, trn{1/2}.
 496         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 497         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 498         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 499         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 500         Account for new instructions.
 501         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 502         S4x32 operand.
 503         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 504
 505 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 506 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 507
 508         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 509         Armv8.6-A.
 510         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 511         (neon_opcodes): Add bfloat SIMD instructions.
 512         (print_insn_coprocessor): Add new control character %b to print
 513         condition code without checking cp_num.
 514         (print_insn_neon): Account for BFloat16 instructions that have no
 515         special top-byte handling.
 516
 517 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 518 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 519
 520         * arm-dis.c (print_insn_coprocessor,
 521         print_insn_generic_coprocessor): Create wrapper functions around
 522         the implementation of the print_insn_coprocessor control codes.
 523         (print_insn_coprocessor_1): Original print_insn_coprocessor
 524         function that now takes which array to look at as an argument.
 525         (print_insn_arm): Use both print_insn_coprocessor and
 526         print_insn_generic_coprocessor.
 527         (print_insn_thumb32): As above.
 528
 529 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 530 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 531
 532         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 533         in reglane special case.
 534         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 535         aarch64_find_next_opcode): Account for new instructions.
 536         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 537         in reglane special case.
 538         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 539         new AARCH64_OPND_QLF_S_2H qualifier.
 540         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 541         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 542         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 543         sets.
 544         (BFLOAT_SVE, BFLOAT): New feature set macros.
 545         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 546         instructions.
 547         (aarch64_opcode_table): Define new instructions bfdot,
 548         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 549         bfcvtn2, bfcvt.
 550
 551 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 552 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 553
 554         * aarch64-tbl.h (ARMV8_6): New macro.
 555
 556 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 557
 558         * i386-dis.c (prefix_table): Add mcommit.
 559         (rm_table): Add rdpru.
 560         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 561         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 562         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 563         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 564         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 565         * i386-opc.tbl (mcommit, rdpru): New.
 566         * i386-init.h, i386-tbl.h: Re-generate.
 567
 568 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 569
 570         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 571         "names32" instead.
 572         (OP_Monitor): Drop local variable "op1_names", re-purpose
 573         "names" for it instead, and replace former "names" uses by
 574         "names32" ones.
 575
 576 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 577
 578         PR/gas 25167
 579         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 580         operand-less forms.
 581         * opcodes/i386-tbl.h: Re-generate.
 582
 583 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 584
 585         * i386-dis.c (OP_Mwaitx): Delete.
 586         (prefix_table): Use OP_Mwait for mwaitx entry.
 587         (OP_Mwait): Also handle mwaitx.
 588
 589 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 590
 591         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 592         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 593         (prefix_table): Add respective entries.
 594         (rm_table): Link to those entries.
 595
 596 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 597
 598         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 599         (REG_0F1C_P_0_MOD_0): ... this.
 600         (REG_0F1E_MOD_3): Rename to ...
 601         (REG_0F1E_P_1_MOD_3): ... this.
 602         (RM_0F01_REG_5): Rename to ...
 603         (RM_0F01_REG_5_MOD_3): ... this.
 604         (RM_0F01_REG_7): Rename to ...
 605         (RM_0F01_REG_7_MOD_3): ... this.
 606         (RM_0F1E_MOD_3_REG_7): Rename to ...
 607         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 608         (RM_0FAE_REG_6): Rename to ...
 609         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 610         (RM_0FAE_REG_7): Rename to ...
 611         (RM_0FAE_REG_7_MOD_3): ... this.
 612         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 613         (PREFIX_0F01_REG_5_MOD_0): ... this.
 614         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 615         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 616         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 617         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 618         (PREFIX_0FAE_REG_0): Rename to ...
 619         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 620         (PREFIX_0FAE_REG_1): Rename to ...
 621         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 622         (PREFIX_0FAE_REG_2): Rename to ...
 623         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 624         (PREFIX_0FAE_REG_3): Rename to ...
 625         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 626         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 627         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 628         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 629         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 630         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 631         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 632         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 633         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 634         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 635         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 636         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 637         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 638         (PREFIX_0FAE_REG_7): Rename to ...
 639         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 640         (PREFIX_MOD_0_0FC3): Rename to ...
 641         (PREFIX_0FC3_MOD_0): ... this.
 642         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 643         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 644         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 645         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 646         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 647         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 648         (reg_table, prefix_table, mod_table, rm_table): Adjust
 649         accordingly.
 650
 651 2019-11-04  Nick Clifton  <nickc@redhat.com>
 652
 653         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 654         of a v850 system register.  Move the v850_sreg_names array into
 655         this function.
 656         (get_v850_reg_name): Likewise for ordinary register names.
 657         (get_v850_vreg_name): Likewise for vector register names.
 658         (get_v850_cc_name): Likewise for condition codes.
 659         * get_v850_float_cc_name): Likewise for floating point condition
 660         codes.
 661         (get_v850_cacheop_name): Likewise for cache-ops.
 662         (get_v850_prefop_name): Likewise for pref-ops.
 663         (disassemble): Use the new accessor functions.
 664
 665 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 666
 667         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 668         immediate for the writeback form of ldraa/ldrab if it is 0.
 669         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 670         * aarch64-opc-2.c: Regenerated.
 671
 672 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 673
 674         * i386-gen.c (operand_type_shorthands): Delete.
 675         (operand_type_init): Expand previous shorthands.
 676         (set_bitfield_from_shorthand): Rename back to ...
 677         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 678         of operand_type_init[].
 679         (set_bitfield): Adjust call to the above function.
 680         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 681         RegXMM, RegYMM, RegZMM): Define.
 682         * i386-reg.tbl: Expand prior shorthands.
 683
 684 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 685
 686         * i386-gen.c (output_i386_opcode): Change order of fields
 687         emitted to output.
 688         * i386-opc.h (struct insn_template): Move operands field.
 689         Convert extension_opcode field to unsigned short.
 690         * i386-tbl.h: Re-generate.
 691
 692 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 693
 694         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 695         of W.
 696         * i386-opc.h (W): Extend comment.
 697         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 698         general purpose variants not allowing for byte operands.
 699         * i386-tbl.h: Re-generate.
 700
 701 2019-10-29  Nick Clifton  <nickc@redhat.com>
 702
 703         * tic30-dis.c (print_branch): Correct size of operand array.
 704
 705 2019-10-29  Nick Clifton  <nickc@redhat.com>
 706
 707         * d30v-dis.c (print_insn): Check that operand index is valid
 708         before attempting to access the operands array.
 709
 710 2019-10-29  Nick Clifton  <nickc@redhat.com>
 711
 712         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 713         locating the bit to be tested.
 714
 715 2019-10-29  Nick Clifton  <nickc@redhat.com>
 716
 717         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 718         values.
 719         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 720         (print_insn_s12z):  Check for illegal size values.
 721
 722 2019-10-28  Nick Clifton  <nickc@redhat.com>
 723
 724         * csky-dis.c (csky_chars_to_number): Check for a negative
 725         count. Use an unsigned integer to construct the return value.
 726
 727 2019-10-28  Nick Clifton  <nickc@redhat.com>
 728
 729         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 730         operand buffer.  Set value to 15 not 13.
 731         (get_register_operand): Use OPERAND_BUFFER_LEN.
 732         (get_indirect_operand): Likewise.
 733         (print_two_operand): Likewise.
 734         (print_three_operand): Likewise.
 735         (print_oar_insn): Likewise.
 736
 737 2019-10-28  Nick Clifton  <nickc@redhat.com>
 738
 739         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 740         (bit_extract_simple): Likewise.
 741         (bit_copy): Likewise.
 742         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 743         index_offset array are not accessed.
 744
 745 2019-10-28  Nick Clifton  <nickc@redhat.com>
 746
 747         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 748         operand.
 749
 750 2019-10-25  Nick Clifton  <nickc@redhat.com>
 751
 752         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 753         access to opcodes.op array element.
 754
 755 2019-10-23  Nick Clifton  <nickc@redhat.com>
 756
 757         * rx-dis.c (get_register_name): Fix spelling typo in error
 758         message.
 759         (get_condition_name, get_flag_name, get_double_register_name)
 760         (get_double_register_high_name, get_double_register_low_name)
 761         (get_double_control_register_name, get_double_condition_name)
 762         (get_opsize_name, get_size_name): Likewise.
 763
 764 2019-10-22  Nick Clifton  <nickc@redhat.com>
 765
 766         * rx-dis.c (get_size_name): New function.  Provides safe
 767         access to name array.
 768         (get_opsize_name): Likewise.
 769         (print_insn_rx): Use the accessor functions.
 770
 771 2019-10-16  Nick Clifton  <nickc@redhat.com>
 772
 773         * rx-dis.c (get_register_name): New function.  Provides safe
 774         access to name array.
 775         (get_condition_name, get_flag_name, get_double_register_name)
 776         (get_double_register_high_name, get_double_register_low_name)
 777         (get_double_control_register_name, get_double_condition_name):
 778         Likewise.
 779         (print_insn_rx): Use the accessor functions.
 780
 781 2019-10-09  Nick Clifton  <nickc@redhat.com>
 782
 783         PR 25041
 784         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 785         instructions.
 786
 787 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 788
 789         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 790         (cmpsd): Likewise. Move EsSeg to other operand.
 791         * opcodes/i386-tbl.h: Re-generate.
 792
 793 2019-09-23  Alan Modra  <amodra@gmail.com>
 794
 795         * m68k-dis.c: Include cpu-m68k.h
 796
 797 2019-09-23  Alan Modra  <amodra@gmail.com>
 798
 799         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 800         "elf/mips.h" earlier.
 801
 802 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 803
 804         PR gas/25012
 805         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 806         with SReg operand.
 807         * i386-tbl.h: Re-generate.
 808
 809 2019-09-18  Alan Modra  <amodra@gmail.com>
 810
 811         * arc-ext.c: Update throughout for bfd section macro changes.
 812
 813 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 814
 815         * Makefile.in: Re-generate.
 816         * configure: Re-generate.
 817
 818 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 819
 820         * riscv-opc.c (riscv_opcodes): Change subset field
 821         to insn_class field for all instructions.
 822         (riscv_insn_types): Likewise.
 823
 824 2019-09-16  Phil Blundell  <pb@pbcl.net>
 825
 826         * configure: Regenerated.
 827
 828 2019-09-10  Miod Vallat  <miod@online.fr>
 829
 830         PR 24982
 831         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 832
 833 2019-09-09  Phil Blundell  <pb@pbcl.net>
 834
 835         binutils 2.33 branch created.
 836
 837 2019-09-03  Nick Clifton  <nickc@redhat.com>
 838
 839         PR 24961
 840         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 841         greater than zero before indexing via (bufcnt -1).
 842
 843 2019-09-03  Nick Clifton  <nickc@redhat.com>
 844
 845         PR 24958
 846         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 847         (MAX_SPEC_REG_NAME_LEN): Define.
 848         (struct mmix_dis_info): Use defined constants for array lengths.
 849         (get_reg_name): New function.
 850         (get_sprec_reg_name): New function.
 851         (print_insn_mmix): Use new functions.
 852
 853 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 854
 855         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 856         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 857         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 858
 859 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 860
 861         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 862         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 863         (aarch64_sys_reg_supported_p): Update checks for the above.
 864
 865 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 866
 867         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 868         cases MVE_SQRSHRL and MVE_UQRSHLL.
 869         (print_insn_mve): Add case for specifier 'k' to check
 870         specific bit of the instruction.
 871
 872 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 873
 874         PR 24854
 875         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 876         encountering an unknown machine type.
 877         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 878         cases return -1 rather than calling abort.
 879
 880 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 881
 882         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 883         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 884         IgnoreSize.
 885         * i386-tbl.h: Re-generate.
 886
 887 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 888
 889         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 890         instructions.
 891
 892 2019-07-30  Mel Chen <mel.chen@sifive.com>
 893
 894         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 895         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 896
 897         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 898         fscsr.
 899
 900 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 901
 902         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 903         and MPY class instructions.
 904         (parse_option): Add nps400 option.
 905         (print_arc_disassembler_options): Add nps400 info.
 906
 907 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 908
 909         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 910         (bspop): Likewise.
 911         (modapp): Likewise.
 912         * arc-opc.c (RAD_CHK): Add.
 913         * arc-tbl.h: Regenerate.
 914
 915 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 916
 917         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 918         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 919
 920 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 921
 922         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 923         instructions as UNPREDICTABLE.
 924
 925 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 926
 927         * bpf-desc.c: Regenerated.
 928
 929 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 930
 931         * i386-gen.c (static_assert): Define.
 932         (main): Use it.
 933         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 934         (Opcode_Modifier_Num): ... this.
 935         (Mem): Delete.
 936
 937 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 938
 939         * i386-gen.c (operand_types): Move RegMem ...
 940         (opcode_modifiers): ... here.
 941         * i386-opc.h (RegMem): Move to opcode modifer enum.
 942         (union i386_operand_type): Move regmem field ...
 943         (struct i386_opcode_modifier): ... here.
 944         * i386-opc.tbl (RegMem): Define.
 945         (mov, movq): Move RegMem on segment, control, debug, and test
 946         register flavors.
 947         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 948         to non-SSE2AVX flavor.
 949         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 950         Move RegMem on register only flavors. Drop IgnoreSize from
 951         legacy encoding flavors.
 952         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 953         flavors.
 954         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 955         register only flavors.
 956         (vmovd): Move RegMem and drop IgnoreSize on register only
 957         flavor. Change opcode and operand order to store form.
 958         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 959
 960 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 961
 962         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 963         entries.
 964         * i386-opc.h (SReg2, SReg3): Replace by ...
 965         (SReg): ... this.
 966         (union i386_operand_type): Replace sreg fields.
 967         * i386-opc.tbl (mov, ): Use SReg.
 968         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 969         register flavors.
 970         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 971         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 972
 973 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 974
 975         * bpf-desc.c: Regenerate.
 976         * bpf-opc.c: Likewise.
 977         * bpf-opc.h: Likewise.
 978
 979 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 980
 981         * bpf-desc.c: Regenerate.
 982         * bpf-opc.c: Likewise.
 983
 984 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 985
 986         * arm-dis.c (print_insn_coprocessor): Rename index to
 987         index_operand.
 988
 989 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 990
 991         * riscv-opc.c (riscv_insn_types): Add r4 type.
 992
 993         * riscv-opc.c (riscv_insn_types): Add b and j type.
 994
 995         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 996         format for sb type and correct s type.
 997
 998 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 999
1000         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1001         SVE FMOV alias of FCPY.
1002
1003 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1004
1005         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1006         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1007
1008 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1009
1010         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1011         registers in an instruction prefixed by MOVPRFX.
1012
1013 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
1014
1015         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1016         sve_size_13 icode to account for variant behaviour of
1017         pmull{t,b}.
1018         * aarch64-dis-2.c: Regenerate.
1019         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1020         sve_size_13 icode to account for variant behaviour of
1021         pmull{t,b}.
1022         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1023         (OP_SVE_VVV_Q_D): Add new qualifier.
1024         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1025         (struct aarch64_opcode): Split pmull{t,b} into those requiring
1026         AES and those not.
1027
1028 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1029
1030         * opcodes/i386-gen.c (operand_type_init): Remove
1031         OPERAND_TYPE_VEC_IMM4 entry.
1032         (operand_types): Remove Vec_Imm4.
1033         * opcodes/i386-opc.h (Vec_Imm4): Delete.
1034         (union i386_operand_type): Remove vec_imm4.
1035         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1036         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1037
1038 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1039
1040         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1041         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1042         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1043         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1044         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1045         monitorx, mwaitx): Drop ImmExt from operand-less forms.
1046         * i386-tbl.h: Re-generate.
1047
1048 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1049
1050         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1051         register operands.
1052         * i386-tbl.h: Re-generate.
1053
1054 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1055
1056         * i386-opc.tbl (C): New.
1057         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1058         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1059         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1060         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1061         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1062         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1063         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1064         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1065         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1066         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1067         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1068         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1069         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1070         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1071         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1072         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1073         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1074         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1075         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1076         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1077         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1078         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1079         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1080         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1081         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1082         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1083         flavors.
1084         * i386-tbl.h: Re-generate.
1085
1086 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1087
1088         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1089         register operands.
1090         * i386-tbl.h: Re-generate.
1091
1092 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1093
1094         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1095         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1096         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1097         * i386-tbl.h: Re-generate.
1098
1099 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1100
1101         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1102         Disp8MemShift from register only templates.
1103         * i386-tbl.h: Re-generate.
1104
1105 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1106
1107         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1108         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1109         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1110         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1111         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1112         EVEX_W_0F11_P_3_M_1): Delete.
1113         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1114         EVEX_W_0F11_P_3): New.
1115         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1116         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1117         MOD_EVEX_0F11_PREFIX_3 table entries.
1118         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1119         PREFIX_EVEX_0F11 table entries.
1120         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1121         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1122         EVEX_W_0F11_P_3_M_{0,1} table entries.
1123
1124 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1125
1126         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1127         Delete.
1128
1129 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1130
1131         PR binutils/24719
1132         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1133         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1134         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1135         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1136         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1137         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1138         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1139         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1140         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1141         PREFIX_EVEX_0F38C6_REG_6 entries.
1142         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1143         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1144         EVEX_W_0F38C7_R_6_P_2 entries.
1145         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1146         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1147         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1148         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1149         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1150         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1151         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1152
1153 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1154
1155         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1156         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1157         VEX_LEN_0F2D_P_3): Delete.
1158         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1159         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1160         (prefix_table): ... here.
1161
1162 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1163
1164         * i386-dis.c (Iq): Delete.
1165         (Id): New.
1166         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1167         TBM insns.
1168         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1169         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1170         (OP_E_memory): Also honor needindex when deciding whether an
1171         address size prefix needs printing.
1172         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1173
1174 2019-06-26  Jim Wilson  <jimw@sifive.com>
1175
1176         PR binutils/24739
1177         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1178         Set info->display_endian to info->endian_code.
1179
1180 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1181
1182         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1183         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1184         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1185         OPERAND_TYPE_ACC64 entries.
1186         * i386-init.h: Re-generate.
1187
1188 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1189
1190         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1191         Delete.
1192         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1193         of dqa_mode.
1194         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1195         entries here.
1196         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1197         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1198
1199 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1200
1201         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1202         variables.
1203
1204 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1205
1206         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1207         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1208         movnti.
1209         * i386-opc.tbl (movnti): Add IgnoreSize.
1210         * i386-tbl.h: Re-generate.
1211
1212 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1213
1214         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1215         * i386-tbl.h: Re-generate.
1216
1217 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1218
1219         * i386-dis-evex.h: Break into ...
1220         * i386-dis-evex-len.h: New file.
1221         * i386-dis-evex-mod.h: Likewise.
1222         * i386-dis-evex-prefix.h: Likewise.
1223         * i386-dis-evex-reg.h: Likewise.
1224         * i386-dis-evex-w.h: Likewise.
1225         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1226         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1227         i386-dis-evex-mod.h.
1228
1229 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1230
1231         PR binutils/24700
1232         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1233         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1234         EVEX_W_0F385B_P_2.
1235         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1236         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1237         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1238         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1239         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1240         EVEX_LEN_0F385B_P_2_W_1.
1241         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1242         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1243         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1244         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1245         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1246         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1247         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1248         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1249         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1250         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1251
1252 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1253
1254         PR binutils/24691
1255         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1256         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1257         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1258         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1259         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1260         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1261         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1262         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1263         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1264         EVEX_LEN_0F3A43_P_2_W_1.
1265         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1266         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1267         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1268         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1269         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1270         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1271         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1272         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1273         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1274         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1275         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1276         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1277
1278 2019-06-14  Nick Clifton  <nickc@redhat.com>
1279
1280         * po/fr.po; Updated French translation.
1281
1282 2019-06-13  Stafford Horne  <shorne@gmail.com>
1283
1284         * or1k-asm.c: Regenerated.
1285         * or1k-desc.c: Regenerated.
1286         * or1k-desc.h: Regenerated.
1287         * or1k-dis.c: Regenerated.
1288         * or1k-ibld.c: Regenerated.
1289         * or1k-opc.c: Regenerated.
1290         * or1k-opc.h: Regenerated.
1291         * or1k-opinst.c: Regenerated.
1292
1293 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1294
1295         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1296
1297 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1298
1299         PR binutils/24633
1300         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1301         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1302         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1303         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1304         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1305         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1306         EVEX_LEN_0F3A1B_P_2_W_1.
1307         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1308         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1309         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1310         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1311         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1312         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1313         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1314         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1315
1316 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1317
1318         PR binutils/24626
1319         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1320         EVEX.vvvv when disassembling VEX and EVEX instructions.
1321         (OP_VEX): Set vex.register_specifier to 0 after readding
1322         vex.register_specifier.
1323         (OP_Vex_2src_1): Likewise.
1324         (OP_Vex_2src_2): Likewise.
1325         (OP_LWP_E): Likewise.
1326         (OP_EX_Vex): Don't check vex.register_specifier.
1327         (OP_XMM_Vex): Likewise.
1328
1329 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1330             Lili Cui  <lili.cui@intel.com>
1331
1332         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1333         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1334         instructions.
1335         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1336         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1337         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1338         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1339         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1340         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1341         * i386-init.h: Regenerated.
1342         * i386-tbl.h: Likewise.
1343
1344 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1345             Lili Cui  <lili.cui@intel.com>
1346
1347         * doc/c-i386.texi: Document enqcmd.
1348         * testsuite/gas/i386/enqcmd-intel.d: New file.
1349         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1350         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1351         * testsuite/gas/i386/enqcmd.d: Likewise.
1352         * testsuite/gas/i386/enqcmd.s: Likewise.
1353         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1354         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1355         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1356         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1357         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1358         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1359         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1360         and x86-64-enqcmd.
1361
1362 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1363
1364         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1365
1366 2019-06-03  Alan Modra  <amodra@gmail.com>
1367
1368         * ppc-dis.c (prefix_opcd_indices): Correct size.
1369
1370 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1371
1372         PR gas/24625
1373         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1374         Disp8ShiftVL.
1375         * i386-tbl.h: Regenerated.
1376
1377 2019-05-24  Alan Modra  <amodra@gmail.com>
1378
1379         * po/POTFILES.in: Regenerate.
1380
1381 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1382             Alan Modra  <amodra@gmail.com>
1383
1384         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1385         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1386         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1387         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1388         XTOP>): Define and add entries.
1389         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1390         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1391         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1392         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1393
1394 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1395             Alan Modra  <amodra@gmail.com>
1396
1397         * ppc-dis.c (ppc_opts): Add "future" entry.
1398         (PREFIX_OPCD_SEGS): Define.
1399         (prefix_opcd_indices): New array.
1400         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1401         (lookup_prefix): New function.
1402         (print_insn_powerpc): Handle 64-bit prefix instructions.
1403         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1404         (PMRR, POWERXX): Define.
1405         (prefix_opcodes): New instruction table.
1406         (prefix_num_opcodes): New constant.
1407
1408 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1409
1410         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1411         * configure: Regenerated.
1412         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1413         and cpu/bpf.opc.
1414         (HFILES): Add bpf-desc.h and bpf-opc.h.
1415         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1416         bpf-ibld.c and bpf-opc.c.
1417         (BPF_DEPS): Define.
1418         * Makefile.in: Regenerated.
1419         * disassemble.c (ARCH_bpf): Define.
1420         (disassembler): Add case for bfd_arch_bpf.
1421         (disassemble_init_for_target): Likewise.
1422         (enum epbf_isa_attr): Define.
1423         * disassemble.h: extern print_insn_bpf.
1424         * bpf-asm.c: Generated.
1425         * bpf-opc.h: Likewise.
1426         * bpf-opc.c: Likewise.
1427         * bpf-ibld.c: Likewise.
1428         * bpf-dis.c: Likewise.
1429         * bpf-desc.h: Likewise.
1430         * bpf-desc.c: Likewise.
1431
1432 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1433
1434         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1435         and VMSR with the new operands.
1436
1437 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1438
1439         * arm-dis.c (enum mve_instructions): New enum
1440         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1441         and cneg.
1442         (mve_opcodes): New instructions as above.
1443         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1444         csneg and csel.
1445         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1446
1447 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1448
1449         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1450         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1451         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1452         uqshl, urshrl and urshr.
1453         (is_mve_okay_in_it): Add new instructions to TRUE list.
1454         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1455         (print_insn_mve): Updated to accept new %j,
1456         %<bitfield>m and %<bitfield>n patterns.
1457
1458 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1459
1460         * mips-opc.c (mips_builtin_opcodes): Change source register
1461         constraint for DAUI.
1462
1463 2019-05-20  Nick Clifton  <nickc@redhat.com>
1464
1465         * po/fr.po: Updated French translation.
1466
1467 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1468             Michael Collison <michael.collison@arm.com>
1469
1470         * arm-dis.c (thumb32_opcodes): Add new instructions.
1471         (enum mve_instructions): Likewise.
1472         (enum mve_undefined): Add new reasons.
1473         (is_mve_encoding_conflict): Handle new instructions.
1474         (is_mve_undefined): Likewise.
1475         (is_mve_unpredictable): Likewise.
1476         (print_mve_undefined): Likewise.
1477         (print_mve_size): Likewise.
1478
1479 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1480             Michael Collison <michael.collison@arm.com>
1481
1482         * arm-dis.c (thumb32_opcodes): Add new instructions.
1483         (enum mve_instructions): Likewise.
1484         (is_mve_encoding_conflict): Handle new instructions.
1485         (is_mve_undefined): Likewise.
1486         (is_mve_unpredictable): Likewise.
1487         (print_mve_size): Likewise.
1488
1489 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1490             Michael Collison <michael.collison@arm.com>
1491
1492         * arm-dis.c (thumb32_opcodes): Add new instructions.
1493         (enum mve_instructions): Likewise.
1494         (is_mve_encoding_conflict): Likewise.
1495         (is_mve_unpredictable): Likewise.
1496         (print_mve_size): Likewise.
1497
1498 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1499             Michael Collison <michael.collison@arm.com>
1500
1501         * arm-dis.c (thumb32_opcodes): Add new instructions.
1502         (enum mve_instructions): Likewise.
1503         (is_mve_encoding_conflict): Handle new instructions.
1504         (is_mve_undefined): Likewise.
1505         (is_mve_unpredictable): Likewise.
1506         (print_mve_size): Likewise.
1507
1508 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1509             Michael Collison <michael.collison@arm.com>
1510
1511         * arm-dis.c (thumb32_opcodes): Add new instructions.
1512         (enum mve_instructions): Likewise.
1513         (is_mve_encoding_conflict): Handle new instructions.
1514         (is_mve_undefined): Likewise.
1515         (is_mve_unpredictable): Likewise.
1516         (print_mve_size): Likewise.
1517         (print_insn_mve): Likewise.
1518
1519 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1520             Michael Collison <michael.collison@arm.com>
1521
1522         * arm-dis.c (thumb32_opcodes): Add new instructions.
1523         (print_insn_thumb32): Handle new instructions.
1524
1525 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1526             Michael Collison <michael.collison@arm.com>
1527
1528         * arm-dis.c (enum mve_instructions): Add new instructions.
1529         (enum mve_undefined): Add new reasons.
1530         (is_mve_encoding_conflict): Handle new instructions.
1531         (is_mve_undefined): Likewise.
1532         (is_mve_unpredictable): Likewise.
1533         (print_mve_undefined): Likewise.
1534         (print_mve_size): Likewise.
1535         (print_mve_shift_n): Likewise.
1536         (print_insn_mve): Likewise.
1537
1538 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1539             Michael Collison <michael.collison@arm.com>
1540
1541         * arm-dis.c (enum mve_instructions): Add new instructions.
1542         (is_mve_encoding_conflict): Handle new instructions.
1543         (is_mve_unpredictable): Likewise.
1544         (print_mve_rotate): Likewise.
1545         (print_mve_size): Likewise.
1546         (print_insn_mve): Likewise.
1547
1548 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1549             Michael Collison <michael.collison@arm.com>
1550
1551         * arm-dis.c (enum mve_instructions): Add new instructions.
1552         (is_mve_encoding_conflict): Handle new instructions.
1553         (is_mve_unpredictable): Likewise.
1554         (print_mve_size): Likewise.
1555         (print_insn_mve): Likewise.
1556
1557 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1558             Michael Collison <michael.collison@arm.com>
1559
1560         * arm-dis.c (enum mve_instructions): Add new instructions.
1561         (enum mve_undefined): Add new reasons.
1562         (is_mve_encoding_conflict): Handle new instructions.
1563         (is_mve_undefined): Likewise.
1564         (is_mve_unpredictable): Likewise.
1565         (print_mve_undefined): Likewise.
1566         (print_mve_size): Likewise.
1567         (print_insn_mve): Likewise.
1568
1569 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1570             Michael Collison <michael.collison@arm.com>
1571
1572         * arm-dis.c (enum mve_instructions): Add new instructions.
1573         (is_mve_encoding_conflict): Handle new instructions.
1574         (is_mve_undefined): Likewise.
1575         (is_mve_unpredictable): Likewise.
1576         (print_mve_size): Likewise.
1577         (print_insn_mve): Likewise.
1578
1579 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1580             Michael Collison <michael.collison@arm.com>
1581
1582         * arm-dis.c (enum mve_instructions): Add new instructions.
1583         (enum mve_unpredictable): Add new reasons.
1584         (enum mve_undefined): Likewise.
1585         (is_mve_okay_in_it): Handle new isntructions.
1586         (is_mve_encoding_conflict): Likewise.
1587         (is_mve_undefined): Likewise.
1588         (is_mve_unpredictable): Likewise.
1589         (print_mve_vmov_index): Likewise.
1590         (print_simd_imm8): Likewise.
1591         (print_mve_undefined): Likewise.
1592         (print_mve_unpredictable): Likewise.
1593         (print_mve_size): Likewise.
1594         (print_insn_mve): Likewise.
1595
1596 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1597             Michael Collison <michael.collison@arm.com>
1598
1599         * arm-dis.c (enum mve_instructions): Add new instructions.
1600         (enum mve_unpredictable): Add new reasons.
1601         (enum mve_undefined): Likewise.
1602         (is_mve_encoding_conflict): Handle new instructions.
1603         (is_mve_undefined): Likewise.
1604         (is_mve_unpredictable): Likewise.
1605         (print_mve_undefined): Likewise.
1606         (print_mve_unpredictable): Likewise.
1607         (print_mve_rounding_mode): Likewise.
1608         (print_mve_vcvt_size): Likewise.
1609         (print_mve_size): Likewise.
1610         (print_insn_mve): Likewise.
1611
1612 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1613             Michael Collison <michael.collison@arm.com>
1614
1615         * arm-dis.c (enum mve_instructions): Add new instructions.
1616         (enum mve_unpredictable): Add new reasons.
1617         (enum mve_undefined): Likewise.
1618         (is_mve_undefined): Handle new instructions.
1619         (is_mve_unpredictable): Likewise.
1620         (print_mve_undefined): Likewise.
1621         (print_mve_unpredictable): Likewise.
1622         (print_mve_size): Likewise.
1623         (print_insn_mve): Likewise.
1624
1625 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1626             Michael Collison <michael.collison@arm.com>
1627
1628         * arm-dis.c (enum mve_instructions): Add new instructions.
1629         (enum mve_undefined): Add new reasons.
1630         (insns): Add new instructions.
1631         (is_mve_encoding_conflict):
1632         (print_mve_vld_str_addr): New print function.
1633         (is_mve_undefined): Handle new instructions.
1634         (is_mve_unpredictable): Likewise.
1635         (print_mve_undefined): Likewise.
1636         (print_mve_size): Likewise.
1637         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1638         (print_insn_mve):  Handle new operands.
1639
1640 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1641             Michael Collison <michael.collison@arm.com>
1642
1643         * arm-dis.c (enum mve_instructions): Add new instructions.
1644         (enum mve_unpredictable): Add new reasons.
1645         (is_mve_encoding_conflict): Handle new instructions.
1646         (is_mve_unpredictable): Likewise.
1647         (mve_opcodes): Add new instructions.
1648         (print_mve_unpredictable): Handle new reasons.
1649         (print_mve_register_blocks): New print function.
1650         (print_mve_size): Handle new instructions.
1651         (print_insn_mve): Likewise.
1652
1653 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1654             Michael Collison <michael.collison@arm.com>
1655
1656         * arm-dis.c (enum mve_instructions): Add new instructions.
1657         (enum mve_unpredictable): Add new reasons.
1658         (enum mve_undefined): Likewise.
1659         (is_mve_encoding_conflict): Handle new instructions.
1660         (is_mve_undefined): Likewise.
1661         (is_mve_unpredictable): Likewise.
1662         (coprocessor_opcodes): Move NEON VDUP from here...
1663         (neon_opcodes): ... to here.
1664         (mve_opcodes): Add new instructions.
1665         (print_mve_undefined):  Handle new reasons.
1666         (print_mve_unpredictable): Likewise.
1667         (print_mve_size): Handle new instructions.
1668         (print_insn_neon): Handle vdup.
1669         (print_insn_mve): Handle new operands.
1670
1671 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1672             Michael Collison <michael.collison@arm.com>
1673
1674         * arm-dis.c (enum mve_instructions): Add new instructions.
1675         (enum mve_unpredictable): Add new values.
1676         (mve_opcodes): Add new instructions.
1677         (vec_condnames): New array with vector conditions.
1678         (mve_predicatenames): New array with predicate suffixes.
1679         (mve_vec_sizename): New array with vector sizes.
1680         (enum vpt_pred_state): New enum with vector predication states.
1681         (struct vpt_block): New struct type for vpt blocks.
1682         (vpt_block_state): Global struct to keep track of state.
1683         (mve_extract_pred_mask): New helper function.
1684         (num_instructions_vpt_block): Likewise.
1685         (mark_outside_vpt_block): Likewise.
1686         (mark_inside_vpt_block): Likewise.
1687         (invert_next_predicate_state): Likewise.
1688         (update_next_predicate_state): Likewise.
1689         (update_vpt_block_state): Likewise.
1690         (is_vpt_instruction): Likewise.
1691         (is_mve_encoding_conflict): Add entries for new instructions.
1692         (is_mve_unpredictable): Likewise.
1693         (print_mve_unpredictable): Handle new cases.
1694         (print_instruction_predicate): Likewise.
1695         (print_mve_size): New function.
1696         (print_vec_condition): New function.
1697         (print_insn_mve): Handle vpt blocks and new print operands.
1698
1699 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1700
1701         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1702         8, 14 and 15 for Armv8.1-M Mainline.
1703
1704 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1705             Michael Collison <michael.collison@arm.com>
1706
1707         * arm-dis.c (enum mve_instructions): New enum.
1708         (enum mve_unpredictable): Likewise.
1709         (enum mve_undefined): Likewise.
1710         (struct mopcode32): New struct.
1711         (is_mve_okay_in_it): New function.
1712         (is_mve_architecture): Likewise.
1713         (arm_decode_field): Likewise.
1714         (arm_decode_field_multiple): Likewise.
1715         (is_mve_encoding_conflict): Likewise.
1716         (is_mve_undefined): Likewise.
1717         (is_mve_unpredictable): Likewise.
1718         (print_mve_undefined): Likewise.
1719         (print_mve_unpredictable): Likewise.
1720         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1721         (print_insn_mve): New function.
1722         (print_insn_thumb32): Handle MVE architecture.
1723         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1724
1725 2019-05-10  Nick Clifton  <nickc@redhat.com>
1726
1727         PR 24538
1728         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1729         end of the table prematurely.
1730
1731 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1732
1733         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1734         macros for R6.
1735
1736 2019-05-11  Alan Modra  <amodra@gmail.com>
1737
1738         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1739         when -Mraw is in effect.
1740
1741 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1742
1743         * aarch64-dis-2.c: Regenerate.
1744         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1745         (OP_SVE_BBB): New variant set.
1746         (OP_SVE_DDDD): New variant set.
1747         (OP_SVE_HHH): New variant set.
1748         (OP_SVE_HHHU): New variant set.
1749         (OP_SVE_SSS): New variant set.
1750         (OP_SVE_SSSU): New variant set.
1751         (OP_SVE_SHH): New variant set.
1752         (OP_SVE_SBBU): New variant set.
1753         (OP_SVE_DSS): New variant set.
1754         (OP_SVE_DHHU): New variant set.
1755         (OP_SVE_VMV_HSD_BHS): New variant set.
1756         (OP_SVE_VVU_HSD_BHS): New variant set.
1757         (OP_SVE_VVVU_SD_BH): New variant set.
1758         (OP_SVE_VVVU_BHSD): New variant set.
1759         (OP_SVE_VVV_QHD_DBS): New variant set.
1760         (OP_SVE_VVV_HSD_BHS): New variant set.
1761         (OP_SVE_VVV_HSD_BHS2): New variant set.
1762         (OP_SVE_VVV_BHS_HSD): New variant set.
1763         (OP_SVE_VV_BHS_HSD): New variant set.
1764         (OP_SVE_VVV_SD): New variant set.
1765         (OP_SVE_VVU_BHS_HSD): New variant set.
1766         (OP_SVE_VZVV_SD): New variant set.
1767         (OP_SVE_VZVV_BH): New variant set.
1768         (OP_SVE_VZV_SD): New variant set.
1769         (aarch64_opcode_table): Add sve2 instructions.
1770
1771 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1772
1773         * aarch64-asm-2.c: Regenerated.
1774         * aarch64-dis-2.c: Regenerated.
1775         * aarch64-opc-2.c: Regenerated.
1776         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1777         for SVE_SHLIMM_UNPRED_22.
1778         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1779         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1780         operand.
1781
1782 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1783
1784         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1785         sve_size_tsz_bhs iclass encode.
1786         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1787         sve_size_tsz_bhs iclass decode.
1788
1789 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1790
1791         * aarch64-asm-2.c: Regenerated.
1792         * aarch64-dis-2.c: Regenerated.
1793         * aarch64-opc-2.c: Regenerated.
1794         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1795         for SVE_Zm4_11_INDEX.
1796         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1797         (fields): Handle SVE_i2h field.
1798         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1799         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1800
1801 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1802
1803         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1804         sve_shift_tsz_bhsd iclass encode.
1805         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1806         sve_shift_tsz_bhsd iclass decode.
1807
1808 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1809
1810         * aarch64-asm-2.c: Regenerated.
1811         * aarch64-dis-2.c: Regenerated.
1812         * aarch64-opc-2.c: Regenerated.
1813         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1814         (aarch64_encode_variant_using_iclass): Handle
1815         sve_shift_tsz_hsd iclass encode.
1816         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1817         sve_shift_tsz_hsd iclass decode.
1818         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1819         for SVE_SHRIMM_UNPRED_22.
1820         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1821         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1822         operand.
1823
1824 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1825
1826         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1827         sve_size_013 iclass encode.
1828         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1829         sve_size_013 iclass decode.
1830
1831 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1832
1833         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1834         sve_size_bh iclass encode.
1835         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1836         sve_size_bh iclass decode.
1837
1838 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1839
1840         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1841         sve_size_sd2 iclass encode.
1842         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1843         sve_size_sd2 iclass decode.
1844         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1845         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1846
1847 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1848
1849         * aarch64-asm-2.c: Regenerated.
1850         * aarch64-dis-2.c: Regenerated.
1851         * aarch64-opc-2.c: Regenerated.
1852         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1853         for SVE_ADDR_ZX.
1854         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1855         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1856
1857 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1858
1859         * aarch64-asm-2.c: Regenerated.
1860         * aarch64-dis-2.c: Regenerated.
1861         * aarch64-opc-2.c: Regenerated.
1862         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1863         for SVE_Zm3_11_INDEX.
1864         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1865         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1866         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1867         fields.
1868         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1869
1870 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1871
1872         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1873         sve_size_hsd2 iclass encode.
1874         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1875         sve_size_hsd2 iclass decode.
1876         * aarch64-opc.c (fields): Handle SVE_size field.
1877         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1878
1879 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1880
1881         * aarch64-asm-2.c: Regenerated.
1882         * aarch64-dis-2.c: Regenerated.
1883         * aarch64-opc-2.c: Regenerated.
1884         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1885         for SVE_IMM_ROT3.
1886         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1887         (fields): Handle SVE_rot3 field.
1888         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1889         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1890
1891 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1892
1893         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1894         instructions.
1895
1896 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1897
1898         * aarch64-tbl.h
1899         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1900         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1901         aarch64_feature_sve2bitperm): New feature sets.
1902         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1903         for feature set addresses.
1904         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1905         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1906
1907 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1908             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1909
1910         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1911         argument and set ASE_EVA_R6 appropriately.
1912         (set_default_mips_dis_options): Pass ISA to above.
1913         (parse_mips_dis_option): Likewise.
1914         * mips-opc.c (EVAR6): New macro.
1915         (mips_builtin_opcodes): Add llwpe, scwpe.
1916
1917 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1918
1919         * aarch64-asm-2.c: Regenerated.
1920         * aarch64-dis-2.c: Regenerated.
1921         * aarch64-opc-2.c: Regenerated.
1922         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1923         AARCH64_OPND_TME_UIMM16.
1924         (aarch64_print_operand): Likewise.
1925         * aarch64-tbl.h (QL_IMM_NIL): New.
1926         (TME): New.
1927         (_TME_INSN): New.
1928         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1929
1930 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1931
1932         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1933
1934 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1935             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1936
1937         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1938
1939 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1940
1941         * s12z-opc.h: Add extern "C" bracketing to help
1942         users who wish to use this interface in c++ code.
1943
1944 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1945
1946         * s12z-opc.c (bm_decode): Handle bit map operations with the
1947         "reserved0" mode.
1948
1949 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1950
1951         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1952         specifier.  Add entries for VLDR and VSTR of system registers.
1953         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1954         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1955         of %J and %K format specifier.
1956
1957 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1958
1959         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1960         Add new entries for VSCCLRM instruction.
1961         (print_insn_coprocessor): Handle new %C format control code.
1962
1963 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1964
1965         * arm-dis.c (enum isa): New enum.
1966         (struct sopcode32): New structure.
1967         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1968         set isa field of all current entries to ANY.
1969         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1970         Only match an entry if its isa field allows the current mode.
1971
1972 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1973
1974         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1975         CLRM.
1976         (print_insn_thumb32): Add logic to print %n CLRM register list.
1977
1978 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1979
1980         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1981         and %Q patterns.
1982
1983 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1984
1985         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1986         (print_insn_thumb32): Edit the switch case for %Z.
1987
1988 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1989
1990         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1991
1992 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1993
1994         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1995
1996 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1997
1998         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1999
2000 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2001
2002         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2003         Arm register with r13 and r15 unpredictable.
2004         (thumb32_opcodes): New instructions for bfx and bflx.
2005
2006 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2007
2008         * arm-dis.c (thumb32_opcodes): New instructions for bf.
2009
2010 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2011
2012         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2013
2014 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2015
2016         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2017
2018 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2019
2020         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2021
2022 2019-04-12  John Darrington <john@darrington.wattle.id.au>
2023
2024         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2025         "optr". ("operator" is a reserved word in c++).
2026
2027 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2028
2029         * aarch64-opc.c (aarch64_print_operand): Add case for
2030         AARCH64_OPND_Rt_SP.
2031         (verify_constraints): Likewise.
2032         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2033         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2034         to accept Rt|SP as first operand.
2035         (AARCH64_OPERANDS): Add new Rt_SP.
2036         * aarch64-asm-2.c: Regenerated.
2037         * aarch64-dis-2.c: Regenerated.
2038         * aarch64-opc-2.c: Regenerated.
2039
2040 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2041
2042         * aarch64-asm-2.c: Regenerated.
2043         * aarch64-dis-2.c: Likewise.
2044         * aarch64-opc-2.c: Likewise.
2045         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2046
2047 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
2048
2049         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2050
2051 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
2052
2053         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2054         * i386-init.h: Regenerated.
2055
2056 2019-04-07  Alan Modra  <amodra@gmail.com>
2057
2058         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2059         op_separator to control printing of spaces, comma and parens
2060         rather than need_comma, need_paren and spaces vars.
2061
2062 2019-04-07  Alan Modra  <amodra@gmail.com>
2063
2064         PR 24421
2065         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2066         (print_insn_neon, print_insn_arm): Likewise.
2067
2068 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
2069
2070         * i386-dis-evex.h (evex_table): Updated to support BF16
2071         instructions.
2072         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2073         and EVEX_W_0F3872_P_3.
2074         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2075         (cpu_flags): Add bitfield for CpuAVX512_BF16.
2076         * i386-opc.h (enum): Add CpuAVX512_BF16.
2077         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2078         * i386-opc.tbl: Add AVX512 BF16 instructions.
2079         * i386-init.h: Regenerated.
2080         * i386-tbl.h: Likewise.
2081
2082 2019-04-05  Alan Modra  <amodra@gmail.com>
2083
2084         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2085         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2086         to favour printing of "-" branch hint when using the "y" bit.
2087         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2088
2089 2019-04-05  Alan Modra  <amodra@gmail.com>
2090
2091         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2092         opcode until first operand is output.
2093
2094 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2095
2096         PR gas/24349
2097         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2098         (valid_bo_post_v2): Add support for 'at' branch hints.
2099         (insert_bo): Only error on branch on ctr.
2100         (get_bo_hint_mask): New function.
2101         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2102         for inserting 'at' branch hints.
2103         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2104         for extracting 'at' branch hints.
2105         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2106         (BOE): Delete operand.
2107         (BOM, BOP): New operands.
2108         (RM): Update value.
2109         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2110         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2111         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2112         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2113         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2114         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2115         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2116         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2117         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2118         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2119         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2120         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2121         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2122         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2123         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2124         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2125         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2126         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2127         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2128         bttarl+>: New extended mnemonics.
2129
2130 2019-03-28  Alan Modra  <amodra@gmail.com>
2131
2132         PR 24390
2133         * ppc-opc.c (BTF): Define.
2134         (powerpc_opcodes): Use for mtfsb*.
2135         * ppc-dis.c (print_insn_powerpc): Print fields with both
2136         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2137
2138 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2139
2140         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2141         (mapping_symbol_for_insn): Implement new algorithm.
2142         (print_insn): Remove duplicate code.
2143
2144 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2145
2146         * aarch64-dis.c (print_insn_aarch64):
2147         Implement override.
2148
2149 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2150
2151         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2152         order.
2153
2154 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2155
2156         * aarch64-dis.c (last_stop_offset): New.
2157         (print_insn_aarch64): Use stop_offset.
2158
2159 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2160
2161         PR gas/24359
2162         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2163         CPU_ANY_AVX2_FLAGS.
2164         * i386-init.h: Regenerated.
2165
2166 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2167
2168         PR gas/24348
2169         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2170         vmovdqu16, vmovdqu32 and vmovdqu64.
2171         * i386-tbl.h: Regenerated.
2172
2173 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2174
2175         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2176         from vstrszb, vstrszh, and vstrszf.
2177
2178 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2179
2180         * s390-opc.txt: Add instruction descriptions.
2181
2182 2019-02-08  Jim Wilson  <jimw@sifive.com>
2183
2184         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2185         <bne>: Likewise.
2186
2187 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2188
2189         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2190
2191 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2192
2193         PR binutils/23212
2194         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2195         * aarch64-opc.c (verify_elem_sd): New.
2196         (fields): Add FLD_sz entr.
2197         * aarch64-tbl.h (_SIMD_INSN): New.
2198         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2199         fmulx scalar and vector by element isns.
2200
2201 2019-02-07  Nick Clifton  <nickc@redhat.com>
2202
2203         * po/sv.po: Updated Swedish translation.
2204
2205 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2206
2207         * s390-mkopc.c (main): Accept arch13 as cpu string.
2208         * s390-opc.c: Add new instruction formats and instruction opcode
2209         masks.
2210         * s390-opc.txt: Add new arch13 instructions.
2211
2212 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2213
2214         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2215         (aarch64_opcode): Change encoding for stg, stzg
2216         st2g and st2zg.
2217         * aarch64-asm-2.c: Regenerated.
2218         * aarch64-dis-2.c: Regenerated.
2219         * aarch64-opc-2.c: Regenerated.
2220
2221 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2222
2223         * aarch64-asm-2.c: Regenerated.
2224         * aarch64-dis-2.c: Likewise.
2225         * aarch64-opc-2.c: Likewise.
2226         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2227
2228 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2229             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2230
2231         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2232         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2233         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2234         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2235         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2236         case for ldstgv_indexed.
2237         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2238         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2239         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2240         * aarch64-asm-2.c: Regenerated.
2241         * aarch64-dis-2.c: Regenerated.
2242         * aarch64-opc-2.c: Regenerated.
2243
2244 2019-01-23  Nick Clifton  <nickc@redhat.com>
2245
2246         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2247
2248 2019-01-21  Nick Clifton  <nickc@redhat.com>
2249
2250         * po/de.po: Updated German translation.
2251         * po/uk.po: Updated Ukranian translation.
2252
2253 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2254         * mips-dis.c (mips_arch_choices): Fix typo in
2255         gs464, gs464e and gs264e descriptors.
2256
2257 2019-01-19  Nick Clifton  <nickc@redhat.com>
2258
2259         * configure: Regenerate.
2260         * po/opcodes.pot: Regenerate.
2261
2262 2018-06-24  Nick Clifton  <nickc@redhat.com>
2263
2264         2.32 branch created.
2265
2266 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2267
2268         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2269         if it is null.
2270         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2271         zero.
2272
2273 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2274
2275         * configure: Regenerate.
2276
2277 2019-01-07  Alan Modra  <amodra@gmail.com>
2278
2279         * configure: Regenerate.
2280         * po/POTFILES.in: Regenerate.
2281
2282 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2283
2284         * s12z-opc.c: New file.
2285         * s12z-opc.h: New file.
2286         * s12z-dis.c: Removed all code not directly related to display
2287         of instructions.  Used the interface provided by the new files
2288         instead.
2289         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2290         * Makefile.in: Regenerate.
2291         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2292         * configure: Regenerate.
2293
2294 2019-01-01  Alan Modra  <amodra@gmail.com>
2295
2296         Update year range in copyright notice of all files.
2297
2298 For older changes see ChangeLog-2018
2299 \f
2300 Copyright (C) 2019 Free Software Foundation, Inc.
2301
2302 Copying and distribution of this file, with or without modification,
2303 are permitted in any medium without royalty provided the copyright
2304 notice and this notice are preserved.
2305
2306 Local Variables:
2307 mode: change-log
2308 left-margin: 8
2309 fill-column: 74
2310 version-control: never
2311 End: