opcodes/ChangeLog

   1 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
   2
   3         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
   4         unprivileged CSR can also be initialized.
   5
   6 2020-06-29  Alan Modra  <amodra@gmail.com>
   7
   8         * arm-dis.c: Use C style comments.
   9         * cr16-opc.c: Likewise.
  10         * ft32-dis.c: Likewise.
  11         * moxie-opc.c: Likewise.
  12         * tic54x-dis.c: Likewise.
  13         * s12z-opc.c: Remove useless comment.
  14         * xgate-dis.c: Likewise.
  15
  16 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
  17
  18         * i386-opc.tbl: Add a blank line.
  19
  20 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
  21
  22         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
  23         (VecSIB128): Renamed to ...
  24         (VECSIB128): This.
  25         (VecSIB256): Renamed to ...
  26         (VECSIB256): This.
  27         (VecSIB512): Renamed to ...
  28         (VECSIB512): This.
  29         (VecSIB): Renamed to ...
  30         (SIB): This.
  31         (i386_opcode_modifier): Replace vecsib with sib.
  32         * i386-opc.tbl (VecSIB128): New.
  33         (VecSIB256): Likewise.
  34         (VecSIB512): Likewise.
  35         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
  36         and VecSIB512, respectively.
  37
  38 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  39
  40         * i386-dis.c: Adjust description of I macro.
  41         (x86_64_table): Drop use of I.
  42         (float_mem): Replace use of I.
  43         (putop): Remove handling of I. Adjust setting/clearing of "alt".
  44
  45 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  46
  47         * i386-dis.c: (print_insn): Avoid straight assignment to
  48         priv.orig_sizeflag when processing -M sub-options.
  49
  50 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  51
  52         * i386-dis.c: Adjust description of J macro.
  53         (dis386, x86_64_table, mod_table): Replace J.
  54         (putop): Remove handling of J.
  55
  56 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  57
  58         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
  59
  60 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  61
  62         * i386-dis.c: Adjust description of "LQ" macro.
  63         (dis386_twobyte): Use LQ for sysret.
  64         (putop): Adjust handling of LQ.
  65
  66 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
  67
  68         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
  69         * riscv-dis.c: Include elfxx-riscv.h.
  70
  71 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
  72
  73         * i386-dis.c (prefix_table): Revert the last vmgexit change.
  74
  75 2020-06-17  Lili Cui  <lili.cui@intel.com>
  76
  77         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
  78
  79 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
  80
  81         PR gas/26115
  82         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
  83         * i386-opc.tbl: Likewise.
  84         * i386-tbl.h: Regenerated.
  85
  86 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
  87
  88         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
  89
  90 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
  91
  92         * aarch64-opc.c (SYSREG): New macro for describing system registers.
  93         (SR_CORE): Likewise.
  94         (SR_FEAT): Likewise.
  95         (SR_RNG): Likewise.
  96         (SR_V8_1): Likewise.
  97         (SR_V8_2): Likewise.
  98         (SR_V8_3): Likewise.
  99         (SR_V8_4): Likewise.
 100         (SR_PAN): Likewise.
 101         (SR_RAS): Likewise.
 102         (SR_SSBS): Likewise.
 103         (SR_SVE): Likewise.
 104         (SR_ID_PFR2): Likewise.
 105         (SR_PROFILE): Likewise.
 106         (SR_MEMTAG): Likewise.
 107         (SR_SCXTNUM): Likewise.
 108         (aarch64_sys_regs): Refactor to store feature information in the table.
 109         (aarch64_sys_reg_supported_p): Collapse logic for system registers
 110         that now describe their own features.
 111         (aarch64_pstatefield_supported_p): Likewise.
 112
 113 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 114
 115         * i386-dis.c (prefix_table): Fix a typo in comments.
 116
 117 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 118
 119         * i386-dis.c (rex_ignored): Delete.
 120         (ckprefix): Drop rex_ignored initialization.
 121         (get_valid_dis386): Drop setting of rex_ignored.
 122         (print_insn): Drop checking of rex_ignored. Don't record data
 123         size prefix as used with VEX-and-alike encodings.
 124
 125 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 128         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 129         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 130         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 131         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 132         VEX_0F12, and VEX_0F16.
 133         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 134         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 135         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 136         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 137         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 138         MOD_VEX_0F16_PREFIX_2 entries.
 139
 140 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 141
 142         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 143         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 144         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 145         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 146         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 147         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 148         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 149         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 150         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 151         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 152         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 153         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 154         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 155         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 156         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 157         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 158         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 159         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 160         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 161         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 162         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 163         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 164         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 165         EVEX_W_0FC6_P_2): Delete.
 166         (print_insn): Add EVEX.W vs embedded prefix consistency check
 167         to prefix validation.
 168         * i386-dis-evex.h (evex_table): Don't further descend for
 169         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 170         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 171         and 0F2B.
 172         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 173         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 174         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 175         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 176         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 177         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 178         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 179         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 180         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 181         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 182         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 183         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 184         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 185         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 186         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 187         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 188         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 189         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 190         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 191         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 192         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 193         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 194         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 195         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 196         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 197         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 198         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 199
 200 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 201
 202         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 203         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 204         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 205         vmovmskpX.
 206         (print_insn): Drop pointless check against bad_opcode. Split
 207         prefix validation into legacy and VEX-and-alike parts.
 208         (putop): Re-work 'X' macro handling.
 209
 210 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 211
 212         * i386-dis.c (MOD_0F51): Rename to ...
 213         (MOD_0F50): ... this.
 214
 215 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 216
 217         * arm-dis.c (arm_opcodes): Add dfb.
 218         (thumb32_opcodes): Add dfb.
 219
 220 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 221
 222         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 223
 224 2020-06-06  Alan Modra  <amodra@gmail.com>
 225
 226         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 227
 228 2020-06-05  Alan Modra  <amodra@gmail.com>
 229
 230         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 231         size is large enough.
 232
 233 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 234
 235         * disassemble.c (disassemble_init_for_target): Set endian_code for
 236         bpf targets.
 237         * bpf-desc.c: Regenerate.
 238         * bpf-opc.c: Likewise.
 239         * bpf-dis.c: Likewise.
 240
 241 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 242
 243         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 244         (cgen_put_insn_value): Likewise.
 245         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 246         * cgen-dis.in (print_insn): Likewise.
 247         * cgen-ibld.in (insert_1): Likewise.
 248         (insert_1): Likewise.
 249         (insert_insn_normal): Likewise.
 250         (extract_1): Likewise.
 251         * bpf-dis.c: Regenerate.
 252         * bpf-ibld.c: Likewise.
 253         * bpf-ibld.c: Likewise.
 254         * cgen-dis.in: Likewise.
 255         * cgen-ibld.in: Likewise.
 256         * cgen-opc.c: Likewise.
 257         * epiphany-dis.c: Likewise.
 258         * epiphany-ibld.c: Likewise.
 259         * fr30-dis.c: Likewise.
 260         * fr30-ibld.c: Likewise.
 261         * frv-dis.c: Likewise.
 262         * frv-ibld.c: Likewise.
 263         * ip2k-dis.c: Likewise.
 264         * ip2k-ibld.c: Likewise.
 265         * iq2000-dis.c: Likewise.
 266         * iq2000-ibld.c: Likewise.
 267         * lm32-dis.c: Likewise.
 268         * lm32-ibld.c: Likewise.
 269         * m32c-dis.c: Likewise.
 270         * m32c-ibld.c: Likewise.
 271         * m32r-dis.c: Likewise.
 272         * m32r-ibld.c: Likewise.
 273         * mep-dis.c: Likewise.
 274         * mep-ibld.c: Likewise.
 275         * mt-dis.c: Likewise.
 276         * mt-ibld.c: Likewise.
 277         * or1k-dis.c: Likewise.
 278         * or1k-ibld.c: Likewise.
 279         * xc16x-dis.c: Likewise.
 280         * xc16x-ibld.c: Likewise.
 281         * xstormy16-dis.c: Likewise.
 282         * xstormy16-ibld.c: Likewise.
 283
 284 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 285
 286         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 287         (print_insn_): Handle instruction endian.
 288         * bpf-dis.c: Regenerate.
 289         * bpf-desc.c: Regenerate.
 290         * epiphany-dis.c: Likewise.
 291         * epiphany-desc.c: Likewise.
 292         * fr30-dis.c: Likewise.
 293         * fr30-desc.c: Likewise.
 294         * frv-dis.c: Likewise.
 295         * frv-desc.c: Likewise.
 296         * ip2k-dis.c: Likewise.
 297         * ip2k-desc.c: Likewise.
 298         * iq2000-dis.c: Likewise.
 299         * iq2000-desc.c: Likewise.
 300         * lm32-dis.c: Likewise.
 301         * lm32-desc.c: Likewise.
 302         * m32c-dis.c: Likewise.
 303         * m32c-desc.c: Likewise.
 304         * m32r-dis.c: Likewise.
 305         * m32r-desc.c: Likewise.
 306         * mep-dis.c: Likewise.
 307         * mep-desc.c: Likewise.
 308         * mt-dis.c: Likewise.
 309         * mt-desc.c: Likewise.
 310         * or1k-dis.c: Likewise.
 311         * or1k-desc.c: Likewise.
 312         * xc16x-dis.c: Likewise.
 313         * xc16x-desc.c: Likewise.
 314         * xstormy16-dis.c: Likewise.
 315         * xstormy16-desc.c: Likewise.
 316
 317 2020-06-03  Nick Clifton  <nickc@redhat.com>
 318
 319         * po/sr.po: Updated Serbian translation.
 320
 321 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 322
 323         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 324         (riscv_get_priv_spec_class): Likewise.
 325
 326 2020-06-01  Alan Modra  <amodra@gmail.com>
 327
 328         * bpf-desc.c: Regenerate.
 329
 330 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 331             David Faust <david.faust@oracle.com>
 332
 333         * bpf-desc.c: Regenerate.
 334         * bpf-opc.h: Likewise.
 335         * bpf-opc.c: Likewise.
 336         * bpf-dis.c: Likewise.
 337
 338 2020-05-28  Alan Modra  <amodra@gmail.com>
 339
 340         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 341         values.
 342
 343 2020-05-28  Alan Modra  <amodra@gmail.com>
 344
 345         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 346         immediates.
 347         (print_insn_ns32k): Revert last change.
 348
 349 2020-05-28  Nick Clifton  <nickc@redhat.com>
 350
 351         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 352         static.
 353
 354 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 355
 356         Fix extraction of signed constants in nios2 disassembler (again).
 357
 358         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 359         extractions of signed fields.
 360
 361 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 362
 363         * s390-opc.txt: Relocate vector load/store instructions with
 364         additional alignment parameter and change architecture level
 365         constraint from z14 to z13.
 366
 367 2020-05-21  Alan Modra  <amodra@gmail.com>
 368
 369         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 370         * sparc-dis.c: Likewise.
 371         * tic4x-dis.c: Likewise.
 372         * xtensa-dis.c: Likewise.
 373         * bpf-desc.c: Regenerate.
 374         * epiphany-desc.c: Regenerate.
 375         * fr30-desc.c: Regenerate.
 376         * frv-desc.c: Regenerate.
 377         * ip2k-desc.c: Regenerate.
 378         * iq2000-desc.c: Regenerate.
 379         * lm32-desc.c: Regenerate.
 380         * m32c-desc.c: Regenerate.
 381         * m32r-desc.c: Regenerate.
 382         * mep-asm.c: Regenerate.
 383         * mep-desc.c: Regenerate.
 384         * mt-desc.c: Regenerate.
 385         * or1k-desc.c: Regenerate.
 386         * xc16x-desc.c: Regenerate.
 387         * xstormy16-desc.c: Regenerate.
 388
 389 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 390
 391         * riscv-opc.c (riscv_ext_version_table): The table used to store
 392         all information about the supported spec and the corresponding ISA
 393         versions.  Currently, only Zicsr is supported to verify the
 394         correctness of Z sub extension settings.  Others will be supported
 395         in the future patches.
 396         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 397         classes and the corresponding strings.
 398         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 399         spec class by giving a ISA spec string.
 400         * riscv-opc.c (struct priv_spec_t): New structure.
 401         (struct priv_spec_t priv_specs): List for all supported privilege spec
 402         classes and the corresponding strings.
 403         (riscv_get_priv_spec_class): New function.  Get the corresponding
 404         privilege spec class by giving a spec string.
 405         (riscv_get_priv_spec_name): New function.  Get the corresponding
 406         privilege spec string by giving a CSR version class.
 407         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 408         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 409         according to the chosen version.  Build a hash table riscv_csr_hash to
 410         store the valid CSR for the chosen pirv verison.  Dump the direct
 411         CSR address rather than it's name if it is invalid.
 412         (parse_riscv_dis_option_without_args): New function.  Parse the options
 413         without arguments.
 414         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 415         parse the options without arguments first, and then handle the options
 416         with arguments.  Add the new option -Mpriv-spec, which has argument.
 417         * riscv-dis.c (print_riscv_disassembler_options): Add description
 418         about the new OBJDUMP option.
 419
 420 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 421
 422         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 423         WC values on POWER10 sync, dcbf  and wait instructions.
 424         (insert_pl, extract_pl): New functions.
 425         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 426         (LS3): New , 3-bit L for sync.
 427         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 428         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 429         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 430         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 431         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 432         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 433         <wait>: Enable PL operand on POWER10.
 434         <dcbf>: Enable L3OPT operand on POWER10.
 435         <sync>: Enable SC2 operand on POWER10.
 436
 437 2020-05-19  Stafford Horne  <shorne@gmail.com>
 438
 439         PR 25184
 440         * or1k-asm.c: Regenerate.
 441         * or1k-desc.c: Regenerate.
 442         * or1k-desc.h: Regenerate.
 443         * or1k-dis.c: Regenerate.
 444         * or1k-ibld.c: Regenerate.
 445         * or1k-opc.c: Regenerate.
 446         * or1k-opc.h: Regenerate.
 447         * or1k-opinst.c: Regenerate.
 448
 449 2020-05-11  Alan Modra  <amodra@gmail.com>
 450
 451         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 452         xsmaxcqp, xsmincqp.
 453
 454 2020-05-11  Alan Modra  <amodra@gmail.com>
 455
 456         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 457         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 458
 459 2020-05-11  Alan Modra  <amodra@gmail.com>
 460
 461         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 462
 463 2020-05-11  Alan Modra  <amodra@gmail.com>
 464
 465         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 466         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 467
 468 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 469
 470         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 471         mnemonics.
 472
 473 2020-05-11  Alan Modra  <amodra@gmail.com>
 474
 475         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 476         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 477         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 478         (prefix_opcodes): Add xxeval.
 479
 480 2020-05-11  Alan Modra  <amodra@gmail.com>
 481
 482         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 483         xxgenpcvwm, xxgenpcvdm.
 484
 485 2020-05-11  Alan Modra  <amodra@gmail.com>
 486
 487         * ppc-opc.c (MP, VXVAM_MASK): Define.
 488         (VXVAPS_MASK): Use VXVA_MASK.
 489         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 490         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 491         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 492         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 493
 494 2020-05-11  Alan Modra  <amodra@gmail.com>
 495             Peter Bergner  <bergner@linux.ibm.com>
 496
 497         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 498         New functions.
 499         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 500         YMSK2, XA6a, XA6ap, XB6a entries.
 501         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 502         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 503         (PPCVSX4): Define.
 504         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 505         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 506         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 507         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 508         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 509         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 510         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 511         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 512         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 513         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 514         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 515         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 516         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 517         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 518
 519 2020-05-11  Alan Modra  <amodra@gmail.com>
 520
 521         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 522         (insert_xts, extract_xts): New functions.
 523         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 524         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 525         (VXRC_MASK, VXSH_MASK): Define.
 526         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 527         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 528         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 529         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 530         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 531         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 532         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 533
 534 2020-05-11  Alan Modra  <amodra@gmail.com>
 535
 536         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 537         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 538         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 539         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 540         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 541
 542 2020-05-11  Alan Modra  <amodra@gmail.com>
 543
 544         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 545         (XTP, DQXP, DQXP_MASK): Define.
 546         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 547         (prefix_opcodes): Add plxvp and pstxvp.
 548
 549 2020-05-11  Alan Modra  <amodra@gmail.com>
 550
 551         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 552         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 553         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 554
 555 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 556
 557         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 558
 559 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 560
 561         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 562         (L1OPT): Define.
 563         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 564
 565 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 566
 567         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 568
 569 2020-05-11  Alan Modra  <amodra@gmail.com>
 570
 571         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 572
 573 2020-05-11  Alan Modra  <amodra@gmail.com>
 574
 575         * ppc-dis.c (ppc_opts): Add "power10" entry.
 576         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 577         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 578
 579 2020-05-11  Nick Clifton  <nickc@redhat.com>
 580
 581         * po/fr.po: Updated French translation.
 582
 583 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 584
 585         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 586         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 587         (operand_general_constraint_met_p): validate
 588         AARCH64_OPND_UNDEFINED.
 589         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 590         for FLD_imm16_2.
 591         * aarch64-asm-2.c: Regenerated.
 592         * aarch64-dis-2.c: Regenerated.
 593         * aarch64-opc-2.c: Regenerated.
 594
 595 2020-04-29  Nick Clifton  <nickc@redhat.com>
 596
 597         PR 22699
 598         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 599         and SETRC insns.
 600
 601 2020-04-29  Nick Clifton  <nickc@redhat.com>
 602
 603         * po/sv.po: Updated Swedish translation.
 604
 605 2020-04-29  Nick Clifton  <nickc@redhat.com>
 606
 607         PR 22699
 608         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 609         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 610         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 611         IMM0_8U case.
 612
 613 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 614
 615         PR 25848
 616         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 617         cmpi only on m68020up and cpu32.
 618
 619 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 620
 621         * aarch64-asm.c (aarch64_ins_none): New.
 622         * aarch64-asm.h (ins_none): New declaration.
 623         * aarch64-dis.c (aarch64_ext_none): New.
 624         * aarch64-dis.h (ext_none): New declaration.
 625         * aarch64-opc.c (aarch64_print_operand): Update case for
 626         AARCH64_OPND_BARRIER_PSB.
 627         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 628         (AARCH64_OPERANDS): Update inserter/extracter for
 629         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 630         * aarch64-asm-2.c: Regenerated.
 631         * aarch64-dis-2.c: Regenerated.
 632         * aarch64-opc-2.c: Regenerated.
 633
 634 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 635
 636         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 637         (aarch64_feature_ras, RAS): Likewise.
 638         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 639         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 640         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 641         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 642         * aarch64-asm-2.c: Regenerated.
 643         * aarch64-dis-2.c: Regenerated.
 644         * aarch64-opc-2.c: Regenerated.
 645
 646 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 647
 648         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 649         (print_insn_neon): Support disassembly of conditional
 650         instructions.
 651
 652 2020-02-16  David Faust  <david.faust@oracle.com>
 653
 654         * bpf-desc.c: Regenerate.
 655         * bpf-desc.h: Likewise.
 656         * bpf-opc.c: Regenerate.
 657         * bpf-opc.h: Likewise.
 658
 659 2020-04-07  Lili Cui  <lili.cui@intel.com>
 660
 661         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 662         (prefix_table): New instructions (see prefixes above).
 663         (rm_table): Likewise
 664         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 665         CPU_ANY_TSXLDTRK_FLAGS.
 666         (cpu_flags): Add CpuTSXLDTRK.
 667         * i386-opc.h (enum): Add CpuTSXLDTRK.
 668         (i386_cpu_flags): Add cputsxldtrk.
 669         * i386-opc.tbl: Add XSUSPLDTRK insns.
 670         * i386-init.h: Regenerate.
 671         * i386-tbl.h: Likewise.
 672
 673 2020-04-02  Lili Cui  <lili.cui@intel.com>
 674
 675         * i386-dis.c (prefix_table): New instructions serialize.
 676         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 677         CPU_ANY_SERIALIZE_FLAGS.
 678         (cpu_flags): Add CpuSERIALIZE.
 679         * i386-opc.h (enum): Add CpuSERIALIZE.
 680         (i386_cpu_flags): Add cpuserialize.
 681         * i386-opc.tbl: Add SERIALIZE insns.
 682         * i386-init.h: Regenerate.
 683         * i386-tbl.h: Likewise.
 684
 685 2020-03-26  Alan Modra  <amodra@gmail.com>
 686
 687         * disassemble.h (opcodes_assert): Declare.
 688         (OPCODES_ASSERT): Define.
 689         * disassemble.c: Don't include assert.h.  Include opintl.h.
 690         (opcodes_assert): New function.
 691         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 692         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 693         calculate maxlen.  Omit insn decoding when insn length exceeds
 694         maxlen.  Exit from nibble loop when looking for E, before
 695         accessing next data byte.  Move processing of E outside loop.
 696         Replace tests of maxlen in loop with assertions.
 697
 698 2020-03-26  Alan Modra  <amodra@gmail.com>
 699
 700         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 701
 702 2020-03-25  Alan Modra  <amodra@gmail.com>
 703
 704         * z80-dis.c (suffix): Init mybuf.
 705
 706 2020-03-22  Alan Modra  <amodra@gmail.com>
 707
 708         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 709         successflly read from section.
 710
 711 2020-03-22  Alan Modra  <amodra@gmail.com>
 712
 713         * arc-dis.c (find_format): Use ISO C string concatenation rather
 714         than line continuation within a string.  Don't access needs_limm
 715         before testing opcode != NULL.
 716
 717 2020-03-22  Alan Modra  <amodra@gmail.com>
 718
 719         * ns32k-dis.c (print_insn_arg): Update comment.
 720         (print_insn_ns32k): Reduce size of index_offset array, and
 721         initialize, passing -1 to print_insn_arg for args that are not
 722         an index.  Don't exit arg loop early.  Abort on bad arg number.
 723
 724 2020-03-22  Alan Modra  <amodra@gmail.com>
 725
 726         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 727         * s12z-opc.c: Formatting.
 728         (operands_f): Return an int.
 729         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 730         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 731         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 732         (exg_sex_discrim): Likewise.
 733         (create_immediate_operand, create_bitfield_operand),
 734         (create_register_operand_with_size, create_register_all_operand),
 735         (create_register_all16_operand, create_simple_memory_operand),
 736         (create_memory_operand, create_memory_auto_operand): Don't
 737         segfault on malloc failure.
 738         (z_ext24_decode): Return an int status, negative on fail, zero
 739         on success.
 740         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 741         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 742         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 743         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 744         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 745         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 746         (loop_primitive_decode, shift_decode, psh_pul_decode),
 747         (bit_field_decode): Similarly.
 748         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 749         to return value, update callers.
 750         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 751         Don't segfault on NULL operand.
 752         (decode_operation): Return OP_INVALID on first fail.
 753         (decode_s12z): Check all reads, returning -1 on fail.
 754
 755 2020-03-20  Alan Modra  <amodra@gmail.com>
 756
 757         * metag-dis.c (print_insn_metag): Don't ignore status from
 758         read_memory_func.
 759
 760 2020-03-20  Alan Modra  <amodra@gmail.com>
 761
 762         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 763         Initialize parts of buffer not written when handling a possible
 764         2-byte insn at end of section.  Don't attempt decoding of such
 765         an insn by the 4-byte machinery.
 766
 767 2020-03-20  Alan Modra  <amodra@gmail.com>
 768
 769         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 770         partially filled buffer.  Prevent lookup of 4-byte insns when
 771         only VLE 2-byte insns are possible due to section size.  Print
 772         ".word" rather than ".long" for 2-byte leftovers.
 773
 774 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 775
 776         PR 25641
 777         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 778
 779 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 780
 781         * i386-dis.c (X86_64_0D): Rename to ...
 782         (X86_64_0E): ... this.
 783
 784 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 785
 786         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 787         * Makefile.in: Regenerated.
 788
 789 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 790
 791         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 792         3-operand pseudos.
 793         * i386-tbl.h: Re-generate.
 794
 795 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 796
 797         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 798         vprot*, vpsha*, and vpshl*.
 799         * i386-tbl.h: Re-generate.
 800
 801 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 802
 803         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 804         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 805         * i386-tbl.h: Re-generate.
 806
 807 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 808
 809         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 810         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 811         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 812         * i386-tbl.h: Re-generate.
 813
 814 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 815
 816         * i386-gen.c (struct template_arg, struct template_instance,
 817         struct template_param, struct template, templates,
 818         parse_template, expand_templates): New.
 819         (process_i386_opcodes): Various local variables moved to
 820         expand_templates. Call parse_template and expand_templates.
 821         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 822         * i386-tbl.h: Re-generate.
 823
 824 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 825
 826         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 827         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 828         register and memory source templates. Replace VexW= by VexW*
 829         where applicable.
 830         * i386-tbl.h: Re-generate.
 831
 832 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 833
 834         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 835         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 836         * i386-tbl.h: Re-generate.
 837
 838 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 839
 840         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 841         * i386-tbl.h: Re-generate.
 842
 843 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 844
 845         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 846         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 847         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 848         VexW0 on SSE2AVX variants.
 849         (vmovq): Drop NoRex64 from XMM/XMM variants.
 850         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 851         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 852         applicable use VexW0.
 853         * i386-tbl.h: Re-generate.
 854
 855 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 856
 857         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 858         * i386-opc.h (Rex64): Delete.
 859         (struct i386_opcode_modifier): Remove rex64 field.
 860         * i386-opc.tbl (crc32): Drop Rex64.
 861         Replace Rex64 with Size64 everywhere else.
 862         * i386-tbl.h: Re-generate.
 863
 864 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 865
 866         * i386-dis.c (OP_E_memory): Exclude recording of used address
 867         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 868         addressed memory operands for MPX insns.
 869
 870 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 871
 872         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 873         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 874         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 875         (ptwrite): Split into non-64-bit and 64-bit forms.
 876         * i386-tbl.h: Re-generate.
 877
 878 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 879
 880         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 881         template.
 882         * i386-tbl.h: Re-generate.
 883
 884 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 885
 886         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 887         (prefix_table): Move vmmcall here. Add vmgexit.
 888         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 889         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 890         (cpu_flags): Add CpuSEV_ES entry.
 891         * i386-opc.h (CpuSEV_ES): New.
 892         (union i386_cpu_flags): Add cpusev_es field.
 893         * i386-opc.tbl (vmgexit): New.
 894         * i386-init.h, i386-tbl.h: Re-generate.
 895
 896 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 897
 898         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 899         with MnemonicSize.
 900         * i386-opc.h (IGNORESIZE): New.
 901         (DEFAULTSIZE): Likewise.
 902         (IgnoreSize): Removed.
 903         (DefaultSize): Likewise.
 904         (MnemonicSize): New.
 905         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 906         mnemonicsize.
 907         * i386-opc.tbl (IgnoreSize): New.
 908         (DefaultSize): Likewise.
 909         * i386-tbl.h: Regenerated.
 910
 911 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 912
 913         PR 25627
 914         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 915         instructions.
 916
 917 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 918
 919         PR gas/25622
 920         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 921         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 922         * i386-tbl.h: Regenerated.
 923
 924 2020-02-26  Alan Modra  <amodra@gmail.com>
 925
 926         * aarch64-asm.c: Indent labels correctly.
 927         * aarch64-dis.c: Likewise.
 928         * aarch64-gen.c: Likewise.
 929         * aarch64-opc.c: Likewise.
 930         * alpha-dis.c: Likewise.
 931         * i386-dis.c: Likewise.
 932         * nds32-asm.c: Likewise.
 933         * nfp-dis.c: Likewise.
 934         * visium-dis.c: Likewise.
 935
 936 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 937
 938         * arc-regs.h (int_vector_base): Make it available for all ARC
 939         CPUs.
 940
 941 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 942
 943         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 944         changed.
 945
 946 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 947
 948         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 949         c.mv/c.li if rs1 is zero.
 950
 951 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 952
 953         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 954         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 955         CPU_POPCNT_FLAGS.
 956         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 957         * i386-opc.h (CpuABM): Removed.
 958         (CpuPOPCNT): New.
 959         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 960         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 961         popcnt.  Remove CpuABM from lzcnt.
 962         * i386-init.h: Regenerated.
 963         * i386-tbl.h: Likewise.
 964
 965 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 966
 967         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 968         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 969         VexW1 instead of open-coding them.
 970         * i386-tbl.h: Re-generate.
 971
 972 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 973
 974         * i386-opc.tbl (AddrPrefixOpReg): Define.
 975         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 976         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 977         templates. Drop NoRex64.
 978         * i386-tbl.h: Re-generate.
 979
 980 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 981
 982         PR gas/6518
 983         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 984         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 985         into Intel syntax instance (with Unpsecified) and AT&T one
 986         (without).
 987         (vcvtneps2bf16): Likewise, along with folding the two so far
 988         separate ones.
 989         * i386-tbl.h: Re-generate.
 990
 991 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 992
 993         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 994         CPU_ANY_SSE4A_FLAGS.
 995
 996 2020-02-17  Alan Modra  <amodra@gmail.com>
 997
 998         * i386-gen.c (cpu_flag_init): Correct last change.
 999
1000 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1001
1002         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
1003         CPU_ANY_SSE4_FLAGS.
1004
1005 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
1006
1007         * i386-opc.tbl (movsx): Remove Intel syntax comments.
1008         (movzx): Likewise.
1009
1010 2020-02-14  Jan Beulich  <jbeulich@suse.com>
1011
1012         PR gas/25438
1013         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1014         destination for Cpu64-only variant.
1015         (movzx): Fold patterns.
1016         * i386-tbl.h: Re-generate.
1017
1018 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1019
1020         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1021         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1022         CPU_ANY_SSE4_FLAGS entry.
1023         * i386-init.h: Re-generate.
1024
1025 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1026
1027         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1028         with Unspecified, making the present one AT&T syntax only.
1029         * i386-tbl.h: Re-generate.
1030
1031 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1032
1033         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1034         * i386-tbl.h: Re-generate.
1035
1036 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1037
1038         PR gas/24546
1039         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1040         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1041         Amd64 and Intel64 templates.
1042         (call, jmp): Likewise for far indirect variants. Dro
1043         Unspecified.
1044         * i386-tbl.h: Re-generate.
1045
1046 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1047
1048         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1049         * i386-opc.h (ShortForm): Delete.
1050         (struct i386_opcode_modifier): Remove shortform field.
1051         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1052         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1053         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1054         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1055         Drop ShortForm.
1056         * i386-tbl.h: Re-generate.
1057
1058 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1059
1060         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1061         fucompi): Drop ShortForm from operand-less templates.
1062         * i386-tbl.h: Re-generate.
1063
1064 2020-02-11  Alan Modra  <amodra@gmail.com>
1065
1066         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1067         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1068         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1069         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1070         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1071
1072 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1073
1074         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1075         (cde_opcodes): Add VCX* instructions.
1076
1077 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1078             Matthew Malcomson  <matthew.malcomson@arm.com>
1079
1080         * arm-dis.c (struct cdeopcode32): New.
1081         (CDE_OPCODE): New macro.
1082         (cde_opcodes): New disassembly table.
1083         (regnames): New option to table.
1084         (cde_coprocs): New global variable.
1085         (print_insn_cde): New
1086         (print_insn_thumb32): Use print_insn_cde.
1087         (parse_arm_disassembler_options): Parse coprocN args.
1088
1089 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1090
1091         PR gas/25516
1092         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1093         with ISA64.
1094         * i386-opc.h (AMD64): Removed.
1095         (Intel64): Likewose.
1096         (AMD64): New.
1097         (INTEL64): Likewise.
1098         (INTEL64ONLY): Likewise.
1099         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1100         * i386-opc.tbl (Amd64): New.
1101         (Intel64): Likewise.
1102         (Intel64Only): Likewise.
1103         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1104         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1105         * i386-tbl.h: Regenerated.
1106
1107 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1108
1109         PR 25469
1110         * z80-dis.c: Add support for GBZ80 opcodes.
1111
1112 2020-02-04  Alan Modra  <amodra@gmail.com>
1113
1114         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1115
1116 2020-02-03  Alan Modra  <amodra@gmail.com>
1117
1118         * m32c-ibld.c: Regenerate.
1119
1120 2020-02-01  Alan Modra  <amodra@gmail.com>
1121
1122         * frv-ibld.c: Regenerate.
1123
1124 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1125
1126         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1127         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1128         (OP_E_memory): Replace xmm_mdq_mode case label by
1129         vex_scalar_w_dq_mode one.
1130         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1131
1132 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1133
1134         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1135         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1136         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1137         (intel_operand_size): Drop vex_w_dq_mode case label.
1138
1139 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1140
1141         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1142         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1143
1144 2020-01-30  Alan Modra  <amodra@gmail.com>
1145
1146         * m32c-ibld.c: Regenerate.
1147
1148 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1149
1150         * bpf-opc.c: Regenerate.
1151
1152 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1153
1154         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1155         (dis386): Use them to replace C2/C3 table entries.
1156         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1157         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1158         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1159         * i386-tbl.h: Re-generate.
1160
1161 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1162
1163         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1164         forms.
1165         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1166         DefaultSize.
1167         * i386-tbl.h: Re-generate.
1168
1169 2020-01-30  Alan Modra  <amodra@gmail.com>
1170
1171         * tic4x-dis.c (tic4x_dp): Make unsigned.
1172
1173 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1174             Jan Beulich  <jbeulich@suse.com>
1175
1176         PR binutils/25445
1177         * i386-dis.c (MOVSXD_Fixup): New function.
1178         (movsxd_mode): New enum.
1179         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1180         (intel_operand_size): Handle movsxd_mode.
1181         (OP_E_register): Likewise.
1182         (OP_G): Likewise.
1183         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1184         register on movsxd.  Add movsxd with 16-bit destination register
1185         for AMD64 and Intel64 ISAs.
1186         * i386-tbl.h: Regenerated.
1187
1188 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1189
1190         PR 25403
1191         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1192         * aarch64-asm-2.c: Regenerate
1193         * aarch64-dis-2.c: Likewise.
1194         * aarch64-opc-2.c: Likewise.
1195
1196 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1197
1198         * i386-opc.tbl (sysret): Drop DefaultSize.
1199         * i386-tbl.h: Re-generate.
1200
1201 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1202
1203         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1204         Dword.
1205         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1206         * i386-tbl.h: Re-generate.
1207
1208 2020-01-20  Nick Clifton  <nickc@redhat.com>
1209
1210         * po/de.po: Updated German translation.
1211         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1212         * po/uk.po: Updated Ukranian translation.
1213
1214 2020-01-20  Alan Modra  <amodra@gmail.com>
1215
1216         * hppa-dis.c (fput_const): Remove useless cast.
1217
1218 2020-01-20  Alan Modra  <amodra@gmail.com>
1219
1220         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1221
1222 2020-01-18  Nick Clifton  <nickc@redhat.com>
1223
1224         * configure: Regenerate.
1225         * po/opcodes.pot: Regenerate.
1226
1227 2020-01-18  Nick Clifton  <nickc@redhat.com>
1228
1229         Binutils 2.34 branch created.
1230
1231 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1232
1233         * opintl.h: Fix spelling error (seperate).
1234
1235 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1236
1237         * i386-opc.tbl: Add {vex} pseudo prefix.
1238         * i386-tbl.h: Regenerated.
1239
1240 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1241
1242         PR 25376
1243         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1244         (neon_opcodes): Likewise.
1245         (select_arm_features): Make sure we enable MVE bits when selecting
1246         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1247         any architecture.
1248
1249 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1250
1251         * i386-opc.tbl: Drop stale comment from XOP section.
1252
1253 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1254
1255         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1256         (extractps): Add VexWIG to SSE2AVX forms.
1257         * i386-tbl.h: Re-generate.
1258
1259 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1260
1261         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1262         Size64 from and use VexW1 on SSE2AVX forms.
1263         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1264         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1265         * i386-tbl.h: Re-generate.
1266
1267 2020-01-15  Alan Modra  <amodra@gmail.com>
1268
1269         * tic4x-dis.c (tic4x_version): Make unsigned long.
1270         (optab, optab_special, registernames): New file scope vars.
1271         (tic4x_print_register): Set up registernames rather than
1272         malloc'd registertable.
1273         (tic4x_disassemble): Delete optable and optable_special.  Use
1274         optab and optab_special instead.  Throw away old optab,
1275         optab_special and registernames when info->mach changes.
1276
1277 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1278
1279         PR 25377
1280         * z80-dis.c (suffix): Use .db instruction to generate double
1281         prefix.
1282
1283 2020-01-14  Alan Modra  <amodra@gmail.com>
1284
1285         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1286         values to unsigned before shifting.
1287
1288 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1289
1290         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1291         flow instructions.
1292         (print_insn_thumb16, print_insn_thumb32): Likewise.
1293         (print_insn): Initialize the insn info.
1294         * i386-dis.c (print_insn): Initialize the insn info fields, and
1295         detect jumps.
1296
1297 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1298
1299         * arc-opc.c (C_NE): Make it required.
1300
1301 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1302
1303         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1304         reserved register name.
1305
1306 2020-01-13  Alan Modra  <amodra@gmail.com>
1307
1308         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1309         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1310
1311 2020-01-13  Alan Modra  <amodra@gmail.com>
1312
1313         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1314         result of wasm_read_leb128 in a uint64_t and check that bits
1315         are not lost when copying to other locals.  Use uint32_t for
1316         most locals.  Use PRId64 when printing int64_t.
1317
1318 2020-01-13  Alan Modra  <amodra@gmail.com>
1319
1320         * score-dis.c: Formatting.
1321         * score7-dis.c: Formatting.
1322
1323 2020-01-13  Alan Modra  <amodra@gmail.com>
1324
1325         * score-dis.c (print_insn_score48): Use unsigned variables for
1326         unsigned values.  Don't left shift negative values.
1327         (print_insn_score32): Likewise.
1328         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1329
1330 2020-01-13  Alan Modra  <amodra@gmail.com>
1331
1332         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1333
1334 2020-01-13  Alan Modra  <amodra@gmail.com>
1335
1336         * fr30-ibld.c: Regenerate.
1337
1338 2020-01-13  Alan Modra  <amodra@gmail.com>
1339
1340         * xgate-dis.c (print_insn): Don't left shift signed value.
1341         (ripBits): Formatting, use 1u.
1342
1343 2020-01-10  Alan Modra  <amodra@gmail.com>
1344
1345         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1346         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1347
1348 2020-01-10  Alan Modra  <amodra@gmail.com>
1349
1350         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1351         and XRREG value earlier to avoid a shift with negative exponent.
1352         * m10200-dis.c (disassemble): Similarly.
1353
1354 2020-01-09  Nick Clifton  <nickc@redhat.com>
1355
1356         PR 25224
1357         * z80-dis.c (ld_ii_ii): Use correct cast.
1358
1359 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1360
1361         PR 25224
1362         * z80-dis.c (ld_ii_ii): Use character constant when checking
1363         opcode byte value.
1364
1365 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1366
1367         * i386-dis.c (SEP_Fixup): New.
1368         (SEP): Define.
1369         (dis386_twobyte): Use it for sysenter/sysexit.
1370         (enum x86_64_isa): Change amd64 enumerator to value 1.
1371         (OP_J): Compare isa64 against intel64 instead of amd64.
1372         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1373         forms.
1374         * i386-tbl.h: Re-generate.
1375
1376 2020-01-08  Alan Modra  <amodra@gmail.com>
1377
1378         * z8k-dis.c: Include libiberty.h
1379         (instr_data_s): Make max_fetched unsigned.
1380         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1381         Don't exceed byte_info bounds.
1382         (output_instr): Make num_bytes unsigned.
1383         (unpack_instr): Likewise for nibl_count and loop.
1384         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1385         idx unsigned.
1386         * z8k-opc.h: Regenerate.
1387
1388 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1389
1390         * arc-tbl.h (llock): Use 'LLOCK' as class.
1391         (llockd): Likewise.
1392         (scond): Use 'SCOND' as class.
1393         (scondd): Likewise.
1394         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1395         (scondd): Likewise.
1396
1397 2020-01-06  Alan Modra  <amodra@gmail.com>
1398
1399         * m32c-ibld.c: Regenerate.
1400
1401 2020-01-06  Alan Modra  <amodra@gmail.com>
1402
1403         PR 25344
1404         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1405         Peek at next byte to prevent recursion on repeated prefix bytes.
1406         Ensure uninitialised "mybuf" is not accessed.
1407         (print_insn_z80): Don't zero n_fetch and n_used here,..
1408         (print_insn_z80_buf): ..do it here instead.
1409
1410 2020-01-04  Alan Modra  <amodra@gmail.com>
1411
1412         * m32r-ibld.c: Regenerate.
1413
1414 2020-01-04  Alan Modra  <amodra@gmail.com>
1415
1416         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1417
1418 2020-01-04  Alan Modra  <amodra@gmail.com>
1419
1420         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1421
1422 2020-01-04  Alan Modra  <amodra@gmail.com>
1423
1424         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1425
1426 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1427
1428         * aarch64-tbl.h (aarch64_opcode_table): Use
1429         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1430
1431 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1432
1433         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1434         forms of SUDOT and USDOT.
1435
1436 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1437
1438         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1439         uzip{1,2}.
1440         * opcodes/aarch64-dis-2.c: Re-generate.
1441
1442 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1443
1444         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1445         FMMLA encoding.
1446         * opcodes/aarch64-dis-2.c: Re-generate.
1447
1448 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1449
1450         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1451
1452 2020-01-01  Alan Modra  <amodra@gmail.com>
1453
1454         Update year range in copyright notice of all files.
1455
1456 For older changes see ChangeLog-2019
1457 \f
1458 Copyright (C) 2020 Free Software Foundation, Inc.
1459
1460 Copying and distribution of this file, with or without modification,
1461 are permitted in any medium without royalty provided the copyright
1462 notice and this notice are preserved.
1463
1464 Local Variables:
1465 mode: change-log
1466 left-margin: 8
1467 fill-column: 74
1468 version-control: never
1469 End: