opcodes/ChangeLog

   1 2019-12-17  Alan Modra  <amodra@gmail.com>
   2
   3         * visium-dis.c (print_insn_visium): Avoid signed overflow.
   4
   5 2019-12-17  Alan Modra  <amodra@gmail.com>
   6
   7         * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
   8         (value_fit_unsigned_field_p): Likewise.
   9         (aarch64_wide_constant_p): Likewise.
  10         (operand_general_constraint_met_p): Likewise.
  11         * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
  12
  13 2019-12-17  Alan Modra  <amodra@gmail.com>
  14
  15         * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
  16         (print_insn_nds32): Use uint64_t for "given" and "given1".
  17
  18 2019-12-17  Alan Modra  <amodra@gmail.com>
  19
  20         * tic80-dis.c: Delete file.
  21         * tic80-opc.c: Delete file.
  22         * disassemble.c: Remove tic80 support.
  23         * disassemble.h: Likewise.
  24         * Makefile.am: Likewise.
  25         * configure.ac: Likewise.
  26         * Makefile.in: Regenerate.
  27         * configure: Regenerate.
  28         * po/POTFILES.in: Regenerate.
  29
  30 2019-12-17  Alan Modra  <amodra@gmail.com>
  31
  32         * bpf-ibld.c: Regenerate.
  33
  34 2019-12-16  Alan Modra  <amodra@gmail.com>
  35
  36         * aarch64-dis.c (sign_extend): Return uint64_t.  Rewrite without
  37         conditional.
  38         (aarch64_ext_imm): Avoid signed overflow.
  39
  40 2019-12-16  Alan Modra  <amodra@gmail.com>
  41
  42         * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
  43
  44 2019-12-16  Alan Modra  <amodra@gmail.com>
  45
  46         * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
  47
  48 2019-12-16  Alan Modra  <amodra@gmail.com>
  49
  50         * xstormy16-ibld.c: Regenerate.
  51
  52 2019-12-16  Alan Modra  <amodra@gmail.com>
  53
  54         * score-dis.c (print_insn_score16): Move rpush/rpop imm field
  55         value adjustment so that it doesn't affect reg field too.
  56
  57 2019-12-16  Alan Modra  <amodra@gmail.com>
  58
  59         * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
  60         (get_number_of_operands, getargtype, getbits, getregname),
  61         (getcopregname, getprocregname, gettrapstring, getcinvstring),
  62         (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
  63         (powerof2, match_opcode, make_instruction, print_arguments),
  64         (print_arg): Delete forward declarations, moving static to..
  65         (getregname, getcopregname, getregliststring): ..these definitions.
  66         (build_mask): Return unsigned int mask.
  67         (match_opcode): Use unsigned int vars.
  68
  69 2019-12-16  Alan Modra  <amodra@gmail.com>
  70
  71         * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
  72
  73 2019-12-16  Alan Modra  <amodra@gmail.com>
  74
  75         * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
  76         (struct objdump_disasm_info): Delete.
  77         (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
  78         N32_IMMS to unsigned before shifting left.
  79
  80 2019-12-16  Alan Modra  <amodra@gmail.com>
  81
  82         * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
  83         (print_insn_moxie): Remove unnecessary cast.
  84
  85 2019-12-12  Alan Modra  <amodra@gmail.com>
  86
  87         * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
  88         mask.
  89
  90 2019-12-11  Alan Modra  <amodra@gmail.com>
  91
  92         * arc-dis.c (BITS): Don't truncate high bits with shifts.
  93         * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
  94         * tic54x-dis.c (print_instruction): Likewise.
  95         * tilegx-opc.c (parse_insn_tilegx): Likewise.
  96         * tilepro-opc.c (parse_insn_tilepro): Likewise.
  97         * visium-dis.c (disassem_class0): Likewise.
  98         * pdp11-dis.c (sign_extend): Likewise.
  99         (SIGN_BITS): Delete.
 100         * epiphany-ibld.c: Regenerate.
 101         * lm32-ibld.c: Regenerate.
 102         * m32c-ibld.c: Regenerate.
 103
 104 2019-12-11  Alan Modra  <amodra@gmail.com>
 105
 106         * ns32k-dis.c (sign_extend): Correct last patch.
 107
 108 2019-12-11  Alan Modra  <amodra@gmail.com>
 109
 110         * vax-dis.c (NEXTLONG): Avoid signed overflow.
 111
 112 2019-12-11  Alan Modra  <amodra@gmail.com>
 113
 114         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
 115         sign extend using shifts.
 116
 117 2019-12-11  Alan Modra  <amodra@gmail.com>
 118
 119         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
 120
 121 2019-12-11  Alan Modra  <amodra@gmail.com>
 122
 123         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
 124         on NULL registertable entry.
 125         (tic4x_hash_opcode): Use unsigned arithmetic.
 126
 127 2019-12-11  Alan Modra  <amodra@gmail.com>
 128
 129         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
 130
 131 2019-12-11  Alan Modra  <amodra@gmail.com>
 132
 133         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
 134         (bit_extract_simple, sign_extend): Likewise.
 135
 136 2019-12-11  Alan Modra  <amodra@gmail.com>
 137
 138         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
 139
 140 2019-12-11  Alan Modra  <amodra@gmail.com>
 141
 142         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
 143
 144 2019-12-11  Alan Modra  <amodra@gmail.com>
 145
 146         * m68k-dis.c (COERCE32): Cast value first.
 147         (NEXTLONG, NEXTULONG): Avoid signed overflow.
 148
 149 2019-12-11  Alan Modra  <amodra@gmail.com>
 150
 151         * h8300-dis.c (extract_immediate): Avoid signed overflow.
 152         (bfd_h8_disassemble): Likewise.
 153
 154 2019-12-11  Alan Modra  <amodra@gmail.com>
 155
 156         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
 157         past end of operands array.
 158
 159 2019-12-11  Alan Modra  <amodra@gmail.com>
 160
 161         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
 162         overflow when collecting bytes of a number.
 163
 164 2019-12-11  Alan Modra  <amodra@gmail.com>
 165
 166         * cris-dis.c (print_with_operands): Avoid signed integer
 167         overflow when collecting bytes of a 32-bit integer.
 168
 169 2019-12-11  Alan Modra  <amodra@gmail.com>
 170
 171         * cr16-dis.c (EXTRACT, SBM): Rewrite.
 172         (cr16_match_opcode): Delete duplicate bcond test.
 173
 174 2019-12-11  Alan Modra  <amodra@gmail.com>
 175
 176         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
 177         (SIGNBIT): New.
 178         (MASKBITS, SIGNEXTEND): Rewrite.
 179         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
 180         unsigned arithmetic, instead assign result of SIGNEXTEND back
 181         to x.
 182         (fmtconst_val): Use 1u in shift expression.
 183
 184 2019-12-11  Alan Modra  <amodra@gmail.com>
 185
 186         * arc-dis.c (find_format_from_table): Use ull constant when
 187         shifting by up to 32.
 188
 189 2019-12-11  Alan Modra  <amodra@gmail.com>
 190
 191         PR 25270
 192         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
 193         false when field is zero for sve_size_tsz_bhs.
 194
 195 2019-12-11  Alan Modra  <amodra@gmail.com>
 196
 197         * epiphany-ibld.c: Regenerate.
 198
 199 2019-12-10  Alan Modra  <amodra@gmail.com>
 200
 201         PR 24960
 202         * disassemble.c (disassemble_free_target): New function.
 203
 204 2019-12-10  Alan Modra  <amodra@gmail.com>
 205
 206         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 207         * disassemble.c (disassemble_init_for_target): Likewise.
 208         * bpf-dis.c: Regenerate.
 209         * epiphany-dis.c: Regenerate.
 210         * fr30-dis.c: Regenerate.
 211         * frv-dis.c: Regenerate.
 212         * ip2k-dis.c: Regenerate.
 213         * iq2000-dis.c: Regenerate.
 214         * lm32-dis.c: Regenerate.
 215         * m32c-dis.c: Regenerate.
 216         * m32r-dis.c: Regenerate.
 217         * mep-dis.c: Regenerate.
 218         * mt-dis.c: Regenerate.
 219         * or1k-dis.c: Regenerate.
 220         * xc16x-dis.c: Regenerate.
 221         * xstormy16-dis.c: Regenerate.
 222
 223 2019-12-10  Alan Modra  <amodra@gmail.com>
 224
 225         * ppc-dis.c (private): Delete variable.
 226         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 227         (powerpc_init_dialect): Don't use global private.
 228
 229 2019-12-10  Alan Modra  <amodra@gmail.com>
 230
 231         * s12z-opc.c: Formatting.
 232
 233 2019-12-08  Alan Modra  <amodra@gmail.com>
 234
 235         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 236         registers.
 237
 238 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 239
 240         * aarch64-tbl.h (aarch64_feature_crypto,
 241         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 242         CRYPTO_V8_2_INSN): Delete.
 243
 244 2019-12-05  Alan Modra  <amodra@gmail.com>
 245
 246         PR 25249
 247         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 248         (struct string_buf): New.
 249         (strbuf): New function.
 250         (get_field): Use strbuf rather than strdup of local temp.
 251         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 252         (get_field_rfsl, get_field_imm15): Likewise.
 253         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 254         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 255         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 256         get_field functions.
 257
 258 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 259
 260         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 261         * i386-tbl.h: Re-generate.
 262
 263 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 264
 265         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 266
 267 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 268
 269         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 270         forms.
 271         (xbegin): Drop DefaultSize.
 272         * i386-tbl.h: Re-generate.
 273
 274 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 275
 276         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 277         Change the coproc CRC conditions to use the extension
 278         feature set, second word, base on ARM_EXT2_CRC.
 279
 280 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 281
 282         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 283         * i386-tbl.h: Re-generate.
 284
 285 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 286
 287         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 288         JumpInterSegment, and JumpAbsolute entries.
 289         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 290         JUMP_ABSOLUTE): Define.
 291         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 292         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 293         fields.
 294         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 295         JumpInterSegment): Define.
 296         * i386-tbl.h: Re-generate.
 297
 298 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 299
 300         * i386-gen.c (operand_type_init): Remove
 301         OPERAND_TYPE_JUMPABSOLUTE entry.
 302         (opcode_modifiers): Add JumpAbsolute entry.
 303         (operand_types): Remove JumpAbsolute entry.
 304         * i386-opc.h (JumpAbsolute): Move between enums.
 305         (struct i386_opcode_modifier): Add jumpabsolute field.
 306         (union i386_operand_type): Remove jumpabsolute field.
 307         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 308         * i386-init.h, i386-tbl.h: Re-generate.
 309
 310 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 311
 312         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 313         (operand_types): Remove AnySize entry.
 314         * i386-opc.h (AnySize): Move between enums.
 315         (struct i386_opcode_modifier): Add anysize field.
 316         (OTUnused): Un-comment.
 317         (union i386_operand_type): Remove anysize field.
 318         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 319         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 320         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 321         AnySize.
 322         * i386-tbl.h: Re-generate.
 323
 324 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 325
 326         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 327         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 328         use the floating point register (FPR).
 329
 330 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 331
 332         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 333         cmode 1101.
 334         (is_mve_encoding_conflict): Update cmode conflict checks for
 335         MVE_VMVN_IMM.
 336
 337 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 338
 339         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 340         entry.
 341         (operand_types): Remove EsSeg entry.
 342         (main): Replace stale use of OTMax.
 343         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 344         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 345         (EsSeg): Delete.
 346         (OTUnused): Comment out.
 347         (union i386_operand_type): Remove esseg field.
 348         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 349         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 350         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 351         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 352         * i386-init.h, i386-tbl.h: Re-generate.
 353
 354 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 355
 356         * i386-gen.c (operand_instances): Add RegB entry.
 357         * i386-opc.h (enum operand_instance): Add RegB.
 358         * i386-opc.tbl (RegC, RegD, RegB): Define.
 359         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 360         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 361         monitorx, mwaitx): Drop ImmExt and convert encodings
 362         accordingly.
 363         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 364         (edx, rdx): Add Instance=RegD.
 365         (ebx, rbx): Add Instance=RegB.
 366         * i386-tbl.h: Re-generate.
 367
 368 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 369
 370         * i386-gen.c (operand_type_init): Adjust
 371         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 372         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 373         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 374         (operand_instances): New.
 375         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 376         (output_operand_type): New parameter "instance". Process it.
 377         (process_i386_operand_type): New local variable "instance".
 378         (main): Adjust static assertions.
 379         * i386-opc.h (INSTANCE_WIDTH): Define.
 380         (enum operand_instance): New.
 381         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 382         (union i386_operand_type): Replace acc, inoutportreg, and
 383         shiftcount by instance.
 384         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 385         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 386         Add Instance=.
 387         * i386-init.h, i386-tbl.h: Re-generate.
 388
 389 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 390
 391         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 392         smaxp/sminp entries' "tied_operand" field to 2.
 393
 394 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 395
 396         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 397         "index" local variable by that of the already existing "num".
 398
 399 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 400
 401         PR gas/25167
 402         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 403         * i386-tbl.h: Regenerated.
 404
 405 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 406
 407         * i386-gen.c (operand_type_init): Add Class= to
 408         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 409         OPERAND_TYPE_REGBND entry.
 410         (operand_classes): Add RegMask and RegBND entries.
 411         (operand_types): Drop RegMask and RegBND entry.
 412         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 413         (RegMask, RegBND): Delete.
 414         (union i386_operand_type): Remove regmask and regbnd fields.
 415         * i386-opc.tbl (RegMask, RegBND): Define.
 416         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 417         Class=RegBND.
 418         * i386-init.h, i386-tbl.h: Re-generate.
 419
 420 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 421
 422         * i386-gen.c (operand_type_init): Add Class= to
 423         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 424         OPERAND_TYPE_REGZMM entries.
 425         (operand_classes): Add RegMMX and RegSIMD entries.
 426         (operand_types): Drop RegMMX and RegSIMD entries.
 427         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 428         (RegMMX, RegSIMD): Delete.
 429         (union i386_operand_type): Remove regmmx and regsimd fields.
 430         * i386-opc.tbl (RegMMX): Define.
 431         (RegXMM, RegYMM, RegZMM): Add Class=.
 432         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 433         Class=RegSIMD.
 434         * i386-init.h, i386-tbl.h: Re-generate.
 435
 436 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 437
 438         * i386-gen.c (operand_type_init): Add Class= to
 439         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 440         entries.
 441         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 442         (operand_types): Drop Control, Debug, and Test entries.
 443         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 444         (Control, Debug, Test): Delete.
 445         (union i386_operand_type): Remove control, debug, and test
 446         fields.
 447         * i386-opc.tbl (Control, Debug, Test): Define.
 448         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 449         Class=RegDR, and Test by Class=RegTR.
 450         * i386-init.h, i386-tbl.h: Re-generate.
 451
 452 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 453
 454         * i386-gen.c (operand_type_init): Add Class= to
 455         OPERAND_TYPE_SREG entry.
 456         (operand_classes): Add SReg entry.
 457         (operand_types): Drop SReg entry.
 458         * i386-opc.h (enum operand_class): Add SReg.
 459         (SReg): Delete.
 460         (union i386_operand_type): Remove sreg field.
 461         * i386-opc.tbl (SReg): Define.
 462         * i386-reg.tbl: Replace SReg by Class=SReg.
 463         * i386-init.h, i386-tbl.h: Re-generate.
 464
 465 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 466
 467         * i386-gen.c (operand_type_init): Add Class=. New
 468         OPERAND_TYPE_ANYIMM entry.
 469         (operand_classes): New.
 470         (operand_types): Drop Reg entry.
 471         (output_operand_type): New parameter "class". Process it.
 472         (process_i386_operand_type): New local variable "class".
 473         (main): Adjust static assertions.
 474         * i386-opc.h (CLASS_WIDTH): Define.
 475         (enum operand_class): New.
 476         (Reg): Replace by Class. Adjust comment.
 477         (union i386_operand_type): Replace reg by class.
 478         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 479         Class=.
 480         * i386-reg.tbl: Replace Reg by Class=Reg.
 481         * i386-init.h: Re-generate.
 482
 483 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 484
 485         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 486         (aarch64_opcode_table): Add data gathering hint mnemonic.
 487         * opcodes/aarch64-dis-2.c: Account for new instruction.
 488
 489 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 490
 491         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 492
 493
 494 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 495
 496         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 497         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 498         aarch64_feature_f64mm): New feature sets.
 499         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 500         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 501         instructions.
 502         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 503         macros.
 504         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 505         (OP_SVE_QQQ): New qualifier.
 506         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 507         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 508         the movprfx constraint.
 509         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 510         (aarch64_opcode_table): Define new instructions smmla,
 511         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 512         uzip{1/2}, trn{1/2}.
 513         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 514         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 515         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 516         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 517         Account for new instructions.
 518         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 519         S4x32 operand.
 520         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 521
 522 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 523 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 524
 525         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 526         Armv8.6-A.
 527         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 528         (neon_opcodes): Add bfloat SIMD instructions.
 529         (print_insn_coprocessor): Add new control character %b to print
 530         condition code without checking cp_num.
 531         (print_insn_neon): Account for BFloat16 instructions that have no
 532         special top-byte handling.
 533
 534 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 535 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 536
 537         * arm-dis.c (print_insn_coprocessor,
 538         print_insn_generic_coprocessor): Create wrapper functions around
 539         the implementation of the print_insn_coprocessor control codes.
 540         (print_insn_coprocessor_1): Original print_insn_coprocessor
 541         function that now takes which array to look at as an argument.
 542         (print_insn_arm): Use both print_insn_coprocessor and
 543         print_insn_generic_coprocessor.
 544         (print_insn_thumb32): As above.
 545
 546 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 547 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 548
 549         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 550         in reglane special case.
 551         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 552         aarch64_find_next_opcode): Account for new instructions.
 553         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 554         in reglane special case.
 555         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 556         new AARCH64_OPND_QLF_S_2H qualifier.
 557         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 558         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 559         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 560         sets.
 561         (BFLOAT_SVE, BFLOAT): New feature set macros.
 562         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 563         instructions.
 564         (aarch64_opcode_table): Define new instructions bfdot,
 565         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 566         bfcvtn2, bfcvt.
 567
 568 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 569 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 570
 571         * aarch64-tbl.h (ARMV8_6): New macro.
 572
 573 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 574
 575         * i386-dis.c (prefix_table): Add mcommit.
 576         (rm_table): Add rdpru.
 577         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 578         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 579         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 580         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 581         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 582         * i386-opc.tbl (mcommit, rdpru): New.
 583         * i386-init.h, i386-tbl.h: Re-generate.
 584
 585 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 586
 587         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 588         "names32" instead.
 589         (OP_Monitor): Drop local variable "op1_names", re-purpose
 590         "names" for it instead, and replace former "names" uses by
 591         "names32" ones.
 592
 593 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 594
 595         PR/gas 25167
 596         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 597         operand-less forms.
 598         * opcodes/i386-tbl.h: Re-generate.
 599
 600 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 601
 602         * i386-dis.c (OP_Mwaitx): Delete.
 603         (prefix_table): Use OP_Mwait for mwaitx entry.
 604         (OP_Mwait): Also handle mwaitx.
 605
 606 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 607
 608         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 609         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 610         (prefix_table): Add respective entries.
 611         (rm_table): Link to those entries.
 612
 613 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 614
 615         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 616         (REG_0F1C_P_0_MOD_0): ... this.
 617         (REG_0F1E_MOD_3): Rename to ...
 618         (REG_0F1E_P_1_MOD_3): ... this.
 619         (RM_0F01_REG_5): Rename to ...
 620         (RM_0F01_REG_5_MOD_3): ... this.
 621         (RM_0F01_REG_7): Rename to ...
 622         (RM_0F01_REG_7_MOD_3): ... this.
 623         (RM_0F1E_MOD_3_REG_7): Rename to ...
 624         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 625         (RM_0FAE_REG_6): Rename to ...
 626         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 627         (RM_0FAE_REG_7): Rename to ...
 628         (RM_0FAE_REG_7_MOD_3): ... this.
 629         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 630         (PREFIX_0F01_REG_5_MOD_0): ... this.
 631         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 632         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 633         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 634         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 635         (PREFIX_0FAE_REG_0): Rename to ...
 636         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 637         (PREFIX_0FAE_REG_1): Rename to ...
 638         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 639         (PREFIX_0FAE_REG_2): Rename to ...
 640         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 641         (PREFIX_0FAE_REG_3): Rename to ...
 642         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 643         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 644         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 645         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 646         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 647         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 648         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 649         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 650         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 651         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 652         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 653         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 654         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 655         (PREFIX_0FAE_REG_7): Rename to ...
 656         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 657         (PREFIX_MOD_0_0FC3): Rename to ...
 658         (PREFIX_0FC3_MOD_0): ... this.
 659         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 660         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 661         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 662         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 663         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 664         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 665         (reg_table, prefix_table, mod_table, rm_table): Adjust
 666         accordingly.
 667
 668 2019-11-04  Nick Clifton  <nickc@redhat.com>
 669
 670         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 671         of a v850 system register.  Move the v850_sreg_names array into
 672         this function.
 673         (get_v850_reg_name): Likewise for ordinary register names.
 674         (get_v850_vreg_name): Likewise for vector register names.
 675         (get_v850_cc_name): Likewise for condition codes.
 676         * get_v850_float_cc_name): Likewise for floating point condition
 677         codes.
 678         (get_v850_cacheop_name): Likewise for cache-ops.
 679         (get_v850_prefop_name): Likewise for pref-ops.
 680         (disassemble): Use the new accessor functions.
 681
 682 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 683
 684         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 685         immediate for the writeback form of ldraa/ldrab if it is 0.
 686         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 687         * aarch64-opc-2.c: Regenerated.
 688
 689 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 690
 691         * i386-gen.c (operand_type_shorthands): Delete.
 692         (operand_type_init): Expand previous shorthands.
 693         (set_bitfield_from_shorthand): Rename back to ...
 694         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 695         of operand_type_init[].
 696         (set_bitfield): Adjust call to the above function.
 697         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 698         RegXMM, RegYMM, RegZMM): Define.
 699         * i386-reg.tbl: Expand prior shorthands.
 700
 701 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 702
 703         * i386-gen.c (output_i386_opcode): Change order of fields
 704         emitted to output.
 705         * i386-opc.h (struct insn_template): Move operands field.
 706         Convert extension_opcode field to unsigned short.
 707         * i386-tbl.h: Re-generate.
 708
 709 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 710
 711         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 712         of W.
 713         * i386-opc.h (W): Extend comment.
 714         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 715         general purpose variants not allowing for byte operands.
 716         * i386-tbl.h: Re-generate.
 717
 718 2019-10-29  Nick Clifton  <nickc@redhat.com>
 719
 720         * tic30-dis.c (print_branch): Correct size of operand array.
 721
 722 2019-10-29  Nick Clifton  <nickc@redhat.com>
 723
 724         * d30v-dis.c (print_insn): Check that operand index is valid
 725         before attempting to access the operands array.
 726
 727 2019-10-29  Nick Clifton  <nickc@redhat.com>
 728
 729         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 730         locating the bit to be tested.
 731
 732 2019-10-29  Nick Clifton  <nickc@redhat.com>
 733
 734         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 735         values.
 736         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 737         (print_insn_s12z):  Check for illegal size values.
 738
 739 2019-10-28  Nick Clifton  <nickc@redhat.com>
 740
 741         * csky-dis.c (csky_chars_to_number): Check for a negative
 742         count. Use an unsigned integer to construct the return value.
 743
 744 2019-10-28  Nick Clifton  <nickc@redhat.com>
 745
 746         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 747         operand buffer.  Set value to 15 not 13.
 748         (get_register_operand): Use OPERAND_BUFFER_LEN.
 749         (get_indirect_operand): Likewise.
 750         (print_two_operand): Likewise.
 751         (print_three_operand): Likewise.
 752         (print_oar_insn): Likewise.
 753
 754 2019-10-28  Nick Clifton  <nickc@redhat.com>
 755
 756         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 757         (bit_extract_simple): Likewise.
 758         (bit_copy): Likewise.
 759         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 760         index_offset array are not accessed.
 761
 762 2019-10-28  Nick Clifton  <nickc@redhat.com>
 763
 764         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 765         operand.
 766
 767 2019-10-25  Nick Clifton  <nickc@redhat.com>
 768
 769         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 770         access to opcodes.op array element.
 771
 772 2019-10-23  Nick Clifton  <nickc@redhat.com>
 773
 774         * rx-dis.c (get_register_name): Fix spelling typo in error
 775         message.
 776         (get_condition_name, get_flag_name, get_double_register_name)
 777         (get_double_register_high_name, get_double_register_low_name)
 778         (get_double_control_register_name, get_double_condition_name)
 779         (get_opsize_name, get_size_name): Likewise.
 780
 781 2019-10-22  Nick Clifton  <nickc@redhat.com>
 782
 783         * rx-dis.c (get_size_name): New function.  Provides safe
 784         access to name array.
 785         (get_opsize_name): Likewise.
 786         (print_insn_rx): Use the accessor functions.
 787
 788 2019-10-16  Nick Clifton  <nickc@redhat.com>
 789
 790         * rx-dis.c (get_register_name): New function.  Provides safe
 791         access to name array.
 792         (get_condition_name, get_flag_name, get_double_register_name)
 793         (get_double_register_high_name, get_double_register_low_name)
 794         (get_double_control_register_name, get_double_condition_name):
 795         Likewise.
 796         (print_insn_rx): Use the accessor functions.
 797
 798 2019-10-09  Nick Clifton  <nickc@redhat.com>
 799
 800         PR 25041
 801         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 802         instructions.
 803
 804 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 805
 806         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 807         (cmpsd): Likewise. Move EsSeg to other operand.
 808         * opcodes/i386-tbl.h: Re-generate.
 809
 810 2019-09-23  Alan Modra  <amodra@gmail.com>
 811
 812         * m68k-dis.c: Include cpu-m68k.h
 813
 814 2019-09-23  Alan Modra  <amodra@gmail.com>
 815
 816         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 817         "elf/mips.h" earlier.
 818
 819 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 820
 821         PR gas/25012
 822         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 823         with SReg operand.
 824         * i386-tbl.h: Re-generate.
 825
 826 2019-09-18  Alan Modra  <amodra@gmail.com>
 827
 828         * arc-ext.c: Update throughout for bfd section macro changes.
 829
 830 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 831
 832         * Makefile.in: Re-generate.
 833         * configure: Re-generate.
 834
 835 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 836
 837         * riscv-opc.c (riscv_opcodes): Change subset field
 838         to insn_class field for all instructions.
 839         (riscv_insn_types): Likewise.
 840
 841 2019-09-16  Phil Blundell  <pb@pbcl.net>
 842
 843         * configure: Regenerated.
 844
 845 2019-09-10  Miod Vallat  <miod@online.fr>
 846
 847         PR 24982
 848         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 849
 850 2019-09-09  Phil Blundell  <pb@pbcl.net>
 851
 852         binutils 2.33 branch created.
 853
 854 2019-09-03  Nick Clifton  <nickc@redhat.com>
 855
 856         PR 24961
 857         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 858         greater than zero before indexing via (bufcnt -1).
 859
 860 2019-09-03  Nick Clifton  <nickc@redhat.com>
 861
 862         PR 24958
 863         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 864         (MAX_SPEC_REG_NAME_LEN): Define.
 865         (struct mmix_dis_info): Use defined constants for array lengths.
 866         (get_reg_name): New function.
 867         (get_sprec_reg_name): New function.
 868         (print_insn_mmix): Use new functions.
 869
 870 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 871
 872         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 873         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 874         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 875
 876 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 877
 878         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 879         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 880         (aarch64_sys_reg_supported_p): Update checks for the above.
 881
 882 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 883
 884         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 885         cases MVE_SQRSHRL and MVE_UQRSHLL.
 886         (print_insn_mve): Add case for specifier 'k' to check
 887         specific bit of the instruction.
 888
 889 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 890
 891         PR 24854
 892         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 893         encountering an unknown machine type.
 894         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 895         cases return -1 rather than calling abort.
 896
 897 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 898
 899         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 900         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 901         IgnoreSize.
 902         * i386-tbl.h: Re-generate.
 903
 904 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 905
 906         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 907         instructions.
 908
 909 2019-07-30  Mel Chen <mel.chen@sifive.com>
 910
 911         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 912         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 913
 914         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 915         fscsr.
 916
 917 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 918
 919         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 920         and MPY class instructions.
 921         (parse_option): Add nps400 option.
 922         (print_arc_disassembler_options): Add nps400 info.
 923
 924 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 925
 926         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 927         (bspop): Likewise.
 928         (modapp): Likewise.
 929         * arc-opc.c (RAD_CHK): Add.
 930         * arc-tbl.h: Regenerate.
 931
 932 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 933
 934         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 935         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 936
 937 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 938
 939         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 940         instructions as UNPREDICTABLE.
 941
 942 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 943
 944         * bpf-desc.c: Regenerated.
 945
 946 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 947
 948         * i386-gen.c (static_assert): Define.
 949         (main): Use it.
 950         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 951         (Opcode_Modifier_Num): ... this.
 952         (Mem): Delete.
 953
 954 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 955
 956         * i386-gen.c (operand_types): Move RegMem ...
 957         (opcode_modifiers): ... here.
 958         * i386-opc.h (RegMem): Move to opcode modifer enum.
 959         (union i386_operand_type): Move regmem field ...
 960         (struct i386_opcode_modifier): ... here.
 961         * i386-opc.tbl (RegMem): Define.
 962         (mov, movq): Move RegMem on segment, control, debug, and test
 963         register flavors.
 964         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 965         to non-SSE2AVX flavor.
 966         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 967         Move RegMem on register only flavors. Drop IgnoreSize from
 968         legacy encoding flavors.
 969         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 970         flavors.
 971         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 972         register only flavors.
 973         (vmovd): Move RegMem and drop IgnoreSize on register only
 974         flavor. Change opcode and operand order to store form.
 975         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 976
 977 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 978
 979         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 980         entries.
 981         * i386-opc.h (SReg2, SReg3): Replace by ...
 982         (SReg): ... this.
 983         (union i386_operand_type): Replace sreg fields.
 984         * i386-opc.tbl (mov, ): Use SReg.
 985         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 986         register flavors.
 987         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 988         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 989
 990 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 991
 992         * bpf-desc.c: Regenerate.
 993         * bpf-opc.c: Likewise.
 994         * bpf-opc.h: Likewise.
 995
 996 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 997
 998         * bpf-desc.c: Regenerate.
 999         * bpf-opc.c: Likewise.
1000
1001 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
1002
1003         * arm-dis.c (print_insn_coprocessor): Rename index to
1004         index_operand.
1005
1006 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
1007
1008         * riscv-opc.c (riscv_insn_types): Add r4 type.
1009
1010         * riscv-opc.c (riscv_insn_types): Add b and j type.
1011
1012         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1013         format for sb type and correct s type.
1014
1015 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1016
1017         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1018         SVE FMOV alias of FCPY.
1019
1020 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1021
1022         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1023         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1024
1025 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1026
1027         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1028         registers in an instruction prefixed by MOVPRFX.
1029
1030 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
1031
1032         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1033         sve_size_13 icode to account for variant behaviour of
1034         pmull{t,b}.
1035         * aarch64-dis-2.c: Regenerate.
1036         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1037         sve_size_13 icode to account for variant behaviour of
1038         pmull{t,b}.
1039         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1040         (OP_SVE_VVV_Q_D): Add new qualifier.
1041         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1042         (struct aarch64_opcode): Split pmull{t,b} into those requiring
1043         AES and those not.
1044
1045 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1046
1047         * opcodes/i386-gen.c (operand_type_init): Remove
1048         OPERAND_TYPE_VEC_IMM4 entry.
1049         (operand_types): Remove Vec_Imm4.
1050         * opcodes/i386-opc.h (Vec_Imm4): Delete.
1051         (union i386_operand_type): Remove vec_imm4.
1052         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1053         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1054
1055 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1056
1057         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1058         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1059         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1060         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1061         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1062         monitorx, mwaitx): Drop ImmExt from operand-less forms.
1063         * i386-tbl.h: Re-generate.
1064
1065 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1066
1067         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1068         register operands.
1069         * i386-tbl.h: Re-generate.
1070
1071 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1072
1073         * i386-opc.tbl (C): New.
1074         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1075         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1076         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1077         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1078         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1079         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1080         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1081         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1082         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1083         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1084         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1085         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1086         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1087         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1088         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1089         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1090         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1091         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1092         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1093         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1094         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1095         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1096         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1097         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1098         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1099         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1100         flavors.
1101         * i386-tbl.h: Re-generate.
1102
1103 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1104
1105         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1106         register operands.
1107         * i386-tbl.h: Re-generate.
1108
1109 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1110
1111         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1112         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1113         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1114         * i386-tbl.h: Re-generate.
1115
1116 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1117
1118         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1119         Disp8MemShift from register only templates.
1120         * i386-tbl.h: Re-generate.
1121
1122 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1123
1124         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1125         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1126         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1127         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1128         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1129         EVEX_W_0F11_P_3_M_1): Delete.
1130         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1131         EVEX_W_0F11_P_3): New.
1132         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1133         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1134         MOD_EVEX_0F11_PREFIX_3 table entries.
1135         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1136         PREFIX_EVEX_0F11 table entries.
1137         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1138         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1139         EVEX_W_0F11_P_3_M_{0,1} table entries.
1140
1141 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1142
1143         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1144         Delete.
1145
1146 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1147
1148         PR binutils/24719
1149         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1150         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1151         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1152         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1153         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1154         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1155         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1156         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1157         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1158         PREFIX_EVEX_0F38C6_REG_6 entries.
1159         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1160         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1161         EVEX_W_0F38C7_R_6_P_2 entries.
1162         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1163         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1164         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1165         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1166         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1167         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1168         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1169
1170 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1171
1172         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1173         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1174         VEX_LEN_0F2D_P_3): Delete.
1175         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1176         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1177         (prefix_table): ... here.
1178
1179 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1180
1181         * i386-dis.c (Iq): Delete.
1182         (Id): New.
1183         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1184         TBM insns.
1185         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1186         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1187         (OP_E_memory): Also honor needindex when deciding whether an
1188         address size prefix needs printing.
1189         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1190
1191 2019-06-26  Jim Wilson  <jimw@sifive.com>
1192
1193         PR binutils/24739
1194         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1195         Set info->display_endian to info->endian_code.
1196
1197 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1198
1199         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1200         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1201         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1202         OPERAND_TYPE_ACC64 entries.
1203         * i386-init.h: Re-generate.
1204
1205 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1206
1207         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1208         Delete.
1209         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1210         of dqa_mode.
1211         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1212         entries here.
1213         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1214         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1215
1216 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1217
1218         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1219         variables.
1220
1221 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1222
1223         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1224         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1225         movnti.
1226         * i386-opc.tbl (movnti): Add IgnoreSize.
1227         * i386-tbl.h: Re-generate.
1228
1229 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1230
1231         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1232         * i386-tbl.h: Re-generate.
1233
1234 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1235
1236         * i386-dis-evex.h: Break into ...
1237         * i386-dis-evex-len.h: New file.
1238         * i386-dis-evex-mod.h: Likewise.
1239         * i386-dis-evex-prefix.h: Likewise.
1240         * i386-dis-evex-reg.h: Likewise.
1241         * i386-dis-evex-w.h: Likewise.
1242         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1243         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1244         i386-dis-evex-mod.h.
1245
1246 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1247
1248         PR binutils/24700
1249         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1250         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1251         EVEX_W_0F385B_P_2.
1252         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1253         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1254         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1255         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1256         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1257         EVEX_LEN_0F385B_P_2_W_1.
1258         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1259         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1260         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1261         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1262         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1263         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1264         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1265         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1266         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1267         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1268
1269 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1270
1271         PR binutils/24691
1272         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1273         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1274         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1275         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1276         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1277         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1278         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1279         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1280         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1281         EVEX_LEN_0F3A43_P_2_W_1.
1282         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1283         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1284         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1285         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1286         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1287         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1288         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1289         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1290         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1291         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1292         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1293         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1294
1295 2019-06-14  Nick Clifton  <nickc@redhat.com>
1296
1297         * po/fr.po; Updated French translation.
1298
1299 2019-06-13  Stafford Horne  <shorne@gmail.com>
1300
1301         * or1k-asm.c: Regenerated.
1302         * or1k-desc.c: Regenerated.
1303         * or1k-desc.h: Regenerated.
1304         * or1k-dis.c: Regenerated.
1305         * or1k-ibld.c: Regenerated.
1306         * or1k-opc.c: Regenerated.
1307         * or1k-opc.h: Regenerated.
1308         * or1k-opinst.c: Regenerated.
1309
1310 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1311
1312         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1313
1314 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1315
1316         PR binutils/24633
1317         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1318         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1319         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1320         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1321         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1322         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1323         EVEX_LEN_0F3A1B_P_2_W_1.
1324         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1325         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1326         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1327         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1328         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1329         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1330         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1331         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1332
1333 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1334
1335         PR binutils/24626
1336         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1337         EVEX.vvvv when disassembling VEX and EVEX instructions.
1338         (OP_VEX): Set vex.register_specifier to 0 after readding
1339         vex.register_specifier.
1340         (OP_Vex_2src_1): Likewise.
1341         (OP_Vex_2src_2): Likewise.
1342         (OP_LWP_E): Likewise.
1343         (OP_EX_Vex): Don't check vex.register_specifier.
1344         (OP_XMM_Vex): Likewise.
1345
1346 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1347             Lili Cui  <lili.cui@intel.com>
1348
1349         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1350         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1351         instructions.
1352         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1353         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1354         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1355         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1356         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1357         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1358         * i386-init.h: Regenerated.
1359         * i386-tbl.h: Likewise.
1360
1361 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1362             Lili Cui  <lili.cui@intel.com>
1363
1364         * doc/c-i386.texi: Document enqcmd.
1365         * testsuite/gas/i386/enqcmd-intel.d: New file.
1366         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1367         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1368         * testsuite/gas/i386/enqcmd.d: Likewise.
1369         * testsuite/gas/i386/enqcmd.s: Likewise.
1370         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1371         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1372         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1373         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1374         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1375         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1376         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1377         and x86-64-enqcmd.
1378
1379 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1380
1381         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1382
1383 2019-06-03  Alan Modra  <amodra@gmail.com>
1384
1385         * ppc-dis.c (prefix_opcd_indices): Correct size.
1386
1387 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1388
1389         PR gas/24625
1390         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1391         Disp8ShiftVL.
1392         * i386-tbl.h: Regenerated.
1393
1394 2019-05-24  Alan Modra  <amodra@gmail.com>
1395
1396         * po/POTFILES.in: Regenerate.
1397
1398 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1399             Alan Modra  <amodra@gmail.com>
1400
1401         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1402         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1403         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1404         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1405         XTOP>): Define and add entries.
1406         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1407         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1408         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1409         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1410
1411 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1412             Alan Modra  <amodra@gmail.com>
1413
1414         * ppc-dis.c (ppc_opts): Add "future" entry.
1415         (PREFIX_OPCD_SEGS): Define.
1416         (prefix_opcd_indices): New array.
1417         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1418         (lookup_prefix): New function.
1419         (print_insn_powerpc): Handle 64-bit prefix instructions.
1420         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1421         (PMRR, POWERXX): Define.
1422         (prefix_opcodes): New instruction table.
1423         (prefix_num_opcodes): New constant.
1424
1425 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1426
1427         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1428         * configure: Regenerated.
1429         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1430         and cpu/bpf.opc.
1431         (HFILES): Add bpf-desc.h and bpf-opc.h.
1432         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1433         bpf-ibld.c and bpf-opc.c.
1434         (BPF_DEPS): Define.
1435         * Makefile.in: Regenerated.
1436         * disassemble.c (ARCH_bpf): Define.
1437         (disassembler): Add case for bfd_arch_bpf.
1438         (disassemble_init_for_target): Likewise.
1439         (enum epbf_isa_attr): Define.
1440         * disassemble.h: extern print_insn_bpf.
1441         * bpf-asm.c: Generated.
1442         * bpf-opc.h: Likewise.
1443         * bpf-opc.c: Likewise.
1444         * bpf-ibld.c: Likewise.
1445         * bpf-dis.c: Likewise.
1446         * bpf-desc.h: Likewise.
1447         * bpf-desc.c: Likewise.
1448
1449 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1450
1451         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1452         and VMSR with the new operands.
1453
1454 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1455
1456         * arm-dis.c (enum mve_instructions): New enum
1457         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1458         and cneg.
1459         (mve_opcodes): New instructions as above.
1460         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1461         csneg and csel.
1462         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1463
1464 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1465
1466         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1467         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1468         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1469         uqshl, urshrl and urshr.
1470         (is_mve_okay_in_it): Add new instructions to TRUE list.
1471         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1472         (print_insn_mve): Updated to accept new %j,
1473         %<bitfield>m and %<bitfield>n patterns.
1474
1475 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1476
1477         * mips-opc.c (mips_builtin_opcodes): Change source register
1478         constraint for DAUI.
1479
1480 2019-05-20  Nick Clifton  <nickc@redhat.com>
1481
1482         * po/fr.po: Updated French translation.
1483
1484 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1485             Michael Collison <michael.collison@arm.com>
1486
1487         * arm-dis.c (thumb32_opcodes): Add new instructions.
1488         (enum mve_instructions): Likewise.
1489         (enum mve_undefined): Add new reasons.
1490         (is_mve_encoding_conflict): Handle new instructions.
1491         (is_mve_undefined): Likewise.
1492         (is_mve_unpredictable): Likewise.
1493         (print_mve_undefined): Likewise.
1494         (print_mve_size): Likewise.
1495
1496 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1497             Michael Collison <michael.collison@arm.com>
1498
1499         * arm-dis.c (thumb32_opcodes): Add new instructions.
1500         (enum mve_instructions): Likewise.
1501         (is_mve_encoding_conflict): Handle new instructions.
1502         (is_mve_undefined): Likewise.
1503         (is_mve_unpredictable): Likewise.
1504         (print_mve_size): Likewise.
1505
1506 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1507             Michael Collison <michael.collison@arm.com>
1508
1509         * arm-dis.c (thumb32_opcodes): Add new instructions.
1510         (enum mve_instructions): Likewise.
1511         (is_mve_encoding_conflict): Likewise.
1512         (is_mve_unpredictable): Likewise.
1513         (print_mve_size): Likewise.
1514
1515 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1516             Michael Collison <michael.collison@arm.com>
1517
1518         * arm-dis.c (thumb32_opcodes): Add new instructions.
1519         (enum mve_instructions): Likewise.
1520         (is_mve_encoding_conflict): Handle new instructions.
1521         (is_mve_undefined): Likewise.
1522         (is_mve_unpredictable): Likewise.
1523         (print_mve_size): Likewise.
1524
1525 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1526             Michael Collison <michael.collison@arm.com>
1527
1528         * arm-dis.c (thumb32_opcodes): Add new instructions.
1529         (enum mve_instructions): Likewise.
1530         (is_mve_encoding_conflict): Handle new instructions.
1531         (is_mve_undefined): Likewise.
1532         (is_mve_unpredictable): Likewise.
1533         (print_mve_size): Likewise.
1534         (print_insn_mve): Likewise.
1535
1536 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1537             Michael Collison <michael.collison@arm.com>
1538
1539         * arm-dis.c (thumb32_opcodes): Add new instructions.
1540         (print_insn_thumb32): Handle new instructions.
1541
1542 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1543             Michael Collison <michael.collison@arm.com>
1544
1545         * arm-dis.c (enum mve_instructions): Add new instructions.
1546         (enum mve_undefined): Add new reasons.
1547         (is_mve_encoding_conflict): Handle new instructions.
1548         (is_mve_undefined): Likewise.
1549         (is_mve_unpredictable): Likewise.
1550         (print_mve_undefined): Likewise.
1551         (print_mve_size): Likewise.
1552         (print_mve_shift_n): Likewise.
1553         (print_insn_mve): Likewise.
1554
1555 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1556             Michael Collison <michael.collison@arm.com>
1557
1558         * arm-dis.c (enum mve_instructions): Add new instructions.
1559         (is_mve_encoding_conflict): Handle new instructions.
1560         (is_mve_unpredictable): Likewise.
1561         (print_mve_rotate): Likewise.
1562         (print_mve_size): Likewise.
1563         (print_insn_mve): Likewise.
1564
1565 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1566             Michael Collison <michael.collison@arm.com>
1567
1568         * arm-dis.c (enum mve_instructions): Add new instructions.
1569         (is_mve_encoding_conflict): Handle new instructions.
1570         (is_mve_unpredictable): Likewise.
1571         (print_mve_size): Likewise.
1572         (print_insn_mve): Likewise.
1573
1574 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1575             Michael Collison <michael.collison@arm.com>
1576
1577         * arm-dis.c (enum mve_instructions): Add new instructions.
1578         (enum mve_undefined): Add new reasons.
1579         (is_mve_encoding_conflict): Handle new instructions.
1580         (is_mve_undefined): Likewise.
1581         (is_mve_unpredictable): Likewise.
1582         (print_mve_undefined): Likewise.
1583         (print_mve_size): Likewise.
1584         (print_insn_mve): Likewise.
1585
1586 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1587             Michael Collison <michael.collison@arm.com>
1588
1589         * arm-dis.c (enum mve_instructions): Add new instructions.
1590         (is_mve_encoding_conflict): Handle new instructions.
1591         (is_mve_undefined): Likewise.
1592         (is_mve_unpredictable): Likewise.
1593         (print_mve_size): Likewise.
1594         (print_insn_mve): Likewise.
1595
1596 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1597             Michael Collison <michael.collison@arm.com>
1598
1599         * arm-dis.c (enum mve_instructions): Add new instructions.
1600         (enum mve_unpredictable): Add new reasons.
1601         (enum mve_undefined): Likewise.
1602         (is_mve_okay_in_it): Handle new isntructions.
1603         (is_mve_encoding_conflict): Likewise.
1604         (is_mve_undefined): Likewise.
1605         (is_mve_unpredictable): Likewise.
1606         (print_mve_vmov_index): Likewise.
1607         (print_simd_imm8): Likewise.
1608         (print_mve_undefined): Likewise.
1609         (print_mve_unpredictable): Likewise.
1610         (print_mve_size): Likewise.
1611         (print_insn_mve): Likewise.
1612
1613 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1614             Michael Collison <michael.collison@arm.com>
1615
1616         * arm-dis.c (enum mve_instructions): Add new instructions.
1617         (enum mve_unpredictable): Add new reasons.
1618         (enum mve_undefined): Likewise.
1619         (is_mve_encoding_conflict): Handle new instructions.
1620         (is_mve_undefined): Likewise.
1621         (is_mve_unpredictable): Likewise.
1622         (print_mve_undefined): Likewise.
1623         (print_mve_unpredictable): Likewise.
1624         (print_mve_rounding_mode): Likewise.
1625         (print_mve_vcvt_size): Likewise.
1626         (print_mve_size): Likewise.
1627         (print_insn_mve): Likewise.
1628
1629 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1630             Michael Collison <michael.collison@arm.com>
1631
1632         * arm-dis.c (enum mve_instructions): Add new instructions.
1633         (enum mve_unpredictable): Add new reasons.
1634         (enum mve_undefined): Likewise.
1635         (is_mve_undefined): Handle new instructions.
1636         (is_mve_unpredictable): Likewise.
1637         (print_mve_undefined): Likewise.
1638         (print_mve_unpredictable): Likewise.
1639         (print_mve_size): Likewise.
1640         (print_insn_mve): Likewise.
1641
1642 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1643             Michael Collison <michael.collison@arm.com>
1644
1645         * arm-dis.c (enum mve_instructions): Add new instructions.
1646         (enum mve_undefined): Add new reasons.
1647         (insns): Add new instructions.
1648         (is_mve_encoding_conflict):
1649         (print_mve_vld_str_addr): New print function.
1650         (is_mve_undefined): Handle new instructions.
1651         (is_mve_unpredictable): Likewise.
1652         (print_mve_undefined): Likewise.
1653         (print_mve_size): Likewise.
1654         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1655         (print_insn_mve):  Handle new operands.
1656
1657 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1658             Michael Collison <michael.collison@arm.com>
1659
1660         * arm-dis.c (enum mve_instructions): Add new instructions.
1661         (enum mve_unpredictable): Add new reasons.
1662         (is_mve_encoding_conflict): Handle new instructions.
1663         (is_mve_unpredictable): Likewise.
1664         (mve_opcodes): Add new instructions.
1665         (print_mve_unpredictable): Handle new reasons.
1666         (print_mve_register_blocks): New print function.
1667         (print_mve_size): Handle new instructions.
1668         (print_insn_mve): Likewise.
1669
1670 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1671             Michael Collison <michael.collison@arm.com>
1672
1673         * arm-dis.c (enum mve_instructions): Add new instructions.
1674         (enum mve_unpredictable): Add new reasons.
1675         (enum mve_undefined): Likewise.
1676         (is_mve_encoding_conflict): Handle new instructions.
1677         (is_mve_undefined): Likewise.
1678         (is_mve_unpredictable): Likewise.
1679         (coprocessor_opcodes): Move NEON VDUP from here...
1680         (neon_opcodes): ... to here.
1681         (mve_opcodes): Add new instructions.
1682         (print_mve_undefined):  Handle new reasons.
1683         (print_mve_unpredictable): Likewise.
1684         (print_mve_size): Handle new instructions.
1685         (print_insn_neon): Handle vdup.
1686         (print_insn_mve): Handle new operands.
1687
1688 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1689             Michael Collison <michael.collison@arm.com>
1690
1691         * arm-dis.c (enum mve_instructions): Add new instructions.
1692         (enum mve_unpredictable): Add new values.
1693         (mve_opcodes): Add new instructions.
1694         (vec_condnames): New array with vector conditions.
1695         (mve_predicatenames): New array with predicate suffixes.
1696         (mve_vec_sizename): New array with vector sizes.
1697         (enum vpt_pred_state): New enum with vector predication states.
1698         (struct vpt_block): New struct type for vpt blocks.
1699         (vpt_block_state): Global struct to keep track of state.
1700         (mve_extract_pred_mask): New helper function.
1701         (num_instructions_vpt_block): Likewise.
1702         (mark_outside_vpt_block): Likewise.
1703         (mark_inside_vpt_block): Likewise.
1704         (invert_next_predicate_state): Likewise.
1705         (update_next_predicate_state): Likewise.
1706         (update_vpt_block_state): Likewise.
1707         (is_vpt_instruction): Likewise.
1708         (is_mve_encoding_conflict): Add entries for new instructions.
1709         (is_mve_unpredictable): Likewise.
1710         (print_mve_unpredictable): Handle new cases.
1711         (print_instruction_predicate): Likewise.
1712         (print_mve_size): New function.
1713         (print_vec_condition): New function.
1714         (print_insn_mve): Handle vpt blocks and new print operands.
1715
1716 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1717
1718         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1719         8, 14 and 15 for Armv8.1-M Mainline.
1720
1721 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1722             Michael Collison <michael.collison@arm.com>
1723
1724         * arm-dis.c (enum mve_instructions): New enum.
1725         (enum mve_unpredictable): Likewise.
1726         (enum mve_undefined): Likewise.
1727         (struct mopcode32): New struct.
1728         (is_mve_okay_in_it): New function.
1729         (is_mve_architecture): Likewise.
1730         (arm_decode_field): Likewise.
1731         (arm_decode_field_multiple): Likewise.
1732         (is_mve_encoding_conflict): Likewise.
1733         (is_mve_undefined): Likewise.
1734         (is_mve_unpredictable): Likewise.
1735         (print_mve_undefined): Likewise.
1736         (print_mve_unpredictable): Likewise.
1737         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1738         (print_insn_mve): New function.
1739         (print_insn_thumb32): Handle MVE architecture.
1740         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1741
1742 2019-05-10  Nick Clifton  <nickc@redhat.com>
1743
1744         PR 24538
1745         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1746         end of the table prematurely.
1747
1748 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1749
1750         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1751         macros for R6.
1752
1753 2019-05-11  Alan Modra  <amodra@gmail.com>
1754
1755         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1756         when -Mraw is in effect.
1757
1758 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1759
1760         * aarch64-dis-2.c: Regenerate.
1761         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1762         (OP_SVE_BBB): New variant set.
1763         (OP_SVE_DDDD): New variant set.
1764         (OP_SVE_HHH): New variant set.
1765         (OP_SVE_HHHU): New variant set.
1766         (OP_SVE_SSS): New variant set.
1767         (OP_SVE_SSSU): New variant set.
1768         (OP_SVE_SHH): New variant set.
1769         (OP_SVE_SBBU): New variant set.
1770         (OP_SVE_DSS): New variant set.
1771         (OP_SVE_DHHU): New variant set.
1772         (OP_SVE_VMV_HSD_BHS): New variant set.
1773         (OP_SVE_VVU_HSD_BHS): New variant set.
1774         (OP_SVE_VVVU_SD_BH): New variant set.
1775         (OP_SVE_VVVU_BHSD): New variant set.
1776         (OP_SVE_VVV_QHD_DBS): New variant set.
1777         (OP_SVE_VVV_HSD_BHS): New variant set.
1778         (OP_SVE_VVV_HSD_BHS2): New variant set.
1779         (OP_SVE_VVV_BHS_HSD): New variant set.
1780         (OP_SVE_VV_BHS_HSD): New variant set.
1781         (OP_SVE_VVV_SD): New variant set.
1782         (OP_SVE_VVU_BHS_HSD): New variant set.
1783         (OP_SVE_VZVV_SD): New variant set.
1784         (OP_SVE_VZVV_BH): New variant set.
1785         (OP_SVE_VZV_SD): New variant set.
1786         (aarch64_opcode_table): Add sve2 instructions.
1787
1788 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1789
1790         * aarch64-asm-2.c: Regenerated.
1791         * aarch64-dis-2.c: Regenerated.
1792         * aarch64-opc-2.c: Regenerated.
1793         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1794         for SVE_SHLIMM_UNPRED_22.
1795         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1796         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1797         operand.
1798
1799 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1800
1801         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1802         sve_size_tsz_bhs iclass encode.
1803         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1804         sve_size_tsz_bhs iclass decode.
1805
1806 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1807
1808         * aarch64-asm-2.c: Regenerated.
1809         * aarch64-dis-2.c: Regenerated.
1810         * aarch64-opc-2.c: Regenerated.
1811         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1812         for SVE_Zm4_11_INDEX.
1813         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1814         (fields): Handle SVE_i2h field.
1815         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1816         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1817
1818 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1819
1820         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1821         sve_shift_tsz_bhsd iclass encode.
1822         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1823         sve_shift_tsz_bhsd iclass decode.
1824
1825 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1826
1827         * aarch64-asm-2.c: Regenerated.
1828         * aarch64-dis-2.c: Regenerated.
1829         * aarch64-opc-2.c: Regenerated.
1830         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1831         (aarch64_encode_variant_using_iclass): Handle
1832         sve_shift_tsz_hsd iclass encode.
1833         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1834         sve_shift_tsz_hsd iclass decode.
1835         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1836         for SVE_SHRIMM_UNPRED_22.
1837         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1838         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1839         operand.
1840
1841 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1842
1843         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1844         sve_size_013 iclass encode.
1845         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1846         sve_size_013 iclass decode.
1847
1848 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1849
1850         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1851         sve_size_bh iclass encode.
1852         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1853         sve_size_bh iclass decode.
1854
1855 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1856
1857         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1858         sve_size_sd2 iclass encode.
1859         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1860         sve_size_sd2 iclass decode.
1861         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1862         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1863
1864 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1865
1866         * aarch64-asm-2.c: Regenerated.
1867         * aarch64-dis-2.c: Regenerated.
1868         * aarch64-opc-2.c: Regenerated.
1869         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1870         for SVE_ADDR_ZX.
1871         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1872         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1873
1874 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1875
1876         * aarch64-asm-2.c: Regenerated.
1877         * aarch64-dis-2.c: Regenerated.
1878         * aarch64-opc-2.c: Regenerated.
1879         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1880         for SVE_Zm3_11_INDEX.
1881         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1882         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1883         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1884         fields.
1885         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1886
1887 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1888
1889         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1890         sve_size_hsd2 iclass encode.
1891         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1892         sve_size_hsd2 iclass decode.
1893         * aarch64-opc.c (fields): Handle SVE_size field.
1894         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1895
1896 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1897
1898         * aarch64-asm-2.c: Regenerated.
1899         * aarch64-dis-2.c: Regenerated.
1900         * aarch64-opc-2.c: Regenerated.
1901         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1902         for SVE_IMM_ROT3.
1903         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1904         (fields): Handle SVE_rot3 field.
1905         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1906         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1907
1908 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1909
1910         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1911         instructions.
1912
1913 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1914
1915         * aarch64-tbl.h
1916         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1917         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1918         aarch64_feature_sve2bitperm): New feature sets.
1919         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1920         for feature set addresses.
1921         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1922         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1923
1924 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1925             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1926
1927         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1928         argument and set ASE_EVA_R6 appropriately.
1929         (set_default_mips_dis_options): Pass ISA to above.
1930         (parse_mips_dis_option): Likewise.
1931         * mips-opc.c (EVAR6): New macro.
1932         (mips_builtin_opcodes): Add llwpe, scwpe.
1933
1934 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1935
1936         * aarch64-asm-2.c: Regenerated.
1937         * aarch64-dis-2.c: Regenerated.
1938         * aarch64-opc-2.c: Regenerated.
1939         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1940         AARCH64_OPND_TME_UIMM16.
1941         (aarch64_print_operand): Likewise.
1942         * aarch64-tbl.h (QL_IMM_NIL): New.
1943         (TME): New.
1944         (_TME_INSN): New.
1945         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1946
1947 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1948
1949         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1950
1951 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1952             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1953
1954         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1955
1956 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1957
1958         * s12z-opc.h: Add extern "C" bracketing to help
1959         users who wish to use this interface in c++ code.
1960
1961 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1962
1963         * s12z-opc.c (bm_decode): Handle bit map operations with the
1964         "reserved0" mode.
1965
1966 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1967
1968         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1969         specifier.  Add entries for VLDR and VSTR of system registers.
1970         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1971         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1972         of %J and %K format specifier.
1973
1974 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1975
1976         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1977         Add new entries for VSCCLRM instruction.
1978         (print_insn_coprocessor): Handle new %C format control code.
1979
1980 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1981
1982         * arm-dis.c (enum isa): New enum.
1983         (struct sopcode32): New structure.
1984         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1985         set isa field of all current entries to ANY.
1986         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1987         Only match an entry if its isa field allows the current mode.
1988
1989 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1990
1991         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1992         CLRM.
1993         (print_insn_thumb32): Add logic to print %n CLRM register list.
1994
1995 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1996
1997         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1998         and %Q patterns.
1999
2000 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2001
2002         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2003         (print_insn_thumb32): Edit the switch case for %Z.
2004
2005 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2006
2007         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2008
2009 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2010
2011         * arm-dis.c (thumb32_opcodes): New instruction bfl.
2012
2013 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2014
2015         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2016
2017 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2018
2019         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2020         Arm register with r13 and r15 unpredictable.
2021         (thumb32_opcodes): New instructions for bfx and bflx.
2022
2023 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2024
2025         * arm-dis.c (thumb32_opcodes): New instructions for bf.
2026
2027 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2028
2029         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2030
2031 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2032
2033         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2034
2035 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2036
2037         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2038
2039 2019-04-12  John Darrington <john@darrington.wattle.id.au>
2040
2041         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2042         "optr". ("operator" is a reserved word in c++).
2043
2044 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2045
2046         * aarch64-opc.c (aarch64_print_operand): Add case for
2047         AARCH64_OPND_Rt_SP.
2048         (verify_constraints): Likewise.
2049         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2050         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2051         to accept Rt|SP as first operand.
2052         (AARCH64_OPERANDS): Add new Rt_SP.
2053         * aarch64-asm-2.c: Regenerated.
2054         * aarch64-dis-2.c: Regenerated.
2055         * aarch64-opc-2.c: Regenerated.
2056
2057 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2058
2059         * aarch64-asm-2.c: Regenerated.
2060         * aarch64-dis-2.c: Likewise.
2061         * aarch64-opc-2.c: Likewise.
2062         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2063
2064 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
2065
2066         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2067
2068 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
2069
2070         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2071         * i386-init.h: Regenerated.
2072
2073 2019-04-07  Alan Modra  <amodra@gmail.com>
2074
2075         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2076         op_separator to control printing of spaces, comma and parens
2077         rather than need_comma, need_paren and spaces vars.
2078
2079 2019-04-07  Alan Modra  <amodra@gmail.com>
2080
2081         PR 24421
2082         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2083         (print_insn_neon, print_insn_arm): Likewise.
2084
2085 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
2086
2087         * i386-dis-evex.h (evex_table): Updated to support BF16
2088         instructions.
2089         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2090         and EVEX_W_0F3872_P_3.
2091         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2092         (cpu_flags): Add bitfield for CpuAVX512_BF16.
2093         * i386-opc.h (enum): Add CpuAVX512_BF16.
2094         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2095         * i386-opc.tbl: Add AVX512 BF16 instructions.
2096         * i386-init.h: Regenerated.
2097         * i386-tbl.h: Likewise.
2098
2099 2019-04-05  Alan Modra  <amodra@gmail.com>
2100
2101         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2102         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2103         to favour printing of "-" branch hint when using the "y" bit.
2104         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2105
2106 2019-04-05  Alan Modra  <amodra@gmail.com>
2107
2108         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2109         opcode until first operand is output.
2110
2111 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2112
2113         PR gas/24349
2114         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2115         (valid_bo_post_v2): Add support for 'at' branch hints.
2116         (insert_bo): Only error on branch on ctr.
2117         (get_bo_hint_mask): New function.
2118         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2119         for inserting 'at' branch hints.
2120         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2121         for extracting 'at' branch hints.
2122         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2123         (BOE): Delete operand.
2124         (BOM, BOP): New operands.
2125         (RM): Update value.
2126         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2127         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2128         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2129         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2130         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2131         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2132         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2133         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2134         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2135         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2136         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2137         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2138         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2139         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2140         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2141         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2142         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2143         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2144         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2145         bttarl+>: New extended mnemonics.
2146
2147 2019-03-28  Alan Modra  <amodra@gmail.com>
2148
2149         PR 24390
2150         * ppc-opc.c (BTF): Define.
2151         (powerpc_opcodes): Use for mtfsb*.
2152         * ppc-dis.c (print_insn_powerpc): Print fields with both
2153         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2154
2155 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2156
2157         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2158         (mapping_symbol_for_insn): Implement new algorithm.
2159         (print_insn): Remove duplicate code.
2160
2161 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2162
2163         * aarch64-dis.c (print_insn_aarch64):
2164         Implement override.
2165
2166 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2167
2168         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2169         order.
2170
2171 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2172
2173         * aarch64-dis.c (last_stop_offset): New.
2174         (print_insn_aarch64): Use stop_offset.
2175
2176 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2177
2178         PR gas/24359
2179         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2180         CPU_ANY_AVX2_FLAGS.
2181         * i386-init.h: Regenerated.
2182
2183 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2184
2185         PR gas/24348
2186         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2187         vmovdqu16, vmovdqu32 and vmovdqu64.
2188         * i386-tbl.h: Regenerated.
2189
2190 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2191
2192         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2193         from vstrszb, vstrszh, and vstrszf.
2194
2195 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2196
2197         * s390-opc.txt: Add instruction descriptions.
2198
2199 2019-02-08  Jim Wilson  <jimw@sifive.com>
2200
2201         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2202         <bne>: Likewise.
2203
2204 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2205
2206         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2207
2208 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2209
2210         PR binutils/23212
2211         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2212         * aarch64-opc.c (verify_elem_sd): New.
2213         (fields): Add FLD_sz entr.
2214         * aarch64-tbl.h (_SIMD_INSN): New.
2215         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2216         fmulx scalar and vector by element isns.
2217
2218 2019-02-07  Nick Clifton  <nickc@redhat.com>
2219
2220         * po/sv.po: Updated Swedish translation.
2221
2222 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2223
2224         * s390-mkopc.c (main): Accept arch13 as cpu string.
2225         * s390-opc.c: Add new instruction formats and instruction opcode
2226         masks.
2227         * s390-opc.txt: Add new arch13 instructions.
2228
2229 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2230
2231         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2232         (aarch64_opcode): Change encoding for stg, stzg
2233         st2g and st2zg.
2234         * aarch64-asm-2.c: Regenerated.
2235         * aarch64-dis-2.c: Regenerated.
2236         * aarch64-opc-2.c: Regenerated.
2237
2238 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2239
2240         * aarch64-asm-2.c: Regenerated.
2241         * aarch64-dis-2.c: Likewise.
2242         * aarch64-opc-2.c: Likewise.
2243         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2244
2245 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2246             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2247
2248         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2249         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2250         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2251         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2252         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2253         case for ldstgv_indexed.
2254         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2255         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2256         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2257         * aarch64-asm-2.c: Regenerated.
2258         * aarch64-dis-2.c: Regenerated.
2259         * aarch64-opc-2.c: Regenerated.
2260
2261 2019-01-23  Nick Clifton  <nickc@redhat.com>
2262
2263         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2264
2265 2019-01-21  Nick Clifton  <nickc@redhat.com>
2266
2267         * po/de.po: Updated German translation.
2268         * po/uk.po: Updated Ukranian translation.
2269
2270 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2271         * mips-dis.c (mips_arch_choices): Fix typo in
2272         gs464, gs464e and gs264e descriptors.
2273
2274 2019-01-19  Nick Clifton  <nickc@redhat.com>
2275
2276         * configure: Regenerate.
2277         * po/opcodes.pot: Regenerate.
2278
2279 2018-06-24  Nick Clifton  <nickc@redhat.com>
2280
2281         2.32 branch created.
2282
2283 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2284
2285         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2286         if it is null.
2287         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2288         zero.
2289
2290 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2291
2292         * configure: Regenerate.
2293
2294 2019-01-07  Alan Modra  <amodra@gmail.com>
2295
2296         * configure: Regenerate.
2297         * po/POTFILES.in: Regenerate.
2298
2299 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2300
2301         * s12z-opc.c: New file.
2302         * s12z-opc.h: New file.
2303         * s12z-dis.c: Removed all code not directly related to display
2304         of instructions.  Used the interface provided by the new files
2305         instead.
2306         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2307         * Makefile.in: Regenerate.
2308         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2309         * configure: Regenerate.
2310
2311 2019-01-01  Alan Modra  <amodra@gmail.com>
2312
2313         Update year range in copyright notice of all files.
2314
2315 For older changes see ChangeLog-2018
2316 \f
2317 Copyright (C) 2019 Free Software Foundation, Inc.
2318
2319 Copying and distribution of this file, with or without modification,
2320 are permitted in any medium without royalty provided the copyright
2321 notice and this notice are preserved.
2322
2323 Local Variables:
2324 mode: change-log
2325 left-margin: 8
2326 fill-column: 74
2327 version-control: never
2328 End: