opcodes/ChangeLog

   1 2019-12-16  Alan Modra  <amodra@gmail.com>
   2
   3         * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
   4
   5 2019-12-16  Alan Modra  <amodra@gmail.com>
   6
   7         * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
   8         (struct objdump_disasm_info): Delete.
   9         (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
  10         N32_IMMS to unsigned before shifting left.
  11
  12 2019-12-16  Alan Modra  <amodra@gmail.com>
  13
  14         * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
  15         (print_insn_moxie): Remove unnecessary cast.
  16
  17 2019-12-12  Alan Modra  <amodra@gmail.com>
  18
  19         * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
  20         mask.
  21
  22 2019-12-11  Alan Modra  <amodra@gmail.com>
  23
  24         * arc-dis.c (BITS): Don't truncate high bits with shifts.
  25         * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
  26         * tic54x-dis.c (print_instruction): Likewise.
  27         * tilegx-opc.c (parse_insn_tilegx): Likewise.
  28         * tilepro-opc.c (parse_insn_tilepro): Likewise.
  29         * visium-dis.c (disassem_class0): Likewise.
  30         * pdp11-dis.c (sign_extend): Likewise.
  31         (SIGN_BITS): Delete.
  32         * epiphany-ibld.c: Regenerate.
  33         * lm32-ibld.c: Regenerate.
  34         * m32c-ibld.c: Regenerate.
  35
  36 2019-12-11  Alan Modra  <amodra@gmail.com>
  37
  38         * ns32k-dis.c (sign_extend): Correct last patch.
  39
  40 2019-12-11  Alan Modra  <amodra@gmail.com>
  41
  42         * vax-dis.c (NEXTLONG): Avoid signed overflow.
  43
  44 2019-12-11  Alan Modra  <amodra@gmail.com>
  45
  46         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
  47         sign extend using shifts.
  48
  49 2019-12-11  Alan Modra  <amodra@gmail.com>
  50
  51         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
  52
  53 2019-12-11  Alan Modra  <amodra@gmail.com>
  54
  55         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
  56         on NULL registertable entry.
  57         (tic4x_hash_opcode): Use unsigned arithmetic.
  58
  59 2019-12-11  Alan Modra  <amodra@gmail.com>
  60
  61         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
  62
  63 2019-12-11  Alan Modra  <amodra@gmail.com>
  64
  65         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
  66         (bit_extract_simple, sign_extend): Likewise.
  67
  68 2019-12-11  Alan Modra  <amodra@gmail.com>
  69
  70         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
  71
  72 2019-12-11  Alan Modra  <amodra@gmail.com>
  73
  74         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
  75
  76 2019-12-11  Alan Modra  <amodra@gmail.com>
  77
  78         * m68k-dis.c (COERCE32): Cast value first.
  79         (NEXTLONG, NEXTULONG): Avoid signed overflow.
  80
  81 2019-12-11  Alan Modra  <amodra@gmail.com>
  82
  83         * h8300-dis.c (extract_immediate): Avoid signed overflow.
  84         (bfd_h8_disassemble): Likewise.
  85
  86 2019-12-11  Alan Modra  <amodra@gmail.com>
  87
  88         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
  89         past end of operands array.
  90
  91 2019-12-11  Alan Modra  <amodra@gmail.com>
  92
  93         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
  94         overflow when collecting bytes of a number.
  95
  96 2019-12-11  Alan Modra  <amodra@gmail.com>
  97
  98         * cris-dis.c (print_with_operands): Avoid signed integer
  99         overflow when collecting bytes of a 32-bit integer.
 100
 101 2019-12-11  Alan Modra  <amodra@gmail.com>
 102
 103         * cr16-dis.c (EXTRACT, SBM): Rewrite.
 104         (cr16_match_opcode): Delete duplicate bcond test.
 105
 106 2019-12-11  Alan Modra  <amodra@gmail.com>
 107
 108         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
 109         (SIGNBIT): New.
 110         (MASKBITS, SIGNEXTEND): Rewrite.
 111         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
 112         unsigned arithmetic, instead assign result of SIGNEXTEND back
 113         to x.
 114         (fmtconst_val): Use 1u in shift expression.
 115
 116 2019-12-11  Alan Modra  <amodra@gmail.com>
 117
 118         * arc-dis.c (find_format_from_table): Use ull constant when
 119         shifting by up to 32.
 120
 121 2019-12-11  Alan Modra  <amodra@gmail.com>
 122
 123         PR 25270
 124         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
 125         false when field is zero for sve_size_tsz_bhs.
 126
 127 2019-12-11  Alan Modra  <amodra@gmail.com>
 128
 129         * epiphany-ibld.c: Regenerate.
 130
 131 2019-12-10  Alan Modra  <amodra@gmail.com>
 132
 133         PR 24960
 134         * disassemble.c (disassemble_free_target): New function.
 135
 136 2019-12-10  Alan Modra  <amodra@gmail.com>
 137
 138         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 139         * disassemble.c (disassemble_init_for_target): Likewise.
 140         * bpf-dis.c: Regenerate.
 141         * epiphany-dis.c: Regenerate.
 142         * fr30-dis.c: Regenerate.
 143         * frv-dis.c: Regenerate.
 144         * ip2k-dis.c: Regenerate.
 145         * iq2000-dis.c: Regenerate.
 146         * lm32-dis.c: Regenerate.
 147         * m32c-dis.c: Regenerate.
 148         * m32r-dis.c: Regenerate.
 149         * mep-dis.c: Regenerate.
 150         * mt-dis.c: Regenerate.
 151         * or1k-dis.c: Regenerate.
 152         * xc16x-dis.c: Regenerate.
 153         * xstormy16-dis.c: Regenerate.
 154
 155 2019-12-10  Alan Modra  <amodra@gmail.com>
 156
 157         * ppc-dis.c (private): Delete variable.
 158         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 159         (powerpc_init_dialect): Don't use global private.
 160
 161 2019-12-10  Alan Modra  <amodra@gmail.com>
 162
 163         * s12z-opc.c: Formatting.
 164
 165 2019-12-08  Alan Modra  <amodra@gmail.com>
 166
 167         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 168         registers.
 169
 170 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 171
 172         * aarch64-tbl.h (aarch64_feature_crypto,
 173         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 174         CRYPTO_V8_2_INSN): Delete.
 175
 176 2019-12-05  Alan Modra  <amodra@gmail.com>
 177
 178         PR 25249
 179         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 180         (struct string_buf): New.
 181         (strbuf): New function.
 182         (get_field): Use strbuf rather than strdup of local temp.
 183         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 184         (get_field_rfsl, get_field_imm15): Likewise.
 185         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 186         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 187         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 188         get_field functions.
 189
 190 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 191
 192         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 193         * i386-tbl.h: Re-generate.
 194
 195 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 196
 197         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 198
 199 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 200
 201         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 202         forms.
 203         (xbegin): Drop DefaultSize.
 204         * i386-tbl.h: Re-generate.
 205
 206 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 207
 208         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 209         Change the coproc CRC conditions to use the extension
 210         feature set, second word, base on ARM_EXT2_CRC.
 211
 212 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 213
 214         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 215         * i386-tbl.h: Re-generate.
 216
 217 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 218
 219         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 220         JumpInterSegment, and JumpAbsolute entries.
 221         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 222         JUMP_ABSOLUTE): Define.
 223         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 224         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 225         fields.
 226         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 227         JumpInterSegment): Define.
 228         * i386-tbl.h: Re-generate.
 229
 230 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 231
 232         * i386-gen.c (operand_type_init): Remove
 233         OPERAND_TYPE_JUMPABSOLUTE entry.
 234         (opcode_modifiers): Add JumpAbsolute entry.
 235         (operand_types): Remove JumpAbsolute entry.
 236         * i386-opc.h (JumpAbsolute): Move between enums.
 237         (struct i386_opcode_modifier): Add jumpabsolute field.
 238         (union i386_operand_type): Remove jumpabsolute field.
 239         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 240         * i386-init.h, i386-tbl.h: Re-generate.
 241
 242 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 243
 244         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 245         (operand_types): Remove AnySize entry.
 246         * i386-opc.h (AnySize): Move between enums.
 247         (struct i386_opcode_modifier): Add anysize field.
 248         (OTUnused): Un-comment.
 249         (union i386_operand_type): Remove anysize field.
 250         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 251         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 252         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 253         AnySize.
 254         * i386-tbl.h: Re-generate.
 255
 256 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 257
 258         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 259         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 260         use the floating point register (FPR).
 261
 262 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 263
 264         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 265         cmode 1101.
 266         (is_mve_encoding_conflict): Update cmode conflict checks for
 267         MVE_VMVN_IMM.
 268
 269 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 270
 271         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 272         entry.
 273         (operand_types): Remove EsSeg entry.
 274         (main): Replace stale use of OTMax.
 275         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 276         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 277         (EsSeg): Delete.
 278         (OTUnused): Comment out.
 279         (union i386_operand_type): Remove esseg field.
 280         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 281         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 282         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 283         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 284         * i386-init.h, i386-tbl.h: Re-generate.
 285
 286 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 287
 288         * i386-gen.c (operand_instances): Add RegB entry.
 289         * i386-opc.h (enum operand_instance): Add RegB.
 290         * i386-opc.tbl (RegC, RegD, RegB): Define.
 291         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 292         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 293         monitorx, mwaitx): Drop ImmExt and convert encodings
 294         accordingly.
 295         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 296         (edx, rdx): Add Instance=RegD.
 297         (ebx, rbx): Add Instance=RegB.
 298         * i386-tbl.h: Re-generate.
 299
 300 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 301
 302         * i386-gen.c (operand_type_init): Adjust
 303         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 304         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 305         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 306         (operand_instances): New.
 307         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 308         (output_operand_type): New parameter "instance". Process it.
 309         (process_i386_operand_type): New local variable "instance".
 310         (main): Adjust static assertions.
 311         * i386-opc.h (INSTANCE_WIDTH): Define.
 312         (enum operand_instance): New.
 313         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 314         (union i386_operand_type): Replace acc, inoutportreg, and
 315         shiftcount by instance.
 316         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 317         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 318         Add Instance=.
 319         * i386-init.h, i386-tbl.h: Re-generate.
 320
 321 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 322
 323         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 324         smaxp/sminp entries' "tied_operand" field to 2.
 325
 326 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 327
 328         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 329         "index" local variable by that of the already existing "num".
 330
 331 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 332
 333         PR gas/25167
 334         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 335         * i386-tbl.h: Regenerated.
 336
 337 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 338
 339         * i386-gen.c (operand_type_init): Add Class= to
 340         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 341         OPERAND_TYPE_REGBND entry.
 342         (operand_classes): Add RegMask and RegBND entries.
 343         (operand_types): Drop RegMask and RegBND entry.
 344         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 345         (RegMask, RegBND): Delete.
 346         (union i386_operand_type): Remove regmask and regbnd fields.
 347         * i386-opc.tbl (RegMask, RegBND): Define.
 348         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 349         Class=RegBND.
 350         * i386-init.h, i386-tbl.h: Re-generate.
 351
 352 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 353
 354         * i386-gen.c (operand_type_init): Add Class= to
 355         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 356         OPERAND_TYPE_REGZMM entries.
 357         (operand_classes): Add RegMMX and RegSIMD entries.
 358         (operand_types): Drop RegMMX and RegSIMD entries.
 359         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 360         (RegMMX, RegSIMD): Delete.
 361         (union i386_operand_type): Remove regmmx and regsimd fields.
 362         * i386-opc.tbl (RegMMX): Define.
 363         (RegXMM, RegYMM, RegZMM): Add Class=.
 364         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 365         Class=RegSIMD.
 366         * i386-init.h, i386-tbl.h: Re-generate.
 367
 368 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 369
 370         * i386-gen.c (operand_type_init): Add Class= to
 371         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 372         entries.
 373         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 374         (operand_types): Drop Control, Debug, and Test entries.
 375         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 376         (Control, Debug, Test): Delete.
 377         (union i386_operand_type): Remove control, debug, and test
 378         fields.
 379         * i386-opc.tbl (Control, Debug, Test): Define.
 380         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 381         Class=RegDR, and Test by Class=RegTR.
 382         * i386-init.h, i386-tbl.h: Re-generate.
 383
 384 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 385
 386         * i386-gen.c (operand_type_init): Add Class= to
 387         OPERAND_TYPE_SREG entry.
 388         (operand_classes): Add SReg entry.
 389         (operand_types): Drop SReg entry.
 390         * i386-opc.h (enum operand_class): Add SReg.
 391         (SReg): Delete.
 392         (union i386_operand_type): Remove sreg field.
 393         * i386-opc.tbl (SReg): Define.
 394         * i386-reg.tbl: Replace SReg by Class=SReg.
 395         * i386-init.h, i386-tbl.h: Re-generate.
 396
 397 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 398
 399         * i386-gen.c (operand_type_init): Add Class=. New
 400         OPERAND_TYPE_ANYIMM entry.
 401         (operand_classes): New.
 402         (operand_types): Drop Reg entry.
 403         (output_operand_type): New parameter "class". Process it.
 404         (process_i386_operand_type): New local variable "class".
 405         (main): Adjust static assertions.
 406         * i386-opc.h (CLASS_WIDTH): Define.
 407         (enum operand_class): New.
 408         (Reg): Replace by Class. Adjust comment.
 409         (union i386_operand_type): Replace reg by class.
 410         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 411         Class=.
 412         * i386-reg.tbl: Replace Reg by Class=Reg.
 413         * i386-init.h: Re-generate.
 414
 415 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 416
 417         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 418         (aarch64_opcode_table): Add data gathering hint mnemonic.
 419         * opcodes/aarch64-dis-2.c: Account for new instruction.
 420
 421 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 422
 423         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 424
 425
 426 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 427
 428         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 429         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 430         aarch64_feature_f64mm): New feature sets.
 431         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 432         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 433         instructions.
 434         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 435         macros.
 436         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 437         (OP_SVE_QQQ): New qualifier.
 438         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 439         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 440         the movprfx constraint.
 441         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 442         (aarch64_opcode_table): Define new instructions smmla,
 443         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 444         uzip{1/2}, trn{1/2}.
 445         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 446         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 447         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 448         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 449         Account for new instructions.
 450         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 451         S4x32 operand.
 452         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 453
 454 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 455 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 456
 457         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 458         Armv8.6-A.
 459         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 460         (neon_opcodes): Add bfloat SIMD instructions.
 461         (print_insn_coprocessor): Add new control character %b to print
 462         condition code without checking cp_num.
 463         (print_insn_neon): Account for BFloat16 instructions that have no
 464         special top-byte handling.
 465
 466 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 467 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 468
 469         * arm-dis.c (print_insn_coprocessor,
 470         print_insn_generic_coprocessor): Create wrapper functions around
 471         the implementation of the print_insn_coprocessor control codes.
 472         (print_insn_coprocessor_1): Original print_insn_coprocessor
 473         function that now takes which array to look at as an argument.
 474         (print_insn_arm): Use both print_insn_coprocessor and
 475         print_insn_generic_coprocessor.
 476         (print_insn_thumb32): As above.
 477
 478 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 479 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 480
 481         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 482         in reglane special case.
 483         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 484         aarch64_find_next_opcode): Account for new instructions.
 485         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 486         in reglane special case.
 487         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 488         new AARCH64_OPND_QLF_S_2H qualifier.
 489         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 490         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 491         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 492         sets.
 493         (BFLOAT_SVE, BFLOAT): New feature set macros.
 494         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 495         instructions.
 496         (aarch64_opcode_table): Define new instructions bfdot,
 497         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 498         bfcvtn2, bfcvt.
 499
 500 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 501 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 502
 503         * aarch64-tbl.h (ARMV8_6): New macro.
 504
 505 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 506
 507         * i386-dis.c (prefix_table): Add mcommit.
 508         (rm_table): Add rdpru.
 509         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 510         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 511         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 512         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 513         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 514         * i386-opc.tbl (mcommit, rdpru): New.
 515         * i386-init.h, i386-tbl.h: Re-generate.
 516
 517 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 518
 519         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 520         "names32" instead.
 521         (OP_Monitor): Drop local variable "op1_names", re-purpose
 522         "names" for it instead, and replace former "names" uses by
 523         "names32" ones.
 524
 525 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 526
 527         PR/gas 25167
 528         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 529         operand-less forms.
 530         * opcodes/i386-tbl.h: Re-generate.
 531
 532 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 533
 534         * i386-dis.c (OP_Mwaitx): Delete.
 535         (prefix_table): Use OP_Mwait for mwaitx entry.
 536         (OP_Mwait): Also handle mwaitx.
 537
 538 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 539
 540         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 541         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 542         (prefix_table): Add respective entries.
 543         (rm_table): Link to those entries.
 544
 545 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 546
 547         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 548         (REG_0F1C_P_0_MOD_0): ... this.
 549         (REG_0F1E_MOD_3): Rename to ...
 550         (REG_0F1E_P_1_MOD_3): ... this.
 551         (RM_0F01_REG_5): Rename to ...
 552         (RM_0F01_REG_5_MOD_3): ... this.
 553         (RM_0F01_REG_7): Rename to ...
 554         (RM_0F01_REG_7_MOD_3): ... this.
 555         (RM_0F1E_MOD_3_REG_7): Rename to ...
 556         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 557         (RM_0FAE_REG_6): Rename to ...
 558         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 559         (RM_0FAE_REG_7): Rename to ...
 560         (RM_0FAE_REG_7_MOD_3): ... this.
 561         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 562         (PREFIX_0F01_REG_5_MOD_0): ... this.
 563         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 564         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 565         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 566         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 567         (PREFIX_0FAE_REG_0): Rename to ...
 568         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 569         (PREFIX_0FAE_REG_1): Rename to ...
 570         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 571         (PREFIX_0FAE_REG_2): Rename to ...
 572         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 573         (PREFIX_0FAE_REG_3): Rename to ...
 574         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 575         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 576         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 577         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 578         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 579         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 580         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 581         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 582         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 583         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 584         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 585         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 586         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 587         (PREFIX_0FAE_REG_7): Rename to ...
 588         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 589         (PREFIX_MOD_0_0FC3): Rename to ...
 590         (PREFIX_0FC3_MOD_0): ... this.
 591         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 592         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 593         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 594         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 595         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 596         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 597         (reg_table, prefix_table, mod_table, rm_table): Adjust
 598         accordingly.
 599
 600 2019-11-04  Nick Clifton  <nickc@redhat.com>
 601
 602         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 603         of a v850 system register.  Move the v850_sreg_names array into
 604         this function.
 605         (get_v850_reg_name): Likewise for ordinary register names.
 606         (get_v850_vreg_name): Likewise for vector register names.
 607         (get_v850_cc_name): Likewise for condition codes.
 608         * get_v850_float_cc_name): Likewise for floating point condition
 609         codes.
 610         (get_v850_cacheop_name): Likewise for cache-ops.
 611         (get_v850_prefop_name): Likewise for pref-ops.
 612         (disassemble): Use the new accessor functions.
 613
 614 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 615
 616         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 617         immediate for the writeback form of ldraa/ldrab if it is 0.
 618         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 619         * aarch64-opc-2.c: Regenerated.
 620
 621 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 622
 623         * i386-gen.c (operand_type_shorthands): Delete.
 624         (operand_type_init): Expand previous shorthands.
 625         (set_bitfield_from_shorthand): Rename back to ...
 626         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 627         of operand_type_init[].
 628         (set_bitfield): Adjust call to the above function.
 629         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 630         RegXMM, RegYMM, RegZMM): Define.
 631         * i386-reg.tbl: Expand prior shorthands.
 632
 633 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 634
 635         * i386-gen.c (output_i386_opcode): Change order of fields
 636         emitted to output.
 637         * i386-opc.h (struct insn_template): Move operands field.
 638         Convert extension_opcode field to unsigned short.
 639         * i386-tbl.h: Re-generate.
 640
 641 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 642
 643         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 644         of W.
 645         * i386-opc.h (W): Extend comment.
 646         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 647         general purpose variants not allowing for byte operands.
 648         * i386-tbl.h: Re-generate.
 649
 650 2019-10-29  Nick Clifton  <nickc@redhat.com>
 651
 652         * tic30-dis.c (print_branch): Correct size of operand array.
 653
 654 2019-10-29  Nick Clifton  <nickc@redhat.com>
 655
 656         * d30v-dis.c (print_insn): Check that operand index is valid
 657         before attempting to access the operands array.
 658
 659 2019-10-29  Nick Clifton  <nickc@redhat.com>
 660
 661         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 662         locating the bit to be tested.
 663
 664 2019-10-29  Nick Clifton  <nickc@redhat.com>
 665
 666         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 667         values.
 668         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 669         (print_insn_s12z):  Check for illegal size values.
 670
 671 2019-10-28  Nick Clifton  <nickc@redhat.com>
 672
 673         * csky-dis.c (csky_chars_to_number): Check for a negative
 674         count. Use an unsigned integer to construct the return value.
 675
 676 2019-10-28  Nick Clifton  <nickc@redhat.com>
 677
 678         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 679         operand buffer.  Set value to 15 not 13.
 680         (get_register_operand): Use OPERAND_BUFFER_LEN.
 681         (get_indirect_operand): Likewise.
 682         (print_two_operand): Likewise.
 683         (print_three_operand): Likewise.
 684         (print_oar_insn): Likewise.
 685
 686 2019-10-28  Nick Clifton  <nickc@redhat.com>
 687
 688         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 689         (bit_extract_simple): Likewise.
 690         (bit_copy): Likewise.
 691         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 692         index_offset array are not accessed.
 693
 694 2019-10-28  Nick Clifton  <nickc@redhat.com>
 695
 696         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 697         operand.
 698
 699 2019-10-25  Nick Clifton  <nickc@redhat.com>
 700
 701         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 702         access to opcodes.op array element.
 703
 704 2019-10-23  Nick Clifton  <nickc@redhat.com>
 705
 706         * rx-dis.c (get_register_name): Fix spelling typo in error
 707         message.
 708         (get_condition_name, get_flag_name, get_double_register_name)
 709         (get_double_register_high_name, get_double_register_low_name)
 710         (get_double_control_register_name, get_double_condition_name)
 711         (get_opsize_name, get_size_name): Likewise.
 712
 713 2019-10-22  Nick Clifton  <nickc@redhat.com>
 714
 715         * rx-dis.c (get_size_name): New function.  Provides safe
 716         access to name array.
 717         (get_opsize_name): Likewise.
 718         (print_insn_rx): Use the accessor functions.
 719
 720 2019-10-16  Nick Clifton  <nickc@redhat.com>
 721
 722         * rx-dis.c (get_register_name): New function.  Provides safe
 723         access to name array.
 724         (get_condition_name, get_flag_name, get_double_register_name)
 725         (get_double_register_high_name, get_double_register_low_name)
 726         (get_double_control_register_name, get_double_condition_name):
 727         Likewise.
 728         (print_insn_rx): Use the accessor functions.
 729
 730 2019-10-09  Nick Clifton  <nickc@redhat.com>
 731
 732         PR 25041
 733         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 734         instructions.
 735
 736 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 737
 738         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 739         (cmpsd): Likewise. Move EsSeg to other operand.
 740         * opcodes/i386-tbl.h: Re-generate.
 741
 742 2019-09-23  Alan Modra  <amodra@gmail.com>
 743
 744         * m68k-dis.c: Include cpu-m68k.h
 745
 746 2019-09-23  Alan Modra  <amodra@gmail.com>
 747
 748         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 749         "elf/mips.h" earlier.
 750
 751 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 752
 753         PR gas/25012
 754         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 755         with SReg operand.
 756         * i386-tbl.h: Re-generate.
 757
 758 2019-09-18  Alan Modra  <amodra@gmail.com>
 759
 760         * arc-ext.c: Update throughout for bfd section macro changes.
 761
 762 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 763
 764         * Makefile.in: Re-generate.
 765         * configure: Re-generate.
 766
 767 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 768
 769         * riscv-opc.c (riscv_opcodes): Change subset field
 770         to insn_class field for all instructions.
 771         (riscv_insn_types): Likewise.
 772
 773 2019-09-16  Phil Blundell  <pb@pbcl.net>
 774
 775         * configure: Regenerated.
 776
 777 2019-09-10  Miod Vallat  <miod@online.fr>
 778
 779         PR 24982
 780         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 781
 782 2019-09-09  Phil Blundell  <pb@pbcl.net>
 783
 784         binutils 2.33 branch created.
 785
 786 2019-09-03  Nick Clifton  <nickc@redhat.com>
 787
 788         PR 24961
 789         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 790         greater than zero before indexing via (bufcnt -1).
 791
 792 2019-09-03  Nick Clifton  <nickc@redhat.com>
 793
 794         PR 24958
 795         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 796         (MAX_SPEC_REG_NAME_LEN): Define.
 797         (struct mmix_dis_info): Use defined constants for array lengths.
 798         (get_reg_name): New function.
 799         (get_sprec_reg_name): New function.
 800         (print_insn_mmix): Use new functions.
 801
 802 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 803
 804         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 805         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 806         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 807
 808 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 809
 810         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 811         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 812         (aarch64_sys_reg_supported_p): Update checks for the above.
 813
 814 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 815
 816         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 817         cases MVE_SQRSHRL and MVE_UQRSHLL.
 818         (print_insn_mve): Add case for specifier 'k' to check
 819         specific bit of the instruction.
 820
 821 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 822
 823         PR 24854
 824         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 825         encountering an unknown machine type.
 826         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 827         cases return -1 rather than calling abort.
 828
 829 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 830
 831         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 832         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 833         IgnoreSize.
 834         * i386-tbl.h: Re-generate.
 835
 836 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 837
 838         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 839         instructions.
 840
 841 2019-07-30  Mel Chen <mel.chen@sifive.com>
 842
 843         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 844         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 845
 846         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 847         fscsr.
 848
 849 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 850
 851         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 852         and MPY class instructions.
 853         (parse_option): Add nps400 option.
 854         (print_arc_disassembler_options): Add nps400 info.
 855
 856 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 857
 858         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 859         (bspop): Likewise.
 860         (modapp): Likewise.
 861         * arc-opc.c (RAD_CHK): Add.
 862         * arc-tbl.h: Regenerate.
 863
 864 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 865
 866         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 867         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 868
 869 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 870
 871         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 872         instructions as UNPREDICTABLE.
 873
 874 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 875
 876         * bpf-desc.c: Regenerated.
 877
 878 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 879
 880         * i386-gen.c (static_assert): Define.
 881         (main): Use it.
 882         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 883         (Opcode_Modifier_Num): ... this.
 884         (Mem): Delete.
 885
 886 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 887
 888         * i386-gen.c (operand_types): Move RegMem ...
 889         (opcode_modifiers): ... here.
 890         * i386-opc.h (RegMem): Move to opcode modifer enum.
 891         (union i386_operand_type): Move regmem field ...
 892         (struct i386_opcode_modifier): ... here.
 893         * i386-opc.tbl (RegMem): Define.
 894         (mov, movq): Move RegMem on segment, control, debug, and test
 895         register flavors.
 896         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 897         to non-SSE2AVX flavor.
 898         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 899         Move RegMem on register only flavors. Drop IgnoreSize from
 900         legacy encoding flavors.
 901         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 902         flavors.
 903         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 904         register only flavors.
 905         (vmovd): Move RegMem and drop IgnoreSize on register only
 906         flavor. Change opcode and operand order to store form.
 907         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 908
 909 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 910
 911         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 912         entries.
 913         * i386-opc.h (SReg2, SReg3): Replace by ...
 914         (SReg): ... this.
 915         (union i386_operand_type): Replace sreg fields.
 916         * i386-opc.tbl (mov, ): Use SReg.
 917         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 918         register flavors.
 919         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 920         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 921
 922 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 923
 924         * bpf-desc.c: Regenerate.
 925         * bpf-opc.c: Likewise.
 926         * bpf-opc.h: Likewise.
 927
 928 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 929
 930         * bpf-desc.c: Regenerate.
 931         * bpf-opc.c: Likewise.
 932
 933 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 934
 935         * arm-dis.c (print_insn_coprocessor): Rename index to
 936         index_operand.
 937
 938 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 939
 940         * riscv-opc.c (riscv_insn_types): Add r4 type.
 941
 942         * riscv-opc.c (riscv_insn_types): Add b and j type.
 943
 944         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 945         format for sb type and correct s type.
 946
 947 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 948
 949         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 950         SVE FMOV alias of FCPY.
 951
 952 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 953
 954         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 955         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 956
 957 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 958
 959         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 960         registers in an instruction prefixed by MOVPRFX.
 961
 962 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 963
 964         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 965         sve_size_13 icode to account for variant behaviour of
 966         pmull{t,b}.
 967         * aarch64-dis-2.c: Regenerate.
 968         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 969         sve_size_13 icode to account for variant behaviour of
 970         pmull{t,b}.
 971         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 972         (OP_SVE_VVV_Q_D): Add new qualifier.
 973         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 974         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 975         AES and those not.
 976
 977 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 978
 979         * opcodes/i386-gen.c (operand_type_init): Remove
 980         OPERAND_TYPE_VEC_IMM4 entry.
 981         (operand_types): Remove Vec_Imm4.
 982         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 983         (union i386_operand_type): Remove vec_imm4.
 984         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 985         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 986
 987 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 988
 989         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 990         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 991         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 992         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 993         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 994         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 995         * i386-tbl.h: Re-generate.
 996
 997 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 998
 999         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1000         register operands.
1001         * i386-tbl.h: Re-generate.
1002
1003 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1004
1005         * i386-opc.tbl (C): New.
1006         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1007         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1008         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1009         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1010         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1011         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1012         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1013         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1014         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1015         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1016         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1017         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1018         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1019         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1020         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1021         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1022         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1023         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1024         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1025         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1026         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1027         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1028         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1029         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1030         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1031         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1032         flavors.
1033         * i386-tbl.h: Re-generate.
1034
1035 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1036
1037         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1038         register operands.
1039         * i386-tbl.h: Re-generate.
1040
1041 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1042
1043         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1044         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1045         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1046         * i386-tbl.h: Re-generate.
1047
1048 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1049
1050         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1051         Disp8MemShift from register only templates.
1052         * i386-tbl.h: Re-generate.
1053
1054 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1055
1056         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1057         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1058         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1059         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1060         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1061         EVEX_W_0F11_P_3_M_1): Delete.
1062         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1063         EVEX_W_0F11_P_3): New.
1064         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1065         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1066         MOD_EVEX_0F11_PREFIX_3 table entries.
1067         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1068         PREFIX_EVEX_0F11 table entries.
1069         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1070         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1071         EVEX_W_0F11_P_3_M_{0,1} table entries.
1072
1073 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1074
1075         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1076         Delete.
1077
1078 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1079
1080         PR binutils/24719
1081         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1082         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1083         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1084         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1085         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1086         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1087         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1088         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1089         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1090         PREFIX_EVEX_0F38C6_REG_6 entries.
1091         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1092         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1093         EVEX_W_0F38C7_R_6_P_2 entries.
1094         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1095         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1096         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1097         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1098         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1099         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1100         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1101
1102 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1103
1104         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1105         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1106         VEX_LEN_0F2D_P_3): Delete.
1107         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1108         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1109         (prefix_table): ... here.
1110
1111 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1112
1113         * i386-dis.c (Iq): Delete.
1114         (Id): New.
1115         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1116         TBM insns.
1117         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1118         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1119         (OP_E_memory): Also honor needindex when deciding whether an
1120         address size prefix needs printing.
1121         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1122
1123 2019-06-26  Jim Wilson  <jimw@sifive.com>
1124
1125         PR binutils/24739
1126         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1127         Set info->display_endian to info->endian_code.
1128
1129 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1130
1131         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1132         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1133         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1134         OPERAND_TYPE_ACC64 entries.
1135         * i386-init.h: Re-generate.
1136
1137 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1138
1139         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1140         Delete.
1141         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1142         of dqa_mode.
1143         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1144         entries here.
1145         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1146         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1147
1148 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1149
1150         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1151         variables.
1152
1153 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1154
1155         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1156         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1157         movnti.
1158         * i386-opc.tbl (movnti): Add IgnoreSize.
1159         * i386-tbl.h: Re-generate.
1160
1161 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1162
1163         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1164         * i386-tbl.h: Re-generate.
1165
1166 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1167
1168         * i386-dis-evex.h: Break into ...
1169         * i386-dis-evex-len.h: New file.
1170         * i386-dis-evex-mod.h: Likewise.
1171         * i386-dis-evex-prefix.h: Likewise.
1172         * i386-dis-evex-reg.h: Likewise.
1173         * i386-dis-evex-w.h: Likewise.
1174         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1175         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1176         i386-dis-evex-mod.h.
1177
1178 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1179
1180         PR binutils/24700
1181         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1182         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1183         EVEX_W_0F385B_P_2.
1184         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1185         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1186         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1187         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1188         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1189         EVEX_LEN_0F385B_P_2_W_1.
1190         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1191         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1192         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1193         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1194         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1195         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1196         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1197         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1198         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1199         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1200
1201 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1202
1203         PR binutils/24691
1204         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1205         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1206         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1207         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1208         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1209         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1210         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1211         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1212         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1213         EVEX_LEN_0F3A43_P_2_W_1.
1214         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1215         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1216         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1217         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1218         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1219         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1220         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1221         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1222         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1223         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1224         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1225         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1226
1227 2019-06-14  Nick Clifton  <nickc@redhat.com>
1228
1229         * po/fr.po; Updated French translation.
1230
1231 2019-06-13  Stafford Horne  <shorne@gmail.com>
1232
1233         * or1k-asm.c: Regenerated.
1234         * or1k-desc.c: Regenerated.
1235         * or1k-desc.h: Regenerated.
1236         * or1k-dis.c: Regenerated.
1237         * or1k-ibld.c: Regenerated.
1238         * or1k-opc.c: Regenerated.
1239         * or1k-opc.h: Regenerated.
1240         * or1k-opinst.c: Regenerated.
1241
1242 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1243
1244         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1245
1246 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1247
1248         PR binutils/24633
1249         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1250         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1251         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1252         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1253         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1254         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1255         EVEX_LEN_0F3A1B_P_2_W_1.
1256         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1257         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1258         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1259         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1260         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1261         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1262         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1263         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1264
1265 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1266
1267         PR binutils/24626
1268         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1269         EVEX.vvvv when disassembling VEX and EVEX instructions.
1270         (OP_VEX): Set vex.register_specifier to 0 after readding
1271         vex.register_specifier.
1272         (OP_Vex_2src_1): Likewise.
1273         (OP_Vex_2src_2): Likewise.
1274         (OP_LWP_E): Likewise.
1275         (OP_EX_Vex): Don't check vex.register_specifier.
1276         (OP_XMM_Vex): Likewise.
1277
1278 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1279             Lili Cui  <lili.cui@intel.com>
1280
1281         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1282         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1283         instructions.
1284         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1285         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1286         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1287         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1288         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1289         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1290         * i386-init.h: Regenerated.
1291         * i386-tbl.h: Likewise.
1292
1293 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1294             Lili Cui  <lili.cui@intel.com>
1295
1296         * doc/c-i386.texi: Document enqcmd.
1297         * testsuite/gas/i386/enqcmd-intel.d: New file.
1298         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1299         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1300         * testsuite/gas/i386/enqcmd.d: Likewise.
1301         * testsuite/gas/i386/enqcmd.s: Likewise.
1302         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1303         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1304         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1305         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1306         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1307         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1308         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1309         and x86-64-enqcmd.
1310
1311 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1312
1313         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1314
1315 2019-06-03  Alan Modra  <amodra@gmail.com>
1316
1317         * ppc-dis.c (prefix_opcd_indices): Correct size.
1318
1319 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1320
1321         PR gas/24625
1322         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1323         Disp8ShiftVL.
1324         * i386-tbl.h: Regenerated.
1325
1326 2019-05-24  Alan Modra  <amodra@gmail.com>
1327
1328         * po/POTFILES.in: Regenerate.
1329
1330 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1331             Alan Modra  <amodra@gmail.com>
1332
1333         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1334         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1335         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1336         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1337         XTOP>): Define and add entries.
1338         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1339         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1340         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1341         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1342
1343 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1344             Alan Modra  <amodra@gmail.com>
1345
1346         * ppc-dis.c (ppc_opts): Add "future" entry.
1347         (PREFIX_OPCD_SEGS): Define.
1348         (prefix_opcd_indices): New array.
1349         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1350         (lookup_prefix): New function.
1351         (print_insn_powerpc): Handle 64-bit prefix instructions.
1352         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1353         (PMRR, POWERXX): Define.
1354         (prefix_opcodes): New instruction table.
1355         (prefix_num_opcodes): New constant.
1356
1357 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1358
1359         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1360         * configure: Regenerated.
1361         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1362         and cpu/bpf.opc.
1363         (HFILES): Add bpf-desc.h and bpf-opc.h.
1364         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1365         bpf-ibld.c and bpf-opc.c.
1366         (BPF_DEPS): Define.
1367         * Makefile.in: Regenerated.
1368         * disassemble.c (ARCH_bpf): Define.
1369         (disassembler): Add case for bfd_arch_bpf.
1370         (disassemble_init_for_target): Likewise.
1371         (enum epbf_isa_attr): Define.
1372         * disassemble.h: extern print_insn_bpf.
1373         * bpf-asm.c: Generated.
1374         * bpf-opc.h: Likewise.
1375         * bpf-opc.c: Likewise.
1376         * bpf-ibld.c: Likewise.
1377         * bpf-dis.c: Likewise.
1378         * bpf-desc.h: Likewise.
1379         * bpf-desc.c: Likewise.
1380
1381 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1382
1383         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1384         and VMSR with the new operands.
1385
1386 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1387
1388         * arm-dis.c (enum mve_instructions): New enum
1389         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1390         and cneg.
1391         (mve_opcodes): New instructions as above.
1392         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1393         csneg and csel.
1394         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1395
1396 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1397
1398         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1399         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1400         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1401         uqshl, urshrl and urshr.
1402         (is_mve_okay_in_it): Add new instructions to TRUE list.
1403         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1404         (print_insn_mve): Updated to accept new %j,
1405         %<bitfield>m and %<bitfield>n patterns.
1406
1407 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1408
1409         * mips-opc.c (mips_builtin_opcodes): Change source register
1410         constraint for DAUI.
1411
1412 2019-05-20  Nick Clifton  <nickc@redhat.com>
1413
1414         * po/fr.po: Updated French translation.
1415
1416 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1417             Michael Collison <michael.collison@arm.com>
1418
1419         * arm-dis.c (thumb32_opcodes): Add new instructions.
1420         (enum mve_instructions): Likewise.
1421         (enum mve_undefined): Add new reasons.
1422         (is_mve_encoding_conflict): Handle new instructions.
1423         (is_mve_undefined): Likewise.
1424         (is_mve_unpredictable): Likewise.
1425         (print_mve_undefined): Likewise.
1426         (print_mve_size): Likewise.
1427
1428 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1429             Michael Collison <michael.collison@arm.com>
1430
1431         * arm-dis.c (thumb32_opcodes): Add new instructions.
1432         (enum mve_instructions): Likewise.
1433         (is_mve_encoding_conflict): Handle new instructions.
1434         (is_mve_undefined): Likewise.
1435         (is_mve_unpredictable): Likewise.
1436         (print_mve_size): Likewise.
1437
1438 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1439             Michael Collison <michael.collison@arm.com>
1440
1441         * arm-dis.c (thumb32_opcodes): Add new instructions.
1442         (enum mve_instructions): Likewise.
1443         (is_mve_encoding_conflict): Likewise.
1444         (is_mve_unpredictable): Likewise.
1445         (print_mve_size): Likewise.
1446
1447 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1448             Michael Collison <michael.collison@arm.com>
1449
1450         * arm-dis.c (thumb32_opcodes): Add new instructions.
1451         (enum mve_instructions): Likewise.
1452         (is_mve_encoding_conflict): Handle new instructions.
1453         (is_mve_undefined): Likewise.
1454         (is_mve_unpredictable): Likewise.
1455         (print_mve_size): Likewise.
1456
1457 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1458             Michael Collison <michael.collison@arm.com>
1459
1460         * arm-dis.c (thumb32_opcodes): Add new instructions.
1461         (enum mve_instructions): Likewise.
1462         (is_mve_encoding_conflict): Handle new instructions.
1463         (is_mve_undefined): Likewise.
1464         (is_mve_unpredictable): Likewise.
1465         (print_mve_size): Likewise.
1466         (print_insn_mve): Likewise.
1467
1468 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1469             Michael Collison <michael.collison@arm.com>
1470
1471         * arm-dis.c (thumb32_opcodes): Add new instructions.
1472         (print_insn_thumb32): Handle new instructions.
1473
1474 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1475             Michael Collison <michael.collison@arm.com>
1476
1477         * arm-dis.c (enum mve_instructions): Add new instructions.
1478         (enum mve_undefined): Add new reasons.
1479         (is_mve_encoding_conflict): Handle new instructions.
1480         (is_mve_undefined): Likewise.
1481         (is_mve_unpredictable): Likewise.
1482         (print_mve_undefined): Likewise.
1483         (print_mve_size): Likewise.
1484         (print_mve_shift_n): Likewise.
1485         (print_insn_mve): Likewise.
1486
1487 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1488             Michael Collison <michael.collison@arm.com>
1489
1490         * arm-dis.c (enum mve_instructions): Add new instructions.
1491         (is_mve_encoding_conflict): Handle new instructions.
1492         (is_mve_unpredictable): Likewise.
1493         (print_mve_rotate): Likewise.
1494         (print_mve_size): Likewise.
1495         (print_insn_mve): Likewise.
1496
1497 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1498             Michael Collison <michael.collison@arm.com>
1499
1500         * arm-dis.c (enum mve_instructions): Add new instructions.
1501         (is_mve_encoding_conflict): Handle new instructions.
1502         (is_mve_unpredictable): Likewise.
1503         (print_mve_size): Likewise.
1504         (print_insn_mve): Likewise.
1505
1506 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1507             Michael Collison <michael.collison@arm.com>
1508
1509         * arm-dis.c (enum mve_instructions): Add new instructions.
1510         (enum mve_undefined): Add new reasons.
1511         (is_mve_encoding_conflict): Handle new instructions.
1512         (is_mve_undefined): Likewise.
1513         (is_mve_unpredictable): Likewise.
1514         (print_mve_undefined): Likewise.
1515         (print_mve_size): Likewise.
1516         (print_insn_mve): Likewise.
1517
1518 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1519             Michael Collison <michael.collison@arm.com>
1520
1521         * arm-dis.c (enum mve_instructions): Add new instructions.
1522         (is_mve_encoding_conflict): Handle new instructions.
1523         (is_mve_undefined): Likewise.
1524         (is_mve_unpredictable): Likewise.
1525         (print_mve_size): Likewise.
1526         (print_insn_mve): Likewise.
1527
1528 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1529             Michael Collison <michael.collison@arm.com>
1530
1531         * arm-dis.c (enum mve_instructions): Add new instructions.
1532         (enum mve_unpredictable): Add new reasons.
1533         (enum mve_undefined): Likewise.
1534         (is_mve_okay_in_it): Handle new isntructions.
1535         (is_mve_encoding_conflict): Likewise.
1536         (is_mve_undefined): Likewise.
1537         (is_mve_unpredictable): Likewise.
1538         (print_mve_vmov_index): Likewise.
1539         (print_simd_imm8): Likewise.
1540         (print_mve_undefined): Likewise.
1541         (print_mve_unpredictable): Likewise.
1542         (print_mve_size): Likewise.
1543         (print_insn_mve): Likewise.
1544
1545 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1546             Michael Collison <michael.collison@arm.com>
1547
1548         * arm-dis.c (enum mve_instructions): Add new instructions.
1549         (enum mve_unpredictable): Add new reasons.
1550         (enum mve_undefined): Likewise.
1551         (is_mve_encoding_conflict): Handle new instructions.
1552         (is_mve_undefined): Likewise.
1553         (is_mve_unpredictable): Likewise.
1554         (print_mve_undefined): Likewise.
1555         (print_mve_unpredictable): Likewise.
1556         (print_mve_rounding_mode): Likewise.
1557         (print_mve_vcvt_size): Likewise.
1558         (print_mve_size): Likewise.
1559         (print_insn_mve): Likewise.
1560
1561 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1562             Michael Collison <michael.collison@arm.com>
1563
1564         * arm-dis.c (enum mve_instructions): Add new instructions.
1565         (enum mve_unpredictable): Add new reasons.
1566         (enum mve_undefined): Likewise.
1567         (is_mve_undefined): Handle new instructions.
1568         (is_mve_unpredictable): Likewise.
1569         (print_mve_undefined): Likewise.
1570         (print_mve_unpredictable): Likewise.
1571         (print_mve_size): Likewise.
1572         (print_insn_mve): Likewise.
1573
1574 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1575             Michael Collison <michael.collison@arm.com>
1576
1577         * arm-dis.c (enum mve_instructions): Add new instructions.
1578         (enum mve_undefined): Add new reasons.
1579         (insns): Add new instructions.
1580         (is_mve_encoding_conflict):
1581         (print_mve_vld_str_addr): New print function.
1582         (is_mve_undefined): Handle new instructions.
1583         (is_mve_unpredictable): Likewise.
1584         (print_mve_undefined): Likewise.
1585         (print_mve_size): Likewise.
1586         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1587         (print_insn_mve):  Handle new operands.
1588
1589 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1590             Michael Collison <michael.collison@arm.com>
1591
1592         * arm-dis.c (enum mve_instructions): Add new instructions.
1593         (enum mve_unpredictable): Add new reasons.
1594         (is_mve_encoding_conflict): Handle new instructions.
1595         (is_mve_unpredictable): Likewise.
1596         (mve_opcodes): Add new instructions.
1597         (print_mve_unpredictable): Handle new reasons.
1598         (print_mve_register_blocks): New print function.
1599         (print_mve_size): Handle new instructions.
1600         (print_insn_mve): Likewise.
1601
1602 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1603             Michael Collison <michael.collison@arm.com>
1604
1605         * arm-dis.c (enum mve_instructions): Add new instructions.
1606         (enum mve_unpredictable): Add new reasons.
1607         (enum mve_undefined): Likewise.
1608         (is_mve_encoding_conflict): Handle new instructions.
1609         (is_mve_undefined): Likewise.
1610         (is_mve_unpredictable): Likewise.
1611         (coprocessor_opcodes): Move NEON VDUP from here...
1612         (neon_opcodes): ... to here.
1613         (mve_opcodes): Add new instructions.
1614         (print_mve_undefined):  Handle new reasons.
1615         (print_mve_unpredictable): Likewise.
1616         (print_mve_size): Handle new instructions.
1617         (print_insn_neon): Handle vdup.
1618         (print_insn_mve): Handle new operands.
1619
1620 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1621             Michael Collison <michael.collison@arm.com>
1622
1623         * arm-dis.c (enum mve_instructions): Add new instructions.
1624         (enum mve_unpredictable): Add new values.
1625         (mve_opcodes): Add new instructions.
1626         (vec_condnames): New array with vector conditions.
1627         (mve_predicatenames): New array with predicate suffixes.
1628         (mve_vec_sizename): New array with vector sizes.
1629         (enum vpt_pred_state): New enum with vector predication states.
1630         (struct vpt_block): New struct type for vpt blocks.
1631         (vpt_block_state): Global struct to keep track of state.
1632         (mve_extract_pred_mask): New helper function.
1633         (num_instructions_vpt_block): Likewise.
1634         (mark_outside_vpt_block): Likewise.
1635         (mark_inside_vpt_block): Likewise.
1636         (invert_next_predicate_state): Likewise.
1637         (update_next_predicate_state): Likewise.
1638         (update_vpt_block_state): Likewise.
1639         (is_vpt_instruction): Likewise.
1640         (is_mve_encoding_conflict): Add entries for new instructions.
1641         (is_mve_unpredictable): Likewise.
1642         (print_mve_unpredictable): Handle new cases.
1643         (print_instruction_predicate): Likewise.
1644         (print_mve_size): New function.
1645         (print_vec_condition): New function.
1646         (print_insn_mve): Handle vpt blocks and new print operands.
1647
1648 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1649
1650         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1651         8, 14 and 15 for Armv8.1-M Mainline.
1652
1653 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1654             Michael Collison <michael.collison@arm.com>
1655
1656         * arm-dis.c (enum mve_instructions): New enum.
1657         (enum mve_unpredictable): Likewise.
1658         (enum mve_undefined): Likewise.
1659         (struct mopcode32): New struct.
1660         (is_mve_okay_in_it): New function.
1661         (is_mve_architecture): Likewise.
1662         (arm_decode_field): Likewise.
1663         (arm_decode_field_multiple): Likewise.
1664         (is_mve_encoding_conflict): Likewise.
1665         (is_mve_undefined): Likewise.
1666         (is_mve_unpredictable): Likewise.
1667         (print_mve_undefined): Likewise.
1668         (print_mve_unpredictable): Likewise.
1669         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1670         (print_insn_mve): New function.
1671         (print_insn_thumb32): Handle MVE architecture.
1672         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1673
1674 2019-05-10  Nick Clifton  <nickc@redhat.com>
1675
1676         PR 24538
1677         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1678         end of the table prematurely.
1679
1680 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1681
1682         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1683         macros for R6.
1684
1685 2019-05-11  Alan Modra  <amodra@gmail.com>
1686
1687         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1688         when -Mraw is in effect.
1689
1690 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1691
1692         * aarch64-dis-2.c: Regenerate.
1693         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1694         (OP_SVE_BBB): New variant set.
1695         (OP_SVE_DDDD): New variant set.
1696         (OP_SVE_HHH): New variant set.
1697         (OP_SVE_HHHU): New variant set.
1698         (OP_SVE_SSS): New variant set.
1699         (OP_SVE_SSSU): New variant set.
1700         (OP_SVE_SHH): New variant set.
1701         (OP_SVE_SBBU): New variant set.
1702         (OP_SVE_DSS): New variant set.
1703         (OP_SVE_DHHU): New variant set.
1704         (OP_SVE_VMV_HSD_BHS): New variant set.
1705         (OP_SVE_VVU_HSD_BHS): New variant set.
1706         (OP_SVE_VVVU_SD_BH): New variant set.
1707         (OP_SVE_VVVU_BHSD): New variant set.
1708         (OP_SVE_VVV_QHD_DBS): New variant set.
1709         (OP_SVE_VVV_HSD_BHS): New variant set.
1710         (OP_SVE_VVV_HSD_BHS2): New variant set.
1711         (OP_SVE_VVV_BHS_HSD): New variant set.
1712         (OP_SVE_VV_BHS_HSD): New variant set.
1713         (OP_SVE_VVV_SD): New variant set.
1714         (OP_SVE_VVU_BHS_HSD): New variant set.
1715         (OP_SVE_VZVV_SD): New variant set.
1716         (OP_SVE_VZVV_BH): New variant set.
1717         (OP_SVE_VZV_SD): New variant set.
1718         (aarch64_opcode_table): Add sve2 instructions.
1719
1720 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1721
1722         * aarch64-asm-2.c: Regenerated.
1723         * aarch64-dis-2.c: Regenerated.
1724         * aarch64-opc-2.c: Regenerated.
1725         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1726         for SVE_SHLIMM_UNPRED_22.
1727         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1728         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1729         operand.
1730
1731 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1732
1733         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1734         sve_size_tsz_bhs iclass encode.
1735         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1736         sve_size_tsz_bhs iclass decode.
1737
1738 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1739
1740         * aarch64-asm-2.c: Regenerated.
1741         * aarch64-dis-2.c: Regenerated.
1742         * aarch64-opc-2.c: Regenerated.
1743         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1744         for SVE_Zm4_11_INDEX.
1745         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1746         (fields): Handle SVE_i2h field.
1747         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1748         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1749
1750 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1751
1752         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1753         sve_shift_tsz_bhsd iclass encode.
1754         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1755         sve_shift_tsz_bhsd iclass decode.
1756
1757 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1758
1759         * aarch64-asm-2.c: Regenerated.
1760         * aarch64-dis-2.c: Regenerated.
1761         * aarch64-opc-2.c: Regenerated.
1762         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1763         (aarch64_encode_variant_using_iclass): Handle
1764         sve_shift_tsz_hsd iclass encode.
1765         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1766         sve_shift_tsz_hsd iclass decode.
1767         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1768         for SVE_SHRIMM_UNPRED_22.
1769         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1770         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1771         operand.
1772
1773 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1774
1775         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1776         sve_size_013 iclass encode.
1777         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1778         sve_size_013 iclass decode.
1779
1780 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1781
1782         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1783         sve_size_bh iclass encode.
1784         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1785         sve_size_bh iclass decode.
1786
1787 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1788
1789         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1790         sve_size_sd2 iclass encode.
1791         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1792         sve_size_sd2 iclass decode.
1793         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1794         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1795
1796 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1797
1798         * aarch64-asm-2.c: Regenerated.
1799         * aarch64-dis-2.c: Regenerated.
1800         * aarch64-opc-2.c: Regenerated.
1801         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1802         for SVE_ADDR_ZX.
1803         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1804         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1805
1806 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1807
1808         * aarch64-asm-2.c: Regenerated.
1809         * aarch64-dis-2.c: Regenerated.
1810         * aarch64-opc-2.c: Regenerated.
1811         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1812         for SVE_Zm3_11_INDEX.
1813         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1814         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1815         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1816         fields.
1817         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1818
1819 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1820
1821         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1822         sve_size_hsd2 iclass encode.
1823         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1824         sve_size_hsd2 iclass decode.
1825         * aarch64-opc.c (fields): Handle SVE_size field.
1826         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1827
1828 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1829
1830         * aarch64-asm-2.c: Regenerated.
1831         * aarch64-dis-2.c: Regenerated.
1832         * aarch64-opc-2.c: Regenerated.
1833         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1834         for SVE_IMM_ROT3.
1835         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1836         (fields): Handle SVE_rot3 field.
1837         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1838         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1839
1840 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1841
1842         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1843         instructions.
1844
1845 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1846
1847         * aarch64-tbl.h
1848         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1849         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1850         aarch64_feature_sve2bitperm): New feature sets.
1851         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1852         for feature set addresses.
1853         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1854         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1855
1856 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1857             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1858
1859         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1860         argument and set ASE_EVA_R6 appropriately.
1861         (set_default_mips_dis_options): Pass ISA to above.
1862         (parse_mips_dis_option): Likewise.
1863         * mips-opc.c (EVAR6): New macro.
1864         (mips_builtin_opcodes): Add llwpe, scwpe.
1865
1866 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1867
1868         * aarch64-asm-2.c: Regenerated.
1869         * aarch64-dis-2.c: Regenerated.
1870         * aarch64-opc-2.c: Regenerated.
1871         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1872         AARCH64_OPND_TME_UIMM16.
1873         (aarch64_print_operand): Likewise.
1874         * aarch64-tbl.h (QL_IMM_NIL): New.
1875         (TME): New.
1876         (_TME_INSN): New.
1877         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1878
1879 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1880
1881         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1882
1883 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1884             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1885
1886         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1887
1888 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1889
1890         * s12z-opc.h: Add extern "C" bracketing to help
1891         users who wish to use this interface in c++ code.
1892
1893 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1894
1895         * s12z-opc.c (bm_decode): Handle bit map operations with the
1896         "reserved0" mode.
1897
1898 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1899
1900         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1901         specifier.  Add entries for VLDR and VSTR of system registers.
1902         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1903         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1904         of %J and %K format specifier.
1905
1906 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1907
1908         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1909         Add new entries for VSCCLRM instruction.
1910         (print_insn_coprocessor): Handle new %C format control code.
1911
1912 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1913
1914         * arm-dis.c (enum isa): New enum.
1915         (struct sopcode32): New structure.
1916         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1917         set isa field of all current entries to ANY.
1918         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1919         Only match an entry if its isa field allows the current mode.
1920
1921 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1922
1923         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1924         CLRM.
1925         (print_insn_thumb32): Add logic to print %n CLRM register list.
1926
1927 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1928
1929         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1930         and %Q patterns.
1931
1932 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1933
1934         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1935         (print_insn_thumb32): Edit the switch case for %Z.
1936
1937 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1938
1939         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1940
1941 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1942
1943         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1944
1945 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1946
1947         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1948
1949 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1950
1951         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1952         Arm register with r13 and r15 unpredictable.
1953         (thumb32_opcodes): New instructions for bfx and bflx.
1954
1955 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1956
1957         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1958
1959 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1960
1961         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1962
1963 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1964
1965         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1966
1967 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1968
1969         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1970
1971 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1972
1973         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1974         "optr". ("operator" is a reserved word in c++).
1975
1976 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1977
1978         * aarch64-opc.c (aarch64_print_operand): Add case for
1979         AARCH64_OPND_Rt_SP.
1980         (verify_constraints): Likewise.
1981         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1982         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1983         to accept Rt|SP as first operand.
1984         (AARCH64_OPERANDS): Add new Rt_SP.
1985         * aarch64-asm-2.c: Regenerated.
1986         * aarch64-dis-2.c: Regenerated.
1987         * aarch64-opc-2.c: Regenerated.
1988
1989 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1990
1991         * aarch64-asm-2.c: Regenerated.
1992         * aarch64-dis-2.c: Likewise.
1993         * aarch64-opc-2.c: Likewise.
1994         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1995
1996 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1997
1998         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1999
2000 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
2001
2002         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2003         * i386-init.h: Regenerated.
2004
2005 2019-04-07  Alan Modra  <amodra@gmail.com>
2006
2007         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2008         op_separator to control printing of spaces, comma and parens
2009         rather than need_comma, need_paren and spaces vars.
2010
2011 2019-04-07  Alan Modra  <amodra@gmail.com>
2012
2013         PR 24421
2014         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2015         (print_insn_neon, print_insn_arm): Likewise.
2016
2017 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
2018
2019         * i386-dis-evex.h (evex_table): Updated to support BF16
2020         instructions.
2021         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2022         and EVEX_W_0F3872_P_3.
2023         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2024         (cpu_flags): Add bitfield for CpuAVX512_BF16.
2025         * i386-opc.h (enum): Add CpuAVX512_BF16.
2026         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2027         * i386-opc.tbl: Add AVX512 BF16 instructions.
2028         * i386-init.h: Regenerated.
2029         * i386-tbl.h: Likewise.
2030
2031 2019-04-05  Alan Modra  <amodra@gmail.com>
2032
2033         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2034         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2035         to favour printing of "-" branch hint when using the "y" bit.
2036         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2037
2038 2019-04-05  Alan Modra  <amodra@gmail.com>
2039
2040         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2041         opcode until first operand is output.
2042
2043 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2044
2045         PR gas/24349
2046         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2047         (valid_bo_post_v2): Add support for 'at' branch hints.
2048         (insert_bo): Only error on branch on ctr.
2049         (get_bo_hint_mask): New function.
2050         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2051         for inserting 'at' branch hints.
2052         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2053         for extracting 'at' branch hints.
2054         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2055         (BOE): Delete operand.
2056         (BOM, BOP): New operands.
2057         (RM): Update value.
2058         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2059         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2060         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2061         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2062         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2063         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2064         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2065         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2066         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2067         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2068         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2069         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2070         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2071         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2072         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2073         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2074         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2075         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2076         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2077         bttarl+>: New extended mnemonics.
2078
2079 2019-03-28  Alan Modra  <amodra@gmail.com>
2080
2081         PR 24390
2082         * ppc-opc.c (BTF): Define.
2083         (powerpc_opcodes): Use for mtfsb*.
2084         * ppc-dis.c (print_insn_powerpc): Print fields with both
2085         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2086
2087 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2088
2089         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2090         (mapping_symbol_for_insn): Implement new algorithm.
2091         (print_insn): Remove duplicate code.
2092
2093 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2094
2095         * aarch64-dis.c (print_insn_aarch64):
2096         Implement override.
2097
2098 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2099
2100         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2101         order.
2102
2103 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2104
2105         * aarch64-dis.c (last_stop_offset): New.
2106         (print_insn_aarch64): Use stop_offset.
2107
2108 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2109
2110         PR gas/24359
2111         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2112         CPU_ANY_AVX2_FLAGS.
2113         * i386-init.h: Regenerated.
2114
2115 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2116
2117         PR gas/24348
2118         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2119         vmovdqu16, vmovdqu32 and vmovdqu64.
2120         * i386-tbl.h: Regenerated.
2121
2122 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2123
2124         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2125         from vstrszb, vstrszh, and vstrszf.
2126
2127 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2128
2129         * s390-opc.txt: Add instruction descriptions.
2130
2131 2019-02-08  Jim Wilson  <jimw@sifive.com>
2132
2133         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2134         <bne>: Likewise.
2135
2136 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2137
2138         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2139
2140 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2141
2142         PR binutils/23212
2143         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2144         * aarch64-opc.c (verify_elem_sd): New.
2145         (fields): Add FLD_sz entr.
2146         * aarch64-tbl.h (_SIMD_INSN): New.
2147         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2148         fmulx scalar and vector by element isns.
2149
2150 2019-02-07  Nick Clifton  <nickc@redhat.com>
2151
2152         * po/sv.po: Updated Swedish translation.
2153
2154 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2155
2156         * s390-mkopc.c (main): Accept arch13 as cpu string.
2157         * s390-opc.c: Add new instruction formats and instruction opcode
2158         masks.
2159         * s390-opc.txt: Add new arch13 instructions.
2160
2161 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2162
2163         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2164         (aarch64_opcode): Change encoding for stg, stzg
2165         st2g and st2zg.
2166         * aarch64-asm-2.c: Regenerated.
2167         * aarch64-dis-2.c: Regenerated.
2168         * aarch64-opc-2.c: Regenerated.
2169
2170 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2171
2172         * aarch64-asm-2.c: Regenerated.
2173         * aarch64-dis-2.c: Likewise.
2174         * aarch64-opc-2.c: Likewise.
2175         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2176
2177 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2178             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2179
2180         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2181         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2182         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2183         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2184         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2185         case for ldstgv_indexed.
2186         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2187         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2188         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2189         * aarch64-asm-2.c: Regenerated.
2190         * aarch64-dis-2.c: Regenerated.
2191         * aarch64-opc-2.c: Regenerated.
2192
2193 2019-01-23  Nick Clifton  <nickc@redhat.com>
2194
2195         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2196
2197 2019-01-21  Nick Clifton  <nickc@redhat.com>
2198
2199         * po/de.po: Updated German translation.
2200         * po/uk.po: Updated Ukranian translation.
2201
2202 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2203         * mips-dis.c (mips_arch_choices): Fix typo in
2204         gs464, gs464e and gs264e descriptors.
2205
2206 2019-01-19  Nick Clifton  <nickc@redhat.com>
2207
2208         * configure: Regenerate.
2209         * po/opcodes.pot: Regenerate.
2210
2211 2018-06-24  Nick Clifton  <nickc@redhat.com>
2212
2213         2.32 branch created.
2214
2215 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2216
2217         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2218         if it is null.
2219         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2220         zero.
2221
2222 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2223
2224         * configure: Regenerate.
2225
2226 2019-01-07  Alan Modra  <amodra@gmail.com>
2227
2228         * configure: Regenerate.
2229         * po/POTFILES.in: Regenerate.
2230
2231 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2232
2233         * s12z-opc.c: New file.
2234         * s12z-opc.h: New file.
2235         * s12z-dis.c: Removed all code not directly related to display
2236         of instructions.  Used the interface provided by the new files
2237         instead.
2238         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2239         * Makefile.in: Regenerate.
2240         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2241         * configure: Regenerate.
2242
2243 2019-01-01  Alan Modra  <amodra@gmail.com>
2244
2245         Update year range in copyright notice of all files.
2246
2247 For older changes see ChangeLog-2018
2248 \f
2249 Copyright (C) 2019 Free Software Foundation, Inc.
2250
2251 Copying and distribution of this file, with or without modification,
2252 are permitted in any medium without royalty provided the copyright
2253 notice and this notice are preserved.
2254
2255 Local Variables:
2256 mode: change-log
2257 left-margin: 8
2258 fill-column: 74
2259 version-control: never
2260 End: