opcodes/ChangeLog

   1 2019-12-16  Alan Modra  <amodra@gmail.com>
   2
   3         * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
   4
   5 2019-12-16  Alan Modra  <amodra@gmail.com>
   6
   7         * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
   8
   9 2019-12-16  Alan Modra  <amodra@gmail.com>
  10
  11         * xstormy16-ibld.c: Regenerate.
  12
  13 2019-12-16  Alan Modra  <amodra@gmail.com>
  14
  15         * score-dis.c (print_insn_score16): Move rpush/rpop imm field
  16         value adjustment so that it doesn't affect reg field too.
  17
  18 2019-12-16  Alan Modra  <amodra@gmail.com>
  19
  20         * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
  21         (get_number_of_operands, getargtype, getbits, getregname),
  22         (getcopregname, getprocregname, gettrapstring, getcinvstring),
  23         (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
  24         (powerof2, match_opcode, make_instruction, print_arguments),
  25         (print_arg): Delete forward declarations, moving static to..
  26         (getregname, getcopregname, getregliststring): ..these definitions.
  27         (build_mask): Return unsigned int mask.
  28         (match_opcode): Use unsigned int vars.
  29
  30 2019-12-16  Alan Modra  <amodra@gmail.com>
  31
  32         * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
  33
  34 2019-12-16  Alan Modra  <amodra@gmail.com>
  35
  36         * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
  37         (struct objdump_disasm_info): Delete.
  38         (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
  39         N32_IMMS to unsigned before shifting left.
  40
  41 2019-12-16  Alan Modra  <amodra@gmail.com>
  42
  43         * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
  44         (print_insn_moxie): Remove unnecessary cast.
  45
  46 2019-12-12  Alan Modra  <amodra@gmail.com>
  47
  48         * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
  49         mask.
  50
  51 2019-12-11  Alan Modra  <amodra@gmail.com>
  52
  53         * arc-dis.c (BITS): Don't truncate high bits with shifts.
  54         * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
  55         * tic54x-dis.c (print_instruction): Likewise.
  56         * tilegx-opc.c (parse_insn_tilegx): Likewise.
  57         * tilepro-opc.c (parse_insn_tilepro): Likewise.
  58         * visium-dis.c (disassem_class0): Likewise.
  59         * pdp11-dis.c (sign_extend): Likewise.
  60         (SIGN_BITS): Delete.
  61         * epiphany-ibld.c: Regenerate.
  62         * lm32-ibld.c: Regenerate.
  63         * m32c-ibld.c: Regenerate.
  64
  65 2019-12-11  Alan Modra  <amodra@gmail.com>
  66
  67         * ns32k-dis.c (sign_extend): Correct last patch.
  68
  69 2019-12-11  Alan Modra  <amodra@gmail.com>
  70
  71         * vax-dis.c (NEXTLONG): Avoid signed overflow.
  72
  73 2019-12-11  Alan Modra  <amodra@gmail.com>
  74
  75         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
  76         sign extend using shifts.
  77
  78 2019-12-11  Alan Modra  <amodra@gmail.com>
  79
  80         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
  81
  82 2019-12-11  Alan Modra  <amodra@gmail.com>
  83
  84         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
  85         on NULL registertable entry.
  86         (tic4x_hash_opcode): Use unsigned arithmetic.
  87
  88 2019-12-11  Alan Modra  <amodra@gmail.com>
  89
  90         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
  91
  92 2019-12-11  Alan Modra  <amodra@gmail.com>
  93
  94         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
  95         (bit_extract_simple, sign_extend): Likewise.
  96
  97 2019-12-11  Alan Modra  <amodra@gmail.com>
  98
  99         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
 100
 101 2019-12-11  Alan Modra  <amodra@gmail.com>
 102
 103         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
 104
 105 2019-12-11  Alan Modra  <amodra@gmail.com>
 106
 107         * m68k-dis.c (COERCE32): Cast value first.
 108         (NEXTLONG, NEXTULONG): Avoid signed overflow.
 109
 110 2019-12-11  Alan Modra  <amodra@gmail.com>
 111
 112         * h8300-dis.c (extract_immediate): Avoid signed overflow.
 113         (bfd_h8_disassemble): Likewise.
 114
 115 2019-12-11  Alan Modra  <amodra@gmail.com>
 116
 117         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
 118         past end of operands array.
 119
 120 2019-12-11  Alan Modra  <amodra@gmail.com>
 121
 122         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
 123         overflow when collecting bytes of a number.
 124
 125 2019-12-11  Alan Modra  <amodra@gmail.com>
 126
 127         * cris-dis.c (print_with_operands): Avoid signed integer
 128         overflow when collecting bytes of a 32-bit integer.
 129
 130 2019-12-11  Alan Modra  <amodra@gmail.com>
 131
 132         * cr16-dis.c (EXTRACT, SBM): Rewrite.
 133         (cr16_match_opcode): Delete duplicate bcond test.
 134
 135 2019-12-11  Alan Modra  <amodra@gmail.com>
 136
 137         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
 138         (SIGNBIT): New.
 139         (MASKBITS, SIGNEXTEND): Rewrite.
 140         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
 141         unsigned arithmetic, instead assign result of SIGNEXTEND back
 142         to x.
 143         (fmtconst_val): Use 1u in shift expression.
 144
 145 2019-12-11  Alan Modra  <amodra@gmail.com>
 146
 147         * arc-dis.c (find_format_from_table): Use ull constant when
 148         shifting by up to 32.
 149
 150 2019-12-11  Alan Modra  <amodra@gmail.com>
 151
 152         PR 25270
 153         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
 154         false when field is zero for sve_size_tsz_bhs.
 155
 156 2019-12-11  Alan Modra  <amodra@gmail.com>
 157
 158         * epiphany-ibld.c: Regenerate.
 159
 160 2019-12-10  Alan Modra  <amodra@gmail.com>
 161
 162         PR 24960
 163         * disassemble.c (disassemble_free_target): New function.
 164
 165 2019-12-10  Alan Modra  <amodra@gmail.com>
 166
 167         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 168         * disassemble.c (disassemble_init_for_target): Likewise.
 169         * bpf-dis.c: Regenerate.
 170         * epiphany-dis.c: Regenerate.
 171         * fr30-dis.c: Regenerate.
 172         * frv-dis.c: Regenerate.
 173         * ip2k-dis.c: Regenerate.
 174         * iq2000-dis.c: Regenerate.
 175         * lm32-dis.c: Regenerate.
 176         * m32c-dis.c: Regenerate.
 177         * m32r-dis.c: Regenerate.
 178         * mep-dis.c: Regenerate.
 179         * mt-dis.c: Regenerate.
 180         * or1k-dis.c: Regenerate.
 181         * xc16x-dis.c: Regenerate.
 182         * xstormy16-dis.c: Regenerate.
 183
 184 2019-12-10  Alan Modra  <amodra@gmail.com>
 185
 186         * ppc-dis.c (private): Delete variable.
 187         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 188         (powerpc_init_dialect): Don't use global private.
 189
 190 2019-12-10  Alan Modra  <amodra@gmail.com>
 191
 192         * s12z-opc.c: Formatting.
 193
 194 2019-12-08  Alan Modra  <amodra@gmail.com>
 195
 196         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 197         registers.
 198
 199 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 200
 201         * aarch64-tbl.h (aarch64_feature_crypto,
 202         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 203         CRYPTO_V8_2_INSN): Delete.
 204
 205 2019-12-05  Alan Modra  <amodra@gmail.com>
 206
 207         PR 25249
 208         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 209         (struct string_buf): New.
 210         (strbuf): New function.
 211         (get_field): Use strbuf rather than strdup of local temp.
 212         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 213         (get_field_rfsl, get_field_imm15): Likewise.
 214         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 215         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 216         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 217         get_field functions.
 218
 219 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 220
 221         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 222         * i386-tbl.h: Re-generate.
 223
 224 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 225
 226         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 227
 228 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 229
 230         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 231         forms.
 232         (xbegin): Drop DefaultSize.
 233         * i386-tbl.h: Re-generate.
 234
 235 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 236
 237         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 238         Change the coproc CRC conditions to use the extension
 239         feature set, second word, base on ARM_EXT2_CRC.
 240
 241 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 242
 243         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 244         * i386-tbl.h: Re-generate.
 245
 246 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 247
 248         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 249         JumpInterSegment, and JumpAbsolute entries.
 250         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 251         JUMP_ABSOLUTE): Define.
 252         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 253         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 254         fields.
 255         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 256         JumpInterSegment): Define.
 257         * i386-tbl.h: Re-generate.
 258
 259 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 260
 261         * i386-gen.c (operand_type_init): Remove
 262         OPERAND_TYPE_JUMPABSOLUTE entry.
 263         (opcode_modifiers): Add JumpAbsolute entry.
 264         (operand_types): Remove JumpAbsolute entry.
 265         * i386-opc.h (JumpAbsolute): Move between enums.
 266         (struct i386_opcode_modifier): Add jumpabsolute field.
 267         (union i386_operand_type): Remove jumpabsolute field.
 268         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 269         * i386-init.h, i386-tbl.h: Re-generate.
 270
 271 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 272
 273         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 274         (operand_types): Remove AnySize entry.
 275         * i386-opc.h (AnySize): Move between enums.
 276         (struct i386_opcode_modifier): Add anysize field.
 277         (OTUnused): Un-comment.
 278         (union i386_operand_type): Remove anysize field.
 279         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 280         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 281         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 282         AnySize.
 283         * i386-tbl.h: Re-generate.
 284
 285 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 286
 287         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 288         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 289         use the floating point register (FPR).
 290
 291 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 292
 293         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 294         cmode 1101.
 295         (is_mve_encoding_conflict): Update cmode conflict checks for
 296         MVE_VMVN_IMM.
 297
 298 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 299
 300         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 301         entry.
 302         (operand_types): Remove EsSeg entry.
 303         (main): Replace stale use of OTMax.
 304         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 305         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 306         (EsSeg): Delete.
 307         (OTUnused): Comment out.
 308         (union i386_operand_type): Remove esseg field.
 309         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 310         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 311         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 312         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 313         * i386-init.h, i386-tbl.h: Re-generate.
 314
 315 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 316
 317         * i386-gen.c (operand_instances): Add RegB entry.
 318         * i386-opc.h (enum operand_instance): Add RegB.
 319         * i386-opc.tbl (RegC, RegD, RegB): Define.
 320         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 321         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 322         monitorx, mwaitx): Drop ImmExt and convert encodings
 323         accordingly.
 324         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 325         (edx, rdx): Add Instance=RegD.
 326         (ebx, rbx): Add Instance=RegB.
 327         * i386-tbl.h: Re-generate.
 328
 329 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 330
 331         * i386-gen.c (operand_type_init): Adjust
 332         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 333         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 334         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 335         (operand_instances): New.
 336         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 337         (output_operand_type): New parameter "instance". Process it.
 338         (process_i386_operand_type): New local variable "instance".
 339         (main): Adjust static assertions.
 340         * i386-opc.h (INSTANCE_WIDTH): Define.
 341         (enum operand_instance): New.
 342         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 343         (union i386_operand_type): Replace acc, inoutportreg, and
 344         shiftcount by instance.
 345         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 346         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 347         Add Instance=.
 348         * i386-init.h, i386-tbl.h: Re-generate.
 349
 350 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 351
 352         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 353         smaxp/sminp entries' "tied_operand" field to 2.
 354
 355 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 356
 357         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 358         "index" local variable by that of the already existing "num".
 359
 360 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 361
 362         PR gas/25167
 363         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 364         * i386-tbl.h: Regenerated.
 365
 366 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 367
 368         * i386-gen.c (operand_type_init): Add Class= to
 369         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 370         OPERAND_TYPE_REGBND entry.
 371         (operand_classes): Add RegMask and RegBND entries.
 372         (operand_types): Drop RegMask and RegBND entry.
 373         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 374         (RegMask, RegBND): Delete.
 375         (union i386_operand_type): Remove regmask and regbnd fields.
 376         * i386-opc.tbl (RegMask, RegBND): Define.
 377         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 378         Class=RegBND.
 379         * i386-init.h, i386-tbl.h: Re-generate.
 380
 381 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 382
 383         * i386-gen.c (operand_type_init): Add Class= to
 384         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 385         OPERAND_TYPE_REGZMM entries.
 386         (operand_classes): Add RegMMX and RegSIMD entries.
 387         (operand_types): Drop RegMMX and RegSIMD entries.
 388         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 389         (RegMMX, RegSIMD): Delete.
 390         (union i386_operand_type): Remove regmmx and regsimd fields.
 391         * i386-opc.tbl (RegMMX): Define.
 392         (RegXMM, RegYMM, RegZMM): Add Class=.
 393         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 394         Class=RegSIMD.
 395         * i386-init.h, i386-tbl.h: Re-generate.
 396
 397 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 398
 399         * i386-gen.c (operand_type_init): Add Class= to
 400         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 401         entries.
 402         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 403         (operand_types): Drop Control, Debug, and Test entries.
 404         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 405         (Control, Debug, Test): Delete.
 406         (union i386_operand_type): Remove control, debug, and test
 407         fields.
 408         * i386-opc.tbl (Control, Debug, Test): Define.
 409         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 410         Class=RegDR, and Test by Class=RegTR.
 411         * i386-init.h, i386-tbl.h: Re-generate.
 412
 413 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 414
 415         * i386-gen.c (operand_type_init): Add Class= to
 416         OPERAND_TYPE_SREG entry.
 417         (operand_classes): Add SReg entry.
 418         (operand_types): Drop SReg entry.
 419         * i386-opc.h (enum operand_class): Add SReg.
 420         (SReg): Delete.
 421         (union i386_operand_type): Remove sreg field.
 422         * i386-opc.tbl (SReg): Define.
 423         * i386-reg.tbl: Replace SReg by Class=SReg.
 424         * i386-init.h, i386-tbl.h: Re-generate.
 425
 426 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 427
 428         * i386-gen.c (operand_type_init): Add Class=. New
 429         OPERAND_TYPE_ANYIMM entry.
 430         (operand_classes): New.
 431         (operand_types): Drop Reg entry.
 432         (output_operand_type): New parameter "class". Process it.
 433         (process_i386_operand_type): New local variable "class".
 434         (main): Adjust static assertions.
 435         * i386-opc.h (CLASS_WIDTH): Define.
 436         (enum operand_class): New.
 437         (Reg): Replace by Class. Adjust comment.
 438         (union i386_operand_type): Replace reg by class.
 439         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 440         Class=.
 441         * i386-reg.tbl: Replace Reg by Class=Reg.
 442         * i386-init.h: Re-generate.
 443
 444 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 445
 446         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 447         (aarch64_opcode_table): Add data gathering hint mnemonic.
 448         * opcodes/aarch64-dis-2.c: Account for new instruction.
 449
 450 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 451
 452         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 453
 454
 455 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 456
 457         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 458         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 459         aarch64_feature_f64mm): New feature sets.
 460         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 461         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 462         instructions.
 463         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 464         macros.
 465         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 466         (OP_SVE_QQQ): New qualifier.
 467         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 468         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 469         the movprfx constraint.
 470         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 471         (aarch64_opcode_table): Define new instructions smmla,
 472         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 473         uzip{1/2}, trn{1/2}.
 474         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 475         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 476         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 477         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 478         Account for new instructions.
 479         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 480         S4x32 operand.
 481         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 482
 483 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 484 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 485
 486         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 487         Armv8.6-A.
 488         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 489         (neon_opcodes): Add bfloat SIMD instructions.
 490         (print_insn_coprocessor): Add new control character %b to print
 491         condition code without checking cp_num.
 492         (print_insn_neon): Account for BFloat16 instructions that have no
 493         special top-byte handling.
 494
 495 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 496 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 497
 498         * arm-dis.c (print_insn_coprocessor,
 499         print_insn_generic_coprocessor): Create wrapper functions around
 500         the implementation of the print_insn_coprocessor control codes.
 501         (print_insn_coprocessor_1): Original print_insn_coprocessor
 502         function that now takes which array to look at as an argument.
 503         (print_insn_arm): Use both print_insn_coprocessor and
 504         print_insn_generic_coprocessor.
 505         (print_insn_thumb32): As above.
 506
 507 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 508 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 509
 510         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 511         in reglane special case.
 512         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 513         aarch64_find_next_opcode): Account for new instructions.
 514         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 515         in reglane special case.
 516         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 517         new AARCH64_OPND_QLF_S_2H qualifier.
 518         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 519         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 520         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 521         sets.
 522         (BFLOAT_SVE, BFLOAT): New feature set macros.
 523         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 524         instructions.
 525         (aarch64_opcode_table): Define new instructions bfdot,
 526         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 527         bfcvtn2, bfcvt.
 528
 529 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 530 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 531
 532         * aarch64-tbl.h (ARMV8_6): New macro.
 533
 534 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 535
 536         * i386-dis.c (prefix_table): Add mcommit.
 537         (rm_table): Add rdpru.
 538         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 539         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 540         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 541         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 542         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 543         * i386-opc.tbl (mcommit, rdpru): New.
 544         * i386-init.h, i386-tbl.h: Re-generate.
 545
 546 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 547
 548         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 549         "names32" instead.
 550         (OP_Monitor): Drop local variable "op1_names", re-purpose
 551         "names" for it instead, and replace former "names" uses by
 552         "names32" ones.
 553
 554 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 555
 556         PR/gas 25167
 557         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 558         operand-less forms.
 559         * opcodes/i386-tbl.h: Re-generate.
 560
 561 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 562
 563         * i386-dis.c (OP_Mwaitx): Delete.
 564         (prefix_table): Use OP_Mwait for mwaitx entry.
 565         (OP_Mwait): Also handle mwaitx.
 566
 567 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 568
 569         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 570         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 571         (prefix_table): Add respective entries.
 572         (rm_table): Link to those entries.
 573
 574 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 575
 576         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 577         (REG_0F1C_P_0_MOD_0): ... this.
 578         (REG_0F1E_MOD_3): Rename to ...
 579         (REG_0F1E_P_1_MOD_3): ... this.
 580         (RM_0F01_REG_5): Rename to ...
 581         (RM_0F01_REG_5_MOD_3): ... this.
 582         (RM_0F01_REG_7): Rename to ...
 583         (RM_0F01_REG_7_MOD_3): ... this.
 584         (RM_0F1E_MOD_3_REG_7): Rename to ...
 585         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 586         (RM_0FAE_REG_6): Rename to ...
 587         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 588         (RM_0FAE_REG_7): Rename to ...
 589         (RM_0FAE_REG_7_MOD_3): ... this.
 590         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 591         (PREFIX_0F01_REG_5_MOD_0): ... this.
 592         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 593         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 594         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 595         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 596         (PREFIX_0FAE_REG_0): Rename to ...
 597         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 598         (PREFIX_0FAE_REG_1): Rename to ...
 599         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 600         (PREFIX_0FAE_REG_2): Rename to ...
 601         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 602         (PREFIX_0FAE_REG_3): Rename to ...
 603         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 604         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 605         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 606         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 607         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 608         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 609         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 610         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 611         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 612         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 613         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 614         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 615         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 616         (PREFIX_0FAE_REG_7): Rename to ...
 617         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 618         (PREFIX_MOD_0_0FC3): Rename to ...
 619         (PREFIX_0FC3_MOD_0): ... this.
 620         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 621         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 622         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 623         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 624         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 625         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 626         (reg_table, prefix_table, mod_table, rm_table): Adjust
 627         accordingly.
 628
 629 2019-11-04  Nick Clifton  <nickc@redhat.com>
 630
 631         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 632         of a v850 system register.  Move the v850_sreg_names array into
 633         this function.
 634         (get_v850_reg_name): Likewise for ordinary register names.
 635         (get_v850_vreg_name): Likewise for vector register names.
 636         (get_v850_cc_name): Likewise for condition codes.
 637         * get_v850_float_cc_name): Likewise for floating point condition
 638         codes.
 639         (get_v850_cacheop_name): Likewise for cache-ops.
 640         (get_v850_prefop_name): Likewise for pref-ops.
 641         (disassemble): Use the new accessor functions.
 642
 643 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 644
 645         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 646         immediate for the writeback form of ldraa/ldrab if it is 0.
 647         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 648         * aarch64-opc-2.c: Regenerated.
 649
 650 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 651
 652         * i386-gen.c (operand_type_shorthands): Delete.
 653         (operand_type_init): Expand previous shorthands.
 654         (set_bitfield_from_shorthand): Rename back to ...
 655         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 656         of operand_type_init[].
 657         (set_bitfield): Adjust call to the above function.
 658         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 659         RegXMM, RegYMM, RegZMM): Define.
 660         * i386-reg.tbl: Expand prior shorthands.
 661
 662 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 663
 664         * i386-gen.c (output_i386_opcode): Change order of fields
 665         emitted to output.
 666         * i386-opc.h (struct insn_template): Move operands field.
 667         Convert extension_opcode field to unsigned short.
 668         * i386-tbl.h: Re-generate.
 669
 670 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 671
 672         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 673         of W.
 674         * i386-opc.h (W): Extend comment.
 675         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 676         general purpose variants not allowing for byte operands.
 677         * i386-tbl.h: Re-generate.
 678
 679 2019-10-29  Nick Clifton  <nickc@redhat.com>
 680
 681         * tic30-dis.c (print_branch): Correct size of operand array.
 682
 683 2019-10-29  Nick Clifton  <nickc@redhat.com>
 684
 685         * d30v-dis.c (print_insn): Check that operand index is valid
 686         before attempting to access the operands array.
 687
 688 2019-10-29  Nick Clifton  <nickc@redhat.com>
 689
 690         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 691         locating the bit to be tested.
 692
 693 2019-10-29  Nick Clifton  <nickc@redhat.com>
 694
 695         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 696         values.
 697         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 698         (print_insn_s12z):  Check for illegal size values.
 699
 700 2019-10-28  Nick Clifton  <nickc@redhat.com>
 701
 702         * csky-dis.c (csky_chars_to_number): Check for a negative
 703         count. Use an unsigned integer to construct the return value.
 704
 705 2019-10-28  Nick Clifton  <nickc@redhat.com>
 706
 707         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 708         operand buffer.  Set value to 15 not 13.
 709         (get_register_operand): Use OPERAND_BUFFER_LEN.
 710         (get_indirect_operand): Likewise.
 711         (print_two_operand): Likewise.
 712         (print_three_operand): Likewise.
 713         (print_oar_insn): Likewise.
 714
 715 2019-10-28  Nick Clifton  <nickc@redhat.com>
 716
 717         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 718         (bit_extract_simple): Likewise.
 719         (bit_copy): Likewise.
 720         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 721         index_offset array are not accessed.
 722
 723 2019-10-28  Nick Clifton  <nickc@redhat.com>
 724
 725         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 726         operand.
 727
 728 2019-10-25  Nick Clifton  <nickc@redhat.com>
 729
 730         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 731         access to opcodes.op array element.
 732
 733 2019-10-23  Nick Clifton  <nickc@redhat.com>
 734
 735         * rx-dis.c (get_register_name): Fix spelling typo in error
 736         message.
 737         (get_condition_name, get_flag_name, get_double_register_name)
 738         (get_double_register_high_name, get_double_register_low_name)
 739         (get_double_control_register_name, get_double_condition_name)
 740         (get_opsize_name, get_size_name): Likewise.
 741
 742 2019-10-22  Nick Clifton  <nickc@redhat.com>
 743
 744         * rx-dis.c (get_size_name): New function.  Provides safe
 745         access to name array.
 746         (get_opsize_name): Likewise.
 747         (print_insn_rx): Use the accessor functions.
 748
 749 2019-10-16  Nick Clifton  <nickc@redhat.com>
 750
 751         * rx-dis.c (get_register_name): New function.  Provides safe
 752         access to name array.
 753         (get_condition_name, get_flag_name, get_double_register_name)
 754         (get_double_register_high_name, get_double_register_low_name)
 755         (get_double_control_register_name, get_double_condition_name):
 756         Likewise.
 757         (print_insn_rx): Use the accessor functions.
 758
 759 2019-10-09  Nick Clifton  <nickc@redhat.com>
 760
 761         PR 25041
 762         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 763         instructions.
 764
 765 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 766
 767         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 768         (cmpsd): Likewise. Move EsSeg to other operand.
 769         * opcodes/i386-tbl.h: Re-generate.
 770
 771 2019-09-23  Alan Modra  <amodra@gmail.com>
 772
 773         * m68k-dis.c: Include cpu-m68k.h
 774
 775 2019-09-23  Alan Modra  <amodra@gmail.com>
 776
 777         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 778         "elf/mips.h" earlier.
 779
 780 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 781
 782         PR gas/25012
 783         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 784         with SReg operand.
 785         * i386-tbl.h: Re-generate.
 786
 787 2019-09-18  Alan Modra  <amodra@gmail.com>
 788
 789         * arc-ext.c: Update throughout for bfd section macro changes.
 790
 791 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 792
 793         * Makefile.in: Re-generate.
 794         * configure: Re-generate.
 795
 796 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 797
 798         * riscv-opc.c (riscv_opcodes): Change subset field
 799         to insn_class field for all instructions.
 800         (riscv_insn_types): Likewise.
 801
 802 2019-09-16  Phil Blundell  <pb@pbcl.net>
 803
 804         * configure: Regenerated.
 805
 806 2019-09-10  Miod Vallat  <miod@online.fr>
 807
 808         PR 24982
 809         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 810
 811 2019-09-09  Phil Blundell  <pb@pbcl.net>
 812
 813         binutils 2.33 branch created.
 814
 815 2019-09-03  Nick Clifton  <nickc@redhat.com>
 816
 817         PR 24961
 818         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 819         greater than zero before indexing via (bufcnt -1).
 820
 821 2019-09-03  Nick Clifton  <nickc@redhat.com>
 822
 823         PR 24958
 824         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 825         (MAX_SPEC_REG_NAME_LEN): Define.
 826         (struct mmix_dis_info): Use defined constants for array lengths.
 827         (get_reg_name): New function.
 828         (get_sprec_reg_name): New function.
 829         (print_insn_mmix): Use new functions.
 830
 831 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 832
 833         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 834         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 835         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 836
 837 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 838
 839         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 840         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 841         (aarch64_sys_reg_supported_p): Update checks for the above.
 842
 843 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 844
 845         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 846         cases MVE_SQRSHRL and MVE_UQRSHLL.
 847         (print_insn_mve): Add case for specifier 'k' to check
 848         specific bit of the instruction.
 849
 850 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 851
 852         PR 24854
 853         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 854         encountering an unknown machine type.
 855         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 856         cases return -1 rather than calling abort.
 857
 858 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 859
 860         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 861         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 862         IgnoreSize.
 863         * i386-tbl.h: Re-generate.
 864
 865 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 866
 867         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 868         instructions.
 869
 870 2019-07-30  Mel Chen <mel.chen@sifive.com>
 871
 872         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 873         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 874
 875         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 876         fscsr.
 877
 878 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 879
 880         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 881         and MPY class instructions.
 882         (parse_option): Add nps400 option.
 883         (print_arc_disassembler_options): Add nps400 info.
 884
 885 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 886
 887         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 888         (bspop): Likewise.
 889         (modapp): Likewise.
 890         * arc-opc.c (RAD_CHK): Add.
 891         * arc-tbl.h: Regenerate.
 892
 893 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 894
 895         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 896         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 897
 898 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 899
 900         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 901         instructions as UNPREDICTABLE.
 902
 903 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 904
 905         * bpf-desc.c: Regenerated.
 906
 907 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 908
 909         * i386-gen.c (static_assert): Define.
 910         (main): Use it.
 911         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 912         (Opcode_Modifier_Num): ... this.
 913         (Mem): Delete.
 914
 915 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 916
 917         * i386-gen.c (operand_types): Move RegMem ...
 918         (opcode_modifiers): ... here.
 919         * i386-opc.h (RegMem): Move to opcode modifer enum.
 920         (union i386_operand_type): Move regmem field ...
 921         (struct i386_opcode_modifier): ... here.
 922         * i386-opc.tbl (RegMem): Define.
 923         (mov, movq): Move RegMem on segment, control, debug, and test
 924         register flavors.
 925         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 926         to non-SSE2AVX flavor.
 927         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 928         Move RegMem on register only flavors. Drop IgnoreSize from
 929         legacy encoding flavors.
 930         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 931         flavors.
 932         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 933         register only flavors.
 934         (vmovd): Move RegMem and drop IgnoreSize on register only
 935         flavor. Change opcode and operand order to store form.
 936         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 937
 938 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 939
 940         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 941         entries.
 942         * i386-opc.h (SReg2, SReg3): Replace by ...
 943         (SReg): ... this.
 944         (union i386_operand_type): Replace sreg fields.
 945         * i386-opc.tbl (mov, ): Use SReg.
 946         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 947         register flavors.
 948         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 949         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 950
 951 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 952
 953         * bpf-desc.c: Regenerate.
 954         * bpf-opc.c: Likewise.
 955         * bpf-opc.h: Likewise.
 956
 957 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 958
 959         * bpf-desc.c: Regenerate.
 960         * bpf-opc.c: Likewise.
 961
 962 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 963
 964         * arm-dis.c (print_insn_coprocessor): Rename index to
 965         index_operand.
 966
 967 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 968
 969         * riscv-opc.c (riscv_insn_types): Add r4 type.
 970
 971         * riscv-opc.c (riscv_insn_types): Add b and j type.
 972
 973         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 974         format for sb type and correct s type.
 975
 976 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 977
 978         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 979         SVE FMOV alias of FCPY.
 980
 981 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 982
 983         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 984         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 985
 986 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 987
 988         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 989         registers in an instruction prefixed by MOVPRFX.
 990
 991 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 992
 993         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 994         sve_size_13 icode to account for variant behaviour of
 995         pmull{t,b}.
 996         * aarch64-dis-2.c: Regenerate.
 997         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 998         sve_size_13 icode to account for variant behaviour of
 999         pmull{t,b}.
1000         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1001         (OP_SVE_VVV_Q_D): Add new qualifier.
1002         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1003         (struct aarch64_opcode): Split pmull{t,b} into those requiring
1004         AES and those not.
1005
1006 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1007
1008         * opcodes/i386-gen.c (operand_type_init): Remove
1009         OPERAND_TYPE_VEC_IMM4 entry.
1010         (operand_types): Remove Vec_Imm4.
1011         * opcodes/i386-opc.h (Vec_Imm4): Delete.
1012         (union i386_operand_type): Remove vec_imm4.
1013         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1014         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1015
1016 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1017
1018         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1019         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1020         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1021         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1022         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1023         monitorx, mwaitx): Drop ImmExt from operand-less forms.
1024         * i386-tbl.h: Re-generate.
1025
1026 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1027
1028         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1029         register operands.
1030         * i386-tbl.h: Re-generate.
1031
1032 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1033
1034         * i386-opc.tbl (C): New.
1035         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1036         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1037         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1038         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1039         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1040         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1041         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1042         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1043         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1044         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1045         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1046         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1047         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1048         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1049         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1050         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1051         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1052         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1053         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1054         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1055         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1056         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1057         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1058         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1059         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1060         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1061         flavors.
1062         * i386-tbl.h: Re-generate.
1063
1064 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1065
1066         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1067         register operands.
1068         * i386-tbl.h: Re-generate.
1069
1070 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1071
1072         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1073         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1074         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1075         * i386-tbl.h: Re-generate.
1076
1077 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1078
1079         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1080         Disp8MemShift from register only templates.
1081         * i386-tbl.h: Re-generate.
1082
1083 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1084
1085         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1086         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1087         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1088         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1089         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1090         EVEX_W_0F11_P_3_M_1): Delete.
1091         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1092         EVEX_W_0F11_P_3): New.
1093         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1094         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1095         MOD_EVEX_0F11_PREFIX_3 table entries.
1096         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1097         PREFIX_EVEX_0F11 table entries.
1098         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1099         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1100         EVEX_W_0F11_P_3_M_{0,1} table entries.
1101
1102 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1103
1104         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1105         Delete.
1106
1107 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1108
1109         PR binutils/24719
1110         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1111         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1112         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1113         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1114         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1115         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1116         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1117         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1118         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1119         PREFIX_EVEX_0F38C6_REG_6 entries.
1120         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1121         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1122         EVEX_W_0F38C7_R_6_P_2 entries.
1123         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1124         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1125         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1126         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1127         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1128         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1129         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1130
1131 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1132
1133         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1134         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1135         VEX_LEN_0F2D_P_3): Delete.
1136         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1137         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1138         (prefix_table): ... here.
1139
1140 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1141
1142         * i386-dis.c (Iq): Delete.
1143         (Id): New.
1144         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1145         TBM insns.
1146         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1147         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1148         (OP_E_memory): Also honor needindex when deciding whether an
1149         address size prefix needs printing.
1150         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1151
1152 2019-06-26  Jim Wilson  <jimw@sifive.com>
1153
1154         PR binutils/24739
1155         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1156         Set info->display_endian to info->endian_code.
1157
1158 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1159
1160         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1161         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1162         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1163         OPERAND_TYPE_ACC64 entries.
1164         * i386-init.h: Re-generate.
1165
1166 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1167
1168         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1169         Delete.
1170         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1171         of dqa_mode.
1172         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1173         entries here.
1174         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1175         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1176
1177 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1178
1179         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1180         variables.
1181
1182 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1183
1184         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1185         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1186         movnti.
1187         * i386-opc.tbl (movnti): Add IgnoreSize.
1188         * i386-tbl.h: Re-generate.
1189
1190 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1191
1192         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1193         * i386-tbl.h: Re-generate.
1194
1195 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1196
1197         * i386-dis-evex.h: Break into ...
1198         * i386-dis-evex-len.h: New file.
1199         * i386-dis-evex-mod.h: Likewise.
1200         * i386-dis-evex-prefix.h: Likewise.
1201         * i386-dis-evex-reg.h: Likewise.
1202         * i386-dis-evex-w.h: Likewise.
1203         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1204         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1205         i386-dis-evex-mod.h.
1206
1207 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1208
1209         PR binutils/24700
1210         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1211         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1212         EVEX_W_0F385B_P_2.
1213         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1214         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1215         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1216         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1217         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1218         EVEX_LEN_0F385B_P_2_W_1.
1219         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1220         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1221         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1222         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1223         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1224         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1225         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1226         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1227         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1228         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1229
1230 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1231
1232         PR binutils/24691
1233         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1234         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1235         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1236         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1237         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1238         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1239         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1240         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1241         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1242         EVEX_LEN_0F3A43_P_2_W_1.
1243         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1244         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1245         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1246         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1247         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1248         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1249         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1250         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1251         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1252         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1253         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1254         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1255
1256 2019-06-14  Nick Clifton  <nickc@redhat.com>
1257
1258         * po/fr.po; Updated French translation.
1259
1260 2019-06-13  Stafford Horne  <shorne@gmail.com>
1261
1262         * or1k-asm.c: Regenerated.
1263         * or1k-desc.c: Regenerated.
1264         * or1k-desc.h: Regenerated.
1265         * or1k-dis.c: Regenerated.
1266         * or1k-ibld.c: Regenerated.
1267         * or1k-opc.c: Regenerated.
1268         * or1k-opc.h: Regenerated.
1269         * or1k-opinst.c: Regenerated.
1270
1271 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1272
1273         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1274
1275 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1276
1277         PR binutils/24633
1278         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1279         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1280         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1281         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1282         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1283         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1284         EVEX_LEN_0F3A1B_P_2_W_1.
1285         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1286         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1287         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1288         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1289         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1290         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1291         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1292         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1293
1294 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1295
1296         PR binutils/24626
1297         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1298         EVEX.vvvv when disassembling VEX and EVEX instructions.
1299         (OP_VEX): Set vex.register_specifier to 0 after readding
1300         vex.register_specifier.
1301         (OP_Vex_2src_1): Likewise.
1302         (OP_Vex_2src_2): Likewise.
1303         (OP_LWP_E): Likewise.
1304         (OP_EX_Vex): Don't check vex.register_specifier.
1305         (OP_XMM_Vex): Likewise.
1306
1307 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1308             Lili Cui  <lili.cui@intel.com>
1309
1310         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1311         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1312         instructions.
1313         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1314         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1315         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1316         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1317         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1318         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1319         * i386-init.h: Regenerated.
1320         * i386-tbl.h: Likewise.
1321
1322 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1323             Lili Cui  <lili.cui@intel.com>
1324
1325         * doc/c-i386.texi: Document enqcmd.
1326         * testsuite/gas/i386/enqcmd-intel.d: New file.
1327         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1328         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1329         * testsuite/gas/i386/enqcmd.d: Likewise.
1330         * testsuite/gas/i386/enqcmd.s: Likewise.
1331         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1332         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1333         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1334         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1335         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1336         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1337         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1338         and x86-64-enqcmd.
1339
1340 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1341
1342         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1343
1344 2019-06-03  Alan Modra  <amodra@gmail.com>
1345
1346         * ppc-dis.c (prefix_opcd_indices): Correct size.
1347
1348 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1349
1350         PR gas/24625
1351         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1352         Disp8ShiftVL.
1353         * i386-tbl.h: Regenerated.
1354
1355 2019-05-24  Alan Modra  <amodra@gmail.com>
1356
1357         * po/POTFILES.in: Regenerate.
1358
1359 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1360             Alan Modra  <amodra@gmail.com>
1361
1362         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1363         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1364         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1365         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1366         XTOP>): Define and add entries.
1367         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1368         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1369         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1370         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1371
1372 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1373             Alan Modra  <amodra@gmail.com>
1374
1375         * ppc-dis.c (ppc_opts): Add "future" entry.
1376         (PREFIX_OPCD_SEGS): Define.
1377         (prefix_opcd_indices): New array.
1378         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1379         (lookup_prefix): New function.
1380         (print_insn_powerpc): Handle 64-bit prefix instructions.
1381         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1382         (PMRR, POWERXX): Define.
1383         (prefix_opcodes): New instruction table.
1384         (prefix_num_opcodes): New constant.
1385
1386 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1387
1388         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1389         * configure: Regenerated.
1390         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1391         and cpu/bpf.opc.
1392         (HFILES): Add bpf-desc.h and bpf-opc.h.
1393         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1394         bpf-ibld.c and bpf-opc.c.
1395         (BPF_DEPS): Define.
1396         * Makefile.in: Regenerated.
1397         * disassemble.c (ARCH_bpf): Define.
1398         (disassembler): Add case for bfd_arch_bpf.
1399         (disassemble_init_for_target): Likewise.
1400         (enum epbf_isa_attr): Define.
1401         * disassemble.h: extern print_insn_bpf.
1402         * bpf-asm.c: Generated.
1403         * bpf-opc.h: Likewise.
1404         * bpf-opc.c: Likewise.
1405         * bpf-ibld.c: Likewise.
1406         * bpf-dis.c: Likewise.
1407         * bpf-desc.h: Likewise.
1408         * bpf-desc.c: Likewise.
1409
1410 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1411
1412         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1413         and VMSR with the new operands.
1414
1415 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1416
1417         * arm-dis.c (enum mve_instructions): New enum
1418         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1419         and cneg.
1420         (mve_opcodes): New instructions as above.
1421         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1422         csneg and csel.
1423         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1424
1425 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1426
1427         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1428         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1429         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1430         uqshl, urshrl and urshr.
1431         (is_mve_okay_in_it): Add new instructions to TRUE list.
1432         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1433         (print_insn_mve): Updated to accept new %j,
1434         %<bitfield>m and %<bitfield>n patterns.
1435
1436 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1437
1438         * mips-opc.c (mips_builtin_opcodes): Change source register
1439         constraint for DAUI.
1440
1441 2019-05-20  Nick Clifton  <nickc@redhat.com>
1442
1443         * po/fr.po: Updated French translation.
1444
1445 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1446             Michael Collison <michael.collison@arm.com>
1447
1448         * arm-dis.c (thumb32_opcodes): Add new instructions.
1449         (enum mve_instructions): Likewise.
1450         (enum mve_undefined): Add new reasons.
1451         (is_mve_encoding_conflict): Handle new instructions.
1452         (is_mve_undefined): Likewise.
1453         (is_mve_unpredictable): Likewise.
1454         (print_mve_undefined): Likewise.
1455         (print_mve_size): Likewise.
1456
1457 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1458             Michael Collison <michael.collison@arm.com>
1459
1460         * arm-dis.c (thumb32_opcodes): Add new instructions.
1461         (enum mve_instructions): Likewise.
1462         (is_mve_encoding_conflict): Handle new instructions.
1463         (is_mve_undefined): Likewise.
1464         (is_mve_unpredictable): Likewise.
1465         (print_mve_size): Likewise.
1466
1467 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1468             Michael Collison <michael.collison@arm.com>
1469
1470         * arm-dis.c (thumb32_opcodes): Add new instructions.
1471         (enum mve_instructions): Likewise.
1472         (is_mve_encoding_conflict): Likewise.
1473         (is_mve_unpredictable): Likewise.
1474         (print_mve_size): Likewise.
1475
1476 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1477             Michael Collison <michael.collison@arm.com>
1478
1479         * arm-dis.c (thumb32_opcodes): Add new instructions.
1480         (enum mve_instructions): Likewise.
1481         (is_mve_encoding_conflict): Handle new instructions.
1482         (is_mve_undefined): Likewise.
1483         (is_mve_unpredictable): Likewise.
1484         (print_mve_size): Likewise.
1485
1486 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1487             Michael Collison <michael.collison@arm.com>
1488
1489         * arm-dis.c (thumb32_opcodes): Add new instructions.
1490         (enum mve_instructions): Likewise.
1491         (is_mve_encoding_conflict): Handle new instructions.
1492         (is_mve_undefined): Likewise.
1493         (is_mve_unpredictable): Likewise.
1494         (print_mve_size): Likewise.
1495         (print_insn_mve): Likewise.
1496
1497 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1498             Michael Collison <michael.collison@arm.com>
1499
1500         * arm-dis.c (thumb32_opcodes): Add new instructions.
1501         (print_insn_thumb32): Handle new instructions.
1502
1503 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1504             Michael Collison <michael.collison@arm.com>
1505
1506         * arm-dis.c (enum mve_instructions): Add new instructions.
1507         (enum mve_undefined): Add new reasons.
1508         (is_mve_encoding_conflict): Handle new instructions.
1509         (is_mve_undefined): Likewise.
1510         (is_mve_unpredictable): Likewise.
1511         (print_mve_undefined): Likewise.
1512         (print_mve_size): Likewise.
1513         (print_mve_shift_n): Likewise.
1514         (print_insn_mve): Likewise.
1515
1516 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1517             Michael Collison <michael.collison@arm.com>
1518
1519         * arm-dis.c (enum mve_instructions): Add new instructions.
1520         (is_mve_encoding_conflict): Handle new instructions.
1521         (is_mve_unpredictable): Likewise.
1522         (print_mve_rotate): Likewise.
1523         (print_mve_size): Likewise.
1524         (print_insn_mve): Likewise.
1525
1526 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1527             Michael Collison <michael.collison@arm.com>
1528
1529         * arm-dis.c (enum mve_instructions): Add new instructions.
1530         (is_mve_encoding_conflict): Handle new instructions.
1531         (is_mve_unpredictable): Likewise.
1532         (print_mve_size): Likewise.
1533         (print_insn_mve): Likewise.
1534
1535 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1536             Michael Collison <michael.collison@arm.com>
1537
1538         * arm-dis.c (enum mve_instructions): Add new instructions.
1539         (enum mve_undefined): Add new reasons.
1540         (is_mve_encoding_conflict): Handle new instructions.
1541         (is_mve_undefined): Likewise.
1542         (is_mve_unpredictable): Likewise.
1543         (print_mve_undefined): Likewise.
1544         (print_mve_size): Likewise.
1545         (print_insn_mve): Likewise.
1546
1547 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1548             Michael Collison <michael.collison@arm.com>
1549
1550         * arm-dis.c (enum mve_instructions): Add new instructions.
1551         (is_mve_encoding_conflict): Handle new instructions.
1552         (is_mve_undefined): Likewise.
1553         (is_mve_unpredictable): Likewise.
1554         (print_mve_size): Likewise.
1555         (print_insn_mve): Likewise.
1556
1557 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1558             Michael Collison <michael.collison@arm.com>
1559
1560         * arm-dis.c (enum mve_instructions): Add new instructions.
1561         (enum mve_unpredictable): Add new reasons.
1562         (enum mve_undefined): Likewise.
1563         (is_mve_okay_in_it): Handle new isntructions.
1564         (is_mve_encoding_conflict): Likewise.
1565         (is_mve_undefined): Likewise.
1566         (is_mve_unpredictable): Likewise.
1567         (print_mve_vmov_index): Likewise.
1568         (print_simd_imm8): Likewise.
1569         (print_mve_undefined): Likewise.
1570         (print_mve_unpredictable): Likewise.
1571         (print_mve_size): Likewise.
1572         (print_insn_mve): Likewise.
1573
1574 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1575             Michael Collison <michael.collison@arm.com>
1576
1577         * arm-dis.c (enum mve_instructions): Add new instructions.
1578         (enum mve_unpredictable): Add new reasons.
1579         (enum mve_undefined): Likewise.
1580         (is_mve_encoding_conflict): Handle new instructions.
1581         (is_mve_undefined): Likewise.
1582         (is_mve_unpredictable): Likewise.
1583         (print_mve_undefined): Likewise.
1584         (print_mve_unpredictable): Likewise.
1585         (print_mve_rounding_mode): Likewise.
1586         (print_mve_vcvt_size): Likewise.
1587         (print_mve_size): Likewise.
1588         (print_insn_mve): Likewise.
1589
1590 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1591             Michael Collison <michael.collison@arm.com>
1592
1593         * arm-dis.c (enum mve_instructions): Add new instructions.
1594         (enum mve_unpredictable): Add new reasons.
1595         (enum mve_undefined): Likewise.
1596         (is_mve_undefined): Handle new instructions.
1597         (is_mve_unpredictable): Likewise.
1598         (print_mve_undefined): Likewise.
1599         (print_mve_unpredictable): Likewise.
1600         (print_mve_size): Likewise.
1601         (print_insn_mve): Likewise.
1602
1603 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1604             Michael Collison <michael.collison@arm.com>
1605
1606         * arm-dis.c (enum mve_instructions): Add new instructions.
1607         (enum mve_undefined): Add new reasons.
1608         (insns): Add new instructions.
1609         (is_mve_encoding_conflict):
1610         (print_mve_vld_str_addr): New print function.
1611         (is_mve_undefined): Handle new instructions.
1612         (is_mve_unpredictable): Likewise.
1613         (print_mve_undefined): Likewise.
1614         (print_mve_size): Likewise.
1615         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1616         (print_insn_mve):  Handle new operands.
1617
1618 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1619             Michael Collison <michael.collison@arm.com>
1620
1621         * arm-dis.c (enum mve_instructions): Add new instructions.
1622         (enum mve_unpredictable): Add new reasons.
1623         (is_mve_encoding_conflict): Handle new instructions.
1624         (is_mve_unpredictable): Likewise.
1625         (mve_opcodes): Add new instructions.
1626         (print_mve_unpredictable): Handle new reasons.
1627         (print_mve_register_blocks): New print function.
1628         (print_mve_size): Handle new instructions.
1629         (print_insn_mve): Likewise.
1630
1631 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1632             Michael Collison <michael.collison@arm.com>
1633
1634         * arm-dis.c (enum mve_instructions): Add new instructions.
1635         (enum mve_unpredictable): Add new reasons.
1636         (enum mve_undefined): Likewise.
1637         (is_mve_encoding_conflict): Handle new instructions.
1638         (is_mve_undefined): Likewise.
1639         (is_mve_unpredictable): Likewise.
1640         (coprocessor_opcodes): Move NEON VDUP from here...
1641         (neon_opcodes): ... to here.
1642         (mve_opcodes): Add new instructions.
1643         (print_mve_undefined):  Handle new reasons.
1644         (print_mve_unpredictable): Likewise.
1645         (print_mve_size): Handle new instructions.
1646         (print_insn_neon): Handle vdup.
1647         (print_insn_mve): Handle new operands.
1648
1649 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1650             Michael Collison <michael.collison@arm.com>
1651
1652         * arm-dis.c (enum mve_instructions): Add new instructions.
1653         (enum mve_unpredictable): Add new values.
1654         (mve_opcodes): Add new instructions.
1655         (vec_condnames): New array with vector conditions.
1656         (mve_predicatenames): New array with predicate suffixes.
1657         (mve_vec_sizename): New array with vector sizes.
1658         (enum vpt_pred_state): New enum with vector predication states.
1659         (struct vpt_block): New struct type for vpt blocks.
1660         (vpt_block_state): Global struct to keep track of state.
1661         (mve_extract_pred_mask): New helper function.
1662         (num_instructions_vpt_block): Likewise.
1663         (mark_outside_vpt_block): Likewise.
1664         (mark_inside_vpt_block): Likewise.
1665         (invert_next_predicate_state): Likewise.
1666         (update_next_predicate_state): Likewise.
1667         (update_vpt_block_state): Likewise.
1668         (is_vpt_instruction): Likewise.
1669         (is_mve_encoding_conflict): Add entries for new instructions.
1670         (is_mve_unpredictable): Likewise.
1671         (print_mve_unpredictable): Handle new cases.
1672         (print_instruction_predicate): Likewise.
1673         (print_mve_size): New function.
1674         (print_vec_condition): New function.
1675         (print_insn_mve): Handle vpt blocks and new print operands.
1676
1677 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1678
1679         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1680         8, 14 and 15 for Armv8.1-M Mainline.
1681
1682 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1683             Michael Collison <michael.collison@arm.com>
1684
1685         * arm-dis.c (enum mve_instructions): New enum.
1686         (enum mve_unpredictable): Likewise.
1687         (enum mve_undefined): Likewise.
1688         (struct mopcode32): New struct.
1689         (is_mve_okay_in_it): New function.
1690         (is_mve_architecture): Likewise.
1691         (arm_decode_field): Likewise.
1692         (arm_decode_field_multiple): Likewise.
1693         (is_mve_encoding_conflict): Likewise.
1694         (is_mve_undefined): Likewise.
1695         (is_mve_unpredictable): Likewise.
1696         (print_mve_undefined): Likewise.
1697         (print_mve_unpredictable): Likewise.
1698         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1699         (print_insn_mve): New function.
1700         (print_insn_thumb32): Handle MVE architecture.
1701         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1702
1703 2019-05-10  Nick Clifton  <nickc@redhat.com>
1704
1705         PR 24538
1706         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1707         end of the table prematurely.
1708
1709 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1710
1711         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1712         macros for R6.
1713
1714 2019-05-11  Alan Modra  <amodra@gmail.com>
1715
1716         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1717         when -Mraw is in effect.
1718
1719 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1720
1721         * aarch64-dis-2.c: Regenerate.
1722         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1723         (OP_SVE_BBB): New variant set.
1724         (OP_SVE_DDDD): New variant set.
1725         (OP_SVE_HHH): New variant set.
1726         (OP_SVE_HHHU): New variant set.
1727         (OP_SVE_SSS): New variant set.
1728         (OP_SVE_SSSU): New variant set.
1729         (OP_SVE_SHH): New variant set.
1730         (OP_SVE_SBBU): New variant set.
1731         (OP_SVE_DSS): New variant set.
1732         (OP_SVE_DHHU): New variant set.
1733         (OP_SVE_VMV_HSD_BHS): New variant set.
1734         (OP_SVE_VVU_HSD_BHS): New variant set.
1735         (OP_SVE_VVVU_SD_BH): New variant set.
1736         (OP_SVE_VVVU_BHSD): New variant set.
1737         (OP_SVE_VVV_QHD_DBS): New variant set.
1738         (OP_SVE_VVV_HSD_BHS): New variant set.
1739         (OP_SVE_VVV_HSD_BHS2): New variant set.
1740         (OP_SVE_VVV_BHS_HSD): New variant set.
1741         (OP_SVE_VV_BHS_HSD): New variant set.
1742         (OP_SVE_VVV_SD): New variant set.
1743         (OP_SVE_VVU_BHS_HSD): New variant set.
1744         (OP_SVE_VZVV_SD): New variant set.
1745         (OP_SVE_VZVV_BH): New variant set.
1746         (OP_SVE_VZV_SD): New variant set.
1747         (aarch64_opcode_table): Add sve2 instructions.
1748
1749 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1750
1751         * aarch64-asm-2.c: Regenerated.
1752         * aarch64-dis-2.c: Regenerated.
1753         * aarch64-opc-2.c: Regenerated.
1754         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1755         for SVE_SHLIMM_UNPRED_22.
1756         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1757         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1758         operand.
1759
1760 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1761
1762         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1763         sve_size_tsz_bhs iclass encode.
1764         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1765         sve_size_tsz_bhs iclass decode.
1766
1767 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1768
1769         * aarch64-asm-2.c: Regenerated.
1770         * aarch64-dis-2.c: Regenerated.
1771         * aarch64-opc-2.c: Regenerated.
1772         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1773         for SVE_Zm4_11_INDEX.
1774         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1775         (fields): Handle SVE_i2h field.
1776         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1777         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1778
1779 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1780
1781         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1782         sve_shift_tsz_bhsd iclass encode.
1783         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1784         sve_shift_tsz_bhsd iclass decode.
1785
1786 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1787
1788         * aarch64-asm-2.c: Regenerated.
1789         * aarch64-dis-2.c: Regenerated.
1790         * aarch64-opc-2.c: Regenerated.
1791         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1792         (aarch64_encode_variant_using_iclass): Handle
1793         sve_shift_tsz_hsd iclass encode.
1794         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1795         sve_shift_tsz_hsd iclass decode.
1796         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1797         for SVE_SHRIMM_UNPRED_22.
1798         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1799         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1800         operand.
1801
1802 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1803
1804         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1805         sve_size_013 iclass encode.
1806         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1807         sve_size_013 iclass decode.
1808
1809 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1810
1811         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1812         sve_size_bh iclass encode.
1813         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1814         sve_size_bh iclass decode.
1815
1816 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1817
1818         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1819         sve_size_sd2 iclass encode.
1820         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1821         sve_size_sd2 iclass decode.
1822         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1823         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1824
1825 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1826
1827         * aarch64-asm-2.c: Regenerated.
1828         * aarch64-dis-2.c: Regenerated.
1829         * aarch64-opc-2.c: Regenerated.
1830         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1831         for SVE_ADDR_ZX.
1832         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1833         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1834
1835 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1836
1837         * aarch64-asm-2.c: Regenerated.
1838         * aarch64-dis-2.c: Regenerated.
1839         * aarch64-opc-2.c: Regenerated.
1840         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1841         for SVE_Zm3_11_INDEX.
1842         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1843         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1844         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1845         fields.
1846         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1847
1848 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1849
1850         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1851         sve_size_hsd2 iclass encode.
1852         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1853         sve_size_hsd2 iclass decode.
1854         * aarch64-opc.c (fields): Handle SVE_size field.
1855         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1856
1857 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1858
1859         * aarch64-asm-2.c: Regenerated.
1860         * aarch64-dis-2.c: Regenerated.
1861         * aarch64-opc-2.c: Regenerated.
1862         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1863         for SVE_IMM_ROT3.
1864         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1865         (fields): Handle SVE_rot3 field.
1866         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1867         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1868
1869 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1870
1871         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1872         instructions.
1873
1874 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1875
1876         * aarch64-tbl.h
1877         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1878         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1879         aarch64_feature_sve2bitperm): New feature sets.
1880         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1881         for feature set addresses.
1882         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1883         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1884
1885 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1886             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1887
1888         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1889         argument and set ASE_EVA_R6 appropriately.
1890         (set_default_mips_dis_options): Pass ISA to above.
1891         (parse_mips_dis_option): Likewise.
1892         * mips-opc.c (EVAR6): New macro.
1893         (mips_builtin_opcodes): Add llwpe, scwpe.
1894
1895 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1896
1897         * aarch64-asm-2.c: Regenerated.
1898         * aarch64-dis-2.c: Regenerated.
1899         * aarch64-opc-2.c: Regenerated.
1900         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1901         AARCH64_OPND_TME_UIMM16.
1902         (aarch64_print_operand): Likewise.
1903         * aarch64-tbl.h (QL_IMM_NIL): New.
1904         (TME): New.
1905         (_TME_INSN): New.
1906         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1907
1908 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1909
1910         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1911
1912 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1913             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1914
1915         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1916
1917 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1918
1919         * s12z-opc.h: Add extern "C" bracketing to help
1920         users who wish to use this interface in c++ code.
1921
1922 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1923
1924         * s12z-opc.c (bm_decode): Handle bit map operations with the
1925         "reserved0" mode.
1926
1927 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1928
1929         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1930         specifier.  Add entries for VLDR and VSTR of system registers.
1931         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1932         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1933         of %J and %K format specifier.
1934
1935 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1936
1937         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1938         Add new entries for VSCCLRM instruction.
1939         (print_insn_coprocessor): Handle new %C format control code.
1940
1941 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1942
1943         * arm-dis.c (enum isa): New enum.
1944         (struct sopcode32): New structure.
1945         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1946         set isa field of all current entries to ANY.
1947         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1948         Only match an entry if its isa field allows the current mode.
1949
1950 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1951
1952         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1953         CLRM.
1954         (print_insn_thumb32): Add logic to print %n CLRM register list.
1955
1956 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1957
1958         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1959         and %Q patterns.
1960
1961 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1962
1963         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1964         (print_insn_thumb32): Edit the switch case for %Z.
1965
1966 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1967
1968         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1969
1970 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1971
1972         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1973
1974 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1975
1976         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1977
1978 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1979
1980         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1981         Arm register with r13 and r15 unpredictable.
1982         (thumb32_opcodes): New instructions for bfx and bflx.
1983
1984 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1985
1986         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1987
1988 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1989
1990         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1991
1992 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1993
1994         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1995
1996 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1997
1998         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1999
2000 2019-04-12  John Darrington <john@darrington.wattle.id.au>
2001
2002         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2003         "optr". ("operator" is a reserved word in c++).
2004
2005 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2006
2007         * aarch64-opc.c (aarch64_print_operand): Add case for
2008         AARCH64_OPND_Rt_SP.
2009         (verify_constraints): Likewise.
2010         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2011         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2012         to accept Rt|SP as first operand.
2013         (AARCH64_OPERANDS): Add new Rt_SP.
2014         * aarch64-asm-2.c: Regenerated.
2015         * aarch64-dis-2.c: Regenerated.
2016         * aarch64-opc-2.c: Regenerated.
2017
2018 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2019
2020         * aarch64-asm-2.c: Regenerated.
2021         * aarch64-dis-2.c: Likewise.
2022         * aarch64-opc-2.c: Likewise.
2023         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2024
2025 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
2026
2027         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2028
2029 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
2030
2031         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2032         * i386-init.h: Regenerated.
2033
2034 2019-04-07  Alan Modra  <amodra@gmail.com>
2035
2036         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2037         op_separator to control printing of spaces, comma and parens
2038         rather than need_comma, need_paren and spaces vars.
2039
2040 2019-04-07  Alan Modra  <amodra@gmail.com>
2041
2042         PR 24421
2043         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2044         (print_insn_neon, print_insn_arm): Likewise.
2045
2046 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
2047
2048         * i386-dis-evex.h (evex_table): Updated to support BF16
2049         instructions.
2050         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2051         and EVEX_W_0F3872_P_3.
2052         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2053         (cpu_flags): Add bitfield for CpuAVX512_BF16.
2054         * i386-opc.h (enum): Add CpuAVX512_BF16.
2055         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2056         * i386-opc.tbl: Add AVX512 BF16 instructions.
2057         * i386-init.h: Regenerated.
2058         * i386-tbl.h: Likewise.
2059
2060 2019-04-05  Alan Modra  <amodra@gmail.com>
2061
2062         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2063         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2064         to favour printing of "-" branch hint when using the "y" bit.
2065         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2066
2067 2019-04-05  Alan Modra  <amodra@gmail.com>
2068
2069         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2070         opcode until first operand is output.
2071
2072 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2073
2074         PR gas/24349
2075         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2076         (valid_bo_post_v2): Add support for 'at' branch hints.
2077         (insert_bo): Only error on branch on ctr.
2078         (get_bo_hint_mask): New function.
2079         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2080         for inserting 'at' branch hints.
2081         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2082         for extracting 'at' branch hints.
2083         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2084         (BOE): Delete operand.
2085         (BOM, BOP): New operands.
2086         (RM): Update value.
2087         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2088         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2089         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2090         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2091         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2092         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2093         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2094         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2095         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2096         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2097         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2098         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2099         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2100         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2101         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2102         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2103         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2104         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2105         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2106         bttarl+>: New extended mnemonics.
2107
2108 2019-03-28  Alan Modra  <amodra@gmail.com>
2109
2110         PR 24390
2111         * ppc-opc.c (BTF): Define.
2112         (powerpc_opcodes): Use for mtfsb*.
2113         * ppc-dis.c (print_insn_powerpc): Print fields with both
2114         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2115
2116 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2117
2118         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2119         (mapping_symbol_for_insn): Implement new algorithm.
2120         (print_insn): Remove duplicate code.
2121
2122 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2123
2124         * aarch64-dis.c (print_insn_aarch64):
2125         Implement override.
2126
2127 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2128
2129         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2130         order.
2131
2132 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2133
2134         * aarch64-dis.c (last_stop_offset): New.
2135         (print_insn_aarch64): Use stop_offset.
2136
2137 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2138
2139         PR gas/24359
2140         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2141         CPU_ANY_AVX2_FLAGS.
2142         * i386-init.h: Regenerated.
2143
2144 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2145
2146         PR gas/24348
2147         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2148         vmovdqu16, vmovdqu32 and vmovdqu64.
2149         * i386-tbl.h: Regenerated.
2150
2151 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2152
2153         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2154         from vstrszb, vstrszh, and vstrszf.
2155
2156 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2157
2158         * s390-opc.txt: Add instruction descriptions.
2159
2160 2019-02-08  Jim Wilson  <jimw@sifive.com>
2161
2162         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2163         <bne>: Likewise.
2164
2165 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2166
2167         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2168
2169 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2170
2171         PR binutils/23212
2172         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2173         * aarch64-opc.c (verify_elem_sd): New.
2174         (fields): Add FLD_sz entr.
2175         * aarch64-tbl.h (_SIMD_INSN): New.
2176         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2177         fmulx scalar and vector by element isns.
2178
2179 2019-02-07  Nick Clifton  <nickc@redhat.com>
2180
2181         * po/sv.po: Updated Swedish translation.
2182
2183 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2184
2185         * s390-mkopc.c (main): Accept arch13 as cpu string.
2186         * s390-opc.c: Add new instruction formats and instruction opcode
2187         masks.
2188         * s390-opc.txt: Add new arch13 instructions.
2189
2190 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2191
2192         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2193         (aarch64_opcode): Change encoding for stg, stzg
2194         st2g and st2zg.
2195         * aarch64-asm-2.c: Regenerated.
2196         * aarch64-dis-2.c: Regenerated.
2197         * aarch64-opc-2.c: Regenerated.
2198
2199 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2200
2201         * aarch64-asm-2.c: Regenerated.
2202         * aarch64-dis-2.c: Likewise.
2203         * aarch64-opc-2.c: Likewise.
2204         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2205
2206 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2207             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2208
2209         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2210         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2211         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2212         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2213         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2214         case for ldstgv_indexed.
2215         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2216         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2217         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2218         * aarch64-asm-2.c: Regenerated.
2219         * aarch64-dis-2.c: Regenerated.
2220         * aarch64-opc-2.c: Regenerated.
2221
2222 2019-01-23  Nick Clifton  <nickc@redhat.com>
2223
2224         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2225
2226 2019-01-21  Nick Clifton  <nickc@redhat.com>
2227
2228         * po/de.po: Updated German translation.
2229         * po/uk.po: Updated Ukranian translation.
2230
2231 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2232         * mips-dis.c (mips_arch_choices): Fix typo in
2233         gs464, gs464e and gs264e descriptors.
2234
2235 2019-01-19  Nick Clifton  <nickc@redhat.com>
2236
2237         * configure: Regenerate.
2238         * po/opcodes.pot: Regenerate.
2239
2240 2018-06-24  Nick Clifton  <nickc@redhat.com>
2241
2242         2.32 branch created.
2243
2244 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2245
2246         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2247         if it is null.
2248         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2249         zero.
2250
2251 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2252
2253         * configure: Regenerate.
2254
2255 2019-01-07  Alan Modra  <amodra@gmail.com>
2256
2257         * configure: Regenerate.
2258         * po/POTFILES.in: Regenerate.
2259
2260 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2261
2262         * s12z-opc.c: New file.
2263         * s12z-opc.h: New file.
2264         * s12z-dis.c: Removed all code not directly related to display
2265         of instructions.  Used the interface provided by the new files
2266         instead.
2267         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2268         * Makefile.in: Regenerate.
2269         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2270         * configure: Regenerate.
2271
2272 2019-01-01  Alan Modra  <amodra@gmail.com>
2273
2274         Update year range in copyright notice of all files.
2275
2276 For older changes see ChangeLog-2018
2277 \f
2278 Copyright (C) 2019 Free Software Foundation, Inc.
2279
2280 Copying and distribution of this file, with or without modification,
2281 are permitted in any medium without royalty provided the copyright
2282 notice and this notice are preserved.
2283
2284 Local Variables:
2285 mode: change-log
2286 left-margin: 8
2287 fill-column: 74
2288 version-control: never
2289 End: