opcodes/ChangeLog

   1 2020-07-06  Nick Clifton  <nickc@redhat.com>
   2
   3         * po/pt_BR.po: Updated Brazilian Portugugese translation.
   4         * po/uk.po: Updated Ukranian translation.
   5
   6 2020-07-04  Nick Clifton  <nickc@redhat.com>
   7
   8         * configure: Regenerate.
   9         * po/opcodes.pot: Regenerate.
  10
  11 2020-07-04  Nick Clifton  <nickc@redhat.com>
  12
  13         Binutils 2.35 branch created.
  14
  15 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
  16
  17         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
  18         * i386-opc.h (VexSwapSources): New.
  19         (i386_opcode_modifier): Add vexswapsources.
  20         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
  21         with two source operands swapped.
  22         * i386-tbl.h: Regenerated.
  23
  24 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
  25
  26         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
  27         unprivileged CSR can also be initialized.
  28
  29 2020-06-29  Alan Modra  <amodra@gmail.com>
  30
  31         * arm-dis.c: Use C style comments.
  32         * cr16-opc.c: Likewise.
  33         * ft32-dis.c: Likewise.
  34         * moxie-opc.c: Likewise.
  35         * tic54x-dis.c: Likewise.
  36         * s12z-opc.c: Remove useless comment.
  37         * xgate-dis.c: Likewise.
  38
  39 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
  40
  41         * i386-opc.tbl: Add a blank line.
  42
  43 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
  44
  45         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
  46         (VecSIB128): Renamed to ...
  47         (VECSIB128): This.
  48         (VecSIB256): Renamed to ...
  49         (VECSIB256): This.
  50         (VecSIB512): Renamed to ...
  51         (VECSIB512): This.
  52         (VecSIB): Renamed to ...
  53         (SIB): This.
  54         (i386_opcode_modifier): Replace vecsib with sib.
  55         * i386-opc.tbl (VecSIB128): New.
  56         (VecSIB256): Likewise.
  57         (VecSIB512): Likewise.
  58         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
  59         and VecSIB512, respectively.
  60
  61 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  62
  63         * i386-dis.c: Adjust description of I macro.
  64         (x86_64_table): Drop use of I.
  65         (float_mem): Replace use of I.
  66         (putop): Remove handling of I. Adjust setting/clearing of "alt".
  67
  68 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  69
  70         * i386-dis.c: (print_insn): Avoid straight assignment to
  71         priv.orig_sizeflag when processing -M sub-options.
  72
  73 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  74
  75         * i386-dis.c: Adjust description of J macro.
  76         (dis386, x86_64_table, mod_table): Replace J.
  77         (putop): Remove handling of J.
  78
  79 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
  82
  83 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  84
  85         * i386-dis.c: Adjust description of "LQ" macro.
  86         (dis386_twobyte): Use LQ for sysret.
  87         (putop): Adjust handling of LQ.
  88
  89 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
  90
  91         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
  92         * riscv-dis.c: Include elfxx-riscv.h.
  93
  94 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
  95
  96         * i386-dis.c (prefix_table): Revert the last vmgexit change.
  97
  98 2020-06-17  Lili Cui  <lili.cui@intel.com>
  99
 100         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
 101
 102 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
 103
 104         PR gas/26115
 105         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
 106         * i386-opc.tbl: Likewise.
 107         * i386-tbl.h: Regenerated.
 108
 109 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
 110
 111         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
 112
 113 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
 114
 115         * aarch64-opc.c (SYSREG): New macro for describing system registers.
 116         (SR_CORE): Likewise.
 117         (SR_FEAT): Likewise.
 118         (SR_RNG): Likewise.
 119         (SR_V8_1): Likewise.
 120         (SR_V8_2): Likewise.
 121         (SR_V8_3): Likewise.
 122         (SR_V8_4): Likewise.
 123         (SR_PAN): Likewise.
 124         (SR_RAS): Likewise.
 125         (SR_SSBS): Likewise.
 126         (SR_SVE): Likewise.
 127         (SR_ID_PFR2): Likewise.
 128         (SR_PROFILE): Likewise.
 129         (SR_MEMTAG): Likewise.
 130         (SR_SCXTNUM): Likewise.
 131         (aarch64_sys_regs): Refactor to store feature information in the table.
 132         (aarch64_sys_reg_supported_p): Collapse logic for system registers
 133         that now describe their own features.
 134         (aarch64_pstatefield_supported_p): Likewise.
 135
 136 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 137
 138         * i386-dis.c (prefix_table): Fix a typo in comments.
 139
 140 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 141
 142         * i386-dis.c (rex_ignored): Delete.
 143         (ckprefix): Drop rex_ignored initialization.
 144         (get_valid_dis386): Drop setting of rex_ignored.
 145         (print_insn): Drop checking of rex_ignored. Don't record data
 146         size prefix as used with VEX-and-alike encodings.
 147
 148 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 149
 150         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 151         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 152         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 153         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 154         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 155         VEX_0F12, and VEX_0F16.
 156         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 157         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 158         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 159         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 160         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 161         MOD_VEX_0F16_PREFIX_2 entries.
 162
 163 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 164
 165         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 166         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 167         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 168         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 169         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 170         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 171         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 172         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 173         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 174         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 175         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 176         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 177         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 178         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 179         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 180         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 181         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 182         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 183         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 184         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 185         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 186         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 187         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 188         EVEX_W_0FC6_P_2): Delete.
 189         (print_insn): Add EVEX.W vs embedded prefix consistency check
 190         to prefix validation.
 191         * i386-dis-evex.h (evex_table): Don't further descend for
 192         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 193         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 194         and 0F2B.
 195         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 196         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 197         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 198         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 199         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 200         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 201         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 202         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 203         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 204         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 205         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 206         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 207         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 208         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 209         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 210         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 211         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 212         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 213         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 214         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 215         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 216         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 217         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 218         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 219         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 220         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 221         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 222
 223 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 224
 225         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 226         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 227         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 228         vmovmskpX.
 229         (print_insn): Drop pointless check against bad_opcode. Split
 230         prefix validation into legacy and VEX-and-alike parts.
 231         (putop): Re-work 'X' macro handling.
 232
 233 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 234
 235         * i386-dis.c (MOD_0F51): Rename to ...
 236         (MOD_0F50): ... this.
 237
 238 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 239
 240         * arm-dis.c (arm_opcodes): Add dfb.
 241         (thumb32_opcodes): Add dfb.
 242
 243 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 244
 245         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 246
 247 2020-06-06  Alan Modra  <amodra@gmail.com>
 248
 249         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 250
 251 2020-06-05  Alan Modra  <amodra@gmail.com>
 252
 253         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 254         size is large enough.
 255
 256 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 257
 258         * disassemble.c (disassemble_init_for_target): Set endian_code for
 259         bpf targets.
 260         * bpf-desc.c: Regenerate.
 261         * bpf-opc.c: Likewise.
 262         * bpf-dis.c: Likewise.
 263
 264 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 265
 266         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 267         (cgen_put_insn_value): Likewise.
 268         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 269         * cgen-dis.in (print_insn): Likewise.
 270         * cgen-ibld.in (insert_1): Likewise.
 271         (insert_1): Likewise.
 272         (insert_insn_normal): Likewise.
 273         (extract_1): Likewise.
 274         * bpf-dis.c: Regenerate.
 275         * bpf-ibld.c: Likewise.
 276         * bpf-ibld.c: Likewise.
 277         * cgen-dis.in: Likewise.
 278         * cgen-ibld.in: Likewise.
 279         * cgen-opc.c: Likewise.
 280         * epiphany-dis.c: Likewise.
 281         * epiphany-ibld.c: Likewise.
 282         * fr30-dis.c: Likewise.
 283         * fr30-ibld.c: Likewise.
 284         * frv-dis.c: Likewise.
 285         * frv-ibld.c: Likewise.
 286         * ip2k-dis.c: Likewise.
 287         * ip2k-ibld.c: Likewise.
 288         * iq2000-dis.c: Likewise.
 289         * iq2000-ibld.c: Likewise.
 290         * lm32-dis.c: Likewise.
 291         * lm32-ibld.c: Likewise.
 292         * m32c-dis.c: Likewise.
 293         * m32c-ibld.c: Likewise.
 294         * m32r-dis.c: Likewise.
 295         * m32r-ibld.c: Likewise.
 296         * mep-dis.c: Likewise.
 297         * mep-ibld.c: Likewise.
 298         * mt-dis.c: Likewise.
 299         * mt-ibld.c: Likewise.
 300         * or1k-dis.c: Likewise.
 301         * or1k-ibld.c: Likewise.
 302         * xc16x-dis.c: Likewise.
 303         * xc16x-ibld.c: Likewise.
 304         * xstormy16-dis.c: Likewise.
 305         * xstormy16-ibld.c: Likewise.
 306
 307 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 308
 309         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 310         (print_insn_): Handle instruction endian.
 311         * bpf-dis.c: Regenerate.
 312         * bpf-desc.c: Regenerate.
 313         * epiphany-dis.c: Likewise.
 314         * epiphany-desc.c: Likewise.
 315         * fr30-dis.c: Likewise.
 316         * fr30-desc.c: Likewise.
 317         * frv-dis.c: Likewise.
 318         * frv-desc.c: Likewise.
 319         * ip2k-dis.c: Likewise.
 320         * ip2k-desc.c: Likewise.
 321         * iq2000-dis.c: Likewise.
 322         * iq2000-desc.c: Likewise.
 323         * lm32-dis.c: Likewise.
 324         * lm32-desc.c: Likewise.
 325         * m32c-dis.c: Likewise.
 326         * m32c-desc.c: Likewise.
 327         * m32r-dis.c: Likewise.
 328         * m32r-desc.c: Likewise.
 329         * mep-dis.c: Likewise.
 330         * mep-desc.c: Likewise.
 331         * mt-dis.c: Likewise.
 332         * mt-desc.c: Likewise.
 333         * or1k-dis.c: Likewise.
 334         * or1k-desc.c: Likewise.
 335         * xc16x-dis.c: Likewise.
 336         * xc16x-desc.c: Likewise.
 337         * xstormy16-dis.c: Likewise.
 338         * xstormy16-desc.c: Likewise.
 339
 340 2020-06-03  Nick Clifton  <nickc@redhat.com>
 341
 342         * po/sr.po: Updated Serbian translation.
 343
 344 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 345
 346         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 347         (riscv_get_priv_spec_class): Likewise.
 348
 349 2020-06-01  Alan Modra  <amodra@gmail.com>
 350
 351         * bpf-desc.c: Regenerate.
 352
 353 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 354             David Faust <david.faust@oracle.com>
 355
 356         * bpf-desc.c: Regenerate.
 357         * bpf-opc.h: Likewise.
 358         * bpf-opc.c: Likewise.
 359         * bpf-dis.c: Likewise.
 360
 361 2020-05-28  Alan Modra  <amodra@gmail.com>
 362
 363         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 364         values.
 365
 366 2020-05-28  Alan Modra  <amodra@gmail.com>
 367
 368         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 369         immediates.
 370         (print_insn_ns32k): Revert last change.
 371
 372 2020-05-28  Nick Clifton  <nickc@redhat.com>
 373
 374         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 375         static.
 376
 377 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 378
 379         Fix extraction of signed constants in nios2 disassembler (again).
 380
 381         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 382         extractions of signed fields.
 383
 384 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 385
 386         * s390-opc.txt: Relocate vector load/store instructions with
 387         additional alignment parameter and change architecture level
 388         constraint from z14 to z13.
 389
 390 2020-05-21  Alan Modra  <amodra@gmail.com>
 391
 392         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 393         * sparc-dis.c: Likewise.
 394         * tic4x-dis.c: Likewise.
 395         * xtensa-dis.c: Likewise.
 396         * bpf-desc.c: Regenerate.
 397         * epiphany-desc.c: Regenerate.
 398         * fr30-desc.c: Regenerate.
 399         * frv-desc.c: Regenerate.
 400         * ip2k-desc.c: Regenerate.
 401         * iq2000-desc.c: Regenerate.
 402         * lm32-desc.c: Regenerate.
 403         * m32c-desc.c: Regenerate.
 404         * m32r-desc.c: Regenerate.
 405         * mep-asm.c: Regenerate.
 406         * mep-desc.c: Regenerate.
 407         * mt-desc.c: Regenerate.
 408         * or1k-desc.c: Regenerate.
 409         * xc16x-desc.c: Regenerate.
 410         * xstormy16-desc.c: Regenerate.
 411
 412 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 413
 414         * riscv-opc.c (riscv_ext_version_table): The table used to store
 415         all information about the supported spec and the corresponding ISA
 416         versions.  Currently, only Zicsr is supported to verify the
 417         correctness of Z sub extension settings.  Others will be supported
 418         in the future patches.
 419         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 420         classes and the corresponding strings.
 421         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 422         spec class by giving a ISA spec string.
 423         * riscv-opc.c (struct priv_spec_t): New structure.
 424         (struct priv_spec_t priv_specs): List for all supported privilege spec
 425         classes and the corresponding strings.
 426         (riscv_get_priv_spec_class): New function.  Get the corresponding
 427         privilege spec class by giving a spec string.
 428         (riscv_get_priv_spec_name): New function.  Get the corresponding
 429         privilege spec string by giving a CSR version class.
 430         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 431         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 432         according to the chosen version.  Build a hash table riscv_csr_hash to
 433         store the valid CSR for the chosen pirv verison.  Dump the direct
 434         CSR address rather than it's name if it is invalid.
 435         (parse_riscv_dis_option_without_args): New function.  Parse the options
 436         without arguments.
 437         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 438         parse the options without arguments first, and then handle the options
 439         with arguments.  Add the new option -Mpriv-spec, which has argument.
 440         * riscv-dis.c (print_riscv_disassembler_options): Add description
 441         about the new OBJDUMP option.
 442
 443 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 444
 445         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 446         WC values on POWER10 sync, dcbf  and wait instructions.
 447         (insert_pl, extract_pl): New functions.
 448         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 449         (LS3): New , 3-bit L for sync.
 450         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 451         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 452         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 453         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 454         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 455         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 456         <wait>: Enable PL operand on POWER10.
 457         <dcbf>: Enable L3OPT operand on POWER10.
 458         <sync>: Enable SC2 operand on POWER10.
 459
 460 2020-05-19  Stafford Horne  <shorne@gmail.com>
 461
 462         PR 25184
 463         * or1k-asm.c: Regenerate.
 464         * or1k-desc.c: Regenerate.
 465         * or1k-desc.h: Regenerate.
 466         * or1k-dis.c: Regenerate.
 467         * or1k-ibld.c: Regenerate.
 468         * or1k-opc.c: Regenerate.
 469         * or1k-opc.h: Regenerate.
 470         * or1k-opinst.c: Regenerate.
 471
 472 2020-05-11  Alan Modra  <amodra@gmail.com>
 473
 474         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 475         xsmaxcqp, xsmincqp.
 476
 477 2020-05-11  Alan Modra  <amodra@gmail.com>
 478
 479         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 480         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 481
 482 2020-05-11  Alan Modra  <amodra@gmail.com>
 483
 484         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 485
 486 2020-05-11  Alan Modra  <amodra@gmail.com>
 487
 488         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 489         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 490
 491 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 492
 493         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 494         mnemonics.
 495
 496 2020-05-11  Alan Modra  <amodra@gmail.com>
 497
 498         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 499         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 500         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 501         (prefix_opcodes): Add xxeval.
 502
 503 2020-05-11  Alan Modra  <amodra@gmail.com>
 504
 505         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 506         xxgenpcvwm, xxgenpcvdm.
 507
 508 2020-05-11  Alan Modra  <amodra@gmail.com>
 509
 510         * ppc-opc.c (MP, VXVAM_MASK): Define.
 511         (VXVAPS_MASK): Use VXVA_MASK.
 512         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 513         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 514         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 515         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 516
 517 2020-05-11  Alan Modra  <amodra@gmail.com>
 518             Peter Bergner  <bergner@linux.ibm.com>
 519
 520         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 521         New functions.
 522         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 523         YMSK2, XA6a, XA6ap, XB6a entries.
 524         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 525         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 526         (PPCVSX4): Define.
 527         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 528         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 529         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 530         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 531         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 532         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 533         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 534         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 535         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 536         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 537         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 538         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 539         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 540         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 541
 542 2020-05-11  Alan Modra  <amodra@gmail.com>
 543
 544         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 545         (insert_xts, extract_xts): New functions.
 546         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 547         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 548         (VXRC_MASK, VXSH_MASK): Define.
 549         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 550         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 551         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 552         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 553         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 554         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 555         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 556
 557 2020-05-11  Alan Modra  <amodra@gmail.com>
 558
 559         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 560         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 561         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 562         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 563         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 564
 565 2020-05-11  Alan Modra  <amodra@gmail.com>
 566
 567         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 568         (XTP, DQXP, DQXP_MASK): Define.
 569         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 570         (prefix_opcodes): Add plxvp and pstxvp.
 571
 572 2020-05-11  Alan Modra  <amodra@gmail.com>
 573
 574         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 575         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 576         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 577
 578 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 579
 580         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 581
 582 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 583
 584         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 585         (L1OPT): Define.
 586         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 587
 588 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 589
 590         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 591
 592 2020-05-11  Alan Modra  <amodra@gmail.com>
 593
 594         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 595
 596 2020-05-11  Alan Modra  <amodra@gmail.com>
 597
 598         * ppc-dis.c (ppc_opts): Add "power10" entry.
 599         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 600         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 601
 602 2020-05-11  Nick Clifton  <nickc@redhat.com>
 603
 604         * po/fr.po: Updated French translation.
 605
 606 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 607
 608         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 609         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 610         (operand_general_constraint_met_p): validate
 611         AARCH64_OPND_UNDEFINED.
 612         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 613         for FLD_imm16_2.
 614         * aarch64-asm-2.c: Regenerated.
 615         * aarch64-dis-2.c: Regenerated.
 616         * aarch64-opc-2.c: Regenerated.
 617
 618 2020-04-29  Nick Clifton  <nickc@redhat.com>
 619
 620         PR 22699
 621         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 622         and SETRC insns.
 623
 624 2020-04-29  Nick Clifton  <nickc@redhat.com>
 625
 626         * po/sv.po: Updated Swedish translation.
 627
 628 2020-04-29  Nick Clifton  <nickc@redhat.com>
 629
 630         PR 22699
 631         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 632         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 633         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 634         IMM0_8U case.
 635
 636 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 637
 638         PR 25848
 639         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 640         cmpi only on m68020up and cpu32.
 641
 642 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 643
 644         * aarch64-asm.c (aarch64_ins_none): New.
 645         * aarch64-asm.h (ins_none): New declaration.
 646         * aarch64-dis.c (aarch64_ext_none): New.
 647         * aarch64-dis.h (ext_none): New declaration.
 648         * aarch64-opc.c (aarch64_print_operand): Update case for
 649         AARCH64_OPND_BARRIER_PSB.
 650         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 651         (AARCH64_OPERANDS): Update inserter/extracter for
 652         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 653         * aarch64-asm-2.c: Regenerated.
 654         * aarch64-dis-2.c: Regenerated.
 655         * aarch64-opc-2.c: Regenerated.
 656
 657 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 658
 659         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 660         (aarch64_feature_ras, RAS): Likewise.
 661         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 662         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 663         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 664         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 665         * aarch64-asm-2.c: Regenerated.
 666         * aarch64-dis-2.c: Regenerated.
 667         * aarch64-opc-2.c: Regenerated.
 668
 669 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 670
 671         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 672         (print_insn_neon): Support disassembly of conditional
 673         instructions.
 674
 675 2020-02-16  David Faust  <david.faust@oracle.com>
 676
 677         * bpf-desc.c: Regenerate.
 678         * bpf-desc.h: Likewise.
 679         * bpf-opc.c: Regenerate.
 680         * bpf-opc.h: Likewise.
 681
 682 2020-04-07  Lili Cui  <lili.cui@intel.com>
 683
 684         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 685         (prefix_table): New instructions (see prefixes above).
 686         (rm_table): Likewise
 687         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 688         CPU_ANY_TSXLDTRK_FLAGS.
 689         (cpu_flags): Add CpuTSXLDTRK.
 690         * i386-opc.h (enum): Add CpuTSXLDTRK.
 691         (i386_cpu_flags): Add cputsxldtrk.
 692         * i386-opc.tbl: Add XSUSPLDTRK insns.
 693         * i386-init.h: Regenerate.
 694         * i386-tbl.h: Likewise.
 695
 696 2020-04-02  Lili Cui  <lili.cui@intel.com>
 697
 698         * i386-dis.c (prefix_table): New instructions serialize.
 699         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 700         CPU_ANY_SERIALIZE_FLAGS.
 701         (cpu_flags): Add CpuSERIALIZE.
 702         * i386-opc.h (enum): Add CpuSERIALIZE.
 703         (i386_cpu_flags): Add cpuserialize.
 704         * i386-opc.tbl: Add SERIALIZE insns.
 705         * i386-init.h: Regenerate.
 706         * i386-tbl.h: Likewise.
 707
 708 2020-03-26  Alan Modra  <amodra@gmail.com>
 709
 710         * disassemble.h (opcodes_assert): Declare.
 711         (OPCODES_ASSERT): Define.
 712         * disassemble.c: Don't include assert.h.  Include opintl.h.
 713         (opcodes_assert): New function.
 714         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 715         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 716         calculate maxlen.  Omit insn decoding when insn length exceeds
 717         maxlen.  Exit from nibble loop when looking for E, before
 718         accessing next data byte.  Move processing of E outside loop.
 719         Replace tests of maxlen in loop with assertions.
 720
 721 2020-03-26  Alan Modra  <amodra@gmail.com>
 722
 723         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 724
 725 2020-03-25  Alan Modra  <amodra@gmail.com>
 726
 727         * z80-dis.c (suffix): Init mybuf.
 728
 729 2020-03-22  Alan Modra  <amodra@gmail.com>
 730
 731         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 732         successflly read from section.
 733
 734 2020-03-22  Alan Modra  <amodra@gmail.com>
 735
 736         * arc-dis.c (find_format): Use ISO C string concatenation rather
 737         than line continuation within a string.  Don't access needs_limm
 738         before testing opcode != NULL.
 739
 740 2020-03-22  Alan Modra  <amodra@gmail.com>
 741
 742         * ns32k-dis.c (print_insn_arg): Update comment.
 743         (print_insn_ns32k): Reduce size of index_offset array, and
 744         initialize, passing -1 to print_insn_arg for args that are not
 745         an index.  Don't exit arg loop early.  Abort on bad arg number.
 746
 747 2020-03-22  Alan Modra  <amodra@gmail.com>
 748
 749         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 750         * s12z-opc.c: Formatting.
 751         (operands_f): Return an int.
 752         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 753         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 754         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 755         (exg_sex_discrim): Likewise.
 756         (create_immediate_operand, create_bitfield_operand),
 757         (create_register_operand_with_size, create_register_all_operand),
 758         (create_register_all16_operand, create_simple_memory_operand),
 759         (create_memory_operand, create_memory_auto_operand): Don't
 760         segfault on malloc failure.
 761         (z_ext24_decode): Return an int status, negative on fail, zero
 762         on success.
 763         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 764         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 765         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 766         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 767         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 768         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 769         (loop_primitive_decode, shift_decode, psh_pul_decode),
 770         (bit_field_decode): Similarly.
 771         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 772         to return value, update callers.
 773         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 774         Don't segfault on NULL operand.
 775         (decode_operation): Return OP_INVALID on first fail.
 776         (decode_s12z): Check all reads, returning -1 on fail.
 777
 778 2020-03-20  Alan Modra  <amodra@gmail.com>
 779
 780         * metag-dis.c (print_insn_metag): Don't ignore status from
 781         read_memory_func.
 782
 783 2020-03-20  Alan Modra  <amodra@gmail.com>
 784
 785         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 786         Initialize parts of buffer not written when handling a possible
 787         2-byte insn at end of section.  Don't attempt decoding of such
 788         an insn by the 4-byte machinery.
 789
 790 2020-03-20  Alan Modra  <amodra@gmail.com>
 791
 792         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 793         partially filled buffer.  Prevent lookup of 4-byte insns when
 794         only VLE 2-byte insns are possible due to section size.  Print
 795         ".word" rather than ".long" for 2-byte leftovers.
 796
 797 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 798
 799         PR 25641
 800         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 801
 802 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 803
 804         * i386-dis.c (X86_64_0D): Rename to ...
 805         (X86_64_0E): ... this.
 806
 807 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 808
 809         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 810         * Makefile.in: Regenerated.
 811
 812 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 813
 814         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 815         3-operand pseudos.
 816         * i386-tbl.h: Re-generate.
 817
 818 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 819
 820         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 821         vprot*, vpsha*, and vpshl*.
 822         * i386-tbl.h: Re-generate.
 823
 824 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 825
 826         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 827         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 828         * i386-tbl.h: Re-generate.
 829
 830 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 831
 832         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 833         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 834         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 835         * i386-tbl.h: Re-generate.
 836
 837 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 838
 839         * i386-gen.c (struct template_arg, struct template_instance,
 840         struct template_param, struct template, templates,
 841         parse_template, expand_templates): New.
 842         (process_i386_opcodes): Various local variables moved to
 843         expand_templates. Call parse_template and expand_templates.
 844         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 845         * i386-tbl.h: Re-generate.
 846
 847 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 848
 849         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 850         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 851         register and memory source templates. Replace VexW= by VexW*
 852         where applicable.
 853         * i386-tbl.h: Re-generate.
 854
 855 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 856
 857         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 858         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 859         * i386-tbl.h: Re-generate.
 860
 861 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 862
 863         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 864         * i386-tbl.h: Re-generate.
 865
 866 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 867
 868         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 869         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 870         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 871         VexW0 on SSE2AVX variants.
 872         (vmovq): Drop NoRex64 from XMM/XMM variants.
 873         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 874         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 875         applicable use VexW0.
 876         * i386-tbl.h: Re-generate.
 877
 878 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 879
 880         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 881         * i386-opc.h (Rex64): Delete.
 882         (struct i386_opcode_modifier): Remove rex64 field.
 883         * i386-opc.tbl (crc32): Drop Rex64.
 884         Replace Rex64 with Size64 everywhere else.
 885         * i386-tbl.h: Re-generate.
 886
 887 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 888
 889         * i386-dis.c (OP_E_memory): Exclude recording of used address
 890         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 891         addressed memory operands for MPX insns.
 892
 893 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 894
 895         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 896         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 897         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 898         (ptwrite): Split into non-64-bit and 64-bit forms.
 899         * i386-tbl.h: Re-generate.
 900
 901 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 902
 903         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 904         template.
 905         * i386-tbl.h: Re-generate.
 906
 907 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 908
 909         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 910         (prefix_table): Move vmmcall here. Add vmgexit.
 911         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 912         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 913         (cpu_flags): Add CpuSEV_ES entry.
 914         * i386-opc.h (CpuSEV_ES): New.
 915         (union i386_cpu_flags): Add cpusev_es field.
 916         * i386-opc.tbl (vmgexit): New.
 917         * i386-init.h, i386-tbl.h: Re-generate.
 918
 919 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 920
 921         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 922         with MnemonicSize.
 923         * i386-opc.h (IGNORESIZE): New.
 924         (DEFAULTSIZE): Likewise.
 925         (IgnoreSize): Removed.
 926         (DefaultSize): Likewise.
 927         (MnemonicSize): New.
 928         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 929         mnemonicsize.
 930         * i386-opc.tbl (IgnoreSize): New.
 931         (DefaultSize): Likewise.
 932         * i386-tbl.h: Regenerated.
 933
 934 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 935
 936         PR 25627
 937         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 938         instructions.
 939
 940 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 941
 942         PR gas/25622
 943         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 944         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 945         * i386-tbl.h: Regenerated.
 946
 947 2020-02-26  Alan Modra  <amodra@gmail.com>
 948
 949         * aarch64-asm.c: Indent labels correctly.
 950         * aarch64-dis.c: Likewise.
 951         * aarch64-gen.c: Likewise.
 952         * aarch64-opc.c: Likewise.
 953         * alpha-dis.c: Likewise.
 954         * i386-dis.c: Likewise.
 955         * nds32-asm.c: Likewise.
 956         * nfp-dis.c: Likewise.
 957         * visium-dis.c: Likewise.
 958
 959 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 960
 961         * arc-regs.h (int_vector_base): Make it available for all ARC
 962         CPUs.
 963
 964 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 965
 966         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 967         changed.
 968
 969 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 970
 971         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 972         c.mv/c.li if rs1 is zero.
 973
 974 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 975
 976         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 977         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 978         CPU_POPCNT_FLAGS.
 979         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 980         * i386-opc.h (CpuABM): Removed.
 981         (CpuPOPCNT): New.
 982         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 983         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 984         popcnt.  Remove CpuABM from lzcnt.
 985         * i386-init.h: Regenerated.
 986         * i386-tbl.h: Likewise.
 987
 988 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 989
 990         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 991         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 992         VexW1 instead of open-coding them.
 993         * i386-tbl.h: Re-generate.
 994
 995 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 996
 997         * i386-opc.tbl (AddrPrefixOpReg): Define.
 998         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 999         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1000         templates. Drop NoRex64.
1001         * i386-tbl.h: Re-generate.
1002
1003 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1004
1005         PR gas/6518
1006         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1007         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1008         into Intel syntax instance (with Unpsecified) and AT&T one
1009         (without).
1010         (vcvtneps2bf16): Likewise, along with folding the two so far
1011         separate ones.
1012         * i386-tbl.h: Re-generate.
1013
1014 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1015
1016         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1017         CPU_ANY_SSE4A_FLAGS.
1018
1019 2020-02-17  Alan Modra  <amodra@gmail.com>
1020
1021         * i386-gen.c (cpu_flag_init): Correct last change.
1022
1023 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1024
1025         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
1026         CPU_ANY_SSE4_FLAGS.
1027
1028 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
1029
1030         * i386-opc.tbl (movsx): Remove Intel syntax comments.
1031         (movzx): Likewise.
1032
1033 2020-02-14  Jan Beulich  <jbeulich@suse.com>
1034
1035         PR gas/25438
1036         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1037         destination for Cpu64-only variant.
1038         (movzx): Fold patterns.
1039         * i386-tbl.h: Re-generate.
1040
1041 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1042
1043         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1044         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1045         CPU_ANY_SSE4_FLAGS entry.
1046         * i386-init.h: Re-generate.
1047
1048 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1049
1050         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1051         with Unspecified, making the present one AT&T syntax only.
1052         * i386-tbl.h: Re-generate.
1053
1054 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1055
1056         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1057         * i386-tbl.h: Re-generate.
1058
1059 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1060
1061         PR gas/24546
1062         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1063         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1064         Amd64 and Intel64 templates.
1065         (call, jmp): Likewise for far indirect variants. Dro
1066         Unspecified.
1067         * i386-tbl.h: Re-generate.
1068
1069 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1070
1071         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1072         * i386-opc.h (ShortForm): Delete.
1073         (struct i386_opcode_modifier): Remove shortform field.
1074         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1075         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1076         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1077         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1078         Drop ShortForm.
1079         * i386-tbl.h: Re-generate.
1080
1081 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1082
1083         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1084         fucompi): Drop ShortForm from operand-less templates.
1085         * i386-tbl.h: Re-generate.
1086
1087 2020-02-11  Alan Modra  <amodra@gmail.com>
1088
1089         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1090         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1091         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1092         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1093         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1094
1095 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1096
1097         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1098         (cde_opcodes): Add VCX* instructions.
1099
1100 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1101             Matthew Malcomson  <matthew.malcomson@arm.com>
1102
1103         * arm-dis.c (struct cdeopcode32): New.
1104         (CDE_OPCODE): New macro.
1105         (cde_opcodes): New disassembly table.
1106         (regnames): New option to table.
1107         (cde_coprocs): New global variable.
1108         (print_insn_cde): New
1109         (print_insn_thumb32): Use print_insn_cde.
1110         (parse_arm_disassembler_options): Parse coprocN args.
1111
1112 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1113
1114         PR gas/25516
1115         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1116         with ISA64.
1117         * i386-opc.h (AMD64): Removed.
1118         (Intel64): Likewose.
1119         (AMD64): New.
1120         (INTEL64): Likewise.
1121         (INTEL64ONLY): Likewise.
1122         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1123         * i386-opc.tbl (Amd64): New.
1124         (Intel64): Likewise.
1125         (Intel64Only): Likewise.
1126         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1127         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1128         * i386-tbl.h: Regenerated.
1129
1130 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1131
1132         PR 25469
1133         * z80-dis.c: Add support for GBZ80 opcodes.
1134
1135 2020-02-04  Alan Modra  <amodra@gmail.com>
1136
1137         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1138
1139 2020-02-03  Alan Modra  <amodra@gmail.com>
1140
1141         * m32c-ibld.c: Regenerate.
1142
1143 2020-02-01  Alan Modra  <amodra@gmail.com>
1144
1145         * frv-ibld.c: Regenerate.
1146
1147 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1148
1149         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1150         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1151         (OP_E_memory): Replace xmm_mdq_mode case label by
1152         vex_scalar_w_dq_mode one.
1153         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1154
1155 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1156
1157         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1158         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1159         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1160         (intel_operand_size): Drop vex_w_dq_mode case label.
1161
1162 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1163
1164         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1165         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1166
1167 2020-01-30  Alan Modra  <amodra@gmail.com>
1168
1169         * m32c-ibld.c: Regenerate.
1170
1171 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1172
1173         * bpf-opc.c: Regenerate.
1174
1175 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1176
1177         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1178         (dis386): Use them to replace C2/C3 table entries.
1179         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1180         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1181         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1182         * i386-tbl.h: Re-generate.
1183
1184 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1185
1186         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1187         forms.
1188         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1189         DefaultSize.
1190         * i386-tbl.h: Re-generate.
1191
1192 2020-01-30  Alan Modra  <amodra@gmail.com>
1193
1194         * tic4x-dis.c (tic4x_dp): Make unsigned.
1195
1196 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1197             Jan Beulich  <jbeulich@suse.com>
1198
1199         PR binutils/25445
1200         * i386-dis.c (MOVSXD_Fixup): New function.
1201         (movsxd_mode): New enum.
1202         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1203         (intel_operand_size): Handle movsxd_mode.
1204         (OP_E_register): Likewise.
1205         (OP_G): Likewise.
1206         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1207         register on movsxd.  Add movsxd with 16-bit destination register
1208         for AMD64 and Intel64 ISAs.
1209         * i386-tbl.h: Regenerated.
1210
1211 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1212
1213         PR 25403
1214         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1215         * aarch64-asm-2.c: Regenerate
1216         * aarch64-dis-2.c: Likewise.
1217         * aarch64-opc-2.c: Likewise.
1218
1219 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1220
1221         * i386-opc.tbl (sysret): Drop DefaultSize.
1222         * i386-tbl.h: Re-generate.
1223
1224 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1225
1226         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1227         Dword.
1228         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1229         * i386-tbl.h: Re-generate.
1230
1231 2020-01-20  Nick Clifton  <nickc@redhat.com>
1232
1233         * po/de.po: Updated German translation.
1234         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1235         * po/uk.po: Updated Ukranian translation.
1236
1237 2020-01-20  Alan Modra  <amodra@gmail.com>
1238
1239         * hppa-dis.c (fput_const): Remove useless cast.
1240
1241 2020-01-20  Alan Modra  <amodra@gmail.com>
1242
1243         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1244
1245 2020-01-18  Nick Clifton  <nickc@redhat.com>
1246
1247         * configure: Regenerate.
1248         * po/opcodes.pot: Regenerate.
1249
1250 2020-01-18  Nick Clifton  <nickc@redhat.com>
1251
1252         Binutils 2.34 branch created.
1253
1254 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1255
1256         * opintl.h: Fix spelling error (seperate).
1257
1258 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1259
1260         * i386-opc.tbl: Add {vex} pseudo prefix.
1261         * i386-tbl.h: Regenerated.
1262
1263 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1264
1265         PR 25376
1266         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1267         (neon_opcodes): Likewise.
1268         (select_arm_features): Make sure we enable MVE bits when selecting
1269         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1270         any architecture.
1271
1272 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1273
1274         * i386-opc.tbl: Drop stale comment from XOP section.
1275
1276 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1277
1278         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1279         (extractps): Add VexWIG to SSE2AVX forms.
1280         * i386-tbl.h: Re-generate.
1281
1282 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1283
1284         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1285         Size64 from and use VexW1 on SSE2AVX forms.
1286         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1287         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1288         * i386-tbl.h: Re-generate.
1289
1290 2020-01-15  Alan Modra  <amodra@gmail.com>
1291
1292         * tic4x-dis.c (tic4x_version): Make unsigned long.
1293         (optab, optab_special, registernames): New file scope vars.
1294         (tic4x_print_register): Set up registernames rather than
1295         malloc'd registertable.
1296         (tic4x_disassemble): Delete optable and optable_special.  Use
1297         optab and optab_special instead.  Throw away old optab,
1298         optab_special and registernames when info->mach changes.
1299
1300 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1301
1302         PR 25377
1303         * z80-dis.c (suffix): Use .db instruction to generate double
1304         prefix.
1305
1306 2020-01-14  Alan Modra  <amodra@gmail.com>
1307
1308         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1309         values to unsigned before shifting.
1310
1311 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1312
1313         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1314         flow instructions.
1315         (print_insn_thumb16, print_insn_thumb32): Likewise.
1316         (print_insn): Initialize the insn info.
1317         * i386-dis.c (print_insn): Initialize the insn info fields, and
1318         detect jumps.
1319
1320 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1321
1322         * arc-opc.c (C_NE): Make it required.
1323
1324 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1325
1326         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1327         reserved register name.
1328
1329 2020-01-13  Alan Modra  <amodra@gmail.com>
1330
1331         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1332         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1333
1334 2020-01-13  Alan Modra  <amodra@gmail.com>
1335
1336         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1337         result of wasm_read_leb128 in a uint64_t and check that bits
1338         are not lost when copying to other locals.  Use uint32_t for
1339         most locals.  Use PRId64 when printing int64_t.
1340
1341 2020-01-13  Alan Modra  <amodra@gmail.com>
1342
1343         * score-dis.c: Formatting.
1344         * score7-dis.c: Formatting.
1345
1346 2020-01-13  Alan Modra  <amodra@gmail.com>
1347
1348         * score-dis.c (print_insn_score48): Use unsigned variables for
1349         unsigned values.  Don't left shift negative values.
1350         (print_insn_score32): Likewise.
1351         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1352
1353 2020-01-13  Alan Modra  <amodra@gmail.com>
1354
1355         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1356
1357 2020-01-13  Alan Modra  <amodra@gmail.com>
1358
1359         * fr30-ibld.c: Regenerate.
1360
1361 2020-01-13  Alan Modra  <amodra@gmail.com>
1362
1363         * xgate-dis.c (print_insn): Don't left shift signed value.
1364         (ripBits): Formatting, use 1u.
1365
1366 2020-01-10  Alan Modra  <amodra@gmail.com>
1367
1368         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1369         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1370
1371 2020-01-10  Alan Modra  <amodra@gmail.com>
1372
1373         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1374         and XRREG value earlier to avoid a shift with negative exponent.
1375         * m10200-dis.c (disassemble): Similarly.
1376
1377 2020-01-09  Nick Clifton  <nickc@redhat.com>
1378
1379         PR 25224
1380         * z80-dis.c (ld_ii_ii): Use correct cast.
1381
1382 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1383
1384         PR 25224
1385         * z80-dis.c (ld_ii_ii): Use character constant when checking
1386         opcode byte value.
1387
1388 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1389
1390         * i386-dis.c (SEP_Fixup): New.
1391         (SEP): Define.
1392         (dis386_twobyte): Use it for sysenter/sysexit.
1393         (enum x86_64_isa): Change amd64 enumerator to value 1.
1394         (OP_J): Compare isa64 against intel64 instead of amd64.
1395         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1396         forms.
1397         * i386-tbl.h: Re-generate.
1398
1399 2020-01-08  Alan Modra  <amodra@gmail.com>
1400
1401         * z8k-dis.c: Include libiberty.h
1402         (instr_data_s): Make max_fetched unsigned.
1403         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1404         Don't exceed byte_info bounds.
1405         (output_instr): Make num_bytes unsigned.
1406         (unpack_instr): Likewise for nibl_count and loop.
1407         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1408         idx unsigned.
1409         * z8k-opc.h: Regenerate.
1410
1411 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1412
1413         * arc-tbl.h (llock): Use 'LLOCK' as class.
1414         (llockd): Likewise.
1415         (scond): Use 'SCOND' as class.
1416         (scondd): Likewise.
1417         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1418         (scondd): Likewise.
1419
1420 2020-01-06  Alan Modra  <amodra@gmail.com>
1421
1422         * m32c-ibld.c: Regenerate.
1423
1424 2020-01-06  Alan Modra  <amodra@gmail.com>
1425
1426         PR 25344
1427         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1428         Peek at next byte to prevent recursion on repeated prefix bytes.
1429         Ensure uninitialised "mybuf" is not accessed.
1430         (print_insn_z80): Don't zero n_fetch and n_used here,..
1431         (print_insn_z80_buf): ..do it here instead.
1432
1433 2020-01-04  Alan Modra  <amodra@gmail.com>
1434
1435         * m32r-ibld.c: Regenerate.
1436
1437 2020-01-04  Alan Modra  <amodra@gmail.com>
1438
1439         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1440
1441 2020-01-04  Alan Modra  <amodra@gmail.com>
1442
1443         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1444
1445 2020-01-04  Alan Modra  <amodra@gmail.com>
1446
1447         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1448
1449 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1450
1451         * aarch64-tbl.h (aarch64_opcode_table): Use
1452         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1453
1454 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1455
1456         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1457         forms of SUDOT and USDOT.
1458
1459 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1460
1461         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1462         uzip{1,2}.
1463         * opcodes/aarch64-dis-2.c: Re-generate.
1464
1465 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1466
1467         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1468         FMMLA encoding.
1469         * opcodes/aarch64-dis-2.c: Re-generate.
1470
1471 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1472
1473         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1474
1475 2020-01-01  Alan Modra  <amodra@gmail.com>
1476
1477         Update year range in copyright notice of all files.
1478
1479 For older changes see ChangeLog-2019
1480 \f
1481 Copyright (C) 2020 Free Software Foundation, Inc.
1482
1483 Copying and distribution of this file, with or without modification,
1484 are permitted in any medium without royalty provided the copyright
1485 notice and this notice are preserved.
1486
1487 Local Variables:
1488 mode: change-log
1489 left-margin: 8
1490 fill-column: 74
1491 version-control: never
1492 End: