opcodes/ChangeLog

   1 2020-07-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
   4         vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
   5         EXymm.
   6         (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
   7         Likewise. Mark 256-bit entries invalid.
   8
   9 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  10
  11         * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
  12         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
  13         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
  14         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
  15         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
  16         PREFIX_EVEX_0F382B): Delete.
  17         (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
  18         EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
  19         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
  20         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
  21         EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
  22         to ...
  23         (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
  24         EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
  25         EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
  26         EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
  27         respectively.
  28         * i386-dis-evex.h (evex_table): Reference VEX_W table entries
  29         for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
  30         0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
  31         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
  32         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
  33         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
  34         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
  35         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
  36         PREFIX_EVEX_0F382B): Remove table entries.
  37         * i386-dis-evex-w.h: Reference VEX table entries for opcodes
  38         0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
  39         0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
  40
  41 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
  44         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
  45         enumerators.
  46         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
  47         EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
  48         EVEX_LEN_0F3A01_P_2_W_1 table entries.
  49         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
  50         entries.
  51
  52 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  53
  54         * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
  55         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
  56         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
  57         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
  58         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
  59         EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
  60         EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
  61         EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
  62         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
  63         entries.
  64
  65 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  66
  67         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
  68         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
  69         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
  70         respectively.
  71         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
  72         entries.
  73         * i386-dis-evex.h (evex_table): Reference VEX table entry for
  74         opcode 0F3A1D.
  75         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
  76         entry.
  77         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
  78
  79 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
  82         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
  83         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
  84         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
  85         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
  86         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
  87         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
  88         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
  89         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
  90         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
  91         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
  92         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
  93         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
  94         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
  95         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
  96         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
  97         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
  98         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
  99         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
 100         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
 101         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
 102         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
 103         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
 104         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
 105         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
 106         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
 107         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
 108         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
 109         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
 110         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
 111         (prefix_table): Add EXxEVexR to FMA table entries.
 112         (OP_Rounding): Move abort() invocation.
 113         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
 114         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
 115         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
 116         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
 117         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
 118         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
 119         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
 120         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
 121         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
 122         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
 123         0F3ACE, 0F3ACF.
 124         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
 125         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 126         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
 127         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
 128         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 129         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
 130         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
 131         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
 132         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 133         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
 134         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
 135         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
 136         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
 137         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
 138         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
 139         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
 140         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
 141         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
 142         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
 143         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
 144         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
 145         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
 146         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
 147         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
 148         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
 149         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
 150         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
 151         Delete table entries.
 152         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
 153         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
 154         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
 155         Likewise.
 156
 157 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 158
 159         * i386-dis.c (EXqScalarS): Delete.
 160         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
 161         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
 162
 163 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 164
 165         * i386-dis.c (safe-ctype.h): Include.
 166         (EXdScalar, EXqScalar): Delete.
 167         (d_scalar_mode, q_scalar_mode): Delete.
 168         (prefix_table, vex_len_table): Use EXxmm_md in place of
 169         EXdScalar and EXxmm_mq in place of EXqScalar.
 170         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
 171         d_scalar_mode and q_scalar_mode.
 172         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
 173         (vmovsd): Use EXxmm_mq.
 174
 175 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
 176
 177         PR 26204
 178         * arc-dis.c: Fix spelling mistake.
 179         * po/opcodes.pot: Regenerate.
 180
 181 2020-07-06  Nick Clifton  <nickc@redhat.com>
 182
 183         * po/pt_BR.po: Updated Brazilian Portugugese translation.
 184         * po/uk.po: Updated Ukranian translation.
 185
 186 2020-07-04  Nick Clifton  <nickc@redhat.com>
 187
 188         * configure: Regenerate.
 189         * po/opcodes.pot: Regenerate.
 190
 191 2020-07-04  Nick Clifton  <nickc@redhat.com>
 192
 193         Binutils 2.35 branch created.
 194
 195 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
 196
 197         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
 198         * i386-opc.h (VexSwapSources): New.
 199         (i386_opcode_modifier): Add vexswapsources.
 200         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
 201         with two source operands swapped.
 202         * i386-tbl.h: Regenerated.
 203
 204 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
 205
 206         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
 207         unprivileged CSR can also be initialized.
 208
 209 2020-06-29  Alan Modra  <amodra@gmail.com>
 210
 211         * arm-dis.c: Use C style comments.
 212         * cr16-opc.c: Likewise.
 213         * ft32-dis.c: Likewise.
 214         * moxie-opc.c: Likewise.
 215         * tic54x-dis.c: Likewise.
 216         * s12z-opc.c: Remove useless comment.
 217         * xgate-dis.c: Likewise.
 218
 219 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 220
 221         * i386-opc.tbl: Add a blank line.
 222
 223 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 224
 225         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
 226         (VecSIB128): Renamed to ...
 227         (VECSIB128): This.
 228         (VecSIB256): Renamed to ...
 229         (VECSIB256): This.
 230         (VecSIB512): Renamed to ...
 231         (VECSIB512): This.
 232         (VecSIB): Renamed to ...
 233         (SIB): This.
 234         (i386_opcode_modifier): Replace vecsib with sib.
 235         * i386-opc.tbl (VecSIB128): New.
 236         (VecSIB256): Likewise.
 237         (VecSIB512): Likewise.
 238         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
 239         and VecSIB512, respectively.
 240
 241 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 242
 243         * i386-dis.c: Adjust description of I macro.
 244         (x86_64_table): Drop use of I.
 245         (float_mem): Replace use of I.
 246         (putop): Remove handling of I. Adjust setting/clearing of "alt".
 247
 248 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 249
 250         * i386-dis.c: (print_insn): Avoid straight assignment to
 251         priv.orig_sizeflag when processing -M sub-options.
 252
 253 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 254
 255         * i386-dis.c: Adjust description of J macro.
 256         (dis386, x86_64_table, mod_table): Replace J.
 257         (putop): Remove handling of J.
 258
 259 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 260
 261         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
 262
 263 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 264
 265         * i386-dis.c: Adjust description of "LQ" macro.
 266         (dis386_twobyte): Use LQ for sysret.
 267         (putop): Adjust handling of LQ.
 268
 269 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
 270
 271         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
 272         * riscv-dis.c: Include elfxx-riscv.h.
 273
 274 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
 275
 276         * i386-dis.c (prefix_table): Revert the last vmgexit change.
 277
 278 2020-06-17  Lili Cui  <lili.cui@intel.com>
 279
 280         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
 281
 282 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
 283
 284         PR gas/26115
 285         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
 286         * i386-opc.tbl: Likewise.
 287         * i386-tbl.h: Regenerated.
 288
 289 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
 290
 291         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
 292
 293 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
 294
 295         * aarch64-opc.c (SYSREG): New macro for describing system registers.
 296         (SR_CORE): Likewise.
 297         (SR_FEAT): Likewise.
 298         (SR_RNG): Likewise.
 299         (SR_V8_1): Likewise.
 300         (SR_V8_2): Likewise.
 301         (SR_V8_3): Likewise.
 302         (SR_V8_4): Likewise.
 303         (SR_PAN): Likewise.
 304         (SR_RAS): Likewise.
 305         (SR_SSBS): Likewise.
 306         (SR_SVE): Likewise.
 307         (SR_ID_PFR2): Likewise.
 308         (SR_PROFILE): Likewise.
 309         (SR_MEMTAG): Likewise.
 310         (SR_SCXTNUM): Likewise.
 311         (aarch64_sys_regs): Refactor to store feature information in the table.
 312         (aarch64_sys_reg_supported_p): Collapse logic for system registers
 313         that now describe their own features.
 314         (aarch64_pstatefield_supported_p): Likewise.
 315
 316 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 317
 318         * i386-dis.c (prefix_table): Fix a typo in comments.
 319
 320 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 321
 322         * i386-dis.c (rex_ignored): Delete.
 323         (ckprefix): Drop rex_ignored initialization.
 324         (get_valid_dis386): Drop setting of rex_ignored.
 325         (print_insn): Drop checking of rex_ignored. Don't record data
 326         size prefix as used with VEX-and-alike encodings.
 327
 328 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 329
 330         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 331         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 332         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 333         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 334         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 335         VEX_0F12, and VEX_0F16.
 336         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 337         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 338         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 339         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 340         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 341         MOD_VEX_0F16_PREFIX_2 entries.
 342
 343 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 344
 345         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 346         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 347         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 348         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 349         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 350         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 351         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 352         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 353         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 354         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 355         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 356         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 357         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 358         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 359         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 360         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 361         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 362         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 363         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 364         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 365         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 366         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 367         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 368         EVEX_W_0FC6_P_2): Delete.
 369         (print_insn): Add EVEX.W vs embedded prefix consistency check
 370         to prefix validation.
 371         * i386-dis-evex.h (evex_table): Don't further descend for
 372         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 373         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 374         and 0F2B.
 375         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 376         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 377         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 378         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 379         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 380         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 381         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 382         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 383         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 384         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 385         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 386         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 387         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 388         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 389         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 390         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 391         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 392         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 393         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 394         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 395         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 396         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 397         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 398         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 399         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 400         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 401         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 402
 403 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 404
 405         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 406         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 407         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 408         vmovmskpX.
 409         (print_insn): Drop pointless check against bad_opcode. Split
 410         prefix validation into legacy and VEX-and-alike parts.
 411         (putop): Re-work 'X' macro handling.
 412
 413 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 414
 415         * i386-dis.c (MOD_0F51): Rename to ...
 416         (MOD_0F50): ... this.
 417
 418 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 419
 420         * arm-dis.c (arm_opcodes): Add dfb.
 421         (thumb32_opcodes): Add dfb.
 422
 423 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 424
 425         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 426
 427 2020-06-06  Alan Modra  <amodra@gmail.com>
 428
 429         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 430
 431 2020-06-05  Alan Modra  <amodra@gmail.com>
 432
 433         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 434         size is large enough.
 435
 436 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 437
 438         * disassemble.c (disassemble_init_for_target): Set endian_code for
 439         bpf targets.
 440         * bpf-desc.c: Regenerate.
 441         * bpf-opc.c: Likewise.
 442         * bpf-dis.c: Likewise.
 443
 444 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 445
 446         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 447         (cgen_put_insn_value): Likewise.
 448         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 449         * cgen-dis.in (print_insn): Likewise.
 450         * cgen-ibld.in (insert_1): Likewise.
 451         (insert_1): Likewise.
 452         (insert_insn_normal): Likewise.
 453         (extract_1): Likewise.
 454         * bpf-dis.c: Regenerate.
 455         * bpf-ibld.c: Likewise.
 456         * bpf-ibld.c: Likewise.
 457         * cgen-dis.in: Likewise.
 458         * cgen-ibld.in: Likewise.
 459         * cgen-opc.c: Likewise.
 460         * epiphany-dis.c: Likewise.
 461         * epiphany-ibld.c: Likewise.
 462         * fr30-dis.c: Likewise.
 463         * fr30-ibld.c: Likewise.
 464         * frv-dis.c: Likewise.
 465         * frv-ibld.c: Likewise.
 466         * ip2k-dis.c: Likewise.
 467         * ip2k-ibld.c: Likewise.
 468         * iq2000-dis.c: Likewise.
 469         * iq2000-ibld.c: Likewise.
 470         * lm32-dis.c: Likewise.
 471         * lm32-ibld.c: Likewise.
 472         * m32c-dis.c: Likewise.
 473         * m32c-ibld.c: Likewise.
 474         * m32r-dis.c: Likewise.
 475         * m32r-ibld.c: Likewise.
 476         * mep-dis.c: Likewise.
 477         * mep-ibld.c: Likewise.
 478         * mt-dis.c: Likewise.
 479         * mt-ibld.c: Likewise.
 480         * or1k-dis.c: Likewise.
 481         * or1k-ibld.c: Likewise.
 482         * xc16x-dis.c: Likewise.
 483         * xc16x-ibld.c: Likewise.
 484         * xstormy16-dis.c: Likewise.
 485         * xstormy16-ibld.c: Likewise.
 486
 487 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 488
 489         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 490         (print_insn_): Handle instruction endian.
 491         * bpf-dis.c: Regenerate.
 492         * bpf-desc.c: Regenerate.
 493         * epiphany-dis.c: Likewise.
 494         * epiphany-desc.c: Likewise.
 495         * fr30-dis.c: Likewise.
 496         * fr30-desc.c: Likewise.
 497         * frv-dis.c: Likewise.
 498         * frv-desc.c: Likewise.
 499         * ip2k-dis.c: Likewise.
 500         * ip2k-desc.c: Likewise.
 501         * iq2000-dis.c: Likewise.
 502         * iq2000-desc.c: Likewise.
 503         * lm32-dis.c: Likewise.
 504         * lm32-desc.c: Likewise.
 505         * m32c-dis.c: Likewise.
 506         * m32c-desc.c: Likewise.
 507         * m32r-dis.c: Likewise.
 508         * m32r-desc.c: Likewise.
 509         * mep-dis.c: Likewise.
 510         * mep-desc.c: Likewise.
 511         * mt-dis.c: Likewise.
 512         * mt-desc.c: Likewise.
 513         * or1k-dis.c: Likewise.
 514         * or1k-desc.c: Likewise.
 515         * xc16x-dis.c: Likewise.
 516         * xc16x-desc.c: Likewise.
 517         * xstormy16-dis.c: Likewise.
 518         * xstormy16-desc.c: Likewise.
 519
 520 2020-06-03  Nick Clifton  <nickc@redhat.com>
 521
 522         * po/sr.po: Updated Serbian translation.
 523
 524 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 525
 526         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 527         (riscv_get_priv_spec_class): Likewise.
 528
 529 2020-06-01  Alan Modra  <amodra@gmail.com>
 530
 531         * bpf-desc.c: Regenerate.
 532
 533 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 534             David Faust <david.faust@oracle.com>
 535
 536         * bpf-desc.c: Regenerate.
 537         * bpf-opc.h: Likewise.
 538         * bpf-opc.c: Likewise.
 539         * bpf-dis.c: Likewise.
 540
 541 2020-05-28  Alan Modra  <amodra@gmail.com>
 542
 543         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 544         values.
 545
 546 2020-05-28  Alan Modra  <amodra@gmail.com>
 547
 548         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 549         immediates.
 550         (print_insn_ns32k): Revert last change.
 551
 552 2020-05-28  Nick Clifton  <nickc@redhat.com>
 553
 554         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 555         static.
 556
 557 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 558
 559         Fix extraction of signed constants in nios2 disassembler (again).
 560
 561         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 562         extractions of signed fields.
 563
 564 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 565
 566         * s390-opc.txt: Relocate vector load/store instructions with
 567         additional alignment parameter and change architecture level
 568         constraint from z14 to z13.
 569
 570 2020-05-21  Alan Modra  <amodra@gmail.com>
 571
 572         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 573         * sparc-dis.c: Likewise.
 574         * tic4x-dis.c: Likewise.
 575         * xtensa-dis.c: Likewise.
 576         * bpf-desc.c: Regenerate.
 577         * epiphany-desc.c: Regenerate.
 578         * fr30-desc.c: Regenerate.
 579         * frv-desc.c: Regenerate.
 580         * ip2k-desc.c: Regenerate.
 581         * iq2000-desc.c: Regenerate.
 582         * lm32-desc.c: Regenerate.
 583         * m32c-desc.c: Regenerate.
 584         * m32r-desc.c: Regenerate.
 585         * mep-asm.c: Regenerate.
 586         * mep-desc.c: Regenerate.
 587         * mt-desc.c: Regenerate.
 588         * or1k-desc.c: Regenerate.
 589         * xc16x-desc.c: Regenerate.
 590         * xstormy16-desc.c: Regenerate.
 591
 592 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 593
 594         * riscv-opc.c (riscv_ext_version_table): The table used to store
 595         all information about the supported spec and the corresponding ISA
 596         versions.  Currently, only Zicsr is supported to verify the
 597         correctness of Z sub extension settings.  Others will be supported
 598         in the future patches.
 599         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 600         classes and the corresponding strings.
 601         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 602         spec class by giving a ISA spec string.
 603         * riscv-opc.c (struct priv_spec_t): New structure.
 604         (struct priv_spec_t priv_specs): List for all supported privilege spec
 605         classes and the corresponding strings.
 606         (riscv_get_priv_spec_class): New function.  Get the corresponding
 607         privilege spec class by giving a spec string.
 608         (riscv_get_priv_spec_name): New function.  Get the corresponding
 609         privilege spec string by giving a CSR version class.
 610         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 611         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 612         according to the chosen version.  Build a hash table riscv_csr_hash to
 613         store the valid CSR for the chosen pirv verison.  Dump the direct
 614         CSR address rather than it's name if it is invalid.
 615         (parse_riscv_dis_option_without_args): New function.  Parse the options
 616         without arguments.
 617         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 618         parse the options without arguments first, and then handle the options
 619         with arguments.  Add the new option -Mpriv-spec, which has argument.
 620         * riscv-dis.c (print_riscv_disassembler_options): Add description
 621         about the new OBJDUMP option.
 622
 623 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 624
 625         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 626         WC values on POWER10 sync, dcbf  and wait instructions.
 627         (insert_pl, extract_pl): New functions.
 628         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 629         (LS3): New , 3-bit L for sync.
 630         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 631         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 632         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 633         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 634         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 635         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 636         <wait>: Enable PL operand on POWER10.
 637         <dcbf>: Enable L3OPT operand on POWER10.
 638         <sync>: Enable SC2 operand on POWER10.
 639
 640 2020-05-19  Stafford Horne  <shorne@gmail.com>
 641
 642         PR 25184
 643         * or1k-asm.c: Regenerate.
 644         * or1k-desc.c: Regenerate.
 645         * or1k-desc.h: Regenerate.
 646         * or1k-dis.c: Regenerate.
 647         * or1k-ibld.c: Regenerate.
 648         * or1k-opc.c: Regenerate.
 649         * or1k-opc.h: Regenerate.
 650         * or1k-opinst.c: Regenerate.
 651
 652 2020-05-11  Alan Modra  <amodra@gmail.com>
 653
 654         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 655         xsmaxcqp, xsmincqp.
 656
 657 2020-05-11  Alan Modra  <amodra@gmail.com>
 658
 659         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 660         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 661
 662 2020-05-11  Alan Modra  <amodra@gmail.com>
 663
 664         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 665
 666 2020-05-11  Alan Modra  <amodra@gmail.com>
 667
 668         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 669         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 670
 671 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 672
 673         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 674         mnemonics.
 675
 676 2020-05-11  Alan Modra  <amodra@gmail.com>
 677
 678         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 679         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 680         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 681         (prefix_opcodes): Add xxeval.
 682
 683 2020-05-11  Alan Modra  <amodra@gmail.com>
 684
 685         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 686         xxgenpcvwm, xxgenpcvdm.
 687
 688 2020-05-11  Alan Modra  <amodra@gmail.com>
 689
 690         * ppc-opc.c (MP, VXVAM_MASK): Define.
 691         (VXVAPS_MASK): Use VXVA_MASK.
 692         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 693         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 694         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 695         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 696
 697 2020-05-11  Alan Modra  <amodra@gmail.com>
 698             Peter Bergner  <bergner@linux.ibm.com>
 699
 700         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 701         New functions.
 702         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 703         YMSK2, XA6a, XA6ap, XB6a entries.
 704         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 705         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 706         (PPCVSX4): Define.
 707         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 708         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 709         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 710         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 711         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 712         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 713         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 714         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 715         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 716         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 717         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 718         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 719         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 720         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 721
 722 2020-05-11  Alan Modra  <amodra@gmail.com>
 723
 724         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 725         (insert_xts, extract_xts): New functions.
 726         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 727         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 728         (VXRC_MASK, VXSH_MASK): Define.
 729         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 730         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 731         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 732         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 733         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 734         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 735         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 736
 737 2020-05-11  Alan Modra  <amodra@gmail.com>
 738
 739         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 740         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 741         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 742         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 743         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 744
 745 2020-05-11  Alan Modra  <amodra@gmail.com>
 746
 747         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 748         (XTP, DQXP, DQXP_MASK): Define.
 749         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 750         (prefix_opcodes): Add plxvp and pstxvp.
 751
 752 2020-05-11  Alan Modra  <amodra@gmail.com>
 753
 754         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 755         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 756         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 757
 758 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 759
 760         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 761
 762 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 763
 764         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 765         (L1OPT): Define.
 766         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 767
 768 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 769
 770         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 771
 772 2020-05-11  Alan Modra  <amodra@gmail.com>
 773
 774         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 775
 776 2020-05-11  Alan Modra  <amodra@gmail.com>
 777
 778         * ppc-dis.c (ppc_opts): Add "power10" entry.
 779         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 780         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 781
 782 2020-05-11  Nick Clifton  <nickc@redhat.com>
 783
 784         * po/fr.po: Updated French translation.
 785
 786 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 787
 788         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 789         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 790         (operand_general_constraint_met_p): validate
 791         AARCH64_OPND_UNDEFINED.
 792         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 793         for FLD_imm16_2.
 794         * aarch64-asm-2.c: Regenerated.
 795         * aarch64-dis-2.c: Regenerated.
 796         * aarch64-opc-2.c: Regenerated.
 797
 798 2020-04-29  Nick Clifton  <nickc@redhat.com>
 799
 800         PR 22699
 801         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 802         and SETRC insns.
 803
 804 2020-04-29  Nick Clifton  <nickc@redhat.com>
 805
 806         * po/sv.po: Updated Swedish translation.
 807
 808 2020-04-29  Nick Clifton  <nickc@redhat.com>
 809
 810         PR 22699
 811         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 812         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 813         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 814         IMM0_8U case.
 815
 816 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 817
 818         PR 25848
 819         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 820         cmpi only on m68020up and cpu32.
 821
 822 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 823
 824         * aarch64-asm.c (aarch64_ins_none): New.
 825         * aarch64-asm.h (ins_none): New declaration.
 826         * aarch64-dis.c (aarch64_ext_none): New.
 827         * aarch64-dis.h (ext_none): New declaration.
 828         * aarch64-opc.c (aarch64_print_operand): Update case for
 829         AARCH64_OPND_BARRIER_PSB.
 830         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 831         (AARCH64_OPERANDS): Update inserter/extracter for
 832         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 833         * aarch64-asm-2.c: Regenerated.
 834         * aarch64-dis-2.c: Regenerated.
 835         * aarch64-opc-2.c: Regenerated.
 836
 837 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 838
 839         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 840         (aarch64_feature_ras, RAS): Likewise.
 841         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 842         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 843         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 844         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 845         * aarch64-asm-2.c: Regenerated.
 846         * aarch64-dis-2.c: Regenerated.
 847         * aarch64-opc-2.c: Regenerated.
 848
 849 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 850
 851         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 852         (print_insn_neon): Support disassembly of conditional
 853         instructions.
 854
 855 2020-02-16  David Faust  <david.faust@oracle.com>
 856
 857         * bpf-desc.c: Regenerate.
 858         * bpf-desc.h: Likewise.
 859         * bpf-opc.c: Regenerate.
 860         * bpf-opc.h: Likewise.
 861
 862 2020-04-07  Lili Cui  <lili.cui@intel.com>
 863
 864         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 865         (prefix_table): New instructions (see prefixes above).
 866         (rm_table): Likewise
 867         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 868         CPU_ANY_TSXLDTRK_FLAGS.
 869         (cpu_flags): Add CpuTSXLDTRK.
 870         * i386-opc.h (enum): Add CpuTSXLDTRK.
 871         (i386_cpu_flags): Add cputsxldtrk.
 872         * i386-opc.tbl: Add XSUSPLDTRK insns.
 873         * i386-init.h: Regenerate.
 874         * i386-tbl.h: Likewise.
 875
 876 2020-04-02  Lili Cui  <lili.cui@intel.com>
 877
 878         * i386-dis.c (prefix_table): New instructions serialize.
 879         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 880         CPU_ANY_SERIALIZE_FLAGS.
 881         (cpu_flags): Add CpuSERIALIZE.
 882         * i386-opc.h (enum): Add CpuSERIALIZE.
 883         (i386_cpu_flags): Add cpuserialize.
 884         * i386-opc.tbl: Add SERIALIZE insns.
 885         * i386-init.h: Regenerate.
 886         * i386-tbl.h: Likewise.
 887
 888 2020-03-26  Alan Modra  <amodra@gmail.com>
 889
 890         * disassemble.h (opcodes_assert): Declare.
 891         (OPCODES_ASSERT): Define.
 892         * disassemble.c: Don't include assert.h.  Include opintl.h.
 893         (opcodes_assert): New function.
 894         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 895         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 896         calculate maxlen.  Omit insn decoding when insn length exceeds
 897         maxlen.  Exit from nibble loop when looking for E, before
 898         accessing next data byte.  Move processing of E outside loop.
 899         Replace tests of maxlen in loop with assertions.
 900
 901 2020-03-26  Alan Modra  <amodra@gmail.com>
 902
 903         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 904
 905 2020-03-25  Alan Modra  <amodra@gmail.com>
 906
 907         * z80-dis.c (suffix): Init mybuf.
 908
 909 2020-03-22  Alan Modra  <amodra@gmail.com>
 910
 911         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 912         successflly read from section.
 913
 914 2020-03-22  Alan Modra  <amodra@gmail.com>
 915
 916         * arc-dis.c (find_format): Use ISO C string concatenation rather
 917         than line continuation within a string.  Don't access needs_limm
 918         before testing opcode != NULL.
 919
 920 2020-03-22  Alan Modra  <amodra@gmail.com>
 921
 922         * ns32k-dis.c (print_insn_arg): Update comment.
 923         (print_insn_ns32k): Reduce size of index_offset array, and
 924         initialize, passing -1 to print_insn_arg for args that are not
 925         an index.  Don't exit arg loop early.  Abort on bad arg number.
 926
 927 2020-03-22  Alan Modra  <amodra@gmail.com>
 928
 929         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 930         * s12z-opc.c: Formatting.
 931         (operands_f): Return an int.
 932         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 933         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 934         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 935         (exg_sex_discrim): Likewise.
 936         (create_immediate_operand, create_bitfield_operand),
 937         (create_register_operand_with_size, create_register_all_operand),
 938         (create_register_all16_operand, create_simple_memory_operand),
 939         (create_memory_operand, create_memory_auto_operand): Don't
 940         segfault on malloc failure.
 941         (z_ext24_decode): Return an int status, negative on fail, zero
 942         on success.
 943         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 944         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 945         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 946         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 947         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 948         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 949         (loop_primitive_decode, shift_decode, psh_pul_decode),
 950         (bit_field_decode): Similarly.
 951         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 952         to return value, update callers.
 953         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 954         Don't segfault on NULL operand.
 955         (decode_operation): Return OP_INVALID on first fail.
 956         (decode_s12z): Check all reads, returning -1 on fail.
 957
 958 2020-03-20  Alan Modra  <amodra@gmail.com>
 959
 960         * metag-dis.c (print_insn_metag): Don't ignore status from
 961         read_memory_func.
 962
 963 2020-03-20  Alan Modra  <amodra@gmail.com>
 964
 965         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 966         Initialize parts of buffer not written when handling a possible
 967         2-byte insn at end of section.  Don't attempt decoding of such
 968         an insn by the 4-byte machinery.
 969
 970 2020-03-20  Alan Modra  <amodra@gmail.com>
 971
 972         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 973         partially filled buffer.  Prevent lookup of 4-byte insns when
 974         only VLE 2-byte insns are possible due to section size.  Print
 975         ".word" rather than ".long" for 2-byte leftovers.
 976
 977 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 978
 979         PR 25641
 980         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 981
 982 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 983
 984         * i386-dis.c (X86_64_0D): Rename to ...
 985         (X86_64_0E): ... this.
 986
 987 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 988
 989         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 990         * Makefile.in: Regenerated.
 991
 992 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 993
 994         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 995         3-operand pseudos.
 996         * i386-tbl.h: Re-generate.
 997
 998 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 999
1000         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1001         vprot*, vpsha*, and vpshl*.
1002         * i386-tbl.h: Re-generate.
1003
1004 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1005
1006         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1007         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1008         * i386-tbl.h: Re-generate.
1009
1010 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1011
1012         * i386-gen.c (set_bitfield): Ignore zero-length field names.
1013         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1014         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1015         * i386-tbl.h: Re-generate.
1016
1017 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1018
1019         * i386-gen.c (struct template_arg, struct template_instance,
1020         struct template_param, struct template, templates,
1021         parse_template, expand_templates): New.
1022         (process_i386_opcodes): Various local variables moved to
1023         expand_templates. Call parse_template and expand_templates.
1024         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1025         * i386-tbl.h: Re-generate.
1026
1027 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1028
1029         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1030         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1031         register and memory source templates. Replace VexW= by VexW*
1032         where applicable.
1033         * i386-tbl.h: Re-generate.
1034
1035 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1036
1037         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1038         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1039         * i386-tbl.h: Re-generate.
1040
1041 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1042
1043         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1044         * i386-tbl.h: Re-generate.
1045
1046 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1047
1048         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1049         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1050         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1051         VexW0 on SSE2AVX variants.
1052         (vmovq): Drop NoRex64 from XMM/XMM variants.
1053         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1054         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1055         applicable use VexW0.
1056         * i386-tbl.h: Re-generate.
1057
1058 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1059
1060         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1061         * i386-opc.h (Rex64): Delete.
1062         (struct i386_opcode_modifier): Remove rex64 field.
1063         * i386-opc.tbl (crc32): Drop Rex64.
1064         Replace Rex64 with Size64 everywhere else.
1065         * i386-tbl.h: Re-generate.
1066
1067 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1068
1069         * i386-dis.c (OP_E_memory): Exclude recording of used address
1070         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1071         addressed memory operands for MPX insns.
1072
1073 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1074
1075         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1076         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1077         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1078         (ptwrite): Split into non-64-bit and 64-bit forms.
1079         * i386-tbl.h: Re-generate.
1080
1081 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1082
1083         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1084         template.
1085         * i386-tbl.h: Re-generate.
1086
1087 2020-03-04  Jan Beulich  <jbeulich@suse.com>
1088
1089         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1090         (prefix_table): Move vmmcall here. Add vmgexit.
1091         (rm_table): Replace vmmcall entry by prefix_table[] escape.
1092         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1093         (cpu_flags): Add CpuSEV_ES entry.
1094         * i386-opc.h (CpuSEV_ES): New.
1095         (union i386_cpu_flags): Add cpusev_es field.
1096         * i386-opc.tbl (vmgexit): New.
1097         * i386-init.h, i386-tbl.h: Re-generate.
1098
1099 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1100
1101         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1102         with MnemonicSize.
1103         * i386-opc.h (IGNORESIZE): New.
1104         (DEFAULTSIZE): Likewise.
1105         (IgnoreSize): Removed.
1106         (DefaultSize): Likewise.
1107         (MnemonicSize): New.
1108         (i386_opcode_modifier): Replace ignoresize/defaultsize with
1109         mnemonicsize.
1110         * i386-opc.tbl (IgnoreSize): New.
1111         (DefaultSize): Likewise.
1112         * i386-tbl.h: Regenerated.
1113
1114 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1115
1116         PR 25627
1117         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1118         instructions.
1119
1120 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1121
1122         PR gas/25622
1123         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1124         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1125         * i386-tbl.h: Regenerated.
1126
1127 2020-02-26  Alan Modra  <amodra@gmail.com>
1128
1129         * aarch64-asm.c: Indent labels correctly.
1130         * aarch64-dis.c: Likewise.
1131         * aarch64-gen.c: Likewise.
1132         * aarch64-opc.c: Likewise.
1133         * alpha-dis.c: Likewise.
1134         * i386-dis.c: Likewise.
1135         * nds32-asm.c: Likewise.
1136         * nfp-dis.c: Likewise.
1137         * visium-dis.c: Likewise.
1138
1139 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
1140
1141         * arc-regs.h (int_vector_base): Make it available for all ARC
1142         CPUs.
1143
1144 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
1145
1146         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1147         changed.
1148
1149 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
1150
1151         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1152         c.mv/c.li if rs1 is zero.
1153
1154 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
1155
1156         * i386-gen.c (cpu_flag_init): Replace CpuABM with
1157         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
1158         CPU_POPCNT_FLAGS.
1159         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
1160         * i386-opc.h (CpuABM): Removed.
1161         (CpuPOPCNT): New.
1162         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
1163         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1164         popcnt.  Remove CpuABM from lzcnt.
1165         * i386-init.h: Regenerated.
1166         * i386-tbl.h: Likewise.
1167
1168 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1169
1170         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1171         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1172         VexW1 instead of open-coding them.
1173         * i386-tbl.h: Re-generate.
1174
1175 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1176
1177         * i386-opc.tbl (AddrPrefixOpReg): Define.
1178         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1179         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1180         templates. Drop NoRex64.
1181         * i386-tbl.h: Re-generate.
1182
1183 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1184
1185         PR gas/6518
1186         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1187         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1188         into Intel syntax instance (with Unpsecified) and AT&T one
1189         (without).
1190         (vcvtneps2bf16): Likewise, along with folding the two so far
1191         separate ones.
1192         * i386-tbl.h: Re-generate.
1193
1194 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1195
1196         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1197         CPU_ANY_SSE4A_FLAGS.
1198
1199 2020-02-17  Alan Modra  <amodra@gmail.com>
1200
1201         * i386-gen.c (cpu_flag_init): Correct last change.
1202
1203 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1204
1205         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
1206         CPU_ANY_SSE4_FLAGS.
1207
1208 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
1209
1210         * i386-opc.tbl (movsx): Remove Intel syntax comments.
1211         (movzx): Likewise.
1212
1213 2020-02-14  Jan Beulich  <jbeulich@suse.com>
1214
1215         PR gas/25438
1216         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1217         destination for Cpu64-only variant.
1218         (movzx): Fold patterns.
1219         * i386-tbl.h: Re-generate.
1220
1221 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1222
1223         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1224         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1225         CPU_ANY_SSE4_FLAGS entry.
1226         * i386-init.h: Re-generate.
1227
1228 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1229
1230         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1231         with Unspecified, making the present one AT&T syntax only.
1232         * i386-tbl.h: Re-generate.
1233
1234 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1235
1236         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1237         * i386-tbl.h: Re-generate.
1238
1239 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1240
1241         PR gas/24546
1242         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1243         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1244         Amd64 and Intel64 templates.
1245         (call, jmp): Likewise for far indirect variants. Dro
1246         Unspecified.
1247         * i386-tbl.h: Re-generate.
1248
1249 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1250
1251         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1252         * i386-opc.h (ShortForm): Delete.
1253         (struct i386_opcode_modifier): Remove shortform field.
1254         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1255         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1256         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1257         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1258         Drop ShortForm.
1259         * i386-tbl.h: Re-generate.
1260
1261 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1262
1263         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1264         fucompi): Drop ShortForm from operand-less templates.
1265         * i386-tbl.h: Re-generate.
1266
1267 2020-02-11  Alan Modra  <amodra@gmail.com>
1268
1269         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1270         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1271         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1272         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1273         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1274
1275 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1276
1277         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1278         (cde_opcodes): Add VCX* instructions.
1279
1280 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1281             Matthew Malcomson  <matthew.malcomson@arm.com>
1282
1283         * arm-dis.c (struct cdeopcode32): New.
1284         (CDE_OPCODE): New macro.
1285         (cde_opcodes): New disassembly table.
1286         (regnames): New option to table.
1287         (cde_coprocs): New global variable.
1288         (print_insn_cde): New
1289         (print_insn_thumb32): Use print_insn_cde.
1290         (parse_arm_disassembler_options): Parse coprocN args.
1291
1292 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1293
1294         PR gas/25516
1295         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1296         with ISA64.
1297         * i386-opc.h (AMD64): Removed.
1298         (Intel64): Likewose.
1299         (AMD64): New.
1300         (INTEL64): Likewise.
1301         (INTEL64ONLY): Likewise.
1302         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1303         * i386-opc.tbl (Amd64): New.
1304         (Intel64): Likewise.
1305         (Intel64Only): Likewise.
1306         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1307         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1308         * i386-tbl.h: Regenerated.
1309
1310 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1311
1312         PR 25469
1313         * z80-dis.c: Add support for GBZ80 opcodes.
1314
1315 2020-02-04  Alan Modra  <amodra@gmail.com>
1316
1317         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1318
1319 2020-02-03  Alan Modra  <amodra@gmail.com>
1320
1321         * m32c-ibld.c: Regenerate.
1322
1323 2020-02-01  Alan Modra  <amodra@gmail.com>
1324
1325         * frv-ibld.c: Regenerate.
1326
1327 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1328
1329         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1330         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1331         (OP_E_memory): Replace xmm_mdq_mode case label by
1332         vex_scalar_w_dq_mode one.
1333         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1334
1335 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1336
1337         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1338         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1339         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1340         (intel_operand_size): Drop vex_w_dq_mode case label.
1341
1342 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1343
1344         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1345         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1346
1347 2020-01-30  Alan Modra  <amodra@gmail.com>
1348
1349         * m32c-ibld.c: Regenerate.
1350
1351 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1352
1353         * bpf-opc.c: Regenerate.
1354
1355 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1356
1357         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1358         (dis386): Use them to replace C2/C3 table entries.
1359         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1360         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1361         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1362         * i386-tbl.h: Re-generate.
1363
1364 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1365
1366         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1367         forms.
1368         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1369         DefaultSize.
1370         * i386-tbl.h: Re-generate.
1371
1372 2020-01-30  Alan Modra  <amodra@gmail.com>
1373
1374         * tic4x-dis.c (tic4x_dp): Make unsigned.
1375
1376 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1377             Jan Beulich  <jbeulich@suse.com>
1378
1379         PR binutils/25445
1380         * i386-dis.c (MOVSXD_Fixup): New function.
1381         (movsxd_mode): New enum.
1382         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1383         (intel_operand_size): Handle movsxd_mode.
1384         (OP_E_register): Likewise.
1385         (OP_G): Likewise.
1386         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1387         register on movsxd.  Add movsxd with 16-bit destination register
1388         for AMD64 and Intel64 ISAs.
1389         * i386-tbl.h: Regenerated.
1390
1391 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1392
1393         PR 25403
1394         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1395         * aarch64-asm-2.c: Regenerate
1396         * aarch64-dis-2.c: Likewise.
1397         * aarch64-opc-2.c: Likewise.
1398
1399 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1400
1401         * i386-opc.tbl (sysret): Drop DefaultSize.
1402         * i386-tbl.h: Re-generate.
1403
1404 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1405
1406         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1407         Dword.
1408         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1409         * i386-tbl.h: Re-generate.
1410
1411 2020-01-20  Nick Clifton  <nickc@redhat.com>
1412
1413         * po/de.po: Updated German translation.
1414         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1415         * po/uk.po: Updated Ukranian translation.
1416
1417 2020-01-20  Alan Modra  <amodra@gmail.com>
1418
1419         * hppa-dis.c (fput_const): Remove useless cast.
1420
1421 2020-01-20  Alan Modra  <amodra@gmail.com>
1422
1423         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1424
1425 2020-01-18  Nick Clifton  <nickc@redhat.com>
1426
1427         * configure: Regenerate.
1428         * po/opcodes.pot: Regenerate.
1429
1430 2020-01-18  Nick Clifton  <nickc@redhat.com>
1431
1432         Binutils 2.34 branch created.
1433
1434 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1435
1436         * opintl.h: Fix spelling error (seperate).
1437
1438 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1439
1440         * i386-opc.tbl: Add {vex} pseudo prefix.
1441         * i386-tbl.h: Regenerated.
1442
1443 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1444
1445         PR 25376
1446         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1447         (neon_opcodes): Likewise.
1448         (select_arm_features): Make sure we enable MVE bits when selecting
1449         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1450         any architecture.
1451
1452 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1453
1454         * i386-opc.tbl: Drop stale comment from XOP section.
1455
1456 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1457
1458         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1459         (extractps): Add VexWIG to SSE2AVX forms.
1460         * i386-tbl.h: Re-generate.
1461
1462 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1463
1464         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1465         Size64 from and use VexW1 on SSE2AVX forms.
1466         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1467         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1468         * i386-tbl.h: Re-generate.
1469
1470 2020-01-15  Alan Modra  <amodra@gmail.com>
1471
1472         * tic4x-dis.c (tic4x_version): Make unsigned long.
1473         (optab, optab_special, registernames): New file scope vars.
1474         (tic4x_print_register): Set up registernames rather than
1475         malloc'd registertable.
1476         (tic4x_disassemble): Delete optable and optable_special.  Use
1477         optab and optab_special instead.  Throw away old optab,
1478         optab_special and registernames when info->mach changes.
1479
1480 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1481
1482         PR 25377
1483         * z80-dis.c (suffix): Use .db instruction to generate double
1484         prefix.
1485
1486 2020-01-14  Alan Modra  <amodra@gmail.com>
1487
1488         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1489         values to unsigned before shifting.
1490
1491 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1492
1493         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1494         flow instructions.
1495         (print_insn_thumb16, print_insn_thumb32): Likewise.
1496         (print_insn): Initialize the insn info.
1497         * i386-dis.c (print_insn): Initialize the insn info fields, and
1498         detect jumps.
1499
1500 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1501
1502         * arc-opc.c (C_NE): Make it required.
1503
1504 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1505
1506         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1507         reserved register name.
1508
1509 2020-01-13  Alan Modra  <amodra@gmail.com>
1510
1511         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1512         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1513
1514 2020-01-13  Alan Modra  <amodra@gmail.com>
1515
1516         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1517         result of wasm_read_leb128 in a uint64_t and check that bits
1518         are not lost when copying to other locals.  Use uint32_t for
1519         most locals.  Use PRId64 when printing int64_t.
1520
1521 2020-01-13  Alan Modra  <amodra@gmail.com>
1522
1523         * score-dis.c: Formatting.
1524         * score7-dis.c: Formatting.
1525
1526 2020-01-13  Alan Modra  <amodra@gmail.com>
1527
1528         * score-dis.c (print_insn_score48): Use unsigned variables for
1529         unsigned values.  Don't left shift negative values.
1530         (print_insn_score32): Likewise.
1531         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1532
1533 2020-01-13  Alan Modra  <amodra@gmail.com>
1534
1535         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1536
1537 2020-01-13  Alan Modra  <amodra@gmail.com>
1538
1539         * fr30-ibld.c: Regenerate.
1540
1541 2020-01-13  Alan Modra  <amodra@gmail.com>
1542
1543         * xgate-dis.c (print_insn): Don't left shift signed value.
1544         (ripBits): Formatting, use 1u.
1545
1546 2020-01-10  Alan Modra  <amodra@gmail.com>
1547
1548         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1549         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1550
1551 2020-01-10  Alan Modra  <amodra@gmail.com>
1552
1553         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1554         and XRREG value earlier to avoid a shift with negative exponent.
1555         * m10200-dis.c (disassemble): Similarly.
1556
1557 2020-01-09  Nick Clifton  <nickc@redhat.com>
1558
1559         PR 25224
1560         * z80-dis.c (ld_ii_ii): Use correct cast.
1561
1562 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1563
1564         PR 25224
1565         * z80-dis.c (ld_ii_ii): Use character constant when checking
1566         opcode byte value.
1567
1568 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1569
1570         * i386-dis.c (SEP_Fixup): New.
1571         (SEP): Define.
1572         (dis386_twobyte): Use it for sysenter/sysexit.
1573         (enum x86_64_isa): Change amd64 enumerator to value 1.
1574         (OP_J): Compare isa64 against intel64 instead of amd64.
1575         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1576         forms.
1577         * i386-tbl.h: Re-generate.
1578
1579 2020-01-08  Alan Modra  <amodra@gmail.com>
1580
1581         * z8k-dis.c: Include libiberty.h
1582         (instr_data_s): Make max_fetched unsigned.
1583         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1584         Don't exceed byte_info bounds.
1585         (output_instr): Make num_bytes unsigned.
1586         (unpack_instr): Likewise for nibl_count and loop.
1587         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1588         idx unsigned.
1589         * z8k-opc.h: Regenerate.
1590
1591 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1592
1593         * arc-tbl.h (llock): Use 'LLOCK' as class.
1594         (llockd): Likewise.
1595         (scond): Use 'SCOND' as class.
1596         (scondd): Likewise.
1597         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1598         (scondd): Likewise.
1599
1600 2020-01-06  Alan Modra  <amodra@gmail.com>
1601
1602         * m32c-ibld.c: Regenerate.
1603
1604 2020-01-06  Alan Modra  <amodra@gmail.com>
1605
1606         PR 25344
1607         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1608         Peek at next byte to prevent recursion on repeated prefix bytes.
1609         Ensure uninitialised "mybuf" is not accessed.
1610         (print_insn_z80): Don't zero n_fetch and n_used here,..
1611         (print_insn_z80_buf): ..do it here instead.
1612
1613 2020-01-04  Alan Modra  <amodra@gmail.com>
1614
1615         * m32r-ibld.c: Regenerate.
1616
1617 2020-01-04  Alan Modra  <amodra@gmail.com>
1618
1619         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1620
1621 2020-01-04  Alan Modra  <amodra@gmail.com>
1622
1623         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1624
1625 2020-01-04  Alan Modra  <amodra@gmail.com>
1626
1627         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1628
1629 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1630
1631         * aarch64-tbl.h (aarch64_opcode_table): Use
1632         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1633
1634 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1635
1636         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1637         forms of SUDOT and USDOT.
1638
1639 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1640
1641         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1642         uzip{1,2}.
1643         * opcodes/aarch64-dis-2.c: Re-generate.
1644
1645 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1646
1647         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1648         FMMLA encoding.
1649         * opcodes/aarch64-dis-2.c: Re-generate.
1650
1651 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1652
1653         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1654
1655 2020-01-01  Alan Modra  <amodra@gmail.com>
1656
1657         Update year range in copyright notice of all files.
1658
1659 For older changes see ChangeLog-2019
1660 \f
1661 Copyright (C) 2020 Free Software Foundation, Inc.
1662
1663 Copying and distribution of this file, with or without modification,
1664 are permitted in any medium without royalty provided the copyright
1665 notice and this notice are preserved.
1666
1667 Local Variables:
1668 mode: change-log
1669 left-margin: 8
1670 fill-column: 74
1671 version-control: never
1672 End: