opcodes/ChangeLog

   1 2020-07-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
   4         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
   5         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
   6         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
   7         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
   8         PREFIX_EVEX_0F382B): Delete.
   9         (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
  10         EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
  11         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
  12         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
  13         EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
  14         to ...
  15         (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
  16         EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
  17         EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
  18         EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
  19         respectively.
  20         * i386-dis-evex.h (evex_table): Reference VEX_W table entries
  21         for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
  22         0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
  23         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
  24         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
  25         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
  26         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
  27         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
  28         PREFIX_EVEX_0F382B): Remove table entries.
  29         * i386-dis-evex-w.h: Reference VEX table entries for opcodes
  30         0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
  31         0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
  32
  33 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
  36         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
  37         enumerators.
  38         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
  39         EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
  40         EVEX_LEN_0F3A01_P_2_W_1 table entries.
  41         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
  42         entries.
  43
  44 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  45
  46         * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
  47         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
  48         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
  49         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
  50         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
  51         EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
  52         EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
  53         EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
  54         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
  55         entries.
  56
  57 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  58
  59         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
  60         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
  61         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
  62         respectively.
  63         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
  64         entries.
  65         * i386-dis-evex.h (evex_table): Reference VEX table entry for
  66         opcode 0F3A1D.
  67         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
  68         entry.
  69         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
  70
  71 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  72
  73         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
  74         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
  75         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
  76         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
  77         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
  78         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
  79         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
  80         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
  81         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
  82         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
  83         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
  84         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
  85         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
  86         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
  87         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
  88         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
  89         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
  90         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
  91         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
  92         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
  93         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
  94         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
  95         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
  96         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
  97         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
  98         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
  99         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
 100         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
 101         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
 102         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
 103         (prefix_table): Add EXxEVexR to FMA table entries.
 104         (OP_Rounding): Move abort() invocation.
 105         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
 106         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
 107         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
 108         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
 109         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
 110         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
 111         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
 112         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
 113         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
 114         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
 115         0F3ACE, 0F3ACF.
 116         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
 117         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 118         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
 119         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
 120         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 121         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
 122         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
 123         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
 124         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 125         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
 126         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
 127         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
 128         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
 129         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
 130         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
 131         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
 132         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
 133         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
 134         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
 135         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
 136         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
 137         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
 138         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
 139         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
 140         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
 141         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
 142         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
 143         Delete table entries.
 144         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
 145         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
 146         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
 147         Likewise.
 148
 149 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 150
 151         * i386-dis.c (EXqScalarS): Delete.
 152         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
 153         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
 154
 155 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 156
 157         * i386-dis.c (safe-ctype.h): Include.
 158         (EXdScalar, EXqScalar): Delete.
 159         (d_scalar_mode, q_scalar_mode): Delete.
 160         (prefix_table, vex_len_table): Use EXxmm_md in place of
 161         EXdScalar and EXxmm_mq in place of EXqScalar.
 162         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
 163         d_scalar_mode and q_scalar_mode.
 164         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
 165         (vmovsd): Use EXxmm_mq.
 166
 167 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
 168
 169         PR 26204
 170         * arc-dis.c: Fix spelling mistake.
 171         * po/opcodes.pot: Regenerate.
 172
 173 2020-07-06  Nick Clifton  <nickc@redhat.com>
 174
 175         * po/pt_BR.po: Updated Brazilian Portugugese translation.
 176         * po/uk.po: Updated Ukranian translation.
 177
 178 2020-07-04  Nick Clifton  <nickc@redhat.com>
 179
 180         * configure: Regenerate.
 181         * po/opcodes.pot: Regenerate.
 182
 183 2020-07-04  Nick Clifton  <nickc@redhat.com>
 184
 185         Binutils 2.35 branch created.
 186
 187 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
 188
 189         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
 190         * i386-opc.h (VexSwapSources): New.
 191         (i386_opcode_modifier): Add vexswapsources.
 192         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
 193         with two source operands swapped.
 194         * i386-tbl.h: Regenerated.
 195
 196 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
 197
 198         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
 199         unprivileged CSR can also be initialized.
 200
 201 2020-06-29  Alan Modra  <amodra@gmail.com>
 202
 203         * arm-dis.c: Use C style comments.
 204         * cr16-opc.c: Likewise.
 205         * ft32-dis.c: Likewise.
 206         * moxie-opc.c: Likewise.
 207         * tic54x-dis.c: Likewise.
 208         * s12z-opc.c: Remove useless comment.
 209         * xgate-dis.c: Likewise.
 210
 211 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 212
 213         * i386-opc.tbl: Add a blank line.
 214
 215 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 216
 217         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
 218         (VecSIB128): Renamed to ...
 219         (VECSIB128): This.
 220         (VecSIB256): Renamed to ...
 221         (VECSIB256): This.
 222         (VecSIB512): Renamed to ...
 223         (VECSIB512): This.
 224         (VecSIB): Renamed to ...
 225         (SIB): This.
 226         (i386_opcode_modifier): Replace vecsib with sib.
 227         * i386-opc.tbl (VecSIB128): New.
 228         (VecSIB256): Likewise.
 229         (VecSIB512): Likewise.
 230         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
 231         and VecSIB512, respectively.
 232
 233 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 234
 235         * i386-dis.c: Adjust description of I macro.
 236         (x86_64_table): Drop use of I.
 237         (float_mem): Replace use of I.
 238         (putop): Remove handling of I. Adjust setting/clearing of "alt".
 239
 240 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 241
 242         * i386-dis.c: (print_insn): Avoid straight assignment to
 243         priv.orig_sizeflag when processing -M sub-options.
 244
 245 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 246
 247         * i386-dis.c: Adjust description of J macro.
 248         (dis386, x86_64_table, mod_table): Replace J.
 249         (putop): Remove handling of J.
 250
 251 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
 254
 255 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 256
 257         * i386-dis.c: Adjust description of "LQ" macro.
 258         (dis386_twobyte): Use LQ for sysret.
 259         (putop): Adjust handling of LQ.
 260
 261 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
 262
 263         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
 264         * riscv-dis.c: Include elfxx-riscv.h.
 265
 266 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
 267
 268         * i386-dis.c (prefix_table): Revert the last vmgexit change.
 269
 270 2020-06-17  Lili Cui  <lili.cui@intel.com>
 271
 272         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
 273
 274 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
 275
 276         PR gas/26115
 277         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
 278         * i386-opc.tbl: Likewise.
 279         * i386-tbl.h: Regenerated.
 280
 281 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
 282
 283         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
 284
 285 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
 286
 287         * aarch64-opc.c (SYSREG): New macro for describing system registers.
 288         (SR_CORE): Likewise.
 289         (SR_FEAT): Likewise.
 290         (SR_RNG): Likewise.
 291         (SR_V8_1): Likewise.
 292         (SR_V8_2): Likewise.
 293         (SR_V8_3): Likewise.
 294         (SR_V8_4): Likewise.
 295         (SR_PAN): Likewise.
 296         (SR_RAS): Likewise.
 297         (SR_SSBS): Likewise.
 298         (SR_SVE): Likewise.
 299         (SR_ID_PFR2): Likewise.
 300         (SR_PROFILE): Likewise.
 301         (SR_MEMTAG): Likewise.
 302         (SR_SCXTNUM): Likewise.
 303         (aarch64_sys_regs): Refactor to store feature information in the table.
 304         (aarch64_sys_reg_supported_p): Collapse logic for system registers
 305         that now describe their own features.
 306         (aarch64_pstatefield_supported_p): Likewise.
 307
 308 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 309
 310         * i386-dis.c (prefix_table): Fix a typo in comments.
 311
 312 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 313
 314         * i386-dis.c (rex_ignored): Delete.
 315         (ckprefix): Drop rex_ignored initialization.
 316         (get_valid_dis386): Drop setting of rex_ignored.
 317         (print_insn): Drop checking of rex_ignored. Don't record data
 318         size prefix as used with VEX-and-alike encodings.
 319
 320 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 321
 322         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 323         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 324         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 325         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 326         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 327         VEX_0F12, and VEX_0F16.
 328         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 329         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 330         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 331         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 332         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 333         MOD_VEX_0F16_PREFIX_2 entries.
 334
 335 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 336
 337         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 338         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 339         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 340         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 341         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 342         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 343         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 344         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 345         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 346         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 347         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 348         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 349         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 350         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 351         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 352         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 353         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 354         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 355         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 356         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 357         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 358         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 359         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 360         EVEX_W_0FC6_P_2): Delete.
 361         (print_insn): Add EVEX.W vs embedded prefix consistency check
 362         to prefix validation.
 363         * i386-dis-evex.h (evex_table): Don't further descend for
 364         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 365         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 366         and 0F2B.
 367         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 368         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 369         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 370         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 371         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 372         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 373         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 374         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 375         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 376         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 377         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 378         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 379         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 380         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 381         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 382         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 383         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 384         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 385         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 386         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 387         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 388         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 389         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 390         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 391         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 392         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 393         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 394
 395 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 396
 397         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 398         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 399         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 400         vmovmskpX.
 401         (print_insn): Drop pointless check against bad_opcode. Split
 402         prefix validation into legacy and VEX-and-alike parts.
 403         (putop): Re-work 'X' macro handling.
 404
 405 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 406
 407         * i386-dis.c (MOD_0F51): Rename to ...
 408         (MOD_0F50): ... this.
 409
 410 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 411
 412         * arm-dis.c (arm_opcodes): Add dfb.
 413         (thumb32_opcodes): Add dfb.
 414
 415 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 416
 417         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 418
 419 2020-06-06  Alan Modra  <amodra@gmail.com>
 420
 421         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 422
 423 2020-06-05  Alan Modra  <amodra@gmail.com>
 424
 425         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 426         size is large enough.
 427
 428 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 429
 430         * disassemble.c (disassemble_init_for_target): Set endian_code for
 431         bpf targets.
 432         * bpf-desc.c: Regenerate.
 433         * bpf-opc.c: Likewise.
 434         * bpf-dis.c: Likewise.
 435
 436 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 437
 438         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 439         (cgen_put_insn_value): Likewise.
 440         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 441         * cgen-dis.in (print_insn): Likewise.
 442         * cgen-ibld.in (insert_1): Likewise.
 443         (insert_1): Likewise.
 444         (insert_insn_normal): Likewise.
 445         (extract_1): Likewise.
 446         * bpf-dis.c: Regenerate.
 447         * bpf-ibld.c: Likewise.
 448         * bpf-ibld.c: Likewise.
 449         * cgen-dis.in: Likewise.
 450         * cgen-ibld.in: Likewise.
 451         * cgen-opc.c: Likewise.
 452         * epiphany-dis.c: Likewise.
 453         * epiphany-ibld.c: Likewise.
 454         * fr30-dis.c: Likewise.
 455         * fr30-ibld.c: Likewise.
 456         * frv-dis.c: Likewise.
 457         * frv-ibld.c: Likewise.
 458         * ip2k-dis.c: Likewise.
 459         * ip2k-ibld.c: Likewise.
 460         * iq2000-dis.c: Likewise.
 461         * iq2000-ibld.c: Likewise.
 462         * lm32-dis.c: Likewise.
 463         * lm32-ibld.c: Likewise.
 464         * m32c-dis.c: Likewise.
 465         * m32c-ibld.c: Likewise.
 466         * m32r-dis.c: Likewise.
 467         * m32r-ibld.c: Likewise.
 468         * mep-dis.c: Likewise.
 469         * mep-ibld.c: Likewise.
 470         * mt-dis.c: Likewise.
 471         * mt-ibld.c: Likewise.
 472         * or1k-dis.c: Likewise.
 473         * or1k-ibld.c: Likewise.
 474         * xc16x-dis.c: Likewise.
 475         * xc16x-ibld.c: Likewise.
 476         * xstormy16-dis.c: Likewise.
 477         * xstormy16-ibld.c: Likewise.
 478
 479 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 480
 481         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 482         (print_insn_): Handle instruction endian.
 483         * bpf-dis.c: Regenerate.
 484         * bpf-desc.c: Regenerate.
 485         * epiphany-dis.c: Likewise.
 486         * epiphany-desc.c: Likewise.
 487         * fr30-dis.c: Likewise.
 488         * fr30-desc.c: Likewise.
 489         * frv-dis.c: Likewise.
 490         * frv-desc.c: Likewise.
 491         * ip2k-dis.c: Likewise.
 492         * ip2k-desc.c: Likewise.
 493         * iq2000-dis.c: Likewise.
 494         * iq2000-desc.c: Likewise.
 495         * lm32-dis.c: Likewise.
 496         * lm32-desc.c: Likewise.
 497         * m32c-dis.c: Likewise.
 498         * m32c-desc.c: Likewise.
 499         * m32r-dis.c: Likewise.
 500         * m32r-desc.c: Likewise.
 501         * mep-dis.c: Likewise.
 502         * mep-desc.c: Likewise.
 503         * mt-dis.c: Likewise.
 504         * mt-desc.c: Likewise.
 505         * or1k-dis.c: Likewise.
 506         * or1k-desc.c: Likewise.
 507         * xc16x-dis.c: Likewise.
 508         * xc16x-desc.c: Likewise.
 509         * xstormy16-dis.c: Likewise.
 510         * xstormy16-desc.c: Likewise.
 511
 512 2020-06-03  Nick Clifton  <nickc@redhat.com>
 513
 514         * po/sr.po: Updated Serbian translation.
 515
 516 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 517
 518         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 519         (riscv_get_priv_spec_class): Likewise.
 520
 521 2020-06-01  Alan Modra  <amodra@gmail.com>
 522
 523         * bpf-desc.c: Regenerate.
 524
 525 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 526             David Faust <david.faust@oracle.com>
 527
 528         * bpf-desc.c: Regenerate.
 529         * bpf-opc.h: Likewise.
 530         * bpf-opc.c: Likewise.
 531         * bpf-dis.c: Likewise.
 532
 533 2020-05-28  Alan Modra  <amodra@gmail.com>
 534
 535         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 536         values.
 537
 538 2020-05-28  Alan Modra  <amodra@gmail.com>
 539
 540         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 541         immediates.
 542         (print_insn_ns32k): Revert last change.
 543
 544 2020-05-28  Nick Clifton  <nickc@redhat.com>
 545
 546         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 547         static.
 548
 549 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 550
 551         Fix extraction of signed constants in nios2 disassembler (again).
 552
 553         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 554         extractions of signed fields.
 555
 556 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 557
 558         * s390-opc.txt: Relocate vector load/store instructions with
 559         additional alignment parameter and change architecture level
 560         constraint from z14 to z13.
 561
 562 2020-05-21  Alan Modra  <amodra@gmail.com>
 563
 564         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 565         * sparc-dis.c: Likewise.
 566         * tic4x-dis.c: Likewise.
 567         * xtensa-dis.c: Likewise.
 568         * bpf-desc.c: Regenerate.
 569         * epiphany-desc.c: Regenerate.
 570         * fr30-desc.c: Regenerate.
 571         * frv-desc.c: Regenerate.
 572         * ip2k-desc.c: Regenerate.
 573         * iq2000-desc.c: Regenerate.
 574         * lm32-desc.c: Regenerate.
 575         * m32c-desc.c: Regenerate.
 576         * m32r-desc.c: Regenerate.
 577         * mep-asm.c: Regenerate.
 578         * mep-desc.c: Regenerate.
 579         * mt-desc.c: Regenerate.
 580         * or1k-desc.c: Regenerate.
 581         * xc16x-desc.c: Regenerate.
 582         * xstormy16-desc.c: Regenerate.
 583
 584 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 585
 586         * riscv-opc.c (riscv_ext_version_table): The table used to store
 587         all information about the supported spec and the corresponding ISA
 588         versions.  Currently, only Zicsr is supported to verify the
 589         correctness of Z sub extension settings.  Others will be supported
 590         in the future patches.
 591         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 592         classes and the corresponding strings.
 593         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 594         spec class by giving a ISA spec string.
 595         * riscv-opc.c (struct priv_spec_t): New structure.
 596         (struct priv_spec_t priv_specs): List for all supported privilege spec
 597         classes and the corresponding strings.
 598         (riscv_get_priv_spec_class): New function.  Get the corresponding
 599         privilege spec class by giving a spec string.
 600         (riscv_get_priv_spec_name): New function.  Get the corresponding
 601         privilege spec string by giving a CSR version class.
 602         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 603         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 604         according to the chosen version.  Build a hash table riscv_csr_hash to
 605         store the valid CSR for the chosen pirv verison.  Dump the direct
 606         CSR address rather than it's name if it is invalid.
 607         (parse_riscv_dis_option_without_args): New function.  Parse the options
 608         without arguments.
 609         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 610         parse the options without arguments first, and then handle the options
 611         with arguments.  Add the new option -Mpriv-spec, which has argument.
 612         * riscv-dis.c (print_riscv_disassembler_options): Add description
 613         about the new OBJDUMP option.
 614
 615 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 616
 617         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 618         WC values on POWER10 sync, dcbf  and wait instructions.
 619         (insert_pl, extract_pl): New functions.
 620         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 621         (LS3): New , 3-bit L for sync.
 622         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 623         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 624         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 625         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 626         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 627         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 628         <wait>: Enable PL operand on POWER10.
 629         <dcbf>: Enable L3OPT operand on POWER10.
 630         <sync>: Enable SC2 operand on POWER10.
 631
 632 2020-05-19  Stafford Horne  <shorne@gmail.com>
 633
 634         PR 25184
 635         * or1k-asm.c: Regenerate.
 636         * or1k-desc.c: Regenerate.
 637         * or1k-desc.h: Regenerate.
 638         * or1k-dis.c: Regenerate.
 639         * or1k-ibld.c: Regenerate.
 640         * or1k-opc.c: Regenerate.
 641         * or1k-opc.h: Regenerate.
 642         * or1k-opinst.c: Regenerate.
 643
 644 2020-05-11  Alan Modra  <amodra@gmail.com>
 645
 646         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 647         xsmaxcqp, xsmincqp.
 648
 649 2020-05-11  Alan Modra  <amodra@gmail.com>
 650
 651         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 652         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 653
 654 2020-05-11  Alan Modra  <amodra@gmail.com>
 655
 656         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 657
 658 2020-05-11  Alan Modra  <amodra@gmail.com>
 659
 660         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 661         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 662
 663 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 664
 665         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 666         mnemonics.
 667
 668 2020-05-11  Alan Modra  <amodra@gmail.com>
 669
 670         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 671         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 672         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 673         (prefix_opcodes): Add xxeval.
 674
 675 2020-05-11  Alan Modra  <amodra@gmail.com>
 676
 677         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 678         xxgenpcvwm, xxgenpcvdm.
 679
 680 2020-05-11  Alan Modra  <amodra@gmail.com>
 681
 682         * ppc-opc.c (MP, VXVAM_MASK): Define.
 683         (VXVAPS_MASK): Use VXVA_MASK.
 684         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 685         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 686         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 687         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 688
 689 2020-05-11  Alan Modra  <amodra@gmail.com>
 690             Peter Bergner  <bergner@linux.ibm.com>
 691
 692         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 693         New functions.
 694         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 695         YMSK2, XA6a, XA6ap, XB6a entries.
 696         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 697         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 698         (PPCVSX4): Define.
 699         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 700         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 701         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 702         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 703         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 704         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 705         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 706         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 707         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 708         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 709         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 710         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 711         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 712         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 713
 714 2020-05-11  Alan Modra  <amodra@gmail.com>
 715
 716         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 717         (insert_xts, extract_xts): New functions.
 718         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 719         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 720         (VXRC_MASK, VXSH_MASK): Define.
 721         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 722         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 723         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 724         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 725         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 726         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 727         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 728
 729 2020-05-11  Alan Modra  <amodra@gmail.com>
 730
 731         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 732         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 733         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 734         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 735         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 736
 737 2020-05-11  Alan Modra  <amodra@gmail.com>
 738
 739         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 740         (XTP, DQXP, DQXP_MASK): Define.
 741         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 742         (prefix_opcodes): Add plxvp and pstxvp.
 743
 744 2020-05-11  Alan Modra  <amodra@gmail.com>
 745
 746         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 747         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 748         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 749
 750 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 751
 752         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 753
 754 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 755
 756         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 757         (L1OPT): Define.
 758         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 759
 760 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 761
 762         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 763
 764 2020-05-11  Alan Modra  <amodra@gmail.com>
 765
 766         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 767
 768 2020-05-11  Alan Modra  <amodra@gmail.com>
 769
 770         * ppc-dis.c (ppc_opts): Add "power10" entry.
 771         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 772         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 773
 774 2020-05-11  Nick Clifton  <nickc@redhat.com>
 775
 776         * po/fr.po: Updated French translation.
 777
 778 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 779
 780         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 781         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 782         (operand_general_constraint_met_p): validate
 783         AARCH64_OPND_UNDEFINED.
 784         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 785         for FLD_imm16_2.
 786         * aarch64-asm-2.c: Regenerated.
 787         * aarch64-dis-2.c: Regenerated.
 788         * aarch64-opc-2.c: Regenerated.
 789
 790 2020-04-29  Nick Clifton  <nickc@redhat.com>
 791
 792         PR 22699
 793         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 794         and SETRC insns.
 795
 796 2020-04-29  Nick Clifton  <nickc@redhat.com>
 797
 798         * po/sv.po: Updated Swedish translation.
 799
 800 2020-04-29  Nick Clifton  <nickc@redhat.com>
 801
 802         PR 22699
 803         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 804         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 805         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 806         IMM0_8U case.
 807
 808 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 809
 810         PR 25848
 811         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 812         cmpi only on m68020up and cpu32.
 813
 814 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 815
 816         * aarch64-asm.c (aarch64_ins_none): New.
 817         * aarch64-asm.h (ins_none): New declaration.
 818         * aarch64-dis.c (aarch64_ext_none): New.
 819         * aarch64-dis.h (ext_none): New declaration.
 820         * aarch64-opc.c (aarch64_print_operand): Update case for
 821         AARCH64_OPND_BARRIER_PSB.
 822         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 823         (AARCH64_OPERANDS): Update inserter/extracter for
 824         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 825         * aarch64-asm-2.c: Regenerated.
 826         * aarch64-dis-2.c: Regenerated.
 827         * aarch64-opc-2.c: Regenerated.
 828
 829 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 830
 831         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 832         (aarch64_feature_ras, RAS): Likewise.
 833         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 834         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 835         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 836         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 837         * aarch64-asm-2.c: Regenerated.
 838         * aarch64-dis-2.c: Regenerated.
 839         * aarch64-opc-2.c: Regenerated.
 840
 841 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 842
 843         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 844         (print_insn_neon): Support disassembly of conditional
 845         instructions.
 846
 847 2020-02-16  David Faust  <david.faust@oracle.com>
 848
 849         * bpf-desc.c: Regenerate.
 850         * bpf-desc.h: Likewise.
 851         * bpf-opc.c: Regenerate.
 852         * bpf-opc.h: Likewise.
 853
 854 2020-04-07  Lili Cui  <lili.cui@intel.com>
 855
 856         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 857         (prefix_table): New instructions (see prefixes above).
 858         (rm_table): Likewise
 859         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 860         CPU_ANY_TSXLDTRK_FLAGS.
 861         (cpu_flags): Add CpuTSXLDTRK.
 862         * i386-opc.h (enum): Add CpuTSXLDTRK.
 863         (i386_cpu_flags): Add cputsxldtrk.
 864         * i386-opc.tbl: Add XSUSPLDTRK insns.
 865         * i386-init.h: Regenerate.
 866         * i386-tbl.h: Likewise.
 867
 868 2020-04-02  Lili Cui  <lili.cui@intel.com>
 869
 870         * i386-dis.c (prefix_table): New instructions serialize.
 871         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 872         CPU_ANY_SERIALIZE_FLAGS.
 873         (cpu_flags): Add CpuSERIALIZE.
 874         * i386-opc.h (enum): Add CpuSERIALIZE.
 875         (i386_cpu_flags): Add cpuserialize.
 876         * i386-opc.tbl: Add SERIALIZE insns.
 877         * i386-init.h: Regenerate.
 878         * i386-tbl.h: Likewise.
 879
 880 2020-03-26  Alan Modra  <amodra@gmail.com>
 881
 882         * disassemble.h (opcodes_assert): Declare.
 883         (OPCODES_ASSERT): Define.
 884         * disassemble.c: Don't include assert.h.  Include opintl.h.
 885         (opcodes_assert): New function.
 886         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 887         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 888         calculate maxlen.  Omit insn decoding when insn length exceeds
 889         maxlen.  Exit from nibble loop when looking for E, before
 890         accessing next data byte.  Move processing of E outside loop.
 891         Replace tests of maxlen in loop with assertions.
 892
 893 2020-03-26  Alan Modra  <amodra@gmail.com>
 894
 895         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 896
 897 2020-03-25  Alan Modra  <amodra@gmail.com>
 898
 899         * z80-dis.c (suffix): Init mybuf.
 900
 901 2020-03-22  Alan Modra  <amodra@gmail.com>
 902
 903         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 904         successflly read from section.
 905
 906 2020-03-22  Alan Modra  <amodra@gmail.com>
 907
 908         * arc-dis.c (find_format): Use ISO C string concatenation rather
 909         than line continuation within a string.  Don't access needs_limm
 910         before testing opcode != NULL.
 911
 912 2020-03-22  Alan Modra  <amodra@gmail.com>
 913
 914         * ns32k-dis.c (print_insn_arg): Update comment.
 915         (print_insn_ns32k): Reduce size of index_offset array, and
 916         initialize, passing -1 to print_insn_arg for args that are not
 917         an index.  Don't exit arg loop early.  Abort on bad arg number.
 918
 919 2020-03-22  Alan Modra  <amodra@gmail.com>
 920
 921         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 922         * s12z-opc.c: Formatting.
 923         (operands_f): Return an int.
 924         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 925         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 926         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 927         (exg_sex_discrim): Likewise.
 928         (create_immediate_operand, create_bitfield_operand),
 929         (create_register_operand_with_size, create_register_all_operand),
 930         (create_register_all16_operand, create_simple_memory_operand),
 931         (create_memory_operand, create_memory_auto_operand): Don't
 932         segfault on malloc failure.
 933         (z_ext24_decode): Return an int status, negative on fail, zero
 934         on success.
 935         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 936         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 937         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 938         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 939         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 940         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 941         (loop_primitive_decode, shift_decode, psh_pul_decode),
 942         (bit_field_decode): Similarly.
 943         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 944         to return value, update callers.
 945         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 946         Don't segfault on NULL operand.
 947         (decode_operation): Return OP_INVALID on first fail.
 948         (decode_s12z): Check all reads, returning -1 on fail.
 949
 950 2020-03-20  Alan Modra  <amodra@gmail.com>
 951
 952         * metag-dis.c (print_insn_metag): Don't ignore status from
 953         read_memory_func.
 954
 955 2020-03-20  Alan Modra  <amodra@gmail.com>
 956
 957         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 958         Initialize parts of buffer not written when handling a possible
 959         2-byte insn at end of section.  Don't attempt decoding of such
 960         an insn by the 4-byte machinery.
 961
 962 2020-03-20  Alan Modra  <amodra@gmail.com>
 963
 964         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 965         partially filled buffer.  Prevent lookup of 4-byte insns when
 966         only VLE 2-byte insns are possible due to section size.  Print
 967         ".word" rather than ".long" for 2-byte leftovers.
 968
 969 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 970
 971         PR 25641
 972         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 973
 974 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 975
 976         * i386-dis.c (X86_64_0D): Rename to ...
 977         (X86_64_0E): ... this.
 978
 979 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 980
 981         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 982         * Makefile.in: Regenerated.
 983
 984 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 985
 986         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 987         3-operand pseudos.
 988         * i386-tbl.h: Re-generate.
 989
 990 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 991
 992         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 993         vprot*, vpsha*, and vpshl*.
 994         * i386-tbl.h: Re-generate.
 995
 996 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 997
 998         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 999         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1000         * i386-tbl.h: Re-generate.
1001
1002 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1003
1004         * i386-gen.c (set_bitfield): Ignore zero-length field names.
1005         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1006         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1007         * i386-tbl.h: Re-generate.
1008
1009 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1010
1011         * i386-gen.c (struct template_arg, struct template_instance,
1012         struct template_param, struct template, templates,
1013         parse_template, expand_templates): New.
1014         (process_i386_opcodes): Various local variables moved to
1015         expand_templates. Call parse_template and expand_templates.
1016         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1017         * i386-tbl.h: Re-generate.
1018
1019 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1020
1021         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1022         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1023         register and memory source templates. Replace VexW= by VexW*
1024         where applicable.
1025         * i386-tbl.h: Re-generate.
1026
1027 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1028
1029         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1030         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1031         * i386-tbl.h: Re-generate.
1032
1033 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1034
1035         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1036         * i386-tbl.h: Re-generate.
1037
1038 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1039
1040         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1041         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1042         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1043         VexW0 on SSE2AVX variants.
1044         (vmovq): Drop NoRex64 from XMM/XMM variants.
1045         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1046         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1047         applicable use VexW0.
1048         * i386-tbl.h: Re-generate.
1049
1050 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1051
1052         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1053         * i386-opc.h (Rex64): Delete.
1054         (struct i386_opcode_modifier): Remove rex64 field.
1055         * i386-opc.tbl (crc32): Drop Rex64.
1056         Replace Rex64 with Size64 everywhere else.
1057         * i386-tbl.h: Re-generate.
1058
1059 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1060
1061         * i386-dis.c (OP_E_memory): Exclude recording of used address
1062         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1063         addressed memory operands for MPX insns.
1064
1065 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1066
1067         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1068         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1069         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1070         (ptwrite): Split into non-64-bit and 64-bit forms.
1071         * i386-tbl.h: Re-generate.
1072
1073 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1074
1075         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1076         template.
1077         * i386-tbl.h: Re-generate.
1078
1079 2020-03-04  Jan Beulich  <jbeulich@suse.com>
1080
1081         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1082         (prefix_table): Move vmmcall here. Add vmgexit.
1083         (rm_table): Replace vmmcall entry by prefix_table[] escape.
1084         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1085         (cpu_flags): Add CpuSEV_ES entry.
1086         * i386-opc.h (CpuSEV_ES): New.
1087         (union i386_cpu_flags): Add cpusev_es field.
1088         * i386-opc.tbl (vmgexit): New.
1089         * i386-init.h, i386-tbl.h: Re-generate.
1090
1091 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1092
1093         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1094         with MnemonicSize.
1095         * i386-opc.h (IGNORESIZE): New.
1096         (DEFAULTSIZE): Likewise.
1097         (IgnoreSize): Removed.
1098         (DefaultSize): Likewise.
1099         (MnemonicSize): New.
1100         (i386_opcode_modifier): Replace ignoresize/defaultsize with
1101         mnemonicsize.
1102         * i386-opc.tbl (IgnoreSize): New.
1103         (DefaultSize): Likewise.
1104         * i386-tbl.h: Regenerated.
1105
1106 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1107
1108         PR 25627
1109         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1110         instructions.
1111
1112 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1113
1114         PR gas/25622
1115         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1116         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1117         * i386-tbl.h: Regenerated.
1118
1119 2020-02-26  Alan Modra  <amodra@gmail.com>
1120
1121         * aarch64-asm.c: Indent labels correctly.
1122         * aarch64-dis.c: Likewise.
1123         * aarch64-gen.c: Likewise.
1124         * aarch64-opc.c: Likewise.
1125         * alpha-dis.c: Likewise.
1126         * i386-dis.c: Likewise.
1127         * nds32-asm.c: Likewise.
1128         * nfp-dis.c: Likewise.
1129         * visium-dis.c: Likewise.
1130
1131 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
1132
1133         * arc-regs.h (int_vector_base): Make it available for all ARC
1134         CPUs.
1135
1136 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
1137
1138         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1139         changed.
1140
1141 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
1142
1143         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1144         c.mv/c.li if rs1 is zero.
1145
1146 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
1147
1148         * i386-gen.c (cpu_flag_init): Replace CpuABM with
1149         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
1150         CPU_POPCNT_FLAGS.
1151         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
1152         * i386-opc.h (CpuABM): Removed.
1153         (CpuPOPCNT): New.
1154         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
1155         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1156         popcnt.  Remove CpuABM from lzcnt.
1157         * i386-init.h: Regenerated.
1158         * i386-tbl.h: Likewise.
1159
1160 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1161
1162         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1163         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1164         VexW1 instead of open-coding them.
1165         * i386-tbl.h: Re-generate.
1166
1167 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1168
1169         * i386-opc.tbl (AddrPrefixOpReg): Define.
1170         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1171         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1172         templates. Drop NoRex64.
1173         * i386-tbl.h: Re-generate.
1174
1175 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1176
1177         PR gas/6518
1178         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1179         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1180         into Intel syntax instance (with Unpsecified) and AT&T one
1181         (without).
1182         (vcvtneps2bf16): Likewise, along with folding the two so far
1183         separate ones.
1184         * i386-tbl.h: Re-generate.
1185
1186 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1187
1188         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1189         CPU_ANY_SSE4A_FLAGS.
1190
1191 2020-02-17  Alan Modra  <amodra@gmail.com>
1192
1193         * i386-gen.c (cpu_flag_init): Correct last change.
1194
1195 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1196
1197         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
1198         CPU_ANY_SSE4_FLAGS.
1199
1200 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
1201
1202         * i386-opc.tbl (movsx): Remove Intel syntax comments.
1203         (movzx): Likewise.
1204
1205 2020-02-14  Jan Beulich  <jbeulich@suse.com>
1206
1207         PR gas/25438
1208         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1209         destination for Cpu64-only variant.
1210         (movzx): Fold patterns.
1211         * i386-tbl.h: Re-generate.
1212
1213 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1214
1215         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1216         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1217         CPU_ANY_SSE4_FLAGS entry.
1218         * i386-init.h: Re-generate.
1219
1220 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1221
1222         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1223         with Unspecified, making the present one AT&T syntax only.
1224         * i386-tbl.h: Re-generate.
1225
1226 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1227
1228         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1229         * i386-tbl.h: Re-generate.
1230
1231 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1232
1233         PR gas/24546
1234         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1235         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1236         Amd64 and Intel64 templates.
1237         (call, jmp): Likewise for far indirect variants. Dro
1238         Unspecified.
1239         * i386-tbl.h: Re-generate.
1240
1241 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1242
1243         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1244         * i386-opc.h (ShortForm): Delete.
1245         (struct i386_opcode_modifier): Remove shortform field.
1246         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1247         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1248         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1249         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1250         Drop ShortForm.
1251         * i386-tbl.h: Re-generate.
1252
1253 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1254
1255         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1256         fucompi): Drop ShortForm from operand-less templates.
1257         * i386-tbl.h: Re-generate.
1258
1259 2020-02-11  Alan Modra  <amodra@gmail.com>
1260
1261         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1262         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1263         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1264         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1265         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1266
1267 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1268
1269         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1270         (cde_opcodes): Add VCX* instructions.
1271
1272 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1273             Matthew Malcomson  <matthew.malcomson@arm.com>
1274
1275         * arm-dis.c (struct cdeopcode32): New.
1276         (CDE_OPCODE): New macro.
1277         (cde_opcodes): New disassembly table.
1278         (regnames): New option to table.
1279         (cde_coprocs): New global variable.
1280         (print_insn_cde): New
1281         (print_insn_thumb32): Use print_insn_cde.
1282         (parse_arm_disassembler_options): Parse coprocN args.
1283
1284 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1285
1286         PR gas/25516
1287         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1288         with ISA64.
1289         * i386-opc.h (AMD64): Removed.
1290         (Intel64): Likewose.
1291         (AMD64): New.
1292         (INTEL64): Likewise.
1293         (INTEL64ONLY): Likewise.
1294         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1295         * i386-opc.tbl (Amd64): New.
1296         (Intel64): Likewise.
1297         (Intel64Only): Likewise.
1298         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1299         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1300         * i386-tbl.h: Regenerated.
1301
1302 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1303
1304         PR 25469
1305         * z80-dis.c: Add support for GBZ80 opcodes.
1306
1307 2020-02-04  Alan Modra  <amodra@gmail.com>
1308
1309         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1310
1311 2020-02-03  Alan Modra  <amodra@gmail.com>
1312
1313         * m32c-ibld.c: Regenerate.
1314
1315 2020-02-01  Alan Modra  <amodra@gmail.com>
1316
1317         * frv-ibld.c: Regenerate.
1318
1319 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1320
1321         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1322         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1323         (OP_E_memory): Replace xmm_mdq_mode case label by
1324         vex_scalar_w_dq_mode one.
1325         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1326
1327 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1328
1329         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1330         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1331         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1332         (intel_operand_size): Drop vex_w_dq_mode case label.
1333
1334 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1335
1336         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1337         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1338
1339 2020-01-30  Alan Modra  <amodra@gmail.com>
1340
1341         * m32c-ibld.c: Regenerate.
1342
1343 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1344
1345         * bpf-opc.c: Regenerate.
1346
1347 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1348
1349         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1350         (dis386): Use them to replace C2/C3 table entries.
1351         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1352         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1353         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1354         * i386-tbl.h: Re-generate.
1355
1356 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1357
1358         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1359         forms.
1360         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1361         DefaultSize.
1362         * i386-tbl.h: Re-generate.
1363
1364 2020-01-30  Alan Modra  <amodra@gmail.com>
1365
1366         * tic4x-dis.c (tic4x_dp): Make unsigned.
1367
1368 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1369             Jan Beulich  <jbeulich@suse.com>
1370
1371         PR binutils/25445
1372         * i386-dis.c (MOVSXD_Fixup): New function.
1373         (movsxd_mode): New enum.
1374         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1375         (intel_operand_size): Handle movsxd_mode.
1376         (OP_E_register): Likewise.
1377         (OP_G): Likewise.
1378         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1379         register on movsxd.  Add movsxd with 16-bit destination register
1380         for AMD64 and Intel64 ISAs.
1381         * i386-tbl.h: Regenerated.
1382
1383 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1384
1385         PR 25403
1386         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1387         * aarch64-asm-2.c: Regenerate
1388         * aarch64-dis-2.c: Likewise.
1389         * aarch64-opc-2.c: Likewise.
1390
1391 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1392
1393         * i386-opc.tbl (sysret): Drop DefaultSize.
1394         * i386-tbl.h: Re-generate.
1395
1396 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1397
1398         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1399         Dword.
1400         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1401         * i386-tbl.h: Re-generate.
1402
1403 2020-01-20  Nick Clifton  <nickc@redhat.com>
1404
1405         * po/de.po: Updated German translation.
1406         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1407         * po/uk.po: Updated Ukranian translation.
1408
1409 2020-01-20  Alan Modra  <amodra@gmail.com>
1410
1411         * hppa-dis.c (fput_const): Remove useless cast.
1412
1413 2020-01-20  Alan Modra  <amodra@gmail.com>
1414
1415         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1416
1417 2020-01-18  Nick Clifton  <nickc@redhat.com>
1418
1419         * configure: Regenerate.
1420         * po/opcodes.pot: Regenerate.
1421
1422 2020-01-18  Nick Clifton  <nickc@redhat.com>
1423
1424         Binutils 2.34 branch created.
1425
1426 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1427
1428         * opintl.h: Fix spelling error (seperate).
1429
1430 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1431
1432         * i386-opc.tbl: Add {vex} pseudo prefix.
1433         * i386-tbl.h: Regenerated.
1434
1435 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1436
1437         PR 25376
1438         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1439         (neon_opcodes): Likewise.
1440         (select_arm_features): Make sure we enable MVE bits when selecting
1441         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1442         any architecture.
1443
1444 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1445
1446         * i386-opc.tbl: Drop stale comment from XOP section.
1447
1448 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1449
1450         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1451         (extractps): Add VexWIG to SSE2AVX forms.
1452         * i386-tbl.h: Re-generate.
1453
1454 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1455
1456         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1457         Size64 from and use VexW1 on SSE2AVX forms.
1458         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1459         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1460         * i386-tbl.h: Re-generate.
1461
1462 2020-01-15  Alan Modra  <amodra@gmail.com>
1463
1464         * tic4x-dis.c (tic4x_version): Make unsigned long.
1465         (optab, optab_special, registernames): New file scope vars.
1466         (tic4x_print_register): Set up registernames rather than
1467         malloc'd registertable.
1468         (tic4x_disassemble): Delete optable and optable_special.  Use
1469         optab and optab_special instead.  Throw away old optab,
1470         optab_special and registernames when info->mach changes.
1471
1472 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1473
1474         PR 25377
1475         * z80-dis.c (suffix): Use .db instruction to generate double
1476         prefix.
1477
1478 2020-01-14  Alan Modra  <amodra@gmail.com>
1479
1480         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1481         values to unsigned before shifting.
1482
1483 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1484
1485         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1486         flow instructions.
1487         (print_insn_thumb16, print_insn_thumb32): Likewise.
1488         (print_insn): Initialize the insn info.
1489         * i386-dis.c (print_insn): Initialize the insn info fields, and
1490         detect jumps.
1491
1492 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1493
1494         * arc-opc.c (C_NE): Make it required.
1495
1496 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1497
1498         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1499         reserved register name.
1500
1501 2020-01-13  Alan Modra  <amodra@gmail.com>
1502
1503         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1504         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1505
1506 2020-01-13  Alan Modra  <amodra@gmail.com>
1507
1508         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1509         result of wasm_read_leb128 in a uint64_t and check that bits
1510         are not lost when copying to other locals.  Use uint32_t for
1511         most locals.  Use PRId64 when printing int64_t.
1512
1513 2020-01-13  Alan Modra  <amodra@gmail.com>
1514
1515         * score-dis.c: Formatting.
1516         * score7-dis.c: Formatting.
1517
1518 2020-01-13  Alan Modra  <amodra@gmail.com>
1519
1520         * score-dis.c (print_insn_score48): Use unsigned variables for
1521         unsigned values.  Don't left shift negative values.
1522         (print_insn_score32): Likewise.
1523         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1524
1525 2020-01-13  Alan Modra  <amodra@gmail.com>
1526
1527         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1528
1529 2020-01-13  Alan Modra  <amodra@gmail.com>
1530
1531         * fr30-ibld.c: Regenerate.
1532
1533 2020-01-13  Alan Modra  <amodra@gmail.com>
1534
1535         * xgate-dis.c (print_insn): Don't left shift signed value.
1536         (ripBits): Formatting, use 1u.
1537
1538 2020-01-10  Alan Modra  <amodra@gmail.com>
1539
1540         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1541         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1542
1543 2020-01-10  Alan Modra  <amodra@gmail.com>
1544
1545         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1546         and XRREG value earlier to avoid a shift with negative exponent.
1547         * m10200-dis.c (disassemble): Similarly.
1548
1549 2020-01-09  Nick Clifton  <nickc@redhat.com>
1550
1551         PR 25224
1552         * z80-dis.c (ld_ii_ii): Use correct cast.
1553
1554 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1555
1556         PR 25224
1557         * z80-dis.c (ld_ii_ii): Use character constant when checking
1558         opcode byte value.
1559
1560 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1561
1562         * i386-dis.c (SEP_Fixup): New.
1563         (SEP): Define.
1564         (dis386_twobyte): Use it for sysenter/sysexit.
1565         (enum x86_64_isa): Change amd64 enumerator to value 1.
1566         (OP_J): Compare isa64 against intel64 instead of amd64.
1567         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1568         forms.
1569         * i386-tbl.h: Re-generate.
1570
1571 2020-01-08  Alan Modra  <amodra@gmail.com>
1572
1573         * z8k-dis.c: Include libiberty.h
1574         (instr_data_s): Make max_fetched unsigned.
1575         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1576         Don't exceed byte_info bounds.
1577         (output_instr): Make num_bytes unsigned.
1578         (unpack_instr): Likewise for nibl_count and loop.
1579         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1580         idx unsigned.
1581         * z8k-opc.h: Regenerate.
1582
1583 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1584
1585         * arc-tbl.h (llock): Use 'LLOCK' as class.
1586         (llockd): Likewise.
1587         (scond): Use 'SCOND' as class.
1588         (scondd): Likewise.
1589         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1590         (scondd): Likewise.
1591
1592 2020-01-06  Alan Modra  <amodra@gmail.com>
1593
1594         * m32c-ibld.c: Regenerate.
1595
1596 2020-01-06  Alan Modra  <amodra@gmail.com>
1597
1598         PR 25344
1599         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1600         Peek at next byte to prevent recursion on repeated prefix bytes.
1601         Ensure uninitialised "mybuf" is not accessed.
1602         (print_insn_z80): Don't zero n_fetch and n_used here,..
1603         (print_insn_z80_buf): ..do it here instead.
1604
1605 2020-01-04  Alan Modra  <amodra@gmail.com>
1606
1607         * m32r-ibld.c: Regenerate.
1608
1609 2020-01-04  Alan Modra  <amodra@gmail.com>
1610
1611         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1612
1613 2020-01-04  Alan Modra  <amodra@gmail.com>
1614
1615         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1616
1617 2020-01-04  Alan Modra  <amodra@gmail.com>
1618
1619         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1620
1621 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1622
1623         * aarch64-tbl.h (aarch64_opcode_table): Use
1624         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1625
1626 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1627
1628         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1629         forms of SUDOT and USDOT.
1630
1631 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1632
1633         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1634         uzip{1,2}.
1635         * opcodes/aarch64-dis-2.c: Re-generate.
1636
1637 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1638
1639         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1640         FMMLA encoding.
1641         * opcodes/aarch64-dis-2.c: Re-generate.
1642
1643 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1644
1645         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1646
1647 2020-01-01  Alan Modra  <amodra@gmail.com>
1648
1649         Update year range in copyright notice of all files.
1650
1651 For older changes see ChangeLog-2019
1652 \f
1653 Copyright (C) 2020 Free Software Foundation, Inc.
1654
1655 Copying and distribution of this file, with or without modification,
1656 are permitted in any medium without royalty provided the copyright
1657 notice and this notice are preserved.
1658
1659 Local Variables:
1660 mode: change-log
1661 left-margin: 8
1662 fill-column: 74
1663 version-control: never
1664 End: