opcodes/ChangeLog

   1 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
   2
   3         * arm-dis.c (print_insn_cde): Define 'V' parse character.
   4         (cde_opcodes): Add VCX* instructions.
   5
   6 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
   7             Matthew Malcomson  <matthew.malcomson@arm.com>
   8
   9         * arm-dis.c (struct cdeopcode32): New.
  10         (CDE_OPCODE): New macro.
  11         (cde_opcodes): New disassembly table.
  12         (regnames): New option to table.
  13         (cde_coprocs): New global variable.
  14         (print_insn_cde): New
  15         (print_insn_thumb32): Use print_insn_cde.
  16         (parse_arm_disassembler_options): Parse coprocN args.
  17
  18 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
  19
  20         PR gas/25516
  21         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
  22         with ISA64.
  23         * i386-opc.h (AMD64): Removed.
  24         (Intel64): Likewose.
  25         (AMD64): New.
  26         (INTEL64): Likewise.
  27         (INTEL64ONLY): Likewise.
  28         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
  29         * i386-opc.tbl (Amd64): New.
  30         (Intel64): Likewise.
  31         (Intel64Only): Likewise.
  32         Replace AMD64 with Amd64.  Update sysenter/sysenter with
  33         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
  34         * i386-tbl.h: Regenerated.
  35
  36 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
  37
  38         PR 25469
  39         * z80-dis.c: Add support for GBZ80 opcodes.
  40
  41 2020-02-04  Alan Modra  <amodra@gmail.com>
  42
  43         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
  44
  45 2020-02-03  Alan Modra  <amodra@gmail.com>
  46
  47         * m32c-ibld.c: Regenerate.
  48
  49 2020-02-01  Alan Modra  <amodra@gmail.com>
  50
  51         * frv-ibld.c: Regenerate.
  52
  53 2020-01-31  Jan Beulich  <jbeulich@suse.com>
  54
  55         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
  56         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
  57         (OP_E_memory): Replace xmm_mdq_mode case label by
  58         vex_scalar_w_dq_mode one.
  59         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
  60
  61 2020-01-31  Jan Beulich  <jbeulich@suse.com>
  62
  63         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
  64         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
  65         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
  66         (intel_operand_size): Drop vex_w_dq_mode case label.
  67
  68 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
  69
  70         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
  71         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
  72
  73 2020-01-30  Alan Modra  <amodra@gmail.com>
  74
  75         * m32c-ibld.c: Regenerate.
  76
  77 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
  78
  79         * bpf-opc.c: Regenerate.
  80
  81 2020-01-30  Jan Beulich  <jbeulich@suse.com>
  82
  83         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
  84         (dis386): Use them to replace C2/C3 table entries.
  85         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
  86         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
  87         ones. Use Size64 instead of DefaultSize on Intel64 ones.
  88         * i386-tbl.h: Re-generate.
  89
  90 2020-01-30  Jan Beulich  <jbeulich@suse.com>
  91
  92         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
  93         forms.
  94         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
  95         DefaultSize.
  96         * i386-tbl.h: Re-generate.
  97
  98 2020-01-30  Alan Modra  <amodra@gmail.com>
  99
 100         * tic4x-dis.c (tic4x_dp): Make unsigned.
 101
 102 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 103             Jan Beulich  <jbeulich@suse.com>
 104
 105         PR binutils/25445
 106         * i386-dis.c (MOVSXD_Fixup): New function.
 107         (movsxd_mode): New enum.
 108         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 109         (intel_operand_size): Handle movsxd_mode.
 110         (OP_E_register): Likewise.
 111         (OP_G): Likewise.
 112         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 113         register on movsxd.  Add movsxd with 16-bit destination register
 114         for AMD64 and Intel64 ISAs.
 115         * i386-tbl.h: Regenerated.
 116
 117 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 118
 119         PR 25403
 120         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 121         * aarch64-asm-2.c: Regenerate
 122         * aarch64-dis-2.c: Likewise.
 123         * aarch64-opc-2.c: Likewise.
 124
 125 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-opc.tbl (sysret): Drop DefaultSize.
 128         * i386-tbl.h: Re-generate.
 129
 130 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 133         Dword.
 134         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 135         * i386-tbl.h: Re-generate.
 136
 137 2020-01-20  Nick Clifton  <nickc@redhat.com>
 138
 139         * po/de.po: Updated German translation.
 140         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 141         * po/uk.po: Updated Ukranian translation.
 142
 143 2020-01-20  Alan Modra  <amodra@gmail.com>
 144
 145         * hppa-dis.c (fput_const): Remove useless cast.
 146
 147 2020-01-20  Alan Modra  <amodra@gmail.com>
 148
 149         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 150
 151 2020-01-18  Nick Clifton  <nickc@redhat.com>
 152
 153         * configure: Regenerate.
 154         * po/opcodes.pot: Regenerate.
 155
 156 2020-01-18  Nick Clifton  <nickc@redhat.com>
 157
 158         Binutils 2.34 branch created.
 159
 160 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 161
 162         * opintl.h: Fix spelling error (seperate).
 163
 164 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 165
 166         * i386-opc.tbl: Add {vex} pseudo prefix.
 167         * i386-tbl.h: Regenerated.
 168
 169 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 170
 171         PR 25376
 172         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 173         (neon_opcodes): Likewise.
 174         (select_arm_features): Make sure we enable MVE bits when selecting
 175         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 176         any architecture.
 177
 178 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 179
 180         * i386-opc.tbl: Drop stale comment from XOP section.
 181
 182 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 183
 184         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 185         (extractps): Add VexWIG to SSE2AVX forms.
 186         * i386-tbl.h: Re-generate.
 187
 188 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 189
 190         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 191         Size64 from and use VexW1 on SSE2AVX forms.
 192         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 193         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 194         * i386-tbl.h: Re-generate.
 195
 196 2020-01-15  Alan Modra  <amodra@gmail.com>
 197
 198         * tic4x-dis.c (tic4x_version): Make unsigned long.
 199         (optab, optab_special, registernames): New file scope vars.
 200         (tic4x_print_register): Set up registernames rather than
 201         malloc'd registertable.
 202         (tic4x_disassemble): Delete optable and optable_special.  Use
 203         optab and optab_special instead.  Throw away old optab,
 204         optab_special and registernames when info->mach changes.
 205
 206 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 207
 208         PR 25377
 209         * z80-dis.c (suffix): Use .db instruction to generate double
 210         prefix.
 211
 212 2020-01-14  Alan Modra  <amodra@gmail.com>
 213
 214         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 215         values to unsigned before shifting.
 216
 217 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 218
 219         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 220         flow instructions.
 221         (print_insn_thumb16, print_insn_thumb32): Likewise.
 222         (print_insn): Initialize the insn info.
 223         * i386-dis.c (print_insn): Initialize the insn info fields, and
 224         detect jumps.
 225
 226 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 227
 228         * arc-opc.c (C_NE): Make it required.
 229
 230 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 231
 232         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 233         reserved register name.
 234
 235 2020-01-13  Alan Modra  <amodra@gmail.com>
 236
 237         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 238         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 239
 240 2020-01-13  Alan Modra  <amodra@gmail.com>
 241
 242         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 243         result of wasm_read_leb128 in a uint64_t and check that bits
 244         are not lost when copying to other locals.  Use uint32_t for
 245         most locals.  Use PRId64 when printing int64_t.
 246
 247 2020-01-13  Alan Modra  <amodra@gmail.com>
 248
 249         * score-dis.c: Formatting.
 250         * score7-dis.c: Formatting.
 251
 252 2020-01-13  Alan Modra  <amodra@gmail.com>
 253
 254         * score-dis.c (print_insn_score48): Use unsigned variables for
 255         unsigned values.  Don't left shift negative values.
 256         (print_insn_score32): Likewise.
 257         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 258
 259 2020-01-13  Alan Modra  <amodra@gmail.com>
 260
 261         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 262
 263 2020-01-13  Alan Modra  <amodra@gmail.com>
 264
 265         * fr30-ibld.c: Regenerate.
 266
 267 2020-01-13  Alan Modra  <amodra@gmail.com>
 268
 269         * xgate-dis.c (print_insn): Don't left shift signed value.
 270         (ripBits): Formatting, use 1u.
 271
 272 2020-01-10  Alan Modra  <amodra@gmail.com>
 273
 274         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 275         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 276
 277 2020-01-10  Alan Modra  <amodra@gmail.com>
 278
 279         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 280         and XRREG value earlier to avoid a shift with negative exponent.
 281         * m10200-dis.c (disassemble): Similarly.
 282
 283 2020-01-09  Nick Clifton  <nickc@redhat.com>
 284
 285         PR 25224
 286         * z80-dis.c (ld_ii_ii): Use correct cast.
 287
 288 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 289
 290         PR 25224
 291         * z80-dis.c (ld_ii_ii): Use character constant when checking
 292         opcode byte value.
 293
 294 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 295
 296         * i386-dis.c (SEP_Fixup): New.
 297         (SEP): Define.
 298         (dis386_twobyte): Use it for sysenter/sysexit.
 299         (enum x86_64_isa): Change amd64 enumerator to value 1.
 300         (OP_J): Compare isa64 against intel64 instead of amd64.
 301         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 302         forms.
 303         * i386-tbl.h: Re-generate.
 304
 305 2020-01-08  Alan Modra  <amodra@gmail.com>
 306
 307         * z8k-dis.c: Include libiberty.h
 308         (instr_data_s): Make max_fetched unsigned.
 309         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 310         Don't exceed byte_info bounds.
 311         (output_instr): Make num_bytes unsigned.
 312         (unpack_instr): Likewise for nibl_count and loop.
 313         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 314         idx unsigned.
 315         * z8k-opc.h: Regenerate.
 316
 317 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 318
 319         * arc-tbl.h (llock): Use 'LLOCK' as class.
 320         (llockd): Likewise.
 321         (scond): Use 'SCOND' as class.
 322         (scondd): Likewise.
 323         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 324         (scondd): Likewise.
 325
 326 2020-01-06  Alan Modra  <amodra@gmail.com>
 327
 328         * m32c-ibld.c: Regenerate.
 329
 330 2020-01-06  Alan Modra  <amodra@gmail.com>
 331
 332         PR 25344
 333         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 334         Peek at next byte to prevent recursion on repeated prefix bytes.
 335         Ensure uninitialised "mybuf" is not accessed.
 336         (print_insn_z80): Don't zero n_fetch and n_used here,..
 337         (print_insn_z80_buf): ..do it here instead.
 338
 339 2020-01-04  Alan Modra  <amodra@gmail.com>
 340
 341         * m32r-ibld.c: Regenerate.
 342
 343 2020-01-04  Alan Modra  <amodra@gmail.com>
 344
 345         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 346
 347 2020-01-04  Alan Modra  <amodra@gmail.com>
 348
 349         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 350
 351 2020-01-04  Alan Modra  <amodra@gmail.com>
 352
 353         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 354
 355 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 356
 357         * aarch64-tbl.h (aarch64_opcode_table): Use
 358         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 359
 360 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 361
 362         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 363         forms of SUDOT and USDOT.
 364
 365 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 366
 367         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 368         uzip{1,2}.
 369         * opcodes/aarch64-dis-2.c: Re-generate.
 370
 371 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 372
 373         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 374         FMMLA encoding.
 375         * opcodes/aarch64-dis-2.c: Re-generate.
 376
 377 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 378
 379         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 380
 381 2020-01-01  Alan Modra  <amodra@gmail.com>
 382
 383         Update year range in copyright notice of all files.
 384
 385 For older changes see ChangeLog-2019
 386 \f
 387 Copyright (C) 2020 Free Software Foundation, Inc.
 388
 389 Copying and distribution of this file, with or without modification,
 390 are permitted in any medium without royalty provided the copyright
 391 notice and this notice are preserved.
 392
 393 Local Variables:
 394 mode: change-log
 395 left-margin: 8
 396 fill-column: 74
 397 version-control: never
 398 End: