opcodes/ChangeLog

   1 2020-04-29  Nick Clifton  <nickc@redhat.com>
   2
   3         PR 22699
   4         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
   5         and SETRC insns.
   6
   7 2020-04-29  Nick Clifton  <nickc@redhat.com>
   8
   9         * po/sv.po: Updated Swedish translation.
  10
  11 2020-04-29  Nick Clifton  <nickc@redhat.com>
  12
  13         PR 22699
  14         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
  15         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
  16         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
  17         IMM0_8U case.
  18
  19 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
  20
  21         PR 25848
  22         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
  23         cmpi only on m68020up and cpu32.
  24
  25 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  26
  27         * aarch64-asm.c (aarch64_ins_none): New.
  28         * aarch64-asm.h (ins_none): New declaration.
  29         * aarch64-dis.c (aarch64_ext_none): New.
  30         * aarch64-dis.h (ext_none): New declaration.
  31         * aarch64-opc.c (aarch64_print_operand): Update case for
  32         AARCH64_OPND_BARRIER_PSB.
  33         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
  34         (AARCH64_OPERANDS): Update inserter/extracter for
  35         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
  36         * aarch64-asm-2.c: Regenerated.
  37         * aarch64-dis-2.c: Regenerated.
  38         * aarch64-opc-2.c: Regenerated.
  39
  40 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  41
  42         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
  43         (aarch64_feature_ras, RAS): Likewise.
  44         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
  45         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
  46         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
  47         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
  48         * aarch64-asm-2.c: Regenerated.
  49         * aarch64-dis-2.c: Regenerated.
  50         * aarch64-opc-2.c: Regenerated.
  51
  52 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
  53
  54         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
  55         (print_insn_neon): Support disassembly of conditional
  56         instructions.
  57
  58 2020-02-16  David Faust  <david.faust@oracle.com>
  59
  60         * bpf-desc.c: Regenerate.
  61         * bpf-desc.h: Likewise.
  62         * bpf-opc.c: Regenerate.
  63         * bpf-opc.h: Likewise.
  64
  65 2020-04-07  Lili Cui  <lili.cui@intel.com>
  66
  67         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
  68         (prefix_table): New instructions (see prefixes above).
  69         (rm_table): Likewise
  70         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
  71         CPU_ANY_TSXLDTRK_FLAGS.
  72         (cpu_flags): Add CpuTSXLDTRK.
  73         * i386-opc.h (enum): Add CpuTSXLDTRK.
  74         (i386_cpu_flags): Add cputsxldtrk.
  75         * i386-opc.tbl: Add XSUSPLDTRK insns.
  76         * i386-init.h: Regenerate.
  77         * i386-tbl.h: Likewise.
  78
  79 2020-04-02  Lili Cui  <lili.cui@intel.com>
  80
  81         * i386-dis.c (prefix_table): New instructions serialize.
  82         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
  83         CPU_ANY_SERIALIZE_FLAGS.
  84         (cpu_flags): Add CpuSERIALIZE.
  85         * i386-opc.h (enum): Add CpuSERIALIZE.
  86         (i386_cpu_flags): Add cpuserialize.
  87         * i386-opc.tbl: Add SERIALIZE insns.
  88         * i386-init.h: Regenerate.
  89         * i386-tbl.h: Likewise.
  90
  91 2020-03-26  Alan Modra  <amodra@gmail.com>
  92
  93         * disassemble.h (opcodes_assert): Declare.
  94         (OPCODES_ASSERT): Define.
  95         * disassemble.c: Don't include assert.h.  Include opintl.h.
  96         (opcodes_assert): New function.
  97         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
  98         (bfd_h8_disassemble): Reduce size of data array.  Correctly
  99         calculate maxlen.  Omit insn decoding when insn length exceeds
 100         maxlen.  Exit from nibble loop when looking for E, before
 101         accessing next data byte.  Move processing of E outside loop.
 102         Replace tests of maxlen in loop with assertions.
 103
 104 2020-03-26  Alan Modra  <amodra@gmail.com>
 105
 106         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 107
 108 2020-03-25  Alan Modra  <amodra@gmail.com>
 109
 110         * z80-dis.c (suffix): Init mybuf.
 111
 112 2020-03-22  Alan Modra  <amodra@gmail.com>
 113
 114         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 115         successflly read from section.
 116
 117 2020-03-22  Alan Modra  <amodra@gmail.com>
 118
 119         * arc-dis.c (find_format): Use ISO C string concatenation rather
 120         than line continuation within a string.  Don't access needs_limm
 121         before testing opcode != NULL.
 122
 123 2020-03-22  Alan Modra  <amodra@gmail.com>
 124
 125         * ns32k-dis.c (print_insn_arg): Update comment.
 126         (print_insn_ns32k): Reduce size of index_offset array, and
 127         initialize, passing -1 to print_insn_arg for args that are not
 128         an index.  Don't exit arg loop early.  Abort on bad arg number.
 129
 130 2020-03-22  Alan Modra  <amodra@gmail.com>
 131
 132         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 133         * s12z-opc.c: Formatting.
 134         (operands_f): Return an int.
 135         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 136         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 137         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 138         (exg_sex_discrim): Likewise.
 139         (create_immediate_operand, create_bitfield_operand),
 140         (create_register_operand_with_size, create_register_all_operand),
 141         (create_register_all16_operand, create_simple_memory_operand),
 142         (create_memory_operand, create_memory_auto_operand): Don't
 143         segfault on malloc failure.
 144         (z_ext24_decode): Return an int status, negative on fail, zero
 145         on success.
 146         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 147         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 148         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 149         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 150         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 151         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 152         (loop_primitive_decode, shift_decode, psh_pul_decode),
 153         (bit_field_decode): Similarly.
 154         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 155         to return value, update callers.
 156         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 157         Don't segfault on NULL operand.
 158         (decode_operation): Return OP_INVALID on first fail.
 159         (decode_s12z): Check all reads, returning -1 on fail.
 160
 161 2020-03-20  Alan Modra  <amodra@gmail.com>
 162
 163         * metag-dis.c (print_insn_metag): Don't ignore status from
 164         read_memory_func.
 165
 166 2020-03-20  Alan Modra  <amodra@gmail.com>
 167
 168         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 169         Initialize parts of buffer not written when handling a possible
 170         2-byte insn at end of section.  Don't attempt decoding of such
 171         an insn by the 4-byte machinery.
 172
 173 2020-03-20  Alan Modra  <amodra@gmail.com>
 174
 175         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 176         partially filled buffer.  Prevent lookup of 4-byte insns when
 177         only VLE 2-byte insns are possible due to section size.  Print
 178         ".word" rather than ".long" for 2-byte leftovers.
 179
 180 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 181
 182         PR 25641
 183         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 184
 185 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 186
 187         * i386-dis.c (X86_64_0D): Rename to ...
 188         (X86_64_0E): ... this.
 189
 190 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 191
 192         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 193         * Makefile.in: Regenerated.
 194
 195 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 196
 197         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 198         3-operand pseudos.
 199         * i386-tbl.h: Re-generate.
 200
 201 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 202
 203         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 204         vprot*, vpsha*, and vpshl*.
 205         * i386-tbl.h: Re-generate.
 206
 207 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 208
 209         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 210         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 211         * i386-tbl.h: Re-generate.
 212
 213 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 214
 215         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 216         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 217         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 218         * i386-tbl.h: Re-generate.
 219
 220 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 221
 222         * i386-gen.c (struct template_arg, struct template_instance,
 223         struct template_param, struct template, templates,
 224         parse_template, expand_templates): New.
 225         (process_i386_opcodes): Various local variables moved to
 226         expand_templates. Call parse_template and expand_templates.
 227         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 228         * i386-tbl.h: Re-generate.
 229
 230 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 231
 232         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 233         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 234         register and memory source templates. Replace VexW= by VexW*
 235         where applicable.
 236         * i386-tbl.h: Re-generate.
 237
 238 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 239
 240         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 241         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 242         * i386-tbl.h: Re-generate.
 243
 244 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 245
 246         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 247         * i386-tbl.h: Re-generate.
 248
 249 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 250
 251         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 252         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 253         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 254         VexW0 on SSE2AVX variants.
 255         (vmovq): Drop NoRex64 from XMM/XMM variants.
 256         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 257         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 258         applicable use VexW0.
 259         * i386-tbl.h: Re-generate.
 260
 261 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 262
 263         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 264         * i386-opc.h (Rex64): Delete.
 265         (struct i386_opcode_modifier): Remove rex64 field.
 266         * i386-opc.tbl (crc32): Drop Rex64.
 267         Replace Rex64 with Size64 everywhere else.
 268         * i386-tbl.h: Re-generate.
 269
 270 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 271
 272         * i386-dis.c (OP_E_memory): Exclude recording of used address
 273         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 274         addressed memory operands for MPX insns.
 275
 276 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 277
 278         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 279         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 280         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 281         (ptwrite): Split into non-64-bit and 64-bit forms.
 282         * i386-tbl.h: Re-generate.
 283
 284 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 285
 286         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 287         template.
 288         * i386-tbl.h: Re-generate.
 289
 290 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 291
 292         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 293         (prefix_table): Move vmmcall here. Add vmgexit.
 294         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 295         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 296         (cpu_flags): Add CpuSEV_ES entry.
 297         * i386-opc.h (CpuSEV_ES): New.
 298         (union i386_cpu_flags): Add cpusev_es field.
 299         * i386-opc.tbl (vmgexit): New.
 300         * i386-init.h, i386-tbl.h: Re-generate.
 301
 302 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 303
 304         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 305         with MnemonicSize.
 306         * i386-opc.h (IGNORESIZE): New.
 307         (DEFAULTSIZE): Likewise.
 308         (IgnoreSize): Removed.
 309         (DefaultSize): Likewise.
 310         (MnemonicSize): New.
 311         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 312         mnemonicsize.
 313         * i386-opc.tbl (IgnoreSize): New.
 314         (DefaultSize): Likewise.
 315         * i386-tbl.h: Regenerated.
 316
 317 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 318
 319         PR 25627
 320         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 321         instructions.
 322
 323 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 324
 325         PR gas/25622
 326         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 327         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 328         * i386-tbl.h: Regenerated.
 329
 330 2020-02-26  Alan Modra  <amodra@gmail.com>
 331
 332         * aarch64-asm.c: Indent labels correctly.
 333         * aarch64-dis.c: Likewise.
 334         * aarch64-gen.c: Likewise.
 335         * aarch64-opc.c: Likewise.
 336         * alpha-dis.c: Likewise.
 337         * i386-dis.c: Likewise.
 338         * nds32-asm.c: Likewise.
 339         * nfp-dis.c: Likewise.
 340         * visium-dis.c: Likewise.
 341
 342 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 343
 344         * arc-regs.h (int_vector_base): Make it available for all ARC
 345         CPUs.
 346
 347 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 348
 349         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 350         changed.
 351
 352 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 353
 354         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 355         c.mv/c.li if rs1 is zero.
 356
 357 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 358
 359         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 360         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 361         CPU_POPCNT_FLAGS.
 362         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 363         * i386-opc.h (CpuABM): Removed.
 364         (CpuPOPCNT): New.
 365         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 366         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 367         popcnt.  Remove CpuABM from lzcnt.
 368         * i386-init.h: Regenerated.
 369         * i386-tbl.h: Likewise.
 370
 371 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 372
 373         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 374         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 375         VexW1 instead of open-coding them.
 376         * i386-tbl.h: Re-generate.
 377
 378 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 379
 380         * i386-opc.tbl (AddrPrefixOpReg): Define.
 381         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 382         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 383         templates. Drop NoRex64.
 384         * i386-tbl.h: Re-generate.
 385
 386 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 387
 388         PR gas/6518
 389         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 390         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 391         into Intel syntax instance (with Unpsecified) and AT&T one
 392         (without).
 393         (vcvtneps2bf16): Likewise, along with folding the two so far
 394         separate ones.
 395         * i386-tbl.h: Re-generate.
 396
 397 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 398
 399         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 400         CPU_ANY_SSE4A_FLAGS.
 401
 402 2020-02-17  Alan Modra  <amodra@gmail.com>
 403
 404         * i386-gen.c (cpu_flag_init): Correct last change.
 405
 406 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 407
 408         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 409         CPU_ANY_SSE4_FLAGS.
 410
 411 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 412
 413         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 414         (movzx): Likewise.
 415
 416 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 417
 418         PR gas/25438
 419         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 420         destination for Cpu64-only variant.
 421         (movzx): Fold patterns.
 422         * i386-tbl.h: Re-generate.
 423
 424 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 425
 426         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 427         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 428         CPU_ANY_SSE4_FLAGS entry.
 429         * i386-init.h: Re-generate.
 430
 431 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 432
 433         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 434         with Unspecified, making the present one AT&T syntax only.
 435         * i386-tbl.h: Re-generate.
 436
 437 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 438
 439         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 440         * i386-tbl.h: Re-generate.
 441
 442 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 443
 444         PR gas/24546
 445         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 446         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 447         Amd64 and Intel64 templates.
 448         (call, jmp): Likewise for far indirect variants. Dro
 449         Unspecified.
 450         * i386-tbl.h: Re-generate.
 451
 452 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 453
 454         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 455         * i386-opc.h (ShortForm): Delete.
 456         (struct i386_opcode_modifier): Remove shortform field.
 457         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 458         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 459         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 460         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 461         Drop ShortForm.
 462         * i386-tbl.h: Re-generate.
 463
 464 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 465
 466         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 467         fucompi): Drop ShortForm from operand-less templates.
 468         * i386-tbl.h: Re-generate.
 469
 470 2020-02-11  Alan Modra  <amodra@gmail.com>
 471
 472         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 473         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 474         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 475         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 476         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 477
 478 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 479
 480         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 481         (cde_opcodes): Add VCX* instructions.
 482
 483 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 484             Matthew Malcomson  <matthew.malcomson@arm.com>
 485
 486         * arm-dis.c (struct cdeopcode32): New.
 487         (CDE_OPCODE): New macro.
 488         (cde_opcodes): New disassembly table.
 489         (regnames): New option to table.
 490         (cde_coprocs): New global variable.
 491         (print_insn_cde): New
 492         (print_insn_thumb32): Use print_insn_cde.
 493         (parse_arm_disassembler_options): Parse coprocN args.
 494
 495 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 496
 497         PR gas/25516
 498         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 499         with ISA64.
 500         * i386-opc.h (AMD64): Removed.
 501         (Intel64): Likewose.
 502         (AMD64): New.
 503         (INTEL64): Likewise.
 504         (INTEL64ONLY): Likewise.
 505         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 506         * i386-opc.tbl (Amd64): New.
 507         (Intel64): Likewise.
 508         (Intel64Only): Likewise.
 509         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 510         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 511         * i386-tbl.h: Regenerated.
 512
 513 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 514
 515         PR 25469
 516         * z80-dis.c: Add support for GBZ80 opcodes.
 517
 518 2020-02-04  Alan Modra  <amodra@gmail.com>
 519
 520         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 521
 522 2020-02-03  Alan Modra  <amodra@gmail.com>
 523
 524         * m32c-ibld.c: Regenerate.
 525
 526 2020-02-01  Alan Modra  <amodra@gmail.com>
 527
 528         * frv-ibld.c: Regenerate.
 529
 530 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 531
 532         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 533         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 534         (OP_E_memory): Replace xmm_mdq_mode case label by
 535         vex_scalar_w_dq_mode one.
 536         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 537
 538 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 539
 540         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 541         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 542         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 543         (intel_operand_size): Drop vex_w_dq_mode case label.
 544
 545 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 546
 547         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 548         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 549
 550 2020-01-30  Alan Modra  <amodra@gmail.com>
 551
 552         * m32c-ibld.c: Regenerate.
 553
 554 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 555
 556         * bpf-opc.c: Regenerate.
 557
 558 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 559
 560         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 561         (dis386): Use them to replace C2/C3 table entries.
 562         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 563         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 564         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 565         * i386-tbl.h: Re-generate.
 566
 567 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 568
 569         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 570         forms.
 571         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 572         DefaultSize.
 573         * i386-tbl.h: Re-generate.
 574
 575 2020-01-30  Alan Modra  <amodra@gmail.com>
 576
 577         * tic4x-dis.c (tic4x_dp): Make unsigned.
 578
 579 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 580             Jan Beulich  <jbeulich@suse.com>
 581
 582         PR binutils/25445
 583         * i386-dis.c (MOVSXD_Fixup): New function.
 584         (movsxd_mode): New enum.
 585         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 586         (intel_operand_size): Handle movsxd_mode.
 587         (OP_E_register): Likewise.
 588         (OP_G): Likewise.
 589         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 590         register on movsxd.  Add movsxd with 16-bit destination register
 591         for AMD64 and Intel64 ISAs.
 592         * i386-tbl.h: Regenerated.
 593
 594 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 595
 596         PR 25403
 597         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 598         * aarch64-asm-2.c: Regenerate
 599         * aarch64-dis-2.c: Likewise.
 600         * aarch64-opc-2.c: Likewise.
 601
 602 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 603
 604         * i386-opc.tbl (sysret): Drop DefaultSize.
 605         * i386-tbl.h: Re-generate.
 606
 607 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 608
 609         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 610         Dword.
 611         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 612         * i386-tbl.h: Re-generate.
 613
 614 2020-01-20  Nick Clifton  <nickc@redhat.com>
 615
 616         * po/de.po: Updated German translation.
 617         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 618         * po/uk.po: Updated Ukranian translation.
 619
 620 2020-01-20  Alan Modra  <amodra@gmail.com>
 621
 622         * hppa-dis.c (fput_const): Remove useless cast.
 623
 624 2020-01-20  Alan Modra  <amodra@gmail.com>
 625
 626         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 627
 628 2020-01-18  Nick Clifton  <nickc@redhat.com>
 629
 630         * configure: Regenerate.
 631         * po/opcodes.pot: Regenerate.
 632
 633 2020-01-18  Nick Clifton  <nickc@redhat.com>
 634
 635         Binutils 2.34 branch created.
 636
 637 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 638
 639         * opintl.h: Fix spelling error (seperate).
 640
 641 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 642
 643         * i386-opc.tbl: Add {vex} pseudo prefix.
 644         * i386-tbl.h: Regenerated.
 645
 646 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 647
 648         PR 25376
 649         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 650         (neon_opcodes): Likewise.
 651         (select_arm_features): Make sure we enable MVE bits when selecting
 652         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 653         any architecture.
 654
 655 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 656
 657         * i386-opc.tbl: Drop stale comment from XOP section.
 658
 659 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 660
 661         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 662         (extractps): Add VexWIG to SSE2AVX forms.
 663         * i386-tbl.h: Re-generate.
 664
 665 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 666
 667         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 668         Size64 from and use VexW1 on SSE2AVX forms.
 669         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 670         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 671         * i386-tbl.h: Re-generate.
 672
 673 2020-01-15  Alan Modra  <amodra@gmail.com>
 674
 675         * tic4x-dis.c (tic4x_version): Make unsigned long.
 676         (optab, optab_special, registernames): New file scope vars.
 677         (tic4x_print_register): Set up registernames rather than
 678         malloc'd registertable.
 679         (tic4x_disassemble): Delete optable and optable_special.  Use
 680         optab and optab_special instead.  Throw away old optab,
 681         optab_special and registernames when info->mach changes.
 682
 683 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 684
 685         PR 25377
 686         * z80-dis.c (suffix): Use .db instruction to generate double
 687         prefix.
 688
 689 2020-01-14  Alan Modra  <amodra@gmail.com>
 690
 691         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 692         values to unsigned before shifting.
 693
 694 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 695
 696         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 697         flow instructions.
 698         (print_insn_thumb16, print_insn_thumb32): Likewise.
 699         (print_insn): Initialize the insn info.
 700         * i386-dis.c (print_insn): Initialize the insn info fields, and
 701         detect jumps.
 702
 703 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 704
 705         * arc-opc.c (C_NE): Make it required.
 706
 707 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 708
 709         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 710         reserved register name.
 711
 712 2020-01-13  Alan Modra  <amodra@gmail.com>
 713
 714         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 715         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 716
 717 2020-01-13  Alan Modra  <amodra@gmail.com>
 718
 719         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 720         result of wasm_read_leb128 in a uint64_t and check that bits
 721         are not lost when copying to other locals.  Use uint32_t for
 722         most locals.  Use PRId64 when printing int64_t.
 723
 724 2020-01-13  Alan Modra  <amodra@gmail.com>
 725
 726         * score-dis.c: Formatting.
 727         * score7-dis.c: Formatting.
 728
 729 2020-01-13  Alan Modra  <amodra@gmail.com>
 730
 731         * score-dis.c (print_insn_score48): Use unsigned variables for
 732         unsigned values.  Don't left shift negative values.
 733         (print_insn_score32): Likewise.
 734         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 735
 736 2020-01-13  Alan Modra  <amodra@gmail.com>
 737
 738         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 739
 740 2020-01-13  Alan Modra  <amodra@gmail.com>
 741
 742         * fr30-ibld.c: Regenerate.
 743
 744 2020-01-13  Alan Modra  <amodra@gmail.com>
 745
 746         * xgate-dis.c (print_insn): Don't left shift signed value.
 747         (ripBits): Formatting, use 1u.
 748
 749 2020-01-10  Alan Modra  <amodra@gmail.com>
 750
 751         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 752         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 753
 754 2020-01-10  Alan Modra  <amodra@gmail.com>
 755
 756         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 757         and XRREG value earlier to avoid a shift with negative exponent.
 758         * m10200-dis.c (disassemble): Similarly.
 759
 760 2020-01-09  Nick Clifton  <nickc@redhat.com>
 761
 762         PR 25224
 763         * z80-dis.c (ld_ii_ii): Use correct cast.
 764
 765 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 766
 767         PR 25224
 768         * z80-dis.c (ld_ii_ii): Use character constant when checking
 769         opcode byte value.
 770
 771 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 772
 773         * i386-dis.c (SEP_Fixup): New.
 774         (SEP): Define.
 775         (dis386_twobyte): Use it for sysenter/sysexit.
 776         (enum x86_64_isa): Change amd64 enumerator to value 1.
 777         (OP_J): Compare isa64 against intel64 instead of amd64.
 778         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 779         forms.
 780         * i386-tbl.h: Re-generate.
 781
 782 2020-01-08  Alan Modra  <amodra@gmail.com>
 783
 784         * z8k-dis.c: Include libiberty.h
 785         (instr_data_s): Make max_fetched unsigned.
 786         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 787         Don't exceed byte_info bounds.
 788         (output_instr): Make num_bytes unsigned.
 789         (unpack_instr): Likewise for nibl_count and loop.
 790         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 791         idx unsigned.
 792         * z8k-opc.h: Regenerate.
 793
 794 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 795
 796         * arc-tbl.h (llock): Use 'LLOCK' as class.
 797         (llockd): Likewise.
 798         (scond): Use 'SCOND' as class.
 799         (scondd): Likewise.
 800         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 801         (scondd): Likewise.
 802
 803 2020-01-06  Alan Modra  <amodra@gmail.com>
 804
 805         * m32c-ibld.c: Regenerate.
 806
 807 2020-01-06  Alan Modra  <amodra@gmail.com>
 808
 809         PR 25344
 810         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 811         Peek at next byte to prevent recursion on repeated prefix bytes.
 812         Ensure uninitialised "mybuf" is not accessed.
 813         (print_insn_z80): Don't zero n_fetch and n_used here,..
 814         (print_insn_z80_buf): ..do it here instead.
 815
 816 2020-01-04  Alan Modra  <amodra@gmail.com>
 817
 818         * m32r-ibld.c: Regenerate.
 819
 820 2020-01-04  Alan Modra  <amodra@gmail.com>
 821
 822         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 823
 824 2020-01-04  Alan Modra  <amodra@gmail.com>
 825
 826         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 827
 828 2020-01-04  Alan Modra  <amodra@gmail.com>
 829
 830         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 831
 832 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 833
 834         * aarch64-tbl.h (aarch64_opcode_table): Use
 835         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 836
 837 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 838
 839         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 840         forms of SUDOT and USDOT.
 841
 842 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 843
 844         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 845         uzip{1,2}.
 846         * opcodes/aarch64-dis-2.c: Re-generate.
 847
 848 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 849
 850         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 851         FMMLA encoding.
 852         * opcodes/aarch64-dis-2.c: Re-generate.
 853
 854 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 855
 856         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 857
 858 2020-01-01  Alan Modra  <amodra@gmail.com>
 859
 860         Update year range in copyright notice of all files.
 861
 862 For older changes see ChangeLog-2019
 863 \f
 864 Copyright (C) 2020 Free Software Foundation, Inc.
 865
 866 Copying and distribution of this file, with or without modification,
 867 are permitted in any medium without royalty provided the copyright
 868 notice and this notice are preserved.
 869
 870 Local Variables:
 871 mode: change-log
 872 left-margin: 8
 873 fill-column: 74
 874 version-control: never
 875 End: