opcodes/ChangeLog

   1 2019-10-29  Nick Clifton  <nickc@redhat.com>
   2
   3         * d30v-dis.c (print_insn): Check that operand index is valid
   4         before attempting to access the operands array.
   5
   6 2019-10-29  Nick Clifton  <nickc@redhat.com>
   7
   8         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
   9         locating the bit to be tested.
  10
  11 2019-10-29  Nick Clifton  <nickc@redhat.com>
  12
  13         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
  14         values.
  15         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
  16         (print_insn_s12z):  Check for illegal size values.
  17
  18 2019-10-28  Nick Clifton  <nickc@redhat.com>
  19
  20         * csky-dis.c (csky_chars_to_number): Check for a negative
  21         count. Use an unsigned integer to construct the return value.
  22
  23 2019-10-28  Nick Clifton  <nickc@redhat.com>
  24
  25         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
  26         operand buffer.  Set value to 15 not 13.
  27         (get_register_operand): Use OPERAND_BUFFER_LEN.
  28         (get_indirect_operand): Likewise.
  29         (print_two_operand): Likewise.
  30         (print_three_operand): Likewise.
  31         (print_oar_insn): Likewise.
  32
  33 2019-10-28  Nick Clifton  <nickc@redhat.com>
  34
  35         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
  36         (bit_extract_simple): Likewise.
  37         (bit_copy): Likewise.
  38         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
  39         index_offset array are not accessed.
  40
  41 2019-10-28  Nick Clifton  <nickc@redhat.com>
  42
  43         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
  44         operand.
  45
  46 2019-10-25  Nick Clifton  <nickc@redhat.com>
  47
  48         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
  49         access to opcodes.op array element.
  50
  51 2019-10-23  Nick Clifton  <nickc@redhat.com>
  52
  53         * rx-dis.c (get_register_name): Fix spelling typo in error
  54         message.
  55         (get_condition_name, get_flag_name, get_double_register_name)
  56         (get_double_register_high_name, get_double_register_low_name)
  57         (get_double_control_register_name, get_double_condition_name)
  58         (get_opsize_name, get_size_name): Likewise.
  59
  60 2019-10-22  Nick Clifton  <nickc@redhat.com>
  61
  62         * rx-dis.c (get_size_name): New function.  Provides safe
  63         access to name array.
  64         (get_opsize_name): Likewise.
  65         (print_insn_rx): Use the accessor functions.
  66
  67 2019-10-16  Nick Clifton  <nickc@redhat.com>
  68
  69         * rx-dis.c (get_register_name): New function.  Provides safe
  70         access to name array.
  71         (get_condition_name, get_flag_name, get_double_register_name)
  72         (get_double_register_high_name, get_double_register_low_name)
  73         (get_double_control_register_name, get_double_condition_name):
  74         Likewise.
  75         (print_insn_rx): Use the accessor functions.
  76
  77 2019-10-09  Nick Clifton  <nickc@redhat.com>
  78
  79         PR 25041
  80         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
  81         instructions.
  82
  83 2019-10-07  Jan Beulich  <jbeulich@suse.com>
  84
  85         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
  86         (cmpsd): Likewise. Move EsSeg to other operand.
  87         * opcodes/i386-tbl.h: Re-generate.
  88
  89 2019-09-23  Alan Modra  <amodra@gmail.com>
  90
  91         * m68k-dis.c: Include cpu-m68k.h
  92
  93 2019-09-23  Alan Modra  <amodra@gmail.com>
  94
  95         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
  96         "elf/mips.h" earlier.
  97
  98 2018-09-20  Jan Beulich  <jbeulich@suse.com>
  99
 100         PR gas/25012
 101         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 102         with SReg operand.
 103         * i386-tbl.h: Re-generate.
 104
 105 2019-09-18  Alan Modra  <amodra@gmail.com>
 106
 107         * arc-ext.c: Update throughout for bfd section macro changes.
 108
 109 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 110
 111         * Makefile.in: Re-generate.
 112         * configure: Re-generate.
 113
 114 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 115
 116         * riscv-opc.c (riscv_opcodes): Change subset field
 117         to insn_class field for all instructions.
 118         (riscv_insn_types): Likewise.
 119
 120 2019-09-16  Phil Blundell  <pb@pbcl.net>
 121
 122         * configure: Regenerated.
 123
 124 2019-09-10  Miod Vallat  <miod@online.fr>
 125
 126         PR 24982
 127         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 128
 129 2019-09-09  Phil Blundell  <pb@pbcl.net>
 130
 131         binutils 2.33 branch created.
 132
 133 2019-09-03  Nick Clifton  <nickc@redhat.com>
 134
 135         PR 24961
 136         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 137         greater than zero before indexing via (bufcnt -1).
 138
 139 2019-09-03  Nick Clifton  <nickc@redhat.com>
 140
 141         PR 24958
 142         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 143         (MAX_SPEC_REG_NAME_LEN): Define.
 144         (struct mmix_dis_info): Use defined constants for array lengths.
 145         (get_reg_name): New function.
 146         (get_sprec_reg_name): New function.
 147         (print_insn_mmix): Use new functions.
 148
 149 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 150
 151         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 152         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 153         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 154
 155 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 156
 157         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 158         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 159         (aarch64_sys_reg_supported_p): Update checks for the above.
 160
 161 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 162
 163         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 164         cases MVE_SQRSHRL and MVE_UQRSHLL.
 165         (print_insn_mve): Add case for specifier 'k' to check
 166         specific bit of the instruction.
 167
 168 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 169
 170         PR 24854
 171         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 172         encountering an unknown machine type.
 173         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 174         cases return -1 rather than calling abort.
 175
 176 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 177
 178         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 179         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 180         IgnoreSize.
 181         * i386-tbl.h: Re-generate.
 182
 183 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 184
 185         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 186         instructions.
 187
 188 2019-07-30  Mel Chen <mel.chen@sifive.com>
 189
 190         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 191         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 192
 193         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 194         fscsr.
 195
 196 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 197
 198         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 199         and MPY class instructions.
 200         (parse_option): Add nps400 option.
 201         (print_arc_disassembler_options): Add nps400 info.
 202
 203 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 204
 205         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 206         (bspop): Likewise.
 207         (modapp): Likewise.
 208         * arc-opc.c (RAD_CHK): Add.
 209         * arc-tbl.h: Regenerate.
 210
 211 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 212
 213         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 214         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 215
 216 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 217
 218         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 219         instructions as UNPREDICTABLE.
 220
 221 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 222
 223         * bpf-desc.c: Regenerated.
 224
 225 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 226
 227         * i386-gen.c (static_assert): Define.
 228         (main): Use it.
 229         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 230         (Opcode_Modifier_Num): ... this.
 231         (Mem): Delete.
 232
 233 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 234
 235         * i386-gen.c (operand_types): Move RegMem ...
 236         (opcode_modifiers): ... here.
 237         * i386-opc.h (RegMem): Move to opcode modifer enum.
 238         (union i386_operand_type): Move regmem field ...
 239         (struct i386_opcode_modifier): ... here.
 240         * i386-opc.tbl (RegMem): Define.
 241         (mov, movq): Move RegMem on segment, control, debug, and test
 242         register flavors.
 243         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 244         to non-SSE2AVX flavor.
 245         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 246         Move RegMem on register only flavors. Drop IgnoreSize from
 247         legacy encoding flavors.
 248         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 249         flavors.
 250         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 251         register only flavors.
 252         (vmovd): Move RegMem and drop IgnoreSize on register only
 253         flavor. Change opcode and operand order to store form.
 254         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 255
 256 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 259         entries.
 260         * i386-opc.h (SReg2, SReg3): Replace by ...
 261         (SReg): ... this.
 262         (union i386_operand_type): Replace sreg fields.
 263         * i386-opc.tbl (mov, ): Use SReg.
 264         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 265         register flavors.
 266         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 267         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 268
 269 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 270
 271         * bpf-desc.c: Regenerate.
 272         * bpf-opc.c: Likewise.
 273         * bpf-opc.h: Likewise.
 274
 275 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 276
 277         * bpf-desc.c: Regenerate.
 278         * bpf-opc.c: Likewise.
 279
 280 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 281
 282         * arm-dis.c (print_insn_coprocessor): Rename index to
 283         index_operand.
 284
 285 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 286
 287         * riscv-opc.c (riscv_insn_types): Add r4 type.
 288
 289         * riscv-opc.c (riscv_insn_types): Add b and j type.
 290
 291         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 292         format for sb type and correct s type.
 293
 294 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 295
 296         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 297         SVE FMOV alias of FCPY.
 298
 299 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 300
 301         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 302         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 303
 304 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 305
 306         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 307         registers in an instruction prefixed by MOVPRFX.
 308
 309 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 310
 311         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 312         sve_size_13 icode to account for variant behaviour of
 313         pmull{t,b}.
 314         * aarch64-dis-2.c: Regenerate.
 315         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 316         sve_size_13 icode to account for variant behaviour of
 317         pmull{t,b}.
 318         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 319         (OP_SVE_VVV_Q_D): Add new qualifier.
 320         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 321         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 322         AES and those not.
 323
 324 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 325
 326         * opcodes/i386-gen.c (operand_type_init): Remove
 327         OPERAND_TYPE_VEC_IMM4 entry.
 328         (operand_types): Remove Vec_Imm4.
 329         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 330         (union i386_operand_type): Remove vec_imm4.
 331         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 332         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 333
 334 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 335
 336         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 337         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 338         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 339         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 340         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 341         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 342         * i386-tbl.h: Re-generate.
 343
 344 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 345
 346         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 347         register operands.
 348         * i386-tbl.h: Re-generate.
 349
 350 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 351
 352         * i386-opc.tbl (C): New.
 353         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 354         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 355         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 356         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 357         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 358         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 359         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 360         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 361         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 362         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 363         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 364         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 365         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 366         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 367         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 368         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 369         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 370         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 371         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 372         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 373         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 374         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 375         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 376         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 377         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 378         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 379         flavors.
 380         * i386-tbl.h: Re-generate.
 381
 382 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 383
 384         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 385         register operands.
 386         * i386-tbl.h: Re-generate.
 387
 388 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 389
 390         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 391         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 392         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 393         * i386-tbl.h: Re-generate.
 394
 395 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 396
 397         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 398         Disp8MemShift from register only templates.
 399         * i386-tbl.h: Re-generate.
 400
 401 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 402
 403         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 404         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 405         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 406         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 407         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 408         EVEX_W_0F11_P_3_M_1): Delete.
 409         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 410         EVEX_W_0F11_P_3): New.
 411         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 412         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 413         MOD_EVEX_0F11_PREFIX_3 table entries.
 414         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 415         PREFIX_EVEX_0F11 table entries.
 416         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 417         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 418         EVEX_W_0F11_P_3_M_{0,1} table entries.
 419
 420 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 421
 422         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 423         Delete.
 424
 425 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 426
 427         PR binutils/24719
 428         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 429         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 430         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 431         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 432         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 433         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 434         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 435         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 436         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 437         PREFIX_EVEX_0F38C6_REG_6 entries.
 438         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 439         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 440         EVEX_W_0F38C7_R_6_P_2 entries.
 441         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 442         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 443         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 444         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 445         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 446         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 447         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 448
 449 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 450
 451         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 452         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 453         VEX_LEN_0F2D_P_3): Delete.
 454         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 455         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 456         (prefix_table): ... here.
 457
 458 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 459
 460         * i386-dis.c (Iq): Delete.
 461         (Id): New.
 462         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 463         TBM insns.
 464         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 465         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 466         (OP_E_memory): Also honor needindex when deciding whether an
 467         address size prefix needs printing.
 468         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 469
 470 2019-06-26  Jim Wilson  <jimw@sifive.com>
 471
 472         PR binutils/24739
 473         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 474         Set info->display_endian to info->endian_code.
 475
 476 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 477
 478         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 479         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 480         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 481         OPERAND_TYPE_ACC64 entries.
 482         * i386-init.h: Re-generate.
 483
 484 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 485
 486         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 487         Delete.
 488         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 489         of dqa_mode.
 490         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 491         entries here.
 492         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 493         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 494
 495 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 496
 497         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 498         variables.
 499
 500 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 501
 502         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 503         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 504         movnti.
 505         * i386-opc.tbl (movnti): Add IgnoreSize.
 506         * i386-tbl.h: Re-generate.
 507
 508 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 509
 510         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 511         * i386-tbl.h: Re-generate.
 512
 513 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 514
 515         * i386-dis-evex.h: Break into ...
 516         * i386-dis-evex-len.h: New file.
 517         * i386-dis-evex-mod.h: Likewise.
 518         * i386-dis-evex-prefix.h: Likewise.
 519         * i386-dis-evex-reg.h: Likewise.
 520         * i386-dis-evex-w.h: Likewise.
 521         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 522         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 523         i386-dis-evex-mod.h.
 524
 525 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 526
 527         PR binutils/24700
 528         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 529         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 530         EVEX_W_0F385B_P_2.
 531         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 532         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 533         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 534         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 535         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 536         EVEX_LEN_0F385B_P_2_W_1.
 537         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 538         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 539         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 540         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 541         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 542         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 543         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 544         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 545         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 546         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 547
 548 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 549
 550         PR binutils/24691
 551         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 552         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 553         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 554         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 555         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 556         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 557         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 558         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 559         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 560         EVEX_LEN_0F3A43_P_2_W_1.
 561         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 562         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 563         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 564         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 565         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 566         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 567         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 568         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 569         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 570         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 571         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 572         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 573
 574 2019-06-14  Nick Clifton  <nickc@redhat.com>
 575
 576         * po/fr.po; Updated French translation.
 577
 578 2019-06-13  Stafford Horne  <shorne@gmail.com>
 579
 580         * or1k-asm.c: Regenerated.
 581         * or1k-desc.c: Regenerated.
 582         * or1k-desc.h: Regenerated.
 583         * or1k-dis.c: Regenerated.
 584         * or1k-ibld.c: Regenerated.
 585         * or1k-opc.c: Regenerated.
 586         * or1k-opc.h: Regenerated.
 587         * or1k-opinst.c: Regenerated.
 588
 589 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 590
 591         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 592
 593 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 594
 595         PR binutils/24633
 596         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 597         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 598         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 599         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 600         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 601         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 602         EVEX_LEN_0F3A1B_P_2_W_1.
 603         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 604         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 605         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 606         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 607         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 608         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 609         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 610         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 611
 612 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 613
 614         PR binutils/24626
 615         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 616         EVEX.vvvv when disassembling VEX and EVEX instructions.
 617         (OP_VEX): Set vex.register_specifier to 0 after readding
 618         vex.register_specifier.
 619         (OP_Vex_2src_1): Likewise.
 620         (OP_Vex_2src_2): Likewise.
 621         (OP_LWP_E): Likewise.
 622         (OP_EX_Vex): Don't check vex.register_specifier.
 623         (OP_XMM_Vex): Likewise.
 624
 625 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 626             Lili Cui  <lili.cui@intel.com>
 627
 628         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 629         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 630         instructions.
 631         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 632         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 633         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 634         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 635         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 636         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 637         * i386-init.h: Regenerated.
 638         * i386-tbl.h: Likewise.
 639
 640 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 641             Lili Cui  <lili.cui@intel.com>
 642
 643         * doc/c-i386.texi: Document enqcmd.
 644         * testsuite/gas/i386/enqcmd-intel.d: New file.
 645         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 646         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 647         * testsuite/gas/i386/enqcmd.d: Likewise.
 648         * testsuite/gas/i386/enqcmd.s: Likewise.
 649         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 650         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 651         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 652         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 653         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 654         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 655         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 656         and x86-64-enqcmd.
 657
 658 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 659
 660         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 661
 662 2019-06-03  Alan Modra  <amodra@gmail.com>
 663
 664         * ppc-dis.c (prefix_opcd_indices): Correct size.
 665
 666 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 667
 668         PR gas/24625
 669         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 670         Disp8ShiftVL.
 671         * i386-tbl.h: Regenerated.
 672
 673 2019-05-24  Alan Modra  <amodra@gmail.com>
 674
 675         * po/POTFILES.in: Regenerate.
 676
 677 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 678             Alan Modra  <amodra@gmail.com>
 679
 680         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 681         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 682         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 683         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 684         XTOP>): Define and add entries.
 685         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 686         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 687         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 688         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 689
 690 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 691             Alan Modra  <amodra@gmail.com>
 692
 693         * ppc-dis.c (ppc_opts): Add "future" entry.
 694         (PREFIX_OPCD_SEGS): Define.
 695         (prefix_opcd_indices): New array.
 696         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 697         (lookup_prefix): New function.
 698         (print_insn_powerpc): Handle 64-bit prefix instructions.
 699         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 700         (PMRR, POWERXX): Define.
 701         (prefix_opcodes): New instruction table.
 702         (prefix_num_opcodes): New constant.
 703
 704 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 705
 706         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 707         * configure: Regenerated.
 708         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 709         and cpu/bpf.opc.
 710         (HFILES): Add bpf-desc.h and bpf-opc.h.
 711         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 712         bpf-ibld.c and bpf-opc.c.
 713         (BPF_DEPS): Define.
 714         * Makefile.in: Regenerated.
 715         * disassemble.c (ARCH_bpf): Define.
 716         (disassembler): Add case for bfd_arch_bpf.
 717         (disassemble_init_for_target): Likewise.
 718         (enum epbf_isa_attr): Define.
 719         * disassemble.h: extern print_insn_bpf.
 720         * bpf-asm.c: Generated.
 721         * bpf-opc.h: Likewise.
 722         * bpf-opc.c: Likewise.
 723         * bpf-ibld.c: Likewise.
 724         * bpf-dis.c: Likewise.
 725         * bpf-desc.h: Likewise.
 726         * bpf-desc.c: Likewise.
 727
 728 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 729
 730         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 731         and VMSR with the new operands.
 732
 733 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 734
 735         * arm-dis.c (enum mve_instructions): New enum
 736         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 737         and cneg.
 738         (mve_opcodes): New instructions as above.
 739         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 740         csneg and csel.
 741         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 742
 743 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 744
 745         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 746         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 747         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 748         uqshl, urshrl and urshr.
 749         (is_mve_okay_in_it): Add new instructions to TRUE list.
 750         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 751         (print_insn_mve): Updated to accept new %j,
 752         %<bitfield>m and %<bitfield>n patterns.
 753
 754 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 755
 756         * mips-opc.c (mips_builtin_opcodes): Change source register
 757         constraint for DAUI.
 758
 759 2019-05-20  Nick Clifton  <nickc@redhat.com>
 760
 761         * po/fr.po: Updated French translation.
 762
 763 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 764             Michael Collison <michael.collison@arm.com>
 765
 766         * arm-dis.c (thumb32_opcodes): Add new instructions.
 767         (enum mve_instructions): Likewise.
 768         (enum mve_undefined): Add new reasons.
 769         (is_mve_encoding_conflict): Handle new instructions.
 770         (is_mve_undefined): Likewise.
 771         (is_mve_unpredictable): Likewise.
 772         (print_mve_undefined): Likewise.
 773         (print_mve_size): Likewise.
 774
 775 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 776             Michael Collison <michael.collison@arm.com>
 777
 778         * arm-dis.c (thumb32_opcodes): Add new instructions.
 779         (enum mve_instructions): Likewise.
 780         (is_mve_encoding_conflict): Handle new instructions.
 781         (is_mve_undefined): Likewise.
 782         (is_mve_unpredictable): Likewise.
 783         (print_mve_size): Likewise.
 784
 785 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 786             Michael Collison <michael.collison@arm.com>
 787
 788         * arm-dis.c (thumb32_opcodes): Add new instructions.
 789         (enum mve_instructions): Likewise.
 790         (is_mve_encoding_conflict): Likewise.
 791         (is_mve_unpredictable): Likewise.
 792         (print_mve_size): Likewise.
 793
 794 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 795             Michael Collison <michael.collison@arm.com>
 796
 797         * arm-dis.c (thumb32_opcodes): Add new instructions.
 798         (enum mve_instructions): Likewise.
 799         (is_mve_encoding_conflict): Handle new instructions.
 800         (is_mve_undefined): Likewise.
 801         (is_mve_unpredictable): Likewise.
 802         (print_mve_size): Likewise.
 803
 804 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 805             Michael Collison <michael.collison@arm.com>
 806
 807         * arm-dis.c (thumb32_opcodes): Add new instructions.
 808         (enum mve_instructions): Likewise.
 809         (is_mve_encoding_conflict): Handle new instructions.
 810         (is_mve_undefined): Likewise.
 811         (is_mve_unpredictable): Likewise.
 812         (print_mve_size): Likewise.
 813         (print_insn_mve): Likewise.
 814
 815 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 816             Michael Collison <michael.collison@arm.com>
 817
 818         * arm-dis.c (thumb32_opcodes): Add new instructions.
 819         (print_insn_thumb32): Handle new instructions.
 820
 821 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 822             Michael Collison <michael.collison@arm.com>
 823
 824         * arm-dis.c (enum mve_instructions): Add new instructions.
 825         (enum mve_undefined): Add new reasons.
 826         (is_mve_encoding_conflict): Handle new instructions.
 827         (is_mve_undefined): Likewise.
 828         (is_mve_unpredictable): Likewise.
 829         (print_mve_undefined): Likewise.
 830         (print_mve_size): Likewise.
 831         (print_mve_shift_n): Likewise.
 832         (print_insn_mve): Likewise.
 833
 834 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 835             Michael Collison <michael.collison@arm.com>
 836
 837         * arm-dis.c (enum mve_instructions): Add new instructions.
 838         (is_mve_encoding_conflict): Handle new instructions.
 839         (is_mve_unpredictable): Likewise.
 840         (print_mve_rotate): Likewise.
 841         (print_mve_size): Likewise.
 842         (print_insn_mve): Likewise.
 843
 844 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 845             Michael Collison <michael.collison@arm.com>
 846
 847         * arm-dis.c (enum mve_instructions): Add new instructions.
 848         (is_mve_encoding_conflict): Handle new instructions.
 849         (is_mve_unpredictable): Likewise.
 850         (print_mve_size): Likewise.
 851         (print_insn_mve): Likewise.
 852
 853 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 854             Michael Collison <michael.collison@arm.com>
 855
 856         * arm-dis.c (enum mve_instructions): Add new instructions.
 857         (enum mve_undefined): Add new reasons.
 858         (is_mve_encoding_conflict): Handle new instructions.
 859         (is_mve_undefined): Likewise.
 860         (is_mve_unpredictable): Likewise.
 861         (print_mve_undefined): Likewise.
 862         (print_mve_size): Likewise.
 863         (print_insn_mve): Likewise.
 864
 865 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 866             Michael Collison <michael.collison@arm.com>
 867
 868         * arm-dis.c (enum mve_instructions): Add new instructions.
 869         (is_mve_encoding_conflict): Handle new instructions.
 870         (is_mve_undefined): Likewise.
 871         (is_mve_unpredictable): Likewise.
 872         (print_mve_size): Likewise.
 873         (print_insn_mve): Likewise.
 874
 875 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 876             Michael Collison <michael.collison@arm.com>
 877
 878         * arm-dis.c (enum mve_instructions): Add new instructions.
 879         (enum mve_unpredictable): Add new reasons.
 880         (enum mve_undefined): Likewise.
 881         (is_mve_okay_in_it): Handle new isntructions.
 882         (is_mve_encoding_conflict): Likewise.
 883         (is_mve_undefined): Likewise.
 884         (is_mve_unpredictable): Likewise.
 885         (print_mve_vmov_index): Likewise.
 886         (print_simd_imm8): Likewise.
 887         (print_mve_undefined): Likewise.
 888         (print_mve_unpredictable): Likewise.
 889         (print_mve_size): Likewise.
 890         (print_insn_mve): Likewise.
 891
 892 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 893             Michael Collison <michael.collison@arm.com>
 894
 895         * arm-dis.c (enum mve_instructions): Add new instructions.
 896         (enum mve_unpredictable): Add new reasons.
 897         (enum mve_undefined): Likewise.
 898         (is_mve_encoding_conflict): Handle new instructions.
 899         (is_mve_undefined): Likewise.
 900         (is_mve_unpredictable): Likewise.
 901         (print_mve_undefined): Likewise.
 902         (print_mve_unpredictable): Likewise.
 903         (print_mve_rounding_mode): Likewise.
 904         (print_mve_vcvt_size): Likewise.
 905         (print_mve_size): Likewise.
 906         (print_insn_mve): Likewise.
 907
 908 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 909             Michael Collison <michael.collison@arm.com>
 910
 911         * arm-dis.c (enum mve_instructions): Add new instructions.
 912         (enum mve_unpredictable): Add new reasons.
 913         (enum mve_undefined): Likewise.
 914         (is_mve_undefined): Handle new instructions.
 915         (is_mve_unpredictable): Likewise.
 916         (print_mve_undefined): Likewise.
 917         (print_mve_unpredictable): Likewise.
 918         (print_mve_size): Likewise.
 919         (print_insn_mve): Likewise.
 920
 921 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 922             Michael Collison <michael.collison@arm.com>
 923
 924         * arm-dis.c (enum mve_instructions): Add new instructions.
 925         (enum mve_undefined): Add new reasons.
 926         (insns): Add new instructions.
 927         (is_mve_encoding_conflict):
 928         (print_mve_vld_str_addr): New print function.
 929         (is_mve_undefined): Handle new instructions.
 930         (is_mve_unpredictable): Likewise.
 931         (print_mve_undefined): Likewise.
 932         (print_mve_size): Likewise.
 933         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 934         (print_insn_mve):  Handle new operands.
 935
 936 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 937             Michael Collison <michael.collison@arm.com>
 938
 939         * arm-dis.c (enum mve_instructions): Add new instructions.
 940         (enum mve_unpredictable): Add new reasons.
 941         (is_mve_encoding_conflict): Handle new instructions.
 942         (is_mve_unpredictable): Likewise.
 943         (mve_opcodes): Add new instructions.
 944         (print_mve_unpredictable): Handle new reasons.
 945         (print_mve_register_blocks): New print function.
 946         (print_mve_size): Handle new instructions.
 947         (print_insn_mve): Likewise.
 948
 949 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 950             Michael Collison <michael.collison@arm.com>
 951
 952         * arm-dis.c (enum mve_instructions): Add new instructions.
 953         (enum mve_unpredictable): Add new reasons.
 954         (enum mve_undefined): Likewise.
 955         (is_mve_encoding_conflict): Handle new instructions.
 956         (is_mve_undefined): Likewise.
 957         (is_mve_unpredictable): Likewise.
 958         (coprocessor_opcodes): Move NEON VDUP from here...
 959         (neon_opcodes): ... to here.
 960         (mve_opcodes): Add new instructions.
 961         (print_mve_undefined):  Handle new reasons.
 962         (print_mve_unpredictable): Likewise.
 963         (print_mve_size): Handle new instructions.
 964         (print_insn_neon): Handle vdup.
 965         (print_insn_mve): Handle new operands.
 966
 967 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 968             Michael Collison <michael.collison@arm.com>
 969
 970         * arm-dis.c (enum mve_instructions): Add new instructions.
 971         (enum mve_unpredictable): Add new values.
 972         (mve_opcodes): Add new instructions.
 973         (vec_condnames): New array with vector conditions.
 974         (mve_predicatenames): New array with predicate suffixes.
 975         (mve_vec_sizename): New array with vector sizes.
 976         (enum vpt_pred_state): New enum with vector predication states.
 977         (struct vpt_block): New struct type for vpt blocks.
 978         (vpt_block_state): Global struct to keep track of state.
 979         (mve_extract_pred_mask): New helper function.
 980         (num_instructions_vpt_block): Likewise.
 981         (mark_outside_vpt_block): Likewise.
 982         (mark_inside_vpt_block): Likewise.
 983         (invert_next_predicate_state): Likewise.
 984         (update_next_predicate_state): Likewise.
 985         (update_vpt_block_state): Likewise.
 986         (is_vpt_instruction): Likewise.
 987         (is_mve_encoding_conflict): Add entries for new instructions.
 988         (is_mve_unpredictable): Likewise.
 989         (print_mve_unpredictable): Handle new cases.
 990         (print_instruction_predicate): Likewise.
 991         (print_mve_size): New function.
 992         (print_vec_condition): New function.
 993         (print_insn_mve): Handle vpt blocks and new print operands.
 994
 995 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 996
 997         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 998         8, 14 and 15 for Armv8.1-M Mainline.
 999
1000 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1001             Michael Collison <michael.collison@arm.com>
1002
1003         * arm-dis.c (enum mve_instructions): New enum.
1004         (enum mve_unpredictable): Likewise.
1005         (enum mve_undefined): Likewise.
1006         (struct mopcode32): New struct.
1007         (is_mve_okay_in_it): New function.
1008         (is_mve_architecture): Likewise.
1009         (arm_decode_field): Likewise.
1010         (arm_decode_field_multiple): Likewise.
1011         (is_mve_encoding_conflict): Likewise.
1012         (is_mve_undefined): Likewise.
1013         (is_mve_unpredictable): Likewise.
1014         (print_mve_undefined): Likewise.
1015         (print_mve_unpredictable): Likewise.
1016         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1017         (print_insn_mve): New function.
1018         (print_insn_thumb32): Handle MVE architecture.
1019         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1020
1021 2019-05-10  Nick Clifton  <nickc@redhat.com>
1022
1023         PR 24538
1024         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1025         end of the table prematurely.
1026
1027 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1028
1029         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1030         macros for R6.
1031
1032 2019-05-11  Alan Modra  <amodra@gmail.com>
1033
1034         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1035         when -Mraw is in effect.
1036
1037 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1038
1039         * aarch64-dis-2.c: Regenerate.
1040         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1041         (OP_SVE_BBB): New variant set.
1042         (OP_SVE_DDDD): New variant set.
1043         (OP_SVE_HHH): New variant set.
1044         (OP_SVE_HHHU): New variant set.
1045         (OP_SVE_SSS): New variant set.
1046         (OP_SVE_SSSU): New variant set.
1047         (OP_SVE_SHH): New variant set.
1048         (OP_SVE_SBBU): New variant set.
1049         (OP_SVE_DSS): New variant set.
1050         (OP_SVE_DHHU): New variant set.
1051         (OP_SVE_VMV_HSD_BHS): New variant set.
1052         (OP_SVE_VVU_HSD_BHS): New variant set.
1053         (OP_SVE_VVVU_SD_BH): New variant set.
1054         (OP_SVE_VVVU_BHSD): New variant set.
1055         (OP_SVE_VVV_QHD_DBS): New variant set.
1056         (OP_SVE_VVV_HSD_BHS): New variant set.
1057         (OP_SVE_VVV_HSD_BHS2): New variant set.
1058         (OP_SVE_VVV_BHS_HSD): New variant set.
1059         (OP_SVE_VV_BHS_HSD): New variant set.
1060         (OP_SVE_VVV_SD): New variant set.
1061         (OP_SVE_VVU_BHS_HSD): New variant set.
1062         (OP_SVE_VZVV_SD): New variant set.
1063         (OP_SVE_VZVV_BH): New variant set.
1064         (OP_SVE_VZV_SD): New variant set.
1065         (aarch64_opcode_table): Add sve2 instructions.
1066
1067 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1068
1069         * aarch64-asm-2.c: Regenerated.
1070         * aarch64-dis-2.c: Regenerated.
1071         * aarch64-opc-2.c: Regenerated.
1072         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1073         for SVE_SHLIMM_UNPRED_22.
1074         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1075         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1076         operand.
1077
1078 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1079
1080         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1081         sve_size_tsz_bhs iclass encode.
1082         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1083         sve_size_tsz_bhs iclass decode.
1084
1085 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1086
1087         * aarch64-asm-2.c: Regenerated.
1088         * aarch64-dis-2.c: Regenerated.
1089         * aarch64-opc-2.c: Regenerated.
1090         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1091         for SVE_Zm4_11_INDEX.
1092         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1093         (fields): Handle SVE_i2h field.
1094         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1095         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1096
1097 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1098
1099         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1100         sve_shift_tsz_bhsd iclass encode.
1101         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1102         sve_shift_tsz_bhsd iclass decode.
1103
1104 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1105
1106         * aarch64-asm-2.c: Regenerated.
1107         * aarch64-dis-2.c: Regenerated.
1108         * aarch64-opc-2.c: Regenerated.
1109         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1110         (aarch64_encode_variant_using_iclass): Handle
1111         sve_shift_tsz_hsd iclass encode.
1112         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1113         sve_shift_tsz_hsd iclass decode.
1114         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1115         for SVE_SHRIMM_UNPRED_22.
1116         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1117         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1118         operand.
1119
1120 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1121
1122         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1123         sve_size_013 iclass encode.
1124         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1125         sve_size_013 iclass decode.
1126
1127 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1128
1129         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1130         sve_size_bh iclass encode.
1131         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1132         sve_size_bh iclass decode.
1133
1134 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1135
1136         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1137         sve_size_sd2 iclass encode.
1138         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1139         sve_size_sd2 iclass decode.
1140         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1141         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1142
1143 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1144
1145         * aarch64-asm-2.c: Regenerated.
1146         * aarch64-dis-2.c: Regenerated.
1147         * aarch64-opc-2.c: Regenerated.
1148         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1149         for SVE_ADDR_ZX.
1150         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1151         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1152
1153 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1154
1155         * aarch64-asm-2.c: Regenerated.
1156         * aarch64-dis-2.c: Regenerated.
1157         * aarch64-opc-2.c: Regenerated.
1158         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1159         for SVE_Zm3_11_INDEX.
1160         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1161         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1162         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1163         fields.
1164         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1165
1166 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1167
1168         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1169         sve_size_hsd2 iclass encode.
1170         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1171         sve_size_hsd2 iclass decode.
1172         * aarch64-opc.c (fields): Handle SVE_size field.
1173         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1174
1175 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1176
1177         * aarch64-asm-2.c: Regenerated.
1178         * aarch64-dis-2.c: Regenerated.
1179         * aarch64-opc-2.c: Regenerated.
1180         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1181         for SVE_IMM_ROT3.
1182         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1183         (fields): Handle SVE_rot3 field.
1184         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1185         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1186
1187 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1188
1189         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1190         instructions.
1191
1192 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1193
1194         * aarch64-tbl.h
1195         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1196         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1197         aarch64_feature_sve2bitperm): New feature sets.
1198         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1199         for feature set addresses.
1200         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1201         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1202
1203 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1204             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1205
1206         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1207         argument and set ASE_EVA_R6 appropriately.
1208         (set_default_mips_dis_options): Pass ISA to above.
1209         (parse_mips_dis_option): Likewise.
1210         * mips-opc.c (EVAR6): New macro.
1211         (mips_builtin_opcodes): Add llwpe, scwpe.
1212
1213 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1214
1215         * aarch64-asm-2.c: Regenerated.
1216         * aarch64-dis-2.c: Regenerated.
1217         * aarch64-opc-2.c: Regenerated.
1218         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1219         AARCH64_OPND_TME_UIMM16.
1220         (aarch64_print_operand): Likewise.
1221         * aarch64-tbl.h (QL_IMM_NIL): New.
1222         (TME): New.
1223         (_TME_INSN): New.
1224         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1225
1226 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1227
1228         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1229
1230 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1231             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1232
1233         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1234
1235 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1236
1237         * s12z-opc.h: Add extern "C" bracketing to help
1238         users who wish to use this interface in c++ code.
1239
1240 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1241
1242         * s12z-opc.c (bm_decode): Handle bit map operations with the
1243         "reserved0" mode.
1244
1245 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1246
1247         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1248         specifier.  Add entries for VLDR and VSTR of system registers.
1249         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1250         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1251         of %J and %K format specifier.
1252
1253 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1254
1255         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1256         Add new entries for VSCCLRM instruction.
1257         (print_insn_coprocessor): Handle new %C format control code.
1258
1259 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1260
1261         * arm-dis.c (enum isa): New enum.
1262         (struct sopcode32): New structure.
1263         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1264         set isa field of all current entries to ANY.
1265         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1266         Only match an entry if its isa field allows the current mode.
1267
1268 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1269
1270         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1271         CLRM.
1272         (print_insn_thumb32): Add logic to print %n CLRM register list.
1273
1274 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1275
1276         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1277         and %Q patterns.
1278
1279 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1280
1281         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1282         (print_insn_thumb32): Edit the switch case for %Z.
1283
1284 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1285
1286         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1287
1288 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1289
1290         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1291
1292 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1293
1294         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1295
1296 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1297
1298         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1299         Arm register with r13 and r15 unpredictable.
1300         (thumb32_opcodes): New instructions for bfx and bflx.
1301
1302 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1303
1304         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1305
1306 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1307
1308         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1309
1310 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1311
1312         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1313
1314 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1315
1316         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1317
1318 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1319
1320         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1321         "optr". ("operator" is a reserved word in c++).
1322
1323 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1324
1325         * aarch64-opc.c (aarch64_print_operand): Add case for
1326         AARCH64_OPND_Rt_SP.
1327         (verify_constraints): Likewise.
1328         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1329         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1330         to accept Rt|SP as first operand.
1331         (AARCH64_OPERANDS): Add new Rt_SP.
1332         * aarch64-asm-2.c: Regenerated.
1333         * aarch64-dis-2.c: Regenerated.
1334         * aarch64-opc-2.c: Regenerated.
1335
1336 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1337
1338         * aarch64-asm-2.c: Regenerated.
1339         * aarch64-dis-2.c: Likewise.
1340         * aarch64-opc-2.c: Likewise.
1341         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1342
1343 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1344
1345         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1346
1347 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1348
1349         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1350         * i386-init.h: Regenerated.
1351
1352 2019-04-07  Alan Modra  <amodra@gmail.com>
1353
1354         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1355         op_separator to control printing of spaces, comma and parens
1356         rather than need_comma, need_paren and spaces vars.
1357
1358 2019-04-07  Alan Modra  <amodra@gmail.com>
1359
1360         PR 24421
1361         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1362         (print_insn_neon, print_insn_arm): Likewise.
1363
1364 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1365
1366         * i386-dis-evex.h (evex_table): Updated to support BF16
1367         instructions.
1368         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1369         and EVEX_W_0F3872_P_3.
1370         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1371         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1372         * i386-opc.h (enum): Add CpuAVX512_BF16.
1373         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1374         * i386-opc.tbl: Add AVX512 BF16 instructions.
1375         * i386-init.h: Regenerated.
1376         * i386-tbl.h: Likewise.
1377
1378 2019-04-05  Alan Modra  <amodra@gmail.com>
1379
1380         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1381         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1382         to favour printing of "-" branch hint when using the "y" bit.
1383         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1384
1385 2019-04-05  Alan Modra  <amodra@gmail.com>
1386
1387         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1388         opcode until first operand is output.
1389
1390 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1391
1392         PR gas/24349
1393         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1394         (valid_bo_post_v2): Add support for 'at' branch hints.
1395         (insert_bo): Only error on branch on ctr.
1396         (get_bo_hint_mask): New function.
1397         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1398         for inserting 'at' branch hints.
1399         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1400         for extracting 'at' branch hints.
1401         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1402         (BOE): Delete operand.
1403         (BOM, BOP): New operands.
1404         (RM): Update value.
1405         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1406         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1407         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1408         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1409         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1410         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1411         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1412         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1413         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1414         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1415         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1416         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1417         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1418         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1419         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1420         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1421         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1422         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1423         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1424         bttarl+>: New extended mnemonics.
1425
1426 2019-03-28  Alan Modra  <amodra@gmail.com>
1427
1428         PR 24390
1429         * ppc-opc.c (BTF): Define.
1430         (powerpc_opcodes): Use for mtfsb*.
1431         * ppc-dis.c (print_insn_powerpc): Print fields with both
1432         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1433
1434 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1435
1436         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1437         (mapping_symbol_for_insn): Implement new algorithm.
1438         (print_insn): Remove duplicate code.
1439
1440 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1441
1442         * aarch64-dis.c (print_insn_aarch64):
1443         Implement override.
1444
1445 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1446
1447         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1448         order.
1449
1450 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1451
1452         * aarch64-dis.c (last_stop_offset): New.
1453         (print_insn_aarch64): Use stop_offset.
1454
1455 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1456
1457         PR gas/24359
1458         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1459         CPU_ANY_AVX2_FLAGS.
1460         * i386-init.h: Regenerated.
1461
1462 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1463
1464         PR gas/24348
1465         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1466         vmovdqu16, vmovdqu32 and vmovdqu64.
1467         * i386-tbl.h: Regenerated.
1468
1469 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1470
1471         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1472         from vstrszb, vstrszh, and vstrszf.
1473
1474 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1475
1476         * s390-opc.txt: Add instruction descriptions.
1477
1478 2019-02-08  Jim Wilson  <jimw@sifive.com>
1479
1480         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1481         <bne>: Likewise.
1482
1483 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1484
1485         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1486
1487 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1488
1489         PR binutils/23212
1490         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1491         * aarch64-opc.c (verify_elem_sd): New.
1492         (fields): Add FLD_sz entr.
1493         * aarch64-tbl.h (_SIMD_INSN): New.
1494         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1495         fmulx scalar and vector by element isns.
1496
1497 2019-02-07  Nick Clifton  <nickc@redhat.com>
1498
1499         * po/sv.po: Updated Swedish translation.
1500
1501 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1502
1503         * s390-mkopc.c (main): Accept arch13 as cpu string.
1504         * s390-opc.c: Add new instruction formats and instruction opcode
1505         masks.
1506         * s390-opc.txt: Add new arch13 instructions.
1507
1508 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1509
1510         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1511         (aarch64_opcode): Change encoding for stg, stzg
1512         st2g and st2zg.
1513         * aarch64-asm-2.c: Regenerated.
1514         * aarch64-dis-2.c: Regenerated.
1515         * aarch64-opc-2.c: Regenerated.
1516
1517 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1518
1519         * aarch64-asm-2.c: Regenerated.
1520         * aarch64-dis-2.c: Likewise.
1521         * aarch64-opc-2.c: Likewise.
1522         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1523
1524 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1525             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1526
1527         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1528         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1529         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1530         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1531         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1532         case for ldstgv_indexed.
1533         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1534         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1535         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1536         * aarch64-asm-2.c: Regenerated.
1537         * aarch64-dis-2.c: Regenerated.
1538         * aarch64-opc-2.c: Regenerated.
1539
1540 2019-01-23  Nick Clifton  <nickc@redhat.com>
1541
1542         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1543
1544 2019-01-21  Nick Clifton  <nickc@redhat.com>
1545
1546         * po/de.po: Updated German translation.
1547         * po/uk.po: Updated Ukranian translation.
1548
1549 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1550         * mips-dis.c (mips_arch_choices): Fix typo in
1551         gs464, gs464e and gs264e descriptors.
1552
1553 2019-01-19  Nick Clifton  <nickc@redhat.com>
1554
1555         * configure: Regenerate.
1556         * po/opcodes.pot: Regenerate.
1557
1558 2018-06-24  Nick Clifton  <nickc@redhat.com>
1559
1560         2.32 branch created.
1561
1562 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1563
1564         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1565         if it is null.
1566         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1567         zero.
1568
1569 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1570
1571         * configure: Regenerate.
1572
1573 2019-01-07  Alan Modra  <amodra@gmail.com>
1574
1575         * configure: Regenerate.
1576         * po/POTFILES.in: Regenerate.
1577
1578 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1579
1580         * s12z-opc.c: New file.
1581         * s12z-opc.h: New file.
1582         * s12z-dis.c: Removed all code not directly related to display
1583         of instructions.  Used the interface provided by the new files
1584         instead.
1585         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1586         * Makefile.in: Regenerate.
1587         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1588         * configure: Regenerate.
1589
1590 2019-01-01  Alan Modra  <amodra@gmail.com>
1591
1592         Update year range in copyright notice of all files.
1593
1594 For older changes see ChangeLog-2018
1595 \f
1596 Copyright (C) 2019 Free Software Foundation, Inc.
1597
1598 Copying and distribution of this file, with or without modification,
1599 are permitted in any medium without royalty provided the copyright
1600 notice and this notice are preserved.
1601
1602 Local Variables:
1603 mode: change-log
1604 left-margin: 8
1605 fill-column: 74
1606 version-control: never
1607 End: