opcodes/aarch64-asm.h

   1 /* aarch64-asm.h -- Header file for aarch64-asm.c and aarch64-asm-2.c.
   2    Copyright (C) 2012-2020 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef OPCODES_AARCH64_ASM_H
  22 #define OPCODES_AARCH64_ASM_H
  23
  24 #include "aarch64-opc.h"
  25
  26 /* Given OPCODE, return the opcode entry that OPCODE aliases to, e.g.
  27    given LSL, return UBFM.  */
  28
  29 const aarch64_opcode* aarch64_find_real_opcode (const aarch64_opcode *);
  30
  31 /* Switch-table-based high-level operand inserter.  */
  32
  33 bfd_boolean aarch64_insert_operand (const aarch64_operand *,
  34                                     const aarch64_opnd_info *, aarch64_insn *,
  35                                     const aarch64_inst *,
  36                                     aarch64_operand_error *);
  37
  38 /* Operand inserters.  */
  39
  40 #define AARCH64_DECL_OPD_INSERTER(x)    \
  41   bfd_boolean aarch64_##x (const aarch64_operand *, const aarch64_opnd_info *, \
  42                            aarch64_insn *, const aarch64_inst *, \
  43                            aarch64_operand_error *)
  44
  45 AARCH64_DECL_OPD_INSERTER (ins_none);
  46 AARCH64_DECL_OPD_INSERTER (ins_regno);
  47 AARCH64_DECL_OPD_INSERTER (ins_reglane);
  48 AARCH64_DECL_OPD_INSERTER (ins_reglist);
  49 AARCH64_DECL_OPD_INSERTER (ins_ldst_reglist);
  50 AARCH64_DECL_OPD_INSERTER (ins_ldst_reglist_r);
  51 AARCH64_DECL_OPD_INSERTER (ins_ldst_elemlist);
  52 AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_shift);
  53 AARCH64_DECL_OPD_INSERTER (ins_imm);
  54 AARCH64_DECL_OPD_INSERTER (ins_imm_half);
  55 AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_modified);
  56 AARCH64_DECL_OPD_INSERTER (ins_fpimm);
  57 AARCH64_DECL_OPD_INSERTER (ins_fbits);
  58 AARCH64_DECL_OPD_INSERTER (ins_aimm);
  59 AARCH64_DECL_OPD_INSERTER (ins_limm);
  60 AARCH64_DECL_OPD_INSERTER (ins_inv_limm);
  61 AARCH64_DECL_OPD_INSERTER (ins_ft);
  62 AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
  63 AARCH64_DECL_OPD_INSERTER (ins_addr_offset);
  64 AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
  65 AARCH64_DECL_OPD_INSERTER (ins_addr_simm);
  66 AARCH64_DECL_OPD_INSERTER (ins_addr_simm10);
  67 AARCH64_DECL_OPD_INSERTER (ins_addr_uimm12);
  68 AARCH64_DECL_OPD_INSERTER (ins_simd_addr_post);
  69 AARCH64_DECL_OPD_INSERTER (ins_cond);
  70 AARCH64_DECL_OPD_INSERTER (ins_sysreg);
  71 AARCH64_DECL_OPD_INSERTER (ins_pstatefield);
  72 AARCH64_DECL_OPD_INSERTER (ins_sysins_op);
  73 AARCH64_DECL_OPD_INSERTER (ins_barrier);
  74 AARCH64_DECL_OPD_INSERTER (ins_hint);
  75 AARCH64_DECL_OPD_INSERTER (ins_prfop);
  76 AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
  77 AARCH64_DECL_OPD_INSERTER (ins_reg_shifted);
  78 AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4);
  79 AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4xvl);
  80 AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s6xvl);
  81 AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s9xvl);
  82 AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_u6);
  83 AARCH64_DECL_OPD_INSERTER (ins_sve_addr_rr_lsl);
  84 AARCH64_DECL_OPD_INSERTER (ins_sve_addr_rz_xtw);
  85 AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zi_u5);
  86 AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_lsl);
  87 AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_sxtw);
  88 AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_uxtw);
  89 AARCH64_DECL_OPD_INSERTER (ins_sve_aimm);
  90 AARCH64_DECL_OPD_INSERTER (ins_sve_asimm);
  91 AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_one);
  92 AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_two);
  93 AARCH64_DECL_OPD_INSERTER (ins_sve_float_zero_one);
  94 AARCH64_DECL_OPD_INSERTER (ins_sve_index);
  95 AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov);
  96 AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index);
  97 AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
  98 AARCH64_DECL_OPD_INSERTER (ins_sve_scale);
  99 AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
 100 AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm);
 101 AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1);
 102 AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2);
 103
 104 #undef AARCH64_DECL_OPD_INSERTER
 105
 106 #endif /* OPCODES_AARCH64_ASM_H */