opcodes/arc-nps400-tbl.h

   1 /****                  Bit Manipulation Instructions                  ****/
   2
   3 /* movl<.cl> */
   4 { "movh", 0x48080000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }},
   5 { "movh", 0x48180000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }},
   6
   7 /* movl<.cl> */
   8 { "movl", 0x48090000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }},
   9 { "movl", 0x48190000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }},
  10
  11 /* movb<.f><.cl> */
  12 { "movb", 0x48010000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
  13 { "movb", 0x48018000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }},
  14
  15 /* movbi<.f><.cl> */
  16 { "movbi", 0x480f0000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_R_SRC1, NPS_BITOP_UIMM8, NPS_BITOP_DST_POS, NPS_BITOP_SIZE_2B  }, { C_NPS_F }},
  17 { "movbi", 0x480f8000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_BITOP_UIMM8, NPS_BITOP_DST_POS, NPS_BITOP_SIZE_2B  }, { C_NPS_F, C_NPS_CL }},
  18
  19 /* decode1<.f> */
  20 { "decode1", 0x48038040, 0xf80f83e0, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
  21
  22 /* decode1.cl<.f> */
  23 { "decode1", 0x48038060, 0xf80803e0, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS_SZ }, { C_NPS_CL, C_NPS_F }},
  24
  25 /* fbset<.f> */
  26 { "fbset", 0x48038000, 0xf80f83e0, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
  27
  28 /* fbclr<.f> */
  29 { "fbclr", 0x48030000, 0xf80f83e0, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
  30
  31 /* encode0<.f> */
  32 { "encode0", 0x48040000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
  33
  34 /* encode1<.f> */
  35 { "encode1", 0x48048000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
  36
  37 /* mrgb - 48 bit instruction, see arc_long_opcodes in arc-opc.c.  */
  38 /* mrgb.cl - 48 bit instruction, see arc_long_opcodes in arc-opc.c.  */
  39 /* mov2b - 48 bit instruction, see arc_long_opcodes in arc-opc.c.  */
  40 /* mov2b.cl - 48 bit instruction, see arc_long_opcodes in arc-opc.c.  */
  41 /* ext4 - 48 bit instruction, see arc_long_opcodes in arc-opc.c.  */
  42 /* ext4.cl - 48 bit instruction, see arc_long_opcodes in arc-opc.c.  */
  43 /* ins4 - 48 bit instruction, see arc_long_opcodes in arc-opc.c.  */
  44 /* ins4.cl - 48 bit instruction, see arc_long_opcodes in arc-opc.c.  */
  45 /* mov3b - 64 bit instruction, see arc_long_opcodes in arc-opc.c.  */
  46 /* mov4b - 64 bit instruction, see arc_long_opcodes in arc-opc.c.  */
  47 /* mov3bcl - 64 bit instruction, see arc_long_opcodes in arc-opc.c.  */
  48 /* mov4bcl - 64 bit instruction, see arc_long_opcodes in arc-opc.c.  */
  49 /* mov3b.cl - 64 bit instruction, see arc_long_opcodes in arc-opc.c.  */
  50 /* mov4b.cl - 64 bit instruction, see arc_long_opcodes in arc-opc.c.  */
  51
  52 /* rflt a,b,c   00111bbb00101110FBBBCCCCCCAAAAAA */
  53 { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }},
  54
  55 /* rflt a,limm,c   0011111000101110F111CCCCCCAAAAAA */
  56 { "rflt", 0x3e2e7000, 0xfffff000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, RC }, { 0 }},
  57
  58 /* rflt a,b,u6   00111bbb01101110FBBBuuuuuuAAAAAA */
  59 { "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }},
  60
  61 /* rflt 0,b,c   00111bbb00101110FBBBCCCCCC111110 */
  62 { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }},
  63
  64 /* rflt 0,limm,c   0011111000101110F111CCCCCC111110 */
  65 { "rflt", 0x3e2e703e, 0xfffff03f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, RC }, { 0 }},
  66
  67 /* rflt 0,b,u6   00111bbb01101110FBBBuuuuuu111110 */
  68 { "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }},
  69
  70 /* rflt 0,b,limm   00111bbb00101110FBBB111110111110 */
  71 { "rflt", 0x382e0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { 0 }},
  72
  73 /* rflt a,b,limm   00111bbb00101110FBBB111110AAAAAA */
  74 { "rflt", 0x382e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { 0 }},
  75
  76 /* rflt a,limm,limm    0011111000101110F111111110AAAAAA */
  77 { "rflt", 0x3e2e7f80, 0xffffffc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, LIMMdup }, { 0 }},
  78
  79 /* rflt a,limm,u6   0011111001101110F111uuuuuuAAAAAA */
  80 { "rflt", 0x3e6e7000, 0xfffff000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, NPS_RFLT_UIMM6 }, { 0 }},
  81
  82 /* rflt 0,limm,u6   0011111001101110F111uuuuuu111110 */
  83 { "rflt", 0x3e6e703e, 0xfffff03f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, NPS_RFLT_UIMM6 }, { 0 }},
  84
  85 /* crc16<.r> a,b,c  00111bbb00110011RBBBCCCCCCAAAAAA */
  86 { "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }},
  87
  88 /* crc16<.r> a,limm,c  0011111000110011R111CCCCCCAAAAAA */
  89 { "crc16", 0x3e337000, 0xffff7000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, RC }, { C_NPS_R }},
  90
  91 /* crc16<.r> a,b,u6  00111bbb01110011RBBBuuuuuuAAAAAA */
  92 { "crc16", 0x38730000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, UIMM6_20 }, { C_NPS_R }},
  93
  94 /* crc16<.r> 0,b,c  00111bbb00110011RBBBCCCCCC111110 */
  95 { "crc16", 0x3833003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { C_NPS_R }},
  96
  97 /* crc16<.r> 0,limm,c  0011111000110011R111CCCCCC111110 */
  98 { "crc16", 0x3e33703e, 0xffff703f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, RC }, { C_NPS_R }},
  99
 100 /* crc16<.r> 0,b,u6  00111bbb01110011RBBBuuuuuu111110 */
 101 { "crc16", 0x3873003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, UIMM6_20 }, { C_NPS_R }},
 102
 103 /* crc16<.r> 0,b,limm  00111bbb00110011RBBB111110111110 */
 104 { "crc16", 0x38330fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { C_NPS_R }},
 105
 106 /* crc16<.r> a,b,limm  00111bbb00110011RBBB111110AAAAAA */
 107 { "crc16", 0x38330f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { C_NPS_R }},
 108
 109 /* crc16<.r> a,limm,limm  0011111000110011R111111110AAAAAA */
 110 { "crc16", 0x3e337f80, 0xffff7fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, LIMMdup }, { C_NPS_R }},
 111
 112 /* crc16<.r> a,limm,u6  0011111001110011R111uuuuuuAAAAAA */
 113 { "crc16", 0x3e737000, 0xffff7000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, UIMM6_20 }, { C_NPS_R }},
 114
 115 /* crc16<.r> 0,limm,u6  0011111001110011R111uuuuuu111110 */
 116 { "crc16", 0x3e73703e, 0xffff703f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }},
 117
 118 /* crc32<.r> a,b,c              00111 bbb 00 110100 R BBB CCCCCC AAAAAA */
 119 { "crc32", 0x38340000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }},
 120
 121 /* crc32<.r> a,limm,c           00111 110 00 110100 R 111 CCCCCC AAAAAA */
 122 { "crc32", 0x3e347000, 0xffff7000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, RC }, { C_NPS_R }},
 123
 124 /* crc32<.r> a,b,u6             00111 bbb 01 110100 R BBB uuuuuu AAAAAA */
 125 { "crc32", 0x38740000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, UIMM6_20 }, { C_NPS_R }},
 126
 127 /* crc32<.r> 0,b,c              00111 bbb 00 110100 R BBB CCCCCC 111110 */
 128 { "crc32", 0x3834003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { C_NPS_R }},
 129
 130 /* crc32<.r> 0,limm,c           00111 110 00 110100 R 111 CCCCCC 111110 */
 131 { "crc32", 0x3e34703e, 0xffff703f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, RC }, { C_NPS_R }},
 132
 133 /* crc32<.r> 0,b,u6             00111 bbb 01 110100 R BBB uuuuuu 111110 */
 134 { "crc32", 0x3874003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, UIMM6_20 }, { C_NPS_R }},
 135
 136 /* crc32<.r> 0,b,limm           00111 bbb 00 110100 R BBB 111110 111110 */
 137 { "crc32", 0x38340fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { C_NPS_R }},
 138
 139 /* crc32<.r> a,b,limm           00111 bbb 00 110100 R BBB 111110 AAAAAA */
 140 { "crc32", 0x38340f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { C_NPS_R }},
 141
 142 /* crc32<.r> a,limm,limm        00111 110 00 110100 R 111 111110 AAAAAA */
 143 { "crc32", 0x3e347f80, 0xffff7fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, LIMMdup }, { C_NPS_R }},
 144
 145 /* crc32<.r> a,limm,u6          00111 110 01 110100 R 111 uuuuuu AAAAAA */
 146 { "crc32", 0x3e747000, 0xffff7000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, UIMM6_20 }, { C_NPS_R }},
 147
 148 /* crc32<.r> 0,limm,u6          00111 110 01 110100 R 111 uuuuuu 111110 */
 149 { "crc32", 0x3e74703e, 0xffff703f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }},
 150
 151 /****                 Arithmetic & Logic Instructions                 ****/
 152
 153 #define ADDB_LIKE(NAME,SUBOP2)                                          \
 154   { NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, NPS_ADDB_SIZE }, { C_NPS_F, C_NPS_SX }},
 155
 156 ADDB_LIKE ("addb", 0)
 157 ADDB_LIKE ("subb", 4)
 158 ADDB_LIKE ("adcb", 5)
 159 ADDB_LIKE ("sbcb", 6)
 160
 161 #define ANDB_LIKE(NAME,SUBOP2,SIZE_OPERAND)                             \
 162   { NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, SIZE_OPERAND }, { C_NPS_F }},
 163
 164 ANDB_LIKE ("andb", 1, NPS_ANDB_SIZE)
 165 ANDB_LIKE ("xorb", 2, NPS_ANDB_SIZE)
 166 ANDB_LIKE ("orb", 3, NPS_ANDB_SIZE)
 167 ANDB_LIKE ("fxorb", 7, NPS_FXORB_SIZE)
 168 ANDB_LIKE ("wxorb", 8, NPS_WXORB_SIZE)
 169 ANDB_LIKE ("shlb", 0xb, NPS_ANDB_SIZE)
 170 ANDB_LIKE ("shrb", 0xc, NPS_ANDB_SIZE)
 171
 172 #define NOTB_LIKE(NAME,SUBOP2)                                          \
 173   { NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_ANDB_SIZE }, { C_NPS_F }},
 174
 175 NOTB_LIKE ("notb", 0x9)
 176 NOTB_LIKE ("cntbb", 0xa)
 177
 178 #define DIV_LIKE(NAME,DIV_MODE)                                          \
 179   { NAME, (0x4800000d | DIV_MODE << 14), 0xf80fc3ff, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, }, { C_NPS_F }}, \
 180   { NAME, (0x4800020d | DIV_MODE << 14), 0xf8efc21f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_DIV_UIMM4, NPS_SRC1_POS }, { C_NPS_F }},
 181
 182 DIV_LIKE ("div", 0x1)
 183 DIV_LIKE ("mod", 0x2)
 184 DIV_LIKE ("divm", 0x0)
 185
 186 { "qcmp", 0x4810000e, 0xf81f001e, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, NPS_QCMP_M3 }, { C_NPS_AR_AL }},
 187 { "qcmp", 0x481001ee, 0xf81f01fe, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2 }, { C_NPS_AR_AL }},
 188 { "qcmp", 0x481001ee, 0xf81f81fe, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE, NPS_QCMP_M1  }, { C_NPS_AR_AL }},
 189 { "qcmp", 0x481001ee, 0xf81fc1fe, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE  }, { C_NPS_AR_AL }},
 190
 191 { "calcsd", 0x48000010, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_CALC_ENTRY_SIZE }, { C_NPS_F }},
 192 { "calcxd", 0x48004010, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_CALC_ENTRY_SIZE }, { C_NPS_F }},
 193
 194 { "calcbsd", 0x48000030, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
 195 { "calcbxd", 0x48004030, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
 196
 197 { "calckey", 0x48000050, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
 198 { "calcxkey", 0x48004050, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
 199
 200 { "mxb", 0x580b0000, 0xf81f8007, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR }, { 0 }},
 201 { "mxb", 0x580b8000, 0xf81f8007, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR, NPS_BITS_TO_SCRAMBLE }, { C_NPS_S }},
 202 { "imxb", 0x580b0001, 0xf81f8007, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR }, { 0 }},
 203 { "imxb", 0x580b8001, 0xf81f8007, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR, NPS_BITS_TO_SCRAMBLE }, { C_NPS_S }},
 204
 205 #define ADDL_LIKE(NAME,SUBOP2,SHIM)                                     \
 206   { NAME, (0x48000000 | (SUBOP2 << 16)), 0xf80f0000, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST, NPS_R_SRC1, SHIM }, { C_NPS_F }},
 207
 208 ADDL_LIKE ("addl", 0xA, NPS_SIMM16)
 209 ADDL_LIKE ("subl", 0xB, NPS_SIMM16)
 210 ADDL_LIKE ("orl", 0xC, NPS_UIMM16)
 211 ADDL_LIKE ("andl", 0xD, NPS_UIMM16)
 212 ADDL_LIKE ("xorl", 0xE, NPS_UIMM16)
 213
 214 { "andab", 0x48000011, 0xf80f801f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
 215 { "andab", 0x48008011, 0xf80f801f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
 216 { "orab", 0x48000012, 0xf80f801f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
 217 { "orab", 0x48008012, 0xf80f801f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
 218
 219 { "lbdsize", 0x382f0005, 0xf8ff003f, ARC_OPCODE_ARC700, ARITH, NPS400, { RB, RC }, { C_F }},
 220
 221 { "bdlen", 0x48000013, 0xf80fc01f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BDLEN_MAX_LEN }, { C_NPS_F }},
 222 { "bdlen", 0x48004013, 0xf80fc01f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
 223 { "bdlen", 0x48008013, 0xf80fc01f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BDLEN_MAX_LEN }, { C_NPS_F }},
 224 { "bdlen", 0x4800c013, 0xf80fc01f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
 225
 226 /* csma a,b,c   00111bbb00100001FBBBCCCCCCAAAAAA */
 227 { "csma", 0x382a0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { 0 }},
 228
 229 /* csma a,limm,c   0011111000100001F111CCCCCCAAAAAA */
 230 { "csma", 0x3e2a7000, 0xfffff000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, RC }, { 0 }},
 231
 232 /* csma a,b,u6   00111bbb01100001FBBBuuuuuuAAAAAA */
 233 { "csma", 0x386a0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, UIMM6_20 }, { 0 }},
 234
 235 /* csma 0,b,c   00111bbb00100001FBBBCCCCCC111110 */
 236 { "csma", 0x382a003e, 0xf8ff803f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, RC }, { 0 }},
 237
 238 /* csma 0,limm,c   0011111000100001F111CCCCCC111110 */
 239 { "csma", 0x3e2a703e, 0xfffff03f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, RC }, { 0 }},
 240
 241 /* csma 0,b,u6   00111bbb01100001FBBBuuuuuu111110 */
 242 { "csma", 0x386a003e, 0xf8ff803f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, UIMM6_20 }, { 0 }},
 243
 244 /* csma 0,b,limm   00111bbb00100001FBBB111110111110 */
 245 { "csma", 0x382a0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, LIMM }, { 0 }},
 246
 247 /* csma a,b,limm   00111bbb00100001FBBB111110AAAAAA */
 248 { "csma", 0x382a0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, LIMM }, { 0 }},
 249
 250 /* csma a,limm,limm    0011111000100001F111111110AAAAAA */
 251 { "csma", 0x3e2a7f80, 0xffffffc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, LIMMdup }, { 0 }},
 252
 253 /* csma a,limm,u6   0011111001100001F111uuuuuuAAAAAA */
 254 { "csma", 0x3e6a7000, 0xfffff000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, UIMM6_20 }, { 0 }},
 255
 256 /* csma 0,limm,u6   0011111001100001F111uuuuuu111110 */
 257 { "csma", 0x3e6a703e, 0xfffff03f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, UIMM6_20 }, { 0 }},
 258
 259 /* csms a,b,c   00111bbb00101100FBBBCCCCCCAAAAAA */
 260 { "csms", 0x382c0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { 0 }},
 261
 262 /* csma a,limm,c   0011111000101100F111CCCCCCAAAAAA */
 263 { "csms", 0x3e2c7000, 0xfffff000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, RC }, { 0 }},
 264
 265 /* csms a,b,u6   00111bbb01101100FBBBuuuuuuAAAAAA */
 266 { "csms", 0x386c0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, UIMM6_20 }, { 0 }},
 267
 268 /* csms 0,b,c   00111bbb00101100FBBBCCCCCC111110 */
 269 { "csms", 0x382c003e, 0xf8ff803f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, RC }, { 0 }},
 270
 271 /* csms 0,limm,c   0011111000101100F111CCCCCC111110 */
 272 { "csms", 0x3e2c703e, 0xfffff03f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, RC }, { 0 }},
 273
 274 /* csms 0,b,u6   00111bbb01101100FBBBuuuuuu111110 */
 275 { "csms", 0x386c003e, 0xf8ff803f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, UIMM6_20 }, { 0 }},
 276
 277 /* csms 0,b,limm   00111bbb00101100FBBB111110111110 */
 278 { "csms", 0x382c0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, LIMM }, { 0 }},
 279
 280 /* csms a,b,limm   00111bbb00101100FBBB111110AAAAAA */
 281 { "csms", 0x382c0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, LIMM }, { 0 }},
 282
 283 /* csms a,limm,limm   0011111000101100F111111110AAAAAA */
 284 { "csms", 0x3e2c7f80, 0xffffffc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, LIMMdup }, { 0 }},
 285
 286 /* csms a,limm,u6   0011111001101100F111uuuuuuAAAAAA */
 287 { "csms", 0x3e6c7000, 0xfffff000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, UIMM6_20 }, { 0 }},
 288
 289 /* csms 0,limm,u6   0011111001101100F111uuuuuu111110 */
 290 { "csms", 0x3e6c703e, 0xfffff03f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, UIMM6_20 }, { 0 }},
 291
 292 /* cbba a,b,c   00111bbb00101101FBBBCCCCCCAAAAAA */
 293 { "cbba", 0x382d0000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { C_F }},
 294
 295 /* cbba a,limm,c    0011111000101101F111CCCCCCAAAAAA */
 296 { "cbba", 0x3e2d7000, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, RC }, { C_F }},
 297
 298 /* cbba a,b,u6   00111bbb01101101FBBBuuuuuuAAAAAA */
 299 { "cbba", 0x386d0000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, UIMM6_20 }, { C_F }},
 300
 301 /* cbba 0,b,c   00111bbb00101101FBBBCCCCCC111110 */
 302 { "cbba", 0x382d003e, 0xf8ff003f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, RC }, { C_F }},
 303
 304 /* cbba 0,limm,c   0011111000101101F111CCCCCC111110 */
 305 { "cbba", 0x3e2d703e, 0xffff703f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, RC }, { C_F }},
 306
 307 /* cbba 0,b,u6   00111bbb01101101FBBBuuuuuu111110 */
 308 { "cbba", 0x386d003e, 0xf8ff003f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, UIMM6_20 }, { C_F }},
 309
 310 /* cbba 0,b,limm   00111bbb00101101FBBB111110111110 */
 311 { "cbba", 0x382d0fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, LIMM }, { C_F }},
 312
 313 /* cbba a,b,limm   00111bbb00101101FBBB111110AAAAAA */
 314 { "cbba", 0x382d0f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, LIMM }, { C_F }},
 315
 316 /* cbba a,limm,limm   0011111000101101F111111110AAAAAA */
 317 { "cbba", 0x3e2d7f80, 0xffff7fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, LIMMdup }, { C_F }},
 318
 319 /* cbba a,limm,u6   0011111001101101F111uuuuuuAAAAAA */
 320 { "cbba", 0x3e6d7000, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, UIMM6_20 }, { C_F }},
 321
 322 /* cbba 0,limm,u6   0011111001101101F111uuuuuu111110 */
 323 { "cbba", 0x3e6d703e, 0xffff703f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, UIMM6_20 }, { C_F }},
 324
 325 /* zncv<.rd|.wr> a,b,c   00111bbb001101010BBBCCCCCCAAAAAA */
 326 { "zncv", 0x38350000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { C_NPS_ZNCV }},
 327
 328 /* zncv<.rd|.wr> a,b,u6   00111bbb011101010BBBuuuuuuAAAAAA */
 329 { "zncv", 0x38750000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, UIMM6_20}, { C_NPS_ZNCV }},
 330
 331 /* zncv<.rd|.wr> b,b,s12   00111bbb101101010BBBssssssSSSSSS */
 332 { "zncv", 0x38b50000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RB, RBdup, SIMM12_20 }, { C_NPS_ZNCV }},
 333
 334 /* zncv<.rd|.wr> a,b,limm   00111bbb001101010BBB111110AAAAAA */
 335 { "zncv", 0x38350f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, LIMM }, { C_NPS_ZNCV }},
 336
 337 /* zncv<.rd|.wr> a,limm,c   00111110001101010111CCCCCCAAAAAA */
 338 { "zncv", 0x3e357000, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, RC }, { C_NPS_ZNCV }},
 339
 340 /* zncv<.rd|.wr> a,limm,u6   00111110011101010111uuuuuuAAAAAA */
 341 { "zncv", 0x3e757000, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, UIMM6_20 }, { C_NPS_ZNCV }},
 342
 343 /* zncv<.rd|.wr> a,limm,limm   00111110001101010111111110AAAAAA */
 344 { "zncv", 0x3e357f80, 0xffff7fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, LIMMdup }, { C_NPS_ZNCV }},
 345
 346 /* zncv<.rd|.wr> 0,b,c 00111bbb001101010BBBCCCCCC111110 */
 347 { "zncv", 0x3835003e, 0xf8ff003f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, RC }, { C_NPS_ZNCV }},
 348
 349 /* zncv<.rd|.wr> 0,b,u6   00111bbb011101010BBBuuuuuu111110 */
 350 { "zncv", 0x3875003e, 0xf8ff003f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, UIMM6_20 }, { C_NPS_ZNCV }},
 351
 352 /* zncv<.rd|.wr> 0,b,limm   00111bbb001101010BBB111110111110 */
 353 { "zncv", 0x38350fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, LIMM }, { C_NPS_ZNCV }},
 354
 355 /* zncv<.rd|.wr> 0,limm,c   00111110001101010111CCCCCC111110 */
 356 { "zncv", 0x3e35703e, 0xffff703f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, RC }, { C_NPS_ZNCV }},
 357
 358 /* zncv<.rd|.wr> 0,limm,u6   00111110011101010111uuuuuu111110 */
 359 { "zncv", 0x3e75703e, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, UIMM6_20 }, { C_NPS_ZNCV }},
 360
 361 /* zncv<.rd|.wr> 0,limm,s12   00111110101101010111ssssssSSSSSS */
 362 { "zncv", 0x3eb57000, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, SIMM12_20 }, { C_NPS_ZNCV }},
 363
 364 /* hofs a,b,c */
 365 { "hofs", 0x38360000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { C_F }},
 366
 367 /* hofs a,b,min_hofs,psbc */
 368 { "hofs", 0x38760000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, NPS_MIN_HOFS, NPS_PSBC }, { C_F }},
 369
 370 /****                  Protocol Decoder Instructions                  ****/
 371
 372 /* dctcp b,c  00111bbb001011110bbbcccccc000000 */
 373 { "dctcp", 0x382f0000, 0xf8ff803f, ARC_OPCODE_ARC700, NET, NPS400, { RB, RC }, { 0 }},
 374
 375 /* dcip a,b,c  00111bbb001011110bbbccccccaaaaaa */
 376 { "dcip", 0x38290000, 0xf8ff8000, ARC_OPCODE_ARC700, NET, NPS400, { RA, RB, RC }, { 0 }},
 377
 378 /* dcet b,c  00111bbb001011110bbbcccccc000010 */
 379 { "dcet", 0x382f0002, 0xf8ff803f, ARC_OPCODE_ARC700, NET, NPS400, { RB, RC }, { 0 }},
 380
 381 /* dcet a,b,c  00111bbb001000000bbbccccccaaaaaa */
 382 { "dcet", 0x38200000, 0xf8ff8000, ARC_OPCODE_ARC700, NET, NPS400, { RA, RB, RC }, { 0 }},
 383
 384 /****                        ACL Instructions                         ****/
 385
 386 /* dcacl<.f> a,b,c  00111bbb001001010bbbccccccaaaaaa */
 387 { "dcacl", 0x38250000, 0xf8ff0000, ARC_OPCODE_ARC700, ACL, NPS400, { RA, RB, RC }, { C_F }},
 388
 389 /****                        DPI Instructions                         ****/
 390
 391 /* hash dst,src1,src2,width,perm,nonlinear,basemat */
 392 { "hash", 0x58180000, 0xf81f0000, ARC_OPCODE_ARC700, DPI, NPS400, { NPS_DPI_DST, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_HASH_WIDTH, NPS_HASH_PERM, NPS_HASH_NONLINEAR, NPS_HASH_BASEMAT }, { 0 }},
 393
 394 /* hash.pN dst,src1,src2,width,len,ofs,basemat */
 395
 396 #define HASH_P(FUNC, SUBOP2)                                            \
 397   { "hash", (0x58100000 | (SUBOP2 << 16)), 0xf81f0000, ARC_OPCODE_ARC700, DPI, NPS400, { NPS_DPI_DST, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_HASH_WIDTH, NPS_HASH_LEN, NPS_HASH_OFS, NPS_HASH_BASEMAT2 }, { C_NPS_P##FUNC }},
 398
 399 HASH_P(0, 0x9)
 400 HASH_P(1, 0xA)
 401 HASH_P(2, 0xB)
 402 HASH_P(3, 0xC)
 403
 404 /* tr<.f> a,b,c   00111bbb00100001FBBBCCCCCCAAAAAA */
 405 { "tr", 0x38210000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, RC }, { C_F }},
 406
 407 /* tr<.f> a,limm,c   0011111000100001F111CCCCCCAAAAAA */
 408 { "tr", 0x3e217000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, RC }, { C_F }},
 409
 410 /* tr<.f> a,b,u6   00111bbb01100001FBBBuuuuuuAAAAAA */
 411 { "tr", 0x38610000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, UIMM6_20 }, { C_F }},
 412
 413 /* tr<.f> 0,b,c   00111bbb00100001FBBBCCCCCC111110 */
 414 { "tr", 0x3821003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, RC }, { C_F }},
 415
 416 /* tr<.f> 0,limm,c   0011111000100001F111CCCCCC111110 */
 417 { "tr", 0x3e21703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, RC }, { C_F }},
 418
 419 /* tr<.f> 0,b,u6   00111bbb01100001FBBBuuuuuu111110 */
 420 { "tr", 0x3861003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, UIMM6_20 }, { C_F }},
 421
 422 /* tr<.f> 0,b,limm   00111bbb00100001FBBB111110111110 */
 423 { "tr", 0x38210fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, LIMM }, { C_F }},
 424
 425 /* tr<.f> a,b,limm   00111bbb00100001FBBB111110AAAAAA */
 426 { "tr", 0x38210f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, LIMM }, { C_F }},
 427
 428 /* tr<.f> a,limm,limm   0011111000100001F111111110AAAAAA */
 429 { "tr", 0x3e217f80, 0xffff7fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, LIMMdup }, { C_F }},
 430
 431 /* tr<.f> a,limm,u6   0011111001100001F111uuuuuuAAAAAA */
 432 { "tr", 0x3e617000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, UIMM6_20 }, { C_F }},
 433
 434 /* tr<.f> 0,limm,u6   0011111001100001F111uuuuuu111110 */
 435 { "tr", 0x3e61703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, UIMM6_20 }, { C_F }},
 436
 437 /* utf8 a,b,c       00111bbb00100011FBBBCCCCCCAAAAAA */
 438 { "utf8", 0x38220000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, RC }, { C_F }},
 439
 440 /* utf8 a,limm,c    0011111000100011F111CCCCCCAAAAAA */
 441 { "utf8", 0x3e227000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, RC }, { C_F }},
 442
 443 /* utf8 a,b,u6      00111bbb01100011FBBBuuuuuuAAAAAA */
 444 { "utf8", 0x38620000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, UIMM6_20 }, { C_F }},
 445
 446 /* utf8 0,b,c       00111bbb00100011FBBBCCCCCC111110 */
 447 { "utf8", 0x3822003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, RC }, { C_F }},
 448
 449 /* utf8 0,limm,c    0011111000100011F111CCCCCC111110 */
 450 { "utf8", 0x3e22703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, RC }, { C_F }},
 451
 452 /* utf8 0,b,u6      00111bbb01100011FBBBuuuuuu111110 */
 453 { "utf8", 0x3862003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, UIMM6_20 }, { C_F }},
 454
 455 /* utf8 0,b,limm    00111bbb00100011FBBB111110111110 */
 456 { "utf8", 0x38220fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, LIMM }, { C_F }},
 457
 458 /* utf8 a,b,limm    00111bbb00100011FBBB111110AAAAAA */
 459 { "utf8", 0x38220f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, LIMM }, { C_F }},
 460
 461 /* utf8 a,limm,limm 0011111000100011F111111110AAAAAA */
 462 { "utf8", 0x3e227f80, 0xffff7fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, LIMMdup }, { C_F }},
 463
 464 /* utf8 a,limm,u6   0011111001100011F111uuuuuuAAAAAA */
 465 { "utf8", 0x3e627000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, UIMM6_20 }, { C_F }},
 466
 467 /* utf8 0,limm,u6   0011111001100011F111uuuuuu111110 */
 468 { "utf8", 0x3e62703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, UIMM6_20 }, { C_F }},
 469
 470 /* e4by dst,src1,src2,index0,index1,index2,index3 */
 471 { "e4by", 0x581d0000, 0xf81f0000, ARC_OPCODE_ARC700, DPI, NPS400, { NPS_DPI_DST, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_E4BY_INDEX0, NPS_E4BY_INDEX1, NPS_E4BY_INDEX2, NPS_E4BY_INDEX3 }, { 0 }},
 472
 473 /* addf<.f> a,b,c       00111bbb00100011FBBBCCCCCCAAAAAA */
 474 { "addf", 0x38230000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, RC }, { C_F }},
 475
 476 /* addf<.f> a,limm,c    0011111000100011F111CCCCCCAAAAAA */
 477 { "addf", 0x3e237000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, RC }, { C_F }},
 478
 479 /* addf<.f> a,b,u6      00111bbb01100011FBBBuuuuuuAAAAAA */
 480 { "addf", 0x38630000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, UIMM6_20 }, { C_F }},
 481
 482 /* addf<.f> 0,b,c       00111bbb00100011FBBBCCCCCC111110 */
 483 { "addf", 0x3823003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, RC }, { C_F }},
 484
 485 /* addf<.f> 0,limm,c    0011111000100011F111CCCCCC111110 */
 486 { "addf", 0x3e23703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, RC }, { C_F }},
 487
 488 /* addf<.f> 0,b,u6      00111bbb01100011FBBBuuuuuu111110 */
 489 { "addf", 0x3863003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, UIMM6_20 }, { C_F }},
 490
 491 /* addf<.f> 0,b,limm    00111bbb00100011FBBB111110111110 */
 492 { "addf", 0x38230fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, LIMM }, { C_F }},
 493
 494 /* addf<.f> a,b,limm    00111bbb00100011FBBB111110AAAAAA */
 495 { "addf", 0x38230f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, LIMM }, { C_F }},
 496
 497 /* addf<.f> a,limm,limm 0011111000100011F111111110AAAAAA */
 498 { "addf", 0x3e237f80, 0xffff7fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, LIMMdup }, { C_F }},
 499
 500 /* addf<.f> a,limm,u6   0011111001100011F111uuuuuuAAAAAA */
 501 { "addf", 0x3e637000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, UIMM6_20 }, { C_F }},
 502
 503 /* addf<.f> 0,limm,u6   0011111001100011F111uuuuuu111110 */
 504 { "addf", 0x3e63703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, UIMM6_20 }, { C_F }},
 505
 506 /* ldbit<.x2|.x4>.di<.cl> a,[b]       00010bbb00000000SBBB10011XAAAAAA */
 507 { "ldbit", 0x10000980, 0xf8ff8980, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, RB, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
 508
 509 /* ldbit<.x2|.x4>.di<.cl> a,[b,s9]    00010bbbssssssssSBBB10011XAAAAAA */
 510 { "ldbit", 0x10000980, 0xf8000980, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
 511
 512 /* ldbit<.x2|.x4>.di<.cl> a,[limm]    0001011000000000011110011XAAAAAA */
 513 { "ldbit", 0x16007980, 0xfffff980, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, LIMM, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
 514
 515 /* ldbit<.x2|.x4>.di<.cl> a,[limm,s9] 00010110ssssssssS11110011XAAAAAA */
 516 { "ldbit", 0x16007980, 0xff007980, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
 517
 518 /* ldbit<.x2|.x4>.di<.cl> a,[b,c]     00100bbb0011011X1BBBCCCCCCAAAAAA */
 519 { "ldbit", 0x20368000, 0xf83e8000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, RB, RC, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }},
 520
 521 /* ldbit<.x2|.x4>.di<.cl> a,[b,limm]  00100bbb0011011X1BBB111110AAAAAA */
 522 { "ldbit", 0x20368f80, 0xf83e8fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, RB, LIMM, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }},
 523
 524 /* ldbit<.x2|.x4>.di<.cl> a,[limm,c]  001001100011011X1111CCCCCCAAAAAA */
 525 { "ldbit", 0x2636f000, 0xff3ef000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, LIMM, RC, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }},
 526
 527 /****                  Pipeline Control Instructions                  ****/
 528
 529 /* schd<.rw|.rd> */
 530 { "schd", 0x3e6f7004, 0xffffff7f, ARC_OPCODE_ARC700, CONTROL, NPS400, { 0 }, { C_NPS_SCHD_RW }},
 531
 532 /* schd.wft.<.ie1|.ie2|.ie12> */
 533 { "schd", 0x3e6f7044, 0xfffffcff, ARC_OPCODE_ARC700, CONTROL, NPS400, { 0 }, { C_NPS_SCHD_TRIG, C_NPS_SCHD_IE }},
 534
 535 /* sync<.rd|.wr> */
 536 { "sync", 0x3e6f703f, 0xffffffbf, ARC_OPCODE_ARC700, CONTROL, NPS400, { 0 }, { C_NPS_SYNC }},
 537
 538 /* hwscd.off B */
 539 { "hwschd", 0x386f00bf, 0xf8ff8fff, ARC_OPCODE_ARC700, CONTROL, NPS400, { RB }, { C_NPS_HWS_OFF }},
 540
 541 /* hwscd.restore 0,C */
 542 { "hwschd", 0x3e6f7003, 0xfffff03f, ARC_OPCODE_ARC700, CONTROL, NPS400, { ZA, RC }, { C_NPS_HWS_RESTORE }},
 543
 544 /****      Load / Store From (0x57f00000 + Offset) Instructions       ****/
 545
 546 #define XLDST_LIKE(NAME,SUBOP2)                                          \
 547   { NAME, (0x58000000 | (SUBOP2 << 16)), 0xf81f0000, ARC_OPCODE_ARC700, MEMORY, NPS400, { NPS_R_DST, BRAKET, NPS_XLDST_UIMM16, BRAKETdup }, { 0 }},
 548
 549 XLDST_LIKE("xldb", 0x8)
 550 XLDST_LIKE("xldw", 0x9)
 551 XLDST_LIKE("xld", 0xa)
 552 XLDST_LIKE("xstb", 0xc)
 553 XLDST_LIKE("xstw", 0xd)
 554 XLDST_LIKE("xst", 0xe)