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gdb: add target_ops::supports_displaced_step
[deliverable/binutils-gdb.git] / opcodes / arc-opc.c
1 /* Opcode table for the ARC.
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software Foundation,
20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
21
22 #include "sysdep.h"
23 #include <stdio.h>
24 #include "bfd.h"
25 #include "opcode/arc.h"
26 #include "opintl.h"
27 #include "libiberty.h"
28
29 /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
30 instructions. All NPS400 features are built into all ARC target builds as
31 this reduces the chances that regressions might creep in. */
32
33 /* Insert RA register into a 32-bit opcode, with checks. */
34
35 static unsigned long long
36 insert_ra_chk (unsigned long long insn,
37 long long value,
38 const char ** errmsg)
39 {
40 if (value == 60)
41 *errmsg = _("LP_COUNT register cannot be used as destination register");
42
43 return insn | (value & 0x3F);
44 }
45
46 /* Insert RB register into a 32-bit opcode. */
47
48 static unsigned long long
49 insert_rb (unsigned long long insn,
50 long long value,
51 const char ** errmsg ATTRIBUTE_UNUSED)
52 {
53 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
54 }
55
56 /* Insert RB register with checks. */
57
58 static unsigned long long
59 insert_rb_chk (unsigned long long insn,
60 long long value,
61 const char ** errmsg)
62 {
63 if (value == 60)
64 *errmsg = _("LP_COUNT register cannot be used as destination register");
65
66 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
67 }
68
69 static long long
70 extract_rb (unsigned long long insn,
71 bfd_boolean * invalid)
72 {
73 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
74
75 if (value == 0x3e && invalid)
76 *invalid = TRUE; /* A limm operand, it should be extracted in a
77 different way. */
78
79 return value;
80 }
81
82 static unsigned long long
83 insert_rad (unsigned long long insn,
84 long long value,
85 const char ** errmsg)
86 {
87 if (value & 0x01)
88 *errmsg = _("cannot use odd number destination register");
89 if (value == 60)
90 *errmsg = _("LP_COUNT register cannot be used as destination register");
91
92 return insn | (value & 0x3F);
93 }
94
95 static unsigned long long
96 insert_rcd (unsigned long long insn,
97 long long value,
98 const char ** errmsg)
99 {
100 if (value & 0x01)
101 *errmsg = _("cannot use odd number source register");
102
103 return insn | ((value & 0x3F) << 6);
104 }
105
106 /* Dummy insert ZERO operand function. */
107
108 static unsigned long long
109 insert_za (unsigned long long insn,
110 long long value,
111 const char ** errmsg)
112 {
113 if (value)
114 *errmsg = _("operand is not zero");
115 return insn;
116 }
117
118 /* Insert Y-bit in bbit/br instructions. This function is called only
119 when solving fixups. */
120
121 static unsigned long long
122 insert_Ybit (unsigned long long insn,
123 long long value,
124 const char ** errmsg ATTRIBUTE_UNUSED)
125 {
126 if (value > 0)
127 insn |= 0x08;
128
129 return insn;
130 }
131
132 /* Insert Y-bit in bbit/br instructions. This function is called only
133 when solving fixups. */
134
135 static unsigned long long
136 insert_NYbit (unsigned long long insn,
137 long long value,
138 const char ** errmsg ATTRIBUTE_UNUSED)
139 {
140 if (value < 0)
141 insn |= 0x08;
142
143 return insn;
144 }
145
146 /* Insert H register into a 16-bit opcode. */
147
148 static unsigned long long
149 insert_rhv1 (unsigned long long insn,
150 long long value,
151 const char ** errmsg ATTRIBUTE_UNUSED)
152 {
153 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
154 }
155
156 static long long
157 extract_rhv1 (unsigned long long insn,
158 bfd_boolean * invalid ATTRIBUTE_UNUSED)
159 {
160 int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
161
162 return value;
163 }
164
165 /* Insert H register into a 16-bit opcode. */
166
167 static unsigned long long
168 insert_rhv2 (unsigned long long insn,
169 long long value,
170 const char ** errmsg)
171 {
172 if (value == 0x1E)
173 *errmsg = _("register R30 is a limm indicator");
174 else if (value < 0 || value > 31)
175 *errmsg = _("register out of range");
176 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
177 }
178
179 static long long
180 extract_rhv2 (unsigned long long insn,
181 bfd_boolean * invalid ATTRIBUTE_UNUSED)
182 {
183 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
184
185 return value;
186 }
187
188 static unsigned long long
189 insert_r0 (unsigned long long insn,
190 long long value,
191 const char ** errmsg)
192 {
193 if (value != 0)
194 *errmsg = _("register must be R0");
195 return insn;
196 }
197
198 static long long
199 extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED,
200 bfd_boolean * invalid ATTRIBUTE_UNUSED)
201 {
202 return 0;
203 }
204
205
206 static unsigned long long
207 insert_r1 (unsigned long long insn,
208 long long value,
209 const char ** errmsg)
210 {
211 if (value != 1)
212 *errmsg = _("register must be R1");
213 return insn;
214 }
215
216 static long long
217 extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED,
218 bfd_boolean * invalid ATTRIBUTE_UNUSED)
219 {
220 return 1;
221 }
222
223 static unsigned long long
224 insert_r2 (unsigned long long insn,
225 long long value,
226 const char ** errmsg)
227 {
228 if (value != 2)
229 *errmsg = _("register must be R2");
230 return insn;
231 }
232
233 static long long
234 extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED,
235 bfd_boolean * invalid ATTRIBUTE_UNUSED)
236 {
237 return 2;
238 }
239
240 static unsigned long long
241 insert_r3 (unsigned long long insn,
242 long long value,
243 const char ** errmsg)
244 {
245 if (value != 3)
246 *errmsg = _("register must be R3");
247 return insn;
248 }
249
250 static long long
251 extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED,
252 bfd_boolean * invalid ATTRIBUTE_UNUSED)
253 {
254 return 3;
255 }
256
257 static unsigned long long
258 insert_sp (unsigned long long insn,
259 long long value,
260 const char ** errmsg)
261 {
262 if (value != 28)
263 *errmsg = _("register must be SP");
264 return insn;
265 }
266
267 static long long
268 extract_sp (unsigned long long insn ATTRIBUTE_UNUSED,
269 bfd_boolean * invalid ATTRIBUTE_UNUSED)
270 {
271 return 28;
272 }
273
274 static unsigned long long
275 insert_gp (unsigned long long insn,
276 long long value,
277 const char ** errmsg)
278 {
279 if (value != 26)
280 *errmsg = _("register must be GP");
281 return insn;
282 }
283
284 static long long
285 extract_gp (unsigned long long insn ATTRIBUTE_UNUSED,
286 bfd_boolean * invalid ATTRIBUTE_UNUSED)
287 {
288 return 26;
289 }
290
291 static unsigned long long
292 insert_pcl (unsigned long long insn,
293 long long value,
294 const char ** errmsg)
295 {
296 if (value != 63)
297 *errmsg = _("register must be PCL");
298 return insn;
299 }
300
301 static long long
302 extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED,
303 bfd_boolean * invalid ATTRIBUTE_UNUSED)
304 {
305 return 63;
306 }
307
308 static unsigned long long
309 insert_blink (unsigned long long insn,
310 long long value,
311 const char ** errmsg)
312 {
313 if (value != 31)
314 *errmsg = _("register must be BLINK");
315 return insn;
316 }
317
318 static long long
319 extract_blink (unsigned long long insn ATTRIBUTE_UNUSED,
320 bfd_boolean * invalid ATTRIBUTE_UNUSED)
321 {
322 return 31;
323 }
324
325 static unsigned long long
326 insert_ilink1 (unsigned long long insn,
327 long long value,
328 const char ** errmsg)
329 {
330 if (value != 29)
331 *errmsg = _("register must be ILINK1");
332 return insn;
333 }
334
335 static long long
336 extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED,
337 bfd_boolean * invalid ATTRIBUTE_UNUSED)
338 {
339 return 29;
340 }
341
342 static unsigned long long
343 insert_ilink2 (unsigned long long insn,
344 long long value,
345 const char ** errmsg)
346 {
347 if (value != 30)
348 *errmsg = _("register must be ILINK2");
349 return insn;
350 }
351
352 static long long
353 extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED,
354 bfd_boolean * invalid ATTRIBUTE_UNUSED)
355 {
356 return 30;
357 }
358
359 static unsigned long long
360 insert_ras (unsigned long long insn,
361 long long value,
362 const char ** errmsg)
363 {
364 switch (value)
365 {
366 case 0:
367 case 1:
368 case 2:
369 case 3:
370 insn |= value;
371 break;
372 case 12:
373 case 13:
374 case 14:
375 case 15:
376 insn |= (value - 8);
377 break;
378 default:
379 *errmsg = _("register must be either r0-r3 or r12-r15");
380 break;
381 }
382 return insn;
383 }
384
385 static long long
386 extract_ras (unsigned long long insn,
387 bfd_boolean * invalid ATTRIBUTE_UNUSED)
388 {
389 int value = insn & 0x07;
390
391 if (value > 3)
392 return (value + 8);
393 else
394 return value;
395 }
396
397 static unsigned long long
398 insert_rbs (unsigned long long insn,
399 long long value,
400 const char ** errmsg)
401 {
402 switch (value)
403 {
404 case 0:
405 case 1:
406 case 2:
407 case 3:
408 insn |= value << 8;
409 break;
410 case 12:
411 case 13:
412 case 14:
413 case 15:
414 insn |= ((value - 8)) << 8;
415 break;
416 default:
417 *errmsg = _("register must be either r0-r3 or r12-r15");
418 break;
419 }
420 return insn;
421 }
422
423 static long long
424 extract_rbs (unsigned long long insn,
425 bfd_boolean * invalid ATTRIBUTE_UNUSED)
426 {
427 int value = (insn >> 8) & 0x07;
428
429 if (value > 3)
430 return (value + 8);
431 else
432 return value;
433 }
434
435 static unsigned long long
436 insert_rcs (unsigned long long insn,
437 long long value,
438 const char ** errmsg)
439 {
440 switch (value)
441 {
442 case 0:
443 case 1:
444 case 2:
445 case 3:
446 insn |= value << 5;
447 break;
448 case 12:
449 case 13:
450 case 14:
451 case 15:
452 insn |= ((value - 8)) << 5;
453 break;
454 default:
455 *errmsg = _("register must be either r0-r3 or r12-r15");
456 break;
457 }
458 return insn;
459 }
460
461 static long long
462 extract_rcs (unsigned long long insn,
463 bfd_boolean * invalid ATTRIBUTE_UNUSED)
464 {
465 int value = (insn >> 5) & 0x07;
466
467 if (value > 3)
468 return (value + 8);
469 else
470 return value;
471 }
472
473 static unsigned long long
474 insert_simm3s (unsigned long long insn,
475 long long value,
476 const char ** errmsg)
477 {
478 int tmp = 0;
479 switch (value)
480 {
481 case -1:
482 tmp = 0x07;
483 break;
484 case 0:
485 tmp = 0x00;
486 break;
487 case 1:
488 tmp = 0x01;
489 break;
490 case 2:
491 tmp = 0x02;
492 break;
493 case 3:
494 tmp = 0x03;
495 break;
496 case 4:
497 tmp = 0x04;
498 break;
499 case 5:
500 tmp = 0x05;
501 break;
502 case 6:
503 tmp = 0x06;
504 break;
505 default:
506 *errmsg = _("accepted values are from -1 to 6");
507 break;
508 }
509
510 insn |= tmp << 8;
511 return insn;
512 }
513
514 static long long
515 extract_simm3s (unsigned long long insn,
516 bfd_boolean * invalid ATTRIBUTE_UNUSED)
517 {
518 int value = (insn >> 8) & 0x07;
519
520 if (value == 7)
521 return -1;
522 else
523 return value;
524 }
525
526 static unsigned long long
527 insert_rrange (unsigned long long insn,
528 long long value,
529 const char ** errmsg)
530 {
531 int reg1 = (value >> 16) & 0xFFFF;
532 int reg2 = value & 0xFFFF;
533
534 if (reg1 != 13)
535 *errmsg = _("first register of the range should be r13");
536 else if (reg2 < 13 || reg2 > 26)
537 *errmsg = _("last register of the range doesn't fit");
538 else
539 insn |= ((reg2 - 12) & 0x0F) << 1;
540 return insn;
541 }
542
543 static long long
544 extract_rrange (unsigned long long insn,
545 bfd_boolean * invalid ATTRIBUTE_UNUSED)
546 {
547 return (insn >> 1) & 0x0F;
548 }
549
550 static unsigned long long
551 insert_r13el (unsigned long long insn,
552 long long int value,
553 const char **errmsg)
554 {
555 if (value != 13)
556 {
557 *errmsg = _("invalid register number, should be fp");
558 return insn;
559 }
560
561 insn |= 0x02;
562 return insn;
563 }
564
565 static unsigned long long
566 insert_fpel (unsigned long long insn,
567 long long value,
568 const char ** errmsg)
569 {
570 if (value != 27)
571 {
572 *errmsg = _("invalid register number, should be fp");
573 return insn;
574 }
575
576 insn |= 0x0100;
577 return insn;
578 }
579
580 static long long
581 extract_fpel (unsigned long long insn,
582 bfd_boolean * invalid ATTRIBUTE_UNUSED)
583 {
584 return (insn & 0x0100) ? 27 : -1;
585 }
586
587 static unsigned long long
588 insert_blinkel (unsigned long long insn,
589 long long value,
590 const char ** errmsg)
591 {
592 if (value != 31)
593 {
594 *errmsg = _("invalid register number, should be blink");
595 return insn;
596 }
597
598 insn |= 0x0200;
599 return insn;
600 }
601
602 static long long
603 extract_blinkel (unsigned long long insn,
604 bfd_boolean * invalid ATTRIBUTE_UNUSED)
605 {
606 return (insn & 0x0200) ? 31 : -1;
607 }
608
609 static unsigned long long
610 insert_pclel (unsigned long long insn,
611 long long value,
612 const char ** errmsg)
613 {
614 if (value != 63)
615 {
616 *errmsg = _("invalid register number, should be pcl");
617 return insn;
618 }
619
620 insn |= 0x0400;
621 return insn;
622 }
623
624 static long long
625 extract_pclel (unsigned long long insn,
626 bfd_boolean * invalid ATTRIBUTE_UNUSED)
627 {
628 return (insn & 0x0400) ? 63 : -1;
629 }
630
631 #define INSERT_W6
632
633 /* mask = 00000000000000000000111111000000
634 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
635
636 static unsigned long long
637 insert_w6 (unsigned long long insn,
638 long long value,
639 const char ** errmsg ATTRIBUTE_UNUSED)
640 {
641 insn |= ((value >> 0) & 0x003f) << 6;
642
643 return insn;
644 }
645
646 #define EXTRACT_W6
647
648 /* mask = 00000000000000000000111111000000. */
649
650 static long long
651 extract_w6 (unsigned long long insn,
652 bfd_boolean * invalid ATTRIBUTE_UNUSED)
653 {
654 int value = 0;
655
656 value |= ((insn >> 6) & 0x003f) << 0;
657
658 /* Extend the sign. */
659 int signbit = 1 << 5;
660 value = (value ^ signbit) - signbit;
661
662 return value;
663 }
664
665 #define INSERT_G_S
666
667 /* mask = 0000011100022000
668 insn = 01000ggghhhGG0HH. */
669
670 static unsigned long long
671 insert_g_s (unsigned long long insn,
672 long long value,
673 const char ** errmsg ATTRIBUTE_UNUSED)
674 {
675 insn |= ((value >> 0) & 0x0007) << 8;
676 insn |= ((value >> 3) & 0x0003) << 3;
677
678 return insn;
679 }
680
681 #define EXTRACT_G_S
682
683 /* mask = 0000011100022000. */
684
685 static long long
686 extract_g_s (unsigned long long insn,
687 bfd_boolean * invalid ATTRIBUTE_UNUSED)
688 {
689 int value = 0;
690 int signbit = 1 << (6 - 1);
691
692 value |= ((insn >> 8) & 0x0007) << 0;
693 value |= ((insn >> 3) & 0x0003) << 3;
694
695 /* Extend the sign. */
696 value = (value ^ signbit) - signbit;
697
698 return value;
699 }
700
701 /* ARC NPS400 Support: See comment near head of file. */
702 #define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \
703 static unsigned long long \
704 insert_nps_3bit_reg_at_##OFFSET##_##NAME \
705 (unsigned long long insn, \
706 long long value, \
707 const char ** errmsg) \
708 { \
709 switch (value) \
710 { \
711 case 0: \
712 case 1: \
713 case 2: \
714 case 3: \
715 insn |= value << (OFFSET); \
716 break; \
717 case 12: \
718 case 13: \
719 case 14: \
720 case 15: \
721 insn |= (value - 8) << (OFFSET); \
722 break; \
723 default: \
724 *errmsg = _("register must be either r0-r3 or r12-r15"); \
725 break; \
726 } \
727 return insn; \
728 } \
729 \
730 static long long \
731 extract_nps_3bit_reg_at_##OFFSET##_##NAME \
732 (unsigned long long insn, \
733 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
734 { \
735 int value = (insn >> (OFFSET)) & 0x07; \
736 if (value > 3) \
737 value += 8; \
738 return value; \
739 } \
740
741 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8)
742 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24)
743 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40)
744 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56)
745
746 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5)
747 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21)
748 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37)
749 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53)
750
751 static unsigned long long
752 insert_nps_bitop_size_2b (unsigned long long insn,
753 long long value,
754 const char ** errmsg)
755 {
756 switch (value)
757 {
758 case 1:
759 value = 0;
760 break;
761 case 2:
762 value = 1;
763 break;
764 case 4:
765 value = 2;
766 break;
767 case 8:
768 value = 3;
769 break;
770 default:
771 value = 0;
772 *errmsg = _("invalid size, should be 1, 2, 4, or 8");
773 break;
774 }
775
776 insn |= value << 10;
777 return insn;
778 }
779
780 static long long
781 extract_nps_bitop_size_2b (unsigned long long insn,
782 bfd_boolean * invalid ATTRIBUTE_UNUSED)
783 {
784 return 1 << ((insn >> 10) & 0x3);
785 }
786
787 static unsigned long long
788 insert_nps_bitop_uimm8 (unsigned long long insn,
789 long long value,
790 const char ** errmsg ATTRIBUTE_UNUSED)
791 {
792 insn |= ((value >> 5) & 7) << 12;
793 insn |= (value & 0x1f);
794 return insn;
795 }
796
797 static long long
798 extract_nps_bitop_uimm8 (unsigned long long insn,
799 bfd_boolean * invalid ATTRIBUTE_UNUSED)
800 {
801 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
802 }
803
804 static unsigned long long
805 insert_nps_rflt_uimm6 (unsigned long long insn,
806 long long value,
807 const char ** errmsg)
808 {
809 switch (value)
810 {
811 case 1:
812 case 2:
813 case 4:
814 break;
815
816 default:
817 *errmsg = _("invalid immediate, must be 1, 2, or 4");
818 value = 0;
819 }
820
821 insn |= (value << 6);
822 return insn;
823 }
824
825 static long long
826 extract_nps_rflt_uimm6 (unsigned long long insn,
827 bfd_boolean * invalid ATTRIBUTE_UNUSED)
828 {
829 return (insn >> 6) & 0x3f;
830 }
831
832 static unsigned long long
833 insert_nps_dst_pos_and_size (unsigned long long insn,
834 long long value,
835 const char ** errmsg ATTRIBUTE_UNUSED)
836 {
837 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
838 return insn;
839 }
840
841 static long long
842 extract_nps_dst_pos_and_size (unsigned long long insn,
843 bfd_boolean * invalid ATTRIBUTE_UNUSED)
844 {
845 return (insn & 0x1f);
846 }
847
848 static unsigned long long
849 insert_nps_cmem_uimm16 (unsigned long long insn,
850 long long value,
851 const char ** errmsg)
852 {
853 int top = (value >> 16) & 0xffff;
854
855 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
856 *errmsg = _("invalid value for CMEM ld/st immediate");
857 insn |= (value & 0xffff);
858 return insn;
859 }
860
861 static long long
862 extract_nps_cmem_uimm16 (unsigned long long insn,
863 bfd_boolean * invalid ATTRIBUTE_UNUSED)
864 {
865 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
866 }
867
868 static unsigned long long
869 insert_nps_imm_offset (unsigned long long insn,
870 long long value,
871 const char ** errmsg)
872 {
873 switch (value)
874 {
875 case 0:
876 case 16:
877 case 32:
878 case 48:
879 case 64:
880 value = value >> 4;
881 break;
882 default:
883 *errmsg = _("invalid position, should be 0, 16, 32, 48 or 64.");
884 value = 0;
885 }
886 insn |= (value << 10);
887 return insn;
888 }
889
890 static long long
891 extract_nps_imm_offset (unsigned long long insn,
892 bfd_boolean * invalid ATTRIBUTE_UNUSED)
893 {
894 return ((insn >> 10) & 0x7) * 16;
895 }
896
897 static unsigned long long
898 insert_nps_imm_entry (unsigned long long insn,
899 long long value,
900 const char ** errmsg)
901 {
902 switch (value)
903 {
904 case 16:
905 value = 0;
906 break;
907 case 32:
908 value = 1;
909 break;
910 case 64:
911 value = 2;
912 break;
913 case 128:
914 value = 3;
915 break;
916 default:
917 *errmsg = _("invalid position, should be 16, 32, 64 or 128.");
918 value = 0;
919 }
920 insn |= (value << 2);
921 return insn;
922 }
923
924 static long long
925 extract_nps_imm_entry (unsigned long long insn,
926 bfd_boolean * invalid ATTRIBUTE_UNUSED)
927 {
928 int imm_entry = ((insn >> 2) & 0x7);
929 return (1 << (imm_entry + 4));
930 }
931
932 static unsigned long long
933 insert_nps_size_16bit (unsigned long long insn,
934 long long value,
935 const char ** errmsg)
936 {
937 if ((value < 1) || (value > 64))
938 {
939 *errmsg = _("invalid size value must be on range 1-64.");
940 value = 0;
941 }
942 value = value & 0x3f;
943 insn |= (value << 6);
944 return insn;
945 }
946
947 static long long
948 extract_nps_size_16bit (unsigned long long insn,
949 bfd_boolean * invalid ATTRIBUTE_UNUSED)
950 {
951 return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64;
952 }
953
954
955 #define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
956 static unsigned long long \
957 insert_nps_##NAME##_pos (unsigned long long insn, \
958 long long value, \
959 const char ** errmsg) \
960 { \
961 switch (value) \
962 { \
963 case 0: \
964 case 8: \
965 case 16: \
966 case 24: \
967 value = value / 8; \
968 break; \
969 default: \
970 *errmsg = _("invalid position, should be 0, 8, 16, or 24"); \
971 value = 0; \
972 } \
973 insn |= (value << SHIFT); \
974 return insn; \
975 } \
976 \
977 static long long \
978 extract_nps_##NAME##_pos (unsigned long long insn, \
979 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
980 { \
981 return ((insn >> SHIFT) & 0x3) * 8; \
982 }
983
984 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
985 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
986
987 #define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT) \
988 static unsigned long long \
989 insert_nps_##NAME (unsigned long long insn, \
990 long long value, \
991 const char ** errmsg) \
992 { \
993 if (value < LOWER || value > UPPER) \
994 { \
995 *errmsg = _("invalid size, value must be " \
996 #LOWER " to " #UPPER "."); \
997 return insn; \
998 } \
999 value -= BIAS; \
1000 insn |= (value << SHIFT); \
1001 return insn; \
1002 } \
1003 \
1004 static long long \
1005 extract_nps_##NAME (unsigned long long insn, \
1006 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1007 { \
1008 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
1009 }
1010
1011 MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5)
1012 MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5)
1013 MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5)
1014 MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5)
1015 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10)
1016 MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9)
1017 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20)
1018 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25)
1019 MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6)
1020 MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2)
1021 MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
1022
1023 static long long
1024 extract_nps_qcmp_m3 (unsigned long long insn,
1025 bfd_boolean * invalid)
1026 {
1027 int m3 = (insn >> 5) & 0xf;
1028 if (m3 == 0xf)
1029 *invalid = TRUE;
1030 return m3;
1031 }
1032
1033 static long long
1034 extract_nps_qcmp_m2 (unsigned long long insn,
1035 bfd_boolean * invalid)
1036 {
1037 bfd_boolean tmp_invalid = FALSE;
1038 int m2 = (insn >> 15) & 0x1;
1039 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
1040
1041 if (m2 == 0 && m3 == 0xf)
1042 *invalid = TRUE;
1043 return m2;
1044 }
1045
1046 static long long
1047 extract_nps_qcmp_m1 (unsigned long long insn,
1048 bfd_boolean * invalid)
1049 {
1050 bfd_boolean tmp_invalid = FALSE;
1051 int m1 = (insn >> 14) & 0x1;
1052 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
1053 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
1054
1055 if (m1 == 0 && m2 == 0 && m3 == 0xf)
1056 *invalid = TRUE;
1057 return m1;
1058 }
1059
1060 static unsigned long long
1061 insert_nps_calc_entry_size (unsigned long long insn,
1062 long long value,
1063 const char ** errmsg)
1064 {
1065 unsigned pwr;
1066
1067 if (value < 1 || value > 256)
1068 {
1069 *errmsg = _("value out of range 1 - 256");
1070 return 0;
1071 }
1072
1073 for (pwr = 0; (value & 1) == 0; value >>= 1)
1074 ++pwr;
1075
1076 if (value != 1)
1077 {
1078 *errmsg = _("value must be power of 2");
1079 return 0;
1080 }
1081
1082 return insn | (pwr << 8);
1083 }
1084
1085 static long long
1086 extract_nps_calc_entry_size (unsigned long long insn,
1087 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1088 {
1089 unsigned entry_size = (insn >> 8) & 0xf;
1090 return 1 << entry_size;
1091 }
1092
1093 static unsigned long long
1094 insert_nps_bitop_mod4 (unsigned long long insn,
1095 long long value,
1096 const char ** errmsg ATTRIBUTE_UNUSED)
1097 {
1098 return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47);
1099 }
1100
1101 static long long
1102 extract_nps_bitop_mod4 (unsigned long long insn,
1103 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1104 {
1105 return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1);
1106 }
1107
1108 static unsigned long long
1109 insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
1110 long long value,
1111 const char ** errmsg ATTRIBUTE_UNUSED)
1112 {
1113 return insn | (value << 42) | (value << 37);
1114 }
1115
1116 static long long
1117 extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
1118 bfd_boolean * invalid)
1119 {
1120 if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f))
1121 *invalid = TRUE;
1122 return ((insn >> 37) & 0x1f);
1123 }
1124
1125 static unsigned long long
1126 insert_nps_bitop_ins_ext (unsigned long long insn,
1127 long long value,
1128 const char ** errmsg)
1129 {
1130 if (value < 0 || value > 28)
1131 *errmsg = _("value must be in the range 0 to 28");
1132 return insn | (value << 20);
1133 }
1134
1135 static long long
1136 extract_nps_bitop_ins_ext (unsigned long long insn,
1137 bfd_boolean * invalid)
1138 {
1139 int value = (insn >> 20) & 0x1f;
1140
1141 if (value > 28)
1142 *invalid = TRUE;
1143 return value;
1144 }
1145
1146 #define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
1147 static unsigned long long \
1148 insert_nps_##NAME (unsigned long long insn, \
1149 long long value, \
1150 const char ** errmsg) \
1151 { \
1152 if (value < 1 || value > UPPER) \
1153 *errmsg = _("value must be in the range 1 to " #UPPER); \
1154 if (value == UPPER) \
1155 value = 0; \
1156 return insn | (value << SHIFT); \
1157 } \
1158 \
1159 static long long \
1160 extract_nps_##NAME (unsigned long long insn, \
1161 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1162 { \
1163 int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
1164 if (value == 0) \
1165 value = UPPER; \
1166 return value; \
1167 }
1168
1169 MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3)
1170 MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3)
1171 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3)
1172 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8)
1173 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3)
1174 MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2)
1175 MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6)
1176
1177 static unsigned long long
1178 insert_nps_min_hofs (unsigned long long insn,
1179 long long value,
1180 const char ** errmsg)
1181 {
1182 if (value < 0 || value > 240)
1183 *errmsg = _("value must be in the range 0 to 240");
1184 if ((value % 16) != 0)
1185 *errmsg = _("value must be a multiple of 16");
1186 value = value / 16;
1187 return insn | (value << 6);
1188 }
1189
1190 static long long
1191 extract_nps_min_hofs (unsigned long long insn,
1192 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1193 {
1194 int value = (insn >> 6) & 0xF;
1195 return value * 16;
1196 }
1197
1198 #define MAKE_INSERT_NPS_ADDRTYPE(NAME, VALUE) \
1199 static unsigned long long \
1200 insert_nps_##NAME (unsigned long long insn, \
1201 long long value, \
1202 const char ** errmsg) \
1203 { \
1204 if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
1205 *errmsg = _("invalid address type for operand"); \
1206 return insn; \
1207 } \
1208 \
1209 static long long \
1210 extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1211 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1212 { \
1213 return ARC_NPS400_ADDRTYPE_##VALUE; \
1214 }
1215
1216 MAKE_INSERT_NPS_ADDRTYPE (bd, BD)
1217 MAKE_INSERT_NPS_ADDRTYPE (jid, JID)
1218 MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD)
1219 MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD)
1220 MAKE_INSERT_NPS_ADDRTYPE (sd, SD)
1221 MAKE_INSERT_NPS_ADDRTYPE (sm, SM)
1222 MAKE_INSERT_NPS_ADDRTYPE (xa, XA)
1223 MAKE_INSERT_NPS_ADDRTYPE (xd, XD)
1224 MAKE_INSERT_NPS_ADDRTYPE (cd, CD)
1225 MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD)
1226 MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID)
1227 MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD)
1228 MAKE_INSERT_NPS_ADDRTYPE (cm, CM)
1229 MAKE_INSERT_NPS_ADDRTYPE (csd, CSD)
1230 MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA)
1231 MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD)
1232
1233 static unsigned long long
1234 insert_nps_rbdouble_64 (unsigned long long insn,
1235 long long value,
1236 const char ** errmsg)
1237 {
1238 if (value < 0 || value > 31)
1239 *errmsg = _("value must be in the range 0 to 31");
1240 return insn | (value << 43) | (value << 48);
1241 }
1242
1243
1244 static long long
1245 extract_nps_rbdouble_64 (unsigned long long insn,
1246 bfd_boolean * invalid)
1247 {
1248 int value1 = (insn >> 43) & 0x1F;
1249 int value2 = (insn >> 48) & 0x1F;
1250
1251 if (value1 != value2)
1252 *invalid = TRUE;
1253
1254 return value1;
1255 }
1256
1257 static unsigned long long
1258 insert_nps_misc_imm_offset (unsigned long long insn,
1259 long long value,
1260 const char ** errmsg)
1261 {
1262 if (value & 0x3)
1263 {
1264 *errmsg = _("invalid position, should be one of: 0,4,8,...124.");
1265 value = 0;
1266 }
1267 insn |= (value << 6);
1268 return insn;
1269 }
1270
1271 static long long int
1272 extract_nps_misc_imm_offset (unsigned long long insn,
1273 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1274 {
1275 return ((insn >> 8) & 0x1f) * 4;
1276 }
1277
1278 static long long int
1279 extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED,
1280 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1281 {
1282 int value = 0;
1283
1284 value |= ((insn >> 6) & 0x003f) << 0;
1285 value |= ((insn >> 0) & 0x003f) << 6;
1286
1287 return value;
1288 }
1289
1290 /* Include the generic extract/insert functions. Order is important
1291 as some of the functions present in the .h may be disabled via
1292 defines. */
1293 #include "arc-fxi.h"
1294
1295 /* The flag operands table.
1296
1297 The format of the table is
1298 NAME CODE BITS SHIFT FAVAIL. */
1299 const struct arc_flag_operand arc_flag_operands[] =
1300 {
1301 #define F_NULL 0
1302 { 0, 0, 0, 0, 0},
1303 #define F_ALWAYS (F_NULL + 1)
1304 { "al", 0, 0, 0, 0 },
1305 #define F_RA (F_ALWAYS + 1)
1306 { "ra", 0, 0, 0, 0 },
1307 #define F_EQUAL (F_RA + 1)
1308 { "eq", 1, 5, 0, 1 },
1309 #define F_ZERO (F_EQUAL + 1)
1310 { "z", 1, 5, 0, 0 },
1311 #define F_NOTEQUAL (F_ZERO + 1)
1312 { "ne", 2, 5, 0, 1 },
1313 #define F_NOTZERO (F_NOTEQUAL + 1)
1314 { "nz", 2, 5, 0, 0 },
1315 #define F_POZITIVE (F_NOTZERO + 1)
1316 { "p", 3, 5, 0, 1 },
1317 #define F_PL (F_POZITIVE + 1)
1318 { "pl", 3, 5, 0, 0 },
1319 #define F_NEGATIVE (F_PL + 1)
1320 { "n", 4, 5, 0, 1 },
1321 #define F_MINUS (F_NEGATIVE + 1)
1322 { "mi", 4, 5, 0, 0 },
1323 #define F_CARRY (F_MINUS + 1)
1324 { "c", 5, 5, 0, 1 },
1325 #define F_CARRYSET (F_CARRY + 1)
1326 { "cs", 5, 5, 0, 0 },
1327 #define F_LOWER (F_CARRYSET + 1)
1328 { "lo", 5, 5, 0, 0 },
1329 #define F_CARRYCLR (F_LOWER + 1)
1330 { "cc", 6, 5, 0, 0 },
1331 #define F_NOTCARRY (F_CARRYCLR + 1)
1332 { "nc", 6, 5, 0, 1 },
1333 #define F_HIGHER (F_NOTCARRY + 1)
1334 { "hs", 6, 5, 0, 0 },
1335 #define F_OVERFLOWSET (F_HIGHER + 1)
1336 { "vs", 7, 5, 0, 0 },
1337 #define F_OVERFLOW (F_OVERFLOWSET + 1)
1338 { "v", 7, 5, 0, 1 },
1339 #define F_NOTOVERFLOW (F_OVERFLOW + 1)
1340 { "nv", 8, 5, 0, 1 },
1341 #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
1342 { "vc", 8, 5, 0, 0 },
1343 #define F_GT (F_OVERFLOWCLR + 1)
1344 { "gt", 9, 5, 0, 1 },
1345 #define F_GE (F_GT + 1)
1346 { "ge", 10, 5, 0, 1 },
1347 #define F_LT (F_GE + 1)
1348 { "lt", 11, 5, 0, 1 },
1349 #define F_LE (F_LT + 1)
1350 { "le", 12, 5, 0, 1 },
1351 #define F_HI (F_LE + 1)
1352 { "hi", 13, 5, 0, 1 },
1353 #define F_LS (F_HI + 1)
1354 { "ls", 14, 5, 0, 1 },
1355 #define F_PNZ (F_LS + 1)
1356 { "pnz", 15, 5, 0, 1 },
1357 #define F_NJ (F_PNZ + 1)
1358 { "nj", 21, 5, 0, 1 },
1359 #define F_NM (F_NJ + 1)
1360 { "nm", 23, 5, 0, 1 },
1361 #define F_NO_T (F_NM + 1)
1362 { "nt", 24, 5, 0, 1 },
1363
1364 /* FLAG. */
1365 #define F_FLAG (F_NO_T + 1)
1366 { "f", 1, 1, 15, 1 },
1367 #define F_FFAKE (F_FLAG + 1)
1368 { "f", 0, 0, 0, 1 },
1369
1370 /* Delay slot. */
1371 #define F_ND (F_FFAKE + 1)
1372 { "nd", 0, 1, 5, 0 },
1373 #define F_D (F_ND + 1)
1374 { "d", 1, 1, 5, 1 },
1375 #define F_DFAKE (F_D + 1)
1376 { "d", 0, 0, 0, 1 },
1377 #define F_DNZ_ND (F_DFAKE + 1)
1378 { "nd", 0, 1, 16, 0 },
1379 #define F_DNZ_D (F_DNZ_ND + 1)
1380 { "d", 1, 1, 16, 1 },
1381
1382 /* Data size. */
1383 #define F_SIZEB1 (F_DNZ_D + 1)
1384 { "b", 1, 2, 1, 1 },
1385 #define F_SIZEB7 (F_SIZEB1 + 1)
1386 { "b", 1, 2, 7, 1 },
1387 #define F_SIZEB17 (F_SIZEB7 + 1)
1388 { "b", 1, 2, 17, 1 },
1389 #define F_SIZEW1 (F_SIZEB17 + 1)
1390 { "w", 2, 2, 1, 0 },
1391 #define F_SIZEW7 (F_SIZEW1 + 1)
1392 { "w", 2, 2, 7, 0 },
1393 #define F_SIZEW17 (F_SIZEW7 + 1)
1394 { "w", 2, 2, 17, 0 },
1395
1396 /* Sign extension. */
1397 #define F_SIGN6 (F_SIZEW17 + 1)
1398 { "x", 1, 1, 6, 1 },
1399 #define F_SIGN16 (F_SIGN6 + 1)
1400 { "x", 1, 1, 16, 1 },
1401 #define F_SIGNX (F_SIGN16 + 1)
1402 { "x", 0, 0, 0, 1 },
1403
1404 /* Address write-back modes. */
1405 #define F_A3 (F_SIGNX + 1)
1406 { "a", 1, 2, 3, 0 },
1407 #define F_A9 (F_A3 + 1)
1408 { "a", 1, 2, 9, 0 },
1409 #define F_A22 (F_A9 + 1)
1410 { "a", 1, 2, 22, 0 },
1411 #define F_AW3 (F_A22 + 1)
1412 { "aw", 1, 2, 3, 1 },
1413 #define F_AW9 (F_AW3 + 1)
1414 { "aw", 1, 2, 9, 1 },
1415 #define F_AW22 (F_AW9 + 1)
1416 { "aw", 1, 2, 22, 1 },
1417 #define F_AB3 (F_AW22 + 1)
1418 { "ab", 2, 2, 3, 1 },
1419 #define F_AB9 (F_AB3 + 1)
1420 { "ab", 2, 2, 9, 1 },
1421 #define F_AB22 (F_AB9 + 1)
1422 { "ab", 2, 2, 22, 1 },
1423 #define F_AS3 (F_AB22 + 1)
1424 { "as", 3, 2, 3, 1 },
1425 #define F_AS9 (F_AS3 + 1)
1426 { "as", 3, 2, 9, 1 },
1427 #define F_AS22 (F_AS9 + 1)
1428 { "as", 3, 2, 22, 1 },
1429 #define F_ASFAKE (F_AS22 + 1)
1430 { "as", 0, 0, 0, 1 },
1431
1432 /* Cache bypass. */
1433 #define F_DI5 (F_ASFAKE + 1)
1434 { "di", 1, 1, 5, 1 },
1435 #define F_DI11 (F_DI5 + 1)
1436 { "di", 1, 1, 11, 1 },
1437 #define F_DI14 (F_DI11 + 1)
1438 { "di", 1, 1, 14, 1 },
1439 #define F_DI15 (F_DI14 + 1)
1440 { "di", 1, 1, 15, 1 },
1441
1442 /* ARCv2 specific. */
1443 #define F_NT (F_DI15 + 1)
1444 { "nt", 0, 1, 3, 1},
1445 #define F_T (F_NT + 1)
1446 { "t", 1, 1, 3, 1},
1447 #define F_H1 (F_T + 1)
1448 { "h", 2, 2, 1, 1 },
1449 #define F_H7 (F_H1 + 1)
1450 { "h", 2, 2, 7, 1 },
1451 #define F_H17 (F_H7 + 1)
1452 { "h", 2, 2, 17, 1 },
1453 #define F_SIZED (F_H17 + 1)
1454 { "dd", 8, 0, 0, 0 }, /* Fake. */
1455
1456 /* Fake Flags. */
1457 #define F_NE (F_SIZED + 1)
1458 { "ne", 0, 0, 0, 1 },
1459
1460 /* ARC NPS400 Support: See comment near head of file. */
1461 #define F_NPS_CL (F_NE + 1)
1462 { "cl", 0, 0, 0, 1 },
1463
1464 #define F_NPS_NA (F_NPS_CL + 1)
1465 { "na", 1, 1, 9, 1 },
1466
1467 #define F_NPS_SR (F_NPS_NA + 1)
1468 { "s", 1, 1, 13, 1 },
1469
1470 #define F_NPS_M (F_NPS_SR + 1)
1471 { "m", 1, 1, 7, 1 },
1472
1473 #define F_NPS_FLAG (F_NPS_M + 1)
1474 { "f", 1, 1, 20, 1 },
1475
1476 #define F_NPS_R (F_NPS_FLAG + 1)
1477 { "r", 1, 1, 15, 1 },
1478
1479 #define F_NPS_RW (F_NPS_R + 1)
1480 { "rw", 0, 1, 7, 1 },
1481
1482 #define F_NPS_RD (F_NPS_RW + 1)
1483 { "rd", 1, 1, 7, 1 },
1484
1485 #define F_NPS_WFT (F_NPS_RD + 1)
1486 { "wft", 0, 0, 0, 1 },
1487
1488 #define F_NPS_IE1 (F_NPS_WFT + 1)
1489 { "ie1", 1, 2, 8, 1 },
1490
1491 #define F_NPS_IE2 (F_NPS_IE1 + 1)
1492 { "ie2", 2, 2, 8, 1 },
1493
1494 #define F_NPS_IE12 (F_NPS_IE2 + 1)
1495 { "ie12", 3, 2, 8, 1 },
1496
1497 #define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1498 { "rd", 0, 1, 6, 1 },
1499
1500 #define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1501 { "wr", 1, 1, 6, 1 },
1502
1503 #define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1504 { "off", 0, 0, 0, 1 },
1505
1506 #define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1507 { "restore", 0, 0, 0, 1 },
1508
1509 #define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
1510 { "sx", 1, 1, 14, 1 },
1511
1512 #define F_NPS_AR (F_NPS_SX + 1)
1513 { "ar", 0, 1, 0, 1 },
1514
1515 #define F_NPS_AL (F_NPS_AR + 1)
1516 { "al", 1, 1, 0, 1 },
1517
1518 #define F_NPS_S (F_NPS_AL + 1)
1519 { "s", 0, 0, 0, 1 },
1520
1521 #define F_NPS_ZNCV_RD (F_NPS_S + 1)
1522 { "rd", 0, 1, 15, 1 },
1523
1524 #define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1)
1525 { "wr", 1, 1, 15, 1 },
1526
1527 #define F_NPS_P0 (F_NPS_ZNCV_WR + 1)
1528 { "p0", 0, 0, 0, 1 },
1529
1530 #define F_NPS_P1 (F_NPS_P0 + 1)
1531 { "p1", 0, 0, 0, 1 },
1532
1533 #define F_NPS_P2 (F_NPS_P1 + 1)
1534 { "p2", 0, 0, 0, 1 },
1535
1536 #define F_NPS_P3 (F_NPS_P2 + 1)
1537 { "p3", 0, 0, 0, 1 },
1538
1539 #define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
1540 { "di", 0, 0, 0, 1 },
1541
1542 #define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
1543 { "cl", 1, 1, 6, 1 },
1544
1545 #define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
1546 { "cl", 1, 1, 16, 1 },
1547
1548 #define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
1549 { "x2", 1, 2, 9, 1 },
1550
1551 #define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
1552 { "x2", 1, 2, 22, 1 },
1553
1554 #define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
1555 { "x4", 2, 2, 9, 1 },
1556
1557 #define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
1558 { "x4", 2, 2, 22, 1 },
1559
1560 #define F_NPS_CORE (F_NPS_LDBIT_X4_2 + 1)
1561 { "core", 1, 3, 6, 1 },
1562
1563 #define F_NPS_CLSR (F_NPS_CORE + 1)
1564 { "clsr", 2, 3, 6, 1 },
1565
1566 #define F_NPS_ALL (F_NPS_CLSR + 1)
1567 { "all", 3, 3, 6, 1 },
1568
1569 #define F_NPS_GIC (F_NPS_ALL + 1)
1570 { "gic", 4, 3, 6, 1 },
1571
1572 #define F_NPS_RSPI_GIC (F_NPS_GIC + 1)
1573 { "gic", 5, 3, 6, 1 },
1574 };
1575
1576 const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
1577
1578 /* Table of the flag classes.
1579
1580 The format of the table is
1581 CLASS {FLAG_CODE}. */
1582 const struct arc_flag_class arc_flag_classes[] =
1583 {
1584 #define C_EMPTY 0
1585 { F_CLASS_NONE, { F_NULL } },
1586
1587 #define C_CC_EQ (C_EMPTY + 1)
1588 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} },
1589
1590 #define C_CC_GE (C_CC_EQ + 1)
1591 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} },
1592
1593 #define C_CC_GT (C_CC_GE + 1)
1594 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} },
1595
1596 #define C_CC_HI (C_CC_GT + 1)
1597 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} },
1598
1599 #define C_CC_HS (C_CC_HI + 1)
1600 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} },
1601
1602 #define C_CC_LE (C_CC_HS + 1)
1603 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} },
1604
1605 #define C_CC_LO (C_CC_LE + 1)
1606 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} },
1607
1608 #define C_CC_LS (C_CC_LO + 1)
1609 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} },
1610
1611 #define C_CC_LT (C_CC_LS + 1)
1612 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} },
1613
1614 #define C_CC_NE (C_CC_LT + 1)
1615 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} },
1616
1617 #define C_AA_AB (C_CC_NE + 1)
1618 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} },
1619
1620 #define C_AA_AW (C_AA_AB + 1)
1621 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} },
1622
1623 #define C_ZZ_D (C_AA_AW + 1)
1624 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} },
1625
1626 #define C_ZZ_H (C_ZZ_D + 1)
1627 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} },
1628
1629 #define C_ZZ_B (C_ZZ_H + 1)
1630 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} },
1631
1632 #define C_CC (C_ZZ_B + 1)
1633 { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
1634 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1635 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1636 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1637 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1638 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
1639 F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL } },
1640
1641 #define C_AA_ADDR3 (C_CC + 1)
1642 #define C_AA27 (C_CC + 1)
1643 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
1644 #define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1645 #define C_AA21 (C_AA_ADDR3 + 1)
1646 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
1647 #define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1648 #define C_AA8 (C_AA_ADDR9 + 1)
1649 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
1650
1651 #define C_F (C_AA_ADDR22 + 1)
1652 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
1653 #define C_FHARD (C_F + 1)
1654 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
1655
1656 #define C_T (C_FHARD + 1)
1657 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
1658 #define C_D (C_T + 1)
1659 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
1660 #define C_DNZ_D (C_D + 1)
1661 { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } },
1662
1663 #define C_DHARD (C_DNZ_D + 1)
1664 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
1665
1666 #define C_DI20 (C_DHARD + 1)
1667 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
1668 #define C_DI14 (C_DI20 + 1)
1669 { F_CLASS_OPTIONAL, { F_DI14, F_NULL }},
1670 #define C_DI16 (C_DI14 + 1)
1671 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
1672 #define C_DI26 (C_DI16 + 1)
1673 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
1674
1675 #define C_X25 (C_DI26 + 1)
1676 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
1677 #define C_X15 (C_X25 + 1)
1678 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
1679 #define C_XHARD (C_X15 + 1)
1680 #define C_X (C_X15 + 1)
1681 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
1682
1683 #define C_ZZ13 (C_X + 1)
1684 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
1685 #define C_ZZ23 (C_ZZ13 + 1)
1686 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
1687 #define C_ZZ29 (C_ZZ23 + 1)
1688 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
1689
1690 #define C_AS (C_ZZ29 + 1)
1691 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
1692
1693 #define C_NE (C_AS + 1)
1694 { F_CLASS_REQUIRED, { F_NE, F_NULL}},
1695
1696 /* ARC NPS400 Support: See comment near head of file. */
1697 #define C_NPS_CL (C_NE + 1)
1698 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1699
1700 #define C_NPS_NA (C_NPS_CL + 1)
1701 { F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}},
1702
1703 #define C_NPS_SR (C_NPS_NA + 1)
1704 { F_CLASS_OPTIONAL, { F_NPS_SR, F_NULL}},
1705
1706 #define C_NPS_M (C_NPS_SR + 1)
1707 { F_CLASS_OPTIONAL, { F_NPS_M, F_NULL}},
1708
1709 #define C_NPS_F (C_NPS_M + 1)
1710 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
1711
1712 #define C_NPS_R (C_NPS_F + 1)
1713 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
1714
1715 #define C_NPS_SCHD_RW (C_NPS_R + 1)
1716 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
1717
1718 #define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1719 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
1720
1721 #define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1722 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
1723
1724 #define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1725 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
1726
1727 #define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1728 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
1729
1730 #define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1731 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
1732
1733 #define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
1734 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
1735
1736 #define C_NPS_AR_AL (C_NPS_SX + 1)
1737 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
1738
1739 #define C_NPS_S (C_NPS_AR_AL + 1)
1740 { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
1741
1742 #define C_NPS_ZNCV (C_NPS_S + 1)
1743 { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
1744
1745 #define C_NPS_P0 (C_NPS_ZNCV + 1)
1746 { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }},
1747
1748 #define C_NPS_P1 (C_NPS_P0 + 1)
1749 { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }},
1750
1751 #define C_NPS_P2 (C_NPS_P1 + 1)
1752 { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }},
1753
1754 #define C_NPS_P3 (C_NPS_P2 + 1)
1755 { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
1756
1757 #define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
1758 { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
1759
1760 #define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
1761 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
1762
1763 #define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
1764 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
1765
1766 #define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
1767 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
1768
1769 #define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
1770 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
1771
1772 #define C_NPS_CORE (C_NPS_LDBIT_X_2 + 1)
1773 { F_CLASS_REQUIRED, { F_NPS_CORE, F_NULL}},
1774
1775 #define C_NPS_CLSR (C_NPS_CORE + 1)
1776 { F_CLASS_REQUIRED, { F_NPS_CLSR, F_NULL}},
1777
1778 #define C_NPS_ALL (C_NPS_CLSR + 1)
1779 { F_CLASS_REQUIRED, { F_NPS_ALL, F_NULL}},
1780
1781 #define C_NPS_GIC (C_NPS_ALL + 1)
1782 { F_CLASS_REQUIRED, { F_NPS_GIC, F_NULL}},
1783
1784 #define C_NPS_RSPI_GIC (C_NPS_GIC + 1)
1785 { F_CLASS_REQUIRED, { F_NPS_RSPI_GIC, F_NULL}},
1786 };
1787
1788 const unsigned char flags_none[] = { 0 };
1789 const unsigned char flags_f[] = { C_F };
1790 const unsigned char flags_cc[] = { C_CC };
1791 const unsigned char flags_ccf[] = { C_CC, C_F };
1792
1793 /* The operands table.
1794
1795 The format of the operands table is:
1796
1797 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1798 const struct arc_operand arc_operands[] =
1799 {
1800 /* The fields are bits, shift, insert, extract, flags. The zero
1801 index is used to indicate end-of-list. */
1802 #define UNUSED 0
1803 { 0, 0, 0, 0, 0, 0 },
1804
1805 #define IGNORED (UNUSED + 1)
1806 { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
1807
1808 /* The plain integer register fields. Used by 32 bit
1809 instructions. */
1810 #define RA (IGNORED + 1)
1811 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
1812 #define RA_CHK (RA + 1)
1813 { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 },
1814 #define RB (RA_CHK + 1)
1815 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
1816 #define RB_CHK (RB + 1)
1817 { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb },
1818 #define RC (RB_CHK + 1)
1819 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1820 #define RBdup (RC + 1)
1821 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1822
1823 #define RAD (RBdup + 1)
1824 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1825 #define RAD_CHK (RAD + 1)
1826 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1827 #define RCD (RAD_CHK + 1)
1828 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1829
1830 /* The plain integer register fields. Used by short
1831 instructions. */
1832 #define RA16 (RCD + 1)
1833 #define RA_S (RCD + 1)
1834 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1835 #define RB16 (RA16 + 1)
1836 #define RB_S (RA16 + 1)
1837 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1838 #define RB16dup (RB16 + 1)
1839 #define RB_Sdup (RB16 + 1)
1840 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1841 #define RC16 (RB16dup + 1)
1842 #define RC_S (RB16dup + 1)
1843 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1844 #define R6H (RC16 + 1) /* 6bit register field 'h' used
1845 by V1 cpus. */
1846 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1847 #define R5H (R6H + 1) /* 5bit register field 'h' used
1848 by V2 cpus. */
1849 #define RH_S (R6H + 1) /* 5bit register field 'h' used
1850 by V2 cpus. */
1851 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1852 #define R5Hdup (R5H + 1)
1853 #define RH_Sdup (R5H + 1)
1854 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1855 insert_rhv2, extract_rhv2 },
1856
1857 #define RG (R5Hdup + 1)
1858 #define G_S (R5Hdup + 1)
1859 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1860
1861 /* Fix registers. */
1862 #define R0 (RG + 1)
1863 #define R0_S (RG + 1)
1864 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1865 #define R1 (R0 + 1)
1866 #define R1_S (R0 + 1)
1867 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1868 #define R2 (R1 + 1)
1869 #define R2_S (R1 + 1)
1870 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1871 #define R3 (R2 + 1)
1872 #define R3_S (R2 + 1)
1873 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
1874 #define RSP (R3 + 1)
1875 #define SP_S (R3 + 1)
1876 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
1877 #define SPdup (RSP + 1)
1878 #define SP_Sdup (RSP + 1)
1879 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1880 #define GP (SPdup + 1)
1881 #define GP_S (SPdup + 1)
1882 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1883
1884 #define PCL_S (GP + 1)
1885 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1886
1887 #define BLINK (PCL_S + 1)
1888 #define BLINK_S (PCL_S + 1)
1889 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1890
1891 #define ILINK1 (BLINK + 1)
1892 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1893 #define ILINK2 (ILINK1 + 1)
1894 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1895
1896 /* Long immediate. */
1897 #define LIMM (ILINK2 + 1)
1898 #define LIMM_S (ILINK2 + 1)
1899 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1900 #define LIMMdup (LIMM + 1)
1901 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1902
1903 /* Special operands. */
1904 #define ZA (LIMMdup + 1)
1905 #define ZB (LIMMdup + 1)
1906 #define ZA_S (LIMMdup + 1)
1907 #define ZB_S (LIMMdup + 1)
1908 #define ZC_S (LIMMdup + 1)
1909 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1910
1911 #define RRANGE_EL (ZA + 1)
1912 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1913 insert_rrange, extract_rrange},
1914 #define R13_EL (RRANGE_EL + 1)
1915 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1916 insert_r13el, extract_rrange },
1917 #define FP_EL (R13_EL + 1)
1918 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1919 insert_fpel, extract_fpel },
1920 #define BLINK_EL (FP_EL + 1)
1921 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1922 insert_blinkel, extract_blinkel },
1923 #define PCL_EL (BLINK_EL + 1)
1924 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1925 insert_pclel, extract_pclel },
1926
1927 /* Fake operand to handle the T flag. */
1928 #define BRAKET (PCL_EL + 1)
1929 #define BRAKETdup (PCL_EL + 1)
1930 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1931
1932 /* Fake operand to handle the T flag. */
1933 #define FKT_T (BRAKET + 1)
1934 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1935 /* Fake operand to handle the T flag. */
1936 #define FKT_NT (FKT_T + 1)
1937 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1938
1939 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1940 #define UIMM6_20 (FKT_NT + 1)
1941 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1942
1943 /* Exactly like the above but used by relaxation. */
1944 #define UIMM6_20R (UIMM6_20 + 1)
1945 {6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
1946 insert_uimm6_20, extract_uimm6_20},
1947
1948 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1949 #define SIMM12_20 (UIMM6_20R + 1)
1950 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1951
1952 /* Exactly like the above but used by relaxation. */
1953 #define SIMM12_20R (SIMM12_20 + 1)
1954 {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL,
1955 insert_simm12_20, extract_simm12_20},
1956
1957 /* UIMM12_20 mask = 00000000000000000000111111222222. */
1958 #define UIMM12_20 (SIMM12_20R + 1)
1959 {12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20},
1960
1961 /* SIMM3_5_S mask = 0000011100000000. */
1962 #define SIMM3_5_S (UIMM12_20 + 1)
1963 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1964 insert_simm3s, extract_simm3s},
1965
1966 /* UIMM7_A32_11_S mask = 0000000000011111. */
1967 #define UIMM7_A32_11_S (SIMM3_5_S + 1)
1968 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1969 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1970 extract_uimm7_a32_11_s},
1971
1972 /* The same as above but used by relaxation. */
1973 #define UIMM7_A32_11R_S (UIMM7_A32_11_S + 1)
1974 {7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1975 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL,
1976 insert_uimm7_a32_11_s, extract_uimm7_a32_11_s},
1977
1978 /* UIMM7_9_S mask = 0000000001111111. */
1979 #define UIMM7_9_S (UIMM7_A32_11R_S + 1)
1980 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1981
1982 /* UIMM3_13_S mask = 0000000000000111. */
1983 #define UIMM3_13_S (UIMM7_9_S + 1)
1984 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1985
1986 /* Exactly like the above but used for relaxation. */
1987 #define UIMM3_13R_S (UIMM3_13_S + 1)
1988 {3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
1989 insert_uimm3_13_s, extract_uimm3_13_s},
1990
1991 /* SIMM11_A32_7_S mask = 0000000111111111. */
1992 #define SIMM11_A32_7_S (UIMM3_13R_S + 1)
1993 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1994 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1995
1996 /* UIMM6_13_S mask = 0000000002220111. */
1997 #define UIMM6_13_S (SIMM11_A32_7_S + 1)
1998 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1999 /* UIMM5_11_S mask = 0000000000011111. */
2000 #define UIMM5_11_S (UIMM6_13_S + 1)
2001 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
2002 extract_uimm5_11_s},
2003
2004 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
2005 #define SIMM9_A16_8 (UIMM5_11_S + 1)
2006 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2007 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
2008 extract_simm9_a16_8},
2009
2010 /* UIMM6_8 mask = 00000000000000000000111111000000. */
2011 #define UIMM6_8 (SIMM9_A16_8 + 1)
2012 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
2013
2014 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
2015 #define SIMM21_A16_5 (UIMM6_8 + 1)
2016 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
2017 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
2018 insert_simm21_a16_5, extract_simm21_a16_5},
2019
2020 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
2021 #define SIMM25_A16_5 (SIMM21_A16_5 + 1)
2022 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
2023 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
2024 insert_simm25_a16_5, extract_simm25_a16_5},
2025
2026 /* SIMM10_A16_7_S mask = 0000000111111111. */
2027 #define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
2028 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2029 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
2030 extract_simm10_a16_7_s},
2031
2032 #define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
2033 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2034 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
2035
2036 /* SIMM7_A16_10_S mask = 0000000000111111. */
2037 #define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
2038 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2039 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
2040 extract_simm7_a16_10_s},
2041
2042 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
2043 #define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
2044 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2045 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
2046 extract_simm21_a32_5},
2047
2048 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
2049 #define SIMM25_A32_5 (SIMM21_A32_5 + 1)
2050 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2051 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
2052 extract_simm25_a32_5},
2053
2054 /* SIMM13_A32_5_S mask = 0000011111111111. */
2055 #define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
2056 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2057 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
2058 extract_simm13_a32_5_s},
2059
2060 /* SIMM8_A16_9_S mask = 0000000001111111. */
2061 #define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
2062 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2063 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
2064 extract_simm8_a16_9_s},
2065
2066 /* UIMM10_6_S_JLIOFF mask = 0000001111111111. */
2067 #define UIMM10_6_S_JLIOFF (SIMM8_A16_9_S + 1)
2068 {12, 0, BFD_RELOC_ARC_JLI_SECTOFF, ARC_OPERAND_UNSIGNED
2069 | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_uimm10_6_s,
2070 extract_uimm10_6_s},
2071
2072 /* UIMM3_23 mask = 00000000000000000000000111000000. */
2073 #define UIMM3_23 (UIMM10_6_S_JLIOFF + 1)
2074 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
2075
2076 /* UIMM10_6_S mask = 0000001111111111. */
2077 #define UIMM10_6_S (UIMM3_23 + 1)
2078 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
2079
2080 /* UIMM6_11_S mask = 0000002200011110. */
2081 #define UIMM6_11_S (UIMM10_6_S + 1)
2082 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
2083
2084 /* SIMM9_8 mask = 00000000111111112000000000000000. */
2085 #define SIMM9_8 (UIMM6_11_S + 1)
2086 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
2087 insert_simm9_8, extract_simm9_8},
2088
2089 /* The same as above but used by relaxation. */
2090 #define SIMM9_8R (SIMM9_8 + 1)
2091 {9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE
2092 | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8},
2093
2094 /* UIMM10_A32_8_S mask = 0000000011111111. */
2095 #define UIMM10_A32_8_S (SIMM9_8R + 1)
2096 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
2097 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
2098 extract_uimm10_a32_8_s},
2099
2100 /* SIMM9_7_S mask = 0000000111111111. */
2101 #define SIMM9_7_S (UIMM10_A32_8_S + 1)
2102 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
2103 extract_simm9_7_s},
2104
2105 /* UIMM6_A16_11_S mask = 0000000000011111. */
2106 #define UIMM6_A16_11_S (SIMM9_7_S + 1)
2107 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
2108 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
2109 extract_uimm6_a16_11_s},
2110
2111 /* UIMM5_A32_11_S mask = 0000020000011000. */
2112 #define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
2113 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
2114 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
2115 extract_uimm5_a32_11_s},
2116
2117 /* SIMM11_A32_13_S mask = 0000022222200111. */
2118 #define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
2119 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2120 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
2121
2122 /* UIMM7_13_S mask = 0000000022220111. */
2123 #define UIMM7_13_S (SIMM11_A32_13_S + 1)
2124 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
2125
2126 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
2127 #define UIMM6_A16_21 (UIMM7_13_S + 1)
2128 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
2129 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
2130
2131 /* UIMM7_11_S mask = 0000022200011110. */
2132 #define UIMM7_11_S (UIMM6_A16_21 + 1)
2133 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
2134
2135 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
2136 #define UIMM7_A16_20 (UIMM7_11_S + 1)
2137 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
2138 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
2139 extract_uimm7_a16_20},
2140
2141 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
2142 #define SIMM13_A16_20 (UIMM7_A16_20 + 1)
2143 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2144 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
2145 extract_simm13_a16_20},
2146
2147 /* UIMM8_8_S mask = 0000000011111111. */
2148 #define UIMM8_8_S (SIMM13_A16_20 + 1)
2149 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
2150
2151 /* The same as above but used for relaxation. */
2152 #define UIMM8_8R_S (UIMM8_8_S + 1)
2153 {8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
2154 insert_uimm8_8_s, extract_uimm8_8_s},
2155
2156 /* W6 mask = 00000000000000000000111111000000. */
2157 #define W6 (UIMM8_8R_S + 1)
2158 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
2159
2160 /* UIMM6_5_S mask = 0000011111100000. */
2161 #define UIMM6_5_S (W6 + 1)
2162 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
2163
2164 /* ARC NPS400 Support: See comment near head of file. */
2165 #define NPS_R_DST_3B (UIMM6_5_S + 1)
2166 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2167 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
2168
2169 #define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
2170 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2171 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
2172
2173 #define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
2174 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2175 insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 },
2176
2177 #define NPS_R_DST (NPS_R_SRC2_3B + 1)
2178 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
2179
2180 #define NPS_R_SRC1 (NPS_R_DST + 1)
2181 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
2182
2183 #define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
2184 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
2185
2186 #define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
2187 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
2188
2189 #define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
2190 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2191 insert_nps_bitop_size, extract_nps_bitop_size },
2192
2193 #define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
2194 { 5, 0, 0, ARC_OPERAND_UNSIGNED,
2195 insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
2196
2197 #define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
2198 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2199 insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
2200
2201 #define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
2202 { 8, 0, 0, ARC_OPERAND_UNSIGNED,
2203 insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
2204
2205 #define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
2206 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2207
2208 #define NPS_SIMM16 (NPS_UIMM16 + 1)
2209 { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
2210
2211 #define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
2212 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2213 insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
2214
2215 #define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
2216 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2217 insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
2218
2219 #define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
2220 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2221 insert_nps_src2_pos, extract_nps_src2_pos },
2222
2223 #define NPS_SRC1_POS (NPS_SRC2_POS + 1)
2224 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2225 insert_nps_src1_pos, extract_nps_src1_pos },
2226
2227 #define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
2228 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2229 insert_nps_addb_size, extract_nps_addb_size },
2230
2231 #define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
2232 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2233 insert_nps_andb_size, extract_nps_andb_size },
2234
2235 #define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
2236 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2237 insert_nps_fxorb_size, extract_nps_fxorb_size },
2238
2239 #define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
2240 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2241 insert_nps_wxorb_size, extract_nps_wxorb_size },
2242
2243 #define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
2244 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
2245
2246 #define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
2247 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2248
2249 #define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
2250 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2251 insert_nps_qcmp_size, extract_nps_qcmp_size },
2252
2253 #define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
2254 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
2255
2256 #define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
2257 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
2258
2259 #define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
2260 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
2261
2262 #define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
2263 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2264 insert_nps_calc_entry_size, extract_nps_calc_entry_size },
2265
2266 #define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
2267 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2268 insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
2269
2270 #define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
2271 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2272 insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
2273
2274 #define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
2275 { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2276 insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 },
2277
2278 #define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
2279 { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2280 insert_nps_bitop2_size, extract_nps_bitop2_size },
2281
2282 #define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
2283 { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2284 insert_nps_bitop1_size, extract_nps_bitop1_size },
2285
2286 #define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
2287 { 5, 0, 0, ARC_OPERAND_UNSIGNED,
2288 insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 },
2289
2290 #define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
2291 { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2292
2293 #define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
2294 { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2295
2296 #define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
2297 { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2298
2299 #define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
2300 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2301
2302 #define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
2303 { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2304
2305 #define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
2306 { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2307
2308 #define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
2309 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2310
2311 #define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
2312 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2313
2314 #define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1)
2315 { 2, 0, 0, ARC_OPERAND_UNSIGNED,
2316 insert_nps_bitop_mod4, extract_nps_bitop_mod4 },
2317
2318 #define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1)
2319 { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2320
2321 #define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
2322 { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2323
2324 #define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
2325 { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2326
2327 #define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
2328 { 5, 20, 0, ARC_OPERAND_UNSIGNED,
2329 insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
2330
2331 #define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1)
2332 { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2333
2334 #define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1)
2335 { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2336 insert_nps_field_size, extract_nps_field_size },
2337
2338 #define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1)
2339 { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2340 insert_nps_shift_factor, extract_nps_shift_factor },
2341
2342 #define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1)
2343 { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2344 insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
2345
2346 #define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1)
2347 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2348
2349 #define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1)
2350 { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2351 insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
2352
2353 #define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1)
2354 { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2355 insert_nps_min_hofs, extract_nps_min_hofs },
2356
2357 #define NPS_PSBC (NPS_MIN_HOFS + 1)
2358 { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2359
2360 #define NPS_DPI_DST (NPS_PSBC + 1)
2361 { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL },
2362
2363 /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B
2364 but doesn't duplicate an operand. */
2365 #define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1)
2366 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2367 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
2368
2369 #define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1)
2370 { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2371 insert_nps_hash_width, extract_nps_hash_width },
2372
2373 #define NPS_HASH_PERM (NPS_HASH_WIDTH + 1)
2374 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2375
2376 #define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1)
2377 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2378
2379 #define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1)
2380 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2381
2382 #define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1)
2383 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2384 insert_nps_hash_len, extract_nps_hash_len },
2385
2386 #define NPS_HASH_OFS (NPS_HASH_LEN + 1)
2387 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2388
2389 #define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1)
2390 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2391
2392 #define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1)
2393 { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2394
2395 #define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1)
2396 { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2397
2398 #define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1)
2399 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2400
2401 #define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
2402 { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2403 insert_nps_index3, extract_nps_index3 },
2404
2405 #define COLON (NPS_E4BY_INDEX3 + 1)
2406 { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL },
2407
2408 #define NPS_BD (COLON + 1)
2409 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2410 insert_nps_bd, extract_nps_bd },
2411
2412 #define NPS_JID (NPS_BD + 1)
2413 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2414 insert_nps_jid, extract_nps_jid },
2415
2416 #define NPS_LBD (NPS_JID + 1)
2417 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2418 insert_nps_lbd, extract_nps_lbd },
2419
2420 #define NPS_MBD (NPS_LBD + 1)
2421 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2422 insert_nps_mbd, extract_nps_mbd },
2423
2424 #define NPS_SD (NPS_MBD + 1)
2425 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2426 insert_nps_sd, extract_nps_sd },
2427
2428 #define NPS_SM (NPS_SD + 1)
2429 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2430 insert_nps_sm, extract_nps_sm },
2431
2432 #define NPS_XA (NPS_SM + 1)
2433 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2434 insert_nps_xa, extract_nps_xa },
2435
2436 #define NPS_XD (NPS_XA + 1)
2437 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2438 insert_nps_xd, extract_nps_xd },
2439
2440 #define NPS_CD (NPS_XD + 1)
2441 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2442 insert_nps_cd, extract_nps_cd },
2443
2444 #define NPS_CBD (NPS_CD + 1)
2445 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2446 insert_nps_cbd, extract_nps_cbd },
2447
2448 #define NPS_CJID (NPS_CBD + 1)
2449 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2450 insert_nps_cjid, extract_nps_cjid },
2451
2452 #define NPS_CLBD (NPS_CJID + 1)
2453 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2454 insert_nps_clbd, extract_nps_clbd },
2455
2456 #define NPS_CM (NPS_CLBD + 1)
2457 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2458 insert_nps_cm, extract_nps_cm },
2459
2460 #define NPS_CSD (NPS_CM + 1)
2461 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2462 insert_nps_csd, extract_nps_csd },
2463
2464 #define NPS_CXA (NPS_CSD + 1)
2465 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2466 insert_nps_cxa, extract_nps_cxa },
2467
2468 #define NPS_CXD (NPS_CXA + 1)
2469 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2470 insert_nps_cxd, extract_nps_cxd },
2471
2472 #define NPS_BD_TYPE (NPS_CXD + 1)
2473 { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2474
2475 #define NPS_BMU_NUM (NPS_BD_TYPE + 1)
2476 { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2477 insert_nps_bd_num_buff, extract_nps_bd_num_buff },
2478
2479 #define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
2480 { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2481
2482 #define NPS_WHASH_SIZE (NPS_PMU_NXT_DST + 1)
2483 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2484 insert_nps_size_16bit, extract_nps_size_16bit },
2485
2486 #define NPS_PMU_NUM_JOB (NPS_WHASH_SIZE + 1)
2487 { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2488 insert_nps_pmu_num_job, extract_nps_pmu_num_job },
2489
2490 #define NPS_DMA_IMM_ENTRY (NPS_PMU_NUM_JOB + 1)
2491 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2492 insert_nps_imm_entry, extract_nps_imm_entry },
2493
2494 #define NPS_DMA_IMM_OFFSET (NPS_DMA_IMM_ENTRY + 1)
2495 { 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2496 insert_nps_imm_offset, extract_nps_imm_offset },
2497
2498 #define NPS_MISC_IMM_SIZE (NPS_DMA_IMM_OFFSET + 1)
2499 { 7, 0, 0, ARC_OPERAND_UNSIGNED , NULL, NULL },
2500
2501 #define NPS_MISC_IMM_OFFSET (NPS_MISC_IMM_SIZE + 1)
2502 { 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2503 insert_nps_misc_imm_offset, extract_nps_misc_imm_offset },
2504
2505 #define NPS_R_DST_3B_48 (NPS_MISC_IMM_OFFSET + 1)
2506 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2507 insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
2508
2509 #define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1)
2510 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2511 insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
2512
2513 #define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1)
2514 { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2515 insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 },
2516
2517 #define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1)
2518 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2519 insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
2520
2521 #define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1)
2522 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2523 insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
2524
2525 #define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1)
2526 { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2527 insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 },
2528
2529 #define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1)
2530 { 6, 53, 0, ARC_OPERAND_IR, NULL, NULL },
2531
2532 #define NPS_RB_64 (NPS_RA_64 + 1)
2533 { 5, 48, 0, ARC_OPERAND_IR, NULL, NULL },
2534
2535 #define NPS_RBdup_64 (NPS_RB_64 + 1)
2536 { 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
2537
2538 #define NPS_RBdouble_64 (NPS_RBdup_64 + 1)
2539 { 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2540 insert_nps_rbdouble_64, extract_nps_rbdouble_64 },
2541
2542 #define NPS_RC_64 (NPS_RBdouble_64 + 1)
2543 { 5, 43, 0, ARC_OPERAND_IR, NULL, NULL },
2544
2545 #define NPS_UIMM16_0_64 (NPS_RC_64 + 1)
2546 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2547
2548 #define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1)
2549 { 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2550 insert_nps_proto_size, extract_nps_proto_size }
2551 };
2552 const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
2553
2554 const unsigned arc_Toperand = FKT_T;
2555 const unsigned arc_NToperand = FKT_NT;
2556
2557 const unsigned char arg_none[] = { 0 };
2558 const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
2559 const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
2560 const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
2561 const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
2562 const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
2563 const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
2564 const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
2565 const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
2566 const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
2567 const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
2568 const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
2569
2570 const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
2571 const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
2572 const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
2573
2574 const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
2575 const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
2576 const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
2577
2578 const unsigned char arg_32bit_rbrc[] = { RB, RC };
2579 const unsigned char arg_32bit_zarc[] = { ZA, RC };
2580 const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
2581 const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
2582 const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
2583 const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
2584
2585 const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
2586 const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
2587 const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
2588 const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
2589
2590 const unsigned char arg_32bit_rc[] = { RC };
2591 const unsigned char arg_32bit_u6[] = { UIMM6_20 };
2592 const unsigned char arg_32bit_limm[] = { LIMM };
2593
2594 /* The opcode table.
2595
2596 The format of the opcode table is:
2597
2598 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
2599
2600 The table is organised such that, where possible, all instructions with
2601 the same mnemonic are together in a block. When the assembler searches
2602 for a suitable instruction the entries are checked in table order, so
2603 more specific, or specialised cases should appear earlier in the table.
2604
2605 As an example, consider two instructions 'add a,b,u6' and 'add
2606 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
2607 32-bit instruction, while the second takes a 32-bit immediate that is
2608 encoded in a follow-on 32-bit, making the total instruction length
2609 64-bits. In this case the u6 variant must appear first in the table, as
2610 all u6 immediates could also be encoded using the 'limm' extension,
2611 however, we want to use the shorter instruction wherever possible.
2612
2613 It is possible though to split instructions with the same mnemonic into
2614 multiple groups. However, the instructions are still checked in table
2615 order, even across groups. The only time that instructions with the
2616 same mnemonic should be split into different groups is when different
2617 variants of the instruction appear in different architectures, in which
2618 case, grouping all instructions from a particular architecture together
2619 might be preferable to merging the instruction into the main instruction
2620 table.
2621
2622 An example of this split instruction groups can be found with the 'sync'
2623 instruction. The core arc architecture provides a 'sync' instruction,
2624 while the nps instruction set extension provides 'sync.rd' and
2625 'sync.wr'. The rd/wr flags are instruction flags, not part of the
2626 mnemonic, so we end up with two groups for the sync instruction, the
2627 first within the core arc instruction table, and the second within the
2628 nps extension instructions. */
2629 const struct arc_opcode arc_opcodes[] =
2630 {
2631 #include "arc-tbl.h"
2632 #include "arc-nps400-tbl.h"
2633 #include "arc-ext-tbl.h"
2634
2635 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
2636 };
2637
2638 /* List with special cases instructions and the applicable flags. */
2639 const struct arc_flag_special arc_flag_special_cases[] =
2640 {
2641 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2642 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2643 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2644 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM,
2645 F_NO_T, F_NULL } },
2646 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2647 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2648 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2649 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2650 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2651 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2652 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2653 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2654 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2655 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2656 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2657 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2658 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2659 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2660 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2661 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2662 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2663 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2664 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2665 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2666 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2667 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2668 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2669 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2670 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
2671 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
2672 };
2673
2674 const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
2675
2676 /* Relocations. */
2677 const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
2678 {
2679 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
2680 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2681 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
2682 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2683 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
2684 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2685 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
2686 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2687
2688 /* Next two entries will cover the undefined behavior ldb/stb with
2689 address scaling. */
2690 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
2691 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2692 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
2693 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
2694
2695 { "sda", "ld", { F_ASFAKE, F_NULL },
2696 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2697 { "sda", "st", { F_ASFAKE, F_NULL },
2698 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2699 { "sda", "ldd", { F_ASFAKE, F_NULL },
2700 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2701 { "sda", "std", { F_ASFAKE, F_NULL },
2702 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2703
2704 /* Short instructions. */
2705 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
2706 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
2707 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
2708 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
2709
2710 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
2711 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2712
2713 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
2714 BFD_RELOC_ARC_S25H_PCREL_PLT },
2715 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
2716 BFD_RELOC_ARC_S21H_PCREL_PLT },
2717 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
2718 BFD_RELOC_ARC_S25W_PCREL_PLT },
2719 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
2720 BFD_RELOC_ARC_S21W_PCREL_PLT },
2721
2722 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
2723 };
2724
2725 const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
2726
2727 const struct arc_pseudo_insn arc_pseudo_insns[] =
2728 {
2729 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2730 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
2731 { BRAKETdup, 1, 0, 4} } },
2732 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2733 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
2734 { BRAKETdup, 1, 0, 4} } },
2735
2736 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2737 { SIMM9_A16_8, 0, 0, 2 } } },
2738 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2739 { SIMM9_A16_8, 0, 0, 2 } } },
2740 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2741 { SIMM9_A16_8, 0, 0, 2 } } },
2742 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2743 { SIMM9_A16_8, 0, 0, 2 } } },
2744 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2745 { SIMM9_A16_8, 0, 0, 2 } } },
2746
2747 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2748 { SIMM9_A16_8, 0, 0, 2 } } },
2749 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2750 { SIMM9_A16_8, 0, 0, 2 } } },
2751 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2752 { SIMM9_A16_8, 0, 0, 2 } } },
2753 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2754 { SIMM9_A16_8, 0, 0, 2 } } },
2755 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2756 { SIMM9_A16_8, 0, 0, 2 } } },
2757
2758 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2759 { SIMM9_A16_8, 0, 0, 2 } } },
2760 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2761 { SIMM9_A16_8, 0, 0, 2 } } },
2762 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2763 { SIMM9_A16_8, 0, 0, 2 } } },
2764 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2765 { SIMM9_A16_8, 0, 0, 2 } } },
2766 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2767 { SIMM9_A16_8, 0, 0, 2 } } },
2768
2769 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2770 { SIMM9_A16_8, 0, 0, 2 } } },
2771 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2772 { SIMM9_A16_8, 0, 0, 2 } } },
2773 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2774 { SIMM9_A16_8, 0, 0, 2 } } },
2775 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2776 { SIMM9_A16_8, 0, 0, 2 } } },
2777 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2778 { SIMM9_A16_8, 0, 0, 2 } } },
2779 };
2780
2781 const unsigned arc_num_pseudo_insn =
2782 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
2783
2784 const struct arc_aux_reg arc_aux_regs[] =
2785 {
2786 #undef DEF
2787 #define DEF(ADDR, CPU, SUBCLASS, NAME) \
2788 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
2789
2790 #include "arc-regs.h"
2791
2792 #undef DEF
2793 };
2794
2795 const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
2796
2797 /* NOTE: The order of this array MUST be consistent with 'enum
2798 arc_rlx_types' located in tc-arc.h! */
2799 const struct arc_opcode arc_relax_opcodes[] =
2800 {
2801 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
2802
2803 /* bl_s s13 11111sssssssssss. */
2804 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2805 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2806 { SIMM13_A32_5_S }, { 0 }},
2807
2808 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
2809 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2810 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2811 { SIMM25_A32_5 }, { C_D }},
2812
2813 /* b_s s10 1111000sssssssss. */
2814 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2815 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2816 { SIMM10_A16_7_S }, { 0 }},
2817
2818 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
2819 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2820 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2821 { SIMM25_A16_5 }, { C_D }},
2822
2823 /* add_s c,b,u3 01101bbbccc00uuu. */
2824 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2825 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2826 { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
2827
2828 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */
2829 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2830 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2831 { RA, RB, UIMM6_20R }, { C_F }},
2832
2833 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
2834 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2835 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2836 { RA, RB, LIMM }, { C_F }},
2837
2838 /* ld_s c,b,u7 10000bbbcccuuuuu. */
2839 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2840 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2841 { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }},
2842
2843 /* ld<.di><.aa><.x><zz> a,b,s9
2844 00010bbbssssssssSBBBDaaZZXAAAAAA. */
2845 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2846 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2847 { RA, BRAKET, RB, SIMM9_8R, BRAKETdup },
2848 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
2849
2850 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
2851 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2852 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2853 { RA, BRAKET, RB, LIMM, BRAKETdup },
2854 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
2855
2856 /* mov_s b,u8 11011bbbuuuuuuuu. */
2857 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2858 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2859 { RB_S, UIMM8_8R_S }, { 0 }},
2860
2861 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */
2862 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2863 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2864 { RB, SIMM12_20R }, { C_F }},
2865
2866 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
2867 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2868 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2869 { RB, LIMM }, { C_F }},
2870
2871 /* sub_s c,b,u3 01101bbbccc01uuu. */
2872 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2873 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2874 { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
2875
2876 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */
2877 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2878 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2879 { RA, RB, UIMM6_20R }, { C_F }},
2880
2881 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
2882 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2883 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2884 { RA, RB, LIMM }, { C_F }},
2885
2886 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */
2887 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2888 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }},
2889
2890 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
2891 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2892 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
2893
2894 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */
2895 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2896 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2897 { RB, UIMM6_20R }, { C_F, C_CC }},
2898
2899 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
2900 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2901 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2902 { RB, LIMM }, { C_F, C_CC }},
2903
2904 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */
2905 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2906 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2907 { RB, RBdup, UIMM6_20R }, { C_F, C_CC }},
2908
2909 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
2910 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2911 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2912 { RB, RBdup, LIMM }, { C_F, C_CC }}
2913 };
2914
2915 const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
2916
2917 /* Return length of an opcode in bytes. */
2918
2919 int
2920 arc_opcode_len (const struct arc_opcode *opcode)
2921 {
2922 if (opcode->mask < 0x10000ull)
2923 return 2;
2924
2925 if (opcode->mask < 0x100000000ull)
2926 return 4;
2927
2928 if (opcode->mask < 0x1000000000000ull)
2929 return 6;
2930
2931 return 8;
2932 }
GDB Binutils - Deliverables
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