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[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "sysdep.h"
24
25 #include "dis-asm.h"
26 #include "opcode/arm.h"
27 #include "opintl.h"
28 #include "safe-ctype.h"
29 #include "floatformat.h"
30
31 /* FIXME: This shouldn't be done here. */
32 #include "coff/internal.h"
33 #include "libcoff.h"
34 #include "elf-bfd.h"
35 #include "elf/internal.h"
36 #include "elf/arm.h"
37 #include "mach-o.h"
38
39 /* FIXME: Belongs in global header. */
40 #ifndef strneq
41 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
42 #endif
43
44 #ifndef NUM_ELEM
45 #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
46 #endif
47
48 /* Cached mapping symbol state. */
49 enum map_type
50 {
51 MAP_ARM,
52 MAP_THUMB,
53 MAP_DATA
54 };
55
56 struct arm_private_data
57 {
58 /* The features to use when disassembling optional instructions. */
59 arm_feature_set features;
60
61 /* Whether any mapping symbols are present in the provided symbol
62 table. -1 if we do not know yet, otherwise 0 or 1. */
63 int has_mapping_symbols;
64
65 /* Track the last type (although this doesn't seem to be useful) */
66 enum map_type last_type;
67
68 /* Tracking symbol table information */
69 int last_mapping_sym;
70 bfd_vma last_mapping_addr;
71 };
72
73 struct opcode32
74 {
75 arm_feature_set arch; /* Architecture defining this insn. */
76 unsigned long value; /* If arch is 0 then value is a sentinel. */
77 unsigned long mask; /* Recognise insn if (op & mask) == value. */
78 const char * assembler; /* How to disassemble this insn. */
79 };
80
81 struct opcode16
82 {
83 arm_feature_set arch; /* Architecture defining this insn. */
84 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
85 const char *assembler; /* How to disassemble this insn. */
86 };
87
88 /* print_insn_coprocessor recognizes the following format control codes:
89
90 %% %
91
92 %c print condition code (always bits 28-31 in ARM mode)
93 %q print shifter argument
94 %u print condition code (unconditional in ARM mode,
95 UNPREDICTABLE if not AL in Thumb)
96 %A print address for ldc/stc/ldf/stf instruction
97 %B print vstm/vldm register list
98 %I print cirrus signed shift immediate: bits 0..3|4..6
99 %F print the COUNT field of a LFM/SFM instruction.
100 %P print floating point precision in arithmetic insn
101 %Q print floating point precision in ldf/stf insn
102 %R print floating point rounding mode
103
104 %<bitfield>c print as a condition code (for vsel)
105 %<bitfield>r print as an ARM register
106 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
107 %<bitfield>ru as %<>r but each u register must be unique.
108 %<bitfield>d print the bitfield in decimal
109 %<bitfield>k print immediate for VFPv3 conversion instruction
110 %<bitfield>x print the bitfield in hex
111 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
112 %<bitfield>f print a floating point constant if >7 else a
113 floating point register
114 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
115 %<bitfield>g print as an iWMMXt 64-bit register
116 %<bitfield>G print as an iWMMXt general purpose or control register
117 %<bitfield>D print as a NEON D register
118 %<bitfield>Q print as a NEON Q register
119 %<bitfield>E print a quarter-float immediate value
120
121 %y<code> print a single precision VFP reg.
122 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
123 %z<code> print a double precision VFP reg
124 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
125
126 %<bitfield>'c print specified char iff bitfield is all ones
127 %<bitfield>`c print specified char iff bitfield is all zeroes
128 %<bitfield>?ab... select from array of values in big endian order
129
130 %L print as an iWMMXt N/M width field.
131 %Z print the Immediate of a WSHUFH instruction.
132 %l like 'A' except use byte offsets for 'B' & 'H'
133 versions.
134 %i print 5-bit immediate in bits 8,3..0
135 (print "32" when 0)
136 %r print register offset address for wldt/wstr instruction. */
137
138 enum opcode_sentinel_enum
139 {
140 SENTINEL_IWMMXT_START = 1,
141 SENTINEL_IWMMXT_END,
142 SENTINEL_GENERIC_START
143 } opcode_sentinels;
144
145 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
146 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
147
148 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
149
150 static const struct opcode32 coprocessor_opcodes[] =
151 {
152 /* XScale instructions. */
153 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
154 0x0e200010, 0x0fff0ff0,
155 "mia%c\tacc0, %0-3r, %12-15r"},
156 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
157 0x0e280010, 0x0fff0ff0,
158 "miaph%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
163 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
164 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
165
166 /* Intel Wireless MMX technology instructions. */
167 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
168 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
169 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
240 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
241 0x0e800120, 0x0f800ff0,
242 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
255 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
256 0x0e8000a0, 0x0f800ff0,
257 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
319 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
320 {ARM_FEATURE_CORE_LOW (0),
321 SENTINEL_IWMMXT_END, 0, "" },
322
323 /* Floating point coprocessor (FPA) instructions. */
324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
405 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
408 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
409 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
410
411 /* Register load/store. */
412 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
413 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
414 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
415 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
416 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
417 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
429 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
431 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
433 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
444
445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
446 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
448 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
450 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
452 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
453
454 /* Data transfer between ARM and NEON registers. */
455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
456 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
458 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
460 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
483 /* Half-precision conversion instructions. */
484 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
485 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
486 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
487 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
488 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
489 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
491 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
492
493 /* Floating point coprocessor (VFP) instructions. */
494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
495 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
496 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
497 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
499 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
507 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
521 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
523 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
525 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
527 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
533 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
535 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
537 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
539 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
543 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
545 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
547 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
549 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
551 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
553 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
555 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
557 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
559 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
561 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
563 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
565 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
567 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
569 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
571 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
573 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
575 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
577 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
579 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
581 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
583 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
585 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
587 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
589 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
591 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
593 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
595 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
597 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
599 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
601 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
603 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
605 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
607 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
609 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
611 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
613 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
615 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
617 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
619 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
621 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
623 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
625 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
627 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
628
629 /* Cirrus coprocessor instructions. */
630 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
631 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
632 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
633 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
634 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
635 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
636 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
637 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
639 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e000600, 0x0ff00f10,
792 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
793 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
794 0x0e100600, 0x0ff00f10,
795 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
797 0x0e200600, 0x0ff00f10,
798 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
799 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
800 0x0e300600, 0x0ff00f10,
801 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
802
803 /* VFP Fused multiply add instructions. */
804 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
805 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
806 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
807 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
808 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
809 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
810 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
811 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
813 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
820
821 /* FP v5. */
822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
825 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
827 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
829 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
831 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
833 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
835 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
837 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
839 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
841 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
843 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
845 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
846
847 /* Generic coprocessor instructions. */
848 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
850 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
852 0x0c500000, 0x0ff00000,
853 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
855 0x0e000000, 0x0f000010,
856 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
858 0x0e10f010, 0x0f10f010,
859 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
861 0x0e100010, 0x0f100010,
862 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
864 0x0e000010, 0x0f100010,
865 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
867 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
869 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
870
871 /* V6 coprocessor instructions. */
872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
873 0xfc500000, 0xfff00000,
874 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
876 0xfc400000, 0xfff00000,
877 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
878
879 /* V5 coprocessor instructions. */
880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
881 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
883 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
885 0xfe000000, 0xff000010,
886 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
888 0xfe000010, 0xff100010,
889 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
891 0xfe100010, 0xff100010,
892 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
893
894 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
895 };
896
897 /* Neon opcode table: This does not encode the top byte -- that is
898 checked by the print_insn_neon routine, as it depends on whether we are
899 doing thumb32 or arm32 disassembly. */
900
901 /* print_insn_neon recognizes the following format control codes:
902
903 %% %
904
905 %c print condition code
906 %u print condition code (unconditional in ARM mode,
907 UNPREDICTABLE if not AL in Thumb)
908 %A print v{st,ld}[1234] operands
909 %B print v{st,ld}[1234] any one operands
910 %C print v{st,ld}[1234] single->all operands
911 %D print scalar
912 %E print vmov, vmvn, vorr, vbic encoded constant
913 %F print vtbl,vtbx register list
914
915 %<bitfield>r print as an ARM register
916 %<bitfield>d print the bitfield in decimal
917 %<bitfield>e print the 2^N - bitfield in decimal
918 %<bitfield>D print as a NEON D register
919 %<bitfield>Q print as a NEON Q register
920 %<bitfield>R print as a NEON D or Q register
921 %<bitfield>Sn print byte scaled width limited by n
922 %<bitfield>Tn print short scaled width limited by n
923 %<bitfield>Un print long scaled width limited by n
924
925 %<bitfield>'c print specified char iff bitfield is all ones
926 %<bitfield>`c print specified char iff bitfield is all zeroes
927 %<bitfield>?ab... select from array of values in big endian order. */
928
929 static const struct opcode32 neon_opcodes[] =
930 {
931 /* Extract. */
932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
933 0xf2b00840, 0xffb00850,
934 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
936 0xf2b00000, 0xffb00810,
937 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
938
939 /* Move data element to all lanes. */
940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
941 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
943 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
945 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
946
947 /* Table lookup. */
948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
949 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
951 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
952
953 /* Half-precision conversions. */
954 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
955 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
956 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
957 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
958
959 /* NEON fused multiply add instructions. */
960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
961 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
963 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
964
965 /* Two registers, miscellaneous. */
966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
967 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
969 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
970 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
971 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
972 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
973 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
974 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
975 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
976 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
977 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
978 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
979 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
980 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
981 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
982 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
983 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
985 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
987 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
989 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
991 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
993 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
995 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
997 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
999 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1001 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1002 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1003 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1004 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1005 0xf3b20300, 0xffb30fd0,
1006 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1007 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1008 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1010 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1011 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1012 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1013 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1014 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1016 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1018 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1019 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1020 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1022 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1024 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1025 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1026 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1028 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1030 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1031 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1032 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1034 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1036 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1037 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1038 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1040 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1042 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1043 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1044 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1046 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1048 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1049 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1050 0xf3b30600, 0xffb30e10,
1051 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1052
1053 /* Three registers of the same length. */
1054 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1055 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1056 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1057 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1058 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1059 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1060 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1061 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1062 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1063 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1064 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1065 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1066 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1067 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1069 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1071 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1073 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1081 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1087 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1089 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1091 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1093 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1094 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1095 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1097 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1099 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1100 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1101 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1103 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1105 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1106 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1107 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1109 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1111 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1113 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1114 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1115 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1116 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1117 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1119 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1120 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1121 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1122 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1123 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1125 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1131 0xf2000b00, 0xff800f10,
1132 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1134 0xf2000b10, 0xff800f10,
1135 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1143 0xf3000b00, 0xff800f10,
1144 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1146 0xf2000000, 0xfe800f10,
1147 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1149 0xf2000010, 0xfe800f10,
1150 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1152 0xf2000100, 0xfe800f10,
1153 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1155 0xf2000200, 0xfe800f10,
1156 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158 0xf2000210, 0xfe800f10,
1159 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1161 0xf2000300, 0xfe800f10,
1162 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164 0xf2000310, 0xfe800f10,
1165 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1167 0xf2000400, 0xfe800f10,
1168 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170 0xf2000410, 0xfe800f10,
1171 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1173 0xf2000500, 0xfe800f10,
1174 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176 0xf2000510, 0xfe800f10,
1177 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1178 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1179 0xf2000600, 0xfe800f10,
1180 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1181 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182 0xf2000610, 0xfe800f10,
1183 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1184 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1185 0xf2000700, 0xfe800f10,
1186 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188 0xf2000710, 0xfe800f10,
1189 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1190 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1191 0xf2000910, 0xfe800f10,
1192 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1193 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1194 0xf2000a00, 0xfe800f10,
1195 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1196 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1197 0xf2000a10, 0xfe800f10,
1198 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1199 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1200 0xf3000b10, 0xff800f10,
1201 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1202 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1203 0xf3000c10, 0xff800f10,
1204 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1205
1206 /* One register and an immediate value. */
1207 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1209 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1211 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1212 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1213 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1216 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1220 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1221 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1222 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1223 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1224 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1233
1234 /* Two registers and a shift amount. */
1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1239 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1240 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1241 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1242 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1243 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1244 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1245 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1246 0xf2880950, 0xfeb80fd0,
1247 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1248 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1249 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1251 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1252 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1253 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1255 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1256 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1257 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1259 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1260 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1261 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1263 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1264 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1265 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1266 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1267 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1268 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1269 0xf2900950, 0xfeb00fd0,
1270 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1280 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1304 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2a00950, 0xfea00fd0,
1315 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1319 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1325 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1349 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353 0xf2a00e10, 0xfea00e90,
1354 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1355
1356 /* Three registers of different lengths. */
1357 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1358 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1361 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362 0xf2800400, 0xff800f50,
1363 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365 0xf2800600, 0xff800f50,
1366 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368 0xf2800900, 0xff800f50,
1369 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf2800b00, 0xff800f50,
1372 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374 0xf2800d00, 0xff800f50,
1375 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf3800400, 0xff800f50,
1378 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf3800600, 0xff800f50,
1381 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf2800000, 0xfe800f50,
1384 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf2800100, 0xfe800f50,
1387 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389 0xf2800200, 0xfe800f50,
1390 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1392 0xf2800300, 0xfe800f50,
1393 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf2800500, 0xfe800f50,
1396 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1398 0xf2800700, 0xfe800f50,
1399 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2800800, 0xfe800f50,
1402 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1404 0xf2800a00, 0xfe800f50,
1405 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2800c00, 0xfe800f50,
1408 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1409
1410 /* Two registers and a scalar. */
1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1412 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1414 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf2800240, 0xfe800f50,
1451 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453 0xf2800640, 0xfe800f50,
1454 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf2800a40, 0xfe800f50,
1457 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1459 0xf2800e40, 0xff800f50,
1460 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1462 0xf2800f40, 0xff800f50,
1463 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1465 0xf3800e40, 0xff800f50,
1466 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1468 0xf3800f40, 0xff800f50,
1469 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1470 },
1471
1472 /* Element and structure load/store. */
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1511
1512 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1513 };
1514
1515 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1516 ordered: they must be searched linearly from the top to obtain a correct
1517 match. */
1518
1519 /* print_insn_arm recognizes the following format control codes:
1520
1521 %% %
1522
1523 %a print address for ldr/str instruction
1524 %s print address for ldr/str halfword/signextend instruction
1525 %S like %s but allow UNPREDICTABLE addressing
1526 %b print branch destination
1527 %c print condition code (always bits 28-31)
1528 %m print register mask for ldm/stm instruction
1529 %o print operand2 (immediate or register + shift)
1530 %p print 'p' iff bits 12-15 are 15
1531 %t print 't' iff bit 21 set and bit 24 clear
1532 %B print arm BLX(1) destination
1533 %C print the PSR sub type.
1534 %U print barrier type.
1535 %P print address for pli instruction.
1536
1537 %<bitfield>r print as an ARM register
1538 %<bitfield>T print as an ARM register + 1
1539 %<bitfield>R as %r but r15 is UNPREDICTABLE
1540 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1541 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1542 %<bitfield>d print the bitfield in decimal
1543 %<bitfield>W print the bitfield plus one in decimal
1544 %<bitfield>x print the bitfield in hex
1545 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
1546
1547 %<bitfield>'c print specified char iff bitfield is all ones
1548 %<bitfield>`c print specified char iff bitfield is all zeroes
1549 %<bitfield>?ab... select from array of values in big endian order
1550
1551 %e print arm SMI operand (bits 0..7,8..19).
1552 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
1553 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1554 %R print the SPSR/CPSR or banked register of an MRS. */
1555
1556 static const struct opcode32 arm_opcodes[] =
1557 {
1558 /* ARM instructions. */
1559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1560 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1562 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1563
1564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1565 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1567 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1569 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1571 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1573 0x00800090, 0x0fa000f0,
1574 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1576 0x00a00090, 0x0fa000f0,
1577 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1578
1579 /* V8 instructions. */
1580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1581 0x0320f005, 0x0fffffff, "sevl"},
1582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1583 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1584 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
1585 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1586 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1587 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1589 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1591 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1592 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1593 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1594 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1595 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1596 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1597 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1598 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1599 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1600 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1601 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1602 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1603 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1604 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1605 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1606 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1607 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1608 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1609 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1610 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1611 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
1612 /* CRC32 instructions. */
1613 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1614 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1615 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1616 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1617 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1618 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1619 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1620 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1621 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1622 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1623 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1624 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1625
1626 /* Privileged Access Never extension instructions. */
1627 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1628 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1629
1630 /* Virtualization Extension instructions. */
1631 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1632 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1633
1634 /* Integer Divide Extension instructions. */
1635 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1636 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1637 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1638 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1639
1640 /* MP Extension instructions. */
1641 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1642
1643 /* V7 instructions. */
1644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1652 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
1653
1654 /* ARM V6T2 instructions. */
1655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1656 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1658 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1660 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1662 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1663
1664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1665 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1667 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1668
1669 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1670 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1671 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1672 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1674 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1676 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1677
1678 /* ARM Security extension instructions. */
1679 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1680 0x01600070, 0x0ff000f0, "smc%c\t%e"},
1681
1682 /* ARM V6K instructions. */
1683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1684 0xf57ff01f, 0xffffffff, "clrex"},
1685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1686 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1688 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1690 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1692 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1694 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1696 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1697
1698 /* ARM V6K NOP hints. */
1699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1700 0x0320f001, 0x0fffffff, "yield%c"},
1701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1702 0x0320f002, 0x0fffffff, "wfe%c"},
1703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1704 0x0320f003, 0x0fffffff, "wfi%c"},
1705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1706 0x0320f004, 0x0fffffff, "sev%c"},
1707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1708 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1709
1710 /* ARM V6 instructions. */
1711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1712 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1714 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1716 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1718 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1720 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1722 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1724 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1726 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1728 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1730 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1732 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1734 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1736 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1738 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1740 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1742 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1744 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1746 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1748 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1750 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1752 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1754 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1756 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1758 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1760 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1762 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1764 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1766 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1768 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1770 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1772 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1774 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1776 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1778 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1780 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1782 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1784 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1786 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1788 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1790 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1792 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1794 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1796 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1798 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1800 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1802 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1804 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1806 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1808 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1810 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1812 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1814 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1816 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1818 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1820 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1822 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1824 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1826 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1828 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1830 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1832 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1834 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1836 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1838 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1840 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1842 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1844 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1846 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1848 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1850 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1852 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1854 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1856 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1858 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1860 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1862 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1864 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1866 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1868 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1870 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1872 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1874 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1876 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1878 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1880 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1882 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1884 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1886 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1888 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1890 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1892 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1894 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1896 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1898 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1900 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1902 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1904 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1906 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1908 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1910 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1912 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1914 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1916 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
1955
1956 /* V5J instruction. */
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
1958 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
1959
1960 /* V5 Instructions. */
1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1962 0xe1200070, 0xfff000f0,
1963 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1965 0xfa000000, 0xfe000000, "blx\t%B"},
1966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1967 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1969 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1970
1971 /* V5E "El Segundo" Instructions. */
1972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1973 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1975 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1977 0xf450f000, 0xfc70f000, "pld\t%a"},
1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1979 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1981 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1983 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1985 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1986
1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1988 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1990 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1991
1992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1993 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1995 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1997 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1999 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2000
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2002 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2004 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2006 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2008 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2009
2010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2011 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2013 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2014
2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2016 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2018 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2020 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2022 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2023
2024 /* ARM Instructions. */
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2026 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2027
2028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2029 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2031 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2033 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2035 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2037 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2039 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2040
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2042 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2044 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2046 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2048 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2049
2050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2051 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2053 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2055 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2057 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2058
2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2060 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2062 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2064 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2065
2066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2067 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2069 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2071 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2072
2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2074 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2076 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2078 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2079
2080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2081 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2083 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2085 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2086
2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2088 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2090 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2092 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2093
2094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2095 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2097 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2099 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2100
2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2102 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2104 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2106 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2107
2108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2109 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2111 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2113 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2114
2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2116 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2118 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2120 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2121
2122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2123 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2125 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2127 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2128
2129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2130 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2132 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2134 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2136 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"},
2137
2138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2139 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2141 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2143 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2144
2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2146 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2148 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2150 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2151
2152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2153 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2155 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2157 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2158
2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2160 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2162 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2164 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2166 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2168 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2170 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2172 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2173
2174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2175 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2177 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2179 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2180
2181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2182 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2184 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2186 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2187
2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2189 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2191 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2192
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2194 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2195
2196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2197 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2199 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2200
2201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2202 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2204 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2206 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2208 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2210 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2212 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2214 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2216 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2218 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2220 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2222 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2224 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2226 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2228 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2230 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2232 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2234 0x092d0000, 0x0fff0000, "push%c\t%m"},
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2236 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2238 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2239
2240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2241 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2243 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2247 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2249 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2251 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2253 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2255 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2261 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2263 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2265 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2267 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2271 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2275 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2277 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2278
2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2282 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2283
2284 /* The rest. */
2285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2286 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
2287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2288 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2289 {ARM_FEATURE_CORE_LOW (0),
2290 0x00000000, 0x00000000, 0}
2291 };
2292
2293 /* print_insn_thumb16 recognizes the following format control codes:
2294
2295 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2296 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2297 %<bitfield>I print bitfield as a signed decimal
2298 (top bit of range being the sign bit)
2299 %N print Thumb register mask (with LR)
2300 %O print Thumb register mask (with PC)
2301 %M print Thumb register mask
2302 %b print CZB's 6-bit unsigned branch destination
2303 %s print Thumb right-shift immediate (6..10; 0 == 32).
2304 %c print the condition code
2305 %C print the condition code, or "s" if not conditional
2306 %x print warning if conditional an not at end of IT block"
2307 %X print "\t; unpredictable <IT:code>" if conditional
2308 %I print IT instruction suffix and operands
2309 %W print Thumb Writeback indicator for LDMIA
2310 %<bitfield>r print bitfield as an ARM register
2311 %<bitfield>d print bitfield as a decimal
2312 %<bitfield>H print (bitfield * 2) as a decimal
2313 %<bitfield>W print (bitfield * 4) as a decimal
2314 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2315 %<bitfield>B print Thumb branch destination (signed displacement)
2316 %<bitfield>c print bitfield as a condition code
2317 %<bitnum>'c print specified char iff bit is one
2318 %<bitnum>?ab print a if bit is one else print b. */
2319
2320 static const struct opcode16 thumb_opcodes[] =
2321 {
2322 /* Thumb instructions. */
2323
2324 /* ARM V8 instructions. */
2325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
2327 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
2328
2329 /* ARM V6K no-argument instructions. */
2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2336
2337 /* ARM V6T2 instructions. */
2338 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2339 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2340 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2341 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2343
2344 /* ARM V6. */
2345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2356
2357 /* ARM V5 ISA extends Thumb. */
2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2359 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
2360 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2362 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
2363 /* ARM V4T ISA (Thumb v1). */
2364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2365 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2366 /* Format 4. */
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2383 /* format 13 */
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2386 /* format 5 */
2387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2391 /* format 14 */
2392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2394 /* format 2 */
2395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2396 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2398 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2400 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2402 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2403 /* format 8 */
2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2405 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2407 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2409 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2410 /* format 7 */
2411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2412 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2414 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2415 /* format 1 */
2416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2418 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2421 /* format 3 */
2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2426 /* format 6 */
2427 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2429 0x4800, 0xF800,
2430 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2431 /* format 9 */
2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2433 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2435 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2437 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2439 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2440 /* format 10 */
2441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2442 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2444 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2445 /* format 11 */
2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2447 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2449 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2450 /* format 12 */
2451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2452 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2454 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2455 /* format 15 */
2456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2458 /* format 17 */
2459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2460 /* format 16 */
2461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2464 /* format 18 */
2465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2466
2467 /* The E800 .. FFFF range is unconditionally redirected to the
2468 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2469 are processed via that table. Thus, we can never encounter a
2470 bare "second half of BL/BLX(1)" instruction here. */
2471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2472 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2473 };
2474
2475 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2476 We adopt the convention that hw1 is the high 16 bits of .value and
2477 .mask, hw2 the low 16 bits.
2478
2479 print_insn_thumb32 recognizes the following format control codes:
2480
2481 %% %
2482
2483 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2484 %M print a modified 12-bit immediate (same location)
2485 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2486 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2487 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
2488 %S print a possibly-shifted Rm
2489
2490 %L print address for a ldrd/strd instruction
2491 %a print the address of a plain load/store
2492 %w print the width and signedness of a core load/store
2493 %m print register mask for ldm/stm
2494
2495 %E print the lsb and width fields of a bfc/bfi instruction
2496 %F print the lsb and width fields of a sbfx/ubfx instruction
2497 %b print a conditional branch offset
2498 %B print an unconditional branch offset
2499 %s print the shift field of an SSAT instruction
2500 %R print the rotation field of an SXT instruction
2501 %U print barrier type.
2502 %P print address for pli instruction.
2503 %c print the condition code
2504 %x print warning if conditional an not at end of IT block"
2505 %X print "\t; unpredictable <IT:code>" if conditional
2506
2507 %<bitfield>d print bitfield in decimal
2508 %<bitfield>D print bitfield plus one in decimal
2509 %<bitfield>W print bitfield*4 in decimal
2510 %<bitfield>r print bitfield as an ARM register
2511 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2512 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
2513 %<bitfield>c print bitfield as a condition code
2514
2515 %<bitfield>'c print specified char iff bitfield is all ones
2516 %<bitfield>`c print specified char iff bitfield is all zeroes
2517 %<bitfield>?ab... select from array of values in big endian order
2518
2519 With one exception at the bottom (done because BL and BLX(1) need
2520 to come dead last), this table was machine-sorted first in
2521 decreasing order of number of bits set in the mask, then in
2522 increasing numeric order of mask, then in increasing numeric order
2523 of opcode. This order is not the clearest for a human reader, but
2524 is guaranteed never to catch a special-case bit pattern with a more
2525 general mask, which is important, because this instruction encoding
2526 makes heavy use of special-case bit patterns. */
2527 static const struct opcode32 thumb32_opcodes[] =
2528 {
2529 /* V8-M instructions. */
2530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2531 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2533 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2534
2535 /* V8 instructions. */
2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2537 0xf3af8005, 0xffffffff, "sevl%c.w"},
2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2539 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2541 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2543 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2545 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2547 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2549 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2551 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2553 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2555 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2557 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2559 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2561 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2563 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2565 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2567 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2568
2569 /* CRC32 instructions. */
2570 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2571 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2572 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2573 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2574 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2575 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2576 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2577 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2578 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2579 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2580 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2581 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
2582
2583 /* V7 instructions. */
2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2592 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2594 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2595
2596 /* Virtualization Extension instructions. */
2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2598 /* We skip ERET as that is SUBS pc, lr, #0. */
2599
2600 /* MP Extension instructions. */
2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
2602
2603 /* Security extension instructions. */
2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2605
2606 /* Instructions defined in the basic V6T2 set. */
2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2613 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2615
2616 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2617 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2619 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2621 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2623 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2625 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2627 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2629 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2631 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2633 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2635 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2637 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2639 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2641 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2643 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2644 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2645 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2646 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2647 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2649 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2651 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2653 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2655 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2657 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2659 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2661 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2663 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2665 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2667 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2669 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2671 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2673 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2675 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2677 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2679 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2681 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2683 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2685 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2687 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2689 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2691 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2693 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2695 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2697 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2699 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2701 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2703 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2705 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2707 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2709 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2711 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2713 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2715 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2717 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2719 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2721 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2723 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2725 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2727 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2729 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2731 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2733 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2735 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2737 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2739 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2741 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2743 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2745 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2747 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2749 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2751 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2753 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2755 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2757 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2759 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2761 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2763 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2765 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2767 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2769 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2771 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
2772 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2773 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2775 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2777 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2779 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2781 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2783 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2785 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2787 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2789 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2791 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2793 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2795 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2797 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2799 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2801 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2803 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2805 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2807 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2809 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2811 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2813 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2815 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2817 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2819 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2821 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2823 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2825 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2827 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2829 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2831 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2833 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2835 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2837 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2839 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2840 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2841 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2843 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2845 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847 0xf810f000, 0xff70f000, "pld%c\t%a"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2849 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2851 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2857 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2859 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873 0xfb100000, 0xfff000c0,
2874 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2876 0xfbc00080, 0xfff000c0,
2877 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
2888 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2889 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
2892 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2893 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
2914 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2915 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949 0xe9400000, 0xff500000,
2950 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2952 0xe9500000, 0xff500000,
2953 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955 0xe8600000, 0xff700000,
2956 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2958 0xe8700000, 0xff700000,
2959 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
2964
2965 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2967 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2973 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
2974
2975 /* These have been 32-bit since the invention of Thumb. */
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2977 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2979 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
2980
2981 /* Fallback. */
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2983 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2984 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2985 };
2986
2987 static const char *const arm_conditional[] =
2988 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
2989 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
2990
2991 static const char *const arm_fp_const[] =
2992 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
2993
2994 static const char *const arm_shift[] =
2995 {"lsl", "lsr", "asr", "ror"};
2996
2997 typedef struct
2998 {
2999 const char *name;
3000 const char *description;
3001 const char *reg_names[16];
3002 }
3003 arm_regname;
3004
3005 static const arm_regname regnames[] =
3006 {
3007 { "raw" , "Select raw register names",
3008 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3009 { "gcc", "Select register names used by GCC",
3010 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3011 { "std", "Select register names used in ARM's ISA documentation",
3012 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3013 { "apcs", "Select register names used in the APCS",
3014 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3015 { "atpcs", "Select register names used in the ATPCS",
3016 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3017 { "special-atpcs", "Select special register names used in the ATPCS",
3018 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
3019 };
3020
3021 static const char *const iwmmxt_wwnames[] =
3022 {"b", "h", "w", "d"};
3023
3024 static const char *const iwmmxt_wwssnames[] =
3025 {"b", "bus", "bc", "bss",
3026 "h", "hus", "hc", "hss",
3027 "w", "wus", "wc", "wss",
3028 "d", "dus", "dc", "dss"
3029 };
3030
3031 static const char *const iwmmxt_regnames[] =
3032 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3033 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3034 };
3035
3036 static const char *const iwmmxt_cregnames[] =
3037 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3038 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3039 };
3040
3041 /* Default to GCC register name set. */
3042 static unsigned int regname_selected = 1;
3043
3044 #define NUM_ARM_REGNAMES NUM_ELEM (regnames)
3045 #define arm_regnames regnames[regname_selected].reg_names
3046
3047 static bfd_boolean force_thumb = FALSE;
3048
3049 /* Current IT instruction state. This contains the same state as the IT
3050 bits in the CPSR. */
3051 static unsigned int ifthen_state;
3052 /* IT state for the next instruction. */
3053 static unsigned int ifthen_next_state;
3054 /* The address of the insn for which the IT state is valid. */
3055 static bfd_vma ifthen_address;
3056 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3057 /* Indicates that the current Conditional state is unconditional or outside
3058 an IT block. */
3059 #define COND_UNCOND 16
3060
3061 \f
3062 /* Functions. */
3063 int
3064 get_arm_regname_num_options (void)
3065 {
3066 return NUM_ARM_REGNAMES;
3067 }
3068
3069 int
3070 set_arm_regname_option (int option)
3071 {
3072 int old = regname_selected;
3073 regname_selected = option;
3074 return old;
3075 }
3076
3077 int
3078 get_arm_regnames (int option,
3079 const char **setname,
3080 const char **setdescription,
3081 const char *const **register_names)
3082 {
3083 *setname = regnames[option].name;
3084 *setdescription = regnames[option].description;
3085 *register_names = regnames[option].reg_names;
3086 return 16;
3087 }
3088
3089 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3090 Returns pointer to following character of the format string and
3091 fills in *VALUEP and *WIDTHP with the extracted value and number of
3092 bits extracted. WIDTHP can be NULL. */
3093
3094 static const char *
3095 arm_decode_bitfield (const char *ptr,
3096 unsigned long insn,
3097 unsigned long *valuep,
3098 int *widthp)
3099 {
3100 unsigned long value = 0;
3101 int width = 0;
3102
3103 do
3104 {
3105 int start, end;
3106 int bits;
3107
3108 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3109 start = start * 10 + *ptr - '0';
3110 if (*ptr == '-')
3111 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3112 end = end * 10 + *ptr - '0';
3113 else
3114 end = start;
3115 bits = end - start;
3116 if (bits < 0)
3117 abort ();
3118 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3119 width += bits + 1;
3120 }
3121 while (*ptr++ == ',');
3122 *valuep = value;
3123 if (widthp)
3124 *widthp = width;
3125 return ptr - 1;
3126 }
3127
3128 static void
3129 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3130 bfd_boolean print_shift)
3131 {
3132 func (stream, "%s", arm_regnames[given & 0xf]);
3133
3134 if ((given & 0xff0) != 0)
3135 {
3136 if ((given & 0x10) == 0)
3137 {
3138 int amount = (given & 0xf80) >> 7;
3139 int shift = (given & 0x60) >> 5;
3140
3141 if (amount == 0)
3142 {
3143 if (shift == 3)
3144 {
3145 func (stream, ", rrx");
3146 return;
3147 }
3148
3149 amount = 32;
3150 }
3151
3152 if (print_shift)
3153 func (stream, ", %s #%d", arm_shift[shift], amount);
3154 else
3155 func (stream, ", #%d", amount);
3156 }
3157 else if ((given & 0x80) == 0x80)
3158 func (stream, "\t; <illegal shifter operand>");
3159 else if (print_shift)
3160 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3161 arm_regnames[(given & 0xf00) >> 8]);
3162 else
3163 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3164 }
3165 }
3166
3167 #define W_BIT 21
3168 #define I_BIT 22
3169 #define U_BIT 23
3170 #define P_BIT 24
3171
3172 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3173 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3174 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3175 #define PRE_BIT_SET (given & (1 << P_BIT))
3176
3177 /* Print one coprocessor instruction on INFO->STREAM.
3178 Return TRUE if the instuction matched, FALSE if this is not a
3179 recognised coprocessor instruction. */
3180
3181 static bfd_boolean
3182 print_insn_coprocessor (bfd_vma pc,
3183 struct disassemble_info *info,
3184 long given,
3185 bfd_boolean thumb)
3186 {
3187 const struct opcode32 *insn;
3188 void *stream = info->stream;
3189 fprintf_ftype func = info->fprintf_func;
3190 unsigned long mask;
3191 unsigned long value = 0;
3192 int cond;
3193 struct arm_private_data *private_data = info->private_data;
3194 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3195
3196 ARM_FEATURE_COPY (allowed_arches, private_data->features);
3197
3198 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3199 {
3200 unsigned long u_reg = 16;
3201 bfd_boolean is_unpredictable = FALSE;
3202 signed long value_in_comment = 0;
3203 const char *c;
3204
3205 if (ARM_FEATURE_ZERO (insn->arch))
3206 switch (insn->value)
3207 {
3208 case SENTINEL_IWMMXT_START:
3209 if (info->mach != bfd_mach_arm_XScale
3210 && info->mach != bfd_mach_arm_iWMMXt
3211 && info->mach != bfd_mach_arm_iWMMXt2)
3212 do
3213 insn++;
3214 while ((! ARM_FEATURE_ZERO (insn->arch))
3215 && insn->value != SENTINEL_IWMMXT_END);
3216 continue;
3217
3218 case SENTINEL_IWMMXT_END:
3219 continue;
3220
3221 case SENTINEL_GENERIC_START:
3222 ARM_FEATURE_COPY (allowed_arches, private_data->features);
3223 continue;
3224
3225 default:
3226 abort ();
3227 }
3228
3229 mask = insn->mask;
3230 value = insn->value;
3231 if (thumb)
3232 {
3233 /* The high 4 bits are 0xe for Arm conditional instructions, and
3234 0xe for arm unconditional instructions. The rest of the
3235 encoding is the same. */
3236 mask |= 0xf0000000;
3237 value |= 0xe0000000;
3238 if (ifthen_state)
3239 cond = IFTHEN_COND;
3240 else
3241 cond = COND_UNCOND;
3242 }
3243 else
3244 {
3245 /* Only match unconditional instuctions against unconditional
3246 patterns. */
3247 if ((given & 0xf0000000) == 0xf0000000)
3248 {
3249 mask |= 0xf0000000;
3250 cond = COND_UNCOND;
3251 }
3252 else
3253 {
3254 cond = (given >> 28) & 0xf;
3255 if (cond == 0xe)
3256 cond = COND_UNCOND;
3257 }
3258 }
3259
3260 if ((given & mask) != value)
3261 continue;
3262
3263 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
3264 continue;
3265
3266 for (c = insn->assembler; *c; c++)
3267 {
3268 if (*c == '%')
3269 {
3270 switch (*++c)
3271 {
3272 case '%':
3273 func (stream, "%%");
3274 break;
3275
3276 case 'A':
3277 {
3278 int rn = (given >> 16) & 0xf;
3279 bfd_vma offset = given & 0xff;
3280
3281 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3282
3283 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3284 {
3285 /* Not unindexed. The offset is scaled. */
3286 offset = offset * 4;
3287 if (NEGATIVE_BIT_SET)
3288 offset = - offset;
3289 if (rn != 15)
3290 value_in_comment = offset;
3291 }
3292
3293 if (PRE_BIT_SET)
3294 {
3295 if (offset)
3296 func (stream, ", #%d]%s",
3297 (int) offset,
3298 WRITEBACK_BIT_SET ? "!" : "");
3299 else if (NEGATIVE_BIT_SET)
3300 func (stream, ", #-0]");
3301 else
3302 func (stream, "]");
3303 }
3304 else
3305 {
3306 func (stream, "]");
3307
3308 if (WRITEBACK_BIT_SET)
3309 {
3310 if (offset)
3311 func (stream, ", #%d", (int) offset);
3312 else if (NEGATIVE_BIT_SET)
3313 func (stream, ", #-0");
3314 }
3315 else
3316 {
3317 func (stream, ", {%s%d}",
3318 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3319 (int) offset);
3320 value_in_comment = offset;
3321 }
3322 }
3323 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3324 {
3325 func (stream, "\t; ");
3326 /* For unaligned PCs, apply off-by-alignment
3327 correction. */
3328 info->print_address_func (offset + pc
3329 + info->bytes_per_chunk * 2
3330 - (pc & 3),
3331 info);
3332 }
3333 }
3334 break;
3335
3336 case 'B':
3337 {
3338 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3339 int offset = (given >> 1) & 0x3f;
3340
3341 if (offset == 1)
3342 func (stream, "{d%d}", regno);
3343 else if (regno + offset > 32)
3344 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3345 else
3346 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3347 }
3348 break;
3349
3350 case 'u':
3351 if (cond != COND_UNCOND)
3352 is_unpredictable = TRUE;
3353
3354 /* Fall through. */
3355 case 'c':
3356 func (stream, "%s", arm_conditional[cond]);
3357 break;
3358
3359 case 'I':
3360 /* Print a Cirrus/DSP shift immediate. */
3361 /* Immediates are 7bit signed ints with bits 0..3 in
3362 bits 0..3 of opcode and bits 4..6 in bits 5..7
3363 of opcode. */
3364 {
3365 int imm;
3366
3367 imm = (given & 0xf) | ((given & 0xe0) >> 1);
3368
3369 /* Is ``imm'' a negative number? */
3370 if (imm & 0x40)
3371 imm -= 0x80;
3372
3373 func (stream, "%d", imm);
3374 }
3375
3376 break;
3377
3378 case 'F':
3379 switch (given & 0x00408000)
3380 {
3381 case 0:
3382 func (stream, "4");
3383 break;
3384 case 0x8000:
3385 func (stream, "1");
3386 break;
3387 case 0x00400000:
3388 func (stream, "2");
3389 break;
3390 default:
3391 func (stream, "3");
3392 }
3393 break;
3394
3395 case 'P':
3396 switch (given & 0x00080080)
3397 {
3398 case 0:
3399 func (stream, "s");
3400 break;
3401 case 0x80:
3402 func (stream, "d");
3403 break;
3404 case 0x00080000:
3405 func (stream, "e");
3406 break;
3407 default:
3408 func (stream, _("<illegal precision>"));
3409 break;
3410 }
3411 break;
3412
3413 case 'Q':
3414 switch (given & 0x00408000)
3415 {
3416 case 0:
3417 func (stream, "s");
3418 break;
3419 case 0x8000:
3420 func (stream, "d");
3421 break;
3422 case 0x00400000:
3423 func (stream, "e");
3424 break;
3425 default:
3426 func (stream, "p");
3427 break;
3428 }
3429 break;
3430
3431 case 'R':
3432 switch (given & 0x60)
3433 {
3434 case 0:
3435 break;
3436 case 0x20:
3437 func (stream, "p");
3438 break;
3439 case 0x40:
3440 func (stream, "m");
3441 break;
3442 default:
3443 func (stream, "z");
3444 break;
3445 }
3446 break;
3447
3448 case '0': case '1': case '2': case '3': case '4':
3449 case '5': case '6': case '7': case '8': case '9':
3450 {
3451 int width;
3452
3453 c = arm_decode_bitfield (c, given, &value, &width);
3454
3455 switch (*c)
3456 {
3457 case 'R':
3458 if (value == 15)
3459 is_unpredictable = TRUE;
3460 /* Fall through. */
3461 case 'r':
3462 if (c[1] == 'u')
3463 {
3464 /* Eat the 'u' character. */
3465 ++ c;
3466
3467 if (u_reg == value)
3468 is_unpredictable = TRUE;
3469 u_reg = value;
3470 }
3471 func (stream, "%s", arm_regnames[value]);
3472 break;
3473 case 'D':
3474 func (stream, "d%ld", value);
3475 break;
3476 case 'Q':
3477 if (value & 1)
3478 func (stream, "<illegal reg q%ld.5>", value >> 1);
3479 else
3480 func (stream, "q%ld", value >> 1);
3481 break;
3482 case 'd':
3483 func (stream, "%ld", value);
3484 value_in_comment = value;
3485 break;
3486 case 'E':
3487 {
3488 /* Converts immediate 8 bit back to float value. */
3489 unsigned floatVal = (value & 0x80) << 24
3490 | (value & 0x3F) << 19
3491 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3492
3493 /* Quarter float have a maximum value of 31.0.
3494 Get floating point value multiplied by 1e7.
3495 The maximum value stays in limit of a 32-bit int. */
3496 unsigned decVal =
3497 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3498 (16 + (value & 0xF));
3499
3500 if (!(decVal % 1000000))
3501 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3502 floatVal, value & 0x80 ? '-' : ' ',
3503 decVal / 10000000,
3504 decVal % 10000000 / 1000000);
3505 else if (!(decVal % 10000))
3506 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3507 floatVal, value & 0x80 ? '-' : ' ',
3508 decVal / 10000000,
3509 decVal % 10000000 / 10000);
3510 else
3511 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3512 floatVal, value & 0x80 ? '-' : ' ',
3513 decVal / 10000000, decVal % 10000000);
3514 break;
3515 }
3516 case 'k':
3517 {
3518 int from = (given & (1 << 7)) ? 32 : 16;
3519 func (stream, "%ld", from - value);
3520 }
3521 break;
3522
3523 case 'f':
3524 if (value > 7)
3525 func (stream, "#%s", arm_fp_const[value & 7]);
3526 else
3527 func (stream, "f%ld", value);
3528 break;
3529
3530 case 'w':
3531 if (width == 2)
3532 func (stream, "%s", iwmmxt_wwnames[value]);
3533 else
3534 func (stream, "%s", iwmmxt_wwssnames[value]);
3535 break;
3536
3537 case 'g':
3538 func (stream, "%s", iwmmxt_regnames[value]);
3539 break;
3540 case 'G':
3541 func (stream, "%s", iwmmxt_cregnames[value]);
3542 break;
3543
3544 case 'x':
3545 func (stream, "0x%lx", (value & 0xffffffffUL));
3546 break;
3547
3548 case 'c':
3549 switch (value)
3550 {
3551 case 0:
3552 func (stream, "eq");
3553 break;
3554
3555 case 1:
3556 func (stream, "vs");
3557 break;
3558
3559 case 2:
3560 func (stream, "ge");
3561 break;
3562
3563 case 3:
3564 func (stream, "gt");
3565 break;
3566
3567 default:
3568 func (stream, "??");
3569 break;
3570 }
3571 break;
3572
3573 case '`':
3574 c++;
3575 if (value == 0)
3576 func (stream, "%c", *c);
3577 break;
3578 case '\'':
3579 c++;
3580 if (value == ((1ul << width) - 1))
3581 func (stream, "%c", *c);
3582 break;
3583 case '?':
3584 func (stream, "%c", c[(1 << width) - (int) value]);
3585 c += 1 << width;
3586 break;
3587 default:
3588 abort ();
3589 }
3590 break;
3591
3592 case 'y':
3593 case 'z':
3594 {
3595 int single = *c++ == 'y';
3596 int regno;
3597
3598 switch (*c)
3599 {
3600 case '4': /* Sm pair */
3601 case '0': /* Sm, Dm */
3602 regno = given & 0x0000000f;
3603 if (single)
3604 {
3605 regno <<= 1;
3606 regno += (given >> 5) & 1;
3607 }
3608 else
3609 regno += ((given >> 5) & 1) << 4;
3610 break;
3611
3612 case '1': /* Sd, Dd */
3613 regno = (given >> 12) & 0x0000000f;
3614 if (single)
3615 {
3616 regno <<= 1;
3617 regno += (given >> 22) & 1;
3618 }
3619 else
3620 regno += ((given >> 22) & 1) << 4;
3621 break;
3622
3623 case '2': /* Sn, Dn */
3624 regno = (given >> 16) & 0x0000000f;
3625 if (single)
3626 {
3627 regno <<= 1;
3628 regno += (given >> 7) & 1;
3629 }
3630 else
3631 regno += ((given >> 7) & 1) << 4;
3632 break;
3633
3634 case '3': /* List */
3635 func (stream, "{");
3636 regno = (given >> 12) & 0x0000000f;
3637 if (single)
3638 {
3639 regno <<= 1;
3640 regno += (given >> 22) & 1;
3641 }
3642 else
3643 regno += ((given >> 22) & 1) << 4;
3644 break;
3645
3646 default:
3647 abort ();
3648 }
3649
3650 func (stream, "%c%d", single ? 's' : 'd', regno);
3651
3652 if (*c == '3')
3653 {
3654 int count = given & 0xff;
3655
3656 if (single == 0)
3657 count >>= 1;
3658
3659 if (--count)
3660 {
3661 func (stream, "-%c%d",
3662 single ? 's' : 'd',
3663 regno + count);
3664 }
3665
3666 func (stream, "}");
3667 }
3668 else if (*c == '4')
3669 func (stream, ", %c%d", single ? 's' : 'd',
3670 regno + 1);
3671 }
3672 break;
3673
3674 case 'L':
3675 switch (given & 0x00400100)
3676 {
3677 case 0x00000000: func (stream, "b"); break;
3678 case 0x00400000: func (stream, "h"); break;
3679 case 0x00000100: func (stream, "w"); break;
3680 case 0x00400100: func (stream, "d"); break;
3681 default:
3682 break;
3683 }
3684 break;
3685
3686 case 'Z':
3687 {
3688 /* given (20, 23) | given (0, 3) */
3689 value = ((given >> 16) & 0xf0) | (given & 0xf);
3690 func (stream, "%d", (int) value);
3691 }
3692 break;
3693
3694 case 'l':
3695 /* This is like the 'A' operator, except that if
3696 the width field "M" is zero, then the offset is
3697 *not* multiplied by four. */
3698 {
3699 int offset = given & 0xff;
3700 int multiplier = (given & 0x00000100) ? 4 : 1;
3701
3702 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3703
3704 if (multiplier > 1)
3705 {
3706 value_in_comment = offset * multiplier;
3707 if (NEGATIVE_BIT_SET)
3708 value_in_comment = - value_in_comment;
3709 }
3710
3711 if (offset)
3712 {
3713 if (PRE_BIT_SET)
3714 func (stream, ", #%s%d]%s",
3715 NEGATIVE_BIT_SET ? "-" : "",
3716 offset * multiplier,
3717 WRITEBACK_BIT_SET ? "!" : "");
3718 else
3719 func (stream, "], #%s%d",
3720 NEGATIVE_BIT_SET ? "-" : "",
3721 offset * multiplier);
3722 }
3723 else
3724 func (stream, "]");
3725 }
3726 break;
3727
3728 case 'r':
3729 {
3730 int imm4 = (given >> 4) & 0xf;
3731 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3732 int ubit = ! NEGATIVE_BIT_SET;
3733 const char *rm = arm_regnames [given & 0xf];
3734 const char *rn = arm_regnames [(given >> 16) & 0xf];
3735
3736 switch (puw_bits)
3737 {
3738 case 1:
3739 case 3:
3740 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3741 if (imm4)
3742 func (stream, ", lsl #%d", imm4);
3743 break;
3744
3745 case 4:
3746 case 5:
3747 case 6:
3748 case 7:
3749 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3750 if (imm4 > 0)
3751 func (stream, ", lsl #%d", imm4);
3752 func (stream, "]");
3753 if (puw_bits == 5 || puw_bits == 7)
3754 func (stream, "!");
3755 break;
3756
3757 default:
3758 func (stream, "INVALID");
3759 }
3760 }
3761 break;
3762
3763 case 'i':
3764 {
3765 long imm5;
3766 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3767 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
3768 }
3769 break;
3770
3771 default:
3772 abort ();
3773 }
3774 }
3775 }
3776 else
3777 func (stream, "%c", *c);
3778 }
3779
3780 if (value_in_comment > 32 || value_in_comment < -16)
3781 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
3782
3783 if (is_unpredictable)
3784 func (stream, UNPREDICTABLE_INSTRUCTION);
3785
3786 return TRUE;
3787 }
3788 return FALSE;
3789 }
3790
3791 /* Decodes and prints ARM addressing modes. Returns the offset
3792 used in the address, if any, if it is worthwhile printing the
3793 offset as a hexadecimal value in a comment at the end of the
3794 line of disassembly. */
3795
3796 static signed long
3797 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
3798 {
3799 void *stream = info->stream;
3800 fprintf_ftype func = info->fprintf_func;
3801 bfd_vma offset = 0;
3802
3803 if (((given & 0x000f0000) == 0x000f0000)
3804 && ((given & 0x02000000) == 0))
3805 {
3806 offset = given & 0xfff;
3807
3808 func (stream, "[pc");
3809
3810 if (PRE_BIT_SET)
3811 {
3812 /* Pre-indexed. Elide offset of positive zero when
3813 non-writeback. */
3814 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
3815 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3816
3817 if (NEGATIVE_BIT_SET)
3818 offset = -offset;
3819
3820 offset += pc + 8;
3821
3822 /* Cope with the possibility of write-back
3823 being used. Probably a very dangerous thing
3824 for the programmer to do, but who are we to
3825 argue ? */
3826 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
3827 }
3828 else /* Post indexed. */
3829 {
3830 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3831
3832 /* Ie ignore the offset. */
3833 offset = pc + 8;
3834 }
3835
3836 func (stream, "\t; ");
3837 info->print_address_func (offset, info);
3838 offset = 0;
3839 }
3840 else
3841 {
3842 func (stream, "[%s",
3843 arm_regnames[(given >> 16) & 0xf]);
3844
3845 if (PRE_BIT_SET)
3846 {
3847 if ((given & 0x02000000) == 0)
3848 {
3849 /* Elide offset of positive zero when non-writeback. */
3850 offset = given & 0xfff;
3851 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
3852 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3853 }
3854 else
3855 {
3856 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
3857 arm_decode_shift (given, func, stream, TRUE);
3858 }
3859
3860 func (stream, "]%s",
3861 WRITEBACK_BIT_SET ? "!" : "");
3862 }
3863 else
3864 {
3865 if ((given & 0x02000000) == 0)
3866 {
3867 /* Always show offset. */
3868 offset = given & 0xfff;
3869 func (stream, "], #%s%d",
3870 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3871 }
3872 else
3873 {
3874 func (stream, "], %s",
3875 NEGATIVE_BIT_SET ? "-" : "");
3876 arm_decode_shift (given, func, stream, TRUE);
3877 }
3878 }
3879 if (NEGATIVE_BIT_SET)
3880 offset = -offset;
3881 }
3882
3883 return (signed long) offset;
3884 }
3885
3886 /* Print one neon instruction on INFO->STREAM.
3887 Return TRUE if the instuction matched, FALSE if this is not a
3888 recognised neon instruction. */
3889
3890 static bfd_boolean
3891 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
3892 {
3893 const struct opcode32 *insn;
3894 void *stream = info->stream;
3895 fprintf_ftype func = info->fprintf_func;
3896
3897 if (thumb)
3898 {
3899 if ((given & 0xef000000) == 0xef000000)
3900 {
3901 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
3902 unsigned long bit28 = given & (1 << 28);
3903
3904 given &= 0x00ffffff;
3905 if (bit28)
3906 given |= 0xf3000000;
3907 else
3908 given |= 0xf2000000;
3909 }
3910 else if ((given & 0xff000000) == 0xf9000000)
3911 given ^= 0xf9000000 ^ 0xf4000000;
3912 else
3913 return FALSE;
3914 }
3915
3916 for (insn = neon_opcodes; insn->assembler; insn++)
3917 {
3918 if ((given & insn->mask) == insn->value)
3919 {
3920 signed long value_in_comment = 0;
3921 bfd_boolean is_unpredictable = FALSE;
3922 const char *c;
3923
3924 for (c = insn->assembler; *c; c++)
3925 {
3926 if (*c == '%')
3927 {
3928 switch (*++c)
3929 {
3930 case '%':
3931 func (stream, "%%");
3932 break;
3933
3934 case 'u':
3935 if (thumb && ifthen_state)
3936 is_unpredictable = TRUE;
3937
3938 /* Fall through. */
3939 case 'c':
3940 if (thumb && ifthen_state)
3941 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3942 break;
3943
3944 case 'A':
3945 {
3946 static const unsigned char enc[16] =
3947 {
3948 0x4, 0x14, /* st4 0,1 */
3949 0x4, /* st1 2 */
3950 0x4, /* st2 3 */
3951 0x3, /* st3 4 */
3952 0x13, /* st3 5 */
3953 0x3, /* st1 6 */
3954 0x1, /* st1 7 */
3955 0x2, /* st2 8 */
3956 0x12, /* st2 9 */
3957 0x2, /* st1 10 */
3958 0, 0, 0, 0, 0
3959 };
3960 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3961 int rn = ((given >> 16) & 0xf);
3962 int rm = ((given >> 0) & 0xf);
3963 int align = ((given >> 4) & 0x3);
3964 int type = ((given >> 8) & 0xf);
3965 int n = enc[type] & 0xf;
3966 int stride = (enc[type] >> 4) + 1;
3967 int ix;
3968
3969 func (stream, "{");
3970 if (stride > 1)
3971 for (ix = 0; ix != n; ix++)
3972 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
3973 else if (n == 1)
3974 func (stream, "d%d", rd);
3975 else
3976 func (stream, "d%d-d%d", rd, rd + n - 1);
3977 func (stream, "}, [%s", arm_regnames[rn]);
3978 if (align)
3979 func (stream, " :%d", 32 << align);
3980 func (stream, "]");
3981 if (rm == 0xd)
3982 func (stream, "!");
3983 else if (rm != 0xf)
3984 func (stream, ", %s", arm_regnames[rm]);
3985 }
3986 break;
3987
3988 case 'B':
3989 {
3990 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3991 int rn = ((given >> 16) & 0xf);
3992 int rm = ((given >> 0) & 0xf);
3993 int idx_align = ((given >> 4) & 0xf);
3994 int align = 0;
3995 int size = ((given >> 10) & 0x3);
3996 int idx = idx_align >> (size + 1);
3997 int length = ((given >> 8) & 3) + 1;
3998 int stride = 1;
3999 int i;
4000
4001 if (length > 1 && size > 0)
4002 stride = (idx_align & (1 << size)) ? 2 : 1;
4003
4004 switch (length)
4005 {
4006 case 1:
4007 {
4008 int amask = (1 << size) - 1;
4009 if ((idx_align & (1 << size)) != 0)
4010 return FALSE;
4011 if (size > 0)
4012 {
4013 if ((idx_align & amask) == amask)
4014 align = 8 << size;
4015 else if ((idx_align & amask) != 0)
4016 return FALSE;
4017 }
4018 }
4019 break;
4020
4021 case 2:
4022 if (size == 2 && (idx_align & 2) != 0)
4023 return FALSE;
4024 align = (idx_align & 1) ? 16 << size : 0;
4025 break;
4026
4027 case 3:
4028 if ((size == 2 && (idx_align & 3) != 0)
4029 || (idx_align & 1) != 0)
4030 return FALSE;
4031 break;
4032
4033 case 4:
4034 if (size == 2)
4035 {
4036 if ((idx_align & 3) == 3)
4037 return FALSE;
4038 align = (idx_align & 3) * 64;
4039 }
4040 else
4041 align = (idx_align & 1) ? 32 << size : 0;
4042 break;
4043
4044 default:
4045 abort ();
4046 }
4047
4048 func (stream, "{");
4049 for (i = 0; i < length; i++)
4050 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4051 rd + i * stride, idx);
4052 func (stream, "}, [%s", arm_regnames[rn]);
4053 if (align)
4054 func (stream, " :%d", align);
4055 func (stream, "]");
4056 if (rm == 0xd)
4057 func (stream, "!");
4058 else if (rm != 0xf)
4059 func (stream, ", %s", arm_regnames[rm]);
4060 }
4061 break;
4062
4063 case 'C':
4064 {
4065 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4066 int rn = ((given >> 16) & 0xf);
4067 int rm = ((given >> 0) & 0xf);
4068 int align = ((given >> 4) & 0x1);
4069 int size = ((given >> 6) & 0x3);
4070 int type = ((given >> 8) & 0x3);
4071 int n = type + 1;
4072 int stride = ((given >> 5) & 0x1);
4073 int ix;
4074
4075 if (stride && (n == 1))
4076 n++;
4077 else
4078 stride++;
4079
4080 func (stream, "{");
4081 if (stride > 1)
4082 for (ix = 0; ix != n; ix++)
4083 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4084 else if (n == 1)
4085 func (stream, "d%d[]", rd);
4086 else
4087 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4088 func (stream, "}, [%s", arm_regnames[rn]);
4089 if (align)
4090 {
4091 align = (8 * (type + 1)) << size;
4092 if (type == 3)
4093 align = (size > 1) ? align >> 1 : align;
4094 if (type == 2 || (type == 0 && !size))
4095 func (stream, " :<bad align %d>", align);
4096 else
4097 func (stream, " :%d", align);
4098 }
4099 func (stream, "]");
4100 if (rm == 0xd)
4101 func (stream, "!");
4102 else if (rm != 0xf)
4103 func (stream, ", %s", arm_regnames[rm]);
4104 }
4105 break;
4106
4107 case 'D':
4108 {
4109 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4110 int size = (given >> 20) & 3;
4111 int reg = raw_reg & ((4 << size) - 1);
4112 int ix = raw_reg >> size >> 2;
4113
4114 func (stream, "d%d[%d]", reg, ix);
4115 }
4116 break;
4117
4118 case 'E':
4119 /* Neon encoded constant for mov, mvn, vorr, vbic. */
4120 {
4121 int bits = 0;
4122 int cmode = (given >> 8) & 0xf;
4123 int op = (given >> 5) & 0x1;
4124 unsigned long value = 0, hival = 0;
4125 unsigned shift;
4126 int size = 0;
4127 int isfloat = 0;
4128
4129 bits |= ((given >> 24) & 1) << 7;
4130 bits |= ((given >> 16) & 7) << 4;
4131 bits |= ((given >> 0) & 15) << 0;
4132
4133 if (cmode < 8)
4134 {
4135 shift = (cmode >> 1) & 3;
4136 value = (unsigned long) bits << (8 * shift);
4137 size = 32;
4138 }
4139 else if (cmode < 12)
4140 {
4141 shift = (cmode >> 1) & 1;
4142 value = (unsigned long) bits << (8 * shift);
4143 size = 16;
4144 }
4145 else if (cmode < 14)
4146 {
4147 shift = (cmode & 1) + 1;
4148 value = (unsigned long) bits << (8 * shift);
4149 value |= (1ul << (8 * shift)) - 1;
4150 size = 32;
4151 }
4152 else if (cmode == 14)
4153 {
4154 if (op)
4155 {
4156 /* Bit replication into bytes. */
4157 int ix;
4158 unsigned long mask;
4159
4160 value = 0;
4161 hival = 0;
4162 for (ix = 7; ix >= 0; ix--)
4163 {
4164 mask = ((bits >> ix) & 1) ? 0xff : 0;
4165 if (ix <= 3)
4166 value = (value << 8) | mask;
4167 else
4168 hival = (hival << 8) | mask;
4169 }
4170 size = 64;
4171 }
4172 else
4173 {
4174 /* Byte replication. */
4175 value = (unsigned long) bits;
4176 size = 8;
4177 }
4178 }
4179 else if (!op)
4180 {
4181 /* Floating point encoding. */
4182 int tmp;
4183
4184 value = (unsigned long) (bits & 0x7f) << 19;
4185 value |= (unsigned long) (bits & 0x80) << 24;
4186 tmp = bits & 0x40 ? 0x3c : 0x40;
4187 value |= (unsigned long) tmp << 24;
4188 size = 32;
4189 isfloat = 1;
4190 }
4191 else
4192 {
4193 func (stream, "<illegal constant %.8x:%x:%x>",
4194 bits, cmode, op);
4195 size = 32;
4196 break;
4197 }
4198 switch (size)
4199 {
4200 case 8:
4201 func (stream, "#%ld\t; 0x%.2lx", value, value);
4202 break;
4203
4204 case 16:
4205 func (stream, "#%ld\t; 0x%.4lx", value, value);
4206 break;
4207
4208 case 32:
4209 if (isfloat)
4210 {
4211 unsigned char valbytes[4];
4212 double fvalue;
4213
4214 /* Do this a byte at a time so we don't have to
4215 worry about the host's endianness. */
4216 valbytes[0] = value & 0xff;
4217 valbytes[1] = (value >> 8) & 0xff;
4218 valbytes[2] = (value >> 16) & 0xff;
4219 valbytes[3] = (value >> 24) & 0xff;
4220
4221 floatformat_to_double
4222 (& floatformat_ieee_single_little, valbytes,
4223 & fvalue);
4224
4225 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4226 value);
4227 }
4228 else
4229 func (stream, "#%ld\t; 0x%.8lx",
4230 (long) (((value & 0x80000000L) != 0)
4231 ? value | ~0xffffffffL : value),
4232 value);
4233 break;
4234
4235 case 64:
4236 func (stream, "#0x%.8lx%.8lx", hival, value);
4237 break;
4238
4239 default:
4240 abort ();
4241 }
4242 }
4243 break;
4244
4245 case 'F':
4246 {
4247 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4248 int num = (given >> 8) & 0x3;
4249
4250 if (!num)
4251 func (stream, "{d%d}", regno);
4252 else if (num + regno >= 32)
4253 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4254 else
4255 func (stream, "{d%d-d%d}", regno, regno + num);
4256 }
4257 break;
4258
4259
4260 case '0': case '1': case '2': case '3': case '4':
4261 case '5': case '6': case '7': case '8': case '9':
4262 {
4263 int width;
4264 unsigned long value;
4265
4266 c = arm_decode_bitfield (c, given, &value, &width);
4267
4268 switch (*c)
4269 {
4270 case 'r':
4271 func (stream, "%s", arm_regnames[value]);
4272 break;
4273 case 'd':
4274 func (stream, "%ld", value);
4275 value_in_comment = value;
4276 break;
4277 case 'e':
4278 func (stream, "%ld", (1ul << width) - value);
4279 break;
4280
4281 case 'S':
4282 case 'T':
4283 case 'U':
4284 /* Various width encodings. */
4285 {
4286 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4287 int limit;
4288 unsigned low, high;
4289
4290 c++;
4291 if (*c >= '0' && *c <= '9')
4292 limit = *c - '0';
4293 else if (*c >= 'a' && *c <= 'f')
4294 limit = *c - 'a' + 10;
4295 else
4296 abort ();
4297 low = limit >> 2;
4298 high = limit & 3;
4299
4300 if (value < low || value > high)
4301 func (stream, "<illegal width %d>", base << value);
4302 else
4303 func (stream, "%d", base << value);
4304 }
4305 break;
4306 case 'R':
4307 if (given & (1 << 6))
4308 goto Q;
4309 /* FALLTHROUGH */
4310 case 'D':
4311 func (stream, "d%ld", value);
4312 break;
4313 case 'Q':
4314 Q:
4315 if (value & 1)
4316 func (stream, "<illegal reg q%ld.5>", value >> 1);
4317 else
4318 func (stream, "q%ld", value >> 1);
4319 break;
4320
4321 case '`':
4322 c++;
4323 if (value == 0)
4324 func (stream, "%c", *c);
4325 break;
4326 case '\'':
4327 c++;
4328 if (value == ((1ul << width) - 1))
4329 func (stream, "%c", *c);
4330 break;
4331 case '?':
4332 func (stream, "%c", c[(1 << width) - (int) value]);
4333 c += 1 << width;
4334 break;
4335 default:
4336 abort ();
4337 }
4338 break;
4339
4340 default:
4341 abort ();
4342 }
4343 }
4344 }
4345 else
4346 func (stream, "%c", *c);
4347 }
4348
4349 if (value_in_comment > 32 || value_in_comment < -16)
4350 func (stream, "\t; 0x%lx", value_in_comment);
4351
4352 if (is_unpredictable)
4353 func (stream, UNPREDICTABLE_INSTRUCTION);
4354
4355 return TRUE;
4356 }
4357 }
4358 return FALSE;
4359 }
4360
4361 /* Return the name of a v7A special register. */
4362
4363 static const char *
4364 banked_regname (unsigned reg)
4365 {
4366 switch (reg)
4367 {
4368 case 15: return "CPSR";
4369 case 32: return "R8_usr";
4370 case 33: return "R9_usr";
4371 case 34: return "R10_usr";
4372 case 35: return "R11_usr";
4373 case 36: return "R12_usr";
4374 case 37: return "SP_usr";
4375 case 38: return "LR_usr";
4376 case 40: return "R8_fiq";
4377 case 41: return "R9_fiq";
4378 case 42: return "R10_fiq";
4379 case 43: return "R11_fiq";
4380 case 44: return "R12_fiq";
4381 case 45: return "SP_fiq";
4382 case 46: return "LR_fiq";
4383 case 48: return "LR_irq";
4384 case 49: return "SP_irq";
4385 case 50: return "LR_svc";
4386 case 51: return "SP_svc";
4387 case 52: return "LR_abt";
4388 case 53: return "SP_abt";
4389 case 54: return "LR_und";
4390 case 55: return "SP_und";
4391 case 60: return "LR_mon";
4392 case 61: return "SP_mon";
4393 case 62: return "ELR_hyp";
4394 case 63: return "SP_hyp";
4395 case 79: return "SPSR";
4396 case 110: return "SPSR_fiq";
4397 case 112: return "SPSR_irq";
4398 case 114: return "SPSR_svc";
4399 case 116: return "SPSR_abt";
4400 case 118: return "SPSR_und";
4401 case 124: return "SPSR_mon";
4402 case 126: return "SPSR_hyp";
4403 default: return NULL;
4404 }
4405 }
4406
4407 /* Return the name of the DMB/DSB option. */
4408 static const char *
4409 data_barrier_option (unsigned option)
4410 {
4411 switch (option & 0xf)
4412 {
4413 case 0xf: return "sy";
4414 case 0xe: return "st";
4415 case 0xd: return "ld";
4416 case 0xb: return "ish";
4417 case 0xa: return "ishst";
4418 case 0x9: return "ishld";
4419 case 0x7: return "un";
4420 case 0x6: return "unst";
4421 case 0x5: return "nshld";
4422 case 0x3: return "osh";
4423 case 0x2: return "oshst";
4424 case 0x1: return "oshld";
4425 default: return NULL;
4426 }
4427 }
4428
4429 /* Print one ARM instruction from PC on INFO->STREAM. */
4430
4431 static void
4432 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
4433 {
4434 const struct opcode32 *insn;
4435 void *stream = info->stream;
4436 fprintf_ftype func = info->fprintf_func;
4437 struct arm_private_data *private_data = info->private_data;
4438
4439 if (print_insn_coprocessor (pc, info, given, FALSE))
4440 return;
4441
4442 if (print_insn_neon (info, given, FALSE))
4443 return;
4444
4445 for (insn = arm_opcodes; insn->assembler; insn++)
4446 {
4447 if ((given & insn->mask) != insn->value)
4448 continue;
4449
4450 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
4451 continue;
4452
4453 /* Special case: an instruction with all bits set in the condition field
4454 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4455 or by the catchall at the end of the table. */
4456 if ((given & 0xF0000000) != 0xF0000000
4457 || (insn->mask & 0xF0000000) == 0xF0000000
4458 || (insn->mask == 0 && insn->value == 0))
4459 {
4460 unsigned long u_reg = 16;
4461 unsigned long U_reg = 16;
4462 bfd_boolean is_unpredictable = FALSE;
4463 signed long value_in_comment = 0;
4464 const char *c;
4465
4466 for (c = insn->assembler; *c; c++)
4467 {
4468 if (*c == '%')
4469 {
4470 bfd_boolean allow_unpredictable = FALSE;
4471
4472 switch (*++c)
4473 {
4474 case '%':
4475 func (stream, "%%");
4476 break;
4477
4478 case 'a':
4479 value_in_comment = print_arm_address (pc, info, given);
4480 break;
4481
4482 case 'P':
4483 /* Set P address bit and use normal address
4484 printing routine. */
4485 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
4486 break;
4487
4488 case 'S':
4489 allow_unpredictable = TRUE;
4490 case 's':
4491 if ((given & 0x004f0000) == 0x004f0000)
4492 {
4493 /* PC relative with immediate offset. */
4494 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
4495
4496 if (PRE_BIT_SET)
4497 {
4498 /* Elide positive zero offset. */
4499 if (offset || NEGATIVE_BIT_SET)
4500 func (stream, "[pc, #%s%d]\t; ",
4501 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4502 else
4503 func (stream, "[pc]\t; ");
4504 if (NEGATIVE_BIT_SET)
4505 offset = -offset;
4506 info->print_address_func (offset + pc + 8, info);
4507 }
4508 else
4509 {
4510 /* Always show the offset. */
4511 func (stream, "[pc], #%s%d",
4512 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4513 if (! allow_unpredictable)
4514 is_unpredictable = TRUE;
4515 }
4516 }
4517 else
4518 {
4519 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4520
4521 func (stream, "[%s",
4522 arm_regnames[(given >> 16) & 0xf]);
4523
4524 if (PRE_BIT_SET)
4525 {
4526 if (IMMEDIATE_BIT_SET)
4527 {
4528 /* Elide offset for non-writeback
4529 positive zero. */
4530 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4531 || offset)
4532 func (stream, ", #%s%d",
4533 NEGATIVE_BIT_SET ? "-" : "", offset);
4534
4535 if (NEGATIVE_BIT_SET)
4536 offset = -offset;
4537
4538 value_in_comment = offset;
4539 }
4540 else
4541 {
4542 /* Register Offset or Register Pre-Indexed. */
4543 func (stream, ", %s%s",
4544 NEGATIVE_BIT_SET ? "-" : "",
4545 arm_regnames[given & 0xf]);
4546
4547 /* Writing back to the register that is the source/
4548 destination of the load/store is unpredictable. */
4549 if (! allow_unpredictable
4550 && WRITEBACK_BIT_SET
4551 && ((given & 0xf) == ((given >> 12) & 0xf)))
4552 is_unpredictable = TRUE;
4553 }
4554
4555 func (stream, "]%s",
4556 WRITEBACK_BIT_SET ? "!" : "");
4557 }
4558 else
4559 {
4560 if (IMMEDIATE_BIT_SET)
4561 {
4562 /* Immediate Post-indexed. */
4563 /* PR 10924: Offset must be printed, even if it is zero. */
4564 func (stream, "], #%s%d",
4565 NEGATIVE_BIT_SET ? "-" : "", offset);
4566 if (NEGATIVE_BIT_SET)
4567 offset = -offset;
4568 value_in_comment = offset;
4569 }
4570 else
4571 {
4572 /* Register Post-indexed. */
4573 func (stream, "], %s%s",
4574 NEGATIVE_BIT_SET ? "-" : "",
4575 arm_regnames[given & 0xf]);
4576
4577 /* Writing back to the register that is the source/
4578 destination of the load/store is unpredictable. */
4579 if (! allow_unpredictable
4580 && (given & 0xf) == ((given >> 12) & 0xf))
4581 is_unpredictable = TRUE;
4582 }
4583
4584 if (! allow_unpredictable)
4585 {
4586 /* Writeback is automatically implied by post- addressing.
4587 Setting the W bit is unnecessary and ARM specify it as
4588 being unpredictable. */
4589 if (WRITEBACK_BIT_SET
4590 /* Specifying the PC register as the post-indexed
4591 registers is also unpredictable. */
4592 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4593 is_unpredictable = TRUE;
4594 }
4595 }
4596 }
4597 break;
4598
4599 case 'b':
4600 {
4601 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
4602 info->print_address_func (disp * 4 + pc + 8, info);
4603 }
4604 break;
4605
4606 case 'c':
4607 if (((given >> 28) & 0xf) != 0xe)
4608 func (stream, "%s",
4609 arm_conditional [(given >> 28) & 0xf]);
4610 break;
4611
4612 case 'm':
4613 {
4614 int started = 0;
4615 int reg;
4616
4617 func (stream, "{");
4618 for (reg = 0; reg < 16; reg++)
4619 if ((given & (1 << reg)) != 0)
4620 {
4621 if (started)
4622 func (stream, ", ");
4623 started = 1;
4624 func (stream, "%s", arm_regnames[reg]);
4625 }
4626 func (stream, "}");
4627 if (! started)
4628 is_unpredictable = TRUE;
4629 }
4630 break;
4631
4632 case 'q':
4633 arm_decode_shift (given, func, stream, FALSE);
4634 break;
4635
4636 case 'o':
4637 if ((given & 0x02000000) != 0)
4638 {
4639 unsigned int rotate = (given & 0xf00) >> 7;
4640 unsigned int immed = (given & 0xff);
4641 unsigned int a, i;
4642
4643 a = (((immed << (32 - rotate))
4644 | (immed >> rotate)) & 0xffffffff);
4645 /* If there is another encoding with smaller rotate,
4646 the rotate should be specified directly. */
4647 for (i = 0; i < 32; i += 2)
4648 if ((a << i | a >> (32 - i)) <= 0xff)
4649 break;
4650
4651 if (i != rotate)
4652 func (stream, "#%d, %d", immed, rotate);
4653 else
4654 func (stream, "#%d", a);
4655 value_in_comment = a;
4656 }
4657 else
4658 arm_decode_shift (given, func, stream, TRUE);
4659 break;
4660
4661 case 'p':
4662 if ((given & 0x0000f000) == 0x0000f000)
4663 {
4664 arm_feature_set arm_ext_v6 =
4665 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4666
4667 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4668 mechanism for setting PSR flag bits. They are
4669 obsolete in V6 onwards. */
4670 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4671 arm_ext_v6))
4672 func (stream, "p");
4673 else
4674 is_unpredictable = TRUE;
4675 }
4676 break;
4677
4678 case 't':
4679 if ((given & 0x01200000) == 0x00200000)
4680 func (stream, "t");
4681 break;
4682
4683 case 'A':
4684 {
4685 int offset = given & 0xff;
4686
4687 value_in_comment = offset * 4;
4688 if (NEGATIVE_BIT_SET)
4689 value_in_comment = - value_in_comment;
4690
4691 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4692
4693 if (PRE_BIT_SET)
4694 {
4695 if (offset)
4696 func (stream, ", #%d]%s",
4697 (int) value_in_comment,
4698 WRITEBACK_BIT_SET ? "!" : "");
4699 else
4700 func (stream, "]");
4701 }
4702 else
4703 {
4704 func (stream, "]");
4705
4706 if (WRITEBACK_BIT_SET)
4707 {
4708 if (offset)
4709 func (stream, ", #%d", (int) value_in_comment);
4710 }
4711 else
4712 {
4713 func (stream, ", {%d}", (int) offset);
4714 value_in_comment = offset;
4715 }
4716 }
4717 }
4718 break;
4719
4720 case 'B':
4721 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4722 {
4723 bfd_vma address;
4724 bfd_vma offset = 0;
4725
4726 if (! NEGATIVE_BIT_SET)
4727 /* Is signed, hi bits should be ones. */
4728 offset = (-1) ^ 0x00ffffff;
4729
4730 /* Offset is (SignExtend(offset field)<<2). */
4731 offset += given & 0x00ffffff;
4732 offset <<= 2;
4733 address = offset + pc + 8;
4734
4735 if (given & 0x01000000)
4736 /* H bit allows addressing to 2-byte boundaries. */
4737 address += 2;
4738
4739 info->print_address_func (address, info);
4740 }
4741 break;
4742
4743 case 'C':
4744 if ((given & 0x02000200) == 0x200)
4745 {
4746 const char * name;
4747 unsigned sysm = (given & 0x004f0000) >> 16;
4748
4749 sysm |= (given & 0x300) >> 4;
4750 name = banked_regname (sysm);
4751
4752 if (name != NULL)
4753 func (stream, "%s", name);
4754 else
4755 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4756 }
4757 else
4758 {
4759 func (stream, "%cPSR_",
4760 (given & 0x00400000) ? 'S' : 'C');
4761 if (given & 0x80000)
4762 func (stream, "f");
4763 if (given & 0x40000)
4764 func (stream, "s");
4765 if (given & 0x20000)
4766 func (stream, "x");
4767 if (given & 0x10000)
4768 func (stream, "c");
4769 }
4770 break;
4771
4772 case 'U':
4773 if ((given & 0xf0) == 0x60)
4774 {
4775 switch (given & 0xf)
4776 {
4777 case 0xf: func (stream, "sy"); break;
4778 default:
4779 func (stream, "#%d", (int) given & 0xf);
4780 break;
4781 }
4782 }
4783 else
4784 {
4785 const char * opt = data_barrier_option (given & 0xf);
4786 if (opt != NULL)
4787 func (stream, "%s", opt);
4788 else
4789 func (stream, "#%d", (int) given & 0xf);
4790 }
4791 break;
4792
4793 case '0': case '1': case '2': case '3': case '4':
4794 case '5': case '6': case '7': case '8': case '9':
4795 {
4796 int width;
4797 unsigned long value;
4798
4799 c = arm_decode_bitfield (c, given, &value, &width);
4800
4801 switch (*c)
4802 {
4803 case 'R':
4804 if (value == 15)
4805 is_unpredictable = TRUE;
4806 /* Fall through. */
4807 case 'r':
4808 case 'T':
4809 /* We want register + 1 when decoding T. */
4810 if (*c == 'T')
4811 ++value;
4812
4813 if (c[1] == 'u')
4814 {
4815 /* Eat the 'u' character. */
4816 ++ c;
4817
4818 if (u_reg == value)
4819 is_unpredictable = TRUE;
4820 u_reg = value;
4821 }
4822 if (c[1] == 'U')
4823 {
4824 /* Eat the 'U' character. */
4825 ++ c;
4826
4827 if (U_reg == value)
4828 is_unpredictable = TRUE;
4829 U_reg = value;
4830 }
4831 func (stream, "%s", arm_regnames[value]);
4832 break;
4833 case 'd':
4834 func (stream, "%ld", value);
4835 value_in_comment = value;
4836 break;
4837 case 'b':
4838 func (stream, "%ld", value * 8);
4839 value_in_comment = value * 8;
4840 break;
4841 case 'W':
4842 func (stream, "%ld", value + 1);
4843 value_in_comment = value + 1;
4844 break;
4845 case 'x':
4846 func (stream, "0x%08lx", value);
4847
4848 /* Some SWI instructions have special
4849 meanings. */
4850 if ((given & 0x0fffffff) == 0x0FF00000)
4851 func (stream, "\t; IMB");
4852 else if ((given & 0x0fffffff) == 0x0FF00001)
4853 func (stream, "\t; IMBRange");
4854 break;
4855 case 'X':
4856 func (stream, "%01lx", value & 0xf);
4857 value_in_comment = value;
4858 break;
4859 case '`':
4860 c++;
4861 if (value == 0)
4862 func (stream, "%c", *c);
4863 break;
4864 case '\'':
4865 c++;
4866 if (value == ((1ul << width) - 1))
4867 func (stream, "%c", *c);
4868 break;
4869 case '?':
4870 func (stream, "%c", c[(1 << width) - (int) value]);
4871 c += 1 << width;
4872 break;
4873 default:
4874 abort ();
4875 }
4876 break;
4877
4878 case 'e':
4879 {
4880 int imm;
4881
4882 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
4883 func (stream, "%d", imm);
4884 value_in_comment = imm;
4885 }
4886 break;
4887
4888 case 'E':
4889 /* LSB and WIDTH fields of BFI or BFC. The machine-
4890 language instruction encodes LSB and MSB. */
4891 {
4892 long msb = (given & 0x001f0000) >> 16;
4893 long lsb = (given & 0x00000f80) >> 7;
4894 long w = msb - lsb + 1;
4895
4896 if (w > 0)
4897 func (stream, "#%lu, #%lu", lsb, w);
4898 else
4899 func (stream, "(invalid: %lu:%lu)", lsb, msb);
4900 }
4901 break;
4902
4903 case 'R':
4904 /* Get the PSR/banked register name. */
4905 {
4906 const char * name;
4907 unsigned sysm = (given & 0x004f0000) >> 16;
4908
4909 sysm |= (given & 0x300) >> 4;
4910 name = banked_regname (sysm);
4911
4912 if (name != NULL)
4913 func (stream, "%s", name);
4914 else
4915 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4916 }
4917 break;
4918
4919 case 'V':
4920 /* 16-bit unsigned immediate from a MOVT or MOVW
4921 instruction, encoded in bits 0:11 and 15:19. */
4922 {
4923 long hi = (given & 0x000f0000) >> 4;
4924 long lo = (given & 0x00000fff);
4925 long imm16 = hi | lo;
4926
4927 func (stream, "#%lu", imm16);
4928 value_in_comment = imm16;
4929 }
4930 break;
4931
4932 default:
4933 abort ();
4934 }
4935 }
4936 }
4937 else
4938 func (stream, "%c", *c);
4939 }
4940
4941 if (value_in_comment > 32 || value_in_comment < -16)
4942 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
4943
4944 if (is_unpredictable)
4945 func (stream, UNPREDICTABLE_INSTRUCTION);
4946
4947 return;
4948 }
4949 }
4950 abort ();
4951 }
4952
4953 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
4954
4955 static void
4956 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
4957 {
4958 const struct opcode16 *insn;
4959 void *stream = info->stream;
4960 fprintf_ftype func = info->fprintf_func;
4961
4962 for (insn = thumb_opcodes; insn->assembler; insn++)
4963 if ((given & insn->mask) == insn->value)
4964 {
4965 signed long value_in_comment = 0;
4966 const char *c = insn->assembler;
4967
4968 for (; *c; c++)
4969 {
4970 int domaskpc = 0;
4971 int domasklr = 0;
4972
4973 if (*c != '%')
4974 {
4975 func (stream, "%c", *c);
4976 continue;
4977 }
4978
4979 switch (*++c)
4980 {
4981 case '%':
4982 func (stream, "%%");
4983 break;
4984
4985 case 'c':
4986 if (ifthen_state)
4987 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4988 break;
4989
4990 case 'C':
4991 if (ifthen_state)
4992 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4993 else
4994 func (stream, "s");
4995 break;
4996
4997 case 'I':
4998 {
4999 unsigned int tmp;
5000
5001 ifthen_next_state = given & 0xff;
5002 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5003 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5004 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5005 }
5006 break;
5007
5008 case 'x':
5009 if (ifthen_next_state)
5010 func (stream, "\t; unpredictable branch in IT block\n");
5011 break;
5012
5013 case 'X':
5014 if (ifthen_state)
5015 func (stream, "\t; unpredictable <IT:%s>",
5016 arm_conditional[IFTHEN_COND]);
5017 break;
5018
5019 case 'S':
5020 {
5021 long reg;
5022
5023 reg = (given >> 3) & 0x7;
5024 if (given & (1 << 6))
5025 reg += 8;
5026
5027 func (stream, "%s", arm_regnames[reg]);
5028 }
5029 break;
5030
5031 case 'D':
5032 {
5033 long reg;
5034
5035 reg = given & 0x7;
5036 if (given & (1 << 7))
5037 reg += 8;
5038
5039 func (stream, "%s", arm_regnames[reg]);
5040 }
5041 break;
5042
5043 case 'N':
5044 if (given & (1 << 8))
5045 domasklr = 1;
5046 /* Fall through. */
5047 case 'O':
5048 if (*c == 'O' && (given & (1 << 8)))
5049 domaskpc = 1;
5050 /* Fall through. */
5051 case 'M':
5052 {
5053 int started = 0;
5054 int reg;
5055
5056 func (stream, "{");
5057
5058 /* It would be nice if we could spot
5059 ranges, and generate the rS-rE format: */
5060 for (reg = 0; (reg < 8); reg++)
5061 if ((given & (1 << reg)) != 0)
5062 {
5063 if (started)
5064 func (stream, ", ");
5065 started = 1;
5066 func (stream, "%s", arm_regnames[reg]);
5067 }
5068
5069 if (domasklr)
5070 {
5071 if (started)
5072 func (stream, ", ");
5073 started = 1;
5074 func (stream, "%s", arm_regnames[14] /* "lr" */);
5075 }
5076
5077 if (domaskpc)
5078 {
5079 if (started)
5080 func (stream, ", ");
5081 func (stream, "%s", arm_regnames[15] /* "pc" */);
5082 }
5083
5084 func (stream, "}");
5085 }
5086 break;
5087
5088 case 'W':
5089 /* Print writeback indicator for a LDMIA. We are doing a
5090 writeback if the base register is not in the register
5091 mask. */
5092 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5093 func (stream, "!");
5094 break;
5095
5096 case 'b':
5097 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5098 {
5099 bfd_vma address = (pc + 4
5100 + ((given & 0x00f8) >> 2)
5101 + ((given & 0x0200) >> 3));
5102 info->print_address_func (address, info);
5103 }
5104 break;
5105
5106 case 's':
5107 /* Right shift immediate -- bits 6..10; 1-31 print
5108 as themselves, 0 prints as 32. */
5109 {
5110 long imm = (given & 0x07c0) >> 6;
5111 if (imm == 0)
5112 imm = 32;
5113 func (stream, "#%ld", imm);
5114 }
5115 break;
5116
5117 case '0': case '1': case '2': case '3': case '4':
5118 case '5': case '6': case '7': case '8': case '9':
5119 {
5120 int bitstart = *c++ - '0';
5121 int bitend = 0;
5122
5123 while (*c >= '0' && *c <= '9')
5124 bitstart = (bitstart * 10) + *c++ - '0';
5125
5126 switch (*c)
5127 {
5128 case '-':
5129 {
5130 bfd_vma reg;
5131
5132 c++;
5133 while (*c >= '0' && *c <= '9')
5134 bitend = (bitend * 10) + *c++ - '0';
5135 if (!bitend)
5136 abort ();
5137 reg = given >> bitstart;
5138 reg &= (2 << (bitend - bitstart)) - 1;
5139
5140 switch (*c)
5141 {
5142 case 'r':
5143 func (stream, "%s", arm_regnames[reg]);
5144 break;
5145
5146 case 'd':
5147 func (stream, "%ld", (long) reg);
5148 value_in_comment = reg;
5149 break;
5150
5151 case 'H':
5152 func (stream, "%ld", (long) (reg << 1));
5153 value_in_comment = reg << 1;
5154 break;
5155
5156 case 'W':
5157 func (stream, "%ld", (long) (reg << 2));
5158 value_in_comment = reg << 2;
5159 break;
5160
5161 case 'a':
5162 /* PC-relative address -- the bottom two
5163 bits of the address are dropped
5164 before the calculation. */
5165 info->print_address_func
5166 (((pc + 4) & ~3) + (reg << 2), info);
5167 value_in_comment = 0;
5168 break;
5169
5170 case 'x':
5171 func (stream, "0x%04lx", (long) reg);
5172 break;
5173
5174 case 'B':
5175 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
5176 info->print_address_func (reg * 2 + pc + 4, info);
5177 value_in_comment = 0;
5178 break;
5179
5180 case 'c':
5181 func (stream, "%s", arm_conditional [reg]);
5182 break;
5183
5184 default:
5185 abort ();
5186 }
5187 }
5188 break;
5189
5190 case '\'':
5191 c++;
5192 if ((given & (1 << bitstart)) != 0)
5193 func (stream, "%c", *c);
5194 break;
5195
5196 case '?':
5197 ++c;
5198 if ((given & (1 << bitstart)) != 0)
5199 func (stream, "%c", *c++);
5200 else
5201 func (stream, "%c", *++c);
5202 break;
5203
5204 default:
5205 abort ();
5206 }
5207 }
5208 break;
5209
5210 default:
5211 abort ();
5212 }
5213 }
5214
5215 if (value_in_comment > 32 || value_in_comment < -16)
5216 func (stream, "\t; 0x%lx", value_in_comment);
5217 return;
5218 }
5219
5220 /* No match. */
5221 abort ();
5222 }
5223
5224 /* Return the name of an V7M special register. */
5225
5226 static const char *
5227 psr_name (int regno)
5228 {
5229 switch (regno)
5230 {
5231 case 0: return "APSR";
5232 case 1: return "IAPSR";
5233 case 2: return "EAPSR";
5234 case 3: return "PSR";
5235 case 5: return "IPSR";
5236 case 6: return "EPSR";
5237 case 7: return "IEPSR";
5238 case 8: return "MSP";
5239 case 9: return "PSP";
5240 case 16: return "PRIMASK";
5241 case 17: return "BASEPRI";
5242 case 18: return "BASEPRI_MAX";
5243 case 19: return "FAULTMASK";
5244 case 20: return "CONTROL";
5245 default: return "<unknown>";
5246 }
5247 }
5248
5249 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5250
5251 static void
5252 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
5253 {
5254 const struct opcode32 *insn;
5255 void *stream = info->stream;
5256 fprintf_ftype func = info->fprintf_func;
5257
5258 if (print_insn_coprocessor (pc, info, given, TRUE))
5259 return;
5260
5261 if (print_insn_neon (info, given, TRUE))
5262 return;
5263
5264 for (insn = thumb32_opcodes; insn->assembler; insn++)
5265 if ((given & insn->mask) == insn->value)
5266 {
5267 bfd_boolean is_unpredictable = FALSE;
5268 signed long value_in_comment = 0;
5269 const char *c = insn->assembler;
5270
5271 for (; *c; c++)
5272 {
5273 if (*c != '%')
5274 {
5275 func (stream, "%c", *c);
5276 continue;
5277 }
5278
5279 switch (*++c)
5280 {
5281 case '%':
5282 func (stream, "%%");
5283 break;
5284
5285 case 'c':
5286 if (ifthen_state)
5287 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5288 break;
5289
5290 case 'x':
5291 if (ifthen_next_state)
5292 func (stream, "\t; unpredictable branch in IT block\n");
5293 break;
5294
5295 case 'X':
5296 if (ifthen_state)
5297 func (stream, "\t; unpredictable <IT:%s>",
5298 arm_conditional[IFTHEN_COND]);
5299 break;
5300
5301 case 'I':
5302 {
5303 unsigned int imm12 = 0;
5304
5305 imm12 |= (given & 0x000000ffu);
5306 imm12 |= (given & 0x00007000u) >> 4;
5307 imm12 |= (given & 0x04000000u) >> 15;
5308 func (stream, "#%u", imm12);
5309 value_in_comment = imm12;
5310 }
5311 break;
5312
5313 case 'M':
5314 {
5315 unsigned int bits = 0, imm, imm8, mod;
5316
5317 bits |= (given & 0x000000ffu);
5318 bits |= (given & 0x00007000u) >> 4;
5319 bits |= (given & 0x04000000u) >> 15;
5320 imm8 = (bits & 0x0ff);
5321 mod = (bits & 0xf00) >> 8;
5322 switch (mod)
5323 {
5324 case 0: imm = imm8; break;
5325 case 1: imm = ((imm8 << 16) | imm8); break;
5326 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5327 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
5328 default:
5329 mod = (bits & 0xf80) >> 7;
5330 imm8 = (bits & 0x07f) | 0x80;
5331 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5332 }
5333 func (stream, "#%u", imm);
5334 value_in_comment = imm;
5335 }
5336 break;
5337
5338 case 'J':
5339 {
5340 unsigned int imm = 0;
5341
5342 imm |= (given & 0x000000ffu);
5343 imm |= (given & 0x00007000u) >> 4;
5344 imm |= (given & 0x04000000u) >> 15;
5345 imm |= (given & 0x000f0000u) >> 4;
5346 func (stream, "#%u", imm);
5347 value_in_comment = imm;
5348 }
5349 break;
5350
5351 case 'K':
5352 {
5353 unsigned int imm = 0;
5354
5355 imm |= (given & 0x000f0000u) >> 16;
5356 imm |= (given & 0x00000ff0u) >> 0;
5357 imm |= (given & 0x0000000fu) << 12;
5358 func (stream, "#%u", imm);
5359 value_in_comment = imm;
5360 }
5361 break;
5362
5363 case 'H':
5364 {
5365 unsigned int imm = 0;
5366
5367 imm |= (given & 0x000f0000u) >> 4;
5368 imm |= (given & 0x00000fffu) >> 0;
5369 func (stream, "#%u", imm);
5370 value_in_comment = imm;
5371 }
5372 break;
5373
5374 case 'V':
5375 {
5376 unsigned int imm = 0;
5377
5378 imm |= (given & 0x00000fffu);
5379 imm |= (given & 0x000f0000u) >> 4;
5380 func (stream, "#%u", imm);
5381 value_in_comment = imm;
5382 }
5383 break;
5384
5385 case 'S':
5386 {
5387 unsigned int reg = (given & 0x0000000fu);
5388 unsigned int stp = (given & 0x00000030u) >> 4;
5389 unsigned int imm = 0;
5390 imm |= (given & 0x000000c0u) >> 6;
5391 imm |= (given & 0x00007000u) >> 10;
5392
5393 func (stream, "%s", arm_regnames[reg]);
5394 switch (stp)
5395 {
5396 case 0:
5397 if (imm > 0)
5398 func (stream, ", lsl #%u", imm);
5399 break;
5400
5401 case 1:
5402 if (imm == 0)
5403 imm = 32;
5404 func (stream, ", lsr #%u", imm);
5405 break;
5406
5407 case 2:
5408 if (imm == 0)
5409 imm = 32;
5410 func (stream, ", asr #%u", imm);
5411 break;
5412
5413 case 3:
5414 if (imm == 0)
5415 func (stream, ", rrx");
5416 else
5417 func (stream, ", ror #%u", imm);
5418 }
5419 }
5420 break;
5421
5422 case 'a':
5423 {
5424 unsigned int Rn = (given & 0x000f0000) >> 16;
5425 unsigned int U = ! NEGATIVE_BIT_SET;
5426 unsigned int op = (given & 0x00000f00) >> 8;
5427 unsigned int i12 = (given & 0x00000fff);
5428 unsigned int i8 = (given & 0x000000ff);
5429 bfd_boolean writeback = FALSE, postind = FALSE;
5430 bfd_vma offset = 0;
5431
5432 func (stream, "[%s", arm_regnames[Rn]);
5433 if (U) /* 12-bit positive immediate offset. */
5434 {
5435 offset = i12;
5436 if (Rn != 15)
5437 value_in_comment = offset;
5438 }
5439 else if (Rn == 15) /* 12-bit negative immediate offset. */
5440 offset = - (int) i12;
5441 else if (op == 0x0) /* Shifted register offset. */
5442 {
5443 unsigned int Rm = (i8 & 0x0f);
5444 unsigned int sh = (i8 & 0x30) >> 4;
5445
5446 func (stream, ", %s", arm_regnames[Rm]);
5447 if (sh)
5448 func (stream, ", lsl #%u", sh);
5449 func (stream, "]");
5450 break;
5451 }
5452 else switch (op)
5453 {
5454 case 0xE: /* 8-bit positive immediate offset. */
5455 offset = i8;
5456 break;
5457
5458 case 0xC: /* 8-bit negative immediate offset. */
5459 offset = -i8;
5460 break;
5461
5462 case 0xF: /* 8-bit + preindex with wb. */
5463 offset = i8;
5464 writeback = TRUE;
5465 break;
5466
5467 case 0xD: /* 8-bit - preindex with wb. */
5468 offset = -i8;
5469 writeback = TRUE;
5470 break;
5471
5472 case 0xB: /* 8-bit + postindex. */
5473 offset = i8;
5474 postind = TRUE;
5475 break;
5476
5477 case 0x9: /* 8-bit - postindex. */
5478 offset = -i8;
5479 postind = TRUE;
5480 break;
5481
5482 default:
5483 func (stream, ", <undefined>]");
5484 goto skip;
5485 }
5486
5487 if (postind)
5488 func (stream, "], #%d", (int) offset);
5489 else
5490 {
5491 if (offset)
5492 func (stream, ", #%d", (int) offset);
5493 func (stream, writeback ? "]!" : "]");
5494 }
5495
5496 if (Rn == 15)
5497 {
5498 func (stream, "\t; ");
5499 info->print_address_func (((pc + 4) & ~3) + offset, info);
5500 }
5501 }
5502 skip:
5503 break;
5504
5505 case 'A':
5506 {
5507 unsigned int U = ! NEGATIVE_BIT_SET;
5508 unsigned int W = WRITEBACK_BIT_SET;
5509 unsigned int Rn = (given & 0x000f0000) >> 16;
5510 unsigned int off = (given & 0x000000ff);
5511
5512 func (stream, "[%s", arm_regnames[Rn]);
5513
5514 if (PRE_BIT_SET)
5515 {
5516 if (off || !U)
5517 {
5518 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5519 value_in_comment = off * 4 * U ? 1 : -1;
5520 }
5521 func (stream, "]");
5522 if (W)
5523 func (stream, "!");
5524 }
5525 else
5526 {
5527 func (stream, "], ");
5528 if (W)
5529 {
5530 func (stream, "#%c%u", U ? '+' : '-', off * 4);
5531 value_in_comment = off * 4 * U ? 1 : -1;
5532 }
5533 else
5534 {
5535 func (stream, "{%u}", off);
5536 value_in_comment = off;
5537 }
5538 }
5539 }
5540 break;
5541
5542 case 'w':
5543 {
5544 unsigned int Sbit = (given & 0x01000000) >> 24;
5545 unsigned int type = (given & 0x00600000) >> 21;
5546
5547 switch (type)
5548 {
5549 case 0: func (stream, Sbit ? "sb" : "b"); break;
5550 case 1: func (stream, Sbit ? "sh" : "h"); break;
5551 case 2:
5552 if (Sbit)
5553 func (stream, "??");
5554 break;
5555 case 3:
5556 func (stream, "??");
5557 break;
5558 }
5559 }
5560 break;
5561
5562 case 'm':
5563 {
5564 int started = 0;
5565 int reg;
5566
5567 func (stream, "{");
5568 for (reg = 0; reg < 16; reg++)
5569 if ((given & (1 << reg)) != 0)
5570 {
5571 if (started)
5572 func (stream, ", ");
5573 started = 1;
5574 func (stream, "%s", arm_regnames[reg]);
5575 }
5576 func (stream, "}");
5577 }
5578 break;
5579
5580 case 'E':
5581 {
5582 unsigned int msb = (given & 0x0000001f);
5583 unsigned int lsb = 0;
5584
5585 lsb |= (given & 0x000000c0u) >> 6;
5586 lsb |= (given & 0x00007000u) >> 10;
5587 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5588 }
5589 break;
5590
5591 case 'F':
5592 {
5593 unsigned int width = (given & 0x0000001f) + 1;
5594 unsigned int lsb = 0;
5595
5596 lsb |= (given & 0x000000c0u) >> 6;
5597 lsb |= (given & 0x00007000u) >> 10;
5598 func (stream, "#%u, #%u", lsb, width);
5599 }
5600 break;
5601
5602 case 'b':
5603 {
5604 unsigned int S = (given & 0x04000000u) >> 26;
5605 unsigned int J1 = (given & 0x00002000u) >> 13;
5606 unsigned int J2 = (given & 0x00000800u) >> 11;
5607 bfd_vma offset = 0;
5608
5609 offset |= !S << 20;
5610 offset |= J2 << 19;
5611 offset |= J1 << 18;
5612 offset |= (given & 0x003f0000) >> 4;
5613 offset |= (given & 0x000007ff) << 1;
5614 offset -= (1 << 20);
5615
5616 info->print_address_func (pc + 4 + offset, info);
5617 }
5618 break;
5619
5620 case 'B':
5621 {
5622 unsigned int S = (given & 0x04000000u) >> 26;
5623 unsigned int I1 = (given & 0x00002000u) >> 13;
5624 unsigned int I2 = (given & 0x00000800u) >> 11;
5625 bfd_vma offset = 0;
5626
5627 offset |= !S << 24;
5628 offset |= !(I1 ^ S) << 23;
5629 offset |= !(I2 ^ S) << 22;
5630 offset |= (given & 0x03ff0000u) >> 4;
5631 offset |= (given & 0x000007ffu) << 1;
5632 offset -= (1 << 24);
5633 offset += pc + 4;
5634
5635 /* BLX target addresses are always word aligned. */
5636 if ((given & 0x00001000u) == 0)
5637 offset &= ~2u;
5638
5639 info->print_address_func (offset, info);
5640 }
5641 break;
5642
5643 case 's':
5644 {
5645 unsigned int shift = 0;
5646
5647 shift |= (given & 0x000000c0u) >> 6;
5648 shift |= (given & 0x00007000u) >> 10;
5649 if (WRITEBACK_BIT_SET)
5650 func (stream, ", asr #%u", shift);
5651 else if (shift)
5652 func (stream, ", lsl #%u", shift);
5653 /* else print nothing - lsl #0 */
5654 }
5655 break;
5656
5657 case 'R':
5658 {
5659 unsigned int rot = (given & 0x00000030) >> 4;
5660
5661 if (rot)
5662 func (stream, ", ror #%u", rot * 8);
5663 }
5664 break;
5665
5666 case 'U':
5667 if ((given & 0xf0) == 0x60)
5668 {
5669 switch (given & 0xf)
5670 {
5671 case 0xf: func (stream, "sy"); break;
5672 default:
5673 func (stream, "#%d", (int) given & 0xf);
5674 break;
5675 }
5676 }
5677 else
5678 {
5679 const char * opt = data_barrier_option (given & 0xf);
5680 if (opt != NULL)
5681 func (stream, "%s", opt);
5682 else
5683 func (stream, "#%d", (int) given & 0xf);
5684 }
5685 break;
5686
5687 case 'C':
5688 if ((given & 0xff) == 0)
5689 {
5690 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5691 if (given & 0x800)
5692 func (stream, "f");
5693 if (given & 0x400)
5694 func (stream, "s");
5695 if (given & 0x200)
5696 func (stream, "x");
5697 if (given & 0x100)
5698 func (stream, "c");
5699 }
5700 else if ((given & 0x20) == 0x20)
5701 {
5702 char const* name;
5703 unsigned sysm = (given & 0xf00) >> 8;
5704
5705 sysm |= (given & 0x30);
5706 sysm |= (given & 0x00100000) >> 14;
5707 name = banked_regname (sysm);
5708
5709 if (name != NULL)
5710 func (stream, "%s", name);
5711 else
5712 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5713 }
5714 else
5715 {
5716 func (stream, "%s", psr_name (given & 0xff));
5717 }
5718 break;
5719
5720 case 'D':
5721 if (((given & 0xff) == 0)
5722 || ((given & 0x20) == 0x20))
5723 {
5724 char const* name;
5725 unsigned sm = (given & 0xf0000) >> 16;
5726
5727 sm |= (given & 0x30);
5728 sm |= (given & 0x00100000) >> 14;
5729 name = banked_regname (sm);
5730
5731 if (name != NULL)
5732 func (stream, "%s", name);
5733 else
5734 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
5735 }
5736 else
5737 func (stream, "%s", psr_name (given & 0xff));
5738 break;
5739
5740 case '0': case '1': case '2': case '3': case '4':
5741 case '5': case '6': case '7': case '8': case '9':
5742 {
5743 int width;
5744 unsigned long val;
5745
5746 c = arm_decode_bitfield (c, given, &val, &width);
5747
5748 switch (*c)
5749 {
5750 case 'd':
5751 func (stream, "%lu", val);
5752 value_in_comment = val;
5753 break;
5754
5755 case 'D':
5756 func (stream, "%lu", val + 1);
5757 value_in_comment = val + 1;
5758 break;
5759
5760 case 'W':
5761 func (stream, "%lu", val * 4);
5762 value_in_comment = val * 4;
5763 break;
5764
5765 case 'S':
5766 if (val == 13)
5767 is_unpredictable = TRUE;
5768 /* Fall through. */
5769 case 'R':
5770 if (val == 15)
5771 is_unpredictable = TRUE;
5772 /* Fall through. */
5773 case 'r':
5774 func (stream, "%s", arm_regnames[val]);
5775 break;
5776
5777 case 'c':
5778 func (stream, "%s", arm_conditional[val]);
5779 break;
5780
5781 case '\'':
5782 c++;
5783 if (val == ((1ul << width) - 1))
5784 func (stream, "%c", *c);
5785 break;
5786
5787 case '`':
5788 c++;
5789 if (val == 0)
5790 func (stream, "%c", *c);
5791 break;
5792
5793 case '?':
5794 func (stream, "%c", c[(1 << width) - (int) val]);
5795 c += 1 << width;
5796 break;
5797
5798 case 'x':
5799 func (stream, "0x%lx", val & 0xffffffffUL);
5800 break;
5801
5802 default:
5803 abort ();
5804 }
5805 }
5806 break;
5807
5808 case 'L':
5809 /* PR binutils/12534
5810 If we have a PC relative offset in an LDRD or STRD
5811 instructions then display the decoded address. */
5812 if (((given >> 16) & 0xf) == 0xf)
5813 {
5814 bfd_vma offset = (given & 0xff) * 4;
5815
5816 if ((given & (1 << 23)) == 0)
5817 offset = - offset;
5818 func (stream, "\t; ");
5819 info->print_address_func ((pc & ~3) + 4 + offset, info);
5820 }
5821 break;
5822
5823 default:
5824 abort ();
5825 }
5826 }
5827
5828 if (value_in_comment > 32 || value_in_comment < -16)
5829 func (stream, "\t; 0x%lx", value_in_comment);
5830
5831 if (is_unpredictable)
5832 func (stream, UNPREDICTABLE_INSTRUCTION);
5833
5834 return;
5835 }
5836
5837 /* No match. */
5838 abort ();
5839 }
5840
5841 /* Print data bytes on INFO->STREAM. */
5842
5843 static void
5844 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
5845 struct disassemble_info *info,
5846 long given)
5847 {
5848 switch (info->bytes_per_chunk)
5849 {
5850 case 1:
5851 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
5852 break;
5853 case 2:
5854 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
5855 break;
5856 case 4:
5857 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
5858 break;
5859 default:
5860 abort ();
5861 }
5862 }
5863
5864 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
5865 being displayed in symbol relative addresses.
5866
5867 Also disallow private symbol, with __tagsym$$ prefix,
5868 from ARM RVCT toolchain being displayed. */
5869
5870 bfd_boolean
5871 arm_symbol_is_valid (asymbol * sym,
5872 struct disassemble_info * info ATTRIBUTE_UNUSED)
5873 {
5874 const char * name;
5875
5876 if (sym == NULL)
5877 return FALSE;
5878
5879 name = bfd_asymbol_name (sym);
5880
5881 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
5882 }
5883
5884 /* Parse an individual disassembler option. */
5885
5886 void
5887 parse_arm_disassembler_option (char *option)
5888 {
5889 if (option == NULL)
5890 return;
5891
5892 if (CONST_STRNEQ (option, "reg-names-"))
5893 {
5894 int i;
5895
5896 option += 10;
5897
5898 for (i = NUM_ARM_REGNAMES; i--;)
5899 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
5900 {
5901 regname_selected = i;
5902 break;
5903 }
5904
5905 if (i < 0)
5906 /* XXX - should break 'option' at following delimiter. */
5907 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
5908 }
5909 else if (CONST_STRNEQ (option, "force-thumb"))
5910 force_thumb = 1;
5911 else if (CONST_STRNEQ (option, "no-force-thumb"))
5912 force_thumb = 0;
5913 else
5914 /* XXX - should break 'option' at following delimiter. */
5915 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
5916
5917 return;
5918 }
5919
5920 /* Parse the string of disassembler options, spliting it at whitespaces
5921 or commas. (Whitespace separators supported for backwards compatibility). */
5922
5923 static void
5924 parse_disassembler_options (char *options)
5925 {
5926 if (options == NULL)
5927 return;
5928
5929 while (*options)
5930 {
5931 parse_arm_disassembler_option (options);
5932
5933 /* Skip forward to next seperator. */
5934 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
5935 ++ options;
5936 /* Skip forward past seperators. */
5937 while (ISSPACE (*options) || (*options == ','))
5938 ++ options;
5939 }
5940 }
5941
5942 /* Search back through the insn stream to determine if this instruction is
5943 conditionally executed. */
5944
5945 static void
5946 find_ifthen_state (bfd_vma pc,
5947 struct disassemble_info *info,
5948 bfd_boolean little)
5949 {
5950 unsigned char b[2];
5951 unsigned int insn;
5952 int status;
5953 /* COUNT is twice the number of instructions seen. It will be odd if we
5954 just crossed an instruction boundary. */
5955 int count;
5956 int it_count;
5957 unsigned int seen_it;
5958 bfd_vma addr;
5959
5960 ifthen_address = pc;
5961 ifthen_state = 0;
5962
5963 addr = pc;
5964 count = 1;
5965 it_count = 0;
5966 seen_it = 0;
5967 /* Scan backwards looking for IT instructions, keeping track of where
5968 instruction boundaries are. We don't know if something is actually an
5969 IT instruction until we find a definite instruction boundary. */
5970 for (;;)
5971 {
5972 if (addr == 0 || info->symbol_at_address_func (addr, info))
5973 {
5974 /* A symbol must be on an instruction boundary, and will not
5975 be within an IT block. */
5976 if (seen_it && (count & 1))
5977 break;
5978
5979 return;
5980 }
5981 addr -= 2;
5982 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
5983 if (status)
5984 return;
5985
5986 if (little)
5987 insn = (b[0]) | (b[1] << 8);
5988 else
5989 insn = (b[1]) | (b[0] << 8);
5990 if (seen_it)
5991 {
5992 if ((insn & 0xf800) < 0xe800)
5993 {
5994 /* Addr + 2 is an instruction boundary. See if this matches
5995 the expected boundary based on the position of the last
5996 IT candidate. */
5997 if (count & 1)
5998 break;
5999 seen_it = 0;
6000 }
6001 }
6002 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6003 {
6004 /* This could be an IT instruction. */
6005 seen_it = insn;
6006 it_count = count >> 1;
6007 }
6008 if ((insn & 0xf800) >= 0xe800)
6009 count++;
6010 else
6011 count = (count + 2) | 1;
6012 /* IT blocks contain at most 4 instructions. */
6013 if (count >= 8 && !seen_it)
6014 return;
6015 }
6016 /* We found an IT instruction. */
6017 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6018 if ((ifthen_state & 0xf) == 0)
6019 ifthen_state = 0;
6020 }
6021
6022 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6023 mapping symbol. */
6024
6025 static int
6026 is_mapping_symbol (struct disassemble_info *info, int n,
6027 enum map_type *map_type)
6028 {
6029 const char *name;
6030
6031 name = bfd_asymbol_name (info->symtab[n]);
6032 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6033 && (name[2] == 0 || name[2] == '.'))
6034 {
6035 *map_type = ((name[1] == 'a') ? MAP_ARM
6036 : (name[1] == 't') ? MAP_THUMB
6037 : MAP_DATA);
6038 return TRUE;
6039 }
6040
6041 return FALSE;
6042 }
6043
6044 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6045 Returns nonzero if *MAP_TYPE was set. */
6046
6047 static int
6048 get_map_sym_type (struct disassemble_info *info,
6049 int n,
6050 enum map_type *map_type)
6051 {
6052 /* If the symbol is in a different section, ignore it. */
6053 if (info->section != NULL && info->section != info->symtab[n]->section)
6054 return FALSE;
6055
6056 return is_mapping_symbol (info, n, map_type);
6057 }
6058
6059 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6060 Returns nonzero if *MAP_TYPE was set. */
6061
6062 static int
6063 get_sym_code_type (struct disassemble_info *info,
6064 int n,
6065 enum map_type *map_type)
6066 {
6067 elf_symbol_type *es;
6068 unsigned int type;
6069
6070 /* If the symbol is in a different section, ignore it. */
6071 if (info->section != NULL && info->section != info->symtab[n]->section)
6072 return FALSE;
6073
6074 es = *(elf_symbol_type **)(info->symtab + n);
6075 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6076
6077 /* If the symbol has function type then use that. */
6078 if (type == STT_FUNC || type == STT_GNU_IFUNC)
6079 {
6080 if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
6081 *map_type = MAP_THUMB;
6082 else
6083 *map_type = MAP_ARM;
6084 return TRUE;
6085 }
6086
6087 return FALSE;
6088 }
6089
6090 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6091 of the supplied arm_feature_set structure with bitmasks indicating
6092 the support base architectures and coprocessor extensions.
6093
6094 FIXME: This could more efficiently implemented as a constant array,
6095 although it would also be less robust. */
6096
6097 static void
6098 select_arm_features (unsigned long mach,
6099 arm_feature_set * features)
6100 {
6101 #undef ARM_SET_FEATURES
6102 #define ARM_SET_FEATURES(FSET) \
6103 { \
6104 const arm_feature_set fset = FSET; \
6105 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6106 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6107 }
6108
6109 switch (mach)
6110 {
6111 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6112 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6113 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6114 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6115 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6116 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6117 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6118 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6119 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6120 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6121 case bfd_mach_arm_ep9312:
6122 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6123 ARM_CEXT_MAVERICK | FPU_MAVERICK));
6124 break;
6125 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6126 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6127 /* If the machine type is unknown allow all
6128 architecture types and all extensions. */
6129 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
6130 default:
6131 abort ();
6132 }
6133
6134 #undef ARM_SET_FEATURES
6135 }
6136
6137
6138 /* NOTE: There are no checks in these routines that
6139 the relevant number of data bytes exist. */
6140
6141 static int
6142 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
6143 {
6144 unsigned char b[4];
6145 long given;
6146 int status;
6147 int is_thumb = FALSE;
6148 int is_data = FALSE;
6149 int little_code;
6150 unsigned int size = 4;
6151 void (*printer) (bfd_vma, struct disassemble_info *, long);
6152 bfd_boolean found = FALSE;
6153 struct arm_private_data *private_data;
6154
6155 if (info->disassembler_options)
6156 {
6157 parse_disassembler_options (info->disassembler_options);
6158
6159 /* To avoid repeated parsing of these options, we remove them here. */
6160 info->disassembler_options = NULL;
6161 }
6162
6163 /* PR 10288: Control which instructions will be disassembled. */
6164 if (info->private_data == NULL)
6165 {
6166 static struct arm_private_data private;
6167
6168 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6169 /* If the user did not use the -m command line switch then default to
6170 disassembling all types of ARM instruction.
6171
6172 The info->mach value has to be ignored as this will be based on
6173 the default archictecture for the target and/or hints in the notes
6174 section, but it will never be greater than the current largest arm
6175 machine value (iWMMXt2), which is only equivalent to the V5TE
6176 architecture. ARM architectures have advanced beyond the machine
6177 value encoding, and these newer architectures would be ignored if
6178 the machine value was used.
6179
6180 Ie the -m switch is used to restrict which instructions will be
6181 disassembled. If it is necessary to use the -m switch to tell
6182 objdump that an ARM binary is being disassembled, eg because the
6183 input is a raw binary file, but it is also desired to disassemble
6184 all ARM instructions then use "-marm". This will select the
6185 "unknown" arm architecture which is compatible with any ARM
6186 instruction. */
6187 info->mach = bfd_mach_arm_unknown;
6188
6189 /* Compute the architecture bitmask from the machine number.
6190 Note: This assumes that the machine number will not change
6191 during disassembly.... */
6192 select_arm_features (info->mach, & private.features);
6193
6194 private.has_mapping_symbols = -1;
6195 private.last_mapping_sym = -1;
6196 private.last_mapping_addr = 0;
6197
6198 info->private_data = & private;
6199 }
6200
6201 private_data = info->private_data;
6202
6203 /* Decide if our code is going to be little-endian, despite what the
6204 function argument might say. */
6205 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6206
6207 /* For ELF, consult the symbol table to determine what kind of code
6208 or data we have. */
6209 if (info->symtab_size != 0
6210 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6211 {
6212 bfd_vma addr;
6213 int n, start;
6214 int last_sym = -1;
6215 enum map_type type = MAP_ARM;
6216
6217 /* Start scanning at the start of the function, or wherever
6218 we finished last time. */
6219 /* PR 14006. When the address is 0 we are either at the start of the
6220 very first function, or else the first function in a new, unlinked
6221 executable section (eg because uf -ffunction-sections). Either way
6222 start scanning from the beginning of the symbol table, not where we
6223 left off last time. */
6224 if (pc == 0)
6225 start = 0;
6226 else
6227 {
6228 start = info->symtab_pos + 1;
6229 if (start < private_data->last_mapping_sym)
6230 start = private_data->last_mapping_sym;
6231 }
6232 found = FALSE;
6233
6234 /* First, look for mapping symbols. */
6235 if (private_data->has_mapping_symbols != 0)
6236 {
6237 /* Scan up to the location being disassembled. */
6238 for (n = start; n < info->symtab_size; n++)
6239 {
6240 addr = bfd_asymbol_value (info->symtab[n]);
6241 if (addr > pc)
6242 break;
6243 if (get_map_sym_type (info, n, &type))
6244 {
6245 last_sym = n;
6246 found = TRUE;
6247 }
6248 }
6249
6250 if (!found)
6251 {
6252 /* No mapping symbol found at this address. Look backwards
6253 for a preceding one. */
6254 for (n = start - 1; n >= 0; n--)
6255 {
6256 if (get_map_sym_type (info, n, &type))
6257 {
6258 last_sym = n;
6259 found = TRUE;
6260 break;
6261 }
6262 }
6263 }
6264
6265 if (found)
6266 private_data->has_mapping_symbols = 1;
6267
6268 /* No mapping symbols were found. A leading $d may be
6269 omitted for sections which start with data; but for
6270 compatibility with legacy and stripped binaries, only
6271 assume the leading $d if there is at least one mapping
6272 symbol in the file. */
6273 if (!found && private_data->has_mapping_symbols == -1)
6274 {
6275 /* Look for mapping symbols, in any section. */
6276 for (n = 0; n < info->symtab_size; n++)
6277 if (is_mapping_symbol (info, n, &type))
6278 {
6279 private_data->has_mapping_symbols = 1;
6280 break;
6281 }
6282 if (private_data->has_mapping_symbols == -1)
6283 private_data->has_mapping_symbols = 0;
6284 }
6285
6286 if (!found && private_data->has_mapping_symbols == 1)
6287 {
6288 type = MAP_DATA;
6289 found = TRUE;
6290 }
6291 }
6292
6293 /* Next search for function symbols to separate ARM from Thumb
6294 in binaries without mapping symbols. */
6295 if (!found)
6296 {
6297 /* Scan up to the location being disassembled. */
6298 for (n = start; n < info->symtab_size; n++)
6299 {
6300 addr = bfd_asymbol_value (info->symtab[n]);
6301 if (addr > pc)
6302 break;
6303 if (get_sym_code_type (info, n, &type))
6304 {
6305 last_sym = n;
6306 found = TRUE;
6307 }
6308 }
6309
6310 if (!found)
6311 {
6312 /* No mapping symbol found at this address. Look backwards
6313 for a preceding one. */
6314 for (n = start - 1; n >= 0; n--)
6315 {
6316 if (get_sym_code_type (info, n, &type))
6317 {
6318 last_sym = n;
6319 found = TRUE;
6320 break;
6321 }
6322 }
6323 }
6324 }
6325
6326 private_data->last_mapping_sym = last_sym;
6327 private_data->last_type = type;
6328 is_thumb = (private_data->last_type == MAP_THUMB);
6329 is_data = (private_data->last_type == MAP_DATA);
6330
6331 /* Look a little bit ahead to see if we should print out
6332 two or four bytes of data. If there's a symbol,
6333 mapping or otherwise, after two bytes then don't
6334 print more. */
6335 if (is_data)
6336 {
6337 size = 4 - (pc & 3);
6338 for (n = last_sym + 1; n < info->symtab_size; n++)
6339 {
6340 addr = bfd_asymbol_value (info->symtab[n]);
6341 if (addr > pc
6342 && (info->section == NULL
6343 || info->section == info->symtab[n]->section))
6344 {
6345 if (addr - pc < size)
6346 size = addr - pc;
6347 break;
6348 }
6349 }
6350 /* If the next symbol is after three bytes, we need to
6351 print only part of the data, so that we can use either
6352 .byte or .short. */
6353 if (size == 3)
6354 size = (pc & 1) ? 1 : 2;
6355 }
6356 }
6357
6358 if (info->symbols != NULL)
6359 {
6360 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6361 {
6362 coff_symbol_type * cs;
6363
6364 cs = coffsymbol (*info->symbols);
6365 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6366 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6367 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6368 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6369 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6370 }
6371 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6372 && !found)
6373 {
6374 /* If no mapping symbol has been found then fall back to the type
6375 of the function symbol. */
6376 elf_symbol_type * es;
6377 unsigned int type;
6378
6379 es = *(elf_symbol_type **)(info->symbols);
6380 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6381
6382 is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
6383 == ST_BRANCH_TO_THUMB)
6384 || type == STT_ARM_16BIT);
6385 }
6386 else if (bfd_asymbol_flavour (*info->symbols)
6387 == bfd_target_mach_o_flavour)
6388 {
6389 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6390
6391 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6392 }
6393 }
6394
6395 if (force_thumb)
6396 is_thumb = TRUE;
6397
6398 if (is_data)
6399 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6400 else
6401 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6402
6403 info->bytes_per_line = 4;
6404
6405 /* PR 10263: Disassemble data if requested to do so by the user. */
6406 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
6407 {
6408 int i;
6409
6410 /* Size was already set above. */
6411 info->bytes_per_chunk = size;
6412 printer = print_insn_data;
6413
6414 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
6415 given = 0;
6416 if (little)
6417 for (i = size - 1; i >= 0; i--)
6418 given = b[i] | (given << 8);
6419 else
6420 for (i = 0; i < (int) size; i++)
6421 given = b[i] | (given << 8);
6422 }
6423 else if (!is_thumb)
6424 {
6425 /* In ARM mode endianness is a straightforward issue: the instruction
6426 is four bytes long and is either ordered 0123 or 3210. */
6427 printer = print_insn_arm;
6428 info->bytes_per_chunk = 4;
6429 size = 4;
6430
6431 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
6432 if (little_code)
6433 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6434 else
6435 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
6436 }
6437 else
6438 {
6439 /* In Thumb mode we have the additional wrinkle of two
6440 instruction lengths. Fortunately, the bits that determine
6441 the length of the current instruction are always to be found
6442 in the first two bytes. */
6443 printer = print_insn_thumb16;
6444 info->bytes_per_chunk = 2;
6445 size = 2;
6446
6447 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
6448 if (little_code)
6449 given = (b[0]) | (b[1] << 8);
6450 else
6451 given = (b[1]) | (b[0] << 8);
6452
6453 if (!status)
6454 {
6455 /* These bit patterns signal a four-byte Thumb
6456 instruction. */
6457 if ((given & 0xF800) == 0xF800
6458 || (given & 0xF800) == 0xF000
6459 || (given & 0xF800) == 0xE800)
6460 {
6461 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
6462 if (little_code)
6463 given = (b[0]) | (b[1] << 8) | (given << 16);
6464 else
6465 given = (b[1]) | (b[0] << 8) | (given << 16);
6466
6467 printer = print_insn_thumb32;
6468 size = 4;
6469 }
6470 }
6471
6472 if (ifthen_address != pc)
6473 find_ifthen_state (pc, info, little_code);
6474
6475 if (ifthen_state)
6476 {
6477 if ((ifthen_state & 0xf) == 0x8)
6478 ifthen_next_state = 0;
6479 else
6480 ifthen_next_state = (ifthen_state & 0xe0)
6481 | ((ifthen_state & 0xf) << 1);
6482 }
6483 }
6484
6485 if (status)
6486 {
6487 info->memory_error_func (status, pc, info);
6488 return -1;
6489 }
6490 if (info->flags & INSN_HAS_RELOC)
6491 /* If the instruction has a reloc associated with it, then
6492 the offset field in the instruction will actually be the
6493 addend for the reloc. (We are using REL type relocs).
6494 In such cases, we can ignore the pc when computing
6495 addresses, since the addend is not currently pc-relative. */
6496 pc = 0;
6497
6498 printer (pc, info, given);
6499
6500 if (is_thumb)
6501 {
6502 ifthen_state = ifthen_next_state;
6503 ifthen_address += size;
6504 }
6505 return size;
6506 }
6507
6508 int
6509 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
6510 {
6511 /* Detect BE8-ness and record it in the disassembler info. */
6512 if (info->flavour == bfd_target_elf_flavour
6513 && info->section != NULL
6514 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6515 info->endian_code = BFD_ENDIAN_LITTLE;
6516
6517 return print_insn (pc, info, FALSE);
6518 }
6519
6520 int
6521 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
6522 {
6523 return print_insn (pc, info, TRUE);
6524 }
6525
6526 void
6527 print_arm_disassembler_options (FILE *stream)
6528 {
6529 int i;
6530
6531 fprintf (stream, _("\n\
6532 The following ARM specific disassembler options are supported for use with\n\
6533 the -M switch:\n"));
6534
6535 for (i = NUM_ARM_REGNAMES; i--;)
6536 fprintf (stream, " reg-names-%s %*c%s\n",
6537 regnames[i].name,
6538 (int)(14 - strlen (regnames[i].name)), ' ',
6539 regnames[i].description);
6540
6541 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
6542 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
6543 }
GDB Binutils - Deliverables
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