opcodes/fr30-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS USED TO GENERATE fr30-opc.c.
   5
   6 Copyright (C) 1998 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software Foundation, Inc.,
  22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "fr30-opc.h"
  31 #include "opintl.h"
  32
  33 /* The hash functions are recorded here to help keep assembler code out of
  34    the disassembler and vice versa.  */
  35
  36 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
  37 static unsigned int asm_hash_insn PARAMS ((const char *));
  38 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
  39 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
  40
  41 /* Look up instruction INSN_VALUE and extract its fields.
  42    INSN, if non-null, is the insn table entry.
  43    Otherwise INSN_VALUE is examined to compute it.
  44    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
  45    0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
  46    If INSN != NULL, LENGTH must be valid.
  47    ALIAS_P is non-zero if alias insns are to be included in the search.
  48
  49    The result is a pointer to the insn table entry, or NULL if the instruction
  50    wasn't recognized.  */
  51
  52 const CGEN_INSN *
  53 fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
  54      CGEN_OPCODE_DESC od;
  55      const CGEN_INSN *insn;
  56      CGEN_INSN_BYTES insn_value;
  57      int length;
  58      CGEN_FIELDS *fields;
  59      int alias_p;
  60 {
  61   unsigned char buf[CGEN_MAX_INSN_SIZE];
  62   unsigned char *bufp;
  63   CGEN_INSN_INT base_insn;
  64 #if CGEN_INT_INSN_P
  65   CGEN_EXTRACT_INFO *info = NULL;
  66 #else
  67   CGEN_EXTRACT_INFO ex_info;
  68   CGEN_EXTRACT_INFO *info = &ex_info;
  69 #endif
  70
  71 #if CGEN_INT_INSN_P
  72   cgen_put_insn_value (od, buf, length, insn_value);
  73   bufp = buf;
  74   base_insn = insn_value; /*???*/
  75 #else
  76   ex_info.dis_info = NULL;
  77   ex_info.insn_bytes = insn_value;
  78   ex_info.valid = -1;
  79   base_insn = cgen_get_insn_value (od, buf, length);
  80   bufp = insn_value;
  81 #endif
  82
  83   if (!insn)
  84     {
  85       const CGEN_INSN_LIST *insn_list;
  86
  87       /* The instructions are stored in hash lists.
  88          Pick the first one and keep trying until we find the right one.  */
  89
  90       insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
  91       while (insn_list != NULL)
  92         {
  93           insn = insn_list->insn;
  94
  95           if (alias_p
  96               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
  97             {
  98               /* Basic bit mask must be correct.  */
  99               /* ??? May wish to allow target to defer this check until the
 100                  extract handler.  */
 101               if ((base_insn & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
 102                 {
 103                   /* ??? 0 is passed for `pc' */
 104                   int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
 105                                                            base_insn, fields,
 106                                                            (bfd_vma) 0);
 107                   if (elength > 0)
 108                     {
 109                       /* sanity check */
 110                       if (length != 0 && length != elength)
 111                         abort ();
 112                       return insn;
 113                     }
 114                 }
 115             }
 116
 117           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 118         }
 119     }
 120   else
 121     {
 122       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 123       if (! alias_p
 124           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 125         abort ();
 126       /* Sanity check: length must be correct.  */
 127       if (length != CGEN_INSN_BITSIZE (insn))
 128         abort ();
 129
 130       /* ??? 0 is passed for `pc' */
 131       length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
 132                                           (bfd_vma) 0);
 133       /* Sanity check: must succeed.
 134          Could relax this later if it ever proves useful.  */
 135       if (length == 0)
 136         abort ();
 137       return insn;
 138     }
 139
 140   return NULL;
 141 }
 142
 143 /* Fill in the operand instances used by INSN whose operands are FIELDS.
 144    INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
 145    in.  */
 146
 147 void
 148 fr30_cgen_get_insn_operands (od, insn, fields, indices)
 149      CGEN_OPCODE_DESC od;
 150      const CGEN_INSN * insn;
 151      const CGEN_FIELDS * fields;
 152      int *indices;
 153 {
 154   const CGEN_OPERAND_INSTANCE *opinst;
 155   int i;
 156
 157   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 158        opinst != NULL
 159          && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 160        ++i, ++opinst)
 161     {
 162       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 163       if (op == NULL)
 164         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 165       else
 166         indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
 167                                                   fields);
 168     }
 169 }
 170
 171 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
 172    isn't known.
 173    The INSN, INSN_VALUE, and LENGTH arguments are passed to
 174    fr30_cgen_lookup_insn unchanged.
 175
 176    The result is the insn table entry or NULL if the instruction wasn't
 177    recognized.  */
 178
 179 const CGEN_INSN *
 180 fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
 181      CGEN_OPCODE_DESC od;
 182      const CGEN_INSN *insn;
 183      CGEN_INSN_BYTES insn_value;
 184      int length;
 185      int *indices;
 186 {
 187   CGEN_FIELDS fields;
 188
 189   /* Pass non-zero for ALIAS_P only if INSN != NULL.
 190      If INSN == NULL, we want a real insn.  */
 191   insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
 192                                   insn != NULL);
 193   if (! insn)
 194     return NULL;
 195
 196   fr30_cgen_get_insn_operands (od, insn, &fields, indices);
 197   return insn;
 198 }
 199 /* Attributes.  */
 200
 201 static const CGEN_ATTR_ENTRY MACH_attr[] =
 202 {
 203   { "base", MACH_BASE },
 204   { "fr30", MACH_FR30 },
 205   { "max", MACH_MAX },
 206   { 0, 0 }
 207 };
 208
 209 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
 210 {
 211   { "CACHE-ADDR", NULL },
 212   { "FUN-ACCESS", NULL },
 213   { "PC", NULL },
 214   { "PROFILE", NULL },
 215   { 0, 0 }
 216 };
 217
 218 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
 219 {
 220   { "ABS-ADDR", NULL },
 221   { "HASH-PREFIX", NULL },
 222   { "NEGATIVE", NULL },
 223   { "PCREL-ADDR", NULL },
 224   { "RELAX", NULL },
 225   { "SEM-ONLY", NULL },
 226   { "SIGN-OPT", NULL },
 227   { "SIGNED", NULL },
 228   { "UNSIGNED", NULL },
 229   { 0, 0 }
 230 };
 231
 232 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
 233 {
 234   { "ALIAS", NULL },
 235   { "COND-CTI", NULL },
 236   { "NO-DIS", NULL },
 237   { "RELAX", NULL },
 238   { "RELAXABLE", NULL },
 239   { "SKIP-CTI", NULL },
 240   { "UNCOND-CTI", NULL },
 241   { "VIRTUAL", NULL },
 242   { 0, 0 }
 243 };
 244
 245 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
 246 {
 247   { "ac", 13 },
 248   { "fp", 14 },
 249   { "sp", 15 },
 250   { "r0", 0 },
 251   { "r1", 1 },
 252   { "r2", 2 },
 253   { "r3", 3 },
 254   { "r4", 4 },
 255   { "r5", 5 },
 256   { "r6", 6 },
 257   { "r7", 7 },
 258   { "r8", 8 },
 259   { "r9", 9 },
 260   { "r10", 10 },
 261   { "r11", 11 },
 262   { "r12", 12 },
 263   { "r13", 13 },
 264   { "r14", 14 },
 265   { "r15", 15 }
 266 };
 267
 268 CGEN_KEYWORD fr30_cgen_opval_h_gr =
 269 {
 270   & fr30_cgen_opval_h_gr_entries[0],
 271   19
 272 };
 273
 274 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
 275 {
 276   { "tbr", 0 },
 277   { "rp", 1 },
 278   { "ssp", 2 },
 279   { "usp", 3 },
 280   { "mdh", 4 },
 281   { "mdl", 5 }
 282 };
 283
 284 CGEN_KEYWORD fr30_cgen_opval_h_dr =
 285 {
 286   & fr30_cgen_opval_h_dr_entries[0],
 287   6
 288 };
 289
 290 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
 291 {
 292   { "ps", 0 }
 293 };
 294
 295 CGEN_KEYWORD fr30_cgen_opval_h_ps =
 296 {
 297   & fr30_cgen_opval_h_ps_entries[0],
 298   1
 299 };
 300
 301 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
 302 {
 303   { "r13", 0 }
 304 };
 305
 306 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
 307 {
 308   & fr30_cgen_opval_h_r13_entries[0],
 309   1
 310 };
 311
 312 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
 313 {
 314   { "r14", 0 }
 315 };
 316
 317 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
 318 {
 319   & fr30_cgen_opval_h_r14_entries[0],
 320   1
 321 };
 322
 323 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
 324 {
 325   { "r15", 0 }
 326 };
 327
 328 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
 329 {
 330   & fr30_cgen_opval_h_r15_entries[0],
 331   1
 332 };
 333
 334
 335 /* The hardware table.  */
 336
 337 #define HW_ENT(n) fr30_cgen_hw_entries[n]
 338 static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
 339 {
 340   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
 341   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 342   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 343   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 344   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 345   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 346   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
 347   { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0, { 0 } } },
 348   { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
 349   { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
 350   { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
 351   { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
 352   { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 353   { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 354   { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 355   { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 356   { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 357   { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
 358   { 0 }
 359 };
 360
 361 /* The operand table.  */
 362
 363 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
 364 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
 365
 366 const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
 367 {
 368 /* pc: program counter */
 369   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 370     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 371 /* Ri: destination register */
 372   { "Ri", & HW_ENT (HW_H_GR), 12, 4,
 373     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 374 /* Rj: source register */
 375   { "Rj", & HW_ENT (HW_H_GR), 8, 4,
 376     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 377 /* Rs1: dedicated register */
 378   { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
 379     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 380 /* Rs2: dedicated register */
 381   { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
 382     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 383 /* R13: General Register 13 */
 384   { "R13", & HW_ENT (HW_H_R13), 0, 0,
 385     { 0, 0, { 0 } }  },
 386 /* R14: General Register 14 */
 387   { "R14", & HW_ENT (HW_H_R14), 0, 0,
 388     { 0, 0, { 0 } }  },
 389 /* R15: General Register 15 */
 390   { "R15", & HW_ENT (HW_H_R15), 0, 0,
 391     { 0, 0, { 0 } }  },
 392 /* ps: Program Status register */
 393   { "ps", & HW_ENT (HW_H_PS), 0, 0,
 394     { 0, 0, { 0 } }  },
 395 /* u4: 4  bit unsigned immediate */
 396   { "u4", & HW_ENT (HW_H_UINT), 8, 4,
 397     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 398 /* m4: 4  bit negative immediate */
 399   { "m4", & HW_ENT (HW_H_UINT), 8, 4,
 400     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 401 /* u8: 8  bit unsigned immediate */
 402   { "u8", & HW_ENT (HW_H_UINT), 8, 8,
 403     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 404 /* i8: 8  bit unsigned immediate */
 405   { "i8", & HW_ENT (HW_H_UINT), 4, 8,
 406     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 407 /* udisp6: 6  bit unsigned immediate */
 408   { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
 409     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 410 /* disp8: 8  bit signed   immediate */
 411   { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
 412     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 413 /* disp9: 9  bit signed   immediate */
 414   { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
 415     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 416 /* disp10: 10 bit signed   immediate */
 417   { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
 418     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 419 /* s10: 10 bit signed   immediate */
 420   { "s10", & HW_ENT (HW_H_SINT), 8, 8,
 421     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 422 /* u10: 10 bit unsigned immediate */
 423   { "u10", & HW_ENT (HW_H_UINT), 8, 8,
 424     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 425 /* i32: 32 bit immediate */
 426   { "i32", & HW_ENT (HW_H_UINT), 16, 32,
 427     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 428 /* dir8: 8  bit direct address */
 429   { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
 430     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 431 /* dir9: 9  bit direct address */
 432   { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
 433     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 434 /* dir10: 10 bit direct address */
 435   { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
 436     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 437 /* label9: 9  bit pc relative address */
 438   { "label9", & HW_ENT (HW_H_SINT), 8, 8,
 439     { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 440 /* label12: 12 bit pc relative address */
 441   { "label12", & HW_ENT (HW_H_SINT), 5, 11,
 442     { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 443 /* cc: condition codes */
 444   { "cc", & HW_ENT (HW_H_UINT), 4, 4,
 445     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 446 /* nbit: negative  bit */
 447   { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
 448     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 449 /* vbit: overflow  bit */
 450   { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
 451     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 452 /* zbit: zero      bit */
 453   { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
 454     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 455 /* cbit: carry     bit */
 456   { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
 457     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 458 /* ibit: interrupt bit */
 459   { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
 460     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 461 /* sbit: stack     bit */
 462   { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
 463     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 464 };
 465
 466 /* Operand references.  */
 467
 468 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
 469 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
 470 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
 471
 472 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
 473   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 474   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 475   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 476   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 477   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 478   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 479   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 480   { 0 }
 481 };
 482
 483 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
 484   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 485   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
 486   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 487   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 488   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 489   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 490   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 491   { 0 }
 492 };
 493
 494 static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
 495   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 496   { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
 497   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 498   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 499   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 500   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 501   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 502   { 0 }
 503 };
 504
 505 static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
 506   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 507   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 508   { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 509   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 510   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 511   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 512   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 513   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 514   { 0 }
 515 };
 516
 517 static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
 518   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 519   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 520   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 521   { 0 }
 522 };
 523
 524 static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
 525   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 526   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
 527   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 528   { 0 }
 529 };
 530
 531 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
 532   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 533   { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
 534   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 535   { 0 }
 536 };
 537
 538 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
 539   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 540   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 541   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 542   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 543   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 544   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 545   { 0 }
 546 };
 547
 548 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
 549   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 550   { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
 551   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 552   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 553   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 554   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 555   { 0 }
 556 };
 557
 558 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
 559   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 560   { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
 561   { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
 562   { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
 563   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 564   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 565   { 0 }
 566 };
 567
 568 static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
 569   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 570   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 571   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 572   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 573   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 574   { 0 }
 575 };
 576
 577 static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
 578   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
 579   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
 580   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
 581   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 582   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 583   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
 584   { 0 }
 585 };
 586
 587 static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
 588   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
 589   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
 590   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
 591   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 592   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 593   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
 594   { 0 }
 595 };
 596
 597 static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
 598   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
 599   { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
 600   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
 601   { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
 602   { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
 603   { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
 604   { 0 }
 605 };
 606
 607 static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
 608   { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
 609   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 610   { 0 }
 611 };
 612
 613 static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
 614   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
 615   { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_USI, & OP_ENT (RS1), 0, 0 },
 616   { 0 }
 617 };
 618
 619 static const CGEN_OPERAND_INSTANCE fmt_int_ops[] = {
 620   { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, 0 },
 621   { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
 622   { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
 623   { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (U8), 0, 0 },
 624   { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, 0 },
 625   { OUTPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, 0 },
 626   { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
 627   { OUTPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
 628   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
 629   { 0 }
 630 };
 631
 632 static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
 633   { INPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
 634   { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, COND_REF },
 635   { INPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
 636   { INPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 3, COND_REF },
 637   { INPUT, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
 638   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
 639   { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, COND_REF },
 640   { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, COND_REF },
 641   { OUTPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 3, COND_REF },
 642   { 0 }
 643 };
 644
 645 #undef INPUT
 646 #undef OUTPUT
 647 #undef COND_REF
 648
 649 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
 650 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
 651 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 652
 653 /* The instruction table.
 654    This is currently non-static because the simulator accesses it
 655    directly.  */
 656
 657 const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
 658 {
 659   /* Special null first entry.
 660      A `num' value of zero is thus invalid.
 661      Also, the special `invalid' insn resides here.  */
 662   { { 0 }, 0 },
 663 /* add $Rj,$Ri */
 664   {
 665     { 1, 1, 1, 1 },
 666     FR30_INSN_ADD, "add", "add",
 667     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 668     { 16, 16, 0xff00 }, 0xa600,
 669     (PTR) & fmt_add_ops[0],
 670     { 0, 0, { 0 } }
 671   },
 672 /* add $u4,$Ri */
 673   {
 674     { 1, 1, 1, 1 },
 675     FR30_INSN_ADDI, "addi", "add",
 676     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
 677     { 16, 16, 0xff00 }, 0xa400,
 678     (PTR) & fmt_addi_ops[0],
 679     { 0, 0, { 0 } }
 680   },
 681 /* add2 $m4,$Ri */
 682   {
 683     { 1, 1, 1, 1 },
 684     FR30_INSN_ADD2, "add2", "add2",
 685     { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
 686     { 16, 16, 0xff00 }, 0xa500,
 687     (PTR) & fmt_add2_ops[0],
 688     { 0, 0, { 0 } }
 689   },
 690 /* addc $Rj,$Ri */
 691   {
 692     { 1, 1, 1, 1 },
 693     FR30_INSN_ADDC, "addc", "addc",
 694     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 695     { 16, 16, 0xff00 }, 0xa700,
 696     (PTR) & fmt_addc_ops[0],
 697     { 0, 0, { 0 } }
 698   },
 699 /* addn $Rj,$Ri */
 700   {
 701     { 1, 1, 1, 1 },
 702     FR30_INSN_ADDN, "addn", "addn",
 703     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 704     { 16, 16, 0xff00 }, 0xa200,
 705     (PTR) & fmt_addn_ops[0],
 706     { 0, 0, { 0 } }
 707   },
 708 /* addn $u4,$Ri */
 709   {
 710     { 1, 1, 1, 1 },
 711     FR30_INSN_ADDNI, "addni", "addn",
 712     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
 713     { 16, 16, 0xff00 }, 0xa000,
 714     (PTR) & fmt_addni_ops[0],
 715     { 0, 0, { 0 } }
 716   },
 717 /* addn2 $m4,$Ri */
 718   {
 719     { 1, 1, 1, 1 },
 720     FR30_INSN_ADDN2, "addn2", "addn2",
 721     { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
 722     { 16, 16, 0xff00 }, 0xa100,
 723     (PTR) & fmt_addn2_ops[0],
 724     { 0, 0, { 0 } }
 725   },
 726 /* sub $Rj,$Ri */
 727   {
 728     { 1, 1, 1, 1 },
 729     FR30_INSN_SUB, "sub", "sub",
 730     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 731     { 16, 16, 0xff00 }, 0xac00,
 732     (PTR) & fmt_add_ops[0],
 733     { 0, 0, { 0 } }
 734   },
 735 /* subc $Rj,$Ri */
 736   {
 737     { 1, 1, 1, 1 },
 738     FR30_INSN_SUBC, "subc", "subc",
 739     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 740     { 16, 16, 0xff00 }, 0xad00,
 741     (PTR) & fmt_addc_ops[0],
 742     { 0, 0, { 0 } }
 743   },
 744 /* subn $Rj,$Ri */
 745   {
 746     { 1, 1, 1, 1 },
 747     FR30_INSN_SUBN, "subn", "subn",
 748     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 749     { 16, 16, 0xff00 }, 0xae00,
 750     (PTR) & fmt_addn_ops[0],
 751     { 0, 0, { 0 } }
 752   },
 753 /* cmp $Rj,$Ri */
 754   {
 755     { 1, 1, 1, 1 },
 756     FR30_INSN_CMP, "cmp", "cmp",
 757     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 758     { 16, 16, 0xff00 }, 0xaa00,
 759     (PTR) & fmt_cmp_ops[0],
 760     { 0, 0, { 0 } }
 761   },
 762 /* cmp $u4,$Ri */
 763   {
 764     { 1, 1, 1, 1 },
 765     FR30_INSN_CMPI, "cmpi", "cmp",
 766     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
 767     { 16, 16, 0xff00 }, 0xa800,
 768     (PTR) & fmt_cmpi_ops[0],
 769     { 0, 0, { 0 } }
 770   },
 771 /* cmp2 $m4,$Ri */
 772   {
 773     { 1, 1, 1, 1 },
 774     FR30_INSN_CMP2, "cmp2", "cmp2",
 775     { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
 776     { 16, 16, 0xff00 }, 0xa900,
 777     (PTR) & fmt_cmp2_ops[0],
 778     { 0, 0, { 0 } }
 779   },
 780 /* and $Rj,$Ri */
 781   {
 782     { 1, 1, 1, 1 },
 783     FR30_INSN_AND, "and", "and",
 784     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 785     { 16, 16, 0xff00 }, 0x8200,
 786     (PTR) & fmt_and_ops[0],
 787     { 0, 0, { 0 } }
 788   },
 789 /* or $Rj,$Ri */
 790   {
 791     { 1, 1, 1, 1 },
 792     FR30_INSN_OR, "or", "or",
 793     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 794     { 16, 16, 0xff00 }, 0x9200,
 795     (PTR) & fmt_and_ops[0],
 796     { 0, 0, { 0 } }
 797   },
 798 /* eor $Rj,$Ri */
 799   {
 800     { 1, 1, 1, 1 },
 801     FR30_INSN_EOR, "eor", "eor",
 802     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 803     { 16, 16, 0xff00 }, 0x9a00,
 804     (PTR) & fmt_and_ops[0],
 805     { 0, 0, { 0 } }
 806   },
 807 /* and $Rj,@$Ri */
 808   {
 809     { 1, 1, 1, 1 },
 810     FR30_INSN_ANDM, "andm", "and",
 811     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 812     { 16, 16, 0xff00 }, 0x8400,
 813     (PTR) & fmt_andm_ops[0],
 814     { 0, 0, { 0 } }
 815   },
 816 /* andh $Rj,@$Ri */
 817   {
 818     { 1, 1, 1, 1 },
 819     FR30_INSN_ANDH, "andh", "andh",
 820     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 821     { 16, 16, 0xff00 }, 0x8500,
 822     (PTR) & fmt_andh_ops[0],
 823     { 0, 0, { 0 } }
 824   },
 825 /* andb $Rj,@$Ri */
 826   {
 827     { 1, 1, 1, 1 },
 828     FR30_INSN_ANDB, "andb", "andb",
 829     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 830     { 16, 16, 0xff00 }, 0x8600,
 831     (PTR) & fmt_andb_ops[0],
 832     { 0, 0, { 0 } }
 833   },
 834 /* or $Rj,@$Ri */
 835   {
 836     { 1, 1, 1, 1 },
 837     FR30_INSN_ORM, "orm", "or",
 838     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 839     { 16, 16, 0xff00 }, 0x9400,
 840     (PTR) & fmt_andm_ops[0],
 841     { 0, 0, { 0 } }
 842   },
 843 /* orh $Rj,@$Ri */
 844   {
 845     { 1, 1, 1, 1 },
 846     FR30_INSN_ORH, "orh", "orh",
 847     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 848     { 16, 16, 0xff00 }, 0x9500,
 849     (PTR) & fmt_andh_ops[0],
 850     { 0, 0, { 0 } }
 851   },
 852 /* orb $Rj,@$Ri */
 853   {
 854     { 1, 1, 1, 1 },
 855     FR30_INSN_ORB, "orb", "orb",
 856     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 857     { 16, 16, 0xff00 }, 0x9600,
 858     (PTR) & fmt_andb_ops[0],
 859     { 0, 0, { 0 } }
 860   },
 861 /* eor $Rj,@$Ri */
 862   {
 863     { 1, 1, 1, 1 },
 864     FR30_INSN_EORM, "eorm", "eor",
 865     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 866     { 16, 16, 0xff00 }, 0x9c00,
 867     (PTR) & fmt_andm_ops[0],
 868     { 0, 0, { 0 } }
 869   },
 870 /* eorh $Rj,@$Ri */
 871   {
 872     { 1, 1, 1, 1 },
 873     FR30_INSN_EORH, "eorh", "eorh",
 874     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 875     { 16, 16, 0xff00 }, 0x9d00,
 876     (PTR) & fmt_andh_ops[0],
 877     { 0, 0, { 0 } }
 878   },
 879 /* eorb $Rj,@$Ri */
 880   {
 881     { 1, 1, 1, 1 },
 882     FR30_INSN_EORB, "eorb", "eorb",
 883     { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
 884     { 16, 16, 0xff00 }, 0x9e00,
 885     (PTR) & fmt_andb_ops[0],
 886     { 0, 0, { 0 } }
 887   },
 888 /* bandl $u4,@$Ri */
 889   {
 890     { 1, 1, 1, 1 },
 891     FR30_INSN_BANDL, "bandl", "bandl",
 892     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 893     { 16, 16, 0xff00 }, 0x8000,
 894     (PTR) 0,
 895     { 0, 0, { 0 } }
 896   },
 897 /* borl $u4,@$Ri */
 898   {
 899     { 1, 1, 1, 1 },
 900     FR30_INSN_BORL, "borl", "borl",
 901     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 902     { 16, 16, 0xff00 }, 0x9000,
 903     (PTR) 0,
 904     { 0, 0, { 0 } }
 905   },
 906 /* beorl $u4,@$Ri */
 907   {
 908     { 1, 1, 1, 1 },
 909     FR30_INSN_BEORL, "beorl", "beorl",
 910     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 911     { 16, 16, 0xff00 }, 0x9800,
 912     (PTR) 0,
 913     { 0, 0, { 0 } }
 914   },
 915 /* bandh $u4,@$Ri */
 916   {
 917     { 1, 1, 1, 1 },
 918     FR30_INSN_BANDH, "bandh", "bandh",
 919     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 920     { 16, 16, 0xff00 }, 0x8100,
 921     (PTR) 0,
 922     { 0, 0, { 0 } }
 923   },
 924 /* borh $u4,@$Ri */
 925   {
 926     { 1, 1, 1, 1 },
 927     FR30_INSN_BORH, "borh", "borh",
 928     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 929     { 16, 16, 0xff00 }, 0x9100,
 930     (PTR) 0,
 931     { 0, 0, { 0 } }
 932   },
 933 /* beorh $u4,@$Ri */
 934   {
 935     { 1, 1, 1, 1 },
 936     FR30_INSN_BEORH, "beorh", "beorh",
 937     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 938     { 16, 16, 0xff00 }, 0x9900,
 939     (PTR) 0,
 940     { 0, 0, { 0 } }
 941   },
 942 /* btstl $u4,@$Ri */
 943   {
 944     { 1, 1, 1, 1 },
 945     FR30_INSN_BTSTL, "btstl", "btstl",
 946     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 947     { 16, 16, 0xff00 }, 0x8800,
 948     (PTR) 0,
 949     { 0, 0, { 0 } }
 950   },
 951 /* btsth $u4,@$Ri */
 952   {
 953     { 1, 1, 1, 1 },
 954     FR30_INSN_BTSTH, "btsth", "btsth",
 955     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
 956     { 16, 16, 0xff00 }, 0x8900,
 957     (PTR) 0,
 958     { 0, 0, { 0 } }
 959   },
 960 /* mul $Rj,$Ri */
 961   {
 962     { 1, 1, 1, 1 },
 963     FR30_INSN_MUL, "mul", "mul",
 964     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 965     { 16, 16, 0xff00 }, 0xaf00,
 966     (PTR) 0,
 967     { 0, 0, { 0 } }
 968   },
 969 /* mulu $Rj,$Ri */
 970   {
 971     { 1, 1, 1, 1 },
 972     FR30_INSN_MULU, "mulu", "mulu",
 973     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 974     { 16, 16, 0xff00 }, 0xab00,
 975     (PTR) 0,
 976     { 0, 0, { 0 } }
 977   },
 978 /* mulh $Rj,$Ri */
 979   {
 980     { 1, 1, 1, 1 },
 981     FR30_INSN_MULH, "mulh", "mulh",
 982     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 983     { 16, 16, 0xff00 }, 0xbf00,
 984     (PTR) 0,
 985     { 0, 0, { 0 } }
 986   },
 987 /* muluh $Rj,$Ri */
 988   {
 989     { 1, 1, 1, 1 },
 990     FR30_INSN_MULUH, "muluh", "muluh",
 991     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
 992     { 16, 16, 0xff00 }, 0xbb00,
 993     (PTR) 0,
 994     { 0, 0, { 0 } }
 995   },
 996 /* div0s $Ri */
 997   {
 998     { 1, 1, 1, 1 },
 999     FR30_INSN_DIV0S, "div0s", "div0s",
1000     { { MNEM, ' ', OP (RI), 0 } },
1001     { 16, 16, 0xfff0 }, 0x9740,
1002     (PTR) 0,
1003     { 0, 0, { 0 } }
1004   },
1005 /* div0u $Ri */
1006   {
1007     { 1, 1, 1, 1 },
1008     FR30_INSN_DIV0U, "div0u", "div0u",
1009     { { MNEM, ' ', OP (RI), 0 } },
1010     { 16, 16, 0xfff0 }, 0x9750,
1011     (PTR) 0,
1012     { 0, 0, { 0 } }
1013   },
1014 /* div1 $Ri */
1015   {
1016     { 1, 1, 1, 1 },
1017     FR30_INSN_DIV1, "div1", "div1",
1018     { { MNEM, ' ', OP (RI), 0 } },
1019     { 16, 16, 0xfff0 }, 0x9760,
1020     (PTR) 0,
1021     { 0, 0, { 0 } }
1022   },
1023 /* div2 $Ri */
1024   {
1025     { 1, 1, 1, 1 },
1026     FR30_INSN_DIV2, "div2", "div2",
1027     { { MNEM, ' ', OP (RI), 0 } },
1028     { 16, 16, 0xfff0 }, 0x9770,
1029     (PTR) 0,
1030     { 0, 0, { 0 } }
1031   },
1032 /* div3 */
1033   {
1034     { 1, 1, 1, 1 },
1035     FR30_INSN_DIV3, "div3", "div3",
1036     { { MNEM, 0 } },
1037     { 16, 16, 0xffff }, 0x9f60,
1038     (PTR) 0,
1039     { 0, 0, { 0 } }
1040   },
1041 /* div4s */
1042   {
1043     { 1, 1, 1, 1 },
1044     FR30_INSN_DIV4S, "div4s", "div4s",
1045     { { MNEM, 0 } },
1046     { 16, 16, 0xffff }, 0x9f70,
1047     (PTR) 0,
1048     { 0, 0, { 0 } }
1049   },
1050 /* lsl $Rj,$Ri */
1051   {
1052     { 1, 1, 1, 1 },
1053     FR30_INSN_LSL, "lsl", "lsl",
1054     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1055     { 16, 16, 0xff00 }, 0xb600,
1056     (PTR) 0,
1057     { 0, 0, { 0 } }
1058   },
1059 /* lsl $u4,$Ri */
1060   {
1061     { 1, 1, 1, 1 },
1062     FR30_INSN_LSLI, "lsli", "lsl",
1063     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1064     { 16, 16, 0xff00 }, 0xb400,
1065     (PTR) 0,
1066     { 0, 0, { 0 } }
1067   },
1068 /* lsl2 $u4,$Ri */
1069   {
1070     { 1, 1, 1, 1 },
1071     FR30_INSN_LSL2, "lsl2", "lsl2",
1072     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1073     { 16, 16, 0xff00 }, 0xb500,
1074     (PTR) 0,
1075     { 0, 0, { 0 } }
1076   },
1077 /* lsr $Rj,$Ri */
1078   {
1079     { 1, 1, 1, 1 },
1080     FR30_INSN_LSR, "lsr", "lsr",
1081     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1082     { 16, 16, 0xff00 }, 0xb200,
1083     (PTR) 0,
1084     { 0, 0, { 0 } }
1085   },
1086 /* lsr $u4,$Ri */
1087   {
1088     { 1, 1, 1, 1 },
1089     FR30_INSN_LSRI, "lsri", "lsr",
1090     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1091     { 16, 16, 0xff00 }, 0xb000,
1092     (PTR) 0,
1093     { 0, 0, { 0 } }
1094   },
1095 /* lsr2 $u4,$Ri */
1096   {
1097     { 1, 1, 1, 1 },
1098     FR30_INSN_LSR2, "lsr2", "lsr2",
1099     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1100     { 16, 16, 0xff00 }, 0xb100,
1101     (PTR) 0,
1102     { 0, 0, { 0 } }
1103   },
1104 /* asr $Rj,$Ri */
1105   {
1106     { 1, 1, 1, 1 },
1107     FR30_INSN_ASR, "asr", "asr",
1108     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1109     { 16, 16, 0xff00 }, 0xba00,
1110     (PTR) 0,
1111     { 0, 0, { 0 } }
1112   },
1113 /* asr $u4,$Ri */
1114   {
1115     { 1, 1, 1, 1 },
1116     FR30_INSN_ASRI, "asri", "asr",
1117     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1118     { 16, 16, 0xff00 }, 0xb800,
1119     (PTR) 0,
1120     { 0, 0, { 0 } }
1121   },
1122 /* asr2 $u4,$Ri */
1123   {
1124     { 1, 1, 1, 1 },
1125     FR30_INSN_ASR2, "asr2", "asr2",
1126     { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1127     { 16, 16, 0xff00 }, 0xb900,
1128     (PTR) 0,
1129     { 0, 0, { 0 } }
1130   },
1131 /* ldi:8 $i8,$Ri */
1132   {
1133     { 1, 1, 1, 1 },
1134     FR30_INSN_LDI_8, "ldi:8", "ldi:8",
1135     { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
1136     { 16, 16, 0xf000 }, 0xc000,
1137     (PTR) 0,
1138     { 0, 0, { 0 } }
1139   },
1140 /* ldi:32 $i32,$Ri */
1141   {
1142     { 1, 1, 1, 1 },
1143     FR30_INSN_LDI32, "ldi32", "ldi:32",
1144     { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
1145     { 16, 48, 0xfff0 }, 0x9f80,
1146     (PTR) & fmt_ldi32_ops[0],
1147     { 0, 0, { 0 } }
1148   },
1149 /* ld @$Rj,$Ri */
1150   {
1151     { 1, 1, 1, 1 },
1152     FR30_INSN_LD, "ld", "ld",
1153     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1154     { 16, 16, 0xff00 }, 0x400,
1155     (PTR) 0,
1156     { 0, 0, { 0 } }
1157   },
1158 /* lduh @$Rj,$Ri */
1159   {
1160     { 1, 1, 1, 1 },
1161     FR30_INSN_LDUH, "lduh", "lduh",
1162     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1163     { 16, 16, 0xff00 }, 0x500,
1164     (PTR) 0,
1165     { 0, 0, { 0 } }
1166   },
1167 /* ldub @$Rj,$Ri */
1168   {
1169     { 1, 1, 1, 1 },
1170     FR30_INSN_LDUB, "ldub", "ldub",
1171     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1172     { 16, 16, 0xff00 }, 0x600,
1173     (PTR) 0,
1174     { 0, 0, { 0 } }
1175   },
1176 /* ld @($r13,$Rj),$Ri */
1177   {
1178     { 1, 1, 1, 1 },
1179     FR30_INSN_LDR13, "ldr13", "ld",
1180     { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1181     { 16, 16, 0xff00 }, 0x0,
1182     (PTR) 0,
1183     { 0, 0, { 0 } }
1184   },
1185 /* lduh @($r13,$Rj),$Ri */
1186   {
1187     { 1, 1, 1, 1 },
1188     FR30_INSN_LDR13UH, "ldr13uh", "lduh",
1189     { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1190     { 16, 16, 0xff00 }, 0x100,
1191     (PTR) 0,
1192     { 0, 0, { 0 } }
1193   },
1194 /* ldub @($r13,$Rj),$Ri */
1195   {
1196     { 1, 1, 1, 1 },
1197     FR30_INSN_LDR13UB, "ldr13ub", "ldub",
1198     { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1199     { 16, 16, 0xff00 }, 0x200,
1200     (PTR) 0,
1201     { 0, 0, { 0 } }
1202   },
1203 /* ld @($r14,$disp10),$Ri */
1204   {
1205     { 1, 1, 1, 1 },
1206     FR30_INSN_LDR14, "ldr14", "ld",
1207     { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
1208     { 16, 16, 0xf000 }, 0x2000,
1209     (PTR) 0,
1210     { 0, 0, { 0 } }
1211   },
1212 /* lduh @($r14,$disp9),$Ri */
1213   {
1214     { 1, 1, 1, 1 },
1215     FR30_INSN_LDR14UH, "ldr14uh", "lduh",
1216     { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
1217     { 16, 16, 0xf000 }, 0x4000,
1218     (PTR) 0,
1219     { 0, 0, { 0 } }
1220   },
1221 /* ldub @($r14,$disp8),$Ri */
1222   {
1223     { 1, 1, 1, 1 },
1224     FR30_INSN_LDR14UB, "ldr14ub", "ldub",
1225     { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
1226     { 16, 16, 0xf000 }, 0x6000,
1227     (PTR) 0,
1228     { 0, 0, { 0 } }
1229   },
1230 /* ld @($r15,$udisp6),$Ri */
1231   {
1232     { 1, 1, 1, 1 },
1233     FR30_INSN_LDR15, "ldr15", "ld",
1234     { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
1235     { 16, 16, 0xff00 }, 0x300,
1236     (PTR) 0,
1237     { 0, 0, { 0 } }
1238   },
1239 /* ld @$r15+,$Ri */
1240   {
1241     { 1, 1, 1, 1 },
1242     FR30_INSN_LDR15GR, "ldr15gr", "ld",
1243     { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
1244     { 16, 16, 0xfff0 }, 0x700,
1245     (PTR) 0,
1246     { 0, 0, { 0 } }
1247   },
1248 /* ld @$r15+,$Rs2 */
1249   {
1250     { 1, 1, 1, 1 },
1251     FR30_INSN_LDR15DR, "ldr15dr", "ld",
1252     { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
1253     { 16, 16, 0xfff0 }, 0x780,
1254     (PTR) 0,
1255     { 0, 0, { 0 } }
1256   },
1257 /* ld @$r15+,$ps */
1258   {
1259     { 1, 1, 1, 1 },
1260     FR30_INSN_LDR15PS, "ldr15ps", "ld",
1261     { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
1262     { 16, 16, 0xffff }, 0x790,
1263     (PTR) 0,
1264     { 0, 0, { 0 } }
1265   },
1266 /* st $Ri,@$Rj */
1267   {
1268     { 1, 1, 1, 1 },
1269     FR30_INSN_ST, "st", "st",
1270     { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1271     { 16, 16, 0xff00 }, 0x1400,
1272     (PTR) 0,
1273     { 0, 0, { 0 } }
1274   },
1275 /* sth $Ri,@$Rj */
1276   {
1277     { 1, 1, 1, 1 },
1278     FR30_INSN_STH, "sth", "sth",
1279     { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1280     { 16, 16, 0xff00 }, 0x1500,
1281     (PTR) 0,
1282     { 0, 0, { 0 } }
1283   },
1284 /* stb $Ri,@$Rj */
1285   {
1286     { 1, 1, 1, 1 },
1287     FR30_INSN_STB, "stb", "stb",
1288     { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1289     { 16, 16, 0xff00 }, 0x1600,
1290     (PTR) 0,
1291     { 0, 0, { 0 } }
1292   },
1293 /* st $Ri,@($r13,$Rj) */
1294   {
1295     { 1, 1, 1, 1 },
1296     FR30_INSN_STR13, "str13", "st",
1297     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1298     { 16, 16, 0xff00 }, 0x1000,
1299     (PTR) 0,
1300     { 0, 0, { 0 } }
1301   },
1302 /* sth $Ri,@($r13,$Rj) */
1303   {
1304     { 1, 1, 1, 1 },
1305     FR30_INSN_STR13H, "str13h", "sth",
1306     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1307     { 16, 16, 0xff00 }, 0x1100,
1308     (PTR) 0,
1309     { 0, 0, { 0 } }
1310   },
1311 /* stb $Ri,@($r13,$Rj) */
1312   {
1313     { 1, 1, 1, 1 },
1314     FR30_INSN_STR13B, "stR13b", "stb",
1315     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1316     { 16, 16, 0xff00 }, 0x1200,
1317     (PTR) 0,
1318     { 0, 0, { 0 } }
1319   },
1320 /* st $Ri,@($r14,$disp10) */
1321   {
1322     { 1, 1, 1, 1 },
1323     FR30_INSN_STR14, "str14", "st",
1324     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
1325     { 16, 16, 0xf000 }, 0x3000,
1326     (PTR) 0,
1327     { 0, 0, { 0 } }
1328   },
1329 /* sth $Ri,@($r14,$disp9) */
1330   {
1331     { 1, 1, 1, 1 },
1332     FR30_INSN_STR14H, "str14h", "sth",
1333     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
1334     { 16, 16, 0xf000 }, 0x5000,
1335     (PTR) 0,
1336     { 0, 0, { 0 } }
1337   },
1338 /* stb $Ri,@($r14,$disp8) */
1339   {
1340     { 1, 1, 1, 1 },
1341     FR30_INSN_STR14B, "str14b", "stb",
1342     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
1343     { 16, 16, 0xf000 }, 0x7000,
1344     (PTR) 0,
1345     { 0, 0, { 0 } }
1346   },
1347 /* st $Ri,@($r15,$udisp6) */
1348   {
1349     { 1, 1, 1, 1 },
1350     FR30_INSN_STR15, "str15", "st",
1351     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
1352     { 16, 16, 0xff00 }, 0x1300,
1353     (PTR) 0,
1354     { 0, 0, { 0 } }
1355   },
1356 /* st $Ri,@-$r15 */
1357   {
1358     { 1, 1, 1, 1 },
1359     FR30_INSN_STR15GR, "str15gr", "st",
1360     { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
1361     { 16, 16, 0xfff0 }, 0x1700,
1362     (PTR) 0,
1363     { 0, 0, { 0 } }
1364   },
1365 /* st $Rs2,@-$r15 */
1366   {
1367     { 1, 1, 1, 1 },
1368     FR30_INSN_STR15DR, "str15dr", "st",
1369     { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
1370     { 16, 16, 0xfff0 }, 0x1780,
1371     (PTR) 0,
1372     { 0, 0, { 0 } }
1373   },
1374 /* st $ps,@-$r15 */
1375   {
1376     { 1, 1, 1, 1 },
1377     FR30_INSN_STR15PS, "str15ps", "st",
1378     { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
1379     { 16, 16, 0xffff }, 0x1790,
1380     (PTR) 0,
1381     { 0, 0, { 0 } }
1382   },
1383 /* mov $Rj,$Ri */
1384   {
1385     { 1, 1, 1, 1 },
1386     FR30_INSN_MOV, "mov", "mov",
1387     { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1388     { 16, 16, 0xff00 }, 0x8b00,
1389     (PTR) 0,
1390     { 0, 0, { 0 } }
1391   },
1392 /* mov $Rs1,$Ri */
1393   {
1394     { 1, 1, 1, 1 },
1395     FR30_INSN_MOVDR, "movdr", "mov",
1396     { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
1397     { 16, 16, 0xff00 }, 0xb700,
1398     (PTR) 0,
1399     { 0, 0, { 0 } }
1400   },
1401 /* mov $ps,$Ri */
1402   {
1403     { 1, 1, 1, 1 },
1404     FR30_INSN_MOVPS, "movps", "mov",
1405     { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
1406     { 16, 16, 0xfff0 }, 0x1710,
1407     (PTR) 0,
1408     { 0, 0, { 0 } }
1409   },
1410 /* mov $Ri,$Rs1 */
1411   {
1412     { 1, 1, 1, 1 },
1413     FR30_INSN_MOV2DR, "mov2dr", "mov",
1414     { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
1415     { 16, 16, 0xff00 }, 0xb300,
1416     (PTR) & fmt_mov2dr_ops[0],
1417     { 0, 0, { 0 } }
1418   },
1419 /* mov $Ri,$ps */
1420   {
1421     { 1, 1, 1, 1 },
1422     FR30_INSN_MOV2PS, "mov2ps", "mov",
1423     { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
1424     { 16, 16, 0xfff0 }, 0x710,
1425     (PTR) 0,
1426     { 0, 0, { 0 } }
1427   },
1428 /* jmp @$Ri */
1429   {
1430     { 1, 1, 1, 1 },
1431     FR30_INSN_JMP, "jmp", "jmp",
1432     { { MNEM, ' ', '@', OP (RI), 0 } },
1433     { 16, 16, 0xfff0 }, 0x9700,
1434     (PTR) 0,
1435     { 0, 0, { 0 } }
1436   },
1437 /* jmp:D @$Ri */
1438   {
1439     { 1, 1, 1, 1 },
1440     FR30_INSN_JMPD, "jmpd", "jmp:D",
1441     { { MNEM, ' ', '@', OP (RI), 0 } },
1442     { 16, 16, 0xfff0 }, 0x9f00,
1443     (PTR) 0,
1444     { 0, 0, { 0 } }
1445   },
1446 /* call $label12 */
1447   {
1448     { 1, 1, 1, 1 },
1449     FR30_INSN_CALL, "call", "call",
1450     { { MNEM, ' ', OP (LABEL12), 0 } },
1451     { 16, 16, 0xf400 }, 0xd000,
1452     (PTR) 0,
1453     { 0, 0, { 0 } }
1454   },
1455 /* call:D $label12 */
1456   {
1457     { 1, 1, 1, 1 },
1458     FR30_INSN_CALLD, "calld", "call:D",
1459     { { MNEM, ' ', OP (LABEL12), 0 } },
1460     { 16, 16, 0xf400 }, 0xd400,
1461     (PTR) 0,
1462     { 0, 0, { 0 } }
1463   },
1464 /* call @$Ri */
1465   {
1466     { 1, 1, 1, 1 },
1467     FR30_INSN_CALLR, "callr", "call",
1468     { { MNEM, ' ', '@', OP (RI), 0 } },
1469     { 16, 16, 0xfff0 }, 0x9710,
1470     (PTR) 0,
1471     { 0, 0, { 0 } }
1472   },
1473 /* call:D @$Ri */
1474   {
1475     { 1, 1, 1, 1 },
1476     FR30_INSN_CALLRD, "callrd", "call:D",
1477     { { MNEM, ' ', '@', OP (RI), 0 } },
1478     { 16, 16, 0xfff0 }, 0x9f10,
1479     (PTR) 0,
1480     { 0, 0, { 0 } }
1481   },
1482 /* ret */
1483   {
1484     { 1, 1, 1, 1 },
1485     FR30_INSN_RET, "ret", "ret",
1486     { { MNEM, 0 } },
1487     { 16, 16, 0xffff }, 0x9720,
1488     (PTR) 0,
1489     { 0, 0, { 0 } }
1490   },
1491 /* ret:D */
1492   {
1493     { 1, 1, 1, 1 },
1494     FR30_INSN_RETD, "retd", "ret:D",
1495     { { MNEM, 0 } },
1496     { 16, 16, 0xffff }, 0x9f20,
1497     (PTR) 0,
1498     { 0, 0, { 0 } }
1499   },
1500 /* int $u8 */
1501   {
1502     { 1, 1, 1, 1 },
1503     FR30_INSN_INT, "int", "int",
1504     { { MNEM, ' ', OP (U8), 0 } },
1505     { 16, 16, 0xff00 }, 0x1f00,
1506     (PTR) & fmt_int_ops[0],
1507     { 0, 0|A(UNCOND_CTI), { 0 } }
1508   },
1509 /* inte */
1510   {
1511     { 1, 1, 1, 1 },
1512     FR30_INSN_INTE, "inte", "inte",
1513     { { MNEM, 0 } },
1514     { 16, 16, 0xffff }, 0x9f30,
1515     (PTR) 0,
1516     { 0, 0, { 0 } }
1517   },
1518 /* reti */
1519   {
1520     { 1, 1, 1, 1 },
1521     FR30_INSN_RETI, "reti", "reti",
1522     { { MNEM, 0 } },
1523     { 16, 16, 0xffff }, 0x9730,
1524     (PTR) & fmt_reti_ops[0],
1525     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
1526   },
1527 /* bra $label9 */
1528   {
1529     { 1, 1, 1, 1 },
1530     FR30_INSN_BRA, "bra", "bra",
1531     { { MNEM, ' ', OP (LABEL9), 0 } },
1532     { 16, 16, 0xff00 }, 0xe000,
1533     (PTR) 0,
1534     { 0, 0, { 0 } }
1535   },
1536 /* bno $label9 */
1537   {
1538     { 1, 1, 1, 1 },
1539     FR30_INSN_BNO, "bno", "bno",
1540     { { MNEM, ' ', OP (LABEL9), 0 } },
1541     { 16, 16, 0xff00 }, 0xe100,
1542     (PTR) 0,
1543     { 0, 0, { 0 } }
1544   },
1545 /* beq $label9 */
1546   {
1547     { 1, 1, 1, 1 },
1548     FR30_INSN_BEQ, "beq", "beq",
1549     { { MNEM, ' ', OP (LABEL9), 0 } },
1550     { 16, 16, 0xff00 }, 0xe200,
1551     (PTR) 0,
1552     { 0, 0, { 0 } }
1553   },
1554 /* bne $label9 */
1555   {
1556     { 1, 1, 1, 1 },
1557     FR30_INSN_BNE, "bne", "bne",
1558     { { MNEM, ' ', OP (LABEL9), 0 } },
1559     { 16, 16, 0xff00 }, 0xe300,
1560     (PTR) 0,
1561     { 0, 0, { 0 } }
1562   },
1563 /* bc $label9 */
1564   {
1565     { 1, 1, 1, 1 },
1566     FR30_INSN_BC, "bc", "bc",
1567     { { MNEM, ' ', OP (LABEL9), 0 } },
1568     { 16, 16, 0xff00 }, 0xe400,
1569     (PTR) 0,
1570     { 0, 0, { 0 } }
1571   },
1572 /* bnc $label9 */
1573   {
1574     { 1, 1, 1, 1 },
1575     FR30_INSN_BNC, "bnc", "bnc",
1576     { { MNEM, ' ', OP (LABEL9), 0 } },
1577     { 16, 16, 0xff00 }, 0xe500,
1578     (PTR) 0,
1579     { 0, 0, { 0 } }
1580   },
1581 /* bn $label9 */
1582   {
1583     { 1, 1, 1, 1 },
1584     FR30_INSN_BN, "bn", "bn",
1585     { { MNEM, ' ', OP (LABEL9), 0 } },
1586     { 16, 16, 0xff00 }, 0xe600,
1587     (PTR) 0,
1588     { 0, 0, { 0 } }
1589   },
1590 /* bp $label9 */
1591   {
1592     { 1, 1, 1, 1 },
1593     FR30_INSN_BP, "bp", "bp",
1594     { { MNEM, ' ', OP (LABEL9), 0 } },
1595     { 16, 16, 0xff00 }, 0xe700,
1596     (PTR) 0,
1597     { 0, 0, { 0 } }
1598   },
1599 /* bv $label9 */
1600   {
1601     { 1, 1, 1, 1 },
1602     FR30_INSN_BV, "bv", "bv",
1603     { { MNEM, ' ', OP (LABEL9), 0 } },
1604     { 16, 16, 0xff00 }, 0xe800,
1605     (PTR) 0,
1606     { 0, 0, { 0 } }
1607   },
1608 /* bnv $label9 */
1609   {
1610     { 1, 1, 1, 1 },
1611     FR30_INSN_BNV, "bnv", "bnv",
1612     { { MNEM, ' ', OP (LABEL9), 0 } },
1613     { 16, 16, 0xff00 }, 0xe900,
1614     (PTR) 0,
1615     { 0, 0, { 0 } }
1616   },
1617 /* blt $label9 */
1618   {
1619     { 1, 1, 1, 1 },
1620     FR30_INSN_BLT, "blt", "blt",
1621     { { MNEM, ' ', OP (LABEL9), 0 } },
1622     { 16, 16, 0xff00 }, 0xea00,
1623     (PTR) 0,
1624     { 0, 0, { 0 } }
1625   },
1626 /* bge $label9 */
1627   {
1628     { 1, 1, 1, 1 },
1629     FR30_INSN_BGE, "bge", "bge",
1630     { { MNEM, ' ', OP (LABEL9), 0 } },
1631     { 16, 16, 0xff00 }, 0xeb00,
1632     (PTR) 0,
1633     { 0, 0, { 0 } }
1634   },
1635 /* ble $label9 */
1636   {
1637     { 1, 1, 1, 1 },
1638     FR30_INSN_BLE, "ble", "ble",
1639     { { MNEM, ' ', OP (LABEL9), 0 } },
1640     { 16, 16, 0xff00 }, 0xec00,
1641     (PTR) 0,
1642     { 0, 0, { 0 } }
1643   },
1644 /* bgt $label9 */
1645   {
1646     { 1, 1, 1, 1 },
1647     FR30_INSN_BGT, "bgt", "bgt",
1648     { { MNEM, ' ', OP (LABEL9), 0 } },
1649     { 16, 16, 0xff00 }, 0xed00,
1650     (PTR) 0,
1651     { 0, 0, { 0 } }
1652   },
1653 /* bls $label9 */
1654   {
1655     { 1, 1, 1, 1 },
1656     FR30_INSN_BLS, "bls", "bls",
1657     { { MNEM, ' ', OP (LABEL9), 0 } },
1658     { 16, 16, 0xff00 }, 0xee00,
1659     (PTR) 0,
1660     { 0, 0, { 0 } }
1661   },
1662 /* bhi $label9 */
1663   {
1664     { 1, 1, 1, 1 },
1665     FR30_INSN_BHI, "bhi", "bhi",
1666     { { MNEM, ' ', OP (LABEL9), 0 } },
1667     { 16, 16, 0xff00 }, 0xef00,
1668     (PTR) 0,
1669     { 0, 0, { 0 } }
1670   },
1671 /* bra:D $label9 */
1672   {
1673     { 1, 1, 1, 1 },
1674     FR30_INSN_BRAD, "brad", "bra:D",
1675     { { MNEM, ' ', OP (LABEL9), 0 } },
1676     { 16, 16, 0xff00 }, 0xf000,
1677     (PTR) 0,
1678     { 0, 0, { 0 } }
1679   },
1680 /* bno:D $label9 */
1681   {
1682     { 1, 1, 1, 1 },
1683     FR30_INSN_BNOD, "bnod", "bno:D",
1684     { { MNEM, ' ', OP (LABEL9), 0 } },
1685     { 16, 16, 0xff00 }, 0xf100,
1686     (PTR) 0,
1687     { 0, 0, { 0 } }
1688   },
1689 /* beq:D $label9 */
1690   {
1691     { 1, 1, 1, 1 },
1692     FR30_INSN_BEQD, "beqd", "beq:D",
1693     { { MNEM, ' ', OP (LABEL9), 0 } },
1694     { 16, 16, 0xff00 }, 0xf200,
1695     (PTR) 0,
1696     { 0, 0, { 0 } }
1697   },
1698 /* bne:D $label9 */
1699   {
1700     { 1, 1, 1, 1 },
1701     FR30_INSN_BNED, "bned", "bne:D",
1702     { { MNEM, ' ', OP (LABEL9), 0 } },
1703     { 16, 16, 0xff00 }, 0xf300,
1704     (PTR) 0,
1705     { 0, 0, { 0 } }
1706   },
1707 /* bc:D $label9 */
1708   {
1709     { 1, 1, 1, 1 },
1710     FR30_INSN_BCD, "bcd", "bc:D",
1711     { { MNEM, ' ', OP (LABEL9), 0 } },
1712     { 16, 16, 0xff00 }, 0xf400,
1713     (PTR) 0,
1714     { 0, 0, { 0 } }
1715   },
1716 /* bnc:D $label9 */
1717   {
1718     { 1, 1, 1, 1 },
1719     FR30_INSN_BNCD, "bncd", "bnc:D",
1720     { { MNEM, ' ', OP (LABEL9), 0 } },
1721     { 16, 16, 0xff00 }, 0xf500,
1722     (PTR) 0,
1723     { 0, 0, { 0 } }
1724   },
1725 /* bn:D $label9 */
1726   {
1727     { 1, 1, 1, 1 },
1728     FR30_INSN_BND, "bnd", "bn:D",
1729     { { MNEM, ' ', OP (LABEL9), 0 } },
1730     { 16, 16, 0xff00 }, 0xf600,
1731     (PTR) 0,
1732     { 0, 0, { 0 } }
1733   },
1734 /* bp:D $label9 */
1735   {
1736     { 1, 1, 1, 1 },
1737     FR30_INSN_BPD, "bpd", "bp:D",
1738     { { MNEM, ' ', OP (LABEL9), 0 } },
1739     { 16, 16, 0xff00 }, 0xf700,
1740     (PTR) 0,
1741     { 0, 0, { 0 } }
1742   },
1743 /* bv:D $label9 */
1744   {
1745     { 1, 1, 1, 1 },
1746     FR30_INSN_BVD, "bvd", "bv:D",
1747     { { MNEM, ' ', OP (LABEL9), 0 } },
1748     { 16, 16, 0xff00 }, 0xf800,
1749     (PTR) 0,
1750     { 0, 0, { 0 } }
1751   },
1752 /* bnv:D $label9 */
1753   {
1754     { 1, 1, 1, 1 },
1755     FR30_INSN_BNVD, "bnvd", "bnv:D",
1756     { { MNEM, ' ', OP (LABEL9), 0 } },
1757     { 16, 16, 0xff00 }, 0xf900,
1758     (PTR) 0,
1759     { 0, 0, { 0 } }
1760   },
1761 /* blt:D $label9 */
1762   {
1763     { 1, 1, 1, 1 },
1764     FR30_INSN_BLTD, "bltd", "blt:D",
1765     { { MNEM, ' ', OP (LABEL9), 0 } },
1766     { 16, 16, 0xff00 }, 0xfa00,
1767     (PTR) 0,
1768     { 0, 0, { 0 } }
1769   },
1770 /* bge:D $label9 */
1771   {
1772     { 1, 1, 1, 1 },
1773     FR30_INSN_BGED, "bged", "bge:D",
1774     { { MNEM, ' ', OP (LABEL9), 0 } },
1775     { 16, 16, 0xff00 }, 0xfb00,
1776     (PTR) 0,
1777     { 0, 0, { 0 } }
1778   },
1779 /* ble:D $label9 */
1780   {
1781     { 1, 1, 1, 1 },
1782     FR30_INSN_BLED, "bled", "ble:D",
1783     { { MNEM, ' ', OP (LABEL9), 0 } },
1784     { 16, 16, 0xff00 }, 0xfc00,
1785     (PTR) 0,
1786     { 0, 0, { 0 } }
1787   },
1788 /* bgt:D $label9 */
1789   {
1790     { 1, 1, 1, 1 },
1791     FR30_INSN_BGTD, "bgtd", "bgt:D",
1792     { { MNEM, ' ', OP (LABEL9), 0 } },
1793     { 16, 16, 0xff00 }, 0xfd00,
1794     (PTR) 0,
1795     { 0, 0, { 0 } }
1796   },
1797 /* bls:D $label9 */
1798   {
1799     { 1, 1, 1, 1 },
1800     FR30_INSN_BLSD, "blsd", "bls:D",
1801     { { MNEM, ' ', OP (LABEL9), 0 } },
1802     { 16, 16, 0xff00 }, 0xfe00,
1803     (PTR) 0,
1804     { 0, 0, { 0 } }
1805   },
1806 /* bhi:D $label9 */
1807   {
1808     { 1, 1, 1, 1 },
1809     FR30_INSN_BHID, "bhid", "bhi:D",
1810     { { MNEM, ' ', OP (LABEL9), 0 } },
1811     { 16, 16, 0xff00 }, 0xff00,
1812     (PTR) 0,
1813     { 0, 0, { 0 } }
1814   },
1815 /* dmov @$dir10,$R13 */
1816   {
1817     { 1, 1, 1, 1 },
1818     FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
1819     { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
1820     { 16, 16, 0xff00 }, 0x800,
1821     (PTR) 0,
1822     { 0, 0, { 0 } }
1823   },
1824 /* dmovh @$dir9,$R13 */
1825   {
1826     { 1, 1, 1, 1 },
1827     FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
1828     { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
1829     { 16, 16, 0xff00 }, 0x900,
1830     (PTR) 0,
1831     { 0, 0, { 0 } }
1832   },
1833 /* dmovb @$dir8,$R13 */
1834   {
1835     { 1, 1, 1, 1 },
1836     FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
1837     { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
1838     { 16, 16, 0xff00 }, 0xa00,
1839     (PTR) 0,
1840     { 0, 0, { 0 } }
1841   },
1842 /* dmov $R13,@$dir10 */
1843   {
1844     { 1, 1, 1, 1 },
1845     FR30_INSN_DMOVR13, "dmovr13", "dmov",
1846     { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
1847     { 16, 16, 0xff00 }, 0x1800,
1848     (PTR) 0,
1849     { 0, 0, { 0 } }
1850   },
1851 /* dmovh $R13,@$dir9 */
1852   {
1853     { 1, 1, 1, 1 },
1854     FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
1855     { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
1856     { 16, 16, 0xff00 }, 0x1900,
1857     (PTR) 0,
1858     { 0, 0, { 0 } }
1859   },
1860 /* dmovb $R13,@$dir8 */
1861   {
1862     { 1, 1, 1, 1 },
1863     FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
1864     { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
1865     { 16, 16, 0xff00 }, 0x1a00,
1866     (PTR) 0,
1867     { 0, 0, { 0 } }
1868   },
1869 /* dmov @$dir10,@$R13+ */
1870   {
1871     { 1, 1, 1, 1 },
1872     FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
1873     { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
1874     { 16, 16, 0xff00 }, 0xc00,
1875     (PTR) 0,
1876     { 0, 0, { 0 } }
1877   },
1878 /* dmovh @$dir9,@$R13+ */
1879   {
1880     { 1, 1, 1, 1 },
1881     FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
1882     { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
1883     { 16, 16, 0xff00 }, 0xd00,
1884     (PTR) 0,
1885     { 0, 0, { 0 } }
1886   },
1887 /* dmovb @$dir8,@$R13+ */
1888   {
1889     { 1, 1, 1, 1 },
1890     FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
1891     { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
1892     { 16, 16, 0xff00 }, 0xe00,
1893     (PTR) 0,
1894     { 0, 0, { 0 } }
1895   },
1896 /* dmov @$R13+,@$dir10 */
1897   {
1898     { 1, 1, 1, 1 },
1899     FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
1900     { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
1901     { 16, 16, 0xff00 }, 0x1c00,
1902     (PTR) 0,
1903     { 0, 0, { 0 } }
1904   },
1905 /* dmovh @$R13+,@$dir9 */
1906   {
1907     { 1, 1, 1, 1 },
1908     FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
1909     { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
1910     { 16, 16, 0xff00 }, 0x1d00,
1911     (PTR) 0,
1912     { 0, 0, { 0 } }
1913   },
1914 /* dmovb @$R13+,@$dir8 */
1915   {
1916     { 1, 1, 1, 1 },
1917     FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
1918     { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
1919     { 16, 16, 0xff00 }, 0x1e00,
1920     (PTR) 0,
1921     { 0, 0, { 0 } }
1922   },
1923 /* dmov @$dir10,@-$R15 */
1924   {
1925     { 1, 1, 1, 1 },
1926     FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
1927     { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
1928     { 16, 16, 0xff00 }, 0xb00,
1929     (PTR) 0,
1930     { 0, 0, { 0 } }
1931   },
1932 /* dmov @$R15+,@$dir10 */
1933   {
1934     { 1, 1, 1, 1 },
1935     FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
1936     { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
1937     { 16, 16, 0xff00 }, 0x1b00,
1938     (PTR) 0,
1939     { 0, 0, { 0 } }
1940   },
1941 /* ldres @$Ri+,$u4 */
1942   {
1943     { 1, 1, 1, 1 },
1944     FR30_INSN_LDRES, "ldres", "ldres",
1945     { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
1946     { 16, 16, 0xff00 }, 0xbc00,
1947     (PTR) 0,
1948     { 0, 0, { 0 } }
1949   },
1950 /* stres $u4,@$Ri+ */
1951   {
1952     { 1, 1, 1, 1 },
1953     FR30_INSN_STRES, "stres", "stres",
1954     { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
1955     { 16, 16, 0xff00 }, 0xbd00,
1956     (PTR) 0,
1957     { 0, 0, { 0 } }
1958   },
1959 /* nop */
1960   {
1961     { 1, 1, 1, 1 },
1962     FR30_INSN_NOP, "nop", "nop",
1963     { { MNEM, 0 } },
1964     { 16, 16, 0xffff }, 0x9fa0,
1965     (PTR) 0,
1966     { 0, 0, { 0 } }
1967   },
1968 /* andccr $u8 */
1969   {
1970     { 1, 1, 1, 1 },
1971     FR30_INSN_ANDCCR, "andccr", "andccr",
1972     { { MNEM, ' ', OP (U8), 0 } },
1973     { 16, 16, 0xff00 }, 0x8300,
1974     (PTR) 0,
1975     { 0, 0, { 0 } }
1976   },
1977 /* orccr $u8 */
1978   {
1979     { 1, 1, 1, 1 },
1980     FR30_INSN_ORCCR, "orccr", "orccr",
1981     { { MNEM, ' ', OP (U8), 0 } },
1982     { 16, 16, 0xff00 }, 0x9300,
1983     (PTR) 0,
1984     { 0, 0, { 0 } }
1985   },
1986 /* stilm $u8 */
1987   {
1988     { 1, 1, 1, 1 },
1989     FR30_INSN_STILM, "stilm", "stilm",
1990     { { MNEM, ' ', OP (U8), 0 } },
1991     { 16, 16, 0xff00 }, 0x8700,
1992     (PTR) 0,
1993     { 0, 0, { 0 } }
1994   },
1995 /* addsp $s10 */
1996   {
1997     { 1, 1, 1, 1 },
1998     FR30_INSN_ADDSP, "addsp", "addsp",
1999     { { MNEM, ' ', OP (S10), 0 } },
2000     { 16, 16, 0xff00 }, 0xa300,
2001     (PTR) 0,
2002     { 0, 0, { 0 } }
2003   },
2004 /* extsb $Ri */
2005   {
2006     { 1, 1, 1, 1 },
2007     FR30_INSN_EXTSB, "extsb", "extsb",
2008     { { MNEM, ' ', OP (RI), 0 } },
2009     { 16, 16, 0xfff0 }, 0x9780,
2010     (PTR) 0,
2011     { 0, 0, { 0 } }
2012   },
2013 /* extub $Ri */
2014   {
2015     { 1, 1, 1, 1 },
2016     FR30_INSN_EXTUB, "extub", "extub",
2017     { { MNEM, ' ', OP (RI), 0 } },
2018     { 16, 16, 0xfff0 }, 0x9790,
2019     (PTR) 0,
2020     { 0, 0, { 0 } }
2021   },
2022 /* extsh $Ri */
2023   {
2024     { 1, 1, 1, 1 },
2025     FR30_INSN_EXTSH, "extsh", "extsh",
2026     { { MNEM, ' ', OP (RI), 0 } },
2027     { 16, 16, 0xfff0 }, 0x97a0,
2028     (PTR) 0,
2029     { 0, 0, { 0 } }
2030   },
2031 /* extuh $Ri */
2032   {
2033     { 1, 1, 1, 1 },
2034     FR30_INSN_EXTUH, "extuh", "extuh",
2035     { { MNEM, ' ', OP (RI), 0 } },
2036     { 16, 16, 0xfff0 }, 0x97b0,
2037     (PTR) 0,
2038     { 0, 0, { 0 } }
2039   },
2040 /* enter $u10 */
2041   {
2042     { 1, 1, 1, 1 },
2043     FR30_INSN_ENTER, "enter", "enter",
2044     { { MNEM, ' ', OP (U10), 0 } },
2045     { 16, 16, 0xff00 }, 0xf00,
2046     (PTR) 0,
2047     { 0, 0, { 0 } }
2048   },
2049 /* leave */
2050   {
2051     { 1, 1, 1, 1 },
2052     FR30_INSN_LEAVE, "leave", "leave",
2053     { { MNEM, 0 } },
2054     { 16, 16, 0xffff }, 0x9f90,
2055     (PTR) 0,
2056     { 0, 0, { 0 } }
2057   },
2058 /* xchb @$Rj,$Ri */
2059   {
2060     { 1, 1, 1, 1 },
2061     FR30_INSN_XCHB, "xchb", "xchb",
2062     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2063     { 16, 16, 0xff00 }, 0x8a00,
2064     (PTR) 0,
2065     { 0, 0, { 0 } }
2066   },
2067 };
2068
2069 #undef A
2070 #undef MNEM
2071 #undef OP
2072
2073 static const CGEN_INSN_TABLE insn_table =
2074 {
2075   & fr30_cgen_insn_table_entries[0],
2076   sizeof (CGEN_INSN),
2077   MAX_INSNS,
2078   NULL
2079 };
2080
2081 /* Each non-simple macro entry points to an array of expansion possibilities.  */
2082
2083 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2084 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2085 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2086
2087 /* The macro instruction table.  */
2088
2089 static const CGEN_INSN macro_insn_table_entries[] =
2090 {
2091 /* ldi32 $i32,$Ri */
2092   {
2093     { 1, 1, 1, 1 },
2094     -1, "ldi32m", "ldi32",
2095     { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
2096     { 16, 48, 0xfff0 }, 0x9f80,
2097     (PTR) 0,
2098     { 0, 0|A(ALIAS), { 0 } }
2099   },
2100 };
2101
2102 #undef A
2103 #undef MNEM
2104 #undef OP
2105
2106 static const CGEN_INSN_TABLE macro_insn_table =
2107 {
2108   & macro_insn_table_entries[0],
2109   sizeof (CGEN_INSN),
2110   (sizeof (macro_insn_table_entries) /
2111    sizeof (macro_insn_table_entries[0])),
2112   NULL
2113 };
2114
2115 static void
2116 init_tables ()
2117 {
2118 }
2119
2120 /* Return non-zero if INSN is to be added to the hash table.
2121    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
2122
2123 static int
2124 asm_hash_insn_p (insn)
2125      const CGEN_INSN * insn;
2126 {
2127   return CGEN_ASM_HASH_P (insn);
2128 }
2129
2130 static int
2131 dis_hash_insn_p (insn)
2132      const CGEN_INSN * insn;
2133 {
2134   /* If building the hash table and the NO-DIS attribute is present,
2135      ignore.  */
2136   if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2137     return 0;
2138   return CGEN_DIS_HASH_P (insn);
2139 }
2140
2141 /* The result is the hash value of the insn.
2142    Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
2143
2144 static unsigned int
2145 asm_hash_insn (mnem)
2146      const char * mnem;
2147 {
2148   return CGEN_ASM_HASH (mnem);
2149 }
2150
2151 /* BUF is a pointer to the insn's bytes in target order.
2152    VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
2153    host order.  */
2154
2155 static unsigned int
2156 dis_hash_insn (buf, value)
2157      const char * buf;
2158      CGEN_INSN_INT value;
2159 {
2160   return CGEN_DIS_HASH (buf, value);
2161 }
2162
2163 /* Initialize an opcode table and return a descriptor.
2164    It's much like opening a file, and must be the first function called.  */
2165
2166 CGEN_OPCODE_DESC
2167 fr30_cgen_opcode_open (mach, endian)
2168      int mach;
2169      enum cgen_endian endian;
2170 {
2171   CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
2172   static int init_p;
2173
2174   if (! init_p)
2175     {
2176       init_tables ();
2177       init_p = 1;
2178     }
2179
2180   memset (table, 0, sizeof (*table));
2181
2182   CGEN_OPCODE_MACH (table) = mach;
2183   CGEN_OPCODE_ENDIAN (table) = endian;
2184   /* FIXME: for the sparc case we can determine insn-endianness statically.
2185      The worry here is where both data and insn endian can be independently
2186      chosen, in which case this function will need another argument.
2187      Actually, will want to allow for more arguments in the future anyway.  */
2188   CGEN_OPCODE_INSN_ENDIAN (table) = endian;
2189
2190   CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
2191
2192   CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
2193
2194   * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
2195
2196   * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
2197
2198   CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
2199   CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
2200   CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
2201
2202   CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
2203   CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
2204   CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
2205
2206   return (CGEN_OPCODE_DESC) table;
2207 }
2208
2209 /* Close an opcode table.  */
2210
2211 void
2212 fr30_cgen_opcode_close (desc)
2213      CGEN_OPCODE_DESC desc;
2214 {
2215   free (desc);
2216 }
2217
2218 /* Getting values from cgen_fields is handled by a collection of functions.
2219    They are distinguished by the type of the VALUE argument they return.
2220    TODO: floating point, inlining support, remove cases where result type
2221    not appropriate.  */
2222
2223 int
2224 fr30_cgen_get_int_operand (opindex, fields)
2225      int opindex;
2226      const CGEN_FIELDS * fields;
2227 {
2228   int value;
2229
2230   switch (opindex)
2231     {
2232     case FR30_OPERAND_RI :
2233       value = fields->f_Ri;
2234       break;
2235     case FR30_OPERAND_RJ :
2236       value = fields->f_Rj;
2237       break;
2238     case FR30_OPERAND_RS1 :
2239       value = fields->f_Rs1;
2240       break;
2241     case FR30_OPERAND_RS2 :
2242       value = fields->f_Rs2;
2243       break;
2244     case FR30_OPERAND_R13 :
2245       value = fields->f_nil;
2246       break;
2247     case FR30_OPERAND_R14 :
2248       value = fields->f_nil;
2249       break;
2250     case FR30_OPERAND_R15 :
2251       value = fields->f_nil;
2252       break;
2253     case FR30_OPERAND_PS :
2254       value = fields->f_nil;
2255       break;
2256     case FR30_OPERAND_U4 :
2257       value = fields->f_u4;
2258       break;
2259     case FR30_OPERAND_M4 :
2260       value = fields->f_m4;
2261       break;
2262     case FR30_OPERAND_U8 :
2263       value = fields->f_u8;
2264       break;
2265     case FR30_OPERAND_I8 :
2266       value = fields->f_i8;
2267       break;
2268     case FR30_OPERAND_UDISP6 :
2269       value = fields->f_udisp6;
2270       break;
2271     case FR30_OPERAND_DISP8 :
2272       value = fields->f_disp8;
2273       break;
2274     case FR30_OPERAND_DISP9 :
2275       value = fields->f_disp9;
2276       break;
2277     case FR30_OPERAND_DISP10 :
2278       value = fields->f_disp10;
2279       break;
2280     case FR30_OPERAND_S10 :
2281       value = fields->f_s10;
2282       break;
2283     case FR30_OPERAND_U10 :
2284       value = fields->f_u10;
2285       break;
2286     case FR30_OPERAND_I32 :
2287       value = fields->f_i32;
2288       break;
2289     case FR30_OPERAND_DIR8 :
2290       value = fields->f_dir8;
2291       break;
2292     case FR30_OPERAND_DIR9 :
2293       value = fields->f_dir9;
2294       break;
2295     case FR30_OPERAND_DIR10 :
2296       value = fields->f_dir10;
2297       break;
2298     case FR30_OPERAND_LABEL9 :
2299       value = fields->f_rel9;
2300       break;
2301     case FR30_OPERAND_LABEL12 :
2302       value = fields->f_rel12;
2303       break;
2304     case FR30_OPERAND_CC :
2305       value = fields->f_cc;
2306       break;
2307
2308     default :
2309       /* xgettext:c-format */
2310       fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
2311                        opindex);
2312       abort ();
2313   }
2314
2315   return value;
2316 }
2317
2318 bfd_vma
2319 fr30_cgen_get_vma_operand (opindex, fields)
2320      int opindex;
2321      const CGEN_FIELDS * fields;
2322 {
2323   bfd_vma value;
2324
2325   switch (opindex)
2326     {
2327     case FR30_OPERAND_RI :
2328       value = fields->f_Ri;
2329       break;
2330     case FR30_OPERAND_RJ :
2331       value = fields->f_Rj;
2332       break;
2333     case FR30_OPERAND_RS1 :
2334       value = fields->f_Rs1;
2335       break;
2336     case FR30_OPERAND_RS2 :
2337       value = fields->f_Rs2;
2338       break;
2339     case FR30_OPERAND_R13 :
2340       value = fields->f_nil;
2341       break;
2342     case FR30_OPERAND_R14 :
2343       value = fields->f_nil;
2344       break;
2345     case FR30_OPERAND_R15 :
2346       value = fields->f_nil;
2347       break;
2348     case FR30_OPERAND_PS :
2349       value = fields->f_nil;
2350       break;
2351     case FR30_OPERAND_U4 :
2352       value = fields->f_u4;
2353       break;
2354     case FR30_OPERAND_M4 :
2355       value = fields->f_m4;
2356       break;
2357     case FR30_OPERAND_U8 :
2358       value = fields->f_u8;
2359       break;
2360     case FR30_OPERAND_I8 :
2361       value = fields->f_i8;
2362       break;
2363     case FR30_OPERAND_UDISP6 :
2364       value = fields->f_udisp6;
2365       break;
2366     case FR30_OPERAND_DISP8 :
2367       value = fields->f_disp8;
2368       break;
2369     case FR30_OPERAND_DISP9 :
2370       value = fields->f_disp9;
2371       break;
2372     case FR30_OPERAND_DISP10 :
2373       value = fields->f_disp10;
2374       break;
2375     case FR30_OPERAND_S10 :
2376       value = fields->f_s10;
2377       break;
2378     case FR30_OPERAND_U10 :
2379       value = fields->f_u10;
2380       break;
2381     case FR30_OPERAND_I32 :
2382       value = fields->f_i32;
2383       break;
2384     case FR30_OPERAND_DIR8 :
2385       value = fields->f_dir8;
2386       break;
2387     case FR30_OPERAND_DIR9 :
2388       value = fields->f_dir9;
2389       break;
2390     case FR30_OPERAND_DIR10 :
2391       value = fields->f_dir10;
2392       break;
2393     case FR30_OPERAND_LABEL9 :
2394       value = fields->f_rel9;
2395       break;
2396     case FR30_OPERAND_LABEL12 :
2397       value = fields->f_rel12;
2398       break;
2399     case FR30_OPERAND_CC :
2400       value = fields->f_cc;
2401       break;
2402
2403     default :
2404       /* xgettext:c-format */
2405       fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
2406                        opindex);
2407       abort ();
2408   }
2409
2410   return value;
2411 }
2412
2413 /* Stuffing values in cgen_fields is handled by a collection of functions.
2414    They are distinguished by the type of the VALUE argument they accept.
2415    TODO: floating point, inlining support, remove cases where argument type
2416    not appropriate.  */
2417
2418 void
2419 fr30_cgen_set_int_operand (opindex, fields, value)
2420      int opindex;
2421      CGEN_FIELDS * fields;
2422      int value;
2423 {
2424   switch (opindex)
2425     {
2426     case FR30_OPERAND_RI :
2427       fields->f_Ri = value;
2428       break;
2429     case FR30_OPERAND_RJ :
2430       fields->f_Rj = value;
2431       break;
2432     case FR30_OPERAND_RS1 :
2433       fields->f_Rs1 = value;
2434       break;
2435     case FR30_OPERAND_RS2 :
2436       fields->f_Rs2 = value;
2437       break;
2438     case FR30_OPERAND_R13 :
2439       fields->f_nil = value;
2440       break;
2441     case FR30_OPERAND_R14 :
2442       fields->f_nil = value;
2443       break;
2444     case FR30_OPERAND_R15 :
2445       fields->f_nil = value;
2446       break;
2447     case FR30_OPERAND_PS :
2448       fields->f_nil = value;
2449       break;
2450     case FR30_OPERAND_U4 :
2451       fields->f_u4 = value;
2452       break;
2453     case FR30_OPERAND_M4 :
2454       fields->f_m4 = value;
2455       break;
2456     case FR30_OPERAND_U8 :
2457       fields->f_u8 = value;
2458       break;
2459     case FR30_OPERAND_I8 :
2460       fields->f_i8 = value;
2461       break;
2462     case FR30_OPERAND_UDISP6 :
2463       fields->f_udisp6 = value;
2464       break;
2465     case FR30_OPERAND_DISP8 :
2466       fields->f_disp8 = value;
2467       break;
2468     case FR30_OPERAND_DISP9 :
2469       fields->f_disp9 = value;
2470       break;
2471     case FR30_OPERAND_DISP10 :
2472       fields->f_disp10 = value;
2473       break;
2474     case FR30_OPERAND_S10 :
2475       fields->f_s10 = value;
2476       break;
2477     case FR30_OPERAND_U10 :
2478       fields->f_u10 = value;
2479       break;
2480     case FR30_OPERAND_I32 :
2481       fields->f_i32 = value;
2482       break;
2483     case FR30_OPERAND_DIR8 :
2484       fields->f_dir8 = value;
2485       break;
2486     case FR30_OPERAND_DIR9 :
2487       fields->f_dir9 = value;
2488       break;
2489     case FR30_OPERAND_DIR10 :
2490       fields->f_dir10 = value;
2491       break;
2492     case FR30_OPERAND_LABEL9 :
2493       fields->f_rel9 = value;
2494       break;
2495     case FR30_OPERAND_LABEL12 :
2496       fields->f_rel12 = value;
2497       break;
2498     case FR30_OPERAND_CC :
2499       fields->f_cc = value;
2500       break;
2501
2502     default :
2503       /* xgettext:c-format */
2504       fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
2505                        opindex);
2506       abort ();
2507   }
2508 }
2509
2510 void
2511 fr30_cgen_set_vma_operand (opindex, fields, value)
2512      int opindex;
2513      CGEN_FIELDS * fields;
2514      bfd_vma value;
2515 {
2516   switch (opindex)
2517     {
2518     case FR30_OPERAND_RI :
2519       fields->f_Ri = value;
2520       break;
2521     case FR30_OPERAND_RJ :
2522       fields->f_Rj = value;
2523       break;
2524     case FR30_OPERAND_RS1 :
2525       fields->f_Rs1 = value;
2526       break;
2527     case FR30_OPERAND_RS2 :
2528       fields->f_Rs2 = value;
2529       break;
2530     case FR30_OPERAND_R13 :
2531       fields->f_nil = value;
2532       break;
2533     case FR30_OPERAND_R14 :
2534       fields->f_nil = value;
2535       break;
2536     case FR30_OPERAND_R15 :
2537       fields->f_nil = value;
2538       break;
2539     case FR30_OPERAND_PS :
2540       fields->f_nil = value;
2541       break;
2542     case FR30_OPERAND_U4 :
2543       fields->f_u4 = value;
2544       break;
2545     case FR30_OPERAND_M4 :
2546       fields->f_m4 = value;
2547       break;
2548     case FR30_OPERAND_U8 :
2549       fields->f_u8 = value;
2550       break;
2551     case FR30_OPERAND_I8 :
2552       fields->f_i8 = value;
2553       break;
2554     case FR30_OPERAND_UDISP6 :
2555       fields->f_udisp6 = value;
2556       break;
2557     case FR30_OPERAND_DISP8 :
2558       fields->f_disp8 = value;
2559       break;
2560     case FR30_OPERAND_DISP9 :
2561       fields->f_disp9 = value;
2562       break;
2563     case FR30_OPERAND_DISP10 :
2564       fields->f_disp10 = value;
2565       break;
2566     case FR30_OPERAND_S10 :
2567       fields->f_s10 = value;
2568       break;
2569     case FR30_OPERAND_U10 :
2570       fields->f_u10 = value;
2571       break;
2572     case FR30_OPERAND_I32 :
2573       fields->f_i32 = value;
2574       break;
2575     case FR30_OPERAND_DIR8 :
2576       fields->f_dir8 = value;
2577       break;
2578     case FR30_OPERAND_DIR9 :
2579       fields->f_dir9 = value;
2580       break;
2581     case FR30_OPERAND_DIR10 :
2582       fields->f_dir10 = value;
2583       break;
2584     case FR30_OPERAND_LABEL9 :
2585       fields->f_rel9 = value;
2586       break;
2587     case FR30_OPERAND_LABEL12 :
2588       fields->f_rel12 = value;
2589       break;
2590     case FR30_OPERAND_CC :
2591       fields->f_cc = value;
2592       break;
2593
2594     default :
2595       /* xgettext:c-format */
2596       fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
2597                        opindex);
2598       abort ();
2599   }
2600 }
2601