opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_EX_Vex (int, int);
  92 static void OP_EX_VexW (int, int);
  93 static void OP_EX_VexImmW (int, int);
  94 static void OP_XMM_Vex (int, int);
  95 static void OP_XMM_VexW (int, int);
  96 static void OP_Rounding (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void SEP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128 static void MOVSXD_Fixup (int, int);
 129
 130 static void OP_Mask (int, int);
 131
 132 struct dis_private {
 133   /* Points to first byte not fetched.  */
 134   bfd_byte *max_fetched;
 135   bfd_byte the_buffer[MAX_MNEM_SIZE];
 136   bfd_vma insn_start;
 137   int orig_sizeflag;
 138   OPCODES_SIGJMP_BUF bailout;
 139 };
 140
 141 enum address_mode
 142 {
 143   mode_16bit,
 144   mode_32bit,
 145   mode_64bit
 146 };
 147
 148 enum address_mode address_mode;
 149
 150 /* Flags for the prefixes for the current instruction.  See below.  */
 151 static int prefixes;
 152
 153 /* REX prefix the current instruction.  See below.  */
 154 static int rex;
 155 /* Bits of REX we've already used.  */
 156 static int rex_used;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mv_bnd { OP_M, v_bndmk_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gva { OP_G, va_mode }
 285 #define Gw { OP_G, w_mode }
 286 #define Rd { OP_R, d_mode }
 287 #define Rdq { OP_R, dq_mode }
 288 #define Rm { OP_R, m_mode }
 289 #define Ib { OP_I, b_mode }
 290 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 292 #define Iv { OP_I, v_mode }
 293 #define sIv { OP_sI, v_mode }
 294 #define Iv64 { OP_I64, v_mode }
 295 #define Id { OP_I, d_mode }
 296 #define Iw { OP_I, w_mode }
 297 #define I1 { OP_I, const_1_mode }
 298 #define Jb { OP_J, b_mode }
 299 #define Jv { OP_J, v_mode }
 300 #define Jdqw { OP_J, dqw_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXq { OP_EX, q_mode }
 389 #define EXqS { OP_EX, q_swap_mode }
 390 #define EXx { OP_EX, x_mode }
 391 #define EXxS { OP_EX, x_swap_mode }
 392 #define EXxmm { OP_EX, xmm_mode }
 393 #define EXymm { OP_EX, ymm_mode }
 394 #define EXxmmq { OP_EX, xmmq_mode }
 395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 398 #define EXxmm_md { OP_EX, xmm_md_mode }
 399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 400 #define EXxmmdw { OP_EX, xmmdw_mode }
 401 #define EXxmmqd { OP_EX, xmmqd_mode }
 402 #define EXymmq { OP_EX, ymmq_mode }
 403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 406 #define MS { OP_MS, v_mode }
 407 #define XS { OP_XS, v_mode }
 408 #define EMCq { OP_EMC, q_mode }
 409 #define MXC { OP_MXC, 0 }
 410 #define OPSUF { OP_3DNowSuffix, 0 }
 411 #define SEP { SEP_Fixup, 0 }
 412 #define CMP { CMP_Fixup, 0 }
 413 #define XMM0 { XMM_Fixup, 0 }
 414 #define FXSAVE { FXSAVE_Fixup, 0 }
 415 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 416 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 417
 418 #define Vex { OP_VEX, vex_mode }
 419 #define VexScalar { OP_VEX, vex_scalar_mode }
 420 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 421 #define Vex128 { OP_VEX, vex128_mode }
 422 #define Vex256 { OP_VEX, vex256_mode }
 423 #define VexGdq { OP_VEX, dq_mode }
 424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 425 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 426 #define EXVexW { OP_EX_VexW, x_mode }
 427 #define EXdVexW { OP_EX_VexW, d_mode }
 428 #define EXqVexW { OP_EX_VexW, q_mode }
 429 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 430 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 431 #define XMVexW { OP_XMM_VexW, 0 }
 432 #define XMVexI4 { OP_REG_VexI4, x_mode }
 433 #define PCLMUL { PCLMUL_Fixup, 0 }
 434 #define VCMP { VCMP_Fixup, 0 }
 435 #define VPCMP { VPCMP_Fixup, 0 }
 436 #define VPCOM { VPCOM_Fixup, 0 }
 437
 438 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 439 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 440 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 441
 442 #define XMask { OP_Mask, mask_mode }
 443 #define MaskG { OP_G, mask_mode }
 444 #define MaskE { OP_E, mask_mode }
 445 #define MaskBDE { OP_E, mask_bd_mode }
 446 #define MaskR { OP_R, mask_mode }
 447 #define MaskVex { OP_VEX, mask_mode }
 448
 449 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 450 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 451 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 452 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 453
 454 /* Used handle "rep" prefix for string instructions.  */
 455 #define Xbr { REP_Fixup, eSI_reg }
 456 #define Xvr { REP_Fixup, eSI_reg }
 457 #define Ybr { REP_Fixup, eDI_reg }
 458 #define Yvr { REP_Fixup, eDI_reg }
 459 #define Yzr { REP_Fixup, eDI_reg }
 460 #define indirDXr { REP_Fixup, indir_dx_reg }
 461 #define ALr { REP_Fixup, al_reg }
 462 #define eAXr { REP_Fixup, eAX_reg }
 463
 464 /* Used handle HLE prefix for lockable instructions.  */
 465 #define Ebh1 { HLE_Fixup1, b_mode }
 466 #define Evh1 { HLE_Fixup1, v_mode }
 467 #define Ebh2 { HLE_Fixup2, b_mode }
 468 #define Evh2 { HLE_Fixup2, v_mode }
 469 #define Ebh3 { HLE_Fixup3, b_mode }
 470 #define Evh3 { HLE_Fixup3, v_mode }
 471
 472 #define BND { BND_Fixup, 0 }
 473 #define NOTRACK { NOTRACK_Fixup, 0 }
 474
 475 #define cond_jump_flag { NULL, cond_jump_mode }
 476 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 477
 478 /* bits in sizeflag */
 479 #define SUFFIX_ALWAYS 4
 480 #define AFLAG 2
 481 #define DFLAG 1
 482
 483 enum
 484 {
 485   /* byte operand */
 486   b_mode = 1,
 487   /* byte operand with operand swapped */
 488   b_swap_mode,
 489   /* byte operand, sign extend like 'T' suffix */
 490   b_T_mode,
 491   /* operand size depends on prefixes */
 492   v_mode,
 493   /* operand size depends on prefixes with operand swapped */
 494   v_swap_mode,
 495   /* operand size depends on address prefix */
 496   va_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* 16-byte XMM, word, double word or quad word operand.  */
 536   xmmdw_mode,
 537   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 538   xmmqd_mode,
 539   /* 32-byte YMM operand */
 540   ymm_mode,
 541   /* quad word, ymmword or zmmword memory operand.  */
 542   ymmq_mode,
 543   /* 32-byte YMM or 16-byte word operand */
 544   ymmxmm_mode,
 545   /* d_mode in 32bit, q_mode in 64bit mode.  */
 546   m_mode,
 547   /* pair of v_mode operands */
 548   a_mode,
 549   cond_jump_mode,
 550   loop_jcxz_mode,
 551   movsxd_mode,
 552   v_bnd_mode,
 553   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 554   v_bndmk_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode, displacements like
 558      v_mode without considering Intel64 ISA.  */
 559   dqw_mode,
 560   /* bounds operand */
 561   bnd_mode,
 562   /* bounds operand with operand swapped */
 563   bnd_swap_mode,
 564   /* 4- or 6-byte pointer operand */
 565   f_mode,
 566   const_1_mode,
 567   /* v_mode for indirect branch opcodes.  */
 568   indir_v_mode,
 569   /* v_mode for stack-related opcodes.  */
 570   stack_v_mode,
 571   /* non-quad operand size depends on prefixes */
 572   z_mode,
 573   /* 16-byte operand */
 574   o_mode,
 575   /* registers like dq_mode, memory like b_mode.  */
 576   dqb_mode,
 577   /* registers like d_mode, memory like b_mode.  */
 578   db_mode,
 579   /* registers like d_mode, memory like w_mode.  */
 580   dw_mode,
 581   /* registers like dq_mode, memory like d_mode.  */
 582   dqd_mode,
 583   /* normal vex mode */
 584   vex_mode,
 585   /* 128bit vex mode */
 586   vex128_mode,
 587   /* 256bit vex mode */
 588   vex256_mode,
 589
 590   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 591   vex_vsib_d_w_dq_mode,
 592   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 593   vex_vsib_d_w_d_mode,
 594   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 595   vex_vsib_q_w_dq_mode,
 596   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 597   vex_vsib_q_w_d_mode,
 598
 599   /* scalar, ignore vector length.  */
 600   scalar_mode,
 601   /* like b_mode, ignore vector length.  */
 602   b_scalar_mode,
 603   /* like w_mode, ignore vector length.  */
 604   w_scalar_mode,
 605   /* like d_swap_mode, ignore vector length.  */
 606   d_scalar_swap_mode,
 607   /* like q_swap_mode, ignore vector length.  */
 608   q_scalar_swap_mode,
 609   /* like vex_mode, ignore vector length.  */
 610   vex_scalar_mode,
 611   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 612   vex_scalar_w_dq_mode,
 613
 614   /* Static rounding.  */
 615   evex_rounding_mode,
 616   /* Static rounding, 64-bit mode only.  */
 617   evex_rounding_64_mode,
 618   /* Supress all exceptions.  */
 619   evex_sae_mode,
 620
 621   /* Mask register operand.  */
 622   mask_mode,
 623   /* Mask register operand.  */
 624   mask_bd_mode,
 625
 626   es_reg,
 627   cs_reg,
 628   ss_reg,
 629   ds_reg,
 630   fs_reg,
 631   gs_reg,
 632
 633   eAX_reg,
 634   eCX_reg,
 635   eDX_reg,
 636   eBX_reg,
 637   eSP_reg,
 638   eBP_reg,
 639   eSI_reg,
 640   eDI_reg,
 641
 642   al_reg,
 643   cl_reg,
 644   dl_reg,
 645   bl_reg,
 646   ah_reg,
 647   ch_reg,
 648   dh_reg,
 649   bh_reg,
 650
 651   ax_reg,
 652   cx_reg,
 653   dx_reg,
 654   bx_reg,
 655   sp_reg,
 656   bp_reg,
 657   si_reg,
 658   di_reg,
 659
 660   rAX_reg,
 661   rCX_reg,
 662   rDX_reg,
 663   rBX_reg,
 664   rSP_reg,
 665   rBP_reg,
 666   rSI_reg,
 667   rDI_reg,
 668
 669   z_mode_ax_reg,
 670   indir_dx_reg
 671 };
 672
 673 enum
 674 {
 675   FLOATCODE = 1,
 676   USE_REG_TABLE,
 677   USE_MOD_TABLE,
 678   USE_RM_TABLE,
 679   USE_PREFIX_TABLE,
 680   USE_X86_64_TABLE,
 681   USE_3BYTE_TABLE,
 682   USE_XOP_8F_TABLE,
 683   USE_VEX_C4_TABLE,
 684   USE_VEX_C5_TABLE,
 685   USE_VEX_LEN_TABLE,
 686   USE_VEX_W_TABLE,
 687   USE_EVEX_TABLE,
 688   USE_EVEX_LEN_TABLE
 689 };
 690
 691 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 692
 693 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 694 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 695 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 696 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 697 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 698 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 699 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 700 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 701 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 702 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 703 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 704 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 705 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 706 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 707 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 708 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 709
 710 enum
 711 {
 712   REG_80 = 0,
 713   REG_81,
 714   REG_83,
 715   REG_8F,
 716   REG_C0,
 717   REG_C1,
 718   REG_C6,
 719   REG_C7,
 720   REG_D0,
 721   REG_D1,
 722   REG_D2,
 723   REG_D3,
 724   REG_F6,
 725   REG_F7,
 726   REG_FE,
 727   REG_FF,
 728   REG_0F00,
 729   REG_0F01,
 730   REG_0F0D,
 731   REG_0F18,
 732   REG_0F1C_P_0_MOD_0,
 733   REG_0F1E_P_1_MOD_3,
 734   REG_0F71,
 735   REG_0F72,
 736   REG_0F73,
 737   REG_0FA6,
 738   REG_0FA7,
 739   REG_0FAE,
 740   REG_0FBA,
 741   REG_0FC7,
 742   REG_VEX_0F71,
 743   REG_VEX_0F72,
 744   REG_VEX_0F73,
 745   REG_VEX_0FAE,
 746   REG_VEX_0F38F3,
 747   REG_XOP_LWPCB,
 748   REG_XOP_LWP,
 749   REG_XOP_TBM_01,
 750   REG_XOP_TBM_02,
 751
 752   REG_EVEX_0F71,
 753   REG_EVEX_0F72,
 754   REG_EVEX_0F73,
 755   REG_EVEX_0F38C6,
 756   REG_EVEX_0F38C7
 757 };
 758
 759 enum
 760 {
 761   MOD_8D = 0,
 762   MOD_C6_REG_7,
 763   MOD_C7_REG_7,
 764   MOD_FF_REG_3,
 765   MOD_FF_REG_5,
 766   MOD_0F01_REG_0,
 767   MOD_0F01_REG_1,
 768   MOD_0F01_REG_2,
 769   MOD_0F01_REG_3,
 770   MOD_0F01_REG_5,
 771   MOD_0F01_REG_7,
 772   MOD_0F12_PREFIX_0,
 773   MOD_0F12_PREFIX_2,
 774   MOD_0F13,
 775   MOD_0F16_PREFIX_0,
 776   MOD_0F16_PREFIX_2,
 777   MOD_0F17,
 778   MOD_0F18_REG_0,
 779   MOD_0F18_REG_1,
 780   MOD_0F18_REG_2,
 781   MOD_0F18_REG_3,
 782   MOD_0F18_REG_4,
 783   MOD_0F18_REG_5,
 784   MOD_0F18_REG_6,
 785   MOD_0F18_REG_7,
 786   MOD_0F1A_PREFIX_0,
 787   MOD_0F1B_PREFIX_0,
 788   MOD_0F1B_PREFIX_1,
 789   MOD_0F1C_PREFIX_0,
 790   MOD_0F1E_PREFIX_1,
 791   MOD_0F24,
 792   MOD_0F26,
 793   MOD_0F2B_PREFIX_0,
 794   MOD_0F2B_PREFIX_1,
 795   MOD_0F2B_PREFIX_2,
 796   MOD_0F2B_PREFIX_3,
 797   MOD_0F50,
 798   MOD_0F71_REG_2,
 799   MOD_0F71_REG_4,
 800   MOD_0F71_REG_6,
 801   MOD_0F72_REG_2,
 802   MOD_0F72_REG_4,
 803   MOD_0F72_REG_6,
 804   MOD_0F73_REG_2,
 805   MOD_0F73_REG_3,
 806   MOD_0F73_REG_6,
 807   MOD_0F73_REG_7,
 808   MOD_0FAE_REG_0,
 809   MOD_0FAE_REG_1,
 810   MOD_0FAE_REG_2,
 811   MOD_0FAE_REG_3,
 812   MOD_0FAE_REG_4,
 813   MOD_0FAE_REG_5,
 814   MOD_0FAE_REG_6,
 815   MOD_0FAE_REG_7,
 816   MOD_0FB2,
 817   MOD_0FB4,
 818   MOD_0FB5,
 819   MOD_0FC3,
 820   MOD_0FC7_REG_3,
 821   MOD_0FC7_REG_4,
 822   MOD_0FC7_REG_5,
 823   MOD_0FC7_REG_6,
 824   MOD_0FC7_REG_7,
 825   MOD_0FD7,
 826   MOD_0FE7_PREFIX_2,
 827   MOD_0FF0_PREFIX_3,
 828   MOD_0F382A_PREFIX_2,
 829   MOD_0F38F5_PREFIX_2,
 830   MOD_0F38F6_PREFIX_0,
 831   MOD_0F38F8_PREFIX_1,
 832   MOD_0F38F8_PREFIX_2,
 833   MOD_0F38F8_PREFIX_3,
 834   MOD_0F38F9_PREFIX_0,
 835   MOD_62_32BIT,
 836   MOD_C4_32BIT,
 837   MOD_C5_32BIT,
 838   MOD_VEX_0F12_PREFIX_0,
 839   MOD_VEX_0F12_PREFIX_2,
 840   MOD_VEX_0F13,
 841   MOD_VEX_0F16_PREFIX_0,
 842   MOD_VEX_0F16_PREFIX_2,
 843   MOD_VEX_0F17,
 844   MOD_VEX_0F2B,
 845   MOD_VEX_W_0_0F41_P_0_LEN_1,
 846   MOD_VEX_W_1_0F41_P_0_LEN_1,
 847   MOD_VEX_W_0_0F41_P_2_LEN_1,
 848   MOD_VEX_W_1_0F41_P_2_LEN_1,
 849   MOD_VEX_W_0_0F42_P_0_LEN_1,
 850   MOD_VEX_W_1_0F42_P_0_LEN_1,
 851   MOD_VEX_W_0_0F42_P_2_LEN_1,
 852   MOD_VEX_W_1_0F42_P_2_LEN_1,
 853   MOD_VEX_W_0_0F44_P_0_LEN_1,
 854   MOD_VEX_W_1_0F44_P_0_LEN_1,
 855   MOD_VEX_W_0_0F44_P_2_LEN_1,
 856   MOD_VEX_W_1_0F44_P_2_LEN_1,
 857   MOD_VEX_W_0_0F45_P_0_LEN_1,
 858   MOD_VEX_W_1_0F45_P_0_LEN_1,
 859   MOD_VEX_W_0_0F45_P_2_LEN_1,
 860   MOD_VEX_W_1_0F45_P_2_LEN_1,
 861   MOD_VEX_W_0_0F46_P_0_LEN_1,
 862   MOD_VEX_W_1_0F46_P_0_LEN_1,
 863   MOD_VEX_W_0_0F46_P_2_LEN_1,
 864   MOD_VEX_W_1_0F46_P_2_LEN_1,
 865   MOD_VEX_W_0_0F47_P_0_LEN_1,
 866   MOD_VEX_W_1_0F47_P_0_LEN_1,
 867   MOD_VEX_W_0_0F47_P_2_LEN_1,
 868   MOD_VEX_W_1_0F47_P_2_LEN_1,
 869   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 870   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 871   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 872   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 873   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 874   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 875   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 876   MOD_VEX_0F50,
 877   MOD_VEX_0F71_REG_2,
 878   MOD_VEX_0F71_REG_4,
 879   MOD_VEX_0F71_REG_6,
 880   MOD_VEX_0F72_REG_2,
 881   MOD_VEX_0F72_REG_4,
 882   MOD_VEX_0F72_REG_6,
 883   MOD_VEX_0F73_REG_2,
 884   MOD_VEX_0F73_REG_3,
 885   MOD_VEX_0F73_REG_6,
 886   MOD_VEX_0F73_REG_7,
 887   MOD_VEX_W_0_0F91_P_0_LEN_0,
 888   MOD_VEX_W_1_0F91_P_0_LEN_0,
 889   MOD_VEX_W_0_0F91_P_2_LEN_0,
 890   MOD_VEX_W_1_0F91_P_2_LEN_0,
 891   MOD_VEX_W_0_0F92_P_0_LEN_0,
 892   MOD_VEX_W_0_0F92_P_2_LEN_0,
 893   MOD_VEX_0F92_P_3_LEN_0,
 894   MOD_VEX_W_0_0F93_P_0_LEN_0,
 895   MOD_VEX_W_0_0F93_P_2_LEN_0,
 896   MOD_VEX_0F93_P_3_LEN_0,
 897   MOD_VEX_W_0_0F98_P_0_LEN_0,
 898   MOD_VEX_W_1_0F98_P_0_LEN_0,
 899   MOD_VEX_W_0_0F98_P_2_LEN_0,
 900   MOD_VEX_W_1_0F98_P_2_LEN_0,
 901   MOD_VEX_W_0_0F99_P_0_LEN_0,
 902   MOD_VEX_W_1_0F99_P_0_LEN_0,
 903   MOD_VEX_W_0_0F99_P_2_LEN_0,
 904   MOD_VEX_W_1_0F99_P_2_LEN_0,
 905   MOD_VEX_0FAE_REG_2,
 906   MOD_VEX_0FAE_REG_3,
 907   MOD_VEX_0FD7_PREFIX_2,
 908   MOD_VEX_0FE7_PREFIX_2,
 909   MOD_VEX_0FF0_PREFIX_3,
 910   MOD_VEX_0F381A_PREFIX_2,
 911   MOD_VEX_0F382A_PREFIX_2,
 912   MOD_VEX_0F382C_PREFIX_2,
 913   MOD_VEX_0F382D_PREFIX_2,
 914   MOD_VEX_0F382E_PREFIX_2,
 915   MOD_VEX_0F382F_PREFIX_2,
 916   MOD_VEX_0F385A_PREFIX_2,
 917   MOD_VEX_0F388C_PREFIX_2,
 918   MOD_VEX_0F388E_PREFIX_2,
 919   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 921   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 922   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 923   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 924   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 925   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 926   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 927
 928   MOD_EVEX_0F12_PREFIX_0,
 929   MOD_EVEX_0F12_PREFIX_2,
 930   MOD_EVEX_0F13,
 931   MOD_EVEX_0F16_PREFIX_0,
 932   MOD_EVEX_0F16_PREFIX_2,
 933   MOD_EVEX_0F17,
 934   MOD_EVEX_0F2B,
 935   MOD_EVEX_0F381A_P_2_W_0,
 936   MOD_EVEX_0F381A_P_2_W_1,
 937   MOD_EVEX_0F381B_P_2_W_0,
 938   MOD_EVEX_0F381B_P_2_W_1,
 939   MOD_EVEX_0F385A_P_2_W_0,
 940   MOD_EVEX_0F385A_P_2_W_1,
 941   MOD_EVEX_0F385B_P_2_W_0,
 942   MOD_EVEX_0F385B_P_2_W_1,
 943   MOD_EVEX_0F38C6_REG_1,
 944   MOD_EVEX_0F38C6_REG_2,
 945   MOD_EVEX_0F38C6_REG_5,
 946   MOD_EVEX_0F38C6_REG_6,
 947   MOD_EVEX_0F38C7_REG_1,
 948   MOD_EVEX_0F38C7_REG_2,
 949   MOD_EVEX_0F38C7_REG_5,
 950   MOD_EVEX_0F38C7_REG_6
 951 };
 952
 953 enum
 954 {
 955   RM_C6_REG_7 = 0,
 956   RM_C7_REG_7,
 957   RM_0F01_REG_0,
 958   RM_0F01_REG_1,
 959   RM_0F01_REG_2,
 960   RM_0F01_REG_3,
 961   RM_0F01_REG_5_MOD_3,
 962   RM_0F01_REG_7_MOD_3,
 963   RM_0F1E_P_1_MOD_3_REG_7,
 964   RM_0FAE_REG_6_MOD_3_P_0,
 965   RM_0FAE_REG_7_MOD_3,
 966 };
 967
 968 enum
 969 {
 970   PREFIX_90 = 0,
 971   PREFIX_0F01_REG_3_RM_1,
 972   PREFIX_0F01_REG_5_MOD_0,
 973   PREFIX_0F01_REG_5_MOD_3_RM_0,
 974   PREFIX_0F01_REG_5_MOD_3_RM_1,
 975   PREFIX_0F01_REG_5_MOD_3_RM_2,
 976   PREFIX_0F01_REG_7_MOD_3_RM_2,
 977   PREFIX_0F01_REG_7_MOD_3_RM_3,
 978   PREFIX_0F09,
 979   PREFIX_0F10,
 980   PREFIX_0F11,
 981   PREFIX_0F12,
 982   PREFIX_0F16,
 983   PREFIX_0F1A,
 984   PREFIX_0F1B,
 985   PREFIX_0F1C,
 986   PREFIX_0F1E,
 987   PREFIX_0F2A,
 988   PREFIX_0F2B,
 989   PREFIX_0F2C,
 990   PREFIX_0F2D,
 991   PREFIX_0F2E,
 992   PREFIX_0F2F,
 993   PREFIX_0F51,
 994   PREFIX_0F52,
 995   PREFIX_0F53,
 996   PREFIX_0F58,
 997   PREFIX_0F59,
 998   PREFIX_0F5A,
 999   PREFIX_0F5B,
1000   PREFIX_0F5C,
1001   PREFIX_0F5D,
1002   PREFIX_0F5E,
1003   PREFIX_0F5F,
1004   PREFIX_0F60,
1005   PREFIX_0F61,
1006   PREFIX_0F62,
1007   PREFIX_0F6C,
1008   PREFIX_0F6D,
1009   PREFIX_0F6F,
1010   PREFIX_0F70,
1011   PREFIX_0F73_REG_3,
1012   PREFIX_0F73_REG_7,
1013   PREFIX_0F78,
1014   PREFIX_0F79,
1015   PREFIX_0F7C,
1016   PREFIX_0F7D,
1017   PREFIX_0F7E,
1018   PREFIX_0F7F,
1019   PREFIX_0FAE_REG_0_MOD_3,
1020   PREFIX_0FAE_REG_1_MOD_3,
1021   PREFIX_0FAE_REG_2_MOD_3,
1022   PREFIX_0FAE_REG_3_MOD_3,
1023   PREFIX_0FAE_REG_4_MOD_0,
1024   PREFIX_0FAE_REG_4_MOD_3,
1025   PREFIX_0FAE_REG_5_MOD_0,
1026   PREFIX_0FAE_REG_5_MOD_3,
1027   PREFIX_0FAE_REG_6_MOD_0,
1028   PREFIX_0FAE_REG_6_MOD_3,
1029   PREFIX_0FAE_REG_7_MOD_0,
1030   PREFIX_0FB8,
1031   PREFIX_0FBC,
1032   PREFIX_0FBD,
1033   PREFIX_0FC2,
1034   PREFIX_0FC3_MOD_0,
1035   PREFIX_0FC7_REG_6_MOD_0,
1036   PREFIX_0FC7_REG_6_MOD_3,
1037   PREFIX_0FC7_REG_7_MOD_3,
1038   PREFIX_0FD0,
1039   PREFIX_0FD6,
1040   PREFIX_0FE6,
1041   PREFIX_0FE7,
1042   PREFIX_0FF0,
1043   PREFIX_0FF7,
1044   PREFIX_0F3810,
1045   PREFIX_0F3814,
1046   PREFIX_0F3815,
1047   PREFIX_0F3817,
1048   PREFIX_0F3820,
1049   PREFIX_0F3821,
1050   PREFIX_0F3822,
1051   PREFIX_0F3823,
1052   PREFIX_0F3824,
1053   PREFIX_0F3825,
1054   PREFIX_0F3828,
1055   PREFIX_0F3829,
1056   PREFIX_0F382A,
1057   PREFIX_0F382B,
1058   PREFIX_0F3830,
1059   PREFIX_0F3831,
1060   PREFIX_0F3832,
1061   PREFIX_0F3833,
1062   PREFIX_0F3834,
1063   PREFIX_0F3835,
1064   PREFIX_0F3837,
1065   PREFIX_0F3838,
1066   PREFIX_0F3839,
1067   PREFIX_0F383A,
1068   PREFIX_0F383B,
1069   PREFIX_0F383C,
1070   PREFIX_0F383D,
1071   PREFIX_0F383E,
1072   PREFIX_0F383F,
1073   PREFIX_0F3840,
1074   PREFIX_0F3841,
1075   PREFIX_0F3880,
1076   PREFIX_0F3881,
1077   PREFIX_0F3882,
1078   PREFIX_0F38C8,
1079   PREFIX_0F38C9,
1080   PREFIX_0F38CA,
1081   PREFIX_0F38CB,
1082   PREFIX_0F38CC,
1083   PREFIX_0F38CD,
1084   PREFIX_0F38CF,
1085   PREFIX_0F38DB,
1086   PREFIX_0F38DC,
1087   PREFIX_0F38DD,
1088   PREFIX_0F38DE,
1089   PREFIX_0F38DF,
1090   PREFIX_0F38F0,
1091   PREFIX_0F38F1,
1092   PREFIX_0F38F5,
1093   PREFIX_0F38F6,
1094   PREFIX_0F38F8,
1095   PREFIX_0F38F9,
1096   PREFIX_0F3A08,
1097   PREFIX_0F3A09,
1098   PREFIX_0F3A0A,
1099   PREFIX_0F3A0B,
1100   PREFIX_0F3A0C,
1101   PREFIX_0F3A0D,
1102   PREFIX_0F3A0E,
1103   PREFIX_0F3A14,
1104   PREFIX_0F3A15,
1105   PREFIX_0F3A16,
1106   PREFIX_0F3A17,
1107   PREFIX_0F3A20,
1108   PREFIX_0F3A21,
1109   PREFIX_0F3A22,
1110   PREFIX_0F3A40,
1111   PREFIX_0F3A41,
1112   PREFIX_0F3A42,
1113   PREFIX_0F3A44,
1114   PREFIX_0F3A60,
1115   PREFIX_0F3A61,
1116   PREFIX_0F3A62,
1117   PREFIX_0F3A63,
1118   PREFIX_0F3ACC,
1119   PREFIX_0F3ACE,
1120   PREFIX_0F3ACF,
1121   PREFIX_0F3ADF,
1122   PREFIX_VEX_0F10,
1123   PREFIX_VEX_0F11,
1124   PREFIX_VEX_0F12,
1125   PREFIX_VEX_0F16,
1126   PREFIX_VEX_0F2A,
1127   PREFIX_VEX_0F2C,
1128   PREFIX_VEX_0F2D,
1129   PREFIX_VEX_0F2E,
1130   PREFIX_VEX_0F2F,
1131   PREFIX_VEX_0F41,
1132   PREFIX_VEX_0F42,
1133   PREFIX_VEX_0F44,
1134   PREFIX_VEX_0F45,
1135   PREFIX_VEX_0F46,
1136   PREFIX_VEX_0F47,
1137   PREFIX_VEX_0F4A,
1138   PREFIX_VEX_0F4B,
1139   PREFIX_VEX_0F51,
1140   PREFIX_VEX_0F52,
1141   PREFIX_VEX_0F53,
1142   PREFIX_VEX_0F58,
1143   PREFIX_VEX_0F59,
1144   PREFIX_VEX_0F5A,
1145   PREFIX_VEX_0F5B,
1146   PREFIX_VEX_0F5C,
1147   PREFIX_VEX_0F5D,
1148   PREFIX_VEX_0F5E,
1149   PREFIX_VEX_0F5F,
1150   PREFIX_VEX_0F60,
1151   PREFIX_VEX_0F61,
1152   PREFIX_VEX_0F62,
1153   PREFIX_VEX_0F63,
1154   PREFIX_VEX_0F64,
1155   PREFIX_VEX_0F65,
1156   PREFIX_VEX_0F66,
1157   PREFIX_VEX_0F67,
1158   PREFIX_VEX_0F68,
1159   PREFIX_VEX_0F69,
1160   PREFIX_VEX_0F6A,
1161   PREFIX_VEX_0F6B,
1162   PREFIX_VEX_0F6C,
1163   PREFIX_VEX_0F6D,
1164   PREFIX_VEX_0F6E,
1165   PREFIX_VEX_0F6F,
1166   PREFIX_VEX_0F70,
1167   PREFIX_VEX_0F71_REG_2,
1168   PREFIX_VEX_0F71_REG_4,
1169   PREFIX_VEX_0F71_REG_6,
1170   PREFIX_VEX_0F72_REG_2,
1171   PREFIX_VEX_0F72_REG_4,
1172   PREFIX_VEX_0F72_REG_6,
1173   PREFIX_VEX_0F73_REG_2,
1174   PREFIX_VEX_0F73_REG_3,
1175   PREFIX_VEX_0F73_REG_6,
1176   PREFIX_VEX_0F73_REG_7,
1177   PREFIX_VEX_0F74,
1178   PREFIX_VEX_0F75,
1179   PREFIX_VEX_0F76,
1180   PREFIX_VEX_0F77,
1181   PREFIX_VEX_0F7C,
1182   PREFIX_VEX_0F7D,
1183   PREFIX_VEX_0F7E,
1184   PREFIX_VEX_0F7F,
1185   PREFIX_VEX_0F90,
1186   PREFIX_VEX_0F91,
1187   PREFIX_VEX_0F92,
1188   PREFIX_VEX_0F93,
1189   PREFIX_VEX_0F98,
1190   PREFIX_VEX_0F99,
1191   PREFIX_VEX_0FC2,
1192   PREFIX_VEX_0FC4,
1193   PREFIX_VEX_0FC5,
1194   PREFIX_VEX_0FD0,
1195   PREFIX_VEX_0FD1,
1196   PREFIX_VEX_0FD2,
1197   PREFIX_VEX_0FD3,
1198   PREFIX_VEX_0FD4,
1199   PREFIX_VEX_0FD5,
1200   PREFIX_VEX_0FD6,
1201   PREFIX_VEX_0FD7,
1202   PREFIX_VEX_0FD8,
1203   PREFIX_VEX_0FD9,
1204   PREFIX_VEX_0FDA,
1205   PREFIX_VEX_0FDB,
1206   PREFIX_VEX_0FDC,
1207   PREFIX_VEX_0FDD,
1208   PREFIX_VEX_0FDE,
1209   PREFIX_VEX_0FDF,
1210   PREFIX_VEX_0FE0,
1211   PREFIX_VEX_0FE1,
1212   PREFIX_VEX_0FE2,
1213   PREFIX_VEX_0FE3,
1214   PREFIX_VEX_0FE4,
1215   PREFIX_VEX_0FE5,
1216   PREFIX_VEX_0FE6,
1217   PREFIX_VEX_0FE7,
1218   PREFIX_VEX_0FE8,
1219   PREFIX_VEX_0FE9,
1220   PREFIX_VEX_0FEA,
1221   PREFIX_VEX_0FEB,
1222   PREFIX_VEX_0FEC,
1223   PREFIX_VEX_0FED,
1224   PREFIX_VEX_0FEE,
1225   PREFIX_VEX_0FEF,
1226   PREFIX_VEX_0FF0,
1227   PREFIX_VEX_0FF1,
1228   PREFIX_VEX_0FF2,
1229   PREFIX_VEX_0FF3,
1230   PREFIX_VEX_0FF4,
1231   PREFIX_VEX_0FF5,
1232   PREFIX_VEX_0FF6,
1233   PREFIX_VEX_0FF7,
1234   PREFIX_VEX_0FF8,
1235   PREFIX_VEX_0FF9,
1236   PREFIX_VEX_0FFA,
1237   PREFIX_VEX_0FFB,
1238   PREFIX_VEX_0FFC,
1239   PREFIX_VEX_0FFD,
1240   PREFIX_VEX_0FFE,
1241   PREFIX_VEX_0F3800,
1242   PREFIX_VEX_0F3801,
1243   PREFIX_VEX_0F3802,
1244   PREFIX_VEX_0F3803,
1245   PREFIX_VEX_0F3804,
1246   PREFIX_VEX_0F3805,
1247   PREFIX_VEX_0F3806,
1248   PREFIX_VEX_0F3807,
1249   PREFIX_VEX_0F3808,
1250   PREFIX_VEX_0F3809,
1251   PREFIX_VEX_0F380A,
1252   PREFIX_VEX_0F380B,
1253   PREFIX_VEX_0F380C,
1254   PREFIX_VEX_0F380D,
1255   PREFIX_VEX_0F380E,
1256   PREFIX_VEX_0F380F,
1257   PREFIX_VEX_0F3813,
1258   PREFIX_VEX_0F3816,
1259   PREFIX_VEX_0F3817,
1260   PREFIX_VEX_0F3818,
1261   PREFIX_VEX_0F3819,
1262   PREFIX_VEX_0F381A,
1263   PREFIX_VEX_0F381C,
1264   PREFIX_VEX_0F381D,
1265   PREFIX_VEX_0F381E,
1266   PREFIX_VEX_0F3820,
1267   PREFIX_VEX_0F3821,
1268   PREFIX_VEX_0F3822,
1269   PREFIX_VEX_0F3823,
1270   PREFIX_VEX_0F3824,
1271   PREFIX_VEX_0F3825,
1272   PREFIX_VEX_0F3828,
1273   PREFIX_VEX_0F3829,
1274   PREFIX_VEX_0F382A,
1275   PREFIX_VEX_0F382B,
1276   PREFIX_VEX_0F382C,
1277   PREFIX_VEX_0F382D,
1278   PREFIX_VEX_0F382E,
1279   PREFIX_VEX_0F382F,
1280   PREFIX_VEX_0F3830,
1281   PREFIX_VEX_0F3831,
1282   PREFIX_VEX_0F3832,
1283   PREFIX_VEX_0F3833,
1284   PREFIX_VEX_0F3834,
1285   PREFIX_VEX_0F3835,
1286   PREFIX_VEX_0F3836,
1287   PREFIX_VEX_0F3837,
1288   PREFIX_VEX_0F3838,
1289   PREFIX_VEX_0F3839,
1290   PREFIX_VEX_0F383A,
1291   PREFIX_VEX_0F383B,
1292   PREFIX_VEX_0F383C,
1293   PREFIX_VEX_0F383D,
1294   PREFIX_VEX_0F383E,
1295   PREFIX_VEX_0F383F,
1296   PREFIX_VEX_0F3840,
1297   PREFIX_VEX_0F3841,
1298   PREFIX_VEX_0F3845,
1299   PREFIX_VEX_0F3846,
1300   PREFIX_VEX_0F3847,
1301   PREFIX_VEX_0F3858,
1302   PREFIX_VEX_0F3859,
1303   PREFIX_VEX_0F385A,
1304   PREFIX_VEX_0F3878,
1305   PREFIX_VEX_0F3879,
1306   PREFIX_VEX_0F388C,
1307   PREFIX_VEX_0F388E,
1308   PREFIX_VEX_0F3890,
1309   PREFIX_VEX_0F3891,
1310   PREFIX_VEX_0F3892,
1311   PREFIX_VEX_0F3893,
1312   PREFIX_VEX_0F3896,
1313   PREFIX_VEX_0F3897,
1314   PREFIX_VEX_0F3898,
1315   PREFIX_VEX_0F3899,
1316   PREFIX_VEX_0F389A,
1317   PREFIX_VEX_0F389B,
1318   PREFIX_VEX_0F389C,
1319   PREFIX_VEX_0F389D,
1320   PREFIX_VEX_0F389E,
1321   PREFIX_VEX_0F389F,
1322   PREFIX_VEX_0F38A6,
1323   PREFIX_VEX_0F38A7,
1324   PREFIX_VEX_0F38A8,
1325   PREFIX_VEX_0F38A9,
1326   PREFIX_VEX_0F38AA,
1327   PREFIX_VEX_0F38AB,
1328   PREFIX_VEX_0F38AC,
1329   PREFIX_VEX_0F38AD,
1330   PREFIX_VEX_0F38AE,
1331   PREFIX_VEX_0F38AF,
1332   PREFIX_VEX_0F38B6,
1333   PREFIX_VEX_0F38B7,
1334   PREFIX_VEX_0F38B8,
1335   PREFIX_VEX_0F38B9,
1336   PREFIX_VEX_0F38BA,
1337   PREFIX_VEX_0F38BB,
1338   PREFIX_VEX_0F38BC,
1339   PREFIX_VEX_0F38BD,
1340   PREFIX_VEX_0F38BE,
1341   PREFIX_VEX_0F38BF,
1342   PREFIX_VEX_0F38CF,
1343   PREFIX_VEX_0F38DB,
1344   PREFIX_VEX_0F38DC,
1345   PREFIX_VEX_0F38DD,
1346   PREFIX_VEX_0F38DE,
1347   PREFIX_VEX_0F38DF,
1348   PREFIX_VEX_0F38F2,
1349   PREFIX_VEX_0F38F3_REG_1,
1350   PREFIX_VEX_0F38F3_REG_2,
1351   PREFIX_VEX_0F38F3_REG_3,
1352   PREFIX_VEX_0F38F5,
1353   PREFIX_VEX_0F38F6,
1354   PREFIX_VEX_0F38F7,
1355   PREFIX_VEX_0F3A00,
1356   PREFIX_VEX_0F3A01,
1357   PREFIX_VEX_0F3A02,
1358   PREFIX_VEX_0F3A04,
1359   PREFIX_VEX_0F3A05,
1360   PREFIX_VEX_0F3A06,
1361   PREFIX_VEX_0F3A08,
1362   PREFIX_VEX_0F3A09,
1363   PREFIX_VEX_0F3A0A,
1364   PREFIX_VEX_0F3A0B,
1365   PREFIX_VEX_0F3A0C,
1366   PREFIX_VEX_0F3A0D,
1367   PREFIX_VEX_0F3A0E,
1368   PREFIX_VEX_0F3A0F,
1369   PREFIX_VEX_0F3A14,
1370   PREFIX_VEX_0F3A15,
1371   PREFIX_VEX_0F3A16,
1372   PREFIX_VEX_0F3A17,
1373   PREFIX_VEX_0F3A18,
1374   PREFIX_VEX_0F3A19,
1375   PREFIX_VEX_0F3A1D,
1376   PREFIX_VEX_0F3A20,
1377   PREFIX_VEX_0F3A21,
1378   PREFIX_VEX_0F3A22,
1379   PREFIX_VEX_0F3A30,
1380   PREFIX_VEX_0F3A31,
1381   PREFIX_VEX_0F3A32,
1382   PREFIX_VEX_0F3A33,
1383   PREFIX_VEX_0F3A38,
1384   PREFIX_VEX_0F3A39,
1385   PREFIX_VEX_0F3A40,
1386   PREFIX_VEX_0F3A41,
1387   PREFIX_VEX_0F3A42,
1388   PREFIX_VEX_0F3A44,
1389   PREFIX_VEX_0F3A46,
1390   PREFIX_VEX_0F3A48,
1391   PREFIX_VEX_0F3A49,
1392   PREFIX_VEX_0F3A4A,
1393   PREFIX_VEX_0F3A4B,
1394   PREFIX_VEX_0F3A4C,
1395   PREFIX_VEX_0F3A5C,
1396   PREFIX_VEX_0F3A5D,
1397   PREFIX_VEX_0F3A5E,
1398   PREFIX_VEX_0F3A5F,
1399   PREFIX_VEX_0F3A60,
1400   PREFIX_VEX_0F3A61,
1401   PREFIX_VEX_0F3A62,
1402   PREFIX_VEX_0F3A63,
1403   PREFIX_VEX_0F3A68,
1404   PREFIX_VEX_0F3A69,
1405   PREFIX_VEX_0F3A6A,
1406   PREFIX_VEX_0F3A6B,
1407   PREFIX_VEX_0F3A6C,
1408   PREFIX_VEX_0F3A6D,
1409   PREFIX_VEX_0F3A6E,
1410   PREFIX_VEX_0F3A6F,
1411   PREFIX_VEX_0F3A78,
1412   PREFIX_VEX_0F3A79,
1413   PREFIX_VEX_0F3A7A,
1414   PREFIX_VEX_0F3A7B,
1415   PREFIX_VEX_0F3A7C,
1416   PREFIX_VEX_0F3A7D,
1417   PREFIX_VEX_0F3A7E,
1418   PREFIX_VEX_0F3A7F,
1419   PREFIX_VEX_0F3ACE,
1420   PREFIX_VEX_0F3ACF,
1421   PREFIX_VEX_0F3ADF,
1422   PREFIX_VEX_0F3AF0,
1423
1424   PREFIX_EVEX_0F10,
1425   PREFIX_EVEX_0F11,
1426   PREFIX_EVEX_0F12,
1427   PREFIX_EVEX_0F16,
1428   PREFIX_EVEX_0F2A,
1429   PREFIX_EVEX_0F2C,
1430   PREFIX_EVEX_0F2D,
1431   PREFIX_EVEX_0F2E,
1432   PREFIX_EVEX_0F2F,
1433   PREFIX_EVEX_0F51,
1434   PREFIX_EVEX_0F58,
1435   PREFIX_EVEX_0F59,
1436   PREFIX_EVEX_0F5A,
1437   PREFIX_EVEX_0F5B,
1438   PREFIX_EVEX_0F5C,
1439   PREFIX_EVEX_0F5D,
1440   PREFIX_EVEX_0F5E,
1441   PREFIX_EVEX_0F5F,
1442   PREFIX_EVEX_0F64,
1443   PREFIX_EVEX_0F65,
1444   PREFIX_EVEX_0F66,
1445   PREFIX_EVEX_0F6E,
1446   PREFIX_EVEX_0F6F,
1447   PREFIX_EVEX_0F70,
1448   PREFIX_EVEX_0F71_REG_2,
1449   PREFIX_EVEX_0F71_REG_4,
1450   PREFIX_EVEX_0F71_REG_6,
1451   PREFIX_EVEX_0F72_REG_0,
1452   PREFIX_EVEX_0F72_REG_1,
1453   PREFIX_EVEX_0F72_REG_2,
1454   PREFIX_EVEX_0F72_REG_4,
1455   PREFIX_EVEX_0F72_REG_6,
1456   PREFIX_EVEX_0F73_REG_2,
1457   PREFIX_EVEX_0F73_REG_3,
1458   PREFIX_EVEX_0F73_REG_6,
1459   PREFIX_EVEX_0F73_REG_7,
1460   PREFIX_EVEX_0F74,
1461   PREFIX_EVEX_0F75,
1462   PREFIX_EVEX_0F76,
1463   PREFIX_EVEX_0F78,
1464   PREFIX_EVEX_0F79,
1465   PREFIX_EVEX_0F7A,
1466   PREFIX_EVEX_0F7B,
1467   PREFIX_EVEX_0F7E,
1468   PREFIX_EVEX_0F7F,
1469   PREFIX_EVEX_0FC2,
1470   PREFIX_EVEX_0FC4,
1471   PREFIX_EVEX_0FC5,
1472   PREFIX_EVEX_0FD6,
1473   PREFIX_EVEX_0FDB,
1474   PREFIX_EVEX_0FDF,
1475   PREFIX_EVEX_0FE2,
1476   PREFIX_EVEX_0FE6,
1477   PREFIX_EVEX_0FE7,
1478   PREFIX_EVEX_0FEB,
1479   PREFIX_EVEX_0FEF,
1480   PREFIX_EVEX_0F380D,
1481   PREFIX_EVEX_0F3810,
1482   PREFIX_EVEX_0F3811,
1483   PREFIX_EVEX_0F3812,
1484   PREFIX_EVEX_0F3813,
1485   PREFIX_EVEX_0F3814,
1486   PREFIX_EVEX_0F3815,
1487   PREFIX_EVEX_0F3816,
1488   PREFIX_EVEX_0F3819,
1489   PREFIX_EVEX_0F381A,
1490   PREFIX_EVEX_0F381B,
1491   PREFIX_EVEX_0F381E,
1492   PREFIX_EVEX_0F381F,
1493   PREFIX_EVEX_0F3820,
1494   PREFIX_EVEX_0F3821,
1495   PREFIX_EVEX_0F3822,
1496   PREFIX_EVEX_0F3823,
1497   PREFIX_EVEX_0F3824,
1498   PREFIX_EVEX_0F3825,
1499   PREFIX_EVEX_0F3826,
1500   PREFIX_EVEX_0F3827,
1501   PREFIX_EVEX_0F3828,
1502   PREFIX_EVEX_0F3829,
1503   PREFIX_EVEX_0F382A,
1504   PREFIX_EVEX_0F382C,
1505   PREFIX_EVEX_0F382D,
1506   PREFIX_EVEX_0F3830,
1507   PREFIX_EVEX_0F3831,
1508   PREFIX_EVEX_0F3832,
1509   PREFIX_EVEX_0F3833,
1510   PREFIX_EVEX_0F3834,
1511   PREFIX_EVEX_0F3835,
1512   PREFIX_EVEX_0F3836,
1513   PREFIX_EVEX_0F3837,
1514   PREFIX_EVEX_0F3838,
1515   PREFIX_EVEX_0F3839,
1516   PREFIX_EVEX_0F383A,
1517   PREFIX_EVEX_0F383B,
1518   PREFIX_EVEX_0F383D,
1519   PREFIX_EVEX_0F383F,
1520   PREFIX_EVEX_0F3840,
1521   PREFIX_EVEX_0F3842,
1522   PREFIX_EVEX_0F3843,
1523   PREFIX_EVEX_0F3844,
1524   PREFIX_EVEX_0F3845,
1525   PREFIX_EVEX_0F3846,
1526   PREFIX_EVEX_0F3847,
1527   PREFIX_EVEX_0F384C,
1528   PREFIX_EVEX_0F384D,
1529   PREFIX_EVEX_0F384E,
1530   PREFIX_EVEX_0F384F,
1531   PREFIX_EVEX_0F3850,
1532   PREFIX_EVEX_0F3851,
1533   PREFIX_EVEX_0F3852,
1534   PREFIX_EVEX_0F3853,
1535   PREFIX_EVEX_0F3854,
1536   PREFIX_EVEX_0F3855,
1537   PREFIX_EVEX_0F3859,
1538   PREFIX_EVEX_0F385A,
1539   PREFIX_EVEX_0F385B,
1540   PREFIX_EVEX_0F3862,
1541   PREFIX_EVEX_0F3863,
1542   PREFIX_EVEX_0F3864,
1543   PREFIX_EVEX_0F3865,
1544   PREFIX_EVEX_0F3866,
1545   PREFIX_EVEX_0F3868,
1546   PREFIX_EVEX_0F3870,
1547   PREFIX_EVEX_0F3871,
1548   PREFIX_EVEX_0F3872,
1549   PREFIX_EVEX_0F3873,
1550   PREFIX_EVEX_0F3875,
1551   PREFIX_EVEX_0F3876,
1552   PREFIX_EVEX_0F3877,
1553   PREFIX_EVEX_0F387A,
1554   PREFIX_EVEX_0F387B,
1555   PREFIX_EVEX_0F387C,
1556   PREFIX_EVEX_0F387D,
1557   PREFIX_EVEX_0F387E,
1558   PREFIX_EVEX_0F387F,
1559   PREFIX_EVEX_0F3883,
1560   PREFIX_EVEX_0F3888,
1561   PREFIX_EVEX_0F3889,
1562   PREFIX_EVEX_0F388A,
1563   PREFIX_EVEX_0F388B,
1564   PREFIX_EVEX_0F388D,
1565   PREFIX_EVEX_0F388F,
1566   PREFIX_EVEX_0F3890,
1567   PREFIX_EVEX_0F3891,
1568   PREFIX_EVEX_0F3892,
1569   PREFIX_EVEX_0F3893,
1570   PREFIX_EVEX_0F389A,
1571   PREFIX_EVEX_0F389B,
1572   PREFIX_EVEX_0F38A0,
1573   PREFIX_EVEX_0F38A1,
1574   PREFIX_EVEX_0F38A2,
1575   PREFIX_EVEX_0F38A3,
1576   PREFIX_EVEX_0F38AA,
1577   PREFIX_EVEX_0F38AB,
1578   PREFIX_EVEX_0F38B4,
1579   PREFIX_EVEX_0F38B5,
1580   PREFIX_EVEX_0F38C4,
1581   PREFIX_EVEX_0F38C6_REG_1,
1582   PREFIX_EVEX_0F38C6_REG_2,
1583   PREFIX_EVEX_0F38C6_REG_5,
1584   PREFIX_EVEX_0F38C6_REG_6,
1585   PREFIX_EVEX_0F38C7_REG_1,
1586   PREFIX_EVEX_0F38C7_REG_2,
1587   PREFIX_EVEX_0F38C7_REG_5,
1588   PREFIX_EVEX_0F38C7_REG_6,
1589   PREFIX_EVEX_0F38C8,
1590   PREFIX_EVEX_0F38CA,
1591   PREFIX_EVEX_0F38CB,
1592   PREFIX_EVEX_0F38CC,
1593   PREFIX_EVEX_0F38CD,
1594
1595   PREFIX_EVEX_0F3A00,
1596   PREFIX_EVEX_0F3A01,
1597   PREFIX_EVEX_0F3A03,
1598   PREFIX_EVEX_0F3A05,
1599   PREFIX_EVEX_0F3A08,
1600   PREFIX_EVEX_0F3A09,
1601   PREFIX_EVEX_0F3A0A,
1602   PREFIX_EVEX_0F3A0B,
1603   PREFIX_EVEX_0F3A14,
1604   PREFIX_EVEX_0F3A15,
1605   PREFIX_EVEX_0F3A16,
1606   PREFIX_EVEX_0F3A17,
1607   PREFIX_EVEX_0F3A18,
1608   PREFIX_EVEX_0F3A19,
1609   PREFIX_EVEX_0F3A1A,
1610   PREFIX_EVEX_0F3A1B,
1611   PREFIX_EVEX_0F3A1E,
1612   PREFIX_EVEX_0F3A1F,
1613   PREFIX_EVEX_0F3A20,
1614   PREFIX_EVEX_0F3A21,
1615   PREFIX_EVEX_0F3A22,
1616   PREFIX_EVEX_0F3A23,
1617   PREFIX_EVEX_0F3A25,
1618   PREFIX_EVEX_0F3A26,
1619   PREFIX_EVEX_0F3A27,
1620   PREFIX_EVEX_0F3A38,
1621   PREFIX_EVEX_0F3A39,
1622   PREFIX_EVEX_0F3A3A,
1623   PREFIX_EVEX_0F3A3B,
1624   PREFIX_EVEX_0F3A3E,
1625   PREFIX_EVEX_0F3A3F,
1626   PREFIX_EVEX_0F3A42,
1627   PREFIX_EVEX_0F3A43,
1628   PREFIX_EVEX_0F3A50,
1629   PREFIX_EVEX_0F3A51,
1630   PREFIX_EVEX_0F3A54,
1631   PREFIX_EVEX_0F3A55,
1632   PREFIX_EVEX_0F3A56,
1633   PREFIX_EVEX_0F3A57,
1634   PREFIX_EVEX_0F3A66,
1635   PREFIX_EVEX_0F3A67,
1636   PREFIX_EVEX_0F3A70,
1637   PREFIX_EVEX_0F3A71,
1638   PREFIX_EVEX_0F3A72,
1639   PREFIX_EVEX_0F3A73,
1640 };
1641
1642 enum
1643 {
1644   X86_64_06 = 0,
1645   X86_64_07,
1646   X86_64_0E,
1647   X86_64_16,
1648   X86_64_17,
1649   X86_64_1E,
1650   X86_64_1F,
1651   X86_64_27,
1652   X86_64_2F,
1653   X86_64_37,
1654   X86_64_3F,
1655   X86_64_60,
1656   X86_64_61,
1657   X86_64_62,
1658   X86_64_63,
1659   X86_64_6D,
1660   X86_64_6F,
1661   X86_64_82,
1662   X86_64_9A,
1663   X86_64_C2,
1664   X86_64_C3,
1665   X86_64_C4,
1666   X86_64_C5,
1667   X86_64_CE,
1668   X86_64_D4,
1669   X86_64_D5,
1670   X86_64_E8,
1671   X86_64_E9,
1672   X86_64_EA,
1673   X86_64_0F01_REG_0,
1674   X86_64_0F01_REG_1,
1675   X86_64_0F01_REG_2,
1676   X86_64_0F01_REG_3
1677 };
1678
1679 enum
1680 {
1681   THREE_BYTE_0F38 = 0,
1682   THREE_BYTE_0F3A
1683 };
1684
1685 enum
1686 {
1687   XOP_08 = 0,
1688   XOP_09,
1689   XOP_0A
1690 };
1691
1692 enum
1693 {
1694   VEX_0F = 0,
1695   VEX_0F38,
1696   VEX_0F3A
1697 };
1698
1699 enum
1700 {
1701   EVEX_0F = 0,
1702   EVEX_0F38,
1703   EVEX_0F3A
1704 };
1705
1706 enum
1707 {
1708   VEX_LEN_0F12_P_0_M_0 = 0,
1709   VEX_LEN_0F12_P_0_M_1,
1710 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1711   VEX_LEN_0F13_M_0,
1712   VEX_LEN_0F16_P_0_M_0,
1713   VEX_LEN_0F16_P_0_M_1,
1714 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1715   VEX_LEN_0F17_M_0,
1716   VEX_LEN_0F41_P_0,
1717   VEX_LEN_0F41_P_2,
1718   VEX_LEN_0F42_P_0,
1719   VEX_LEN_0F42_P_2,
1720   VEX_LEN_0F44_P_0,
1721   VEX_LEN_0F44_P_2,
1722   VEX_LEN_0F45_P_0,
1723   VEX_LEN_0F45_P_2,
1724   VEX_LEN_0F46_P_0,
1725   VEX_LEN_0F46_P_2,
1726   VEX_LEN_0F47_P_0,
1727   VEX_LEN_0F47_P_2,
1728   VEX_LEN_0F4A_P_0,
1729   VEX_LEN_0F4A_P_2,
1730   VEX_LEN_0F4B_P_0,
1731   VEX_LEN_0F4B_P_2,
1732   VEX_LEN_0F6E_P_2,
1733   VEX_LEN_0F77_P_0,
1734   VEX_LEN_0F7E_P_1,
1735   VEX_LEN_0F7E_P_2,
1736   VEX_LEN_0F90_P_0,
1737   VEX_LEN_0F90_P_2,
1738   VEX_LEN_0F91_P_0,
1739   VEX_LEN_0F91_P_2,
1740   VEX_LEN_0F92_P_0,
1741   VEX_LEN_0F92_P_2,
1742   VEX_LEN_0F92_P_3,
1743   VEX_LEN_0F93_P_0,
1744   VEX_LEN_0F93_P_2,
1745   VEX_LEN_0F93_P_3,
1746   VEX_LEN_0F98_P_0,
1747   VEX_LEN_0F98_P_2,
1748   VEX_LEN_0F99_P_0,
1749   VEX_LEN_0F99_P_2,
1750   VEX_LEN_0FAE_R_2_M_0,
1751   VEX_LEN_0FAE_R_3_M_0,
1752   VEX_LEN_0FC4_P_2,
1753   VEX_LEN_0FC5_P_2,
1754   VEX_LEN_0FD6_P_2,
1755   VEX_LEN_0FF7_P_2,
1756   VEX_LEN_0F3816_P_2,
1757   VEX_LEN_0F3819_P_2,
1758   VEX_LEN_0F381A_P_2_M_0,
1759   VEX_LEN_0F3836_P_2,
1760   VEX_LEN_0F3841_P_2,
1761   VEX_LEN_0F385A_P_2_M_0,
1762   VEX_LEN_0F38DB_P_2,
1763   VEX_LEN_0F38F2_P_0,
1764   VEX_LEN_0F38F3_R_1_P_0,
1765   VEX_LEN_0F38F3_R_2_P_0,
1766   VEX_LEN_0F38F3_R_3_P_0,
1767   VEX_LEN_0F38F5_P_0,
1768   VEX_LEN_0F38F5_P_1,
1769   VEX_LEN_0F38F5_P_3,
1770   VEX_LEN_0F38F6_P_3,
1771   VEX_LEN_0F38F7_P_0,
1772   VEX_LEN_0F38F7_P_1,
1773   VEX_LEN_0F38F7_P_2,
1774   VEX_LEN_0F38F7_P_3,
1775   VEX_LEN_0F3A00_P_2,
1776   VEX_LEN_0F3A01_P_2,
1777   VEX_LEN_0F3A06_P_2,
1778   VEX_LEN_0F3A14_P_2,
1779   VEX_LEN_0F3A15_P_2,
1780   VEX_LEN_0F3A16_P_2,
1781   VEX_LEN_0F3A17_P_2,
1782   VEX_LEN_0F3A18_P_2,
1783   VEX_LEN_0F3A19_P_2,
1784   VEX_LEN_0F3A20_P_2,
1785   VEX_LEN_0F3A21_P_2,
1786   VEX_LEN_0F3A22_P_2,
1787   VEX_LEN_0F3A30_P_2,
1788   VEX_LEN_0F3A31_P_2,
1789   VEX_LEN_0F3A32_P_2,
1790   VEX_LEN_0F3A33_P_2,
1791   VEX_LEN_0F3A38_P_2,
1792   VEX_LEN_0F3A39_P_2,
1793   VEX_LEN_0F3A41_P_2,
1794   VEX_LEN_0F3A46_P_2,
1795   VEX_LEN_0F3A60_P_2,
1796   VEX_LEN_0F3A61_P_2,
1797   VEX_LEN_0F3A62_P_2,
1798   VEX_LEN_0F3A63_P_2,
1799   VEX_LEN_0F3A6A_P_2,
1800   VEX_LEN_0F3A6B_P_2,
1801   VEX_LEN_0F3A6E_P_2,
1802   VEX_LEN_0F3A6F_P_2,
1803   VEX_LEN_0F3A7A_P_2,
1804   VEX_LEN_0F3A7B_P_2,
1805   VEX_LEN_0F3A7E_P_2,
1806   VEX_LEN_0F3A7F_P_2,
1807   VEX_LEN_0F3ADF_P_2,
1808   VEX_LEN_0F3AF0_P_3,
1809   VEX_LEN_0FXOP_08_CC,
1810   VEX_LEN_0FXOP_08_CD,
1811   VEX_LEN_0FXOP_08_CE,
1812   VEX_LEN_0FXOP_08_CF,
1813   VEX_LEN_0FXOP_08_EC,
1814   VEX_LEN_0FXOP_08_ED,
1815   VEX_LEN_0FXOP_08_EE,
1816   VEX_LEN_0FXOP_08_EF,
1817   VEX_LEN_0FXOP_09_82_W_0,
1818   VEX_LEN_0FXOP_09_83_W_0,
1819 };
1820
1821 enum
1822 {
1823   EVEX_LEN_0F6E_P_2 = 0,
1824   EVEX_LEN_0F7E_P_1,
1825   EVEX_LEN_0F7E_P_2,
1826   EVEX_LEN_0FC4_P_2,
1827   EVEX_LEN_0FC5_P_2,
1828   EVEX_LEN_0FD6_P_2,
1829   EVEX_LEN_0F3816_P_2,
1830   EVEX_LEN_0F3819_P_2_W_0,
1831   EVEX_LEN_0F3819_P_2_W_1,
1832   EVEX_LEN_0F381A_P_2_W_0_M_0,
1833   EVEX_LEN_0F381A_P_2_W_1_M_0,
1834   EVEX_LEN_0F381B_P_2_W_0_M_0,
1835   EVEX_LEN_0F381B_P_2_W_1_M_0,
1836   EVEX_LEN_0F3836_P_2,
1837   EVEX_LEN_0F385A_P_2_W_0_M_0,
1838   EVEX_LEN_0F385A_P_2_W_1_M_0,
1839   EVEX_LEN_0F385B_P_2_W_0_M_0,
1840   EVEX_LEN_0F385B_P_2_W_1_M_0,
1841   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1842   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1843   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1844   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1845   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1846   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1847   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1848   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1849   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1850   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1851   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1852   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1853   EVEX_LEN_0F3A00_P_2_W_1,
1854   EVEX_LEN_0F3A01_P_2_W_1,
1855   EVEX_LEN_0F3A14_P_2,
1856   EVEX_LEN_0F3A15_P_2,
1857   EVEX_LEN_0F3A16_P_2,
1858   EVEX_LEN_0F3A17_P_2,
1859   EVEX_LEN_0F3A18_P_2_W_0,
1860   EVEX_LEN_0F3A18_P_2_W_1,
1861   EVEX_LEN_0F3A19_P_2_W_0,
1862   EVEX_LEN_0F3A19_P_2_W_1,
1863   EVEX_LEN_0F3A1A_P_2_W_0,
1864   EVEX_LEN_0F3A1A_P_2_W_1,
1865   EVEX_LEN_0F3A1B_P_2_W_0,
1866   EVEX_LEN_0F3A1B_P_2_W_1,
1867   EVEX_LEN_0F3A20_P_2,
1868   EVEX_LEN_0F3A21_P_2_W_0,
1869   EVEX_LEN_0F3A22_P_2,
1870   EVEX_LEN_0F3A23_P_2_W_0,
1871   EVEX_LEN_0F3A23_P_2_W_1,
1872   EVEX_LEN_0F3A38_P_2_W_0,
1873   EVEX_LEN_0F3A38_P_2_W_1,
1874   EVEX_LEN_0F3A39_P_2_W_0,
1875   EVEX_LEN_0F3A39_P_2_W_1,
1876   EVEX_LEN_0F3A3A_P_2_W_0,
1877   EVEX_LEN_0F3A3A_P_2_W_1,
1878   EVEX_LEN_0F3A3B_P_2_W_0,
1879   EVEX_LEN_0F3A3B_P_2_W_1,
1880   EVEX_LEN_0F3A43_P_2_W_0,
1881   EVEX_LEN_0F3A43_P_2_W_1
1882 };
1883
1884 enum
1885 {
1886   VEX_W_0F41_P_0_LEN_1 = 0,
1887   VEX_W_0F41_P_2_LEN_1,
1888   VEX_W_0F42_P_0_LEN_1,
1889   VEX_W_0F42_P_2_LEN_1,
1890   VEX_W_0F44_P_0_LEN_0,
1891   VEX_W_0F44_P_2_LEN_0,
1892   VEX_W_0F45_P_0_LEN_1,
1893   VEX_W_0F45_P_2_LEN_1,
1894   VEX_W_0F46_P_0_LEN_1,
1895   VEX_W_0F46_P_2_LEN_1,
1896   VEX_W_0F47_P_0_LEN_1,
1897   VEX_W_0F47_P_2_LEN_1,
1898   VEX_W_0F4A_P_0_LEN_1,
1899   VEX_W_0F4A_P_2_LEN_1,
1900   VEX_W_0F4B_P_0_LEN_1,
1901   VEX_W_0F4B_P_2_LEN_1,
1902   VEX_W_0F90_P_0_LEN_0,
1903   VEX_W_0F90_P_2_LEN_0,
1904   VEX_W_0F91_P_0_LEN_0,
1905   VEX_W_0F91_P_2_LEN_0,
1906   VEX_W_0F92_P_0_LEN_0,
1907   VEX_W_0F92_P_2_LEN_0,
1908   VEX_W_0F93_P_0_LEN_0,
1909   VEX_W_0F93_P_2_LEN_0,
1910   VEX_W_0F98_P_0_LEN_0,
1911   VEX_W_0F98_P_2_LEN_0,
1912   VEX_W_0F99_P_0_LEN_0,
1913   VEX_W_0F99_P_2_LEN_0,
1914   VEX_W_0F380C_P_2,
1915   VEX_W_0F380D_P_2,
1916   VEX_W_0F380E_P_2,
1917   VEX_W_0F380F_P_2,
1918   VEX_W_0F3813_P_2,
1919   VEX_W_0F3816_P_2,
1920   VEX_W_0F3818_P_2,
1921   VEX_W_0F3819_P_2,
1922   VEX_W_0F381A_P_2_M_0,
1923   VEX_W_0F382C_P_2_M_0,
1924   VEX_W_0F382D_P_2_M_0,
1925   VEX_W_0F382E_P_2_M_0,
1926   VEX_W_0F382F_P_2_M_0,
1927   VEX_W_0F3836_P_2,
1928   VEX_W_0F3846_P_2,
1929   VEX_W_0F3858_P_2,
1930   VEX_W_0F3859_P_2,
1931   VEX_W_0F385A_P_2_M_0,
1932   VEX_W_0F3878_P_2,
1933   VEX_W_0F3879_P_2,
1934   VEX_W_0F38CF_P_2,
1935   VEX_W_0F3A00_P_2,
1936   VEX_W_0F3A01_P_2,
1937   VEX_W_0F3A02_P_2,
1938   VEX_W_0F3A04_P_2,
1939   VEX_W_0F3A05_P_2,
1940   VEX_W_0F3A06_P_2,
1941   VEX_W_0F3A18_P_2,
1942   VEX_W_0F3A19_P_2,
1943   VEX_W_0F3A1D_P_2,
1944   VEX_W_0F3A30_P_2_LEN_0,
1945   VEX_W_0F3A31_P_2_LEN_0,
1946   VEX_W_0F3A32_P_2_LEN_0,
1947   VEX_W_0F3A33_P_2_LEN_0,
1948   VEX_W_0F3A38_P_2,
1949   VEX_W_0F3A39_P_2,
1950   VEX_W_0F3A46_P_2,
1951   VEX_W_0F3A48_P_2,
1952   VEX_W_0F3A49_P_2,
1953   VEX_W_0F3A4A_P_2,
1954   VEX_W_0F3A4B_P_2,
1955   VEX_W_0F3A4C_P_2,
1956   VEX_W_0F3ACE_P_2,
1957   VEX_W_0F3ACF_P_2,
1958
1959   VEX_W_0FXOP_09_80,
1960   VEX_W_0FXOP_09_81,
1961   VEX_W_0FXOP_09_82,
1962   VEX_W_0FXOP_09_83,
1963
1964   EVEX_W_0F10_P_1,
1965   EVEX_W_0F10_P_3,
1966   EVEX_W_0F11_P_1,
1967   EVEX_W_0F11_P_3,
1968   EVEX_W_0F12_P_0_M_1,
1969   EVEX_W_0F12_P_1,
1970   EVEX_W_0F12_P_3,
1971   EVEX_W_0F16_P_0_M_1,
1972   EVEX_W_0F16_P_1,
1973   EVEX_W_0F2A_P_3,
1974   EVEX_W_0F51_P_1,
1975   EVEX_W_0F51_P_3,
1976   EVEX_W_0F58_P_1,
1977   EVEX_W_0F58_P_3,
1978   EVEX_W_0F59_P_1,
1979   EVEX_W_0F59_P_3,
1980   EVEX_W_0F5A_P_0,
1981   EVEX_W_0F5A_P_1,
1982   EVEX_W_0F5A_P_2,
1983   EVEX_W_0F5A_P_3,
1984   EVEX_W_0F5B_P_0,
1985   EVEX_W_0F5B_P_1,
1986   EVEX_W_0F5B_P_2,
1987   EVEX_W_0F5C_P_1,
1988   EVEX_W_0F5C_P_3,
1989   EVEX_W_0F5D_P_1,
1990   EVEX_W_0F5D_P_3,
1991   EVEX_W_0F5E_P_1,
1992   EVEX_W_0F5E_P_3,
1993   EVEX_W_0F5F_P_1,
1994   EVEX_W_0F5F_P_3,
1995   EVEX_W_0F62,
1996   EVEX_W_0F66_P_2,
1997   EVEX_W_0F6A,
1998   EVEX_W_0F6B,
1999   EVEX_W_0F6C,
2000   EVEX_W_0F6D,
2001   EVEX_W_0F6F_P_1,
2002   EVEX_W_0F6F_P_2,
2003   EVEX_W_0F6F_P_3,
2004   EVEX_W_0F70_P_2,
2005   EVEX_W_0F72_R_2_P_2,
2006   EVEX_W_0F72_R_6_P_2,
2007   EVEX_W_0F73_R_2_P_2,
2008   EVEX_W_0F73_R_6_P_2,
2009   EVEX_W_0F76_P_2,
2010   EVEX_W_0F78_P_0,
2011   EVEX_W_0F78_P_2,
2012   EVEX_W_0F79_P_0,
2013   EVEX_W_0F79_P_2,
2014   EVEX_W_0F7A_P_1,
2015   EVEX_W_0F7A_P_2,
2016   EVEX_W_0F7A_P_3,
2017   EVEX_W_0F7B_P_2,
2018   EVEX_W_0F7B_P_3,
2019   EVEX_W_0F7E_P_1,
2020   EVEX_W_0F7F_P_1,
2021   EVEX_W_0F7F_P_2,
2022   EVEX_W_0F7F_P_3,
2023   EVEX_W_0FC2_P_1,
2024   EVEX_W_0FC2_P_3,
2025   EVEX_W_0FD2,
2026   EVEX_W_0FD3,
2027   EVEX_W_0FD4,
2028   EVEX_W_0FD6_P_2,
2029   EVEX_W_0FE6_P_1,
2030   EVEX_W_0FE6_P_2,
2031   EVEX_W_0FE6_P_3,
2032   EVEX_W_0FE7_P_2,
2033   EVEX_W_0FF2,
2034   EVEX_W_0FF3,
2035   EVEX_W_0FF4,
2036   EVEX_W_0FFA,
2037   EVEX_W_0FFB,
2038   EVEX_W_0FFE,
2039   EVEX_W_0F380D_P_2,
2040   EVEX_W_0F3810_P_1,
2041   EVEX_W_0F3810_P_2,
2042   EVEX_W_0F3811_P_1,
2043   EVEX_W_0F3811_P_2,
2044   EVEX_W_0F3812_P_1,
2045   EVEX_W_0F3812_P_2,
2046   EVEX_W_0F3813_P_1,
2047   EVEX_W_0F3813_P_2,
2048   EVEX_W_0F3814_P_1,
2049   EVEX_W_0F3815_P_1,
2050   EVEX_W_0F3819_P_2,
2051   EVEX_W_0F381A_P_2,
2052   EVEX_W_0F381B_P_2,
2053   EVEX_W_0F381E_P_2,
2054   EVEX_W_0F381F_P_2,
2055   EVEX_W_0F3820_P_1,
2056   EVEX_W_0F3821_P_1,
2057   EVEX_W_0F3822_P_1,
2058   EVEX_W_0F3823_P_1,
2059   EVEX_W_0F3824_P_1,
2060   EVEX_W_0F3825_P_1,
2061   EVEX_W_0F3825_P_2,
2062   EVEX_W_0F3828_P_2,
2063   EVEX_W_0F3829_P_2,
2064   EVEX_W_0F382A_P_1,
2065   EVEX_W_0F382A_P_2,
2066   EVEX_W_0F382B,
2067   EVEX_W_0F3830_P_1,
2068   EVEX_W_0F3831_P_1,
2069   EVEX_W_0F3832_P_1,
2070   EVEX_W_0F3833_P_1,
2071   EVEX_W_0F3834_P_1,
2072   EVEX_W_0F3835_P_1,
2073   EVEX_W_0F3835_P_2,
2074   EVEX_W_0F3837_P_2,
2075   EVEX_W_0F383A_P_1,
2076   EVEX_W_0F3852_P_1,
2077   EVEX_W_0F3859_P_2,
2078   EVEX_W_0F385A_P_2,
2079   EVEX_W_0F385B_P_2,
2080   EVEX_W_0F3862_P_2,
2081   EVEX_W_0F3863_P_2,
2082   EVEX_W_0F3870_P_2,
2083   EVEX_W_0F3872_P_1,
2084   EVEX_W_0F3872_P_2,
2085   EVEX_W_0F3872_P_3,
2086   EVEX_W_0F387A_P_2,
2087   EVEX_W_0F387B_P_2,
2088   EVEX_W_0F3883_P_2,
2089   EVEX_W_0F3891_P_2,
2090   EVEX_W_0F3893_P_2,
2091   EVEX_W_0F38A1_P_2,
2092   EVEX_W_0F38A3_P_2,
2093   EVEX_W_0F38C7_R_1_P_2,
2094   EVEX_W_0F38C7_R_2_P_2,
2095   EVEX_W_0F38C7_R_5_P_2,
2096   EVEX_W_0F38C7_R_6_P_2,
2097
2098   EVEX_W_0F3A00_P_2,
2099   EVEX_W_0F3A01_P_2,
2100   EVEX_W_0F3A05_P_2,
2101   EVEX_W_0F3A08_P_2,
2102   EVEX_W_0F3A09_P_2,
2103   EVEX_W_0F3A0A_P_2,
2104   EVEX_W_0F3A0B_P_2,
2105   EVEX_W_0F3A18_P_2,
2106   EVEX_W_0F3A19_P_2,
2107   EVEX_W_0F3A1A_P_2,
2108   EVEX_W_0F3A1B_P_2,
2109   EVEX_W_0F3A21_P_2,
2110   EVEX_W_0F3A23_P_2,
2111   EVEX_W_0F3A38_P_2,
2112   EVEX_W_0F3A39_P_2,
2113   EVEX_W_0F3A3A_P_2,
2114   EVEX_W_0F3A3B_P_2,
2115   EVEX_W_0F3A42_P_2,
2116   EVEX_W_0F3A43_P_2,
2117   EVEX_W_0F3A70_P_2,
2118   EVEX_W_0F3A72_P_2,
2119 };
2120
2121 typedef void (*op_rtn) (int bytemode, int sizeflag);
2122
2123 struct dis386 {
2124   const char *name;
2125   struct
2126     {
2127       op_rtn rtn;
2128       int bytemode;
2129     } op[MAX_OPERANDS];
2130   unsigned int prefix_requirement;
2131 };
2132
2133 /* Upper case letters in the instruction names here are macros.
2134    'A' => print 'b' if no register operands or suffix_always is true
2135    'B' => print 'b' if suffix_always is true
2136    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2137           size prefix
2138    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2139           suffix_always is true
2140    'E' => print 'e' if 32-bit form of jcxz
2141    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2142    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2143    'H' => print ",pt" or ",pn" branch hint
2144    'I' unused.
2145    'J' unused.
2146    'K' => print 'd' or 'q' if rex prefix is present.
2147    'L' => print 'l' if suffix_always is true
2148    'M' => print 'r' if intel_mnemonic is false.
2149    'N' => print 'n' if instruction has no wait "prefix"
2150    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2151    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2152           or suffix_always is true.  print 'q' if rex prefix is present.
2153    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2154           is true
2155    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2156    'S' => print 'w', 'l' or 'q' if suffix_always is true
2157    'T' => print 'q' in 64bit mode if instruction has no operand size
2158           prefix and behave as 'P' otherwise
2159    'U' => print 'q' in 64bit mode if instruction has no operand size
2160           prefix and behave as 'Q' otherwise
2161    'V' => print 'q' in 64bit mode if instruction has no operand size
2162           prefix and behave as 'S' otherwise
2163    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2164    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2165    'Y' unused.
2166    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2167    '!' => change condition from true to false or from false to true.
2168    '%' => add 1 upper case letter to the macro.
2169    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2170           prefix or suffix_always is true (lcall/ljmp).
2171    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2172           on operand size prefix.
2173    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2174           has no operand size prefix for AMD64 ISA, behave as 'P'
2175           otherwise
2176
2177    2 upper case letter macros:
2178    "XY" => print 'x' or 'y' if suffix_always is true or no register
2179            operands and no broadcast.
2180    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2181            register operands and no broadcast.
2182    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2183    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2184            operand or no operand at all in 64bit mode, or if suffix_always
2185            is true.
2186    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2187    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2188    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2189    "LW" => print 'd', 'q' depending on the VEX.W bit
2190    "BW" => print 'b' or 'w' depending on the EVEX.W bit
2191    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2192            an operand size prefix, or suffix_always is true.  print
2193            'q' if rex prefix is present.
2194
2195    Many of the above letters print nothing in Intel mode.  See "putop"
2196    for the details.
2197
2198    Braces '{' and '}', and vertical bars '|', indicate alternative
2199    mnemonic strings for AT&T and Intel.  */
2200
2201 static const struct dis386 dis386[] = {
2202   /* 00 */
2203   { "addB",             { Ebh1, Gb }, 0 },
2204   { "addS",             { Evh1, Gv }, 0 },
2205   { "addB",             { Gb, EbS }, 0 },
2206   { "addS",             { Gv, EvS }, 0 },
2207   { "addB",             { AL, Ib }, 0 },
2208   { "addS",             { eAX, Iv }, 0 },
2209   { X86_64_TABLE (X86_64_06) },
2210   { X86_64_TABLE (X86_64_07) },
2211   /* 08 */
2212   { "orB",              { Ebh1, Gb }, 0 },
2213   { "orS",              { Evh1, Gv }, 0 },
2214   { "orB",              { Gb, EbS }, 0 },
2215   { "orS",              { Gv, EvS }, 0 },
2216   { "orB",              { AL, Ib }, 0 },
2217   { "orS",              { eAX, Iv }, 0 },
2218   { X86_64_TABLE (X86_64_0E) },
2219   { Bad_Opcode },       /* 0x0f extended opcode escape */
2220   /* 10 */
2221   { "adcB",             { Ebh1, Gb }, 0 },
2222   { "adcS",             { Evh1, Gv }, 0 },
2223   { "adcB",             { Gb, EbS }, 0 },
2224   { "adcS",             { Gv, EvS }, 0 },
2225   { "adcB",             { AL, Ib }, 0 },
2226   { "adcS",             { eAX, Iv }, 0 },
2227   { X86_64_TABLE (X86_64_16) },
2228   { X86_64_TABLE (X86_64_17) },
2229   /* 18 */
2230   { "sbbB",             { Ebh1, Gb }, 0 },
2231   { "sbbS",             { Evh1, Gv }, 0 },
2232   { "sbbB",             { Gb, EbS }, 0 },
2233   { "sbbS",             { Gv, EvS }, 0 },
2234   { "sbbB",             { AL, Ib }, 0 },
2235   { "sbbS",             { eAX, Iv }, 0 },
2236   { X86_64_TABLE (X86_64_1E) },
2237   { X86_64_TABLE (X86_64_1F) },
2238   /* 20 */
2239   { "andB",             { Ebh1, Gb }, 0 },
2240   { "andS",             { Evh1, Gv }, 0 },
2241   { "andB",             { Gb, EbS }, 0 },
2242   { "andS",             { Gv, EvS }, 0 },
2243   { "andB",             { AL, Ib }, 0 },
2244   { "andS",             { eAX, Iv }, 0 },
2245   { Bad_Opcode },       /* SEG ES prefix */
2246   { X86_64_TABLE (X86_64_27) },
2247   /* 28 */
2248   { "subB",             { Ebh1, Gb }, 0 },
2249   { "subS",             { Evh1, Gv }, 0 },
2250   { "subB",             { Gb, EbS }, 0 },
2251   { "subS",             { Gv, EvS }, 0 },
2252   { "subB",             { AL, Ib }, 0 },
2253   { "subS",             { eAX, Iv }, 0 },
2254   { Bad_Opcode },       /* SEG CS prefix */
2255   { X86_64_TABLE (X86_64_2F) },
2256   /* 30 */
2257   { "xorB",             { Ebh1, Gb }, 0 },
2258   { "xorS",             { Evh1, Gv }, 0 },
2259   { "xorB",             { Gb, EbS }, 0 },
2260   { "xorS",             { Gv, EvS }, 0 },
2261   { "xorB",             { AL, Ib }, 0 },
2262   { "xorS",             { eAX, Iv }, 0 },
2263   { Bad_Opcode },       /* SEG SS prefix */
2264   { X86_64_TABLE (X86_64_37) },
2265   /* 38 */
2266   { "cmpB",             { Eb, Gb }, 0 },
2267   { "cmpS",             { Ev, Gv }, 0 },
2268   { "cmpB",             { Gb, EbS }, 0 },
2269   { "cmpS",             { Gv, EvS }, 0 },
2270   { "cmpB",             { AL, Ib }, 0 },
2271   { "cmpS",             { eAX, Iv }, 0 },
2272   { Bad_Opcode },       /* SEG DS prefix */
2273   { X86_64_TABLE (X86_64_3F) },
2274   /* 40 */
2275   { "inc{S|}",          { RMeAX }, 0 },
2276   { "inc{S|}",          { RMeCX }, 0 },
2277   { "inc{S|}",          { RMeDX }, 0 },
2278   { "inc{S|}",          { RMeBX }, 0 },
2279   { "inc{S|}",          { RMeSP }, 0 },
2280   { "inc{S|}",          { RMeBP }, 0 },
2281   { "inc{S|}",          { RMeSI }, 0 },
2282   { "inc{S|}",          { RMeDI }, 0 },
2283   /* 48 */
2284   { "dec{S|}",          { RMeAX }, 0 },
2285   { "dec{S|}",          { RMeCX }, 0 },
2286   { "dec{S|}",          { RMeDX }, 0 },
2287   { "dec{S|}",          { RMeBX }, 0 },
2288   { "dec{S|}",          { RMeSP }, 0 },
2289   { "dec{S|}",          { RMeBP }, 0 },
2290   { "dec{S|}",          { RMeSI }, 0 },
2291   { "dec{S|}",          { RMeDI }, 0 },
2292   /* 50 */
2293   { "pushV",            { RMrAX }, 0 },
2294   { "pushV",            { RMrCX }, 0 },
2295   { "pushV",            { RMrDX }, 0 },
2296   { "pushV",            { RMrBX }, 0 },
2297   { "pushV",            { RMrSP }, 0 },
2298   { "pushV",            { RMrBP }, 0 },
2299   { "pushV",            { RMrSI }, 0 },
2300   { "pushV",            { RMrDI }, 0 },
2301   /* 58 */
2302   { "popV",             { RMrAX }, 0 },
2303   { "popV",             { RMrCX }, 0 },
2304   { "popV",             { RMrDX }, 0 },
2305   { "popV",             { RMrBX }, 0 },
2306   { "popV",             { RMrSP }, 0 },
2307   { "popV",             { RMrBP }, 0 },
2308   { "popV",             { RMrSI }, 0 },
2309   { "popV",             { RMrDI }, 0 },
2310   /* 60 */
2311   { X86_64_TABLE (X86_64_60) },
2312   { X86_64_TABLE (X86_64_61) },
2313   { X86_64_TABLE (X86_64_62) },
2314   { X86_64_TABLE (X86_64_63) },
2315   { Bad_Opcode },       /* seg fs */
2316   { Bad_Opcode },       /* seg gs */
2317   { Bad_Opcode },       /* op size prefix */
2318   { Bad_Opcode },       /* adr size prefix */
2319   /* 68 */
2320   { "pushT",            { sIv }, 0 },
2321   { "imulS",            { Gv, Ev, Iv }, 0 },
2322   { "pushT",            { sIbT }, 0 },
2323   { "imulS",            { Gv, Ev, sIb }, 0 },
2324   { "ins{b|}",          { Ybr, indirDX }, 0 },
2325   { X86_64_TABLE (X86_64_6D) },
2326   { "outs{b|}",         { indirDXr, Xb }, 0 },
2327   { X86_64_TABLE (X86_64_6F) },
2328   /* 70 */
2329   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2330   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2331   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2332   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2333   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2334   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2335   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2336   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2337   /* 78 */
2338   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2339   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2340   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2341   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2342   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2343   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2344   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2345   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2346   /* 80 */
2347   { REG_TABLE (REG_80) },
2348   { REG_TABLE (REG_81) },
2349   { X86_64_TABLE (X86_64_82) },
2350   { REG_TABLE (REG_83) },
2351   { "testB",            { Eb, Gb }, 0 },
2352   { "testS",            { Ev, Gv }, 0 },
2353   { "xchgB",            { Ebh2, Gb }, 0 },
2354   { "xchgS",            { Evh2, Gv }, 0 },
2355   /* 88 */
2356   { "movB",             { Ebh3, Gb }, 0 },
2357   { "movS",             { Evh3, Gv }, 0 },
2358   { "movB",             { Gb, EbS }, 0 },
2359   { "movS",             { Gv, EvS }, 0 },
2360   { "movD",             { Sv, Sw }, 0 },
2361   { MOD_TABLE (MOD_8D) },
2362   { "movD",             { Sw, Sv }, 0 },
2363   { REG_TABLE (REG_8F) },
2364   /* 90 */
2365   { PREFIX_TABLE (PREFIX_90) },
2366   { "xchgS",            { RMeCX, eAX }, 0 },
2367   { "xchgS",            { RMeDX, eAX }, 0 },
2368   { "xchgS",            { RMeBX, eAX }, 0 },
2369   { "xchgS",            { RMeSP, eAX }, 0 },
2370   { "xchgS",            { RMeBP, eAX }, 0 },
2371   { "xchgS",            { RMeSI, eAX }, 0 },
2372   { "xchgS",            { RMeDI, eAX }, 0 },
2373   /* 98 */
2374   { "cW{t|}R",          { XX }, 0 },
2375   { "cR{t|}O",          { XX }, 0 },
2376   { X86_64_TABLE (X86_64_9A) },
2377   { Bad_Opcode },       /* fwait */
2378   { "pushfT",           { XX }, 0 },
2379   { "popfT",            { XX }, 0 },
2380   { "sahf",             { XX }, 0 },
2381   { "lahf",             { XX }, 0 },
2382   /* a0 */
2383   { "mov%LB",           { AL, Ob }, 0 },
2384   { "mov%LS",           { eAX, Ov }, 0 },
2385   { "mov%LB",           { Ob, AL }, 0 },
2386   { "mov%LS",           { Ov, eAX }, 0 },
2387   { "movs{b|}",         { Ybr, Xb }, 0 },
2388   { "movs{R|}",         { Yvr, Xv }, 0 },
2389   { "cmps{b|}",         { Xb, Yb }, 0 },
2390   { "cmps{R|}",         { Xv, Yv }, 0 },
2391   /* a8 */
2392   { "testB",            { AL, Ib }, 0 },
2393   { "testS",            { eAX, Iv }, 0 },
2394   { "stosB",            { Ybr, AL }, 0 },
2395   { "stosS",            { Yvr, eAX }, 0 },
2396   { "lodsB",            { ALr, Xb }, 0 },
2397   { "lodsS",            { eAXr, Xv }, 0 },
2398   { "scasB",            { AL, Yb }, 0 },
2399   { "scasS",            { eAX, Yv }, 0 },
2400   /* b0 */
2401   { "movB",             { RMAL, Ib }, 0 },
2402   { "movB",             { RMCL, Ib }, 0 },
2403   { "movB",             { RMDL, Ib }, 0 },
2404   { "movB",             { RMBL, Ib }, 0 },
2405   { "movB",             { RMAH, Ib }, 0 },
2406   { "movB",             { RMCH, Ib }, 0 },
2407   { "movB",             { RMDH, Ib }, 0 },
2408   { "movB",             { RMBH, Ib }, 0 },
2409   /* b8 */
2410   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2411   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2412   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2413   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2414   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2415   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2416   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2417   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2418   /* c0 */
2419   { REG_TABLE (REG_C0) },
2420   { REG_TABLE (REG_C1) },
2421   { X86_64_TABLE (X86_64_C2) },
2422   { X86_64_TABLE (X86_64_C3) },
2423   { X86_64_TABLE (X86_64_C4) },
2424   { X86_64_TABLE (X86_64_C5) },
2425   { REG_TABLE (REG_C6) },
2426   { REG_TABLE (REG_C7) },
2427   /* c8 */
2428   { "enterT",           { Iw, Ib }, 0 },
2429   { "leaveT",           { XX }, 0 },
2430   { "{l|}ret{|f}P",     { Iw }, 0 },
2431   { "{l|}ret{|f}P",     { XX }, 0 },
2432   { "int3",             { XX }, 0 },
2433   { "int",              { Ib }, 0 },
2434   { X86_64_TABLE (X86_64_CE) },
2435   { "iret%LP",          { XX }, 0 },
2436   /* d0 */
2437   { REG_TABLE (REG_D0) },
2438   { REG_TABLE (REG_D1) },
2439   { REG_TABLE (REG_D2) },
2440   { REG_TABLE (REG_D3) },
2441   { X86_64_TABLE (X86_64_D4) },
2442   { X86_64_TABLE (X86_64_D5) },
2443   { Bad_Opcode },
2444   { "xlat",             { DSBX }, 0 },
2445   /* d8 */
2446   { FLOAT },
2447   { FLOAT },
2448   { FLOAT },
2449   { FLOAT },
2450   { FLOAT },
2451   { FLOAT },
2452   { FLOAT },
2453   { FLOAT },
2454   /* e0 */
2455   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2456   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2457   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2458   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2459   { "inB",              { AL, Ib }, 0 },
2460   { "inG",              { zAX, Ib }, 0 },
2461   { "outB",             { Ib, AL }, 0 },
2462   { "outG",             { Ib, zAX }, 0 },
2463   /* e8 */
2464   { X86_64_TABLE (X86_64_E8) },
2465   { X86_64_TABLE (X86_64_E9) },
2466   { X86_64_TABLE (X86_64_EA) },
2467   { "jmp",              { Jb, BND }, 0 },
2468   { "inB",              { AL, indirDX }, 0 },
2469   { "inG",              { zAX, indirDX }, 0 },
2470   { "outB",             { indirDX, AL }, 0 },
2471   { "outG",             { indirDX, zAX }, 0 },
2472   /* f0 */
2473   { Bad_Opcode },       /* lock prefix */
2474   { "icebp",            { XX }, 0 },
2475   { Bad_Opcode },       /* repne */
2476   { Bad_Opcode },       /* repz */
2477   { "hlt",              { XX }, 0 },
2478   { "cmc",              { XX }, 0 },
2479   { REG_TABLE (REG_F6) },
2480   { REG_TABLE (REG_F7) },
2481   /* f8 */
2482   { "clc",              { XX }, 0 },
2483   { "stc",              { XX }, 0 },
2484   { "cli",              { XX }, 0 },
2485   { "sti",              { XX }, 0 },
2486   { "cld",              { XX }, 0 },
2487   { "std",              { XX }, 0 },
2488   { REG_TABLE (REG_FE) },
2489   { REG_TABLE (REG_FF) },
2490 };
2491
2492 static const struct dis386 dis386_twobyte[] = {
2493   /* 00 */
2494   { REG_TABLE (REG_0F00 ) },
2495   { REG_TABLE (REG_0F01 ) },
2496   { "larS",             { Gv, Ew }, 0 },
2497   { "lslS",             { Gv, Ew }, 0 },
2498   { Bad_Opcode },
2499   { "syscall",          { XX }, 0 },
2500   { "clts",             { XX }, 0 },
2501   { "sysret%LQ",                { XX }, 0 },
2502   /* 08 */
2503   { "invd",             { XX }, 0 },
2504   { PREFIX_TABLE (PREFIX_0F09) },
2505   { Bad_Opcode },
2506   { "ud2",              { XX }, 0 },
2507   { Bad_Opcode },
2508   { REG_TABLE (REG_0F0D) },
2509   { "femms",            { XX }, 0 },
2510   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2511   /* 10 */
2512   { PREFIX_TABLE (PREFIX_0F10) },
2513   { PREFIX_TABLE (PREFIX_0F11) },
2514   { PREFIX_TABLE (PREFIX_0F12) },
2515   { MOD_TABLE (MOD_0F13) },
2516   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2517   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2518   { PREFIX_TABLE (PREFIX_0F16) },
2519   { MOD_TABLE (MOD_0F17) },
2520   /* 18 */
2521   { REG_TABLE (REG_0F18) },
2522   { "nopQ",             { Ev }, 0 },
2523   { PREFIX_TABLE (PREFIX_0F1A) },
2524   { PREFIX_TABLE (PREFIX_0F1B) },
2525   { PREFIX_TABLE (PREFIX_0F1C) },
2526   { "nopQ",             { Ev }, 0 },
2527   { PREFIX_TABLE (PREFIX_0F1E) },
2528   { "nopQ",             { Ev }, 0 },
2529   /* 20 */
2530   { "movZ",             { Rm, Cm }, 0 },
2531   { "movZ",             { Rm, Dm }, 0 },
2532   { "movZ",             { Cm, Rm }, 0 },
2533   { "movZ",             { Dm, Rm }, 0 },
2534   { MOD_TABLE (MOD_0F24) },
2535   { Bad_Opcode },
2536   { MOD_TABLE (MOD_0F26) },
2537   { Bad_Opcode },
2538   /* 28 */
2539   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2540   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2541   { PREFIX_TABLE (PREFIX_0F2A) },
2542   { PREFIX_TABLE (PREFIX_0F2B) },
2543   { PREFIX_TABLE (PREFIX_0F2C) },
2544   { PREFIX_TABLE (PREFIX_0F2D) },
2545   { PREFIX_TABLE (PREFIX_0F2E) },
2546   { PREFIX_TABLE (PREFIX_0F2F) },
2547   /* 30 */
2548   { "wrmsr",            { XX }, 0 },
2549   { "rdtsc",            { XX }, 0 },
2550   { "rdmsr",            { XX }, 0 },
2551   { "rdpmc",            { XX }, 0 },
2552   { "sysenter",         { SEP }, 0 },
2553   { "sysexit",          { SEP }, 0 },
2554   { Bad_Opcode },
2555   { "getsec",           { XX }, 0 },
2556   /* 38 */
2557   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2558   { Bad_Opcode },
2559   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2560   { Bad_Opcode },
2561   { Bad_Opcode },
2562   { Bad_Opcode },
2563   { Bad_Opcode },
2564   { Bad_Opcode },
2565   /* 40 */
2566   { "cmovoS",           { Gv, Ev }, 0 },
2567   { "cmovnoS",          { Gv, Ev }, 0 },
2568   { "cmovbS",           { Gv, Ev }, 0 },
2569   { "cmovaeS",          { Gv, Ev }, 0 },
2570   { "cmoveS",           { Gv, Ev }, 0 },
2571   { "cmovneS",          { Gv, Ev }, 0 },
2572   { "cmovbeS",          { Gv, Ev }, 0 },
2573   { "cmovaS",           { Gv, Ev }, 0 },
2574   /* 48 */
2575   { "cmovsS",           { Gv, Ev }, 0 },
2576   { "cmovnsS",          { Gv, Ev }, 0 },
2577   { "cmovpS",           { Gv, Ev }, 0 },
2578   { "cmovnpS",          { Gv, Ev }, 0 },
2579   { "cmovlS",           { Gv, Ev }, 0 },
2580   { "cmovgeS",          { Gv, Ev }, 0 },
2581   { "cmovleS",          { Gv, Ev }, 0 },
2582   { "cmovgS",           { Gv, Ev }, 0 },
2583   /* 50 */
2584   { MOD_TABLE (MOD_0F50) },
2585   { PREFIX_TABLE (PREFIX_0F51) },
2586   { PREFIX_TABLE (PREFIX_0F52) },
2587   { PREFIX_TABLE (PREFIX_0F53) },
2588   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2589   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2590   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2591   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2592   /* 58 */
2593   { PREFIX_TABLE (PREFIX_0F58) },
2594   { PREFIX_TABLE (PREFIX_0F59) },
2595   { PREFIX_TABLE (PREFIX_0F5A) },
2596   { PREFIX_TABLE (PREFIX_0F5B) },
2597   { PREFIX_TABLE (PREFIX_0F5C) },
2598   { PREFIX_TABLE (PREFIX_0F5D) },
2599   { PREFIX_TABLE (PREFIX_0F5E) },
2600   { PREFIX_TABLE (PREFIX_0F5F) },
2601   /* 60 */
2602   { PREFIX_TABLE (PREFIX_0F60) },
2603   { PREFIX_TABLE (PREFIX_0F61) },
2604   { PREFIX_TABLE (PREFIX_0F62) },
2605   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2606   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2607   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2608   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2609   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2610   /* 68 */
2611   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2612   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2613   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2614   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2615   { PREFIX_TABLE (PREFIX_0F6C) },
2616   { PREFIX_TABLE (PREFIX_0F6D) },
2617   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2618   { PREFIX_TABLE (PREFIX_0F6F) },
2619   /* 70 */
2620   { PREFIX_TABLE (PREFIX_0F70) },
2621   { REG_TABLE (REG_0F71) },
2622   { REG_TABLE (REG_0F72) },
2623   { REG_TABLE (REG_0F73) },
2624   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2625   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2626   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2627   { "emms",             { XX }, PREFIX_OPCODE },
2628   /* 78 */
2629   { PREFIX_TABLE (PREFIX_0F78) },
2630   { PREFIX_TABLE (PREFIX_0F79) },
2631   { Bad_Opcode },
2632   { Bad_Opcode },
2633   { PREFIX_TABLE (PREFIX_0F7C) },
2634   { PREFIX_TABLE (PREFIX_0F7D) },
2635   { PREFIX_TABLE (PREFIX_0F7E) },
2636   { PREFIX_TABLE (PREFIX_0F7F) },
2637   /* 80 */
2638   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2639   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2640   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2641   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2642   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2643   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2644   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2645   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2646   /* 88 */
2647   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2648   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2649   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2650   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2651   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2652   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2653   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2654   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2655   /* 90 */
2656   { "seto",             { Eb }, 0 },
2657   { "setno",            { Eb }, 0 },
2658   { "setb",             { Eb }, 0 },
2659   { "setae",            { Eb }, 0 },
2660   { "sete",             { Eb }, 0 },
2661   { "setne",            { Eb }, 0 },
2662   { "setbe",            { Eb }, 0 },
2663   { "seta",             { Eb }, 0 },
2664   /* 98 */
2665   { "sets",             { Eb }, 0 },
2666   { "setns",            { Eb }, 0 },
2667   { "setp",             { Eb }, 0 },
2668   { "setnp",            { Eb }, 0 },
2669   { "setl",             { Eb }, 0 },
2670   { "setge",            { Eb }, 0 },
2671   { "setle",            { Eb }, 0 },
2672   { "setg",             { Eb }, 0 },
2673   /* a0 */
2674   { "pushT",            { fs }, 0 },
2675   { "popT",             { fs }, 0 },
2676   { "cpuid",            { XX }, 0 },
2677   { "btS",              { Ev, Gv }, 0 },
2678   { "shldS",            { Ev, Gv, Ib }, 0 },
2679   { "shldS",            { Ev, Gv, CL }, 0 },
2680   { REG_TABLE (REG_0FA6) },
2681   { REG_TABLE (REG_0FA7) },
2682   /* a8 */
2683   { "pushT",            { gs }, 0 },
2684   { "popT",             { gs }, 0 },
2685   { "rsm",              { XX }, 0 },
2686   { "btsS",             { Evh1, Gv }, 0 },
2687   { "shrdS",            { Ev, Gv, Ib }, 0 },
2688   { "shrdS",            { Ev, Gv, CL }, 0 },
2689   { REG_TABLE (REG_0FAE) },
2690   { "imulS",            { Gv, Ev }, 0 },
2691   /* b0 */
2692   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2693   { "cmpxchgS",         { Evh1, Gv }, 0 },
2694   { MOD_TABLE (MOD_0FB2) },
2695   { "btrS",             { Evh1, Gv }, 0 },
2696   { MOD_TABLE (MOD_0FB4) },
2697   { MOD_TABLE (MOD_0FB5) },
2698   { "movz{bR|x}",       { Gv, Eb }, 0 },
2699   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2700   /* b8 */
2701   { PREFIX_TABLE (PREFIX_0FB8) },
2702   { "ud1S",             { Gv, Ev }, 0 },
2703   { REG_TABLE (REG_0FBA) },
2704   { "btcS",             { Evh1, Gv }, 0 },
2705   { PREFIX_TABLE (PREFIX_0FBC) },
2706   { PREFIX_TABLE (PREFIX_0FBD) },
2707   { "movs{bR|x}",       { Gv, Eb }, 0 },
2708   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2709   /* c0 */
2710   { "xaddB",            { Ebh1, Gb }, 0 },
2711   { "xaddS",            { Evh1, Gv }, 0 },
2712   { PREFIX_TABLE (PREFIX_0FC2) },
2713   { MOD_TABLE (MOD_0FC3) },
2714   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2715   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2716   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2717   { REG_TABLE (REG_0FC7) },
2718   /* c8 */
2719   { "bswap",            { RMeAX }, 0 },
2720   { "bswap",            { RMeCX }, 0 },
2721   { "bswap",            { RMeDX }, 0 },
2722   { "bswap",            { RMeBX }, 0 },
2723   { "bswap",            { RMeSP }, 0 },
2724   { "bswap",            { RMeBP }, 0 },
2725   { "bswap",            { RMeSI }, 0 },
2726   { "bswap",            { RMeDI }, 0 },
2727   /* d0 */
2728   { PREFIX_TABLE (PREFIX_0FD0) },
2729   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2730   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2731   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2732   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2733   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2734   { PREFIX_TABLE (PREFIX_0FD6) },
2735   { MOD_TABLE (MOD_0FD7) },
2736   /* d8 */
2737   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2738   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2739   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2740   { "pand",             { MX, EM }, PREFIX_OPCODE },
2741   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2742   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2743   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2744   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2745   /* e0 */
2746   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2747   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2748   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2749   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2750   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2751   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2752   { PREFIX_TABLE (PREFIX_0FE6) },
2753   { PREFIX_TABLE (PREFIX_0FE7) },
2754   /* e8 */
2755   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2756   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2757   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2758   { "por",              { MX, EM }, PREFIX_OPCODE },
2759   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2760   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2761   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2762   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2763   /* f0 */
2764   { PREFIX_TABLE (PREFIX_0FF0) },
2765   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2766   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2767   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2768   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2769   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2770   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2771   { PREFIX_TABLE (PREFIX_0FF7) },
2772   /* f8 */
2773   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2774   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2775   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2776   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2777   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2778   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2779   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2780   { "ud0S",             { Gv, Ev }, 0 },
2781 };
2782
2783 static const unsigned char onebyte_has_modrm[256] = {
2784   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2785   /*       -------------------------------        */
2786   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2787   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2788   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2789   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2790   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2791   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2792   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2793   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2794   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2795   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2796   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2797   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2798   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2799   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2800   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2801   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2802   /*       -------------------------------        */
2803   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2804 };
2805
2806 static const unsigned char twobyte_has_modrm[256] = {
2807   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2808   /*       -------------------------------        */
2809   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2810   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2811   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2812   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2813   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2814   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2815   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2816   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2817   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2818   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2819   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2820   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2821   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2822   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2823   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2824   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2825   /*       -------------------------------        */
2826   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2827 };
2828
2829 static char obuf[100];
2830 static char *obufp;
2831 static char *mnemonicendp;
2832 static char scratchbuf[100];
2833 static unsigned char *start_codep;
2834 static unsigned char *insn_codep;
2835 static unsigned char *codep;
2836 static unsigned char *end_codep;
2837 static int last_lock_prefix;
2838 static int last_repz_prefix;
2839 static int last_repnz_prefix;
2840 static int last_data_prefix;
2841 static int last_addr_prefix;
2842 static int last_rex_prefix;
2843 static int last_seg_prefix;
2844 static int fwait_prefix;
2845 /* The active segment register prefix.  */
2846 static int active_seg_prefix;
2847 #define MAX_CODE_LENGTH 15
2848 /* We can up to 14 prefixes since the maximum instruction length is
2849    15bytes.  */
2850 static int all_prefixes[MAX_CODE_LENGTH - 1];
2851 static disassemble_info *the_info;
2852 static struct
2853   {
2854     int mod;
2855     int reg;
2856     int rm;
2857   }
2858 modrm;
2859 static unsigned char need_modrm;
2860 static struct
2861   {
2862     int scale;
2863     int index;
2864     int base;
2865   }
2866 sib;
2867 static struct
2868   {
2869     int register_specifier;
2870     int length;
2871     int prefix;
2872     int w;
2873     int evex;
2874     int r;
2875     int v;
2876     int mask_register_specifier;
2877     int zeroing;
2878     int ll;
2879     int b;
2880   }
2881 vex;
2882 static unsigned char need_vex;
2883 static unsigned char need_vex_reg;
2884 static unsigned char vex_w_done;
2885
2886 struct op
2887   {
2888     const char *name;
2889     unsigned int len;
2890   };
2891
2892 /* If we are accessing mod/rm/reg without need_modrm set, then the
2893    values are stale.  Hitting this abort likely indicates that you
2894    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2895 #define MODRM_CHECK  if (!need_modrm) abort ()
2896
2897 static const char **names64;
2898 static const char **names32;
2899 static const char **names16;
2900 static const char **names8;
2901 static const char **names8rex;
2902 static const char **names_seg;
2903 static const char *index64;
2904 static const char *index32;
2905 static const char **index16;
2906 static const char **names_bnd;
2907
2908 static const char *intel_names64[] = {
2909   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2910   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2911 };
2912 static const char *intel_names32[] = {
2913   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2914   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2915 };
2916 static const char *intel_names16[] = {
2917   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2918   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2919 };
2920 static const char *intel_names8[] = {
2921   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2922 };
2923 static const char *intel_names8rex[] = {
2924   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2925   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2926 };
2927 static const char *intel_names_seg[] = {
2928   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2929 };
2930 static const char *intel_index64 = "riz";
2931 static const char *intel_index32 = "eiz";
2932 static const char *intel_index16[] = {
2933   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2934 };
2935
2936 static const char *att_names64[] = {
2937   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2938   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2939 };
2940 static const char *att_names32[] = {
2941   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2942   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2943 };
2944 static const char *att_names16[] = {
2945   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2946   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2947 };
2948 static const char *att_names8[] = {
2949   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2950 };
2951 static const char *att_names8rex[] = {
2952   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2953   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2954 };
2955 static const char *att_names_seg[] = {
2956   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2957 };
2958 static const char *att_index64 = "%riz";
2959 static const char *att_index32 = "%eiz";
2960 static const char *att_index16[] = {
2961   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2962 };
2963
2964 static const char **names_mm;
2965 static const char *intel_names_mm[] = {
2966   "mm0", "mm1", "mm2", "mm3",
2967   "mm4", "mm5", "mm6", "mm7"
2968 };
2969 static const char *att_names_mm[] = {
2970   "%mm0", "%mm1", "%mm2", "%mm3",
2971   "%mm4", "%mm5", "%mm6", "%mm7"
2972 };
2973
2974 static const char *intel_names_bnd[] = {
2975   "bnd0", "bnd1", "bnd2", "bnd3"
2976 };
2977
2978 static const char *att_names_bnd[] = {
2979   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2980 };
2981
2982 static const char **names_xmm;
2983 static const char *intel_names_xmm[] = {
2984   "xmm0", "xmm1", "xmm2", "xmm3",
2985   "xmm4", "xmm5", "xmm6", "xmm7",
2986   "xmm8", "xmm9", "xmm10", "xmm11",
2987   "xmm12", "xmm13", "xmm14", "xmm15",
2988   "xmm16", "xmm17", "xmm18", "xmm19",
2989   "xmm20", "xmm21", "xmm22", "xmm23",
2990   "xmm24", "xmm25", "xmm26", "xmm27",
2991   "xmm28", "xmm29", "xmm30", "xmm31"
2992 };
2993 static const char *att_names_xmm[] = {
2994   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2995   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2996   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2997   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2998   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2999   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3000   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3001   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3002 };
3003
3004 static const char **names_ymm;
3005 static const char *intel_names_ymm[] = {
3006   "ymm0", "ymm1", "ymm2", "ymm3",
3007   "ymm4", "ymm5", "ymm6", "ymm7",
3008   "ymm8", "ymm9", "ymm10", "ymm11",
3009   "ymm12", "ymm13", "ymm14", "ymm15",
3010   "ymm16", "ymm17", "ymm18", "ymm19",
3011   "ymm20", "ymm21", "ymm22", "ymm23",
3012   "ymm24", "ymm25", "ymm26", "ymm27",
3013   "ymm28", "ymm29", "ymm30", "ymm31"
3014 };
3015 static const char *att_names_ymm[] = {
3016   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3017   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3018   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3019   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3020   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3021   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3022   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3023   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3024 };
3025
3026 static const char **names_zmm;
3027 static const char *intel_names_zmm[] = {
3028   "zmm0", "zmm1", "zmm2", "zmm3",
3029   "zmm4", "zmm5", "zmm6", "zmm7",
3030   "zmm8", "zmm9", "zmm10", "zmm11",
3031   "zmm12", "zmm13", "zmm14", "zmm15",
3032   "zmm16", "zmm17", "zmm18", "zmm19",
3033   "zmm20", "zmm21", "zmm22", "zmm23",
3034   "zmm24", "zmm25", "zmm26", "zmm27",
3035   "zmm28", "zmm29", "zmm30", "zmm31"
3036 };
3037 static const char *att_names_zmm[] = {
3038   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3039   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3040   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3041   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3042   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3043   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3044   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3045   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3046 };
3047
3048 static const char **names_mask;
3049 static const char *intel_names_mask[] = {
3050   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3051 };
3052 static const char *att_names_mask[] = {
3053   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3054 };
3055
3056 static const char *names_rounding[] =
3057 {
3058   "{rn-sae}",
3059   "{rd-sae}",
3060   "{ru-sae}",
3061   "{rz-sae}"
3062 };
3063
3064 static const struct dis386 reg_table[][8] = {
3065   /* REG_80 */
3066   {
3067     { "addA",   { Ebh1, Ib }, 0 },
3068     { "orA",    { Ebh1, Ib }, 0 },
3069     { "adcA",   { Ebh1, Ib }, 0 },
3070     { "sbbA",   { Ebh1, Ib }, 0 },
3071     { "andA",   { Ebh1, Ib }, 0 },
3072     { "subA",   { Ebh1, Ib }, 0 },
3073     { "xorA",   { Ebh1, Ib }, 0 },
3074     { "cmpA",   { Eb, Ib }, 0 },
3075   },
3076   /* REG_81 */
3077   {
3078     { "addQ",   { Evh1, Iv }, 0 },
3079     { "orQ",    { Evh1, Iv }, 0 },
3080     { "adcQ",   { Evh1, Iv }, 0 },
3081     { "sbbQ",   { Evh1, Iv }, 0 },
3082     { "andQ",   { Evh1, Iv }, 0 },
3083     { "subQ",   { Evh1, Iv }, 0 },
3084     { "xorQ",   { Evh1, Iv }, 0 },
3085     { "cmpQ",   { Ev, Iv }, 0 },
3086   },
3087   /* REG_83 */
3088   {
3089     { "addQ",   { Evh1, sIb }, 0 },
3090     { "orQ",    { Evh1, sIb }, 0 },
3091     { "adcQ",   { Evh1, sIb }, 0 },
3092     { "sbbQ",   { Evh1, sIb }, 0 },
3093     { "andQ",   { Evh1, sIb }, 0 },
3094     { "subQ",   { Evh1, sIb }, 0 },
3095     { "xorQ",   { Evh1, sIb }, 0 },
3096     { "cmpQ",   { Ev, sIb }, 0 },
3097   },
3098   /* REG_8F */
3099   {
3100     { "popU",   { stackEv }, 0 },
3101     { XOP_8F_TABLE (XOP_09) },
3102     { Bad_Opcode },
3103     { Bad_Opcode },
3104     { Bad_Opcode },
3105     { XOP_8F_TABLE (XOP_09) },
3106   },
3107   /* REG_C0 */
3108   {
3109     { "rolA",   { Eb, Ib }, 0 },
3110     { "rorA",   { Eb, Ib }, 0 },
3111     { "rclA",   { Eb, Ib }, 0 },
3112     { "rcrA",   { Eb, Ib }, 0 },
3113     { "shlA",   { Eb, Ib }, 0 },
3114     { "shrA",   { Eb, Ib }, 0 },
3115     { "shlA",   { Eb, Ib }, 0 },
3116     { "sarA",   { Eb, Ib }, 0 },
3117   },
3118   /* REG_C1 */
3119   {
3120     { "rolQ",   { Ev, Ib }, 0 },
3121     { "rorQ",   { Ev, Ib }, 0 },
3122     { "rclQ",   { Ev, Ib }, 0 },
3123     { "rcrQ",   { Ev, Ib }, 0 },
3124     { "shlQ",   { Ev, Ib }, 0 },
3125     { "shrQ",   { Ev, Ib }, 0 },
3126     { "shlQ",   { Ev, Ib }, 0 },
3127     { "sarQ",   { Ev, Ib }, 0 },
3128   },
3129   /* REG_C6 */
3130   {
3131     { "movA",   { Ebh3, Ib }, 0 },
3132     { Bad_Opcode },
3133     { Bad_Opcode },
3134     { Bad_Opcode },
3135     { Bad_Opcode },
3136     { Bad_Opcode },
3137     { Bad_Opcode },
3138     { MOD_TABLE (MOD_C6_REG_7) },
3139   },
3140   /* REG_C7 */
3141   {
3142     { "movQ",   { Evh3, Iv }, 0 },
3143     { Bad_Opcode },
3144     { Bad_Opcode },
3145     { Bad_Opcode },
3146     { Bad_Opcode },
3147     { Bad_Opcode },
3148     { Bad_Opcode },
3149     { MOD_TABLE (MOD_C7_REG_7) },
3150   },
3151   /* REG_D0 */
3152   {
3153     { "rolA",   { Eb, I1 }, 0 },
3154     { "rorA",   { Eb, I1 }, 0 },
3155     { "rclA",   { Eb, I1 }, 0 },
3156     { "rcrA",   { Eb, I1 }, 0 },
3157     { "shlA",   { Eb, I1 }, 0 },
3158     { "shrA",   { Eb, I1 }, 0 },
3159     { "shlA",   { Eb, I1 }, 0 },
3160     { "sarA",   { Eb, I1 }, 0 },
3161   },
3162   /* REG_D1 */
3163   {
3164     { "rolQ",   { Ev, I1 }, 0 },
3165     { "rorQ",   { Ev, I1 }, 0 },
3166     { "rclQ",   { Ev, I1 }, 0 },
3167     { "rcrQ",   { Ev, I1 }, 0 },
3168     { "shlQ",   { Ev, I1 }, 0 },
3169     { "shrQ",   { Ev, I1 }, 0 },
3170     { "shlQ",   { Ev, I1 }, 0 },
3171     { "sarQ",   { Ev, I1 }, 0 },
3172   },
3173   /* REG_D2 */
3174   {
3175     { "rolA",   { Eb, CL }, 0 },
3176     { "rorA",   { Eb, CL }, 0 },
3177     { "rclA",   { Eb, CL }, 0 },
3178     { "rcrA",   { Eb, CL }, 0 },
3179     { "shlA",   { Eb, CL }, 0 },
3180     { "shrA",   { Eb, CL }, 0 },
3181     { "shlA",   { Eb, CL }, 0 },
3182     { "sarA",   { Eb, CL }, 0 },
3183   },
3184   /* REG_D3 */
3185   {
3186     { "rolQ",   { Ev, CL }, 0 },
3187     { "rorQ",   { Ev, CL }, 0 },
3188     { "rclQ",   { Ev, CL }, 0 },
3189     { "rcrQ",   { Ev, CL }, 0 },
3190     { "shlQ",   { Ev, CL }, 0 },
3191     { "shrQ",   { Ev, CL }, 0 },
3192     { "shlQ",   { Ev, CL }, 0 },
3193     { "sarQ",   { Ev, CL }, 0 },
3194   },
3195   /* REG_F6 */
3196   {
3197     { "testA",  { Eb, Ib }, 0 },
3198     { "testA",  { Eb, Ib }, 0 },
3199     { "notA",   { Ebh1 }, 0 },
3200     { "negA",   { Ebh1 }, 0 },
3201     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3202     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3203     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3204     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3205   },
3206   /* REG_F7 */
3207   {
3208     { "testQ",  { Ev, Iv }, 0 },
3209     { "testQ",  { Ev, Iv }, 0 },
3210     { "notQ",   { Evh1 }, 0 },
3211     { "negQ",   { Evh1 }, 0 },
3212     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3213     { "imulQ",  { Ev }, 0 },
3214     { "divQ",   { Ev }, 0 },
3215     { "idivQ",  { Ev }, 0 },
3216   },
3217   /* REG_FE */
3218   {
3219     { "incA",   { Ebh1 }, 0 },
3220     { "decA",   { Ebh1 }, 0 },
3221   },
3222   /* REG_FF */
3223   {
3224     { "incQ",   { Evh1 }, 0 },
3225     { "decQ",   { Evh1 }, 0 },
3226     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3227     { MOD_TABLE (MOD_FF_REG_3) },
3228     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3229     { MOD_TABLE (MOD_FF_REG_5) },
3230     { "pushU",  { stackEv }, 0 },
3231     { Bad_Opcode },
3232   },
3233   /* REG_0F00 */
3234   {
3235     { "sldtD",  { Sv }, 0 },
3236     { "strD",   { Sv }, 0 },
3237     { "lldt",   { Ew }, 0 },
3238     { "ltr",    { Ew }, 0 },
3239     { "verr",   { Ew }, 0 },
3240     { "verw",   { Ew }, 0 },
3241     { Bad_Opcode },
3242     { Bad_Opcode },
3243   },
3244   /* REG_0F01 */
3245   {
3246     { MOD_TABLE (MOD_0F01_REG_0) },
3247     { MOD_TABLE (MOD_0F01_REG_1) },
3248     { MOD_TABLE (MOD_0F01_REG_2) },
3249     { MOD_TABLE (MOD_0F01_REG_3) },
3250     { "smswD",  { Sv }, 0 },
3251     { MOD_TABLE (MOD_0F01_REG_5) },
3252     { "lmsw",   { Ew }, 0 },
3253     { MOD_TABLE (MOD_0F01_REG_7) },
3254   },
3255   /* REG_0F0D */
3256   {
3257     { "prefetch",       { Mb }, 0 },
3258     { "prefetchw",      { Mb }, 0 },
3259     { "prefetchwt1",    { Mb }, 0 },
3260     { "prefetch",       { Mb }, 0 },
3261     { "prefetch",       { Mb }, 0 },
3262     { "prefetch",       { Mb }, 0 },
3263     { "prefetch",       { Mb }, 0 },
3264     { "prefetch",       { Mb }, 0 },
3265   },
3266   /* REG_0F18 */
3267   {
3268     { MOD_TABLE (MOD_0F18_REG_0) },
3269     { MOD_TABLE (MOD_0F18_REG_1) },
3270     { MOD_TABLE (MOD_0F18_REG_2) },
3271     { MOD_TABLE (MOD_0F18_REG_3) },
3272     { MOD_TABLE (MOD_0F18_REG_4) },
3273     { MOD_TABLE (MOD_0F18_REG_5) },
3274     { MOD_TABLE (MOD_0F18_REG_6) },
3275     { MOD_TABLE (MOD_0F18_REG_7) },
3276   },
3277   /* REG_0F1C_P_0_MOD_0 */
3278   {
3279     { "cldemote",       { Mb }, 0 },
3280     { "nopQ",           { Ev }, 0 },
3281     { "nopQ",           { Ev }, 0 },
3282     { "nopQ",           { Ev }, 0 },
3283     { "nopQ",           { Ev }, 0 },
3284     { "nopQ",           { Ev }, 0 },
3285     { "nopQ",           { Ev }, 0 },
3286     { "nopQ",           { Ev }, 0 },
3287   },
3288   /* REG_0F1E_P_1_MOD_3 */
3289   {
3290     { "nopQ",           { Ev }, 0 },
3291     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3292     { "nopQ",           { Ev }, 0 },
3293     { "nopQ",           { Ev }, 0 },
3294     { "nopQ",           { Ev }, 0 },
3295     { "nopQ",           { Ev }, 0 },
3296     { "nopQ",           { Ev }, 0 },
3297     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3298   },
3299   /* REG_0F71 */
3300   {
3301     { Bad_Opcode },
3302     { Bad_Opcode },
3303     { MOD_TABLE (MOD_0F71_REG_2) },
3304     { Bad_Opcode },
3305     { MOD_TABLE (MOD_0F71_REG_4) },
3306     { Bad_Opcode },
3307     { MOD_TABLE (MOD_0F71_REG_6) },
3308   },
3309   /* REG_0F72 */
3310   {
3311     { Bad_Opcode },
3312     { Bad_Opcode },
3313     { MOD_TABLE (MOD_0F72_REG_2) },
3314     { Bad_Opcode },
3315     { MOD_TABLE (MOD_0F72_REG_4) },
3316     { Bad_Opcode },
3317     { MOD_TABLE (MOD_0F72_REG_6) },
3318   },
3319   /* REG_0F73 */
3320   {
3321     { Bad_Opcode },
3322     { Bad_Opcode },
3323     { MOD_TABLE (MOD_0F73_REG_2) },
3324     { MOD_TABLE (MOD_0F73_REG_3) },
3325     { Bad_Opcode },
3326     { Bad_Opcode },
3327     { MOD_TABLE (MOD_0F73_REG_6) },
3328     { MOD_TABLE (MOD_0F73_REG_7) },
3329   },
3330   /* REG_0FA6 */
3331   {
3332     { "montmul",        { { OP_0f07, 0 } }, 0 },
3333     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3334     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3335   },
3336   /* REG_0FA7 */
3337   {
3338     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3339     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3340     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3341     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3342     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3343     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3344   },
3345   /* REG_0FAE */
3346   {
3347     { MOD_TABLE (MOD_0FAE_REG_0) },
3348     { MOD_TABLE (MOD_0FAE_REG_1) },
3349     { MOD_TABLE (MOD_0FAE_REG_2) },
3350     { MOD_TABLE (MOD_0FAE_REG_3) },
3351     { MOD_TABLE (MOD_0FAE_REG_4) },
3352     { MOD_TABLE (MOD_0FAE_REG_5) },
3353     { MOD_TABLE (MOD_0FAE_REG_6) },
3354     { MOD_TABLE (MOD_0FAE_REG_7) },
3355   },
3356   /* REG_0FBA */
3357   {
3358     { Bad_Opcode },
3359     { Bad_Opcode },
3360     { Bad_Opcode },
3361     { Bad_Opcode },
3362     { "btQ",    { Ev, Ib }, 0 },
3363     { "btsQ",   { Evh1, Ib }, 0 },
3364     { "btrQ",   { Evh1, Ib }, 0 },
3365     { "btcQ",   { Evh1, Ib }, 0 },
3366   },
3367   /* REG_0FC7 */
3368   {
3369     { Bad_Opcode },
3370     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3371     { Bad_Opcode },
3372     { MOD_TABLE (MOD_0FC7_REG_3) },
3373     { MOD_TABLE (MOD_0FC7_REG_4) },
3374     { MOD_TABLE (MOD_0FC7_REG_5) },
3375     { MOD_TABLE (MOD_0FC7_REG_6) },
3376     { MOD_TABLE (MOD_0FC7_REG_7) },
3377   },
3378   /* REG_VEX_0F71 */
3379   {
3380     { Bad_Opcode },
3381     { Bad_Opcode },
3382     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3383     { Bad_Opcode },
3384     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3385     { Bad_Opcode },
3386     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3387   },
3388   /* REG_VEX_0F72 */
3389   {
3390     { Bad_Opcode },
3391     { Bad_Opcode },
3392     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3393     { Bad_Opcode },
3394     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3395     { Bad_Opcode },
3396     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3397   },
3398   /* REG_VEX_0F73 */
3399   {
3400     { Bad_Opcode },
3401     { Bad_Opcode },
3402     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3403     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3404     { Bad_Opcode },
3405     { Bad_Opcode },
3406     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3407     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3408   },
3409   /* REG_VEX_0FAE */
3410   {
3411     { Bad_Opcode },
3412     { Bad_Opcode },
3413     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3414     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3415   },
3416   /* REG_VEX_0F38F3 */
3417   {
3418     { Bad_Opcode },
3419     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3420     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3421     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3422   },
3423   /* REG_XOP_LWPCB */
3424   {
3425     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3426     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3427   },
3428   /* REG_XOP_LWP */
3429   {
3430     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3431     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3432   },
3433   /* REG_XOP_TBM_01 */
3434   {
3435     { Bad_Opcode },
3436     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3437     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3438     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3439     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3440     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3441     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3442     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3443   },
3444   /* REG_XOP_TBM_02 */
3445   {
3446     { Bad_Opcode },
3447     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3448     { Bad_Opcode },
3449     { Bad_Opcode },
3450     { Bad_Opcode },
3451     { Bad_Opcode },
3452     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3453   },
3454
3455 #include "i386-dis-evex-reg.h"
3456 };
3457
3458 static const struct dis386 prefix_table[][4] = {
3459   /* PREFIX_90 */
3460   {
3461     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3462     { "pause", { XX }, 0 },
3463     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3464     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3465   },
3466
3467   /* PREFIX_0F01_REG_3_RM_1 */
3468   {
3469     { "vmmcall",        { Skip_MODRM }, 0 },
3470     { "vmgexit",        { Skip_MODRM }, 0 },
3471     { Bad_Opcode },
3472     { "vmgexit",        { Skip_MODRM }, 0 },
3473   },
3474
3475   /* PREFIX_0F01_REG_5_MOD_0 */
3476   {
3477     { Bad_Opcode },
3478     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3479   },
3480
3481   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3482   {
3483     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3484     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3485     { Bad_Opcode },
3486     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3487   },
3488
3489   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3490   {
3491     { Bad_Opcode },
3492     { Bad_Opcode },
3493     { Bad_Opcode },
3494     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3495   },
3496
3497   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3498   {
3499     { Bad_Opcode },
3500     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3501   },
3502
3503   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3504   {
3505     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3506     { "mcommit",        { Skip_MODRM }, 0 },
3507   },
3508
3509   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3510   {
3511     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3512   },
3513
3514   /* PREFIX_0F09 */
3515   {
3516     { "wbinvd",   { XX }, 0 },
3517     { "wbnoinvd", { XX }, 0 },
3518   },
3519
3520   /* PREFIX_0F10 */
3521   {
3522     { "movups", { XM, EXx }, PREFIX_OPCODE },
3523     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3524     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3525     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3526   },
3527
3528   /* PREFIX_0F11 */
3529   {
3530     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3531     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3532     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3533     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3534   },
3535
3536   /* PREFIX_0F12 */
3537   {
3538     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3539     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3540     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3541     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3542   },
3543
3544   /* PREFIX_0F16 */
3545   {
3546     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3547     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3548     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3549   },
3550
3551   /* PREFIX_0F1A */
3552   {
3553     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3554     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3555     { "bndmov", { Gbnd, Ebnd }, 0 },
3556     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3557   },
3558
3559   /* PREFIX_0F1B */
3560   {
3561     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3562     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3563     { "bndmov", { EbndS, Gbnd }, 0 },
3564     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3565   },
3566
3567   /* PREFIX_0F1C */
3568   {
3569     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3570     { "nopQ",   { Ev }, PREFIX_OPCODE },
3571     { "nopQ",   { Ev }, PREFIX_OPCODE },
3572     { "nopQ",   { Ev }, PREFIX_OPCODE },
3573   },
3574
3575   /* PREFIX_0F1E */
3576   {
3577     { "nopQ",   { Ev }, PREFIX_OPCODE },
3578     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3579     { "nopQ",   { Ev }, PREFIX_OPCODE },
3580     { "nopQ",   { Ev }, PREFIX_OPCODE },
3581   },
3582
3583   /* PREFIX_0F2A */
3584   {
3585     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3586     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3587     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3588     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3589   },
3590
3591   /* PREFIX_0F2B */
3592   {
3593     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3594     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3595     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3596     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3597   },
3598
3599   /* PREFIX_0F2C */
3600   {
3601     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3602     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3603     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3604     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3605   },
3606
3607   /* PREFIX_0F2D */
3608   {
3609     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3610     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3611     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3612     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3613   },
3614
3615   /* PREFIX_0F2E */
3616   {
3617     { "ucomiss",{ XM, EXd }, 0 },
3618     { Bad_Opcode },
3619     { "ucomisd",{ XM, EXq }, 0 },
3620   },
3621
3622   /* PREFIX_0F2F */
3623   {
3624     { "comiss", { XM, EXd }, 0 },
3625     { Bad_Opcode },
3626     { "comisd", { XM, EXq }, 0 },
3627   },
3628
3629   /* PREFIX_0F51 */
3630   {
3631     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3632     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3633     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3634     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3635   },
3636
3637   /* PREFIX_0F52 */
3638   {
3639     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3640     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3641   },
3642
3643   /* PREFIX_0F53 */
3644   {
3645     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3646     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3647   },
3648
3649   /* PREFIX_0F58 */
3650   {
3651     { "addps", { XM, EXx }, PREFIX_OPCODE },
3652     { "addss", { XM, EXd }, PREFIX_OPCODE },
3653     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3654     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3655   },
3656
3657   /* PREFIX_0F59 */
3658   {
3659     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3660     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3661     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3662     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3663   },
3664
3665   /* PREFIX_0F5A */
3666   {
3667     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3668     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3669     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3670     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3671   },
3672
3673   /* PREFIX_0F5B */
3674   {
3675     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3676     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3677     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3678   },
3679
3680   /* PREFIX_0F5C */
3681   {
3682     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3683     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3684     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3685     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3686   },
3687
3688   /* PREFIX_0F5D */
3689   {
3690     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3691     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3692     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3693     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3694   },
3695
3696   /* PREFIX_0F5E */
3697   {
3698     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3699     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3700     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3701     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3702   },
3703
3704   /* PREFIX_0F5F */
3705   {
3706     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3707     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3708     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3709     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3710   },
3711
3712   /* PREFIX_0F60 */
3713   {
3714     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3715     { Bad_Opcode },
3716     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3717   },
3718
3719   /* PREFIX_0F61 */
3720   {
3721     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3722     { Bad_Opcode },
3723     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3724   },
3725
3726   /* PREFIX_0F62 */
3727   {
3728     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3729     { Bad_Opcode },
3730     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3731   },
3732
3733   /* PREFIX_0F6C */
3734   {
3735     { Bad_Opcode },
3736     { Bad_Opcode },
3737     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3738   },
3739
3740   /* PREFIX_0F6D */
3741   {
3742     { Bad_Opcode },
3743     { Bad_Opcode },
3744     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3745   },
3746
3747   /* PREFIX_0F6F */
3748   {
3749     { "movq",   { MX, EM }, PREFIX_OPCODE },
3750     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3751     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3752   },
3753
3754   /* PREFIX_0F70 */
3755   {
3756     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3757     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3758     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3759     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3760   },
3761
3762   /* PREFIX_0F73_REG_3 */
3763   {
3764     { Bad_Opcode },
3765     { Bad_Opcode },
3766     { "psrldq", { XS, Ib }, 0 },
3767   },
3768
3769   /* PREFIX_0F73_REG_7 */
3770   {
3771     { Bad_Opcode },
3772     { Bad_Opcode },
3773     { "pslldq", { XS, Ib }, 0 },
3774   },
3775
3776   /* PREFIX_0F78 */
3777   {
3778     {"vmread",  { Em, Gm }, 0 },
3779     { Bad_Opcode },
3780     {"extrq",   { XS, Ib, Ib }, 0 },
3781     {"insertq", { XM, XS, Ib, Ib }, 0 },
3782   },
3783
3784   /* PREFIX_0F79 */
3785   {
3786     {"vmwrite", { Gm, Em }, 0 },
3787     { Bad_Opcode },
3788     {"extrq",   { XM, XS }, 0 },
3789     {"insertq", { XM, XS }, 0 },
3790   },
3791
3792   /* PREFIX_0F7C */
3793   {
3794     { Bad_Opcode },
3795     { Bad_Opcode },
3796     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3797     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3798   },
3799
3800   /* PREFIX_0F7D */
3801   {
3802     { Bad_Opcode },
3803     { Bad_Opcode },
3804     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3805     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3806   },
3807
3808   /* PREFIX_0F7E */
3809   {
3810     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3811     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3812     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3813   },
3814
3815   /* PREFIX_0F7F */
3816   {
3817     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3818     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3819     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3820   },
3821
3822   /* PREFIX_0FAE_REG_0_MOD_3 */
3823   {
3824     { Bad_Opcode },
3825     { "rdfsbase", { Ev }, 0 },
3826   },
3827
3828   /* PREFIX_0FAE_REG_1_MOD_3 */
3829   {
3830     { Bad_Opcode },
3831     { "rdgsbase", { Ev }, 0 },
3832   },
3833
3834   /* PREFIX_0FAE_REG_2_MOD_3 */
3835   {
3836     { Bad_Opcode },
3837     { "wrfsbase", { Ev }, 0 },
3838   },
3839
3840   /* PREFIX_0FAE_REG_3_MOD_3 */
3841   {
3842     { Bad_Opcode },
3843     { "wrgsbase", { Ev }, 0 },
3844   },
3845
3846   /* PREFIX_0FAE_REG_4_MOD_0 */
3847   {
3848     { "xsave",  { FXSAVE }, 0 },
3849     { "ptwrite%LQ", { Edq }, 0 },
3850   },
3851
3852   /* PREFIX_0FAE_REG_4_MOD_3 */
3853   {
3854     { Bad_Opcode },
3855     { "ptwrite%LQ", { Edq }, 0 },
3856   },
3857
3858   /* PREFIX_0FAE_REG_5_MOD_0 */
3859   {
3860     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3861   },
3862
3863   /* PREFIX_0FAE_REG_5_MOD_3 */
3864   {
3865     { "lfence",         { Skip_MODRM }, 0 },
3866     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3867   },
3868
3869   /* PREFIX_0FAE_REG_6_MOD_0 */
3870   {
3871     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3872     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3873     { "clwb",   { Mb }, PREFIX_OPCODE },
3874   },
3875
3876   /* PREFIX_0FAE_REG_6_MOD_3 */
3877   {
3878     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3879     { "umonitor",       { Eva }, PREFIX_OPCODE },
3880     { "tpause", { Edq }, PREFIX_OPCODE },
3881     { "umwait", { Edq }, PREFIX_OPCODE },
3882   },
3883
3884   /* PREFIX_0FAE_REG_7_MOD_0 */
3885   {
3886     { "clflush",        { Mb }, 0 },
3887     { Bad_Opcode },
3888     { "clflushopt",     { Mb }, 0 },
3889   },
3890
3891   /* PREFIX_0FB8 */
3892   {
3893     { Bad_Opcode },
3894     { "popcntS", { Gv, Ev }, 0 },
3895   },
3896
3897   /* PREFIX_0FBC */
3898   {
3899     { "bsfS",   { Gv, Ev }, 0 },
3900     { "tzcntS", { Gv, Ev }, 0 },
3901     { "bsfS",   { Gv, Ev }, 0 },
3902   },
3903
3904   /* PREFIX_0FBD */
3905   {
3906     { "bsrS",   { Gv, Ev }, 0 },
3907     { "lzcntS", { Gv, Ev }, 0 },
3908     { "bsrS",   { Gv, Ev }, 0 },
3909   },
3910
3911   /* PREFIX_0FC2 */
3912   {
3913     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3914     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3915     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3916     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3917   },
3918
3919   /* PREFIX_0FC3_MOD_0 */
3920   {
3921     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
3922   },
3923
3924   /* PREFIX_0FC7_REG_6_MOD_0 */
3925   {
3926     { "vmptrld",{ Mq }, 0 },
3927     { "vmxon",  { Mq }, 0 },
3928     { "vmclear",{ Mq }, 0 },
3929   },
3930
3931   /* PREFIX_0FC7_REG_6_MOD_3 */
3932   {
3933     { "rdrand", { Ev }, 0 },
3934     { Bad_Opcode },
3935     { "rdrand", { Ev }, 0 }
3936   },
3937
3938   /* PREFIX_0FC7_REG_7_MOD_3 */
3939   {
3940     { "rdseed", { Ev }, 0 },
3941     { "rdpid",  { Em }, 0 },
3942     { "rdseed", { Ev }, 0 },
3943   },
3944
3945   /* PREFIX_0FD0 */
3946   {
3947     { Bad_Opcode },
3948     { Bad_Opcode },
3949     { "addsubpd", { XM, EXx }, 0 },
3950     { "addsubps", { XM, EXx }, 0 },
3951   },
3952
3953   /* PREFIX_0FD6 */
3954   {
3955     { Bad_Opcode },
3956     { "movq2dq",{ XM, MS }, 0 },
3957     { "movq",   { EXqS, XM }, 0 },
3958     { "movdq2q",{ MX, XS }, 0 },
3959   },
3960
3961   /* PREFIX_0FE6 */
3962   {
3963     { Bad_Opcode },
3964     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3965     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3966     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3967   },
3968
3969   /* PREFIX_0FE7 */
3970   {
3971     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3972     { Bad_Opcode },
3973     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3974   },
3975
3976   /* PREFIX_0FF0 */
3977   {
3978     { Bad_Opcode },
3979     { Bad_Opcode },
3980     { Bad_Opcode },
3981     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3982   },
3983
3984   /* PREFIX_0FF7 */
3985   {
3986     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3987     { Bad_Opcode },
3988     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3989   },
3990
3991   /* PREFIX_0F3810 */
3992   {
3993     { Bad_Opcode },
3994     { Bad_Opcode },
3995     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
3996   },
3997
3998   /* PREFIX_0F3814 */
3999   {
4000     { Bad_Opcode },
4001     { Bad_Opcode },
4002     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4003   },
4004
4005   /* PREFIX_0F3815 */
4006   {
4007     { Bad_Opcode },
4008     { Bad_Opcode },
4009     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4010   },
4011
4012   /* PREFIX_0F3817 */
4013   {
4014     { Bad_Opcode },
4015     { Bad_Opcode },
4016     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4017   },
4018
4019   /* PREFIX_0F3820 */
4020   {
4021     { Bad_Opcode },
4022     { Bad_Opcode },
4023     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4024   },
4025
4026   /* PREFIX_0F3821 */
4027   {
4028     { Bad_Opcode },
4029     { Bad_Opcode },
4030     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4031   },
4032
4033   /* PREFIX_0F3822 */
4034   {
4035     { Bad_Opcode },
4036     { Bad_Opcode },
4037     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4038   },
4039
4040   /* PREFIX_0F3823 */
4041   {
4042     { Bad_Opcode },
4043     { Bad_Opcode },
4044     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4045   },
4046
4047   /* PREFIX_0F3824 */
4048   {
4049     { Bad_Opcode },
4050     { Bad_Opcode },
4051     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4052   },
4053
4054   /* PREFIX_0F3825 */
4055   {
4056     { Bad_Opcode },
4057     { Bad_Opcode },
4058     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4059   },
4060
4061   /* PREFIX_0F3828 */
4062   {
4063     { Bad_Opcode },
4064     { Bad_Opcode },
4065     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4066   },
4067
4068   /* PREFIX_0F3829 */
4069   {
4070     { Bad_Opcode },
4071     { Bad_Opcode },
4072     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4073   },
4074
4075   /* PREFIX_0F382A */
4076   {
4077     { Bad_Opcode },
4078     { Bad_Opcode },
4079     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4080   },
4081
4082   /* PREFIX_0F382B */
4083   {
4084     { Bad_Opcode },
4085     { Bad_Opcode },
4086     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4087   },
4088
4089   /* PREFIX_0F3830 */
4090   {
4091     { Bad_Opcode },
4092     { Bad_Opcode },
4093     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4094   },
4095
4096   /* PREFIX_0F3831 */
4097   {
4098     { Bad_Opcode },
4099     { Bad_Opcode },
4100     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4101   },
4102
4103   /* PREFIX_0F3832 */
4104   {
4105     { Bad_Opcode },
4106     { Bad_Opcode },
4107     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4108   },
4109
4110   /* PREFIX_0F3833 */
4111   {
4112     { Bad_Opcode },
4113     { Bad_Opcode },
4114     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4115   },
4116
4117   /* PREFIX_0F3834 */
4118   {
4119     { Bad_Opcode },
4120     { Bad_Opcode },
4121     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4122   },
4123
4124   /* PREFIX_0F3835 */
4125   {
4126     { Bad_Opcode },
4127     { Bad_Opcode },
4128     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4129   },
4130
4131   /* PREFIX_0F3837 */
4132   {
4133     { Bad_Opcode },
4134     { Bad_Opcode },
4135     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4136   },
4137
4138   /* PREFIX_0F3838 */
4139   {
4140     { Bad_Opcode },
4141     { Bad_Opcode },
4142     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4143   },
4144
4145   /* PREFIX_0F3839 */
4146   {
4147     { Bad_Opcode },
4148     { Bad_Opcode },
4149     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4150   },
4151
4152   /* PREFIX_0F383A */
4153   {
4154     { Bad_Opcode },
4155     { Bad_Opcode },
4156     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4157   },
4158
4159   /* PREFIX_0F383B */
4160   {
4161     { Bad_Opcode },
4162     { Bad_Opcode },
4163     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4164   },
4165
4166   /* PREFIX_0F383C */
4167   {
4168     { Bad_Opcode },
4169     { Bad_Opcode },
4170     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4171   },
4172
4173   /* PREFIX_0F383D */
4174   {
4175     { Bad_Opcode },
4176     { Bad_Opcode },
4177     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4178   },
4179
4180   /* PREFIX_0F383E */
4181   {
4182     { Bad_Opcode },
4183     { Bad_Opcode },
4184     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4185   },
4186
4187   /* PREFIX_0F383F */
4188   {
4189     { Bad_Opcode },
4190     { Bad_Opcode },
4191     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4192   },
4193
4194   /* PREFIX_0F3840 */
4195   {
4196     { Bad_Opcode },
4197     { Bad_Opcode },
4198     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4199   },
4200
4201   /* PREFIX_0F3841 */
4202   {
4203     { Bad_Opcode },
4204     { Bad_Opcode },
4205     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4206   },
4207
4208   /* PREFIX_0F3880 */
4209   {
4210     { Bad_Opcode },
4211     { Bad_Opcode },
4212     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4213   },
4214
4215   /* PREFIX_0F3881 */
4216   {
4217     { Bad_Opcode },
4218     { Bad_Opcode },
4219     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4220   },
4221
4222   /* PREFIX_0F3882 */
4223   {
4224     { Bad_Opcode },
4225     { Bad_Opcode },
4226     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4227   },
4228
4229   /* PREFIX_0F38C8 */
4230   {
4231     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4232   },
4233
4234   /* PREFIX_0F38C9 */
4235   {
4236     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4237   },
4238
4239   /* PREFIX_0F38CA */
4240   {
4241     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4242   },
4243
4244   /* PREFIX_0F38CB */
4245   {
4246     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4247   },
4248
4249   /* PREFIX_0F38CC */
4250   {
4251     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4252   },
4253
4254   /* PREFIX_0F38CD */
4255   {
4256     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4257   },
4258
4259   /* PREFIX_0F38CF */
4260   {
4261     { Bad_Opcode },
4262     { Bad_Opcode },
4263     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4264   },
4265
4266   /* PREFIX_0F38DB */
4267   {
4268     { Bad_Opcode },
4269     { Bad_Opcode },
4270     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4271   },
4272
4273   /* PREFIX_0F38DC */
4274   {
4275     { Bad_Opcode },
4276     { Bad_Opcode },
4277     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4278   },
4279
4280   /* PREFIX_0F38DD */
4281   {
4282     { Bad_Opcode },
4283     { Bad_Opcode },
4284     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4285   },
4286
4287   /* PREFIX_0F38DE */
4288   {
4289     { Bad_Opcode },
4290     { Bad_Opcode },
4291     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4292   },
4293
4294   /* PREFIX_0F38DF */
4295   {
4296     { Bad_Opcode },
4297     { Bad_Opcode },
4298     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4299   },
4300
4301   /* PREFIX_0F38F0 */
4302   {
4303     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4304     { Bad_Opcode },
4305     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4306     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4307   },
4308
4309   /* PREFIX_0F38F1 */
4310   {
4311     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4312     { Bad_Opcode },
4313     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4314     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4315   },
4316
4317   /* PREFIX_0F38F5 */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4322   },
4323
4324   /* PREFIX_0F38F6 */
4325   {
4326     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4327     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4328     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4329     { Bad_Opcode },
4330   },
4331
4332   /* PREFIX_0F38F8 */
4333   {
4334     { Bad_Opcode },
4335     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4336     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4337     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4338   },
4339
4340   /* PREFIX_0F38F9 */
4341   {
4342     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4343   },
4344
4345   /* PREFIX_0F3A08 */
4346   {
4347     { Bad_Opcode },
4348     { Bad_Opcode },
4349     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4350   },
4351
4352   /* PREFIX_0F3A09 */
4353   {
4354     { Bad_Opcode },
4355     { Bad_Opcode },
4356     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4357   },
4358
4359   /* PREFIX_0F3A0A */
4360   {
4361     { Bad_Opcode },
4362     { Bad_Opcode },
4363     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4364   },
4365
4366   /* PREFIX_0F3A0B */
4367   {
4368     { Bad_Opcode },
4369     { Bad_Opcode },
4370     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4371   },
4372
4373   /* PREFIX_0F3A0C */
4374   {
4375     { Bad_Opcode },
4376     { Bad_Opcode },
4377     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4378   },
4379
4380   /* PREFIX_0F3A0D */
4381   {
4382     { Bad_Opcode },
4383     { Bad_Opcode },
4384     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4385   },
4386
4387   /* PREFIX_0F3A0E */
4388   {
4389     { Bad_Opcode },
4390     { Bad_Opcode },
4391     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4392   },
4393
4394   /* PREFIX_0F3A14 */
4395   {
4396     { Bad_Opcode },
4397     { Bad_Opcode },
4398     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4399   },
4400
4401   /* PREFIX_0F3A15 */
4402   {
4403     { Bad_Opcode },
4404     { Bad_Opcode },
4405     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4406   },
4407
4408   /* PREFIX_0F3A16 */
4409   {
4410     { Bad_Opcode },
4411     { Bad_Opcode },
4412     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4413   },
4414
4415   /* PREFIX_0F3A17 */
4416   {
4417     { Bad_Opcode },
4418     { Bad_Opcode },
4419     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4420   },
4421
4422   /* PREFIX_0F3A20 */
4423   {
4424     { Bad_Opcode },
4425     { Bad_Opcode },
4426     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4427   },
4428
4429   /* PREFIX_0F3A21 */
4430   {
4431     { Bad_Opcode },
4432     { Bad_Opcode },
4433     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4434   },
4435
4436   /* PREFIX_0F3A22 */
4437   {
4438     { Bad_Opcode },
4439     { Bad_Opcode },
4440     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4441   },
4442
4443   /* PREFIX_0F3A40 */
4444   {
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4448   },
4449
4450   /* PREFIX_0F3A41 */
4451   {
4452     { Bad_Opcode },
4453     { Bad_Opcode },
4454     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4455   },
4456
4457   /* PREFIX_0F3A42 */
4458   {
4459     { Bad_Opcode },
4460     { Bad_Opcode },
4461     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4462   },
4463
4464   /* PREFIX_0F3A44 */
4465   {
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4469   },
4470
4471   /* PREFIX_0F3A60 */
4472   {
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4476   },
4477
4478   /* PREFIX_0F3A61 */
4479   {
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4483   },
4484
4485   /* PREFIX_0F3A62 */
4486   {
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4490   },
4491
4492   /* PREFIX_0F3A63 */
4493   {
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4497   },
4498
4499   /* PREFIX_0F3ACC */
4500   {
4501     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4502   },
4503
4504   /* PREFIX_0F3ACE */
4505   {
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4509   },
4510
4511   /* PREFIX_0F3ACF */
4512   {
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4516   },
4517
4518   /* PREFIX_0F3ADF */
4519   {
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4523   },
4524
4525   /* PREFIX_VEX_0F10 */
4526   {
4527     { "vmovups",        { XM, EXx }, 0 },
4528     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4529     { "vmovupd",        { XM, EXx }, 0 },
4530     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4531   },
4532
4533   /* PREFIX_VEX_0F11 */
4534   {
4535     { "vmovups",        { EXxS, XM }, 0 },
4536     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4537     { "vmovupd",        { EXxS, XM }, 0 },
4538     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4539   },
4540
4541   /* PREFIX_VEX_0F12 */
4542   {
4543     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4544     { "vmovsldup",      { XM, EXx }, 0 },
4545     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4546     { "vmovddup",       { XM, EXymmq }, 0 },
4547   },
4548
4549   /* PREFIX_VEX_0F16 */
4550   {
4551     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4552     { "vmovshdup",      { XM, EXx }, 0 },
4553     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4554   },
4555
4556   /* PREFIX_VEX_0F2A */
4557   {
4558     { Bad_Opcode },
4559     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4560     { Bad_Opcode },
4561     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4562   },
4563
4564   /* PREFIX_VEX_0F2C */
4565   {
4566     { Bad_Opcode },
4567     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4568     { Bad_Opcode },
4569     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4570   },
4571
4572   /* PREFIX_VEX_0F2D */
4573   {
4574     { Bad_Opcode },
4575     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4576     { Bad_Opcode },
4577     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4578   },
4579
4580   /* PREFIX_VEX_0F2E */
4581   {
4582     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4583     { Bad_Opcode },
4584     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4585   },
4586
4587   /* PREFIX_VEX_0F2F */
4588   {
4589     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4590     { Bad_Opcode },
4591     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4592   },
4593
4594   /* PREFIX_VEX_0F41 */
4595   {
4596     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4597     { Bad_Opcode },
4598     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4599   },
4600
4601   /* PREFIX_VEX_0F42 */
4602   {
4603     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4604     { Bad_Opcode },
4605     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4606   },
4607
4608   /* PREFIX_VEX_0F44 */
4609   {
4610     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4611     { Bad_Opcode },
4612     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4613   },
4614
4615   /* PREFIX_VEX_0F45 */
4616   {
4617     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4618     { Bad_Opcode },
4619     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4620   },
4621
4622   /* PREFIX_VEX_0F46 */
4623   {
4624     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4625     { Bad_Opcode },
4626     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4627   },
4628
4629   /* PREFIX_VEX_0F47 */
4630   {
4631     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4632     { Bad_Opcode },
4633     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4634   },
4635
4636   /* PREFIX_VEX_0F4A */
4637   {
4638     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4639     { Bad_Opcode },
4640     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4641   },
4642
4643   /* PREFIX_VEX_0F4B */
4644   {
4645     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4646     { Bad_Opcode },
4647     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4648   },
4649
4650   /* PREFIX_VEX_0F51 */
4651   {
4652     { "vsqrtps",        { XM, EXx }, 0 },
4653     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4654     { "vsqrtpd",        { XM, EXx }, 0 },
4655     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4656   },
4657
4658   /* PREFIX_VEX_0F52 */
4659   {
4660     { "vrsqrtps",       { XM, EXx }, 0 },
4661     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4662   },
4663
4664   /* PREFIX_VEX_0F53 */
4665   {
4666     { "vrcpps",         { XM, EXx }, 0 },
4667     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4668   },
4669
4670   /* PREFIX_VEX_0F58 */
4671   {
4672     { "vaddps",         { XM, Vex, EXx }, 0 },
4673     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4674     { "vaddpd",         { XM, Vex, EXx }, 0 },
4675     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4676   },
4677
4678   /* PREFIX_VEX_0F59 */
4679   {
4680     { "vmulps",         { XM, Vex, EXx }, 0 },
4681     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4682     { "vmulpd",         { XM, Vex, EXx }, 0 },
4683     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4684   },
4685
4686   /* PREFIX_VEX_0F5A */
4687   {
4688     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4689     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4690     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4691     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4692   },
4693
4694   /* PREFIX_VEX_0F5B */
4695   {
4696     { "vcvtdq2ps",      { XM, EXx }, 0 },
4697     { "vcvttps2dq",     { XM, EXx }, 0 },
4698     { "vcvtps2dq",      { XM, EXx }, 0 },
4699   },
4700
4701   /* PREFIX_VEX_0F5C */
4702   {
4703     { "vsubps",         { XM, Vex, EXx }, 0 },
4704     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4705     { "vsubpd",         { XM, Vex, EXx }, 0 },
4706     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4707   },
4708
4709   /* PREFIX_VEX_0F5D */
4710   {
4711     { "vminps",         { XM, Vex, EXx }, 0 },
4712     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4713     { "vminpd",         { XM, Vex, EXx }, 0 },
4714     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4715   },
4716
4717   /* PREFIX_VEX_0F5E */
4718   {
4719     { "vdivps",         { XM, Vex, EXx }, 0 },
4720     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4721     { "vdivpd",         { XM, Vex, EXx }, 0 },
4722     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4723   },
4724
4725   /* PREFIX_VEX_0F5F */
4726   {
4727     { "vmaxps",         { XM, Vex, EXx }, 0 },
4728     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4729     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4730     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4731   },
4732
4733   /* PREFIX_VEX_0F60 */
4734   {
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4738   },
4739
4740   /* PREFIX_VEX_0F61 */
4741   {
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4745   },
4746
4747   /* PREFIX_VEX_0F62 */
4748   {
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4752   },
4753
4754   /* PREFIX_VEX_0F63 */
4755   {
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4759   },
4760
4761   /* PREFIX_VEX_0F64 */
4762   {
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4766   },
4767
4768   /* PREFIX_VEX_0F65 */
4769   {
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4773   },
4774
4775   /* PREFIX_VEX_0F66 */
4776   {
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4780   },
4781
4782   /* PREFIX_VEX_0F67 */
4783   {
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4787   },
4788
4789   /* PREFIX_VEX_0F68 */
4790   {
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4794   },
4795
4796   /* PREFIX_VEX_0F69 */
4797   {
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4801   },
4802
4803   /* PREFIX_VEX_0F6A */
4804   {
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4808   },
4809
4810   /* PREFIX_VEX_0F6B */
4811   {
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4815   },
4816
4817   /* PREFIX_VEX_0F6C */
4818   {
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4822   },
4823
4824   /* PREFIX_VEX_0F6D */
4825   {
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4829   },
4830
4831   /* PREFIX_VEX_0F6E */
4832   {
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4836   },
4837
4838   /* PREFIX_VEX_0F6F */
4839   {
4840     { Bad_Opcode },
4841     { "vmovdqu",        { XM, EXx }, 0 },
4842     { "vmovdqa",        { XM, EXx }, 0 },
4843   },
4844
4845   /* PREFIX_VEX_0F70 */
4846   {
4847     { Bad_Opcode },
4848     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4849     { "vpshufd",        { XM, EXx, Ib }, 0 },
4850     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4851   },
4852
4853   /* PREFIX_VEX_0F71_REG_2 */
4854   {
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4858   },
4859
4860   /* PREFIX_VEX_0F71_REG_4 */
4861   {
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { "vpsraw",         { Vex, XS, Ib }, 0 },
4865   },
4866
4867   /* PREFIX_VEX_0F71_REG_6 */
4868   {
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { "vpsllw",         { Vex, XS, Ib }, 0 },
4872   },
4873
4874   /* PREFIX_VEX_0F72_REG_2 */
4875   {
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { "vpsrld",         { Vex, XS, Ib }, 0 },
4879   },
4880
4881   /* PREFIX_VEX_0F72_REG_4 */
4882   {
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { "vpsrad",         { Vex, XS, Ib }, 0 },
4886   },
4887
4888   /* PREFIX_VEX_0F72_REG_6 */
4889   {
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { "vpslld",         { Vex, XS, Ib }, 0 },
4893   },
4894
4895   /* PREFIX_VEX_0F73_REG_2 */
4896   {
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { "vpsrlq",         { Vex, XS, Ib }, 0 },
4900   },
4901
4902   /* PREFIX_VEX_0F73_REG_3 */
4903   {
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { "vpsrldq",        { Vex, XS, Ib }, 0 },
4907   },
4908
4909   /* PREFIX_VEX_0F73_REG_6 */
4910   {
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { "vpsllq",         { Vex, XS, Ib }, 0 },
4914   },
4915
4916   /* PREFIX_VEX_0F73_REG_7 */
4917   {
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { "vpslldq",        { Vex, XS, Ib }, 0 },
4921   },
4922
4923   /* PREFIX_VEX_0F74 */
4924   {
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
4928   },
4929
4930   /* PREFIX_VEX_0F75 */
4931   {
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
4935   },
4936
4937   /* PREFIX_VEX_0F76 */
4938   {
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
4942   },
4943
4944   /* PREFIX_VEX_0F77 */
4945   {
4946     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
4947   },
4948
4949   /* PREFIX_VEX_0F7C */
4950   {
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { "vhaddpd",        { XM, Vex, EXx }, 0 },
4954     { "vhaddps",        { XM, Vex, EXx }, 0 },
4955   },
4956
4957   /* PREFIX_VEX_0F7D */
4958   {
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { "vhsubpd",        { XM, Vex, EXx }, 0 },
4962     { "vhsubps",        { XM, Vex, EXx }, 0 },
4963   },
4964
4965   /* PREFIX_VEX_0F7E */
4966   {
4967     { Bad_Opcode },
4968     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4969     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4970   },
4971
4972   /* PREFIX_VEX_0F7F */
4973   {
4974     { Bad_Opcode },
4975     { "vmovdqu",        { EXxS, XM }, 0 },
4976     { "vmovdqa",        { EXxS, XM }, 0 },
4977   },
4978
4979   /* PREFIX_VEX_0F90 */
4980   {
4981     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4982     { Bad_Opcode },
4983     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
4984   },
4985
4986   /* PREFIX_VEX_0F91 */
4987   {
4988     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4989     { Bad_Opcode },
4990     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
4991   },
4992
4993   /* PREFIX_VEX_0F92 */
4994   {
4995     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4996     { Bad_Opcode },
4997     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
4998     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
4999   },
5000
5001   /* PREFIX_VEX_0F93 */
5002   {
5003     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5004     { Bad_Opcode },
5005     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5006     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5007   },
5008
5009   /* PREFIX_VEX_0F98 */
5010   {
5011     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5012     { Bad_Opcode },
5013     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5014   },
5015
5016   /* PREFIX_VEX_0F99 */
5017   {
5018     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5019     { Bad_Opcode },
5020     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5021   },
5022
5023   /* PREFIX_VEX_0FC2 */
5024   {
5025     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5026     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 },
5027     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5028     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 },
5029   },
5030
5031   /* PREFIX_VEX_0FC4 */
5032   {
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5036   },
5037
5038   /* PREFIX_VEX_0FC5 */
5039   {
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5043   },
5044
5045   /* PREFIX_VEX_0FD0 */
5046   {
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5050     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5051   },
5052
5053   /* PREFIX_VEX_0FD1 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5058   },
5059
5060   /* PREFIX_VEX_0FD2 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5065   },
5066
5067   /* PREFIX_VEX_0FD3 */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5072   },
5073
5074   /* PREFIX_VEX_0FD4 */
5075   {
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { "vpaddq",         { XM, Vex, EXx }, 0 },
5079   },
5080
5081   /* PREFIX_VEX_0FD5 */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { "vpmullw",        { XM, Vex, EXx }, 0 },
5086   },
5087
5088   /* PREFIX_VEX_0FD6 */
5089   {
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5093   },
5094
5095   /* PREFIX_VEX_0FD7 */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5100   },
5101
5102   /* PREFIX_VEX_0FD8 */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5107   },
5108
5109   /* PREFIX_VEX_0FD9 */
5110   {
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5114   },
5115
5116   /* PREFIX_VEX_0FDA */
5117   {
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { "vpminub",        { XM, Vex, EXx }, 0 },
5121   },
5122
5123   /* PREFIX_VEX_0FDB */
5124   {
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { "vpand",          { XM, Vex, EXx }, 0 },
5128   },
5129
5130   /* PREFIX_VEX_0FDC */
5131   {
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5135   },
5136
5137   /* PREFIX_VEX_0FDD */
5138   {
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5142   },
5143
5144   /* PREFIX_VEX_0FDE */
5145   {
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5149   },
5150
5151   /* PREFIX_VEX_0FDF */
5152   {
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { "vpandn",         { XM, Vex, EXx }, 0 },
5156   },
5157
5158   /* PREFIX_VEX_0FE0 */
5159   {
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { "vpavgb",         { XM, Vex, EXx }, 0 },
5163   },
5164
5165   /* PREFIX_VEX_0FE1 */
5166   {
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5170   },
5171
5172   /* PREFIX_VEX_0FE2 */
5173   {
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5177   },
5178
5179   /* PREFIX_VEX_0FE3 */
5180   {
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { "vpavgw",         { XM, Vex, EXx }, 0 },
5184   },
5185
5186   /* PREFIX_VEX_0FE4 */
5187   {
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5191   },
5192
5193   /* PREFIX_VEX_0FE5 */
5194   {
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5198   },
5199
5200   /* PREFIX_VEX_0FE6 */
5201   {
5202     { Bad_Opcode },
5203     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5204     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5205     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5206   },
5207
5208   /* PREFIX_VEX_0FE7 */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5213   },
5214
5215   /* PREFIX_VEX_0FE8 */
5216   {
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5220   },
5221
5222   /* PREFIX_VEX_0FE9 */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5227   },
5228
5229   /* PREFIX_VEX_0FEA */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { "vpminsw",        { XM, Vex, EXx }, 0 },
5234   },
5235
5236   /* PREFIX_VEX_0FEB */
5237   {
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { "vpor",           { XM, Vex, EXx }, 0 },
5241   },
5242
5243   /* PREFIX_VEX_0FEC */
5244   {
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5248   },
5249
5250   /* PREFIX_VEX_0FED */
5251   {
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5255   },
5256
5257   /* PREFIX_VEX_0FEE */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5262   },
5263
5264   /* PREFIX_VEX_0FEF */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { "vpxor",          { XM, Vex, EXx }, 0 },
5269   },
5270
5271   /* PREFIX_VEX_0FF0 */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5277   },
5278
5279   /* PREFIX_VEX_0FF1 */
5280   {
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5284   },
5285
5286   /* PREFIX_VEX_0FF2 */
5287   {
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5291   },
5292
5293   /* PREFIX_VEX_0FF3 */
5294   {
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5298   },
5299
5300   /* PREFIX_VEX_0FF4 */
5301   {
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5305   },
5306
5307   /* PREFIX_VEX_0FF5 */
5308   {
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5312   },
5313
5314   /* PREFIX_VEX_0FF6 */
5315   {
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5319   },
5320
5321   /* PREFIX_VEX_0FF7 */
5322   {
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5326   },
5327
5328   /* PREFIX_VEX_0FF8 */
5329   {
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { "vpsubb",         { XM, Vex, EXx }, 0 },
5333   },
5334
5335   /* PREFIX_VEX_0FF9 */
5336   {
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { "vpsubw",         { XM, Vex, EXx }, 0 },
5340   },
5341
5342   /* PREFIX_VEX_0FFA */
5343   {
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { "vpsubd",         { XM, Vex, EXx }, 0 },
5347   },
5348
5349   /* PREFIX_VEX_0FFB */
5350   {
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { "vpsubq",         { XM, Vex, EXx }, 0 },
5354   },
5355
5356   /* PREFIX_VEX_0FFC */
5357   {
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { "vpaddb",         { XM, Vex, EXx }, 0 },
5361   },
5362
5363   /* PREFIX_VEX_0FFD */
5364   {
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { "vpaddw",         { XM, Vex, EXx }, 0 },
5368   },
5369
5370   /* PREFIX_VEX_0FFE */
5371   {
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { "vpaddd",         { XM, Vex, EXx }, 0 },
5375   },
5376
5377   /* PREFIX_VEX_0F3800 */
5378   {
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { "vpshufb",        { XM, Vex, EXx }, 0 },
5382   },
5383
5384   /* PREFIX_VEX_0F3801 */
5385   {
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { "vphaddw",        { XM, Vex, EXx }, 0 },
5389   },
5390
5391   /* PREFIX_VEX_0F3802 */
5392   {
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { "vphaddd",        { XM, Vex, EXx }, 0 },
5396   },
5397
5398   /* PREFIX_VEX_0F3803 */
5399   {
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5403   },
5404
5405   /* PREFIX_VEX_0F3804 */
5406   {
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5410   },
5411
5412   /* PREFIX_VEX_0F3805 */
5413   {
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { "vphsubw",        { XM, Vex, EXx }, 0 },
5417   },
5418
5419   /* PREFIX_VEX_0F3806 */
5420   {
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { "vphsubd",        { XM, Vex, EXx }, 0 },
5424   },
5425
5426   /* PREFIX_VEX_0F3807 */
5427   {
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5431   },
5432
5433   /* PREFIX_VEX_0F3808 */
5434   {
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { "vpsignb",        { XM, Vex, EXx }, 0 },
5438   },
5439
5440   /* PREFIX_VEX_0F3809 */
5441   {
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { "vpsignw",        { XM, Vex, EXx }, 0 },
5445   },
5446
5447   /* PREFIX_VEX_0F380A */
5448   {
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { "vpsignd",        { XM, Vex, EXx }, 0 },
5452   },
5453
5454   /* PREFIX_VEX_0F380B */
5455   {
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5459   },
5460
5461   /* PREFIX_VEX_0F380C */
5462   {
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5466   },
5467
5468   /* PREFIX_VEX_0F380D */
5469   {
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5473   },
5474
5475   /* PREFIX_VEX_0F380E */
5476   {
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5480   },
5481
5482   /* PREFIX_VEX_0F380F */
5483   {
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5487   },
5488
5489   /* PREFIX_VEX_0F3813 */
5490   {
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { VEX_W_TABLE (VEX_W_0F3813_P_2) },
5494   },
5495
5496   /* PREFIX_VEX_0F3816 */
5497   {
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5501   },
5502
5503   /* PREFIX_VEX_0F3817 */
5504   {
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { "vptest",         { XM, EXx }, 0 },
5508   },
5509
5510   /* PREFIX_VEX_0F3818 */
5511   {
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5515   },
5516
5517   /* PREFIX_VEX_0F3819 */
5518   {
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5522   },
5523
5524   /* PREFIX_VEX_0F381A */
5525   {
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5529   },
5530
5531   /* PREFIX_VEX_0F381C */
5532   {
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { "vpabsb",         { XM, EXx }, 0 },
5536   },
5537
5538   /* PREFIX_VEX_0F381D */
5539   {
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { "vpabsw",         { XM, EXx }, 0 },
5543   },
5544
5545   /* PREFIX_VEX_0F381E */
5546   {
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { "vpabsd",         { XM, EXx }, 0 },
5550   },
5551
5552   /* PREFIX_VEX_0F3820 */
5553   {
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5557   },
5558
5559   /* PREFIX_VEX_0F3821 */
5560   {
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5564   },
5565
5566   /* PREFIX_VEX_0F3822 */
5567   {
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5571   },
5572
5573   /* PREFIX_VEX_0F3823 */
5574   {
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5578   },
5579
5580   /* PREFIX_VEX_0F3824 */
5581   {
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5585   },
5586
5587   /* PREFIX_VEX_0F3825 */
5588   {
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5592   },
5593
5594   /* PREFIX_VEX_0F3828 */
5595   {
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5599   },
5600
5601   /* PREFIX_VEX_0F3829 */
5602   {
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5606   },
5607
5608   /* PREFIX_VEX_0F382A */
5609   {
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5613   },
5614
5615   /* PREFIX_VEX_0F382B */
5616   {
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5620   },
5621
5622   /* PREFIX_VEX_0F382C */
5623   {
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5627   },
5628
5629   /* PREFIX_VEX_0F382D */
5630   {
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5634   },
5635
5636   /* PREFIX_VEX_0F382E */
5637   {
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5641   },
5642
5643   /* PREFIX_VEX_0F382F */
5644   {
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5648   },
5649
5650   /* PREFIX_VEX_0F3830 */
5651   {
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5655   },
5656
5657   /* PREFIX_VEX_0F3831 */
5658   {
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5662   },
5663
5664   /* PREFIX_VEX_0F3832 */
5665   {
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5669   },
5670
5671   /* PREFIX_VEX_0F3833 */
5672   {
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5676   },
5677
5678   /* PREFIX_VEX_0F3834 */
5679   {
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5683   },
5684
5685   /* PREFIX_VEX_0F3835 */
5686   {
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5690   },
5691
5692   /* PREFIX_VEX_0F3836 */
5693   {
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5697   },
5698
5699   /* PREFIX_VEX_0F3837 */
5700   {
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5704   },
5705
5706   /* PREFIX_VEX_0F3838 */
5707   {
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { "vpminsb",        { XM, Vex, EXx }, 0 },
5711   },
5712
5713   /* PREFIX_VEX_0F3839 */
5714   {
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { "vpminsd",        { XM, Vex, EXx }, 0 },
5718   },
5719
5720   /* PREFIX_VEX_0F383A */
5721   {
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { "vpminuw",        { XM, Vex, EXx }, 0 },
5725   },
5726
5727   /* PREFIX_VEX_0F383B */
5728   {
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { "vpminud",        { XM, Vex, EXx }, 0 },
5732   },
5733
5734   /* PREFIX_VEX_0F383C */
5735   {
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5739   },
5740
5741   /* PREFIX_VEX_0F383D */
5742   {
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5746   },
5747
5748   /* PREFIX_VEX_0F383E */
5749   {
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5753   },
5754
5755   /* PREFIX_VEX_0F383F */
5756   {
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5760   },
5761
5762   /* PREFIX_VEX_0F3840 */
5763   {
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { "vpmulld",        { XM, Vex, EXx }, 0 },
5767   },
5768
5769   /* PREFIX_VEX_0F3841 */
5770   {
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5774   },
5775
5776   /* PREFIX_VEX_0F3845 */
5777   {
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5781   },
5782
5783   /* PREFIX_VEX_0F3846 */
5784   {
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5788   },
5789
5790   /* PREFIX_VEX_0F3847 */
5791   {
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5795   },
5796
5797   /* PREFIX_VEX_0F3858 */
5798   {
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5802   },
5803
5804   /* PREFIX_VEX_0F3859 */
5805   {
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5809   },
5810
5811   /* PREFIX_VEX_0F385A */
5812   {
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5816   },
5817
5818   /* PREFIX_VEX_0F3878 */
5819   {
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5823   },
5824
5825   /* PREFIX_VEX_0F3879 */
5826   {
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5830   },
5831
5832   /* PREFIX_VEX_0F388C */
5833   {
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5837   },
5838
5839   /* PREFIX_VEX_0F388E */
5840   {
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5844   },
5845
5846   /* PREFIX_VEX_0F3890 */
5847   {
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5851   },
5852
5853   /* PREFIX_VEX_0F3891 */
5854   {
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5858   },
5859
5860   /* PREFIX_VEX_0F3892 */
5861   {
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5865   },
5866
5867   /* PREFIX_VEX_0F3893 */
5868   {
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5872   },
5873
5874   /* PREFIX_VEX_0F3896 */
5875   {
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5879   },
5880
5881   /* PREFIX_VEX_0F3897 */
5882   {
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5886   },
5887
5888   /* PREFIX_VEX_0F3898 */
5889   {
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5893   },
5894
5895   /* PREFIX_VEX_0F3899 */
5896   {
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5900   },
5901
5902   /* PREFIX_VEX_0F389A */
5903   {
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5907   },
5908
5909   /* PREFIX_VEX_0F389B */
5910   {
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5914   },
5915
5916   /* PREFIX_VEX_0F389C */
5917   {
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5921   },
5922
5923   /* PREFIX_VEX_0F389D */
5924   {
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5928   },
5929
5930   /* PREFIX_VEX_0F389E */
5931   {
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5935   },
5936
5937   /* PREFIX_VEX_0F389F */
5938   {
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5942   },
5943
5944   /* PREFIX_VEX_0F38A6 */
5945   {
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5949     { Bad_Opcode },
5950   },
5951
5952   /* PREFIX_VEX_0F38A7 */
5953   {
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5957   },
5958
5959   /* PREFIX_VEX_0F38A8 */
5960   {
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5964   },
5965
5966   /* PREFIX_VEX_0F38A9 */
5967   {
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5971   },
5972
5973   /* PREFIX_VEX_0F38AA */
5974   {
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
5978   },
5979
5980   /* PREFIX_VEX_0F38AB */
5981   {
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5985   },
5986
5987   /* PREFIX_VEX_0F38AC */
5988   {
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5992   },
5993
5994   /* PREFIX_VEX_0F38AD */
5995   {
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5999   },
6000
6001   /* PREFIX_VEX_0F38AE */
6002   {
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6006   },
6007
6008   /* PREFIX_VEX_0F38AF */
6009   {
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6013   },
6014
6015   /* PREFIX_VEX_0F38B6 */
6016   {
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6020   },
6021
6022   /* PREFIX_VEX_0F38B7 */
6023   {
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6027   },
6028
6029   /* PREFIX_VEX_0F38B8 */
6030   {
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6034   },
6035
6036   /* PREFIX_VEX_0F38B9 */
6037   {
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6041   },
6042
6043   /* PREFIX_VEX_0F38BA */
6044   {
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6048   },
6049
6050   /* PREFIX_VEX_0F38BB */
6051   {
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6055   },
6056
6057   /* PREFIX_VEX_0F38BC */
6058   {
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6062   },
6063
6064   /* PREFIX_VEX_0F38BD */
6065   {
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6069   },
6070
6071   /* PREFIX_VEX_0F38BE */
6072   {
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6076   },
6077
6078   /* PREFIX_VEX_0F38BF */
6079   {
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6083   },
6084
6085   /* PREFIX_VEX_0F38CF */
6086   {
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6090   },
6091
6092   /* PREFIX_VEX_0F38DB */
6093   {
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6097   },
6098
6099   /* PREFIX_VEX_0F38DC */
6100   {
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { "vaesenc",        { XM, Vex, EXx }, 0 },
6104   },
6105
6106   /* PREFIX_VEX_0F38DD */
6107   {
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6111   },
6112
6113   /* PREFIX_VEX_0F38DE */
6114   {
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { "vaesdec",        { XM, Vex, EXx }, 0 },
6118   },
6119
6120   /* PREFIX_VEX_0F38DF */
6121   {
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6125   },
6126
6127   /* PREFIX_VEX_0F38F2 */
6128   {
6129     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6130   },
6131
6132   /* PREFIX_VEX_0F38F3_REG_1 */
6133   {
6134     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6135   },
6136
6137   /* PREFIX_VEX_0F38F3_REG_2 */
6138   {
6139     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6140   },
6141
6142   /* PREFIX_VEX_0F38F3_REG_3 */
6143   {
6144     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6145   },
6146
6147   /* PREFIX_VEX_0F38F5 */
6148   {
6149     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6150     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6151     { Bad_Opcode },
6152     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6153   },
6154
6155   /* PREFIX_VEX_0F38F6 */
6156   {
6157     { Bad_Opcode },
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6161   },
6162
6163   /* PREFIX_VEX_0F38F7 */
6164   {
6165     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6166     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6167     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6168     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6169   },
6170
6171   /* PREFIX_VEX_0F3A00 */
6172   {
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6176   },
6177
6178   /* PREFIX_VEX_0F3A01 */
6179   {
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6183   },
6184
6185   /* PREFIX_VEX_0F3A02 */
6186   {
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6190   },
6191
6192   /* PREFIX_VEX_0F3A04 */
6193   {
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6197   },
6198
6199   /* PREFIX_VEX_0F3A05 */
6200   {
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6204   },
6205
6206   /* PREFIX_VEX_0F3A06 */
6207   {
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6211   },
6212
6213   /* PREFIX_VEX_0F3A08 */
6214   {
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { "vroundps",       { XM, EXx, Ib }, 0 },
6218   },
6219
6220   /* PREFIX_VEX_0F3A09 */
6221   {
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { "vroundpd",       { XM, EXx, Ib }, 0 },
6225   },
6226
6227   /* PREFIX_VEX_0F3A0A */
6228   {
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6232   },
6233
6234   /* PREFIX_VEX_0F3A0B */
6235   {
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6239   },
6240
6241   /* PREFIX_VEX_0F3A0C */
6242   {
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6246   },
6247
6248   /* PREFIX_VEX_0F3A0D */
6249   {
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6253   },
6254
6255   /* PREFIX_VEX_0F3A0E */
6256   {
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6260   },
6261
6262   /* PREFIX_VEX_0F3A0F */
6263   {
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6267   },
6268
6269   /* PREFIX_VEX_0F3A14 */
6270   {
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6274   },
6275
6276   /* PREFIX_VEX_0F3A15 */
6277   {
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6281   },
6282
6283   /* PREFIX_VEX_0F3A16 */
6284   {
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6288   },
6289
6290   /* PREFIX_VEX_0F3A17 */
6291   {
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6295   },
6296
6297   /* PREFIX_VEX_0F3A18 */
6298   {
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6302   },
6303
6304   /* PREFIX_VEX_0F3A19 */
6305   {
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6309   },
6310
6311   /* PREFIX_VEX_0F3A1D */
6312   {
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
6316   },
6317
6318   /* PREFIX_VEX_0F3A20 */
6319   {
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6323   },
6324
6325   /* PREFIX_VEX_0F3A21 */
6326   {
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6330   },
6331
6332   /* PREFIX_VEX_0F3A22 */
6333   {
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6337   },
6338
6339   /* PREFIX_VEX_0F3A30 */
6340   {
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6344   },
6345
6346   /* PREFIX_VEX_0F3A31 */
6347   {
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6351   },
6352
6353   /* PREFIX_VEX_0F3A32 */
6354   {
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6358   },
6359
6360   /* PREFIX_VEX_0F3A33 */
6361   {
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6365   },
6366
6367   /* PREFIX_VEX_0F3A38 */
6368   {
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6372   },
6373
6374   /* PREFIX_VEX_0F3A39 */
6375   {
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6379   },
6380
6381   /* PREFIX_VEX_0F3A40 */
6382   {
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6386   },
6387
6388   /* PREFIX_VEX_0F3A41 */
6389   {
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6393   },
6394
6395   /* PREFIX_VEX_0F3A42 */
6396   {
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6400   },
6401
6402   /* PREFIX_VEX_0F3A44 */
6403   {
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6407   },
6408
6409   /* PREFIX_VEX_0F3A46 */
6410   {
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6414   },
6415
6416   /* PREFIX_VEX_0F3A48 */
6417   {
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6421   },
6422
6423   /* PREFIX_VEX_0F3A49 */
6424   {
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6428   },
6429
6430   /* PREFIX_VEX_0F3A4A */
6431   {
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6435   },
6436
6437   /* PREFIX_VEX_0F3A4B */
6438   {
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6442   },
6443
6444   /* PREFIX_VEX_0F3A4C */
6445   {
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6449   },
6450
6451   /* PREFIX_VEX_0F3A5C */
6452   {
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6456   },
6457
6458   /* PREFIX_VEX_0F3A5D */
6459   {
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6463   },
6464
6465   /* PREFIX_VEX_0F3A5E */
6466   {
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6470   },
6471
6472   /* PREFIX_VEX_0F3A5F */
6473   {
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6477   },
6478
6479   /* PREFIX_VEX_0F3A60 */
6480   {
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6484     { Bad_Opcode },
6485   },
6486
6487   /* PREFIX_VEX_0F3A61 */
6488   {
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6492   },
6493
6494   /* PREFIX_VEX_0F3A62 */
6495   {
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6499   },
6500
6501   /* PREFIX_VEX_0F3A63 */
6502   {
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6506   },
6507
6508   /* PREFIX_VEX_0F3A68 */
6509   {
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6513   },
6514
6515   /* PREFIX_VEX_0F3A69 */
6516   {
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6520   },
6521
6522   /* PREFIX_VEX_0F3A6A */
6523   {
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6527   },
6528
6529   /* PREFIX_VEX_0F3A6B */
6530   {
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6534   },
6535
6536   /* PREFIX_VEX_0F3A6C */
6537   {
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6541   },
6542
6543   /* PREFIX_VEX_0F3A6D */
6544   {
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6548   },
6549
6550   /* PREFIX_VEX_0F3A6E */
6551   {
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6555   },
6556
6557   /* PREFIX_VEX_0F3A6F */
6558   {
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6562   },
6563
6564   /* PREFIX_VEX_0F3A78 */
6565   {
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6569   },
6570
6571   /* PREFIX_VEX_0F3A79 */
6572   {
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6576   },
6577
6578   /* PREFIX_VEX_0F3A7A */
6579   {
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6583   },
6584
6585   /* PREFIX_VEX_0F3A7B */
6586   {
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6590   },
6591
6592   /* PREFIX_VEX_0F3A7C */
6593   {
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6597     { Bad_Opcode },
6598   },
6599
6600   /* PREFIX_VEX_0F3A7D */
6601   {
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6605   },
6606
6607   /* PREFIX_VEX_0F3A7E */
6608   {
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6612   },
6613
6614   /* PREFIX_VEX_0F3A7F */
6615   {
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6619   },
6620
6621   /* PREFIX_VEX_0F3ACE */
6622   {
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6626   },
6627
6628   /* PREFIX_VEX_0F3ACF */
6629   {
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6633   },
6634
6635   /* PREFIX_VEX_0F3ADF */
6636   {
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6640   },
6641
6642   /* PREFIX_VEX_0F3AF0 */
6643   {
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6648   },
6649
6650 #include "i386-dis-evex-prefix.h"
6651 };
6652
6653 static const struct dis386 x86_64_table[][2] = {
6654   /* X86_64_06 */
6655   {
6656     { "pushP", { es }, 0 },
6657   },
6658
6659   /* X86_64_07 */
6660   {
6661     { "popP", { es }, 0 },
6662   },
6663
6664   /* X86_64_0E */
6665   {
6666     { "pushP", { cs }, 0 },
6667   },
6668
6669   /* X86_64_16 */
6670   {
6671     { "pushP", { ss }, 0 },
6672   },
6673
6674   /* X86_64_17 */
6675   {
6676     { "popP", { ss }, 0 },
6677   },
6678
6679   /* X86_64_1E */
6680   {
6681     { "pushP", { ds }, 0 },
6682   },
6683
6684   /* X86_64_1F */
6685   {
6686     { "popP", { ds }, 0 },
6687   },
6688
6689   /* X86_64_27 */
6690   {
6691     { "daa", { XX }, 0 },
6692   },
6693
6694   /* X86_64_2F */
6695   {
6696     { "das", { XX }, 0 },
6697   },
6698
6699   /* X86_64_37 */
6700   {
6701     { "aaa", { XX }, 0 },
6702   },
6703
6704   /* X86_64_3F */
6705   {
6706     { "aas", { XX }, 0 },
6707   },
6708
6709   /* X86_64_60 */
6710   {
6711     { "pushaP", { XX }, 0 },
6712   },
6713
6714   /* X86_64_61 */
6715   {
6716     { "popaP", { XX }, 0 },
6717   },
6718
6719   /* X86_64_62 */
6720   {
6721     { MOD_TABLE (MOD_62_32BIT) },
6722     { EVEX_TABLE (EVEX_0F) },
6723   },
6724
6725   /* X86_64_63 */
6726   {
6727     { "arpl", { Ew, Gw }, 0 },
6728     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6729   },
6730
6731   /* X86_64_6D */
6732   {
6733     { "ins{R|}", { Yzr, indirDX }, 0 },
6734     { "ins{G|}", { Yzr, indirDX }, 0 },
6735   },
6736
6737   /* X86_64_6F */
6738   {
6739     { "outs{R|}", { indirDXr, Xz }, 0 },
6740     { "outs{G|}", { indirDXr, Xz }, 0 },
6741   },
6742
6743   /* X86_64_82 */
6744   {
6745     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6746     { REG_TABLE (REG_80) },
6747   },
6748
6749   /* X86_64_9A */
6750   {
6751     { "{l|}call{T|}", { Ap }, 0 },
6752   },
6753
6754   /* X86_64_C2 */
6755   {
6756     { "retP",           { Iw, BND }, 0 },
6757     { "ret@",           { Iw, BND }, 0 },
6758   },
6759
6760   /* X86_64_C3 */
6761   {
6762     { "retP",           { BND }, 0 },
6763     { "ret@",           { BND }, 0 },
6764   },
6765
6766   /* X86_64_C4 */
6767   {
6768     { MOD_TABLE (MOD_C4_32BIT) },
6769     { VEX_C4_TABLE (VEX_0F) },
6770   },
6771
6772   /* X86_64_C5 */
6773   {
6774     { MOD_TABLE (MOD_C5_32BIT) },
6775     { VEX_C5_TABLE (VEX_0F) },
6776   },
6777
6778   /* X86_64_CE */
6779   {
6780     { "into", { XX }, 0 },
6781   },
6782
6783   /* X86_64_D4 */
6784   {
6785     { "aam", { Ib }, 0 },
6786   },
6787
6788   /* X86_64_D5 */
6789   {
6790     { "aad", { Ib }, 0 },
6791   },
6792
6793   /* X86_64_E8 */
6794   {
6795     { "callP",          { Jv, BND }, 0 },
6796     { "call@",          { Jv, BND }, 0 }
6797   },
6798
6799   /* X86_64_E9 */
6800   {
6801     { "jmpP",           { Jv, BND }, 0 },
6802     { "jmp@",           { Jv, BND }, 0 }
6803   },
6804
6805   /* X86_64_EA */
6806   {
6807     { "{l|}jmp{T|}", { Ap }, 0 },
6808   },
6809
6810   /* X86_64_0F01_REG_0 */
6811   {
6812     { "sgdt{Q|Q}", { M }, 0 },
6813     { "sgdt", { M }, 0 },
6814   },
6815
6816   /* X86_64_0F01_REG_1 */
6817   {
6818     { "sidt{Q|Q}", { M }, 0 },
6819     { "sidt", { M }, 0 },
6820   },
6821
6822   /* X86_64_0F01_REG_2 */
6823   {
6824     { "lgdt{Q|Q}", { M }, 0 },
6825     { "lgdt", { M }, 0 },
6826   },
6827
6828   /* X86_64_0F01_REG_3 */
6829   {
6830     { "lidt{Q|Q}", { M }, 0 },
6831     { "lidt", { M }, 0 },
6832   },
6833 };
6834
6835 static const struct dis386 three_byte_table[][256] = {
6836
6837   /* THREE_BYTE_0F38 */
6838   {
6839     /* 00 */
6840     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6841     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6842     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6843     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6844     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6845     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6846     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6847     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6848     /* 08 */
6849     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6850     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6851     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6852     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     /* 10 */
6858     { PREFIX_TABLE (PREFIX_0F3810) },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { PREFIX_TABLE (PREFIX_0F3814) },
6863     { PREFIX_TABLE (PREFIX_0F3815) },
6864     { Bad_Opcode },
6865     { PREFIX_TABLE (PREFIX_0F3817) },
6866     /* 18 */
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6872     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6873     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6874     { Bad_Opcode },
6875     /* 20 */
6876     { PREFIX_TABLE (PREFIX_0F3820) },
6877     { PREFIX_TABLE (PREFIX_0F3821) },
6878     { PREFIX_TABLE (PREFIX_0F3822) },
6879     { PREFIX_TABLE (PREFIX_0F3823) },
6880     { PREFIX_TABLE (PREFIX_0F3824) },
6881     { PREFIX_TABLE (PREFIX_0F3825) },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     /* 28 */
6885     { PREFIX_TABLE (PREFIX_0F3828) },
6886     { PREFIX_TABLE (PREFIX_0F3829) },
6887     { PREFIX_TABLE (PREFIX_0F382A) },
6888     { PREFIX_TABLE (PREFIX_0F382B) },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     /* 30 */
6894     { PREFIX_TABLE (PREFIX_0F3830) },
6895     { PREFIX_TABLE (PREFIX_0F3831) },
6896     { PREFIX_TABLE (PREFIX_0F3832) },
6897     { PREFIX_TABLE (PREFIX_0F3833) },
6898     { PREFIX_TABLE (PREFIX_0F3834) },
6899     { PREFIX_TABLE (PREFIX_0F3835) },
6900     { Bad_Opcode },
6901     { PREFIX_TABLE (PREFIX_0F3837) },
6902     /* 38 */
6903     { PREFIX_TABLE (PREFIX_0F3838) },
6904     { PREFIX_TABLE (PREFIX_0F3839) },
6905     { PREFIX_TABLE (PREFIX_0F383A) },
6906     { PREFIX_TABLE (PREFIX_0F383B) },
6907     { PREFIX_TABLE (PREFIX_0F383C) },
6908     { PREFIX_TABLE (PREFIX_0F383D) },
6909     { PREFIX_TABLE (PREFIX_0F383E) },
6910     { PREFIX_TABLE (PREFIX_0F383F) },
6911     /* 40 */
6912     { PREFIX_TABLE (PREFIX_0F3840) },
6913     { PREFIX_TABLE (PREFIX_0F3841) },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     /* 48 */
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     /* 50 */
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     /* 58 */
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     /* 60 */
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     /* 68 */
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     /* 70 */
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     /* 78 */
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     /* 80 */
6984     { PREFIX_TABLE (PREFIX_0F3880) },
6985     { PREFIX_TABLE (PREFIX_0F3881) },
6986     { PREFIX_TABLE (PREFIX_0F3882) },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     /* 88 */
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     /* 90 */
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     /* 98 */
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     /* a0 */
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     /* a8 */
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     /* b0 */
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     /* b8 */
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     /* c0 */
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     /* c8 */
7065     { PREFIX_TABLE (PREFIX_0F38C8) },
7066     { PREFIX_TABLE (PREFIX_0F38C9) },
7067     { PREFIX_TABLE (PREFIX_0F38CA) },
7068     { PREFIX_TABLE (PREFIX_0F38CB) },
7069     { PREFIX_TABLE (PREFIX_0F38CC) },
7070     { PREFIX_TABLE (PREFIX_0F38CD) },
7071     { Bad_Opcode },
7072     { PREFIX_TABLE (PREFIX_0F38CF) },
7073     /* d0 */
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     /* d8 */
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { PREFIX_TABLE (PREFIX_0F38DB) },
7087     { PREFIX_TABLE (PREFIX_0F38DC) },
7088     { PREFIX_TABLE (PREFIX_0F38DD) },
7089     { PREFIX_TABLE (PREFIX_0F38DE) },
7090     { PREFIX_TABLE (PREFIX_0F38DF) },
7091     /* e0 */
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     /* e8 */
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     /* f0 */
7110     { PREFIX_TABLE (PREFIX_0F38F0) },
7111     { PREFIX_TABLE (PREFIX_0F38F1) },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { PREFIX_TABLE (PREFIX_0F38F5) },
7116     { PREFIX_TABLE (PREFIX_0F38F6) },
7117     { Bad_Opcode },
7118     /* f8 */
7119     { PREFIX_TABLE (PREFIX_0F38F8) },
7120     { PREFIX_TABLE (PREFIX_0F38F9) },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127   },
7128   /* THREE_BYTE_0F3A */
7129   {
7130     /* 00 */
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     /* 08 */
7140     { PREFIX_TABLE (PREFIX_0F3A08) },
7141     { PREFIX_TABLE (PREFIX_0F3A09) },
7142     { PREFIX_TABLE (PREFIX_0F3A0A) },
7143     { PREFIX_TABLE (PREFIX_0F3A0B) },
7144     { PREFIX_TABLE (PREFIX_0F3A0C) },
7145     { PREFIX_TABLE (PREFIX_0F3A0D) },
7146     { PREFIX_TABLE (PREFIX_0F3A0E) },
7147     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7148     /* 10 */
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { PREFIX_TABLE (PREFIX_0F3A14) },
7154     { PREFIX_TABLE (PREFIX_0F3A15) },
7155     { PREFIX_TABLE (PREFIX_0F3A16) },
7156     { PREFIX_TABLE (PREFIX_0F3A17) },
7157     /* 18 */
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     /* 20 */
7167     { PREFIX_TABLE (PREFIX_0F3A20) },
7168     { PREFIX_TABLE (PREFIX_0F3A21) },
7169     { PREFIX_TABLE (PREFIX_0F3A22) },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     /* 28 */
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     /* 30 */
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     /* 38 */
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     /* 40 */
7203     { PREFIX_TABLE (PREFIX_0F3A40) },
7204     { PREFIX_TABLE (PREFIX_0F3A41) },
7205     { PREFIX_TABLE (PREFIX_0F3A42) },
7206     { Bad_Opcode },
7207     { PREFIX_TABLE (PREFIX_0F3A44) },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     /* 48 */
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     /* 50 */
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     /* 58 */
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     /* 60 */
7239     { PREFIX_TABLE (PREFIX_0F3A60) },
7240     { PREFIX_TABLE (PREFIX_0F3A61) },
7241     { PREFIX_TABLE (PREFIX_0F3A62) },
7242     { PREFIX_TABLE (PREFIX_0F3A63) },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     /* 68 */
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     /* 70 */
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     /* 78 */
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     /* 80 */
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     /* 88 */
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     /* 90 */
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     /* 98 */
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     /* a0 */
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     /* a8 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* b0 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* b8 */
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     /* c0 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     /* c8 */
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { PREFIX_TABLE (PREFIX_0F3ACC) },
7361     { Bad_Opcode },
7362     { PREFIX_TABLE (PREFIX_0F3ACE) },
7363     { PREFIX_TABLE (PREFIX_0F3ACF) },
7364     /* d0 */
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     /* d8 */
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { PREFIX_TABLE (PREFIX_0F3ADF) },
7382     /* e0 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* e8 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     /* f0 */
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     /* f8 */
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418   },
7419 };
7420
7421 static const struct dis386 xop_table[][256] = {
7422   /* XOP_08 */
7423   {
7424     /* 00 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     /* 08 */
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     /* 10 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     /* 18 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* 20 */
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     /* 28 */
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     /* 30 */
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     /* 38 */
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     /* 40 */
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     /* 48 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     /* 50 */
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* 58 */
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     /* 60 */
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     /* 68 */
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     /* 70 */
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     /* 78 */
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     /* 80 */
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7575     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7576     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7577     /* 88 */
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7585     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7586     /* 90 */
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7593     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7594     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7595     /* 98 */
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7603     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7604     /* a0 */
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7608     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7612     { Bad_Opcode },
7613     /* a8 */
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     /* b0 */
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7630     { Bad_Opcode },
7631     /* b8 */
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     /* c0 */
7641     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7642     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7643     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7644     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     /* c8 */
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7655     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7656     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7657     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7658     /* d0 */
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     /* d8 */
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     /* e0 */
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     /* e8 */
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7691     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7692     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7693     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7694     /* f0 */
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     /* f8 */
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712   },
7713   /* XOP_09 */
7714   {
7715     /* 00 */
7716     { Bad_Opcode },
7717     { REG_TABLE (REG_XOP_TBM_01) },
7718     { REG_TABLE (REG_XOP_TBM_02) },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     /* 08 */
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     /* 10 */
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { REG_TABLE (REG_XOP_LWPCB) },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     /* 18 */
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     /* 20 */
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     /* 28 */
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     /* 30 */
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     /* 38 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     /* 40 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     /* 48 */
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     /* 50 */
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     /* 58 */
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     /* 60 */
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     /* 68 */
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     /* 70 */
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     /* 78 */
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     /* 80 */
7860     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
7861     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
7862     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
7863     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     /* 88 */
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     /* 90 */
7878     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7879     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7880     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7881     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7882     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7883     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7884     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7885     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7886     /* 98 */
7887     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7888     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7889     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7890     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     /* a0 */
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     /* a8 */
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     /* b0 */
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     /* b8 */
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     /* c0 */
7932     { Bad_Opcode },
7933     { "vphaddbw",       { XM, EXxmm }, 0 },
7934     { "vphaddbd",       { XM, EXxmm }, 0 },
7935     { "vphaddbq",       { XM, EXxmm }, 0 },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { "vphaddwd",       { XM, EXxmm }, 0 },
7939     { "vphaddwq",       { XM, EXxmm }, 0 },
7940     /* c8 */
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { "vphadddq",       { XM, EXxmm }, 0 },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     /* d0 */
7950     { Bad_Opcode },
7951     { "vphaddubw",      { XM, EXxmm }, 0 },
7952     { "vphaddubd",      { XM, EXxmm }, 0 },
7953     { "vphaddubq",      { XM, EXxmm }, 0 },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { "vphadduwd",      { XM, EXxmm }, 0 },
7957     { "vphadduwq",      { XM, EXxmm }, 0 },
7958     /* d8 */
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { "vphaddudq",      { XM, EXxmm }, 0 },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     /* e0 */
7968     { Bad_Opcode },
7969     { "vphsubbw",       { XM, EXxmm }, 0 },
7970     { "vphsubwd",       { XM, EXxmm }, 0 },
7971     { "vphsubdq",       { XM, EXxmm }, 0 },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     /* e8 */
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     /* f0 */
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     /* f8 */
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003   },
8004   /* XOP_0A */
8005   {
8006     /* 00 */
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     /* 08 */
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     /* 10 */
8025     { "bextrS", { Gdq, Edq, Id }, 0 },
8026     { Bad_Opcode },
8027     { REG_TABLE (REG_XOP_LWP) },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     /* 18 */
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     /* 20 */
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     /* 28 */
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     /* 30 */
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     /* 38 */
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     /* 40 */
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     /* 48 */
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     /* 50 */
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     /* 58 */
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     /* 60 */
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     /* 68 */
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     /* 70 */
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     /* 78 */
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     /* 80 */
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     /* 88 */
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     /* 90 */
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     /* 98 */
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     /* a0 */
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     /* a8 */
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     /* b0 */
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     /* b8 */
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     /* c0 */
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     /* c8 */
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     /* d0 */
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     /* d8 */
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     /* e0 */
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     /* e8 */
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     /* f0 */
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     /* f8 */
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294   },
8295 };
8296
8297 static const struct dis386 vex_table[][256] = {
8298   /* VEX_0F */
8299   {
8300     /* 00 */
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     /* 08 */
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     /* 10 */
8319     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8320     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8321     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8322     { MOD_TABLE (MOD_VEX_0F13) },
8323     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8324     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8325     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8326     { MOD_TABLE (MOD_VEX_0F17) },
8327     /* 18 */
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     /* 20 */
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     /* 28 */
8346     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8347     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8348     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8349     { MOD_TABLE (MOD_VEX_0F2B) },
8350     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8351     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8352     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8353     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8354     /* 30 */
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     /* 38 */
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     /* 40 */
8373     { Bad_Opcode },
8374     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8375     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8376     { Bad_Opcode },
8377     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8378     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8379     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8380     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8381     /* 48 */
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8385     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     /* 50 */
8391     { MOD_TABLE (MOD_VEX_0F50) },
8392     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8393     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8394     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8395     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8396     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8397     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8398     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8399     /* 58 */
8400     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8401     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8402     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8403     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8404     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8405     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8406     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8407     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8408     /* 60 */
8409     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8410     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8411     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8412     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8413     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8414     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8415     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8416     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8417     /* 68 */
8418     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8419     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8420     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8421     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8422     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8423     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8424     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8425     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8426     /* 70 */
8427     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8428     { REG_TABLE (REG_VEX_0F71) },
8429     { REG_TABLE (REG_VEX_0F72) },
8430     { REG_TABLE (REG_VEX_0F73) },
8431     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8432     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8433     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8434     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8435     /* 78 */
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8441     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8442     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8443     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8444     /* 80 */
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     /* 88 */
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     /* 90 */
8463     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8464     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8465     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8466     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     /* 98 */
8472     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8473     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     /* a0 */
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     /* a8 */
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { REG_TABLE (REG_VEX_0FAE) },
8497     { Bad_Opcode },
8498     /* b0 */
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     /* b8 */
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     /* c0 */
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8520     { Bad_Opcode },
8521     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8522     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8523     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8524     { Bad_Opcode },
8525     /* c8 */
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     /* d0 */
8535     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8536     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8537     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8538     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8539     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8540     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8541     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8542     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8543     /* d8 */
8544     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8545     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8546     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8547     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8548     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8549     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8550     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8551     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8552     /* e0 */
8553     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8554     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8555     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8556     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8557     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8558     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8559     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8560     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8561     /* e8 */
8562     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8563     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8564     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8565     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8566     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8567     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8568     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8569     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8570     /* f0 */
8571     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8572     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8573     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8574     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8575     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8576     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8577     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8578     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8579     /* f8 */
8580     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8581     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8582     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8583     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8584     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8585     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8586     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8587     { Bad_Opcode },
8588   },
8589   /* VEX_0F38 */
8590   {
8591     /* 00 */
8592     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8593     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8594     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8595     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8596     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8600     /* 08 */
8601     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8602     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8603     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8604     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8605     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8606     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8607     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8608     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8609     /* 10 */
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8617     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8618     /* 18 */
8619     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8621     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8622     { Bad_Opcode },
8623     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8624     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8625     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8626     { Bad_Opcode },
8627     /* 20 */
8628     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8629     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8632     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8633     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     /* 28 */
8637     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8638     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8640     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8641     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8645     /* 30 */
8646     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8650     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8651     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8652     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8654     /* 38 */
8655     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8660     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8661     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8662     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8663     /* 40 */
8664     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8672     /* 48 */
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     /* 50 */
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     /* 58 */
8691     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8692     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     /* 60 */
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     /* 68 */
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     /* 70 */
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     /* 78 */
8727     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     /* 80 */
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     /* 88 */
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8750     { Bad_Opcode },
8751     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8752     { Bad_Opcode },
8753     /* 90 */
8754     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8762     /* 98 */
8763     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8771     /* a0 */
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8780     /* a8 */
8781     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8789     /* b0 */
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8798     /* b8 */
8799     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8807     /* c0 */
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     /* c8 */
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8825     /* d0 */
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     /* d8 */
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8839     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8840     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8841     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8842     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8843     /* e0 */
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     /* e8 */
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     /* f0 */
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8865     { REG_TABLE (REG_VEX_0F38F3) },
8866     { Bad_Opcode },
8867     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8868     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8869     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8870     /* f8 */
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879   },
8880   /* VEX_0F3A */
8881   {
8882     /* 00 */
8883     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8886     { Bad_Opcode },
8887     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8890     { Bad_Opcode },
8891     /* 08 */
8892     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8900     /* 10 */
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8909     /* 18 */
8910     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     /* 20 */
8919     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     /* 28 */
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     /* 30 */
8937     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     /* 38 */
8946     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     /* 40 */
8955     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8958     { Bad_Opcode },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8960     { Bad_Opcode },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8962     { Bad_Opcode },
8963     /* 48 */
8964     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     /* 50 */
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     /* 58 */
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8990     /* 60 */
8991     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     /* 68 */
9000     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9008     /* 70 */
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     /* 78 */
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9026     /* 80 */
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     /* 88 */
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     /* 90 */
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     /* 98 */
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     /* a0 */
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     /* a8 */
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     /* b0 */
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     /* b8 */
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     /* c0 */
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     /* c8 */
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9115     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9116     /* d0 */
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     /* d8 */
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9134     /* e0 */
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     /* e8 */
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     /* f0 */
9153     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     /* f8 */
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170   },
9171 };
9172
9173 #include "i386-dis-evex.h"
9174
9175 static const struct dis386 vex_len_table[][2] = {
9176   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9177   {
9178     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9179   },
9180
9181   /* VEX_LEN_0F12_P_0_M_1 */
9182   {
9183     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9184   },
9185
9186   /* VEX_LEN_0F13_M_0 */
9187   {
9188     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9189   },
9190
9191   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9192   {
9193     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9194   },
9195
9196   /* VEX_LEN_0F16_P_0_M_1 */
9197   {
9198     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9199   },
9200
9201   /* VEX_LEN_0F17_M_0 */
9202   {
9203     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9204   },
9205
9206   /* VEX_LEN_0F41_P_0 */
9207   {
9208     { Bad_Opcode },
9209     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9210   },
9211   /* VEX_LEN_0F41_P_2 */
9212   {
9213     { Bad_Opcode },
9214     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9215   },
9216   /* VEX_LEN_0F42_P_0 */
9217   {
9218     { Bad_Opcode },
9219     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9220   },
9221   /* VEX_LEN_0F42_P_2 */
9222   {
9223     { Bad_Opcode },
9224     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9225   },
9226   /* VEX_LEN_0F44_P_0 */
9227   {
9228     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9229   },
9230   /* VEX_LEN_0F44_P_2 */
9231   {
9232     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9233   },
9234   /* VEX_LEN_0F45_P_0 */
9235   {
9236     { Bad_Opcode },
9237     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9238   },
9239   /* VEX_LEN_0F45_P_2 */
9240   {
9241     { Bad_Opcode },
9242     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9243   },
9244   /* VEX_LEN_0F46_P_0 */
9245   {
9246     { Bad_Opcode },
9247     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9248   },
9249   /* VEX_LEN_0F46_P_2 */
9250   {
9251     { Bad_Opcode },
9252     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9253   },
9254   /* VEX_LEN_0F47_P_0 */
9255   {
9256     { Bad_Opcode },
9257     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9258   },
9259   /* VEX_LEN_0F47_P_2 */
9260   {
9261     { Bad_Opcode },
9262     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9263   },
9264   /* VEX_LEN_0F4A_P_0 */
9265   {
9266     { Bad_Opcode },
9267     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9268   },
9269   /* VEX_LEN_0F4A_P_2 */
9270   {
9271     { Bad_Opcode },
9272     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9273   },
9274   /* VEX_LEN_0F4B_P_0 */
9275   {
9276     { Bad_Opcode },
9277     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9278   },
9279   /* VEX_LEN_0F4B_P_2 */
9280   {
9281     { Bad_Opcode },
9282     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9283   },
9284
9285   /* VEX_LEN_0F6E_P_2 */
9286   {
9287     { "vmovK",          { XMScalar, Edq }, 0 },
9288   },
9289
9290   /* VEX_LEN_0F77_P_1 */
9291   {
9292     { "vzeroupper",     { XX }, 0 },
9293     { "vzeroall",       { XX }, 0 },
9294   },
9295
9296   /* VEX_LEN_0F7E_P_1 */
9297   {
9298     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9299   },
9300
9301   /* VEX_LEN_0F7E_P_2 */
9302   {
9303     { "vmovK",          { Edq, XMScalar }, 0 },
9304   },
9305
9306   /* VEX_LEN_0F90_P_0 */
9307   {
9308     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9309   },
9310
9311   /* VEX_LEN_0F90_P_2 */
9312   {
9313     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9314   },
9315
9316   /* VEX_LEN_0F91_P_0 */
9317   {
9318     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9319   },
9320
9321   /* VEX_LEN_0F91_P_2 */
9322   {
9323     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9324   },
9325
9326   /* VEX_LEN_0F92_P_0 */
9327   {
9328     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9329   },
9330
9331   /* VEX_LEN_0F92_P_2 */
9332   {
9333     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9334   },
9335
9336   /* VEX_LEN_0F92_P_3 */
9337   {
9338     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9339   },
9340
9341   /* VEX_LEN_0F93_P_0 */
9342   {
9343     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9344   },
9345
9346   /* VEX_LEN_0F93_P_2 */
9347   {
9348     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9349   },
9350
9351   /* VEX_LEN_0F93_P_3 */
9352   {
9353     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9354   },
9355
9356   /* VEX_LEN_0F98_P_0 */
9357   {
9358     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9359   },
9360
9361   /* VEX_LEN_0F98_P_2 */
9362   {
9363     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9364   },
9365
9366   /* VEX_LEN_0F99_P_0 */
9367   {
9368     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9369   },
9370
9371   /* VEX_LEN_0F99_P_2 */
9372   {
9373     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9374   },
9375
9376   /* VEX_LEN_0FAE_R_2_M_0 */
9377   {
9378     { "vldmxcsr",       { Md }, 0 },
9379   },
9380
9381   /* VEX_LEN_0FAE_R_3_M_0 */
9382   {
9383     { "vstmxcsr",       { Md }, 0 },
9384   },
9385
9386   /* VEX_LEN_0FC4_P_2 */
9387   {
9388     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9389   },
9390
9391   /* VEX_LEN_0FC5_P_2 */
9392   {
9393     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9394   },
9395
9396   /* VEX_LEN_0FD6_P_2 */
9397   {
9398     { "vmovq",          { EXqVexScalarS, XMScalar }, 0 },
9399   },
9400
9401   /* VEX_LEN_0FF7_P_2 */
9402   {
9403     { "vmaskmovdqu",    { XM, XS }, 0 },
9404   },
9405
9406   /* VEX_LEN_0F3816_P_2 */
9407   {
9408     { Bad_Opcode },
9409     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9410   },
9411
9412   /* VEX_LEN_0F3819_P_2 */
9413   {
9414     { Bad_Opcode },
9415     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9416   },
9417
9418   /* VEX_LEN_0F381A_P_2_M_0 */
9419   {
9420     { Bad_Opcode },
9421     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9422   },
9423
9424   /* VEX_LEN_0F3836_P_2 */
9425   {
9426     { Bad_Opcode },
9427     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9428   },
9429
9430   /* VEX_LEN_0F3841_P_2 */
9431   {
9432     { "vphminposuw",    { XM, EXx }, 0 },
9433   },
9434
9435   /* VEX_LEN_0F385A_P_2_M_0 */
9436   {
9437     { Bad_Opcode },
9438     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9439   },
9440
9441   /* VEX_LEN_0F38DB_P_2 */
9442   {
9443     { "vaesimc",        { XM, EXx }, 0 },
9444   },
9445
9446   /* VEX_LEN_0F38F2_P_0 */
9447   {
9448     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9449   },
9450
9451   /* VEX_LEN_0F38F3_R_1_P_0 */
9452   {
9453     { "blsrS",          { VexGdq, Edq }, 0 },
9454   },
9455
9456   /* VEX_LEN_0F38F3_R_2_P_0 */
9457   {
9458     { "blsmskS",        { VexGdq, Edq }, 0 },
9459   },
9460
9461   /* VEX_LEN_0F38F3_R_3_P_0 */
9462   {
9463     { "blsiS",          { VexGdq, Edq }, 0 },
9464   },
9465
9466   /* VEX_LEN_0F38F5_P_0 */
9467   {
9468     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9469   },
9470
9471   /* VEX_LEN_0F38F5_P_1 */
9472   {
9473     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9474   },
9475
9476   /* VEX_LEN_0F38F5_P_3 */
9477   {
9478     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9479   },
9480
9481   /* VEX_LEN_0F38F6_P_3 */
9482   {
9483     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9484   },
9485
9486   /* VEX_LEN_0F38F7_P_0 */
9487   {
9488     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9489   },
9490
9491   /* VEX_LEN_0F38F7_P_1 */
9492   {
9493     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9494   },
9495
9496   /* VEX_LEN_0F38F7_P_2 */
9497   {
9498     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9499   },
9500
9501   /* VEX_LEN_0F38F7_P_3 */
9502   {
9503     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9504   },
9505
9506   /* VEX_LEN_0F3A00_P_2 */
9507   {
9508     { Bad_Opcode },
9509     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9510   },
9511
9512   /* VEX_LEN_0F3A01_P_2 */
9513   {
9514     { Bad_Opcode },
9515     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9516   },
9517
9518   /* VEX_LEN_0F3A06_P_2 */
9519   {
9520     { Bad_Opcode },
9521     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9522   },
9523
9524   /* VEX_LEN_0F3A14_P_2 */
9525   {
9526     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9527   },
9528
9529   /* VEX_LEN_0F3A15_P_2 */
9530   {
9531     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9532   },
9533
9534   /* VEX_LEN_0F3A16_P_2  */
9535   {
9536     { "vpextrK",        { Edq, XM, Ib }, 0 },
9537   },
9538
9539   /* VEX_LEN_0F3A17_P_2 */
9540   {
9541     { "vextractps",     { Edqd, XM, Ib }, 0 },
9542   },
9543
9544   /* VEX_LEN_0F3A18_P_2 */
9545   {
9546     { Bad_Opcode },
9547     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9548   },
9549
9550   /* VEX_LEN_0F3A19_P_2 */
9551   {
9552     { Bad_Opcode },
9553     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9554   },
9555
9556   /* VEX_LEN_0F3A20_P_2 */
9557   {
9558     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9559   },
9560
9561   /* VEX_LEN_0F3A21_P_2 */
9562   {
9563     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9564   },
9565
9566   /* VEX_LEN_0F3A22_P_2 */
9567   {
9568     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9569   },
9570
9571   /* VEX_LEN_0F3A30_P_2 */
9572   {
9573     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9574   },
9575
9576   /* VEX_LEN_0F3A31_P_2 */
9577   {
9578     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9579   },
9580
9581   /* VEX_LEN_0F3A32_P_2 */
9582   {
9583     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9584   },
9585
9586   /* VEX_LEN_0F3A33_P_2 */
9587   {
9588     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9589   },
9590
9591   /* VEX_LEN_0F3A38_P_2 */
9592   {
9593     { Bad_Opcode },
9594     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9595   },
9596
9597   /* VEX_LEN_0F3A39_P_2 */
9598   {
9599     { Bad_Opcode },
9600     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9601   },
9602
9603   /* VEX_LEN_0F3A41_P_2 */
9604   {
9605     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9606   },
9607
9608   /* VEX_LEN_0F3A46_P_2 */
9609   {
9610     { Bad_Opcode },
9611     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9612   },
9613
9614   /* VEX_LEN_0F3A60_P_2 */
9615   {
9616     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9617   },
9618
9619   /* VEX_LEN_0F3A61_P_2 */
9620   {
9621     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9622   },
9623
9624   /* VEX_LEN_0F3A62_P_2 */
9625   {
9626     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9627   },
9628
9629   /* VEX_LEN_0F3A63_P_2 */
9630   {
9631     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9632   },
9633
9634   /* VEX_LEN_0F3A6A_P_2 */
9635   {
9636     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9637   },
9638
9639   /* VEX_LEN_0F3A6B_P_2 */
9640   {
9641     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9642   },
9643
9644   /* VEX_LEN_0F3A6E_P_2 */
9645   {
9646     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9647   },
9648
9649   /* VEX_LEN_0F3A6F_P_2 */
9650   {
9651     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9652   },
9653
9654   /* VEX_LEN_0F3A7A_P_2 */
9655   {
9656     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9657   },
9658
9659   /* VEX_LEN_0F3A7B_P_2 */
9660   {
9661     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9662   },
9663
9664   /* VEX_LEN_0F3A7E_P_2 */
9665   {
9666     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9667   },
9668
9669   /* VEX_LEN_0F3A7F_P_2 */
9670   {
9671     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9672   },
9673
9674   /* VEX_LEN_0F3ADF_P_2 */
9675   {
9676     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9677   },
9678
9679   /* VEX_LEN_0F3AF0_P_3 */
9680   {
9681     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9682   },
9683
9684   /* VEX_LEN_0FXOP_08_CC */
9685   {
9686      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9687   },
9688
9689   /* VEX_LEN_0FXOP_08_CD */
9690   {
9691      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9692   },
9693
9694   /* VEX_LEN_0FXOP_08_CE */
9695   {
9696      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9697   },
9698
9699   /* VEX_LEN_0FXOP_08_CF */
9700   {
9701      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9702   },
9703
9704   /* VEX_LEN_0FXOP_08_EC */
9705   {
9706      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9707   },
9708
9709   /* VEX_LEN_0FXOP_08_ED */
9710   {
9711      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9712   },
9713
9714   /* VEX_LEN_0FXOP_08_EE */
9715   {
9716      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9717   },
9718
9719   /* VEX_LEN_0FXOP_08_EF */
9720   {
9721      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9722   },
9723
9724   /* VEX_LEN_0FXOP_09_82_W_0 */
9725   {
9726     { "vfrczss",        { XM, EXd }, 0 },
9727   },
9728
9729   /* VEX_LEN_0FXOP_09_83_W_0 */
9730   {
9731     { "vfrczsd",        { XM, EXq }, 0 },
9732   },
9733 };
9734
9735 #include "i386-dis-evex-len.h"
9736
9737 static const struct dis386 vex_w_table[][2] = {
9738   {
9739     /* VEX_W_0F41_P_0_LEN_1 */
9740     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9741     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9742   },
9743   {
9744     /* VEX_W_0F41_P_2_LEN_1 */
9745     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9746     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9747   },
9748   {
9749     /* VEX_W_0F42_P_0_LEN_1 */
9750     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9751     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9752   },
9753   {
9754     /* VEX_W_0F42_P_2_LEN_1 */
9755     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9756     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9757   },
9758   {
9759     /* VEX_W_0F44_P_0_LEN_0 */
9760     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9761     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9762   },
9763   {
9764     /* VEX_W_0F44_P_2_LEN_0 */
9765     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9766     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9767   },
9768   {
9769     /* VEX_W_0F45_P_0_LEN_1 */
9770     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9771     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9772   },
9773   {
9774     /* VEX_W_0F45_P_2_LEN_1 */
9775     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9776     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9777   },
9778   {
9779     /* VEX_W_0F46_P_0_LEN_1 */
9780     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9781     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9782   },
9783   {
9784     /* VEX_W_0F46_P_2_LEN_1 */
9785     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9786     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9787   },
9788   {
9789     /* VEX_W_0F47_P_0_LEN_1 */
9790     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9791     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9792   },
9793   {
9794     /* VEX_W_0F47_P_2_LEN_1 */
9795     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9796     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9797   },
9798   {
9799     /* VEX_W_0F4A_P_0_LEN_1 */
9800     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9801     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9802   },
9803   {
9804     /* VEX_W_0F4A_P_2_LEN_1 */
9805     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9806     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9807   },
9808   {
9809     /* VEX_W_0F4B_P_0_LEN_1 */
9810     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9811     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9812   },
9813   {
9814     /* VEX_W_0F4B_P_2_LEN_1 */
9815     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9816   },
9817   {
9818     /* VEX_W_0F90_P_0_LEN_0 */
9819     { "kmovw",          { MaskG, MaskE }, 0 },
9820     { "kmovq",          { MaskG, MaskE }, 0 },
9821   },
9822   {
9823     /* VEX_W_0F90_P_2_LEN_0 */
9824     { "kmovb",          { MaskG, MaskBDE }, 0 },
9825     { "kmovd",          { MaskG, MaskBDE }, 0 },
9826   },
9827   {
9828     /* VEX_W_0F91_P_0_LEN_0 */
9829     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9830     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9831   },
9832   {
9833     /* VEX_W_0F91_P_2_LEN_0 */
9834     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9835     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9836   },
9837   {
9838     /* VEX_W_0F92_P_0_LEN_0 */
9839     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9840   },
9841   {
9842     /* VEX_W_0F92_P_2_LEN_0 */
9843     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9844   },
9845   {
9846     /* VEX_W_0F93_P_0_LEN_0 */
9847     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9848   },
9849   {
9850     /* VEX_W_0F93_P_2_LEN_0 */
9851     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9852   },
9853   {
9854     /* VEX_W_0F98_P_0_LEN_0 */
9855     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9856     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9857   },
9858   {
9859     /* VEX_W_0F98_P_2_LEN_0 */
9860     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
9861     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
9862   },
9863   {
9864     /* VEX_W_0F99_P_0_LEN_0 */
9865     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
9866     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
9867   },
9868   {
9869     /* VEX_W_0F99_P_2_LEN_0 */
9870     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
9871     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
9872   },
9873   {
9874     /* VEX_W_0F380C_P_2  */
9875     { "vpermilps",      { XM, Vex, EXx }, 0 },
9876   },
9877   {
9878     /* VEX_W_0F380D_P_2  */
9879     { "vpermilpd",      { XM, Vex, EXx }, 0 },
9880   },
9881   {
9882     /* VEX_W_0F380E_P_2  */
9883     { "vtestps",        { XM, EXx }, 0 },
9884   },
9885   {
9886     /* VEX_W_0F380F_P_2  */
9887     { "vtestpd",        { XM, EXx }, 0 },
9888   },
9889   {
9890     /* VEX_W_0F3813_P_2 */
9891     { "vcvtph2ps", { XM, EXxmmq }, 0 },
9892   },
9893   {
9894     /* VEX_W_0F3816_P_2  */
9895     { "vpermps",        { XM, Vex, EXx }, 0 },
9896   },
9897   {
9898     /* VEX_W_0F3818_P_2 */
9899     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
9900   },
9901   {
9902     /* VEX_W_0F3819_P_2 */
9903     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
9904   },
9905   {
9906     /* VEX_W_0F381A_P_2_M_0 */
9907     { "vbroadcastf128", { XM, Mxmm }, 0 },
9908   },
9909   {
9910     /* VEX_W_0F382C_P_2_M_0 */
9911     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
9912   },
9913   {
9914     /* VEX_W_0F382D_P_2_M_0 */
9915     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
9916   },
9917   {
9918     /* VEX_W_0F382E_P_2_M_0 */
9919     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
9920   },
9921   {
9922     /* VEX_W_0F382F_P_2_M_0 */
9923     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
9924   },
9925   {
9926     /* VEX_W_0F3836_P_2  */
9927     { "vpermd",         { XM, Vex, EXx }, 0 },
9928   },
9929   {
9930     /* VEX_W_0F3846_P_2 */
9931     { "vpsravd",        { XM, Vex, EXx }, 0 },
9932   },
9933   {
9934     /* VEX_W_0F3858_P_2 */
9935     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
9936   },
9937   {
9938     /* VEX_W_0F3859_P_2 */
9939     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
9940   },
9941   {
9942     /* VEX_W_0F385A_P_2_M_0 */
9943     { "vbroadcasti128", { XM, Mxmm }, 0 },
9944   },
9945   {
9946     /* VEX_W_0F3878_P_2 */
9947     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
9948   },
9949   {
9950     /* VEX_W_0F3879_P_2 */
9951     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
9952   },
9953   {
9954     /* VEX_W_0F38CF_P_2 */
9955     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
9956   },
9957   {
9958     /* VEX_W_0F3A00_P_2 */
9959     { Bad_Opcode },
9960     { "vpermq",         { XM, EXx, Ib }, 0 },
9961   },
9962   {
9963     /* VEX_W_0F3A01_P_2 */
9964     { Bad_Opcode },
9965     { "vpermpd",        { XM, EXx, Ib }, 0 },
9966   },
9967   {
9968     /* VEX_W_0F3A02_P_2 */
9969     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
9970   },
9971   {
9972     /* VEX_W_0F3A04_P_2 */
9973     { "vpermilps",      { XM, EXx, Ib }, 0 },
9974   },
9975   {
9976     /* VEX_W_0F3A05_P_2 */
9977     { "vpermilpd",      { XM, EXx, Ib }, 0 },
9978   },
9979   {
9980     /* VEX_W_0F3A06_P_2 */
9981     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
9982   },
9983   {
9984     /* VEX_W_0F3A18_P_2 */
9985     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
9986   },
9987   {
9988     /* VEX_W_0F3A19_P_2 */
9989     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
9990   },
9991   {
9992     /* VEX_W_0F3A1D_P_2 */
9993     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
9994   },
9995   {
9996     /* VEX_W_0F3A30_P_2_LEN_0 */
9997     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
9998     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
9999   },
10000   {
10001     /* VEX_W_0F3A31_P_2_LEN_0 */
10002     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10003     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10004   },
10005   {
10006     /* VEX_W_0F3A32_P_2_LEN_0 */
10007     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10008     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10009   },
10010   {
10011     /* VEX_W_0F3A33_P_2_LEN_0 */
10012     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10013     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10014   },
10015   {
10016     /* VEX_W_0F3A38_P_2 */
10017     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10018   },
10019   {
10020     /* VEX_W_0F3A39_P_2 */
10021     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10022   },
10023   {
10024     /* VEX_W_0F3A46_P_2 */
10025     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10026   },
10027   {
10028     /* VEX_W_0F3A48_P_2 */
10029     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10030     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10031   },
10032   {
10033     /* VEX_W_0F3A49_P_2 */
10034     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10035     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10036   },
10037   {
10038     /* VEX_W_0F3A4A_P_2 */
10039     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10040   },
10041   {
10042     /* VEX_W_0F3A4B_P_2 */
10043     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10044   },
10045   {
10046     /* VEX_W_0F3A4C_P_2 */
10047     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10048   },
10049   {
10050     /* VEX_W_0F3ACE_P_2 */
10051     { Bad_Opcode },
10052     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10053   },
10054   {
10055     /* VEX_W_0F3ACF_P_2 */
10056     { Bad_Opcode },
10057     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10058   },
10059   /* VEX_W_0FXOP_09_80 */
10060   {
10061     { "vfrczps",        { XM, EXx }, 0 },
10062   },
10063   /* VEX_W_0FXOP_09_81 */
10064   {
10065     { "vfrczpd",        { XM, EXx }, 0 },
10066   },
10067   /* VEX_W_0FXOP_09_82 */
10068   {
10069     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
10070   },
10071   /* VEX_W_0FXOP_09_83 */
10072   {
10073     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
10074   },
10075
10076 #include "i386-dis-evex-w.h"
10077 };
10078
10079 static const struct dis386 mod_table[][2] = {
10080   {
10081     /* MOD_8D */
10082     { "leaS",           { Gv, M }, 0 },
10083   },
10084   {
10085     /* MOD_C6_REG_7 */
10086     { Bad_Opcode },
10087     { RM_TABLE (RM_C6_REG_7) },
10088   },
10089   {
10090     /* MOD_C7_REG_7 */
10091     { Bad_Opcode },
10092     { RM_TABLE (RM_C7_REG_7) },
10093   },
10094   {
10095     /* MOD_FF_REG_3 */
10096     { "{l|}call^", { indirEp }, 0 },
10097   },
10098   {
10099     /* MOD_FF_REG_5 */
10100     { "{l|}jmp^", { indirEp }, 0 },
10101   },
10102   {
10103     /* MOD_0F01_REG_0 */
10104     { X86_64_TABLE (X86_64_0F01_REG_0) },
10105     { RM_TABLE (RM_0F01_REG_0) },
10106   },
10107   {
10108     /* MOD_0F01_REG_1 */
10109     { X86_64_TABLE (X86_64_0F01_REG_1) },
10110     { RM_TABLE (RM_0F01_REG_1) },
10111   },
10112   {
10113     /* MOD_0F01_REG_2 */
10114     { X86_64_TABLE (X86_64_0F01_REG_2) },
10115     { RM_TABLE (RM_0F01_REG_2) },
10116   },
10117   {
10118     /* MOD_0F01_REG_3 */
10119     { X86_64_TABLE (X86_64_0F01_REG_3) },
10120     { RM_TABLE (RM_0F01_REG_3) },
10121   },
10122   {
10123     /* MOD_0F01_REG_5 */
10124     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10125     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10126   },
10127   {
10128     /* MOD_0F01_REG_7 */
10129     { "invlpg",         { Mb }, 0 },
10130     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10131   },
10132   {
10133     /* MOD_0F12_PREFIX_0 */
10134     { "movlpX",         { XM, EXq }, 0 },
10135     { "movhlps",        { XM, EXq }, 0 },
10136   },
10137   {
10138     /* MOD_0F12_PREFIX_2 */
10139     { "movlpX", { XM, EXq }, 0 },
10140   },
10141   {
10142     /* MOD_0F13 */
10143     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10144   },
10145   {
10146     /* MOD_0F16_PREFIX_0 */
10147     { "movhpX",         { XM, EXq }, 0 },
10148     { "movlhps",        { XM, EXq }, 0 },
10149   },
10150   {
10151     /* MOD_0F16_PREFIX_2 */
10152     { "movhpX", { XM, EXq }, 0 },
10153   },
10154   {
10155     /* MOD_0F17 */
10156     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10157   },
10158   {
10159     /* MOD_0F18_REG_0 */
10160     { "prefetchnta",    { Mb }, 0 },
10161   },
10162   {
10163     /* MOD_0F18_REG_1 */
10164     { "prefetcht0",     { Mb }, 0 },
10165   },
10166   {
10167     /* MOD_0F18_REG_2 */
10168     { "prefetcht1",     { Mb }, 0 },
10169   },
10170   {
10171     /* MOD_0F18_REG_3 */
10172     { "prefetcht2",     { Mb }, 0 },
10173   },
10174   {
10175     /* MOD_0F18_REG_4 */
10176     { "nop/reserved",   { Mb }, 0 },
10177   },
10178   {
10179     /* MOD_0F18_REG_5 */
10180     { "nop/reserved",   { Mb }, 0 },
10181   },
10182   {
10183     /* MOD_0F18_REG_6 */
10184     { "nop/reserved",   { Mb }, 0 },
10185   },
10186   {
10187     /* MOD_0F18_REG_7 */
10188     { "nop/reserved",   { Mb }, 0 },
10189   },
10190   {
10191     /* MOD_0F1A_PREFIX_0 */
10192     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10193     { "nopQ",           { Ev }, 0 },
10194   },
10195   {
10196     /* MOD_0F1B_PREFIX_0 */
10197     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10198     { "nopQ",           { Ev }, 0 },
10199   },
10200   {
10201     /* MOD_0F1B_PREFIX_1 */
10202     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10203     { "nopQ",           { Ev }, 0 },
10204   },
10205   {
10206     /* MOD_0F1C_PREFIX_0 */
10207     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10208     { "nopQ",           { Ev }, 0 },
10209   },
10210   {
10211     /* MOD_0F1E_PREFIX_1 */
10212     { "nopQ",           { Ev }, 0 },
10213     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10214   },
10215   {
10216     /* MOD_0F24 */
10217     { Bad_Opcode },
10218     { "movL",           { Rd, Td }, 0 },
10219   },
10220   {
10221     /* MOD_0F26 */
10222     { Bad_Opcode },
10223     { "movL",           { Td, Rd }, 0 },
10224   },
10225   {
10226     /* MOD_0F2B_PREFIX_0 */
10227     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10228   },
10229   {
10230     /* MOD_0F2B_PREFIX_1 */
10231     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10232   },
10233   {
10234     /* MOD_0F2B_PREFIX_2 */
10235     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10236   },
10237   {
10238     /* MOD_0F2B_PREFIX_3 */
10239     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10240   },
10241   {
10242     /* MOD_0F50 */
10243     { Bad_Opcode },
10244     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10245   },
10246   {
10247     /* MOD_0F71_REG_2 */
10248     { Bad_Opcode },
10249     { "psrlw",          { MS, Ib }, 0 },
10250   },
10251   {
10252     /* MOD_0F71_REG_4 */
10253     { Bad_Opcode },
10254     { "psraw",          { MS, Ib }, 0 },
10255   },
10256   {
10257     /* MOD_0F71_REG_6 */
10258     { Bad_Opcode },
10259     { "psllw",          { MS, Ib }, 0 },
10260   },
10261   {
10262     /* MOD_0F72_REG_2 */
10263     { Bad_Opcode },
10264     { "psrld",          { MS, Ib }, 0 },
10265   },
10266   {
10267     /* MOD_0F72_REG_4 */
10268     { Bad_Opcode },
10269     { "psrad",          { MS, Ib }, 0 },
10270   },
10271   {
10272     /* MOD_0F72_REG_6 */
10273     { Bad_Opcode },
10274     { "pslld",          { MS, Ib }, 0 },
10275   },
10276   {
10277     /* MOD_0F73_REG_2 */
10278     { Bad_Opcode },
10279     { "psrlq",          { MS, Ib }, 0 },
10280   },
10281   {
10282     /* MOD_0F73_REG_3 */
10283     { Bad_Opcode },
10284     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10285   },
10286   {
10287     /* MOD_0F73_REG_6 */
10288     { Bad_Opcode },
10289     { "psllq",          { MS, Ib }, 0 },
10290   },
10291   {
10292     /* MOD_0F73_REG_7 */
10293     { Bad_Opcode },
10294     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10295   },
10296   {
10297     /* MOD_0FAE_REG_0 */
10298     { "fxsave",         { FXSAVE }, 0 },
10299     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10300   },
10301   {
10302     /* MOD_0FAE_REG_1 */
10303     { "fxrstor",        { FXSAVE }, 0 },
10304     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10305   },
10306   {
10307     /* MOD_0FAE_REG_2 */
10308     { "ldmxcsr",        { Md }, 0 },
10309     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10310   },
10311   {
10312     /* MOD_0FAE_REG_3 */
10313     { "stmxcsr",        { Md }, 0 },
10314     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10315   },
10316   {
10317     /* MOD_0FAE_REG_4 */
10318     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10319     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10320   },
10321   {
10322     /* MOD_0FAE_REG_5 */
10323     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10324     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10325   },
10326   {
10327     /* MOD_0FAE_REG_6 */
10328     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10329     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10330   },
10331   {
10332     /* MOD_0FAE_REG_7 */
10333     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10334     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10335   },
10336   {
10337     /* MOD_0FB2 */
10338     { "lssS",           { Gv, Mp }, 0 },
10339   },
10340   {
10341     /* MOD_0FB4 */
10342     { "lfsS",           { Gv, Mp }, 0 },
10343   },
10344   {
10345     /* MOD_0FB5 */
10346     { "lgsS",           { Gv, Mp }, 0 },
10347   },
10348   {
10349     /* MOD_0FC3 */
10350     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10351   },
10352   {
10353     /* MOD_0FC7_REG_3 */
10354     { "xrstors",        { FXSAVE }, 0 },
10355   },
10356   {
10357     /* MOD_0FC7_REG_4 */
10358     { "xsavec",         { FXSAVE }, 0 },
10359   },
10360   {
10361     /* MOD_0FC7_REG_5 */
10362     { "xsaves",         { FXSAVE }, 0 },
10363   },
10364   {
10365     /* MOD_0FC7_REG_6 */
10366     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10367     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10368   },
10369   {
10370     /* MOD_0FC7_REG_7 */
10371     { "vmptrst",        { Mq }, 0 },
10372     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10373   },
10374   {
10375     /* MOD_0FD7 */
10376     { Bad_Opcode },
10377     { "pmovmskb",       { Gdq, MS }, 0 },
10378   },
10379   {
10380     /* MOD_0FE7_PREFIX_2 */
10381     { "movntdq",        { Mx, XM }, 0 },
10382   },
10383   {
10384     /* MOD_0FF0_PREFIX_3 */
10385     { "lddqu",          { XM, M }, 0 },
10386   },
10387   {
10388     /* MOD_0F382A_PREFIX_2 */
10389     { "movntdqa",       { XM, Mx }, 0 },
10390   },
10391   {
10392     /* MOD_0F38F5_PREFIX_2 */
10393     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10394   },
10395   {
10396     /* MOD_0F38F6_PREFIX_0 */
10397     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10398   },
10399   {
10400     /* MOD_0F38F8_PREFIX_1 */
10401     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10402   },
10403   {
10404     /* MOD_0F38F8_PREFIX_2 */
10405     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10406   },
10407   {
10408     /* MOD_0F38F8_PREFIX_3 */
10409     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10410   },
10411   {
10412     /* MOD_0F38F9_PREFIX_0 */
10413     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10414   },
10415   {
10416     /* MOD_62_32BIT */
10417     { "bound{S|}",      { Gv, Ma }, 0 },
10418     { EVEX_TABLE (EVEX_0F) },
10419   },
10420   {
10421     /* MOD_C4_32BIT */
10422     { "lesS",           { Gv, Mp }, 0 },
10423     { VEX_C4_TABLE (VEX_0F) },
10424   },
10425   {
10426     /* MOD_C5_32BIT */
10427     { "ldsS",           { Gv, Mp }, 0 },
10428     { VEX_C5_TABLE (VEX_0F) },
10429   },
10430   {
10431     /* MOD_VEX_0F12_PREFIX_0 */
10432     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10433     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10434   },
10435   {
10436     /* MOD_VEX_0F12_PREFIX_2 */
10437     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
10438   },
10439   {
10440     /* MOD_VEX_0F13 */
10441     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10442   },
10443   {
10444     /* MOD_VEX_0F16_PREFIX_0 */
10445     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10446     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10447   },
10448   {
10449     /* MOD_VEX_0F16_PREFIX_2 */
10450     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
10451   },
10452   {
10453     /* MOD_VEX_0F17 */
10454     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10455   },
10456   {
10457     /* MOD_VEX_0F2B */
10458     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
10459   },
10460   {
10461     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10462     { Bad_Opcode },
10463     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10464   },
10465   {
10466     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10467     { Bad_Opcode },
10468     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10469   },
10470   {
10471     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10472     { Bad_Opcode },
10473     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10474   },
10475   {
10476     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10477     { Bad_Opcode },
10478     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10479   },
10480   {
10481     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10482     { Bad_Opcode },
10483     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10484   },
10485   {
10486     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10487     { Bad_Opcode },
10488     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10489   },
10490   {
10491     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10492     { Bad_Opcode },
10493     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10494   },
10495   {
10496     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10497     { Bad_Opcode },
10498     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10499   },
10500   {
10501     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10502     { Bad_Opcode },
10503     { "knotw",          { MaskG, MaskR }, 0 },
10504   },
10505   {
10506     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10507     { Bad_Opcode },
10508     { "knotq",          { MaskG, MaskR }, 0 },
10509   },
10510   {
10511     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10512     { Bad_Opcode },
10513     { "knotb",          { MaskG, MaskR }, 0 },
10514   },
10515   {
10516     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10517     { Bad_Opcode },
10518     { "knotd",          { MaskG, MaskR }, 0 },
10519   },
10520   {
10521     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10522     { Bad_Opcode },
10523     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10524   },
10525   {
10526     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10527     { Bad_Opcode },
10528     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10529   },
10530   {
10531     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10532     { Bad_Opcode },
10533     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10534   },
10535   {
10536     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10537     { Bad_Opcode },
10538     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10539   },
10540  {
10541     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10542     { Bad_Opcode },
10543     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10544   },
10545   {
10546     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10547     { Bad_Opcode },
10548     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10549   },
10550   {
10551     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10552     { Bad_Opcode },
10553     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10554   },
10555   {
10556     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10557     { Bad_Opcode },
10558     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10559   },
10560   {
10561     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10562     { Bad_Opcode },
10563     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10564   },
10565   {
10566     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10567     { Bad_Opcode },
10568     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10569   },
10570   {
10571     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10572     { Bad_Opcode },
10573     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10574   },
10575   {
10576     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10577     { Bad_Opcode },
10578     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10579   },
10580   {
10581     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10582     { Bad_Opcode },
10583     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10584   },
10585   {
10586     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10587     { Bad_Opcode },
10588     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10589   },
10590   {
10591     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10592     { Bad_Opcode },
10593     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10594   },
10595   {
10596     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10597     { Bad_Opcode },
10598     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10599   },
10600   {
10601     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10602     { Bad_Opcode },
10603     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10604   },
10605   {
10606     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10607     { Bad_Opcode },
10608     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10609   },
10610   {
10611     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10612     { Bad_Opcode },
10613     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10614   },
10615   {
10616     /* MOD_VEX_0F50 */
10617     { Bad_Opcode },
10618     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
10619   },
10620   {
10621     /* MOD_VEX_0F71_REG_2 */
10622     { Bad_Opcode },
10623     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10624   },
10625   {
10626     /* MOD_VEX_0F71_REG_4 */
10627     { Bad_Opcode },
10628     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10629   },
10630   {
10631     /* MOD_VEX_0F71_REG_6 */
10632     { Bad_Opcode },
10633     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10634   },
10635   {
10636     /* MOD_VEX_0F72_REG_2 */
10637     { Bad_Opcode },
10638     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10639   },
10640   {
10641     /* MOD_VEX_0F72_REG_4 */
10642     { Bad_Opcode },
10643     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10644   },
10645   {
10646     /* MOD_VEX_0F72_REG_6 */
10647     { Bad_Opcode },
10648     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10649   },
10650   {
10651     /* MOD_VEX_0F73_REG_2 */
10652     { Bad_Opcode },
10653     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10654   },
10655   {
10656     /* MOD_VEX_0F73_REG_3 */
10657     { Bad_Opcode },
10658     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10659   },
10660   {
10661     /* MOD_VEX_0F73_REG_6 */
10662     { Bad_Opcode },
10663     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10664   },
10665   {
10666     /* MOD_VEX_0F73_REG_7 */
10667     { Bad_Opcode },
10668     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10669   },
10670   {
10671     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10672     { "kmovw",          { Ew, MaskG }, 0 },
10673     { Bad_Opcode },
10674   },
10675   {
10676     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10677     { "kmovq",          { Eq, MaskG }, 0 },
10678     { Bad_Opcode },
10679   },
10680   {
10681     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10682     { "kmovb",          { Eb, MaskG }, 0 },
10683     { Bad_Opcode },
10684   },
10685   {
10686     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10687     { "kmovd",          { Ed, MaskG }, 0 },
10688     { Bad_Opcode },
10689   },
10690   {
10691     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10692     { Bad_Opcode },
10693     { "kmovw",          { MaskG, Rdq }, 0 },
10694   },
10695   {
10696     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10697     { Bad_Opcode },
10698     { "kmovb",          { MaskG, Rdq }, 0 },
10699   },
10700   {
10701     /* MOD_VEX_0F92_P_3_LEN_0 */
10702     { Bad_Opcode },
10703     { "kmovK",          { MaskG, Rdq }, 0 },
10704   },
10705   {
10706     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10707     { Bad_Opcode },
10708     { "kmovw",          { Gdq, MaskR }, 0 },
10709   },
10710   {
10711     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10712     { Bad_Opcode },
10713     { "kmovb",          { Gdq, MaskR }, 0 },
10714   },
10715   {
10716     /* MOD_VEX_0F93_P_3_LEN_0 */
10717     { Bad_Opcode },
10718     { "kmovK",          { Gdq, MaskR }, 0 },
10719   },
10720   {
10721     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10722     { Bad_Opcode },
10723     { "kortestw", { MaskG, MaskR }, 0 },
10724   },
10725   {
10726     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10727     { Bad_Opcode },
10728     { "kortestq", { MaskG, MaskR }, 0 },
10729   },
10730   {
10731     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10732     { Bad_Opcode },
10733     { "kortestb", { MaskG, MaskR }, 0 },
10734   },
10735   {
10736     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10737     { Bad_Opcode },
10738     { "kortestd", { MaskG, MaskR }, 0 },
10739   },
10740   {
10741     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10742     { Bad_Opcode },
10743     { "ktestw", { MaskG, MaskR }, 0 },
10744   },
10745   {
10746     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10747     { Bad_Opcode },
10748     { "ktestq", { MaskG, MaskR }, 0 },
10749   },
10750   {
10751     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10752     { Bad_Opcode },
10753     { "ktestb", { MaskG, MaskR }, 0 },
10754   },
10755   {
10756     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10757     { Bad_Opcode },
10758     { "ktestd", { MaskG, MaskR }, 0 },
10759   },
10760   {
10761     /* MOD_VEX_0FAE_REG_2 */
10762     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10763   },
10764   {
10765     /* MOD_VEX_0FAE_REG_3 */
10766     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10767   },
10768   {
10769     /* MOD_VEX_0FD7_PREFIX_2 */
10770     { Bad_Opcode },
10771     { "vpmovmskb",      { Gdq, XS }, 0 },
10772   },
10773   {
10774     /* MOD_VEX_0FE7_PREFIX_2 */
10775     { "vmovntdq",       { Mx, XM }, 0 },
10776   },
10777   {
10778     /* MOD_VEX_0FF0_PREFIX_3 */
10779     { "vlddqu",         { XM, M }, 0 },
10780   },
10781   {
10782     /* MOD_VEX_0F381A_PREFIX_2 */
10783     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10784   },
10785   {
10786     /* MOD_VEX_0F382A_PREFIX_2 */
10787     { "vmovntdqa",      { XM, Mx }, 0 },
10788   },
10789   {
10790     /* MOD_VEX_0F382C_PREFIX_2 */
10791     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10792   },
10793   {
10794     /* MOD_VEX_0F382D_PREFIX_2 */
10795     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10796   },
10797   {
10798     /* MOD_VEX_0F382E_PREFIX_2 */
10799     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10800   },
10801   {
10802     /* MOD_VEX_0F382F_PREFIX_2 */
10803     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10804   },
10805   {
10806     /* MOD_VEX_0F385A_PREFIX_2 */
10807     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10808   },
10809   {
10810     /* MOD_VEX_0F388C_PREFIX_2 */
10811     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10812   },
10813   {
10814     /* MOD_VEX_0F388E_PREFIX_2 */
10815     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10816   },
10817   {
10818     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10819     { Bad_Opcode },
10820     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10821   },
10822   {
10823     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10824     { Bad_Opcode },
10825     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10826   },
10827   {
10828     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10829     { Bad_Opcode },
10830     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10831   },
10832   {
10833     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10834     { Bad_Opcode },
10835     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10836   },
10837   {
10838     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10839     { Bad_Opcode },
10840     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10841   },
10842   {
10843     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10844     { Bad_Opcode },
10845     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10846   },
10847   {
10848     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10849     { Bad_Opcode },
10850     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10851   },
10852   {
10853     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10854     { Bad_Opcode },
10855     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10856   },
10857
10858 #include "i386-dis-evex-mod.h"
10859 };
10860
10861 static const struct dis386 rm_table[][8] = {
10862   {
10863     /* RM_C6_REG_7 */
10864     { "xabort",         { Skip_MODRM, Ib }, 0 },
10865   },
10866   {
10867     /* RM_C7_REG_7 */
10868     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10869   },
10870   {
10871     /* RM_0F01_REG_0 */
10872     { "enclv",          { Skip_MODRM }, 0 },
10873     { "vmcall",         { Skip_MODRM }, 0 },
10874     { "vmlaunch",       { Skip_MODRM }, 0 },
10875     { "vmresume",       { Skip_MODRM }, 0 },
10876     { "vmxoff",         { Skip_MODRM }, 0 },
10877     { "pconfig",        { Skip_MODRM }, 0 },
10878   },
10879   {
10880     /* RM_0F01_REG_1 */
10881     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10882     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10883     { "clac",           { Skip_MODRM }, 0 },
10884     { "stac",           { Skip_MODRM }, 0 },
10885     { Bad_Opcode },
10886     { Bad_Opcode },
10887     { Bad_Opcode },
10888     { "encls",          { Skip_MODRM }, 0 },
10889   },
10890   {
10891     /* RM_0F01_REG_2 */
10892     { "xgetbv",         { Skip_MODRM }, 0 },
10893     { "xsetbv",         { Skip_MODRM }, 0 },
10894     { Bad_Opcode },
10895     { Bad_Opcode },
10896     { "vmfunc",         { Skip_MODRM }, 0 },
10897     { "xend",           { Skip_MODRM }, 0 },
10898     { "xtest",          { Skip_MODRM }, 0 },
10899     { "enclu",          { Skip_MODRM }, 0 },
10900   },
10901   {
10902     /* RM_0F01_REG_3 */
10903     { "vmrun",          { Skip_MODRM }, 0 },
10904     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
10905     { "vmload",         { Skip_MODRM }, 0 },
10906     { "vmsave",         { Skip_MODRM }, 0 },
10907     { "stgi",           { Skip_MODRM }, 0 },
10908     { "clgi",           { Skip_MODRM }, 0 },
10909     { "skinit",         { Skip_MODRM }, 0 },
10910     { "invlpga",        { Skip_MODRM }, 0 },
10911   },
10912   {
10913     /* RM_0F01_REG_5_MOD_3 */
10914     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
10915     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
10916     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
10917     { Bad_Opcode },
10918     { Bad_Opcode },
10919     { Bad_Opcode },
10920     { "rdpkru",         { Skip_MODRM }, 0 },
10921     { "wrpkru",         { Skip_MODRM }, 0 },
10922   },
10923   {
10924     /* RM_0F01_REG_7_MOD_3 */
10925     { "swapgs",         { Skip_MODRM }, 0  },
10926     { "rdtscp",         { Skip_MODRM }, 0  },
10927     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
10928     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
10929     { "clzero",         { Skip_MODRM }, 0  },
10930     { "rdpru",          { Skip_MODRM }, 0  },
10931   },
10932   {
10933     /* RM_0F1E_P_1_MOD_3_REG_7 */
10934     { "nopQ",           { Ev }, 0 },
10935     { "nopQ",           { Ev }, 0 },
10936     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
10937     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
10938     { "nopQ",           { Ev }, 0 },
10939     { "nopQ",           { Ev }, 0 },
10940     { "nopQ",           { Ev }, 0 },
10941     { "nopQ",           { Ev }, 0 },
10942   },
10943   {
10944     /* RM_0FAE_REG_6_MOD_3 */
10945     { "mfence",         { Skip_MODRM }, 0 },
10946   },
10947   {
10948     /* RM_0FAE_REG_7_MOD_3 */
10949     { "sfence",         { Skip_MODRM }, 0 },
10950
10951   },
10952 };
10953
10954 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10955
10956 /* We use the high bit to indicate different name for the same
10957    prefix.  */
10958 #define REP_PREFIX      (0xf3 | 0x100)
10959 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10960 #define XRELEASE_PREFIX (0xf3 | 0x400)
10961 #define BND_PREFIX      (0xf2 | 0x400)
10962 #define NOTRACK_PREFIX  (0x3e | 0x100)
10963
10964 /* Remember if the current op is a jump instruction.  */
10965 static bfd_boolean op_is_jump = FALSE;
10966
10967 static int
10968 ckprefix (void)
10969 {
10970   int newrex, i, length;
10971   rex = 0;
10972   prefixes = 0;
10973   used_prefixes = 0;
10974   rex_used = 0;
10975   last_lock_prefix = -1;
10976   last_repz_prefix = -1;
10977   last_repnz_prefix = -1;
10978   last_data_prefix = -1;
10979   last_addr_prefix = -1;
10980   last_rex_prefix = -1;
10981   last_seg_prefix = -1;
10982   fwait_prefix = -1;
10983   active_seg_prefix = 0;
10984   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10985     all_prefixes[i] = 0;
10986   i = 0;
10987   length = 0;
10988   /* The maximum instruction length is 15bytes.  */
10989   while (length < MAX_CODE_LENGTH - 1)
10990     {
10991       FETCH_DATA (the_info, codep + 1);
10992       newrex = 0;
10993       switch (*codep)
10994         {
10995         /* REX prefixes family.  */
10996         case 0x40:
10997         case 0x41:
10998         case 0x42:
10999         case 0x43:
11000         case 0x44:
11001         case 0x45:
11002         case 0x46:
11003         case 0x47:
11004         case 0x48:
11005         case 0x49:
11006         case 0x4a:
11007         case 0x4b:
11008         case 0x4c:
11009         case 0x4d:
11010         case 0x4e:
11011         case 0x4f:
11012           if (address_mode == mode_64bit)
11013             newrex = *codep;
11014           else
11015             return 1;
11016           last_rex_prefix = i;
11017           break;
11018         case 0xf3:
11019           prefixes |= PREFIX_REPZ;
11020           last_repz_prefix = i;
11021           break;
11022         case 0xf2:
11023           prefixes |= PREFIX_REPNZ;
11024           last_repnz_prefix = i;
11025           break;
11026         case 0xf0:
11027           prefixes |= PREFIX_LOCK;
11028           last_lock_prefix = i;
11029           break;
11030         case 0x2e:
11031           prefixes |= PREFIX_CS;
11032           last_seg_prefix = i;
11033           active_seg_prefix = PREFIX_CS;
11034           break;
11035         case 0x36:
11036           prefixes |= PREFIX_SS;
11037           last_seg_prefix = i;
11038           active_seg_prefix = PREFIX_SS;
11039           break;
11040         case 0x3e:
11041           prefixes |= PREFIX_DS;
11042           last_seg_prefix = i;
11043           active_seg_prefix = PREFIX_DS;
11044           break;
11045         case 0x26:
11046           prefixes |= PREFIX_ES;
11047           last_seg_prefix = i;
11048           active_seg_prefix = PREFIX_ES;
11049           break;
11050         case 0x64:
11051           prefixes |= PREFIX_FS;
11052           last_seg_prefix = i;
11053           active_seg_prefix = PREFIX_FS;
11054           break;
11055         case 0x65:
11056           prefixes |= PREFIX_GS;
11057           last_seg_prefix = i;
11058           active_seg_prefix = PREFIX_GS;
11059           break;
11060         case 0x66:
11061           prefixes |= PREFIX_DATA;
11062           last_data_prefix = i;
11063           break;
11064         case 0x67:
11065           prefixes |= PREFIX_ADDR;
11066           last_addr_prefix = i;
11067           break;
11068         case FWAIT_OPCODE:
11069           /* fwait is really an instruction.  If there are prefixes
11070              before the fwait, they belong to the fwait, *not* to the
11071              following instruction.  */
11072           fwait_prefix = i;
11073           if (prefixes || rex)
11074             {
11075               prefixes |= PREFIX_FWAIT;
11076               codep++;
11077               /* This ensures that the previous REX prefixes are noticed
11078                  as unused prefixes, as in the return case below.  */
11079               rex_used = rex;
11080               return 1;
11081             }
11082           prefixes = PREFIX_FWAIT;
11083           break;
11084         default:
11085           return 1;
11086         }
11087       /* Rex is ignored when followed by another prefix.  */
11088       if (rex)
11089         {
11090           rex_used = rex;
11091           return 1;
11092         }
11093       if (*codep != FWAIT_OPCODE)
11094         all_prefixes[i++] = *codep;
11095       rex = newrex;
11096       codep++;
11097       length++;
11098     }
11099   return 0;
11100 }
11101
11102 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11103    prefix byte.  */
11104
11105 static const char *
11106 prefix_name (int pref, int sizeflag)
11107 {
11108   static const char *rexes [16] =
11109     {
11110       "rex",            /* 0x40 */
11111       "rex.B",          /* 0x41 */
11112       "rex.X",          /* 0x42 */
11113       "rex.XB",         /* 0x43 */
11114       "rex.R",          /* 0x44 */
11115       "rex.RB",         /* 0x45 */
11116       "rex.RX",         /* 0x46 */
11117       "rex.RXB",        /* 0x47 */
11118       "rex.W",          /* 0x48 */
11119       "rex.WB",         /* 0x49 */
11120       "rex.WX",         /* 0x4a */
11121       "rex.WXB",        /* 0x4b */
11122       "rex.WR",         /* 0x4c */
11123       "rex.WRB",        /* 0x4d */
11124       "rex.WRX",        /* 0x4e */
11125       "rex.WRXB",       /* 0x4f */
11126     };
11127
11128   switch (pref)
11129     {
11130     /* REX prefixes family.  */
11131     case 0x40:
11132     case 0x41:
11133     case 0x42:
11134     case 0x43:
11135     case 0x44:
11136     case 0x45:
11137     case 0x46:
11138     case 0x47:
11139     case 0x48:
11140     case 0x49:
11141     case 0x4a:
11142     case 0x4b:
11143     case 0x4c:
11144     case 0x4d:
11145     case 0x4e:
11146     case 0x4f:
11147       return rexes [pref - 0x40];
11148     case 0xf3:
11149       return "repz";
11150     case 0xf2:
11151       return "repnz";
11152     case 0xf0:
11153       return "lock";
11154     case 0x2e:
11155       return "cs";
11156     case 0x36:
11157       return "ss";
11158     case 0x3e:
11159       return "ds";
11160     case 0x26:
11161       return "es";
11162     case 0x64:
11163       return "fs";
11164     case 0x65:
11165       return "gs";
11166     case 0x66:
11167       return (sizeflag & DFLAG) ? "data16" : "data32";
11168     case 0x67:
11169       if (address_mode == mode_64bit)
11170         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11171       else
11172         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11173     case FWAIT_OPCODE:
11174       return "fwait";
11175     case REP_PREFIX:
11176       return "rep";
11177     case XACQUIRE_PREFIX:
11178       return "xacquire";
11179     case XRELEASE_PREFIX:
11180       return "xrelease";
11181     case BND_PREFIX:
11182       return "bnd";
11183     case NOTRACK_PREFIX:
11184       return "notrack";
11185     default:
11186       return NULL;
11187     }
11188 }
11189
11190 static char op_out[MAX_OPERANDS][100];
11191 static int op_ad, op_index[MAX_OPERANDS];
11192 static int two_source_ops;
11193 static bfd_vma op_address[MAX_OPERANDS];
11194 static bfd_vma op_riprel[MAX_OPERANDS];
11195 static bfd_vma start_pc;
11196
11197 /*
11198  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11199  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11200  *   section of the "Virtual 8086 Mode" chapter.)
11201  * 'pc' should be the address of this instruction, it will
11202  *   be used to print the target address if this is a relative jump or call
11203  * The function returns the length of this instruction in bytes.
11204  */
11205
11206 static char intel_syntax;
11207 static char intel_mnemonic = !SYSV386_COMPAT;
11208 static char open_char;
11209 static char close_char;
11210 static char separator_char;
11211 static char scale_char;
11212
11213 enum x86_64_isa
11214 {
11215   amd64 = 1,
11216   intel64
11217 };
11218
11219 static enum x86_64_isa isa64;
11220
11221 /* Here for backwards compatibility.  When gdb stops using
11222    print_insn_i386_att and print_insn_i386_intel these functions can
11223    disappear, and print_insn_i386 be merged into print_insn.  */
11224 int
11225 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11226 {
11227   intel_syntax = 0;
11228
11229   return print_insn (pc, info);
11230 }
11231
11232 int
11233 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11234 {
11235   intel_syntax = 1;
11236
11237   return print_insn (pc, info);
11238 }
11239
11240 int
11241 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11242 {
11243   intel_syntax = -1;
11244
11245   return print_insn (pc, info);
11246 }
11247
11248 void
11249 print_i386_disassembler_options (FILE *stream)
11250 {
11251   fprintf (stream, _("\n\
11252 The following i386/x86-64 specific disassembler options are supported for use\n\
11253 with the -M switch (multiple options should be separated by commas):\n"));
11254
11255   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11256   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11257   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11258   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11259   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11260   fprintf (stream, _("  att-mnemonic\n"
11261                      "              Display instruction in AT&T mnemonic\n"));
11262   fprintf (stream, _("  intel-mnemonic\n"
11263                      "              Display instruction in Intel mnemonic\n"));
11264   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11265   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11266   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11267   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11268   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11269   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11270   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11271   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11272 }
11273
11274 /* Bad opcode.  */
11275 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11276
11277 /* Get a pointer to struct dis386 with a valid name.  */
11278
11279 static const struct dis386 *
11280 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11281 {
11282   int vindex, vex_table_index;
11283
11284   if (dp->name != NULL)
11285     return dp;
11286
11287   switch (dp->op[0].bytemode)
11288     {
11289     case USE_REG_TABLE:
11290       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11291       break;
11292
11293     case USE_MOD_TABLE:
11294       vindex = modrm.mod == 0x3 ? 1 : 0;
11295       dp = &mod_table[dp->op[1].bytemode][vindex];
11296       break;
11297
11298     case USE_RM_TABLE:
11299       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11300       break;
11301
11302     case USE_PREFIX_TABLE:
11303       if (need_vex)
11304         {
11305           /* The prefix in VEX is implicit.  */
11306           switch (vex.prefix)
11307             {
11308             case 0:
11309               vindex = 0;
11310               break;
11311             case REPE_PREFIX_OPCODE:
11312               vindex = 1;
11313               break;
11314             case DATA_PREFIX_OPCODE:
11315               vindex = 2;
11316               break;
11317             case REPNE_PREFIX_OPCODE:
11318               vindex = 3;
11319               break;
11320             default:
11321               abort ();
11322               break;
11323             }
11324         }
11325       else
11326         {
11327           int last_prefix = -1;
11328           int prefix = 0;
11329           vindex = 0;
11330           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11331              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11332              last one wins.  */
11333           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11334             {
11335               if (last_repz_prefix > last_repnz_prefix)
11336                 {
11337                   vindex = 1;
11338                   prefix = PREFIX_REPZ;
11339                   last_prefix = last_repz_prefix;
11340                 }
11341               else
11342                 {
11343                   vindex = 3;
11344                   prefix = PREFIX_REPNZ;
11345                   last_prefix = last_repnz_prefix;
11346                 }
11347
11348               /* Check if prefix should be ignored.  */
11349               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11350                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11351                    & prefix) != 0)
11352                 vindex = 0;
11353             }
11354
11355           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11356             {
11357               vindex = 2;
11358               prefix = PREFIX_DATA;
11359               last_prefix = last_data_prefix;
11360             }
11361
11362           if (vindex != 0)
11363             {
11364               used_prefixes |= prefix;
11365               all_prefixes[last_prefix] = 0;
11366             }
11367         }
11368       dp = &prefix_table[dp->op[1].bytemode][vindex];
11369       break;
11370
11371     case USE_X86_64_TABLE:
11372       vindex = address_mode == mode_64bit ? 1 : 0;
11373       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11374       break;
11375
11376     case USE_3BYTE_TABLE:
11377       FETCH_DATA (info, codep + 2);
11378       vindex = *codep++;
11379       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11380       end_codep = codep;
11381       modrm.mod = (*codep >> 6) & 3;
11382       modrm.reg = (*codep >> 3) & 7;
11383       modrm.rm = *codep & 7;
11384       break;
11385
11386     case USE_VEX_LEN_TABLE:
11387       if (!need_vex)
11388         abort ();
11389
11390       switch (vex.length)
11391         {
11392         case 128:
11393           vindex = 0;
11394           break;
11395         case 256:
11396           vindex = 1;
11397           break;
11398         default:
11399           abort ();
11400           break;
11401         }
11402
11403       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11404       break;
11405
11406     case USE_EVEX_LEN_TABLE:
11407       if (!vex.evex)
11408         abort ();
11409
11410       switch (vex.length)
11411         {
11412         case 128:
11413           vindex = 0;
11414           break;
11415         case 256:
11416           vindex = 1;
11417           break;
11418         case 512:
11419           vindex = 2;
11420           break;
11421         default:
11422           abort ();
11423           break;
11424         }
11425
11426       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11427       break;
11428
11429     case USE_XOP_8F_TABLE:
11430       FETCH_DATA (info, codep + 3);
11431       rex = ~(*codep >> 5) & 0x7;
11432
11433       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11434       switch ((*codep & 0x1f))
11435         {
11436         default:
11437           dp = &bad_opcode;
11438           return dp;
11439         case 0x8:
11440           vex_table_index = XOP_08;
11441           break;
11442         case 0x9:
11443           vex_table_index = XOP_09;
11444           break;
11445         case 0xa:
11446           vex_table_index = XOP_0A;
11447           break;
11448         }
11449       codep++;
11450       vex.w = *codep & 0x80;
11451       if (vex.w && address_mode == mode_64bit)
11452         rex |= REX_W;
11453
11454       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11455       if (address_mode != mode_64bit)
11456         {
11457           /* In 16/32-bit mode REX_B is silently ignored.  */
11458           rex &= ~REX_B;
11459         }
11460
11461       vex.length = (*codep & 0x4) ? 256 : 128;
11462       switch ((*codep & 0x3))
11463         {
11464         case 0:
11465           break;
11466         case 1:
11467           vex.prefix = DATA_PREFIX_OPCODE;
11468           break;
11469         case 2:
11470           vex.prefix = REPE_PREFIX_OPCODE;
11471           break;
11472         case 3:
11473           vex.prefix = REPNE_PREFIX_OPCODE;
11474           break;
11475         }
11476       need_vex = 1;
11477       need_vex_reg = 1;
11478       codep++;
11479       vindex = *codep++;
11480       dp = &xop_table[vex_table_index][vindex];
11481
11482       end_codep = codep;
11483       FETCH_DATA (info, codep + 1);
11484       modrm.mod = (*codep >> 6) & 3;
11485       modrm.reg = (*codep >> 3) & 7;
11486       modrm.rm = *codep & 7;
11487
11488       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
11489          having to decode the bits for every otherwise valid encoding.  */
11490       if (vex.prefix)
11491         return &bad_opcode;
11492       break;
11493
11494     case USE_VEX_C4_TABLE:
11495       /* VEX prefix.  */
11496       FETCH_DATA (info, codep + 3);
11497       rex = ~(*codep >> 5) & 0x7;
11498       switch ((*codep & 0x1f))
11499         {
11500         default:
11501           dp = &bad_opcode;
11502           return dp;
11503         case 0x1:
11504           vex_table_index = VEX_0F;
11505           break;
11506         case 0x2:
11507           vex_table_index = VEX_0F38;
11508           break;
11509         case 0x3:
11510           vex_table_index = VEX_0F3A;
11511           break;
11512         }
11513       codep++;
11514       vex.w = *codep & 0x80;
11515       if (address_mode == mode_64bit)
11516         {
11517           if (vex.w)
11518             rex |= REX_W;
11519         }
11520       else
11521         {
11522           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11523              is ignored, other REX bits are 0 and the highest bit in
11524              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11525           rex = 0;
11526         }
11527       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11528       vex.length = (*codep & 0x4) ? 256 : 128;
11529       switch ((*codep & 0x3))
11530         {
11531         case 0:
11532           break;
11533         case 1:
11534           vex.prefix = DATA_PREFIX_OPCODE;
11535           break;
11536         case 2:
11537           vex.prefix = REPE_PREFIX_OPCODE;
11538           break;
11539         case 3:
11540           vex.prefix = REPNE_PREFIX_OPCODE;
11541           break;
11542         }
11543       need_vex = 1;
11544       need_vex_reg = 1;
11545       codep++;
11546       vindex = *codep++;
11547       dp = &vex_table[vex_table_index][vindex];
11548       end_codep = codep;
11549       /* There is no MODRM byte for VEX0F 77.  */
11550       if (vex_table_index != VEX_0F || vindex != 0x77)
11551         {
11552           FETCH_DATA (info, codep + 1);
11553           modrm.mod = (*codep >> 6) & 3;
11554           modrm.reg = (*codep >> 3) & 7;
11555           modrm.rm = *codep & 7;
11556         }
11557       break;
11558
11559     case USE_VEX_C5_TABLE:
11560       /* VEX prefix.  */
11561       FETCH_DATA (info, codep + 2);
11562       rex = (*codep & 0x80) ? 0 : REX_R;
11563
11564       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11565          VEX.vvvv is 1.  */
11566       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11567       vex.length = (*codep & 0x4) ? 256 : 128;
11568       switch ((*codep & 0x3))
11569         {
11570         case 0:
11571           break;
11572         case 1:
11573           vex.prefix = DATA_PREFIX_OPCODE;
11574           break;
11575         case 2:
11576           vex.prefix = REPE_PREFIX_OPCODE;
11577           break;
11578         case 3:
11579           vex.prefix = REPNE_PREFIX_OPCODE;
11580           break;
11581         }
11582       need_vex = 1;
11583       need_vex_reg = 1;
11584       codep++;
11585       vindex = *codep++;
11586       dp = &vex_table[dp->op[1].bytemode][vindex];
11587       end_codep = codep;
11588       /* There is no MODRM byte for VEX 77.  */
11589       if (vindex != 0x77)
11590         {
11591           FETCH_DATA (info, codep + 1);
11592           modrm.mod = (*codep >> 6) & 3;
11593           modrm.reg = (*codep >> 3) & 7;
11594           modrm.rm = *codep & 7;
11595         }
11596       break;
11597
11598     case USE_VEX_W_TABLE:
11599       if (!need_vex)
11600         abort ();
11601
11602       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11603       break;
11604
11605     case USE_EVEX_TABLE:
11606       two_source_ops = 0;
11607       /* EVEX prefix.  */
11608       vex.evex = 1;
11609       FETCH_DATA (info, codep + 4);
11610       /* The first byte after 0x62.  */
11611       rex = ~(*codep >> 5) & 0x7;
11612       vex.r = *codep & 0x10;
11613       switch ((*codep & 0xf))
11614         {
11615         default:
11616           return &bad_opcode;
11617         case 0x1:
11618           vex_table_index = EVEX_0F;
11619           break;
11620         case 0x2:
11621           vex_table_index = EVEX_0F38;
11622           break;
11623         case 0x3:
11624           vex_table_index = EVEX_0F3A;
11625           break;
11626         }
11627
11628       /* The second byte after 0x62.  */
11629       codep++;
11630       vex.w = *codep & 0x80;
11631       if (vex.w && address_mode == mode_64bit)
11632         rex |= REX_W;
11633
11634       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11635
11636       /* The U bit.  */
11637       if (!(*codep & 0x4))
11638         return &bad_opcode;
11639
11640       switch ((*codep & 0x3))
11641         {
11642         case 0:
11643           break;
11644         case 1:
11645           vex.prefix = DATA_PREFIX_OPCODE;
11646           break;
11647         case 2:
11648           vex.prefix = REPE_PREFIX_OPCODE;
11649           break;
11650         case 3:
11651           vex.prefix = REPNE_PREFIX_OPCODE;
11652           break;
11653         }
11654
11655       /* The third byte after 0x62.  */
11656       codep++;
11657
11658       /* Remember the static rounding bits.  */
11659       vex.ll = (*codep >> 5) & 3;
11660       vex.b = (*codep & 0x10) != 0;
11661
11662       vex.v = *codep & 0x8;
11663       vex.mask_register_specifier = *codep & 0x7;
11664       vex.zeroing = *codep & 0x80;
11665
11666       if (address_mode != mode_64bit)
11667         {
11668           /* In 16/32-bit mode silently ignore following bits.  */
11669           rex &= ~REX_B;
11670           vex.r = 1;
11671           vex.v = 1;
11672         }
11673
11674       need_vex = 1;
11675       need_vex_reg = 1;
11676       codep++;
11677       vindex = *codep++;
11678       dp = &evex_table[vex_table_index][vindex];
11679       end_codep = codep;
11680       FETCH_DATA (info, codep + 1);
11681       modrm.mod = (*codep >> 6) & 3;
11682       modrm.reg = (*codep >> 3) & 7;
11683       modrm.rm = *codep & 7;
11684
11685       /* Set vector length.  */
11686       if (modrm.mod == 3 && vex.b)
11687         vex.length = 512;
11688       else
11689         {
11690           switch (vex.ll)
11691             {
11692             case 0x0:
11693               vex.length = 128;
11694               break;
11695             case 0x1:
11696               vex.length = 256;
11697               break;
11698             case 0x2:
11699               vex.length = 512;
11700               break;
11701             default:
11702               return &bad_opcode;
11703             }
11704         }
11705       break;
11706
11707     case 0:
11708       dp = &bad_opcode;
11709       break;
11710
11711     default:
11712       abort ();
11713     }
11714
11715   if (dp->name != NULL)
11716     return dp;
11717   else
11718     return get_valid_dis386 (dp, info);
11719 }
11720
11721 static void
11722 get_sib (disassemble_info *info, int sizeflag)
11723 {
11724   /* If modrm.mod == 3, operand must be register.  */
11725   if (need_modrm
11726       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11727       && modrm.mod != 3
11728       && modrm.rm == 4)
11729     {
11730       FETCH_DATA (info, codep + 2);
11731       sib.index = (codep [1] >> 3) & 7;
11732       sib.scale = (codep [1] >> 6) & 3;
11733       sib.base = codep [1] & 7;
11734     }
11735 }
11736
11737 static int
11738 print_insn (bfd_vma pc, disassemble_info *info)
11739 {
11740   const struct dis386 *dp;
11741   int i;
11742   char *op_txt[MAX_OPERANDS];
11743   int needcomma;
11744   int sizeflag, orig_sizeflag;
11745   const char *p;
11746   struct dis_private priv;
11747   int prefix_length;
11748
11749   priv.orig_sizeflag = AFLAG | DFLAG;
11750   if ((info->mach & bfd_mach_i386_i386) != 0)
11751     address_mode = mode_32bit;
11752   else if (info->mach == bfd_mach_i386_i8086)
11753     {
11754       address_mode = mode_16bit;
11755       priv.orig_sizeflag = 0;
11756     }
11757   else
11758     address_mode = mode_64bit;
11759
11760   if (intel_syntax == (char) -1)
11761     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11762
11763   for (p = info->disassembler_options; p != NULL; )
11764     {
11765       if (CONST_STRNEQ (p, "amd64"))
11766         isa64 = amd64;
11767       else if (CONST_STRNEQ (p, "intel64"))
11768         isa64 = intel64;
11769       else if (CONST_STRNEQ (p, "x86-64"))
11770         {
11771           address_mode = mode_64bit;
11772           priv.orig_sizeflag |= AFLAG | DFLAG;
11773         }
11774       else if (CONST_STRNEQ (p, "i386"))
11775         {
11776           address_mode = mode_32bit;
11777           priv.orig_sizeflag |= AFLAG | DFLAG;
11778         }
11779       else if (CONST_STRNEQ (p, "i8086"))
11780         {
11781           address_mode = mode_16bit;
11782           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
11783         }
11784       else if (CONST_STRNEQ (p, "intel"))
11785         {
11786           intel_syntax = 1;
11787           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11788             intel_mnemonic = 1;
11789         }
11790       else if (CONST_STRNEQ (p, "att"))
11791         {
11792           intel_syntax = 0;
11793           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11794             intel_mnemonic = 0;
11795         }
11796       else if (CONST_STRNEQ (p, "addr"))
11797         {
11798           if (address_mode == mode_64bit)
11799             {
11800               if (p[4] == '3' && p[5] == '2')
11801                 priv.orig_sizeflag &= ~AFLAG;
11802               else if (p[4] == '6' && p[5] == '4')
11803                 priv.orig_sizeflag |= AFLAG;
11804             }
11805           else
11806             {
11807               if (p[4] == '1' && p[5] == '6')
11808                 priv.orig_sizeflag &= ~AFLAG;
11809               else if (p[4] == '3' && p[5] == '2')
11810                 priv.orig_sizeflag |= AFLAG;
11811             }
11812         }
11813       else if (CONST_STRNEQ (p, "data"))
11814         {
11815           if (p[4] == '1' && p[5] == '6')
11816             priv.orig_sizeflag &= ~DFLAG;
11817           else if (p[4] == '3' && p[5] == '2')
11818             priv.orig_sizeflag |= DFLAG;
11819         }
11820       else if (CONST_STRNEQ (p, "suffix"))
11821         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11822
11823       p = strchr (p, ',');
11824       if (p != NULL)
11825         p++;
11826     }
11827
11828   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11829     {
11830       (*info->fprintf_func) (info->stream,
11831                              _("64-bit address is disabled"));
11832       return -1;
11833     }
11834
11835   if (intel_syntax)
11836     {
11837       names64 = intel_names64;
11838       names32 = intel_names32;
11839       names16 = intel_names16;
11840       names8 = intel_names8;
11841       names8rex = intel_names8rex;
11842       names_seg = intel_names_seg;
11843       names_mm = intel_names_mm;
11844       names_bnd = intel_names_bnd;
11845       names_xmm = intel_names_xmm;
11846       names_ymm = intel_names_ymm;
11847       names_zmm = intel_names_zmm;
11848       index64 = intel_index64;
11849       index32 = intel_index32;
11850       names_mask = intel_names_mask;
11851       index16 = intel_index16;
11852       open_char = '[';
11853       close_char = ']';
11854       separator_char = '+';
11855       scale_char = '*';
11856     }
11857   else
11858     {
11859       names64 = att_names64;
11860       names32 = att_names32;
11861       names16 = att_names16;
11862       names8 = att_names8;
11863       names8rex = att_names8rex;
11864       names_seg = att_names_seg;
11865       names_mm = att_names_mm;
11866       names_bnd = att_names_bnd;
11867       names_xmm = att_names_xmm;
11868       names_ymm = att_names_ymm;
11869       names_zmm = att_names_zmm;
11870       index64 = att_index64;
11871       index32 = att_index32;
11872       names_mask = att_names_mask;
11873       index16 = att_index16;
11874       open_char = '(';
11875       close_char =  ')';
11876       separator_char = ',';
11877       scale_char = ',';
11878     }
11879
11880   /* The output looks better if we put 7 bytes on a line, since that
11881      puts most long word instructions on a single line.  Use 8 bytes
11882      for Intel L1OM.  */
11883   if ((info->mach & bfd_mach_l1om) != 0)
11884     info->bytes_per_line = 8;
11885   else
11886     info->bytes_per_line = 7;
11887
11888   info->private_data = &priv;
11889   priv.max_fetched = priv.the_buffer;
11890   priv.insn_start = pc;
11891
11892   obuf[0] = 0;
11893   for (i = 0; i < MAX_OPERANDS; ++i)
11894     {
11895       op_out[i][0] = 0;
11896       op_index[i] = -1;
11897     }
11898
11899   the_info = info;
11900   start_pc = pc;
11901   start_codep = priv.the_buffer;
11902   codep = priv.the_buffer;
11903
11904   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
11905     {
11906       const char *name;
11907
11908       /* Getting here means we tried for data but didn't get it.  That
11909          means we have an incomplete instruction of some sort.  Just
11910          print the first byte as a prefix or a .byte pseudo-op.  */
11911       if (codep > priv.the_buffer)
11912         {
11913           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11914           if (name != NULL)
11915             (*info->fprintf_func) (info->stream, "%s", name);
11916           else
11917             {
11918               /* Just print the first byte as a .byte instruction.  */
11919               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11920                                      (unsigned int) priv.the_buffer[0]);
11921             }
11922
11923           return 1;
11924         }
11925
11926       return -1;
11927     }
11928
11929   obufp = obuf;
11930   sizeflag = priv.orig_sizeflag;
11931
11932   if (!ckprefix () || rex_used)
11933     {
11934       /* Too many prefixes or unused REX prefixes.  */
11935       for (i = 0;
11936            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11937            i++)
11938         (*info->fprintf_func) (info->stream, "%s%s",
11939                                i == 0 ? "" : " ",
11940                                prefix_name (all_prefixes[i], sizeflag));
11941       return i;
11942     }
11943
11944   insn_codep = codep;
11945
11946   FETCH_DATA (info, codep + 1);
11947   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11948
11949   if (((prefixes & PREFIX_FWAIT)
11950        && ((*codep < 0xd8) || (*codep > 0xdf))))
11951     {
11952       /* Handle prefixes before fwait.  */
11953       for (i = 0; i < fwait_prefix && all_prefixes[i];
11954            i++)
11955         (*info->fprintf_func) (info->stream, "%s ",
11956                                prefix_name (all_prefixes[i], sizeflag));
11957       (*info->fprintf_func) (info->stream, "fwait");
11958       return i + 1;
11959     }
11960
11961   if (*codep == 0x0f)
11962     {
11963       unsigned char threebyte;
11964
11965       codep++;
11966       FETCH_DATA (info, codep + 1);
11967       threebyte = *codep;
11968       dp = &dis386_twobyte[threebyte];
11969       need_modrm = twobyte_has_modrm[*codep];
11970       codep++;
11971     }
11972   else
11973     {
11974       dp = &dis386[*codep];
11975       need_modrm = onebyte_has_modrm[*codep];
11976       codep++;
11977     }
11978
11979   /* Save sizeflag for printing the extra prefixes later before updating
11980      it for mnemonic and operand processing.  The prefix names depend
11981      only on the address mode.  */
11982   orig_sizeflag = sizeflag;
11983   if (prefixes & PREFIX_ADDR)
11984     sizeflag ^= AFLAG;
11985   if ((prefixes & PREFIX_DATA))
11986     sizeflag ^= DFLAG;
11987
11988   end_codep = codep;
11989   if (need_modrm)
11990     {
11991       FETCH_DATA (info, codep + 1);
11992       modrm.mod = (*codep >> 6) & 3;
11993       modrm.reg = (*codep >> 3) & 7;
11994       modrm.rm = *codep & 7;
11995     }
11996
11997   need_vex = 0;
11998   need_vex_reg = 0;
11999   vex_w_done = 0;
12000   memset (&vex, 0, sizeof (vex));
12001
12002   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12003     {
12004       get_sib (info, sizeflag);
12005       dofloat (sizeflag);
12006     }
12007   else
12008     {
12009       dp = get_valid_dis386 (dp, info);
12010       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12011         {
12012           get_sib (info, sizeflag);
12013           for (i = 0; i < MAX_OPERANDS; ++i)
12014             {
12015               obufp = op_out[i];
12016               op_ad = MAX_OPERANDS - 1 - i;
12017               if (dp->op[i].rtn)
12018                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12019               /* For EVEX instruction after the last operand masking
12020                  should be printed.  */
12021               if (i == 0 && vex.evex)
12022                 {
12023                   /* Don't print {%k0}.  */
12024                   if (vex.mask_register_specifier)
12025                     {
12026                       oappend ("{");
12027                       oappend (names_mask[vex.mask_register_specifier]);
12028                       oappend ("}");
12029                     }
12030                   if (vex.zeroing)
12031                     oappend ("{z}");
12032                 }
12033             }
12034         }
12035     }
12036
12037   /* Clear instruction information.  */
12038   if (the_info)
12039     {
12040       the_info->insn_info_valid = 0;
12041       the_info->branch_delay_insns = 0;
12042       the_info->data_size = 0;
12043       the_info->insn_type = dis_noninsn;
12044       the_info->target = 0;
12045       the_info->target2 = 0;
12046     }
12047
12048   /* Reset jump operation indicator.  */
12049   op_is_jump = FALSE;
12050
12051   {
12052     int jump_detection = 0;
12053
12054     /* Extract flags.  */
12055     for (i = 0; i < MAX_OPERANDS; ++i)
12056       {
12057         if ((dp->op[i].rtn == OP_J)
12058             || (dp->op[i].rtn == OP_indirE))
12059           jump_detection |= 1;
12060         else if ((dp->op[i].rtn == BND_Fixup)
12061                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12062           jump_detection |= 2;
12063         else if ((dp->op[i].bytemode == cond_jump_mode)
12064                  || (dp->op[i].bytemode == loop_jcxz_mode))
12065           jump_detection |= 4;
12066       }
12067
12068     /* Determine if this is a jump or branch.  */
12069     if ((jump_detection & 0x3) == 0x3)
12070       {
12071         op_is_jump = TRUE;
12072         if (jump_detection & 0x4)
12073           the_info->insn_type = dis_condbranch;
12074         else
12075           the_info->insn_type =
12076             (dp->name && !strncmp(dp->name, "call", 4))
12077             ? dis_jsr : dis_branch;
12078       }
12079   }
12080
12081   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12082      are all 0s in inverted form.  */
12083   if (need_vex && vex.register_specifier != 0)
12084     {
12085       (*info->fprintf_func) (info->stream, "(bad)");
12086       return end_codep - priv.the_buffer;
12087     }
12088
12089   /* Check if the REX prefix is used.  */
12090   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12091     all_prefixes[last_rex_prefix] = 0;
12092
12093   /* Check if the SEG prefix is used.  */
12094   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12095                    | PREFIX_FS | PREFIX_GS)) != 0
12096       && (used_prefixes & active_seg_prefix) != 0)
12097     all_prefixes[last_seg_prefix] = 0;
12098
12099   /* Check if the ADDR prefix is used.  */
12100   if ((prefixes & PREFIX_ADDR) != 0
12101       && (used_prefixes & PREFIX_ADDR) != 0)
12102     all_prefixes[last_addr_prefix] = 0;
12103
12104   /* Check if the DATA prefix is used.  */
12105   if ((prefixes & PREFIX_DATA) != 0
12106       && (used_prefixes & PREFIX_DATA) != 0
12107       && !need_vex)
12108     all_prefixes[last_data_prefix] = 0;
12109
12110   /* Print the extra prefixes.  */
12111   prefix_length = 0;
12112   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12113     if (all_prefixes[i])
12114       {
12115         const char *name;
12116         name = prefix_name (all_prefixes[i], orig_sizeflag);
12117         if (name == NULL)
12118           abort ();
12119         prefix_length += strlen (name) + 1;
12120         (*info->fprintf_func) (info->stream, "%s ", name);
12121       }
12122
12123   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12124      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12125      used by putop and MMX/SSE operand and may be overriden by the
12126      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12127      separately.  */
12128   if (dp->prefix_requirement == PREFIX_OPCODE
12129       && (((need_vex
12130             ? vex.prefix == REPE_PREFIX_OPCODE
12131               || vex.prefix == REPNE_PREFIX_OPCODE
12132             : (prefixes
12133                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12134            && (used_prefixes
12135                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12136           || (((need_vex
12137                 ? vex.prefix == DATA_PREFIX_OPCODE
12138                 : ((prefixes
12139                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12140                    == PREFIX_DATA))
12141                && (used_prefixes & PREFIX_DATA) == 0))
12142           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12143     {
12144       (*info->fprintf_func) (info->stream, "(bad)");
12145       return end_codep - priv.the_buffer;
12146     }
12147
12148   /* Check maximum code length.  */
12149   if ((codep - start_codep) > MAX_CODE_LENGTH)
12150     {
12151       (*info->fprintf_func) (info->stream, "(bad)");
12152       return MAX_CODE_LENGTH;
12153     }
12154
12155   obufp = mnemonicendp;
12156   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12157     oappend (" ");
12158   oappend (" ");
12159   (*info->fprintf_func) (info->stream, "%s", obuf);
12160
12161   /* The enter and bound instructions are printed with operands in the same
12162      order as the intel book; everything else is printed in reverse order.  */
12163   if (intel_syntax || two_source_ops)
12164     {
12165       bfd_vma riprel;
12166
12167       for (i = 0; i < MAX_OPERANDS; ++i)
12168         op_txt[i] = op_out[i];
12169
12170       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12171           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12172         {
12173           op_txt[2] = op_out[3];
12174           op_txt[3] = op_out[2];
12175         }
12176
12177       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12178         {
12179           op_ad = op_index[i];
12180           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12181           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12182           riprel = op_riprel[i];
12183           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12184           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12185         }
12186     }
12187   else
12188     {
12189       for (i = 0; i < MAX_OPERANDS; ++i)
12190         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12191     }
12192
12193   needcomma = 0;
12194   for (i = 0; i < MAX_OPERANDS; ++i)
12195     if (*op_txt[i])
12196       {
12197         if (needcomma)
12198           (*info->fprintf_func) (info->stream, ",");
12199         if (op_index[i] != -1 && !op_riprel[i])
12200           {
12201             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12202
12203             if (the_info && op_is_jump)
12204               {
12205                 the_info->insn_info_valid = 1;
12206                 the_info->branch_delay_insns = 0;
12207                 the_info->data_size = 0;
12208                 the_info->target = target;
12209                 the_info->target2 = 0;
12210               }
12211             (*info->print_address_func) (target, info);
12212           }
12213         else
12214           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12215         needcomma = 1;
12216       }
12217
12218   for (i = 0; i < MAX_OPERANDS; i++)
12219     if (op_index[i] != -1 && op_riprel[i])
12220       {
12221         (*info->fprintf_func) (info->stream, "        # ");
12222         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12223                                                 + op_address[op_index[i]]), info);
12224         break;
12225       }
12226   return codep - priv.the_buffer;
12227 }
12228
12229 static const char *float_mem[] = {
12230   /* d8 */
12231   "fadd{s|}",
12232   "fmul{s|}",
12233   "fcom{s|}",
12234   "fcomp{s|}",
12235   "fsub{s|}",
12236   "fsubr{s|}",
12237   "fdiv{s|}",
12238   "fdivr{s|}",
12239   /* d9 */
12240   "fld{s|}",
12241   "(bad)",
12242   "fst{s|}",
12243   "fstp{s|}",
12244   "fldenv{C|C}",
12245   "fldcw",
12246   "fNstenv{C|C}",
12247   "fNstcw",
12248   /* da */
12249   "fiadd{l|}",
12250   "fimul{l|}",
12251   "ficom{l|}",
12252   "ficomp{l|}",
12253   "fisub{l|}",
12254   "fisubr{l|}",
12255   "fidiv{l|}",
12256   "fidivr{l|}",
12257   /* db */
12258   "fild{l|}",
12259   "fisttp{l|}",
12260   "fist{l|}",
12261   "fistp{l|}",
12262   "(bad)",
12263   "fld{t|}",
12264   "(bad)",
12265   "fstp{t|}",
12266   /* dc */
12267   "fadd{l|}",
12268   "fmul{l|}",
12269   "fcom{l|}",
12270   "fcomp{l|}",
12271   "fsub{l|}",
12272   "fsubr{l|}",
12273   "fdiv{l|}",
12274   "fdivr{l|}",
12275   /* dd */
12276   "fld{l|}",
12277   "fisttp{ll|}",
12278   "fst{l||}",
12279   "fstp{l|}",
12280   "frstor{C|C}",
12281   "(bad)",
12282   "fNsave{C|C}",
12283   "fNstsw",
12284   /* de */
12285   "fiadd{s|}",
12286   "fimul{s|}",
12287   "ficom{s|}",
12288   "ficomp{s|}",
12289   "fisub{s|}",
12290   "fisubr{s|}",
12291   "fidiv{s|}",
12292   "fidivr{s|}",
12293   /* df */
12294   "fild{s|}",
12295   "fisttp{s|}",
12296   "fist{s|}",
12297   "fistp{s|}",
12298   "fbld",
12299   "fild{ll|}",
12300   "fbstp",
12301   "fistp{ll|}",
12302 };
12303
12304 static const unsigned char float_mem_mode[] = {
12305   /* d8 */
12306   d_mode,
12307   d_mode,
12308   d_mode,
12309   d_mode,
12310   d_mode,
12311   d_mode,
12312   d_mode,
12313   d_mode,
12314   /* d9 */
12315   d_mode,
12316   0,
12317   d_mode,
12318   d_mode,
12319   0,
12320   w_mode,
12321   0,
12322   w_mode,
12323   /* da */
12324   d_mode,
12325   d_mode,
12326   d_mode,
12327   d_mode,
12328   d_mode,
12329   d_mode,
12330   d_mode,
12331   d_mode,
12332   /* db */
12333   d_mode,
12334   d_mode,
12335   d_mode,
12336   d_mode,
12337   0,
12338   t_mode,
12339   0,
12340   t_mode,
12341   /* dc */
12342   q_mode,
12343   q_mode,
12344   q_mode,
12345   q_mode,
12346   q_mode,
12347   q_mode,
12348   q_mode,
12349   q_mode,
12350   /* dd */
12351   q_mode,
12352   q_mode,
12353   q_mode,
12354   q_mode,
12355   0,
12356   0,
12357   0,
12358   w_mode,
12359   /* de */
12360   w_mode,
12361   w_mode,
12362   w_mode,
12363   w_mode,
12364   w_mode,
12365   w_mode,
12366   w_mode,
12367   w_mode,
12368   /* df */
12369   w_mode,
12370   w_mode,
12371   w_mode,
12372   w_mode,
12373   t_mode,
12374   q_mode,
12375   t_mode,
12376   q_mode
12377 };
12378
12379 #define ST { OP_ST, 0 }
12380 #define STi { OP_STi, 0 }
12381
12382 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12383 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12384 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12385 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12386 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12387 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12388 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12389 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12390 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12391
12392 static const struct dis386 float_reg[][8] = {
12393   /* d8 */
12394   {
12395     { "fadd",   { ST, STi }, 0 },
12396     { "fmul",   { ST, STi }, 0 },
12397     { "fcom",   { STi }, 0 },
12398     { "fcomp",  { STi }, 0 },
12399     { "fsub",   { ST, STi }, 0 },
12400     { "fsubr",  { ST, STi }, 0 },
12401     { "fdiv",   { ST, STi }, 0 },
12402     { "fdivr",  { ST, STi }, 0 },
12403   },
12404   /* d9 */
12405   {
12406     { "fld",    { STi }, 0 },
12407     { "fxch",   { STi }, 0 },
12408     { FGRPd9_2 },
12409     { Bad_Opcode },
12410     { FGRPd9_4 },
12411     { FGRPd9_5 },
12412     { FGRPd9_6 },
12413     { FGRPd9_7 },
12414   },
12415   /* da */
12416   {
12417     { "fcmovb", { ST, STi }, 0 },
12418     { "fcmove", { ST, STi }, 0 },
12419     { "fcmovbe",{ ST, STi }, 0 },
12420     { "fcmovu", { ST, STi }, 0 },
12421     { Bad_Opcode },
12422     { FGRPda_5 },
12423     { Bad_Opcode },
12424     { Bad_Opcode },
12425   },
12426   /* db */
12427   {
12428     { "fcmovnb",{ ST, STi }, 0 },
12429     { "fcmovne",{ ST, STi }, 0 },
12430     { "fcmovnbe",{ ST, STi }, 0 },
12431     { "fcmovnu",{ ST, STi }, 0 },
12432     { FGRPdb_4 },
12433     { "fucomi", { ST, STi }, 0 },
12434     { "fcomi",  { ST, STi }, 0 },
12435     { Bad_Opcode },
12436   },
12437   /* dc */
12438   {
12439     { "fadd",   { STi, ST }, 0 },
12440     { "fmul",   { STi, ST }, 0 },
12441     { Bad_Opcode },
12442     { Bad_Opcode },
12443     { "fsub{!M|r}",     { STi, ST }, 0 },
12444     { "fsub{M|}",       { STi, ST }, 0 },
12445     { "fdiv{!M|r}",     { STi, ST }, 0 },
12446     { "fdiv{M|}",       { STi, ST }, 0 },
12447   },
12448   /* dd */
12449   {
12450     { "ffree",  { STi }, 0 },
12451     { Bad_Opcode },
12452     { "fst",    { STi }, 0 },
12453     { "fstp",   { STi }, 0 },
12454     { "fucom",  { STi }, 0 },
12455     { "fucomp", { STi }, 0 },
12456     { Bad_Opcode },
12457     { Bad_Opcode },
12458   },
12459   /* de */
12460   {
12461     { "faddp",  { STi, ST }, 0 },
12462     { "fmulp",  { STi, ST }, 0 },
12463     { Bad_Opcode },
12464     { FGRPde_3 },
12465     { "fsub{!M|r}p",    { STi, ST }, 0 },
12466     { "fsub{M|}p",      { STi, ST }, 0 },
12467     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12468     { "fdiv{M|}p",      { STi, ST }, 0 },
12469   },
12470   /* df */
12471   {
12472     { "ffreep", { STi }, 0 },
12473     { Bad_Opcode },
12474     { Bad_Opcode },
12475     { Bad_Opcode },
12476     { FGRPdf_4 },
12477     { "fucomip", { ST, STi }, 0 },
12478     { "fcomip", { ST, STi }, 0 },
12479     { Bad_Opcode },
12480   },
12481 };
12482
12483 static char *fgrps[][8] = {
12484   /* Bad opcode 0 */
12485   {
12486     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12487   },
12488
12489   /* d9_2  1 */
12490   {
12491     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12492   },
12493
12494   /* d9_4  2 */
12495   {
12496     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12497   },
12498
12499   /* d9_5  3 */
12500   {
12501     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12502   },
12503
12504   /* d9_6  4 */
12505   {
12506     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12507   },
12508
12509   /* d9_7  5 */
12510   {
12511     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12512   },
12513
12514   /* da_5  6 */
12515   {
12516     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12517   },
12518
12519   /* db_4  7 */
12520   {
12521     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12522     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12523   },
12524
12525   /* de_3  8 */
12526   {
12527     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12528   },
12529
12530   /* df_4  9 */
12531   {
12532     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12533   },
12534 };
12535
12536 static void
12537 swap_operand (void)
12538 {
12539   mnemonicendp[0] = '.';
12540   mnemonicendp[1] = 's';
12541   mnemonicendp += 2;
12542 }
12543
12544 static void
12545 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12546                int sizeflag ATTRIBUTE_UNUSED)
12547 {
12548   /* Skip mod/rm byte.  */
12549   MODRM_CHECK;
12550   codep++;
12551 }
12552
12553 static void
12554 dofloat (int sizeflag)
12555 {
12556   const struct dis386 *dp;
12557   unsigned char floatop;
12558
12559   floatop = codep[-1];
12560
12561   if (modrm.mod != 3)
12562     {
12563       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12564
12565       putop (float_mem[fp_indx], sizeflag);
12566       obufp = op_out[0];
12567       op_ad = 2;
12568       OP_E (float_mem_mode[fp_indx], sizeflag);
12569       return;
12570     }
12571   /* Skip mod/rm byte.  */
12572   MODRM_CHECK;
12573   codep++;
12574
12575   dp = &float_reg[floatop - 0xd8][modrm.reg];
12576   if (dp->name == NULL)
12577     {
12578       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12579
12580       /* Instruction fnstsw is only one with strange arg.  */
12581       if (floatop == 0xdf && codep[-1] == 0xe0)
12582         strcpy (op_out[0], names16[0]);
12583     }
12584   else
12585     {
12586       putop (dp->name, sizeflag);
12587
12588       obufp = op_out[0];
12589       op_ad = 2;
12590       if (dp->op[0].rtn)
12591         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12592
12593       obufp = op_out[1];
12594       op_ad = 1;
12595       if (dp->op[1].rtn)
12596         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12597     }
12598 }
12599
12600 /* Like oappend (below), but S is a string starting with '%'.
12601    In Intel syntax, the '%' is elided.  */
12602 static void
12603 oappend_maybe_intel (const char *s)
12604 {
12605   oappend (s + intel_syntax);
12606 }
12607
12608 static void
12609 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12610 {
12611   oappend_maybe_intel ("%st");
12612 }
12613
12614 static void
12615 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12616 {
12617   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12618   oappend_maybe_intel (scratchbuf);
12619 }
12620
12621 /* Capital letters in template are macros.  */
12622 static int
12623 putop (const char *in_template, int sizeflag)
12624 {
12625   const char *p;
12626   int alt = 0;
12627   int cond = 1;
12628   unsigned int l = 0, len = 0;
12629   char last[4];
12630
12631   for (p = in_template; *p; p++)
12632     {
12633       if (len > l)
12634         {
12635           if (l >= sizeof (last) || !ISUPPER (*p))
12636             abort ();
12637           last[l++] = *p;
12638           continue;
12639         }
12640       switch (*p)
12641         {
12642         default:
12643           *obufp++ = *p;
12644           break;
12645         case '%':
12646           len++;
12647           break;
12648         case '!':
12649           cond = 0;
12650           break;
12651         case '{':
12652           if (intel_syntax)
12653             {
12654               while (*++p != '|')
12655                 if (*p == '}' || *p == '\0')
12656                   abort ();
12657               alt = 1;
12658             }
12659           break;
12660         case '|':
12661           while (*++p != '}')
12662             {
12663               if (*p == '\0')
12664                 abort ();
12665             }
12666           break;
12667         case '}':
12668           alt = 0;
12669           break;
12670         case 'A':
12671           if (intel_syntax)
12672             break;
12673           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12674             *obufp++ = 'b';
12675           break;
12676         case 'B':
12677           if (l == 0)
12678             {
12679             case_B:
12680               if (intel_syntax)
12681                 break;
12682               if (sizeflag & SUFFIX_ALWAYS)
12683                 *obufp++ = 'b';
12684             }
12685           else if (l == 1 && last[0] == 'L')
12686             {
12687               if (address_mode == mode_64bit
12688                   && !(prefixes & PREFIX_ADDR))
12689                 {
12690                   *obufp++ = 'a';
12691                   *obufp++ = 'b';
12692                   *obufp++ = 's';
12693                 }
12694
12695               goto case_B;
12696             }
12697           else
12698             abort ();
12699           break;
12700         case 'C':
12701           if (intel_syntax && !alt)
12702             break;
12703           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12704             {
12705               if (sizeflag & DFLAG)
12706                 *obufp++ = intel_syntax ? 'd' : 'l';
12707               else
12708                 *obufp++ = intel_syntax ? 'w' : 's';
12709               used_prefixes |= (prefixes & PREFIX_DATA);
12710             }
12711           break;
12712         case 'D':
12713           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12714             break;
12715           USED_REX (REX_W);
12716           if (modrm.mod == 3)
12717             {
12718               if (rex & REX_W)
12719                 *obufp++ = 'q';
12720               else
12721                 {
12722                   if (sizeflag & DFLAG)
12723                     *obufp++ = intel_syntax ? 'd' : 'l';
12724                   else
12725                     *obufp++ = 'w';
12726                   used_prefixes |= (prefixes & PREFIX_DATA);
12727                 }
12728             }
12729           else
12730             *obufp++ = 'w';
12731           break;
12732         case 'E':               /* For jcxz/jecxz */
12733           if (address_mode == mode_64bit)
12734             {
12735               if (sizeflag & AFLAG)
12736                 *obufp++ = 'r';
12737               else
12738                 *obufp++ = 'e';
12739             }
12740           else
12741             if (sizeflag & AFLAG)
12742               *obufp++ = 'e';
12743           used_prefixes |= (prefixes & PREFIX_ADDR);
12744           break;
12745         case 'F':
12746           if (intel_syntax)
12747             break;
12748           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12749             {
12750               if (sizeflag & AFLAG)
12751                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12752               else
12753                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12754               used_prefixes |= (prefixes & PREFIX_ADDR);
12755             }
12756           break;
12757         case 'G':
12758           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12759             break;
12760           if ((rex & REX_W) || (sizeflag & DFLAG))
12761             *obufp++ = 'l';
12762           else
12763             *obufp++ = 'w';
12764           if (!(rex & REX_W))
12765             used_prefixes |= (prefixes & PREFIX_DATA);
12766           break;
12767         case 'H':
12768           if (intel_syntax)
12769             break;
12770           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12771               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12772             {
12773               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12774               *obufp++ = ',';
12775               *obufp++ = 'p';
12776               if (prefixes & PREFIX_DS)
12777                 *obufp++ = 't';
12778               else
12779                 *obufp++ = 'n';
12780             }
12781           break;
12782         case 'K':
12783           USED_REX (REX_W);
12784           if (rex & REX_W)
12785             *obufp++ = 'q';
12786           else
12787             *obufp++ = 'd';
12788           break;
12789         case 'Z':
12790           if (l != 0)
12791             {
12792               if (l != 1 || last[0] != 'X')
12793                 abort ();
12794               if (!need_vex || !vex.evex)
12795                 abort ();
12796               if (intel_syntax
12797                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12798                 break;
12799               switch (vex.length)
12800                 {
12801                 case 128:
12802                   *obufp++ = 'x';
12803                   break;
12804                 case 256:
12805                   *obufp++ = 'y';
12806                   break;
12807                 case 512:
12808                   *obufp++ = 'z';
12809                   break;
12810                 default:
12811                   abort ();
12812                 }
12813               break;
12814             }
12815           if (intel_syntax)
12816             break;
12817           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12818             {
12819               *obufp++ = 'q';
12820               break;
12821             }
12822           /* Fall through.  */
12823           goto case_L;
12824         case 'L':
12825           if (l != 0)
12826             abort ();
12827         case_L:
12828           if (intel_syntax)
12829             break;
12830           if (sizeflag & SUFFIX_ALWAYS)
12831             *obufp++ = 'l';
12832           break;
12833         case 'M':
12834           if (intel_mnemonic != cond)
12835             *obufp++ = 'r';
12836           break;
12837         case 'N':
12838           if ((prefixes & PREFIX_FWAIT) == 0)
12839             *obufp++ = 'n';
12840           else
12841             used_prefixes |= PREFIX_FWAIT;
12842           break;
12843         case 'O':
12844           USED_REX (REX_W);
12845           if (rex & REX_W)
12846             *obufp++ = 'o';
12847           else if (intel_syntax && (sizeflag & DFLAG))
12848             *obufp++ = 'q';
12849           else
12850             *obufp++ = 'd';
12851           if (!(rex & REX_W))
12852             used_prefixes |= (prefixes & PREFIX_DATA);
12853           break;
12854         case '&':
12855           if (!intel_syntax
12856               && address_mode == mode_64bit
12857               && isa64 == intel64)
12858             {
12859               *obufp++ = 'q';
12860               break;
12861             }
12862           /* Fall through.  */
12863         case 'T':
12864           if (!intel_syntax
12865               && address_mode == mode_64bit
12866               && ((sizeflag & DFLAG) || (rex & REX_W)))
12867             {
12868               *obufp++ = 'q';
12869               break;
12870             }
12871           /* Fall through.  */
12872           goto case_P;
12873         case 'P':
12874           if (l == 0)
12875             {
12876             case_P:
12877               if (intel_syntax)
12878                 {
12879                   if ((rex & REX_W) == 0
12880                       && (prefixes & PREFIX_DATA))
12881                     {
12882                       if ((sizeflag & DFLAG) == 0)
12883                         *obufp++ = 'w';
12884                       used_prefixes |= (prefixes & PREFIX_DATA);
12885                     }
12886                   break;
12887                 }
12888               if ((prefixes & PREFIX_DATA)
12889                   || (rex & REX_W)
12890                   || (sizeflag & SUFFIX_ALWAYS))
12891                 {
12892                   USED_REX (REX_W);
12893                   if (rex & REX_W)
12894                     *obufp++ = 'q';
12895                   else
12896                     {
12897                       if (sizeflag & DFLAG)
12898                         *obufp++ = 'l';
12899                       else
12900                         *obufp++ = 'w';
12901                       used_prefixes |= (prefixes & PREFIX_DATA);
12902                     }
12903                 }
12904             }
12905           else if (l == 1 && last[0] == 'L')
12906             {
12907               if ((prefixes & PREFIX_DATA)
12908                   || (rex & REX_W)
12909                   || (sizeflag & SUFFIX_ALWAYS))
12910                 {
12911                   USED_REX (REX_W);
12912                   if (rex & REX_W)
12913                     *obufp++ = 'q';
12914                   else
12915                     {
12916                       if (sizeflag & DFLAG)
12917                         *obufp++ = intel_syntax ? 'd' : 'l';
12918                       else
12919                         *obufp++ = 'w';
12920                       used_prefixes |= (prefixes & PREFIX_DATA);
12921                     }
12922                 }
12923             }
12924           else
12925             abort ();
12926           break;
12927         case 'U':
12928           if (intel_syntax)
12929             break;
12930           if (address_mode == mode_64bit
12931               && ((sizeflag & DFLAG) || (rex & REX_W)))
12932             {
12933               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12934                 *obufp++ = 'q';
12935               break;
12936             }
12937           /* Fall through.  */
12938           goto case_Q;
12939         case 'Q':
12940           if (l == 0)
12941             {
12942             case_Q:
12943               if (intel_syntax && !alt)
12944                 break;
12945               USED_REX (REX_W);
12946               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12947                 {
12948                   if (rex & REX_W)
12949                     *obufp++ = 'q';
12950                   else
12951                     {
12952                       if (sizeflag & DFLAG)
12953                         *obufp++ = intel_syntax ? 'd' : 'l';
12954                       else
12955                         *obufp++ = 'w';
12956                       used_prefixes |= (prefixes & PREFIX_DATA);
12957                     }
12958                 }
12959             }
12960           else if (l == 1 && last[0] == 'L')
12961             {
12962               if ((intel_syntax && need_modrm)
12963                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12964                 break;
12965               if ((rex & REX_W))
12966                 {
12967                   USED_REX (REX_W);
12968                   *obufp++ = 'q';
12969                 }
12970               else if((address_mode == mode_64bit && need_modrm)
12971                       || (sizeflag & SUFFIX_ALWAYS))
12972                 *obufp++ = intel_syntax? 'd' : 'l';
12973             }
12974           else
12975             abort ();
12976           break;
12977         case 'R':
12978           USED_REX (REX_W);
12979           if (rex & REX_W)
12980             *obufp++ = 'q';
12981           else if (sizeflag & DFLAG)
12982             {
12983               if (intel_syntax)
12984                   *obufp++ = 'd';
12985               else
12986                   *obufp++ = 'l';
12987             }
12988           else
12989             *obufp++ = 'w';
12990           if (intel_syntax && !p[1]
12991               && ((rex & REX_W) || (sizeflag & DFLAG)))
12992             *obufp++ = 'e';
12993           if (!(rex & REX_W))
12994             used_prefixes |= (prefixes & PREFIX_DATA);
12995           break;
12996         case 'V':
12997           if (l == 0)
12998             {
12999               if (intel_syntax)
13000                 break;
13001               if (address_mode == mode_64bit
13002                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13003                 {
13004                   if (sizeflag & SUFFIX_ALWAYS)
13005                     *obufp++ = 'q';
13006                   break;
13007                 }
13008             }
13009           else if (l == 1 && last[0] == 'L')
13010             {
13011               if (rex & REX_W)
13012                 {
13013                   *obufp++ = 'a';
13014                   *obufp++ = 'b';
13015                   *obufp++ = 's';
13016                 }
13017             }
13018           else
13019             abort ();
13020           /* Fall through.  */
13021           goto case_S;
13022         case 'S':
13023           if (l == 0)
13024             {
13025             case_S:
13026               if (intel_syntax)
13027                 break;
13028               if (sizeflag & SUFFIX_ALWAYS)
13029                 {
13030                   if (rex & REX_W)
13031                     *obufp++ = 'q';
13032                   else
13033                     {
13034                       if (sizeflag & DFLAG)
13035                         *obufp++ = 'l';
13036                       else
13037                         *obufp++ = 'w';
13038                       used_prefixes |= (prefixes & PREFIX_DATA);
13039                     }
13040                 }
13041             }
13042           else if (l == 1 && last[0] == 'L')
13043             {
13044               if (address_mode == mode_64bit
13045                   && !(prefixes & PREFIX_ADDR))
13046                 {
13047                   *obufp++ = 'a';
13048                   *obufp++ = 'b';
13049                   *obufp++ = 's';
13050                 }
13051
13052               goto case_S;
13053             }
13054           else
13055             abort ();
13056           break;
13057         case 'X':
13058           if (l != 0)
13059             abort ();
13060           if (need_vex
13061               ? vex.prefix == DATA_PREFIX_OPCODE
13062               : prefixes & PREFIX_DATA)
13063             {
13064               *obufp++ = 'd';
13065               used_prefixes |= PREFIX_DATA;
13066             }
13067           else
13068             *obufp++ = 's';
13069           break;
13070         case 'Y':
13071           if (l == 1 && last[0] == 'X')
13072             {
13073               if (!need_vex)
13074                 abort ();
13075               if (intel_syntax
13076                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13077                 break;
13078               switch (vex.length)
13079                 {
13080                 case 128:
13081                   *obufp++ = 'x';
13082                   break;
13083                 case 256:
13084                   *obufp++ = 'y';
13085                   break;
13086                 case 512:
13087                   if (!vex.evex)
13088                 default:
13089                     abort ();
13090                 }
13091             }
13092           else
13093             abort ();
13094           break;
13095         case 'W':
13096           if (l == 0)
13097             {
13098               /* operand size flag for cwtl, cbtw */
13099               USED_REX (REX_W);
13100               if (rex & REX_W)
13101                 {
13102                   if (intel_syntax)
13103                     *obufp++ = 'd';
13104                   else
13105                     *obufp++ = 'l';
13106                 }
13107               else if (sizeflag & DFLAG)
13108                 *obufp++ = 'w';
13109               else
13110                 *obufp++ = 'b';
13111               if (!(rex & REX_W))
13112                 used_prefixes |= (prefixes & PREFIX_DATA);
13113             }
13114           else if (l == 1)
13115             {
13116               if (!need_vex)
13117                 abort ();
13118               if (last[0] == 'X')
13119                 *obufp++ = vex.w ? 'd': 's';
13120               else if (last[0] == 'L')
13121                 *obufp++ = vex.w ? 'q': 'd';
13122               else if (last[0] == 'B')
13123                 *obufp++ = vex.w ? 'w': 'b';
13124               else
13125                 abort ();
13126             }
13127           else
13128             abort ();
13129           break;
13130         case '^':
13131           if (intel_syntax)
13132             break;
13133           if (isa64 == intel64 && (rex & REX_W))
13134             {
13135               USED_REX (REX_W);
13136               *obufp++ = 'q';
13137               break;
13138             }
13139           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13140             {
13141               if (sizeflag & DFLAG)
13142                 *obufp++ = 'l';
13143               else
13144                 *obufp++ = 'w';
13145               used_prefixes |= (prefixes & PREFIX_DATA);
13146             }
13147           break;
13148         case '@':
13149           if (intel_syntax)
13150             break;
13151           if (address_mode == mode_64bit
13152               && (isa64 == intel64
13153                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13154               *obufp++ = 'q';
13155           else if ((prefixes & PREFIX_DATA))
13156             {
13157               if (!(sizeflag & DFLAG))
13158                 *obufp++ = 'w';
13159               used_prefixes |= (prefixes & PREFIX_DATA);
13160             }
13161           break;
13162         }
13163
13164       if (len == l)
13165         len = l = 0;
13166     }
13167   *obufp = 0;
13168   mnemonicendp = obufp;
13169   return 0;
13170 }
13171
13172 static void
13173 oappend (const char *s)
13174 {
13175   obufp = stpcpy (obufp, s);
13176 }
13177
13178 static void
13179 append_seg (void)
13180 {
13181   /* Only print the active segment register.  */
13182   if (!active_seg_prefix)
13183     return;
13184
13185   used_prefixes |= active_seg_prefix;
13186   switch (active_seg_prefix)
13187     {
13188     case PREFIX_CS:
13189       oappend_maybe_intel ("%cs:");
13190       break;
13191     case PREFIX_DS:
13192       oappend_maybe_intel ("%ds:");
13193       break;
13194     case PREFIX_SS:
13195       oappend_maybe_intel ("%ss:");
13196       break;
13197     case PREFIX_ES:
13198       oappend_maybe_intel ("%es:");
13199       break;
13200     case PREFIX_FS:
13201       oappend_maybe_intel ("%fs:");
13202       break;
13203     case PREFIX_GS:
13204       oappend_maybe_intel ("%gs:");
13205       break;
13206     default:
13207       break;
13208     }
13209 }
13210
13211 static void
13212 OP_indirE (int bytemode, int sizeflag)
13213 {
13214   if (!intel_syntax)
13215     oappend ("*");
13216   OP_E (bytemode, sizeflag);
13217 }
13218
13219 static void
13220 print_operand_value (char *buf, int hex, bfd_vma disp)
13221 {
13222   if (address_mode == mode_64bit)
13223     {
13224       if (hex)
13225         {
13226           char tmp[30];
13227           int i;
13228           buf[0] = '0';
13229           buf[1] = 'x';
13230           sprintf_vma (tmp, disp);
13231           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13232           strcpy (buf + 2, tmp + i);
13233         }
13234       else
13235         {
13236           bfd_signed_vma v = disp;
13237           char tmp[30];
13238           int i;
13239           if (v < 0)
13240             {
13241               *(buf++) = '-';
13242               v = -disp;
13243               /* Check for possible overflow on 0x8000000000000000.  */
13244               if (v < 0)
13245                 {
13246                   strcpy (buf, "9223372036854775808");
13247                   return;
13248                 }
13249             }
13250           if (!v)
13251             {
13252               strcpy (buf, "0");
13253               return;
13254             }
13255
13256           i = 0;
13257           tmp[29] = 0;
13258           while (v)
13259             {
13260               tmp[28 - i] = (v % 10) + '0';
13261               v /= 10;
13262               i++;
13263             }
13264           strcpy (buf, tmp + 29 - i);
13265         }
13266     }
13267   else
13268     {
13269       if (hex)
13270         sprintf (buf, "0x%x", (unsigned int) disp);
13271       else
13272         sprintf (buf, "%d", (int) disp);
13273     }
13274 }
13275
13276 /* Put DISP in BUF as signed hex number.  */
13277
13278 static void
13279 print_displacement (char *buf, bfd_vma disp)
13280 {
13281   bfd_signed_vma val = disp;
13282   char tmp[30];
13283   int i, j = 0;
13284
13285   if (val < 0)
13286     {
13287       buf[j++] = '-';
13288       val = -disp;
13289
13290       /* Check for possible overflow.  */
13291       if (val < 0)
13292         {
13293           switch (address_mode)
13294             {
13295             case mode_64bit:
13296               strcpy (buf + j, "0x8000000000000000");
13297               break;
13298             case mode_32bit:
13299               strcpy (buf + j, "0x80000000");
13300               break;
13301             case mode_16bit:
13302               strcpy (buf + j, "0x8000");
13303               break;
13304             }
13305           return;
13306         }
13307     }
13308
13309   buf[j++] = '0';
13310   buf[j++] = 'x';
13311
13312   sprintf_vma (tmp, (bfd_vma) val);
13313   for (i = 0; tmp[i] == '0'; i++)
13314     continue;
13315   if (tmp[i] == '\0')
13316     i--;
13317   strcpy (buf + j, tmp + i);
13318 }
13319
13320 static void
13321 intel_operand_size (int bytemode, int sizeflag)
13322 {
13323   if (vex.evex
13324       && vex.b
13325       && (bytemode == x_mode
13326           || bytemode == evex_half_bcst_xmmq_mode))
13327     {
13328       if (vex.w)
13329         oappend ("QWORD PTR ");
13330       else
13331         oappend ("DWORD PTR ");
13332       return;
13333     }
13334   switch (bytemode)
13335     {
13336     case b_mode:
13337     case b_swap_mode:
13338     case dqb_mode:
13339     case db_mode:
13340       oappend ("BYTE PTR ");
13341       break;
13342     case w_mode:
13343     case dw_mode:
13344     case dqw_mode:
13345       oappend ("WORD PTR ");
13346       break;
13347     case indir_v_mode:
13348       if (address_mode == mode_64bit && isa64 == intel64)
13349         {
13350           oappend ("QWORD PTR ");
13351           break;
13352         }
13353       /* Fall through.  */
13354     case stack_v_mode:
13355       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13356         {
13357           oappend ("QWORD PTR ");
13358           break;
13359         }
13360       /* Fall through.  */
13361     case v_mode:
13362     case v_swap_mode:
13363     case dq_mode:
13364       USED_REX (REX_W);
13365       if (rex & REX_W)
13366         oappend ("QWORD PTR ");
13367       else
13368         {
13369           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13370             oappend ("DWORD PTR ");
13371           else
13372             oappend ("WORD PTR ");
13373           used_prefixes |= (prefixes & PREFIX_DATA);
13374         }
13375       break;
13376     case z_mode:
13377       if ((rex & REX_W) || (sizeflag & DFLAG))
13378         *obufp++ = 'D';
13379       oappend ("WORD PTR ");
13380       if (!(rex & REX_W))
13381         used_prefixes |= (prefixes & PREFIX_DATA);
13382       break;
13383     case a_mode:
13384       if (sizeflag & DFLAG)
13385         oappend ("QWORD PTR ");
13386       else
13387         oappend ("DWORD PTR ");
13388       used_prefixes |= (prefixes & PREFIX_DATA);
13389       break;
13390     case movsxd_mode:
13391       if (!(sizeflag & DFLAG) && isa64 == intel64)
13392         oappend ("WORD PTR ");
13393       else
13394         oappend ("DWORD PTR ");
13395       used_prefixes |= (prefixes & PREFIX_DATA);
13396       break;
13397     case d_mode:
13398     case d_scalar_swap_mode:
13399     case d_swap_mode:
13400     case dqd_mode:
13401       oappend ("DWORD PTR ");
13402       break;
13403     case q_mode:
13404     case q_scalar_swap_mode:
13405     case q_swap_mode:
13406       oappend ("QWORD PTR ");
13407       break;
13408     case m_mode:
13409       if (address_mode == mode_64bit)
13410         oappend ("QWORD PTR ");
13411       else
13412         oappend ("DWORD PTR ");
13413       break;
13414     case f_mode:
13415       if (sizeflag & DFLAG)
13416         oappend ("FWORD PTR ");
13417       else
13418         oappend ("DWORD PTR ");
13419       used_prefixes |= (prefixes & PREFIX_DATA);
13420       break;
13421     case t_mode:
13422       oappend ("TBYTE PTR ");
13423       break;
13424     case x_mode:
13425     case x_swap_mode:
13426     case evex_x_gscat_mode:
13427     case evex_x_nobcst_mode:
13428     case b_scalar_mode:
13429     case w_scalar_mode:
13430       if (need_vex)
13431         {
13432           switch (vex.length)
13433             {
13434             case 128:
13435               oappend ("XMMWORD PTR ");
13436               break;
13437             case 256:
13438               oappend ("YMMWORD PTR ");
13439               break;
13440             case 512:
13441               oappend ("ZMMWORD PTR ");
13442               break;
13443             default:
13444               abort ();
13445             }
13446         }
13447       else
13448         oappend ("XMMWORD PTR ");
13449       break;
13450     case xmm_mode:
13451       oappend ("XMMWORD PTR ");
13452       break;
13453     case ymm_mode:
13454       oappend ("YMMWORD PTR ");
13455       break;
13456     case xmmq_mode:
13457     case evex_half_bcst_xmmq_mode:
13458       if (!need_vex)
13459         abort ();
13460
13461       switch (vex.length)
13462         {
13463         case 128:
13464           oappend ("QWORD PTR ");
13465           break;
13466         case 256:
13467           oappend ("XMMWORD PTR ");
13468           break;
13469         case 512:
13470           oappend ("YMMWORD PTR ");
13471           break;
13472         default:
13473           abort ();
13474         }
13475       break;
13476     case xmm_mb_mode:
13477       if (!need_vex)
13478         abort ();
13479
13480       switch (vex.length)
13481         {
13482         case 128:
13483         case 256:
13484         case 512:
13485           oappend ("BYTE PTR ");
13486           break;
13487         default:
13488           abort ();
13489         }
13490       break;
13491     case xmm_mw_mode:
13492       if (!need_vex)
13493         abort ();
13494
13495       switch (vex.length)
13496         {
13497         case 128:
13498         case 256:
13499         case 512:
13500           oappend ("WORD PTR ");
13501           break;
13502         default:
13503           abort ();
13504         }
13505       break;
13506     case xmm_md_mode:
13507       if (!need_vex)
13508         abort ();
13509
13510       switch (vex.length)
13511         {
13512         case 128:
13513         case 256:
13514         case 512:
13515           oappend ("DWORD PTR ");
13516           break;
13517         default:
13518           abort ();
13519         }
13520       break;
13521     case xmm_mq_mode:
13522       if (!need_vex)
13523         abort ();
13524
13525       switch (vex.length)
13526         {
13527         case 128:
13528         case 256:
13529         case 512:
13530           oappend ("QWORD PTR ");
13531           break;
13532         default:
13533           abort ();
13534         }
13535       break;
13536     case xmmdw_mode:
13537       if (!need_vex)
13538         abort ();
13539
13540       switch (vex.length)
13541         {
13542         case 128:
13543           oappend ("WORD PTR ");
13544           break;
13545         case 256:
13546           oappend ("DWORD PTR ");
13547           break;
13548         case 512:
13549           oappend ("QWORD PTR ");
13550           break;
13551         default:
13552           abort ();
13553         }
13554       break;
13555     case xmmqd_mode:
13556       if (!need_vex)
13557         abort ();
13558
13559       switch (vex.length)
13560         {
13561         case 128:
13562           oappend ("DWORD PTR ");
13563           break;
13564         case 256:
13565           oappend ("QWORD PTR ");
13566           break;
13567         case 512:
13568           oappend ("XMMWORD PTR ");
13569           break;
13570         default:
13571           abort ();
13572         }
13573       break;
13574     case ymmq_mode:
13575       if (!need_vex)
13576         abort ();
13577
13578       switch (vex.length)
13579         {
13580         case 128:
13581           oappend ("QWORD PTR ");
13582           break;
13583         case 256:
13584           oappend ("YMMWORD PTR ");
13585           break;
13586         case 512:
13587           oappend ("ZMMWORD PTR ");
13588           break;
13589         default:
13590           abort ();
13591         }
13592       break;
13593     case ymmxmm_mode:
13594       if (!need_vex)
13595         abort ();
13596
13597       switch (vex.length)
13598         {
13599         case 128:
13600         case 256:
13601           oappend ("XMMWORD PTR ");
13602           break;
13603         default:
13604           abort ();
13605         }
13606       break;
13607     case o_mode:
13608       oappend ("OWORD PTR ");
13609       break;
13610     case vex_scalar_w_dq_mode:
13611       if (!need_vex)
13612         abort ();
13613
13614       if (vex.w)
13615         oappend ("QWORD PTR ");
13616       else
13617         oappend ("DWORD PTR ");
13618       break;
13619     case vex_vsib_d_w_dq_mode:
13620     case vex_vsib_q_w_dq_mode:
13621       if (!need_vex)
13622         abort ();
13623
13624       if (!vex.evex)
13625         {
13626           if (vex.w)
13627             oappend ("QWORD PTR ");
13628           else
13629             oappend ("DWORD PTR ");
13630         }
13631       else
13632         {
13633           switch (vex.length)
13634             {
13635             case 128:
13636               oappend ("XMMWORD PTR ");
13637               break;
13638             case 256:
13639               oappend ("YMMWORD PTR ");
13640               break;
13641             case 512:
13642               oappend ("ZMMWORD PTR ");
13643               break;
13644             default:
13645               abort ();
13646             }
13647         }
13648       break;
13649     case vex_vsib_q_w_d_mode:
13650     case vex_vsib_d_w_d_mode:
13651       if (!need_vex || !vex.evex)
13652         abort ();
13653
13654       switch (vex.length)
13655         {
13656         case 128:
13657           oappend ("QWORD PTR ");
13658           break;
13659         case 256:
13660           oappend ("XMMWORD PTR ");
13661           break;
13662         case 512:
13663           oappend ("YMMWORD PTR ");
13664           break;
13665         default:
13666           abort ();
13667         }
13668
13669       break;
13670     case mask_bd_mode:
13671       if (!need_vex || vex.length != 128)
13672         abort ();
13673       if (vex.w)
13674         oappend ("DWORD PTR ");
13675       else
13676         oappend ("BYTE PTR ");
13677       break;
13678     case mask_mode:
13679       if (!need_vex)
13680         abort ();
13681       if (vex.w)
13682         oappend ("QWORD PTR ");
13683       else
13684         oappend ("WORD PTR ");
13685       break;
13686     case v_bnd_mode:
13687     case v_bndmk_mode:
13688     default:
13689       break;
13690     }
13691 }
13692
13693 static void
13694 OP_E_register (int bytemode, int sizeflag)
13695 {
13696   int reg = modrm.rm;
13697   const char **names;
13698
13699   USED_REX (REX_B);
13700   if ((rex & REX_B))
13701     reg += 8;
13702
13703   if ((sizeflag & SUFFIX_ALWAYS)
13704       && (bytemode == b_swap_mode
13705           || bytemode == bnd_swap_mode
13706           || bytemode == v_swap_mode))
13707     swap_operand ();
13708
13709   switch (bytemode)
13710     {
13711     case b_mode:
13712     case b_swap_mode:
13713       USED_REX (0);
13714       if (rex)
13715         names = names8rex;
13716       else
13717         names = names8;
13718       break;
13719     case w_mode:
13720       names = names16;
13721       break;
13722     case d_mode:
13723     case dw_mode:
13724     case db_mode:
13725       names = names32;
13726       break;
13727     case q_mode:
13728       names = names64;
13729       break;
13730     case m_mode:
13731     case v_bnd_mode:
13732       names = address_mode == mode_64bit ? names64 : names32;
13733       break;
13734     case bnd_mode:
13735     case bnd_swap_mode:
13736       if (reg > 0x3)
13737         {
13738           oappend ("(bad)");
13739           return;
13740         }
13741       names = names_bnd;
13742       break;
13743     case indir_v_mode:
13744       if (address_mode == mode_64bit && isa64 == intel64)
13745         {
13746           names = names64;
13747           break;
13748         }
13749       /* Fall through.  */
13750     case stack_v_mode:
13751       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13752         {
13753           names = names64;
13754           break;
13755         }
13756       bytemode = v_mode;
13757       /* Fall through.  */
13758     case v_mode:
13759     case v_swap_mode:
13760     case dq_mode:
13761     case dqb_mode:
13762     case dqd_mode:
13763     case dqw_mode:
13764       USED_REX (REX_W);
13765       if (rex & REX_W)
13766         names = names64;
13767       else
13768         {
13769           if ((sizeflag & DFLAG)
13770               || (bytemode != v_mode
13771                   && bytemode != v_swap_mode))
13772             names = names32;
13773           else
13774             names = names16;
13775           used_prefixes |= (prefixes & PREFIX_DATA);
13776         }
13777       break;
13778     case movsxd_mode:
13779       if (!(sizeflag & DFLAG) && isa64 == intel64)
13780         names = names16;
13781       else
13782         names = names32;
13783       used_prefixes |= (prefixes & PREFIX_DATA);
13784       break;
13785     case va_mode:
13786       names = (address_mode == mode_64bit
13787                ? names64 : names32);
13788       if (!(prefixes & PREFIX_ADDR))
13789         names = (address_mode == mode_16bit
13790                      ? names16 : names);
13791       else
13792         {
13793           /* Remove "addr16/addr32".  */
13794           all_prefixes[last_addr_prefix] = 0;
13795           names = (address_mode != mode_32bit
13796                        ? names32 : names16);
13797           used_prefixes |= PREFIX_ADDR;
13798         }
13799       break;
13800     case mask_bd_mode:
13801     case mask_mode:
13802       if (reg > 0x7)
13803         {
13804           oappend ("(bad)");
13805           return;
13806         }
13807       names = names_mask;
13808       break;
13809     case 0:
13810       return;
13811     default:
13812       oappend (INTERNAL_DISASSEMBLER_ERROR);
13813       return;
13814     }
13815   oappend (names[reg]);
13816 }
13817
13818 static void
13819 OP_E_memory (int bytemode, int sizeflag)
13820 {
13821   bfd_vma disp = 0;
13822   int add = (rex & REX_B) ? 8 : 0;
13823   int riprel = 0;
13824   int shift;
13825
13826   if (vex.evex)
13827     {
13828       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13829       if (vex.b
13830           && bytemode != x_mode
13831           && bytemode != xmmq_mode
13832           && bytemode != evex_half_bcst_xmmq_mode)
13833         {
13834           BadOp ();
13835           return;
13836         }
13837       switch (bytemode)
13838         {
13839         case dqw_mode:
13840         case dw_mode:
13841           shift = 1;
13842           break;
13843         case dqb_mode:
13844         case db_mode:
13845           shift = 0;
13846           break;
13847         case dq_mode:
13848           if (address_mode != mode_64bit)
13849             {
13850               shift = 2;
13851               break;
13852             }
13853             /* fall through */
13854         case vex_scalar_w_dq_mode:
13855         case vex_vsib_d_w_dq_mode:
13856         case vex_vsib_d_w_d_mode:
13857         case vex_vsib_q_w_dq_mode:
13858         case vex_vsib_q_w_d_mode:
13859         case evex_x_gscat_mode:
13860           shift = vex.w ? 3 : 2;
13861           break;
13862         case x_mode:
13863         case evex_half_bcst_xmmq_mode:
13864         case xmmq_mode:
13865           if (vex.b)
13866             {
13867               shift = vex.w ? 3 : 2;
13868               break;
13869             }
13870           /* Fall through.  */
13871         case xmmqd_mode:
13872         case xmmdw_mode:
13873         case ymmq_mode:
13874         case evex_x_nobcst_mode:
13875         case x_swap_mode:
13876           switch (vex.length)
13877             {
13878             case 128:
13879               shift = 4;
13880               break;
13881             case 256:
13882               shift = 5;
13883               break;
13884             case 512:
13885               shift = 6;
13886               break;
13887             default:
13888               abort ();
13889             }
13890           break;
13891         case ymm_mode:
13892           shift = 5;
13893           break;
13894         case xmm_mode:
13895           shift = 4;
13896           break;
13897         case xmm_mq_mode:
13898         case q_mode:
13899         case q_swap_mode:
13900         case q_scalar_swap_mode:
13901           shift = 3;
13902           break;
13903         case dqd_mode:
13904         case xmm_md_mode:
13905         case d_mode:
13906         case d_swap_mode:
13907         case d_scalar_swap_mode:
13908           shift = 2;
13909           break;
13910         case w_scalar_mode:
13911         case xmm_mw_mode:
13912           shift = 1;
13913           break;
13914         case b_scalar_mode:
13915         case xmm_mb_mode:
13916           shift = 0;
13917           break;
13918         default:
13919           abort ();
13920         }
13921       /* Make necessary corrections to shift for modes that need it.
13922          For these modes we currently have shift 4, 5 or 6 depending on
13923          vex.length (it corresponds to xmmword, ymmword or zmmword
13924          operand).  We might want to make it 3, 4 or 5 (e.g. for
13925          xmmq_mode).  In case of broadcast enabled the corrections
13926          aren't needed, as element size is always 32 or 64 bits.  */
13927       if (!vex.b
13928           && (bytemode == xmmq_mode
13929               || bytemode == evex_half_bcst_xmmq_mode))
13930         shift -= 1;
13931       else if (bytemode == xmmqd_mode)
13932         shift -= 2;
13933       else if (bytemode == xmmdw_mode)
13934         shift -= 3;
13935       else if (bytemode == ymmq_mode && vex.length == 128)
13936         shift -= 1;
13937     }
13938   else
13939     shift = 0;
13940
13941   USED_REX (REX_B);
13942   if (intel_syntax)
13943     intel_operand_size (bytemode, sizeflag);
13944   append_seg ();
13945
13946   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13947     {
13948       /* 32/64 bit address mode */
13949       int havedisp;
13950       int havesib;
13951       int havebase;
13952       int haveindex;
13953       int needindex;
13954       int needaddr32;
13955       int base, rbase;
13956       int vindex = 0;
13957       int scale = 0;
13958       int addr32flag = !((sizeflag & AFLAG)
13959                          || bytemode == v_bnd_mode
13960                          || bytemode == v_bndmk_mode
13961                          || bytemode == bnd_mode
13962                          || bytemode == bnd_swap_mode);
13963       const char **indexes64 = names64;
13964       const char **indexes32 = names32;
13965
13966       havesib = 0;
13967       havebase = 1;
13968       haveindex = 0;
13969       base = modrm.rm;
13970
13971       if (base == 4)
13972         {
13973           havesib = 1;
13974           vindex = sib.index;
13975           USED_REX (REX_X);
13976           if (rex & REX_X)
13977             vindex += 8;
13978           switch (bytemode)
13979             {
13980             case vex_vsib_d_w_dq_mode:
13981             case vex_vsib_d_w_d_mode:
13982             case vex_vsib_q_w_dq_mode:
13983             case vex_vsib_q_w_d_mode:
13984               if (!need_vex)
13985                 abort ();
13986               if (vex.evex)
13987                 {
13988                   if (!vex.v)
13989                     vindex += 16;
13990                 }
13991
13992               haveindex = 1;
13993               switch (vex.length)
13994                 {
13995                 case 128:
13996                   indexes64 = indexes32 = names_xmm;
13997                   break;
13998                 case 256:
13999                   if (!vex.w
14000                       || bytemode == vex_vsib_q_w_dq_mode
14001                       || bytemode == vex_vsib_q_w_d_mode)
14002                     indexes64 = indexes32 = names_ymm;
14003                   else
14004                     indexes64 = indexes32 = names_xmm;
14005                   break;
14006                 case 512:
14007                   if (!vex.w
14008                       || bytemode == vex_vsib_q_w_dq_mode
14009                       || bytemode == vex_vsib_q_w_d_mode)
14010                     indexes64 = indexes32 = names_zmm;
14011                   else
14012                     indexes64 = indexes32 = names_ymm;
14013                   break;
14014                 default:
14015                   abort ();
14016                 }
14017               break;
14018             default:
14019               haveindex = vindex != 4;
14020               break;
14021             }
14022           scale = sib.scale;
14023           base = sib.base;
14024           codep++;
14025         }
14026       rbase = base + add;
14027
14028       switch (modrm.mod)
14029         {
14030         case 0:
14031           if (base == 5)
14032             {
14033               havebase = 0;
14034               if (address_mode == mode_64bit && !havesib)
14035                 riprel = 1;
14036               disp = get32s ();
14037               if (riprel && bytemode == v_bndmk_mode)
14038                 {
14039                   oappend ("(bad)");
14040                   return;
14041                 }
14042             }
14043           break;
14044         case 1:
14045           FETCH_DATA (the_info, codep + 1);
14046           disp = *codep++;
14047           if ((disp & 0x80) != 0)
14048             disp -= 0x100;
14049           if (vex.evex && shift > 0)
14050             disp <<= shift;
14051           break;
14052         case 2:
14053           disp = get32s ();
14054           break;
14055         }
14056
14057       needindex = 0;
14058       needaddr32 = 0;
14059       if (havesib
14060           && !havebase
14061           && !haveindex
14062           && address_mode != mode_16bit)
14063         {
14064           if (address_mode == mode_64bit)
14065             {
14066               /* Display eiz instead of addr32.  */
14067               needindex = addr32flag;
14068               needaddr32 = 1;
14069             }
14070           else
14071             {
14072               /* In 32-bit mode, we need index register to tell [offset]
14073                  from [eiz*1 + offset].  */
14074               needindex = 1;
14075             }
14076         }
14077
14078       havedisp = (havebase
14079                   || needindex
14080                   || (havesib && (haveindex || scale != 0)));
14081
14082       if (!intel_syntax)
14083         if (modrm.mod != 0 || base == 5)
14084           {
14085             if (havedisp || riprel)
14086               print_displacement (scratchbuf, disp);
14087             else
14088               print_operand_value (scratchbuf, 1, disp);
14089             oappend (scratchbuf);
14090             if (riprel)
14091               {
14092                 set_op (disp, 1);
14093                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14094               }
14095           }
14096
14097       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14098           && (address_mode != mode_64bit
14099               || ((bytemode != v_bnd_mode)
14100                   && (bytemode != v_bndmk_mode)
14101                   && (bytemode != bnd_mode)
14102                   && (bytemode != bnd_swap_mode))))
14103         used_prefixes |= PREFIX_ADDR;
14104
14105       if (havedisp || (intel_syntax && riprel))
14106         {
14107           *obufp++ = open_char;
14108           if (intel_syntax && riprel)
14109             {
14110               set_op (disp, 1);
14111               oappend (!addr32flag ? "rip" : "eip");
14112             }
14113           *obufp = '\0';
14114           if (havebase)
14115             oappend (address_mode == mode_64bit && !addr32flag
14116                      ? names64[rbase] : names32[rbase]);
14117           if (havesib)
14118             {
14119               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14120                  print index to tell base + index from base.  */
14121               if (scale != 0
14122                   || needindex
14123                   || haveindex
14124                   || (havebase && base != ESP_REG_NUM))
14125                 {
14126                   if (!intel_syntax || havebase)
14127                     {
14128                       *obufp++ = separator_char;
14129                       *obufp = '\0';
14130                     }
14131                   if (haveindex)
14132                     oappend (address_mode == mode_64bit && !addr32flag
14133                              ? indexes64[vindex] : indexes32[vindex]);
14134                   else
14135                     oappend (address_mode == mode_64bit && !addr32flag
14136                              ? index64 : index32);
14137
14138                   *obufp++ = scale_char;
14139                   *obufp = '\0';
14140                   sprintf (scratchbuf, "%d", 1 << scale);
14141                   oappend (scratchbuf);
14142                 }
14143             }
14144           if (intel_syntax
14145               && (disp || modrm.mod != 0 || base == 5))
14146             {
14147               if (!havedisp || (bfd_signed_vma) disp >= 0)
14148                 {
14149                   *obufp++ = '+';
14150                   *obufp = '\0';
14151                 }
14152               else if (modrm.mod != 1 && disp != -disp)
14153                 {
14154                   *obufp++ = '-';
14155                   *obufp = '\0';
14156                   disp = - (bfd_signed_vma) disp;
14157                 }
14158
14159               if (havedisp)
14160                 print_displacement (scratchbuf, disp);
14161               else
14162                 print_operand_value (scratchbuf, 1, disp);
14163               oappend (scratchbuf);
14164             }
14165
14166           *obufp++ = close_char;
14167           *obufp = '\0';
14168         }
14169       else if (intel_syntax)
14170         {
14171           if (modrm.mod != 0 || base == 5)
14172             {
14173               if (!active_seg_prefix)
14174                 {
14175                   oappend (names_seg[ds_reg - es_reg]);
14176                   oappend (":");
14177                 }
14178               print_operand_value (scratchbuf, 1, disp);
14179               oappend (scratchbuf);
14180             }
14181         }
14182     }
14183   else if (bytemode == v_bnd_mode
14184            || bytemode == v_bndmk_mode
14185            || bytemode == bnd_mode
14186            || bytemode == bnd_swap_mode)
14187     {
14188       oappend ("(bad)");
14189       return;
14190     }
14191   else
14192     {
14193       /* 16 bit address mode */
14194       used_prefixes |= prefixes & PREFIX_ADDR;
14195       switch (modrm.mod)
14196         {
14197         case 0:
14198           if (modrm.rm == 6)
14199             {
14200               disp = get16 ();
14201               if ((disp & 0x8000) != 0)
14202                 disp -= 0x10000;
14203             }
14204           break;
14205         case 1:
14206           FETCH_DATA (the_info, codep + 1);
14207           disp = *codep++;
14208           if ((disp & 0x80) != 0)
14209             disp -= 0x100;
14210           if (vex.evex && shift > 0)
14211             disp <<= shift;
14212           break;
14213         case 2:
14214           disp = get16 ();
14215           if ((disp & 0x8000) != 0)
14216             disp -= 0x10000;
14217           break;
14218         }
14219
14220       if (!intel_syntax)
14221         if (modrm.mod != 0 || modrm.rm == 6)
14222           {
14223             print_displacement (scratchbuf, disp);
14224             oappend (scratchbuf);
14225           }
14226
14227       if (modrm.mod != 0 || modrm.rm != 6)
14228         {
14229           *obufp++ = open_char;
14230           *obufp = '\0';
14231           oappend (index16[modrm.rm]);
14232           if (intel_syntax
14233               && (disp || modrm.mod != 0 || modrm.rm == 6))
14234             {
14235               if ((bfd_signed_vma) disp >= 0)
14236                 {
14237                   *obufp++ = '+';
14238                   *obufp = '\0';
14239                 }
14240               else if (modrm.mod != 1)
14241                 {
14242                   *obufp++ = '-';
14243                   *obufp = '\0';
14244                   disp = - (bfd_signed_vma) disp;
14245                 }
14246
14247               print_displacement (scratchbuf, disp);
14248               oappend (scratchbuf);
14249             }
14250
14251           *obufp++ = close_char;
14252           *obufp = '\0';
14253         }
14254       else if (intel_syntax)
14255         {
14256           if (!active_seg_prefix)
14257             {
14258               oappend (names_seg[ds_reg - es_reg]);
14259               oappend (":");
14260             }
14261           print_operand_value (scratchbuf, 1, disp & 0xffff);
14262           oappend (scratchbuf);
14263         }
14264     }
14265   if (vex.evex && vex.b
14266       && (bytemode == x_mode
14267           || bytemode == xmmq_mode
14268           || bytemode == evex_half_bcst_xmmq_mode))
14269     {
14270       if (vex.w
14271           || bytemode == xmmq_mode
14272           || bytemode == evex_half_bcst_xmmq_mode)
14273         {
14274           switch (vex.length)
14275             {
14276             case 128:
14277               oappend ("{1to2}");
14278               break;
14279             case 256:
14280               oappend ("{1to4}");
14281               break;
14282             case 512:
14283               oappend ("{1to8}");
14284               break;
14285             default:
14286               abort ();
14287             }
14288         }
14289       else
14290         {
14291           switch (vex.length)
14292             {
14293             case 128:
14294               oappend ("{1to4}");
14295               break;
14296             case 256:
14297               oappend ("{1to8}");
14298               break;
14299             case 512:
14300               oappend ("{1to16}");
14301               break;
14302             default:
14303               abort ();
14304             }
14305         }
14306     }
14307 }
14308
14309 static void
14310 OP_E (int bytemode, int sizeflag)
14311 {
14312   /* Skip mod/rm byte.  */
14313   MODRM_CHECK;
14314   codep++;
14315
14316   if (modrm.mod == 3)
14317     OP_E_register (bytemode, sizeflag);
14318   else
14319     OP_E_memory (bytemode, sizeflag);
14320 }
14321
14322 static void
14323 OP_G (int bytemode, int sizeflag)
14324 {
14325   int add = 0;
14326   const char **names;
14327   USED_REX (REX_R);
14328   if (rex & REX_R)
14329     add += 8;
14330   switch (bytemode)
14331     {
14332     case b_mode:
14333       USED_REX (0);
14334       if (rex)
14335         oappend (names8rex[modrm.reg + add]);
14336       else
14337         oappend (names8[modrm.reg + add]);
14338       break;
14339     case w_mode:
14340       oappend (names16[modrm.reg + add]);
14341       break;
14342     case d_mode:
14343     case db_mode:
14344     case dw_mode:
14345       oappend (names32[modrm.reg + add]);
14346       break;
14347     case q_mode:
14348       oappend (names64[modrm.reg + add]);
14349       break;
14350     case bnd_mode:
14351       if (modrm.reg > 0x3)
14352         {
14353           oappend ("(bad)");
14354           return;
14355         }
14356       oappend (names_bnd[modrm.reg]);
14357       break;
14358     case v_mode:
14359     case dq_mode:
14360     case dqb_mode:
14361     case dqd_mode:
14362     case dqw_mode:
14363     case movsxd_mode:
14364       USED_REX (REX_W);
14365       if (rex & REX_W)
14366         oappend (names64[modrm.reg + add]);
14367       else
14368         {
14369           if ((sizeflag & DFLAG)
14370               || (bytemode != v_mode && bytemode != movsxd_mode))
14371             oappend (names32[modrm.reg + add]);
14372           else
14373             oappend (names16[modrm.reg + add]);
14374           used_prefixes |= (prefixes & PREFIX_DATA);
14375         }
14376       break;
14377     case va_mode:
14378       names = (address_mode == mode_64bit
14379                ? names64 : names32);
14380       if (!(prefixes & PREFIX_ADDR))
14381         {
14382           if (address_mode == mode_16bit)
14383             names = names16;
14384         }
14385       else
14386         {
14387           /* Remove "addr16/addr32".  */
14388           all_prefixes[last_addr_prefix] = 0;
14389           names = (address_mode != mode_32bit
14390                        ? names32 : names16);
14391           used_prefixes |= PREFIX_ADDR;
14392         }
14393       oappend (names[modrm.reg + add]);
14394       break;
14395     case m_mode:
14396       if (address_mode == mode_64bit)
14397         oappend (names64[modrm.reg + add]);
14398       else
14399         oappend (names32[modrm.reg + add]);
14400       break;
14401     case mask_bd_mode:
14402     case mask_mode:
14403       if ((modrm.reg + add) > 0x7)
14404         {
14405           oappend ("(bad)");
14406           return;
14407         }
14408       oappend (names_mask[modrm.reg + add]);
14409       break;
14410     default:
14411       oappend (INTERNAL_DISASSEMBLER_ERROR);
14412       break;
14413     }
14414 }
14415
14416 static bfd_vma
14417 get64 (void)
14418 {
14419   bfd_vma x;
14420 #ifdef BFD64
14421   unsigned int a;
14422   unsigned int b;
14423
14424   FETCH_DATA (the_info, codep + 8);
14425   a = *codep++ & 0xff;
14426   a |= (*codep++ & 0xff) << 8;
14427   a |= (*codep++ & 0xff) << 16;
14428   a |= (*codep++ & 0xffu) << 24;
14429   b = *codep++ & 0xff;
14430   b |= (*codep++ & 0xff) << 8;
14431   b |= (*codep++ & 0xff) << 16;
14432   b |= (*codep++ & 0xffu) << 24;
14433   x = a + ((bfd_vma) b << 32);
14434 #else
14435   abort ();
14436   x = 0;
14437 #endif
14438   return x;
14439 }
14440
14441 static bfd_signed_vma
14442 get32 (void)
14443 {
14444   bfd_signed_vma x = 0;
14445
14446   FETCH_DATA (the_info, codep + 4);
14447   x = *codep++ & (bfd_signed_vma) 0xff;
14448   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14449   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14450   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14451   return x;
14452 }
14453
14454 static bfd_signed_vma
14455 get32s (void)
14456 {
14457   bfd_signed_vma x = 0;
14458
14459   FETCH_DATA (the_info, codep + 4);
14460   x = *codep++ & (bfd_signed_vma) 0xff;
14461   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14462   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14463   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14464
14465   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14466
14467   return x;
14468 }
14469
14470 static int
14471 get16 (void)
14472 {
14473   int x = 0;
14474
14475   FETCH_DATA (the_info, codep + 2);
14476   x = *codep++ & 0xff;
14477   x |= (*codep++ & 0xff) << 8;
14478   return x;
14479 }
14480
14481 static void
14482 set_op (bfd_vma op, int riprel)
14483 {
14484   op_index[op_ad] = op_ad;
14485   if (address_mode == mode_64bit)
14486     {
14487       op_address[op_ad] = op;
14488       op_riprel[op_ad] = riprel;
14489     }
14490   else
14491     {
14492       /* Mask to get a 32-bit address.  */
14493       op_address[op_ad] = op & 0xffffffff;
14494       op_riprel[op_ad] = riprel & 0xffffffff;
14495     }
14496 }
14497
14498 static void
14499 OP_REG (int code, int sizeflag)
14500 {
14501   const char *s;
14502   int add;
14503
14504   switch (code)
14505     {
14506     case es_reg: case ss_reg: case cs_reg:
14507     case ds_reg: case fs_reg: case gs_reg:
14508       oappend (names_seg[code - es_reg]);
14509       return;
14510     }
14511
14512   USED_REX (REX_B);
14513   if (rex & REX_B)
14514     add = 8;
14515   else
14516     add = 0;
14517
14518   switch (code)
14519     {
14520     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14521     case sp_reg: case bp_reg: case si_reg: case di_reg:
14522       s = names16[code - ax_reg + add];
14523       break;
14524     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14525     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14526       USED_REX (0);
14527       if (rex)
14528         s = names8rex[code - al_reg + add];
14529       else
14530         s = names8[code - al_reg];
14531       break;
14532     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14533     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14534       if (address_mode == mode_64bit
14535           && ((sizeflag & DFLAG) || (rex & REX_W)))
14536         {
14537           s = names64[code - rAX_reg + add];
14538           break;
14539         }
14540       code += eAX_reg - rAX_reg;
14541       /* Fall through.  */
14542     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14543     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14544       USED_REX (REX_W);
14545       if (rex & REX_W)
14546         s = names64[code - eAX_reg + add];
14547       else
14548         {
14549           if (sizeflag & DFLAG)
14550             s = names32[code - eAX_reg + add];
14551           else
14552             s = names16[code - eAX_reg + add];
14553           used_prefixes |= (prefixes & PREFIX_DATA);
14554         }
14555       break;
14556     default:
14557       s = INTERNAL_DISASSEMBLER_ERROR;
14558       break;
14559     }
14560   oappend (s);
14561 }
14562
14563 static void
14564 OP_IMREG (int code, int sizeflag)
14565 {
14566   const char *s;
14567
14568   switch (code)
14569     {
14570     case indir_dx_reg:
14571       if (intel_syntax)
14572         s = "dx";
14573       else
14574         s = "(%dx)";
14575       break;
14576     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14577     case sp_reg: case bp_reg: case si_reg: case di_reg:
14578       s = names16[code - ax_reg];
14579       break;
14580     case es_reg: case ss_reg: case cs_reg:
14581     case ds_reg: case fs_reg: case gs_reg:
14582       s = names_seg[code - es_reg];
14583       break;
14584     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14585     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14586       USED_REX (0);
14587       if (rex)
14588         s = names8rex[code - al_reg];
14589       else
14590         s = names8[code - al_reg];
14591       break;
14592     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14593     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14594       USED_REX (REX_W);
14595       if (rex & REX_W)
14596         s = names64[code - eAX_reg];
14597       else
14598         {
14599           if (sizeflag & DFLAG)
14600             s = names32[code - eAX_reg];
14601           else
14602             s = names16[code - eAX_reg];
14603           used_prefixes |= (prefixes & PREFIX_DATA);
14604         }
14605       break;
14606     case z_mode_ax_reg:
14607       if ((rex & REX_W) || (sizeflag & DFLAG))
14608         s = *names32;
14609       else
14610         s = *names16;
14611       if (!(rex & REX_W))
14612         used_prefixes |= (prefixes & PREFIX_DATA);
14613       break;
14614     default:
14615       s = INTERNAL_DISASSEMBLER_ERROR;
14616       break;
14617     }
14618   oappend (s);
14619 }
14620
14621 static void
14622 OP_I (int bytemode, int sizeflag)
14623 {
14624   bfd_signed_vma op;
14625   bfd_signed_vma mask = -1;
14626
14627   switch (bytemode)
14628     {
14629     case b_mode:
14630       FETCH_DATA (the_info, codep + 1);
14631       op = *codep++;
14632       mask = 0xff;
14633       break;
14634     case v_mode:
14635       USED_REX (REX_W);
14636       if (rex & REX_W)
14637         op = get32s ();
14638       else
14639         {
14640           if (sizeflag & DFLAG)
14641             {
14642               op = get32 ();
14643               mask = 0xffffffff;
14644             }
14645           else
14646             {
14647               op = get16 ();
14648               mask = 0xfffff;
14649             }
14650           used_prefixes |= (prefixes & PREFIX_DATA);
14651         }
14652       break;
14653     case d_mode:
14654       mask = 0xffffffff;
14655       op = get32 ();
14656       break;
14657     case w_mode:
14658       mask = 0xfffff;
14659       op = get16 ();
14660       break;
14661     case const_1_mode:
14662       if (intel_syntax)
14663         oappend ("1");
14664       return;
14665     default:
14666       oappend (INTERNAL_DISASSEMBLER_ERROR);
14667       return;
14668     }
14669
14670   op &= mask;
14671   scratchbuf[0] = '$';
14672   print_operand_value (scratchbuf + 1, 1, op);
14673   oappend_maybe_intel (scratchbuf);
14674   scratchbuf[0] = '\0';
14675 }
14676
14677 static void
14678 OP_I64 (int bytemode, int sizeflag)
14679 {
14680   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14681     {
14682       OP_I (bytemode, sizeflag);
14683       return;
14684     }
14685
14686   USED_REX (REX_W);
14687
14688   scratchbuf[0] = '$';
14689   print_operand_value (scratchbuf + 1, 1, get64 ());
14690   oappend_maybe_intel (scratchbuf);
14691   scratchbuf[0] = '\0';
14692 }
14693
14694 static void
14695 OP_sI (int bytemode, int sizeflag)
14696 {
14697   bfd_signed_vma op;
14698
14699   switch (bytemode)
14700     {
14701     case b_mode:
14702     case b_T_mode:
14703       FETCH_DATA (the_info, codep + 1);
14704       op = *codep++;
14705       if ((op & 0x80) != 0)
14706         op -= 0x100;
14707       if (bytemode == b_T_mode)
14708         {
14709           if (address_mode != mode_64bit
14710               || !((sizeflag & DFLAG) || (rex & REX_W)))
14711             {
14712               /* The operand-size prefix is overridden by a REX prefix.  */
14713               if ((sizeflag & DFLAG) || (rex & REX_W))
14714                 op &= 0xffffffff;
14715               else
14716                 op &= 0xffff;
14717           }
14718         }
14719       else
14720         {
14721           if (!(rex & REX_W))
14722             {
14723               if (sizeflag & DFLAG)
14724                 op &= 0xffffffff;
14725               else
14726                 op &= 0xffff;
14727             }
14728         }
14729       break;
14730     case v_mode:
14731       /* The operand-size prefix is overridden by a REX prefix.  */
14732       if ((sizeflag & DFLAG) || (rex & REX_W))
14733         op = get32s ();
14734       else
14735         op = get16 ();
14736       break;
14737     default:
14738       oappend (INTERNAL_DISASSEMBLER_ERROR);
14739       return;
14740     }
14741
14742   scratchbuf[0] = '$';
14743   print_operand_value (scratchbuf + 1, 1, op);
14744   oappend_maybe_intel (scratchbuf);
14745 }
14746
14747 static void
14748 OP_J (int bytemode, int sizeflag)
14749 {
14750   bfd_vma disp;
14751   bfd_vma mask = -1;
14752   bfd_vma segment = 0;
14753
14754   switch (bytemode)
14755     {
14756     case b_mode:
14757       FETCH_DATA (the_info, codep + 1);
14758       disp = *codep++;
14759       if ((disp & 0x80) != 0)
14760         disp -= 0x100;
14761       break;
14762     case v_mode:
14763       if (isa64 != intel64)
14764     case dqw_mode:
14765         USED_REX (REX_W);
14766       if ((sizeflag & DFLAG)
14767           || (address_mode == mode_64bit
14768               && ((isa64 == intel64 && bytemode != dqw_mode)
14769                   || (rex & REX_W))))
14770         disp = get32s ();
14771       else
14772         {
14773           disp = get16 ();
14774           if ((disp & 0x8000) != 0)
14775             disp -= 0x10000;
14776           /* In 16bit mode, address is wrapped around at 64k within
14777              the same segment.  Otherwise, a data16 prefix on a jump
14778              instruction means that the pc is masked to 16 bits after
14779              the displacement is added!  */
14780           mask = 0xffff;
14781           if ((prefixes & PREFIX_DATA) == 0)
14782             segment = ((start_pc + (codep - start_codep))
14783                        & ~((bfd_vma) 0xffff));
14784         }
14785       if (address_mode != mode_64bit
14786           || (isa64 != intel64 && !(rex & REX_W)))
14787         used_prefixes |= (prefixes & PREFIX_DATA);
14788       break;
14789     default:
14790       oappend (INTERNAL_DISASSEMBLER_ERROR);
14791       return;
14792     }
14793   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14794   set_op (disp, 0);
14795   print_operand_value (scratchbuf, 1, disp);
14796   oappend (scratchbuf);
14797 }
14798
14799 static void
14800 OP_SEG (int bytemode, int sizeflag)
14801 {
14802   if (bytemode == w_mode)
14803     oappend (names_seg[modrm.reg]);
14804   else
14805     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14806 }
14807
14808 static void
14809 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14810 {
14811   int seg, offset;
14812
14813   if (sizeflag & DFLAG)
14814     {
14815       offset = get32 ();
14816       seg = get16 ();
14817     }
14818   else
14819     {
14820       offset = get16 ();
14821       seg = get16 ();
14822     }
14823   used_prefixes |= (prefixes & PREFIX_DATA);
14824   if (intel_syntax)
14825     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14826   else
14827     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14828   oappend (scratchbuf);
14829 }
14830
14831 static void
14832 OP_OFF (int bytemode, int sizeflag)
14833 {
14834   bfd_vma off;
14835
14836   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14837     intel_operand_size (bytemode, sizeflag);
14838   append_seg ();
14839
14840   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14841     off = get32 ();
14842   else
14843     off = get16 ();
14844
14845   if (intel_syntax)
14846     {
14847       if (!active_seg_prefix)
14848         {
14849           oappend (names_seg[ds_reg - es_reg]);
14850           oappend (":");
14851         }
14852     }
14853   print_operand_value (scratchbuf, 1, off);
14854   oappend (scratchbuf);
14855 }
14856
14857 static void
14858 OP_OFF64 (int bytemode, int sizeflag)
14859 {
14860   bfd_vma off;
14861
14862   if (address_mode != mode_64bit
14863       || (prefixes & PREFIX_ADDR))
14864     {
14865       OP_OFF (bytemode, sizeflag);
14866       return;
14867     }
14868
14869   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14870     intel_operand_size (bytemode, sizeflag);
14871   append_seg ();
14872
14873   off = get64 ();
14874
14875   if (intel_syntax)
14876     {
14877       if (!active_seg_prefix)
14878         {
14879           oappend (names_seg[ds_reg - es_reg]);
14880           oappend (":");
14881         }
14882     }
14883   print_operand_value (scratchbuf, 1, off);
14884   oappend (scratchbuf);
14885 }
14886
14887 static void
14888 ptr_reg (int code, int sizeflag)
14889 {
14890   const char *s;
14891
14892   *obufp++ = open_char;
14893   used_prefixes |= (prefixes & PREFIX_ADDR);
14894   if (address_mode == mode_64bit)
14895     {
14896       if (!(sizeflag & AFLAG))
14897         s = names32[code - eAX_reg];
14898       else
14899         s = names64[code - eAX_reg];
14900     }
14901   else if (sizeflag & AFLAG)
14902     s = names32[code - eAX_reg];
14903   else
14904     s = names16[code - eAX_reg];
14905   oappend (s);
14906   *obufp++ = close_char;
14907   *obufp = 0;
14908 }
14909
14910 static void
14911 OP_ESreg (int code, int sizeflag)
14912 {
14913   if (intel_syntax)
14914     {
14915       switch (codep[-1])
14916         {
14917         case 0x6d:      /* insw/insl */
14918           intel_operand_size (z_mode, sizeflag);
14919           break;
14920         case 0xa5:      /* movsw/movsl/movsq */
14921         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14922         case 0xab:      /* stosw/stosl */
14923         case 0xaf:      /* scasw/scasl */
14924           intel_operand_size (v_mode, sizeflag);
14925           break;
14926         default:
14927           intel_operand_size (b_mode, sizeflag);
14928         }
14929     }
14930   oappend_maybe_intel ("%es:");
14931   ptr_reg (code, sizeflag);
14932 }
14933
14934 static void
14935 OP_DSreg (int code, int sizeflag)
14936 {
14937   if (intel_syntax)
14938     {
14939       switch (codep[-1])
14940         {
14941         case 0x6f:      /* outsw/outsl */
14942           intel_operand_size (z_mode, sizeflag);
14943           break;
14944         case 0xa5:      /* movsw/movsl/movsq */
14945         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14946         case 0xad:      /* lodsw/lodsl/lodsq */
14947           intel_operand_size (v_mode, sizeflag);
14948           break;
14949         default:
14950           intel_operand_size (b_mode, sizeflag);
14951         }
14952     }
14953   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
14954      default segment register DS is printed.  */
14955   if (!active_seg_prefix)
14956     active_seg_prefix = PREFIX_DS;
14957   append_seg ();
14958   ptr_reg (code, sizeflag);
14959 }
14960
14961 static void
14962 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14963 {
14964   int add;
14965   if (rex & REX_R)
14966     {
14967       USED_REX (REX_R);
14968       add = 8;
14969     }
14970   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
14971     {
14972       all_prefixes[last_lock_prefix] = 0;
14973       used_prefixes |= PREFIX_LOCK;
14974       add = 8;
14975     }
14976   else
14977     add = 0;
14978   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
14979   oappend_maybe_intel (scratchbuf);
14980 }
14981
14982 static void
14983 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14984 {
14985   int add;
14986   USED_REX (REX_R);
14987   if (rex & REX_R)
14988     add = 8;
14989   else
14990     add = 0;
14991   if (intel_syntax)
14992     sprintf (scratchbuf, "db%d", modrm.reg + add);
14993   else
14994     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
14995   oappend (scratchbuf);
14996 }
14997
14998 static void
14999 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15000 {
15001   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15002   oappend_maybe_intel (scratchbuf);
15003 }
15004
15005 static void
15006 OP_R (int bytemode, int sizeflag)
15007 {
15008   /* Skip mod/rm byte.  */
15009   MODRM_CHECK;
15010   codep++;
15011   OP_E_register (bytemode, sizeflag);
15012 }
15013
15014 static void
15015 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15016 {
15017   int reg = modrm.reg;
15018   const char **names;
15019
15020   used_prefixes |= (prefixes & PREFIX_DATA);
15021   if (prefixes & PREFIX_DATA)
15022     {
15023       names = names_xmm;
15024       USED_REX (REX_R);
15025       if (rex & REX_R)
15026         reg += 8;
15027     }
15028   else
15029     names = names_mm;
15030   oappend (names[reg]);
15031 }
15032
15033 static void
15034 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15035 {
15036   int reg = modrm.reg;
15037   const char **names;
15038
15039   USED_REX (REX_R);
15040   if (rex & REX_R)
15041     reg += 8;
15042   if (vex.evex)
15043     {
15044       if (!vex.r)
15045         reg += 16;
15046     }
15047
15048   if (need_vex
15049       && bytemode != xmm_mode
15050       && bytemode != xmmq_mode
15051       && bytemode != evex_half_bcst_xmmq_mode
15052       && bytemode != ymm_mode
15053       && bytemode != scalar_mode)
15054     {
15055       switch (vex.length)
15056         {
15057         case 128:
15058           names = names_xmm;
15059           break;
15060         case 256:
15061           if (vex.w
15062               || (bytemode != vex_vsib_q_w_dq_mode
15063                   && bytemode != vex_vsib_q_w_d_mode))
15064             names = names_ymm;
15065           else
15066             names = names_xmm;
15067           break;
15068         case 512:
15069           names = names_zmm;
15070           break;
15071         default:
15072           abort ();
15073         }
15074     }
15075   else if (bytemode == xmmq_mode
15076            || bytemode == evex_half_bcst_xmmq_mode)
15077     {
15078       switch (vex.length)
15079         {
15080         case 128:
15081         case 256:
15082           names = names_xmm;
15083           break;
15084         case 512:
15085           names = names_ymm;
15086           break;
15087         default:
15088           abort ();
15089         }
15090     }
15091   else if (bytemode == ymm_mode)
15092     names = names_ymm;
15093   else
15094     names = names_xmm;
15095   oappend (names[reg]);
15096 }
15097
15098 static void
15099 OP_EM (int bytemode, int sizeflag)
15100 {
15101   int reg;
15102   const char **names;
15103
15104   if (modrm.mod != 3)
15105     {
15106       if (intel_syntax
15107           && (bytemode == v_mode || bytemode == v_swap_mode))
15108         {
15109           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15110           used_prefixes |= (prefixes & PREFIX_DATA);
15111         }
15112       OP_E (bytemode, sizeflag);
15113       return;
15114     }
15115
15116   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15117     swap_operand ();
15118
15119   /* Skip mod/rm byte.  */
15120   MODRM_CHECK;
15121   codep++;
15122   used_prefixes |= (prefixes & PREFIX_DATA);
15123   reg = modrm.rm;
15124   if (prefixes & PREFIX_DATA)
15125     {
15126       names = names_xmm;
15127       USED_REX (REX_B);
15128       if (rex & REX_B)
15129         reg += 8;
15130     }
15131   else
15132     names = names_mm;
15133   oappend (names[reg]);
15134 }
15135
15136 /* cvt* are the only instructions in sse2 which have
15137    both SSE and MMX operands and also have 0x66 prefix
15138    in their opcode. 0x66 was originally used to differentiate
15139    between SSE and MMX instruction(operands). So we have to handle the
15140    cvt* separately using OP_EMC and OP_MXC */
15141 static void
15142 OP_EMC (int bytemode, int sizeflag)
15143 {
15144   if (modrm.mod != 3)
15145     {
15146       if (intel_syntax && bytemode == v_mode)
15147         {
15148           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15149           used_prefixes |= (prefixes & PREFIX_DATA);
15150         }
15151       OP_E (bytemode, sizeflag);
15152       return;
15153     }
15154
15155   /* Skip mod/rm byte.  */
15156   MODRM_CHECK;
15157   codep++;
15158   used_prefixes |= (prefixes & PREFIX_DATA);
15159   oappend (names_mm[modrm.rm]);
15160 }
15161
15162 static void
15163 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15164 {
15165   used_prefixes |= (prefixes & PREFIX_DATA);
15166   oappend (names_mm[modrm.reg]);
15167 }
15168
15169 static void
15170 OP_EX (int bytemode, int sizeflag)
15171 {
15172   int reg;
15173   const char **names;
15174
15175   /* Skip mod/rm byte.  */
15176   MODRM_CHECK;
15177   codep++;
15178
15179   if (modrm.mod != 3)
15180     {
15181       OP_E_memory (bytemode, sizeflag);
15182       return;
15183     }
15184
15185   reg = modrm.rm;
15186   USED_REX (REX_B);
15187   if (rex & REX_B)
15188     reg += 8;
15189   if (vex.evex)
15190     {
15191       USED_REX (REX_X);
15192       if ((rex & REX_X))
15193         reg += 16;
15194     }
15195
15196   if ((sizeflag & SUFFIX_ALWAYS)
15197       && (bytemode == x_swap_mode
15198           || bytemode == d_swap_mode
15199           || bytemode == d_scalar_swap_mode
15200           || bytemode == q_swap_mode
15201           || bytemode == q_scalar_swap_mode))
15202     swap_operand ();
15203
15204   if (need_vex
15205       && bytemode != xmm_mode
15206       && bytemode != xmmdw_mode
15207       && bytemode != xmmqd_mode
15208       && bytemode != xmm_mb_mode
15209       && bytemode != xmm_mw_mode
15210       && bytemode != xmm_md_mode
15211       && bytemode != xmm_mq_mode
15212       && bytemode != xmmq_mode
15213       && bytemode != evex_half_bcst_xmmq_mode
15214       && bytemode != ymm_mode
15215       && bytemode != d_scalar_swap_mode
15216       && bytemode != q_scalar_swap_mode
15217       && bytemode != vex_scalar_w_dq_mode)
15218     {
15219       switch (vex.length)
15220         {
15221         case 128:
15222           names = names_xmm;
15223           break;
15224         case 256:
15225           names = names_ymm;
15226           break;
15227         case 512:
15228           names = names_zmm;
15229           break;
15230         default:
15231           abort ();
15232         }
15233     }
15234   else if (bytemode == xmmq_mode
15235            || bytemode == evex_half_bcst_xmmq_mode)
15236     {
15237       switch (vex.length)
15238         {
15239         case 128:
15240         case 256:
15241           names = names_xmm;
15242           break;
15243         case 512:
15244           names = names_ymm;
15245           break;
15246         default:
15247           abort ();
15248         }
15249     }
15250   else if (bytemode == ymm_mode)
15251     names = names_ymm;
15252   else
15253     names = names_xmm;
15254   oappend (names[reg]);
15255 }
15256
15257 static void
15258 OP_MS (int bytemode, int sizeflag)
15259 {
15260   if (modrm.mod == 3)
15261     OP_EM (bytemode, sizeflag);
15262   else
15263     BadOp ();
15264 }
15265
15266 static void
15267 OP_XS (int bytemode, int sizeflag)
15268 {
15269   if (modrm.mod == 3)
15270     OP_EX (bytemode, sizeflag);
15271   else
15272     BadOp ();
15273 }
15274
15275 static void
15276 OP_M (int bytemode, int sizeflag)
15277 {
15278   if (modrm.mod == 3)
15279     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15280     BadOp ();
15281   else
15282     OP_E (bytemode, sizeflag);
15283 }
15284
15285 static void
15286 OP_0f07 (int bytemode, int sizeflag)
15287 {
15288   if (modrm.mod != 3 || modrm.rm != 0)
15289     BadOp ();
15290   else
15291     OP_E (bytemode, sizeflag);
15292 }
15293
15294 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15295    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15296
15297 static void
15298 NOP_Fixup1 (int bytemode, int sizeflag)
15299 {
15300   if ((prefixes & PREFIX_DATA) != 0
15301       || (rex != 0
15302           && rex != 0x48
15303           && address_mode == mode_64bit))
15304     OP_REG (bytemode, sizeflag);
15305   else
15306     strcpy (obuf, "nop");
15307 }
15308
15309 static void
15310 NOP_Fixup2 (int bytemode, int sizeflag)
15311 {
15312   if ((prefixes & PREFIX_DATA) != 0
15313       || (rex != 0
15314           && rex != 0x48
15315           && address_mode == mode_64bit))
15316     OP_IMREG (bytemode, sizeflag);
15317 }
15318
15319 static const char *const Suffix3DNow[] = {
15320 /* 00 */        NULL,           NULL,           NULL,           NULL,
15321 /* 04 */        NULL,           NULL,           NULL,           NULL,
15322 /* 08 */        NULL,           NULL,           NULL,           NULL,
15323 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15324 /* 10 */        NULL,           NULL,           NULL,           NULL,
15325 /* 14 */        NULL,           NULL,           NULL,           NULL,
15326 /* 18 */        NULL,           NULL,           NULL,           NULL,
15327 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15328 /* 20 */        NULL,           NULL,           NULL,           NULL,
15329 /* 24 */        NULL,           NULL,           NULL,           NULL,
15330 /* 28 */        NULL,           NULL,           NULL,           NULL,
15331 /* 2C */        NULL,           NULL,           NULL,           NULL,
15332 /* 30 */        NULL,           NULL,           NULL,           NULL,
15333 /* 34 */        NULL,           NULL,           NULL,           NULL,
15334 /* 38 */        NULL,           NULL,           NULL,           NULL,
15335 /* 3C */        NULL,           NULL,           NULL,           NULL,
15336 /* 40 */        NULL,           NULL,           NULL,           NULL,
15337 /* 44 */        NULL,           NULL,           NULL,           NULL,
15338 /* 48 */        NULL,           NULL,           NULL,           NULL,
15339 /* 4C */        NULL,           NULL,           NULL,           NULL,
15340 /* 50 */        NULL,           NULL,           NULL,           NULL,
15341 /* 54 */        NULL,           NULL,           NULL,           NULL,
15342 /* 58 */        NULL,           NULL,           NULL,           NULL,
15343 /* 5C */        NULL,           NULL,           NULL,           NULL,
15344 /* 60 */        NULL,           NULL,           NULL,           NULL,
15345 /* 64 */        NULL,           NULL,           NULL,           NULL,
15346 /* 68 */        NULL,           NULL,           NULL,           NULL,
15347 /* 6C */        NULL,           NULL,           NULL,           NULL,
15348 /* 70 */        NULL,           NULL,           NULL,           NULL,
15349 /* 74 */        NULL,           NULL,           NULL,           NULL,
15350 /* 78 */        NULL,           NULL,           NULL,           NULL,
15351 /* 7C */        NULL,           NULL,           NULL,           NULL,
15352 /* 80 */        NULL,           NULL,           NULL,           NULL,
15353 /* 84 */        NULL,           NULL,           NULL,           NULL,
15354 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15355 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15356 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15357 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15358 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15359 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15360 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15361 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15362 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15363 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15364 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15365 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15366 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15367 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15368 /* C0 */        NULL,           NULL,           NULL,           NULL,
15369 /* C4 */        NULL,           NULL,           NULL,           NULL,
15370 /* C8 */        NULL,           NULL,           NULL,           NULL,
15371 /* CC */        NULL,           NULL,           NULL,           NULL,
15372 /* D0 */        NULL,           NULL,           NULL,           NULL,
15373 /* D4 */        NULL,           NULL,           NULL,           NULL,
15374 /* D8 */        NULL,           NULL,           NULL,           NULL,
15375 /* DC */        NULL,           NULL,           NULL,           NULL,
15376 /* E0 */        NULL,           NULL,           NULL,           NULL,
15377 /* E4 */        NULL,           NULL,           NULL,           NULL,
15378 /* E8 */        NULL,           NULL,           NULL,           NULL,
15379 /* EC */        NULL,           NULL,           NULL,           NULL,
15380 /* F0 */        NULL,           NULL,           NULL,           NULL,
15381 /* F4 */        NULL,           NULL,           NULL,           NULL,
15382 /* F8 */        NULL,           NULL,           NULL,           NULL,
15383 /* FC */        NULL,           NULL,           NULL,           NULL,
15384 };
15385
15386 static void
15387 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15388 {
15389   const char *mnemonic;
15390
15391   FETCH_DATA (the_info, codep + 1);
15392   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15393      place where an 8-bit immediate would normally go.  ie. the last
15394      byte of the instruction.  */
15395   obufp = mnemonicendp;
15396   mnemonic = Suffix3DNow[*codep++ & 0xff];
15397   if (mnemonic)
15398     oappend (mnemonic);
15399   else
15400     {
15401       /* Since a variable sized modrm/sib chunk is between the start
15402          of the opcode (0x0f0f) and the opcode suffix, we need to do
15403          all the modrm processing first, and don't know until now that
15404          we have a bad opcode.  This necessitates some cleaning up.  */
15405       op_out[0][0] = '\0';
15406       op_out[1][0] = '\0';
15407       BadOp ();
15408     }
15409   mnemonicendp = obufp;
15410 }
15411
15412 static struct op simd_cmp_op[] =
15413 {
15414   { STRING_COMMA_LEN ("eq") },
15415   { STRING_COMMA_LEN ("lt") },
15416   { STRING_COMMA_LEN ("le") },
15417   { STRING_COMMA_LEN ("unord") },
15418   { STRING_COMMA_LEN ("neq") },
15419   { STRING_COMMA_LEN ("nlt") },
15420   { STRING_COMMA_LEN ("nle") },
15421   { STRING_COMMA_LEN ("ord") }
15422 };
15423
15424 static void
15425 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15426 {
15427   unsigned int cmp_type;
15428
15429   FETCH_DATA (the_info, codep + 1);
15430   cmp_type = *codep++ & 0xff;
15431   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15432     {
15433       char suffix [3];
15434       char *p = mnemonicendp - 2;
15435       suffix[0] = p[0];
15436       suffix[1] = p[1];
15437       suffix[2] = '\0';
15438       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15439       mnemonicendp += simd_cmp_op[cmp_type].len;
15440     }
15441   else
15442     {
15443       /* We have a reserved extension byte.  Output it directly.  */
15444       scratchbuf[0] = '$';
15445       print_operand_value (scratchbuf + 1, 1, cmp_type);
15446       oappend_maybe_intel (scratchbuf);
15447       scratchbuf[0] = '\0';
15448     }
15449 }
15450
15451 static void
15452 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15453 {
15454   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15455   if (!intel_syntax)
15456     {
15457       strcpy (op_out[0], names32[0]);
15458       strcpy (op_out[1], names32[1]);
15459       if (bytemode == eBX_reg)
15460         strcpy (op_out[2], names32[3]);
15461       two_source_ops = 1;
15462     }
15463   /* Skip mod/rm byte.  */
15464   MODRM_CHECK;
15465   codep++;
15466 }
15467
15468 static void
15469 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15470             int sizeflag ATTRIBUTE_UNUSED)
15471 {
15472   /* monitor %{e,r,}ax,%ecx,%edx"  */
15473   if (!intel_syntax)
15474     {
15475       const char **names = (address_mode == mode_64bit
15476                             ? names64 : names32);
15477
15478       if (prefixes & PREFIX_ADDR)
15479         {
15480           /* Remove "addr16/addr32".  */
15481           all_prefixes[last_addr_prefix] = 0;
15482           names = (address_mode != mode_32bit
15483                    ? names32 : names16);
15484           used_prefixes |= PREFIX_ADDR;
15485         }
15486       else if (address_mode == mode_16bit)
15487         names = names16;
15488       strcpy (op_out[0], names[0]);
15489       strcpy (op_out[1], names32[1]);
15490       strcpy (op_out[2], names32[2]);
15491       two_source_ops = 1;
15492     }
15493   /* Skip mod/rm byte.  */
15494   MODRM_CHECK;
15495   codep++;
15496 }
15497
15498 static void
15499 BadOp (void)
15500 {
15501   /* Throw away prefixes and 1st. opcode byte.  */
15502   codep = insn_codep + 1;
15503   oappend ("(bad)");
15504 }
15505
15506 static void
15507 REP_Fixup (int bytemode, int sizeflag)
15508 {
15509   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15510      lods and stos.  */
15511   if (prefixes & PREFIX_REPZ)
15512     all_prefixes[last_repz_prefix] = REP_PREFIX;
15513
15514   switch (bytemode)
15515     {
15516     case al_reg:
15517     case eAX_reg:
15518     case indir_dx_reg:
15519       OP_IMREG (bytemode, sizeflag);
15520       break;
15521     case eDI_reg:
15522       OP_ESreg (bytemode, sizeflag);
15523       break;
15524     case eSI_reg:
15525       OP_DSreg (bytemode, sizeflag);
15526       break;
15527     default:
15528       abort ();
15529       break;
15530     }
15531 }
15532
15533 static void
15534 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15535 {
15536   if ( isa64 != amd64 )
15537     return;
15538
15539   obufp = obuf;
15540   BadOp ();
15541   mnemonicendp = obufp;
15542   ++codep;
15543 }
15544
15545 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15546    "bnd".  */
15547
15548 static void
15549 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15550 {
15551   if (prefixes & PREFIX_REPNZ)
15552     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15553 }
15554
15555 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15556    "notrack".  */
15557
15558 static void
15559 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15560                int sizeflag ATTRIBUTE_UNUSED)
15561 {
15562   if (active_seg_prefix == PREFIX_DS
15563       && (address_mode != mode_64bit || last_data_prefix < 0))
15564     {
15565       /* NOTRACK prefix is only valid on indirect branch instructions.
15566          NB: DATA prefix is unsupported for Intel64.  */
15567       active_seg_prefix = 0;
15568       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15569     }
15570 }
15571
15572 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15573    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15574  */
15575
15576 static void
15577 HLE_Fixup1 (int bytemode, int sizeflag)
15578 {
15579   if (modrm.mod != 3
15580       && (prefixes & PREFIX_LOCK) != 0)
15581     {
15582       if (prefixes & PREFIX_REPZ)
15583         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15584       if (prefixes & PREFIX_REPNZ)
15585         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15586     }
15587
15588   OP_E (bytemode, sizeflag);
15589 }
15590
15591 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15592    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15593  */
15594
15595 static void
15596 HLE_Fixup2 (int bytemode, int sizeflag)
15597 {
15598   if (modrm.mod != 3)
15599     {
15600       if (prefixes & PREFIX_REPZ)
15601         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15602       if (prefixes & PREFIX_REPNZ)
15603         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15604     }
15605
15606   OP_E (bytemode, sizeflag);
15607 }
15608
15609 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15610    "xrelease" for memory operand.  No check for LOCK prefix.   */
15611
15612 static void
15613 HLE_Fixup3 (int bytemode, int sizeflag)
15614 {
15615   if (modrm.mod != 3
15616       && last_repz_prefix > last_repnz_prefix
15617       && (prefixes & PREFIX_REPZ) != 0)
15618     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15619
15620   OP_E (bytemode, sizeflag);
15621 }
15622
15623 static void
15624 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15625 {
15626   USED_REX (REX_W);
15627   if (rex & REX_W)
15628     {
15629       /* Change cmpxchg8b to cmpxchg16b.  */
15630       char *p = mnemonicendp - 2;
15631       mnemonicendp = stpcpy (p, "16b");
15632       bytemode = o_mode;
15633     }
15634   else if ((prefixes & PREFIX_LOCK) != 0)
15635     {
15636       if (prefixes & PREFIX_REPZ)
15637         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15638       if (prefixes & PREFIX_REPNZ)
15639         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15640     }
15641
15642   OP_M (bytemode, sizeflag);
15643 }
15644
15645 static void
15646 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15647 {
15648   const char **names;
15649
15650   if (need_vex)
15651     {
15652       switch (vex.length)
15653         {
15654         case 128:
15655           names = names_xmm;
15656           break;
15657         case 256:
15658           names = names_ymm;
15659           break;
15660         default:
15661           abort ();
15662         }
15663     }
15664   else
15665     names = names_xmm;
15666   oappend (names[reg]);
15667 }
15668
15669 static void
15670 CRC32_Fixup (int bytemode, int sizeflag)
15671 {
15672   /* Add proper suffix to "crc32".  */
15673   char *p = mnemonicendp;
15674
15675   switch (bytemode)
15676     {
15677     case b_mode:
15678       if (intel_syntax)
15679         goto skip;
15680
15681       *p++ = 'b';
15682       break;
15683     case v_mode:
15684       if (intel_syntax)
15685         goto skip;
15686
15687       USED_REX (REX_W);
15688       if (rex & REX_W)
15689         *p++ = 'q';
15690       else
15691         {
15692           if (sizeflag & DFLAG)
15693             *p++ = 'l';
15694           else
15695             *p++ = 'w';
15696           used_prefixes |= (prefixes & PREFIX_DATA);
15697         }
15698       break;
15699     default:
15700       oappend (INTERNAL_DISASSEMBLER_ERROR);
15701       break;
15702     }
15703   mnemonicendp = p;
15704   *p = '\0';
15705
15706  skip:
15707   if (modrm.mod == 3)
15708     {
15709       int add;
15710
15711       /* Skip mod/rm byte.  */
15712       MODRM_CHECK;
15713       codep++;
15714
15715       USED_REX (REX_B);
15716       add = (rex & REX_B) ? 8 : 0;
15717       if (bytemode == b_mode)
15718         {
15719           USED_REX (0);
15720           if (rex)
15721             oappend (names8rex[modrm.rm + add]);
15722           else
15723             oappend (names8[modrm.rm + add]);
15724         }
15725       else
15726         {
15727           USED_REX (REX_W);
15728           if (rex & REX_W)
15729             oappend (names64[modrm.rm + add]);
15730           else if ((prefixes & PREFIX_DATA))
15731             oappend (names16[modrm.rm + add]);
15732           else
15733             oappend (names32[modrm.rm + add]);
15734         }
15735     }
15736   else
15737     OP_E (bytemode, sizeflag);
15738 }
15739
15740 static void
15741 FXSAVE_Fixup (int bytemode, int sizeflag)
15742 {
15743   /* Add proper suffix to "fxsave" and "fxrstor".  */
15744   USED_REX (REX_W);
15745   if (rex & REX_W)
15746     {
15747       char *p = mnemonicendp;
15748       *p++ = '6';
15749       *p++ = '4';
15750       *p = '\0';
15751       mnemonicendp = p;
15752     }
15753   OP_M (bytemode, sizeflag);
15754 }
15755
15756 static void
15757 PCMPESTR_Fixup (int bytemode, int sizeflag)
15758 {
15759   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15760   if (!intel_syntax)
15761     {
15762       char *p = mnemonicendp;
15763
15764       USED_REX (REX_W);
15765       if (rex & REX_W)
15766         *p++ = 'q';
15767       else if (sizeflag & SUFFIX_ALWAYS)
15768         *p++ = 'l';
15769
15770       *p = '\0';
15771       mnemonicendp = p;
15772     }
15773
15774   OP_EX (bytemode, sizeflag);
15775 }
15776
15777 /* Display the destination register operand for instructions with
15778    VEX. */
15779
15780 static void
15781 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15782 {
15783   int reg;
15784   const char **names;
15785
15786   if (!need_vex)
15787     abort ();
15788
15789   if (!need_vex_reg)
15790     return;
15791
15792   reg = vex.register_specifier;
15793   vex.register_specifier = 0;
15794   if (address_mode != mode_64bit)
15795     reg &= 7;
15796   else if (vex.evex && !vex.v)
15797     reg += 16;
15798
15799   if (bytemode == vex_scalar_mode)
15800     {
15801       oappend (names_xmm[reg]);
15802       return;
15803     }
15804
15805   switch (vex.length)
15806     {
15807     case 128:
15808       switch (bytemode)
15809         {
15810         case vex_mode:
15811         case vex128_mode:
15812         case vex_vsib_q_w_dq_mode:
15813         case vex_vsib_q_w_d_mode:
15814           names = names_xmm;
15815           break;
15816         case dq_mode:
15817           if (rex & REX_W)
15818             names = names64;
15819           else
15820             names = names32;
15821           break;
15822         case mask_bd_mode:
15823         case mask_mode:
15824           if (reg > 0x7)
15825             {
15826               oappend ("(bad)");
15827               return;
15828             }
15829           names = names_mask;
15830           break;
15831         default:
15832           abort ();
15833           return;
15834         }
15835       break;
15836     case 256:
15837       switch (bytemode)
15838         {
15839         case vex_mode:
15840         case vex256_mode:
15841           names = names_ymm;
15842           break;
15843         case vex_vsib_q_w_dq_mode:
15844         case vex_vsib_q_w_d_mode:
15845           names = vex.w ? names_ymm : names_xmm;
15846           break;
15847         case mask_bd_mode:
15848         case mask_mode:
15849           if (reg > 0x7)
15850             {
15851               oappend ("(bad)");
15852               return;
15853             }
15854           names = names_mask;
15855           break;
15856         default:
15857           /* See PR binutils/20893 for a reproducer.  */
15858           oappend ("(bad)");
15859           return;
15860         }
15861       break;
15862     case 512:
15863       names = names_zmm;
15864       break;
15865     default:
15866       abort ();
15867       break;
15868     }
15869   oappend (names[reg]);
15870 }
15871
15872 /* Get the VEX immediate byte without moving codep.  */
15873
15874 static unsigned char
15875 get_vex_imm8 (int sizeflag, int opnum)
15876 {
15877   int bytes_before_imm = 0;
15878
15879   if (modrm.mod != 3)
15880     {
15881       /* There are SIB/displacement bytes.  */
15882       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15883         {
15884           /* 32/64 bit address mode */
15885           int base = modrm.rm;
15886
15887           /* Check SIB byte.  */
15888           if (base == 4)
15889             {
15890               FETCH_DATA (the_info, codep + 1);
15891               base = *codep & 7;
15892               /* When decoding the third source, don't increase
15893                  bytes_before_imm as this has already been incremented
15894                  by one in OP_E_memory while decoding the second
15895                  source operand.  */
15896               if (opnum == 0)
15897                 bytes_before_imm++;
15898             }
15899
15900           /* Don't increase bytes_before_imm when decoding the third source,
15901              it has already been incremented by OP_E_memory while decoding
15902              the second source operand.  */
15903           if (opnum == 0)
15904             {
15905               switch (modrm.mod)
15906                 {
15907                   case 0:
15908                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
15909                        SIB == 5, there is a 4 byte displacement.  */
15910                     if (base != 5)
15911                       /* No displacement. */
15912                       break;
15913                     /* Fall through.  */
15914                   case 2:
15915                     /* 4 byte displacement.  */
15916                     bytes_before_imm += 4;
15917                     break;
15918                   case 1:
15919                     /* 1 byte displacement.  */
15920                     bytes_before_imm++;
15921                     break;
15922                 }
15923             }
15924         }
15925       else
15926         {
15927           /* 16 bit address mode */
15928           /* Don't increase bytes_before_imm when decoding the third source,
15929              it has already been incremented by OP_E_memory while decoding
15930              the second source operand.  */
15931           if (opnum == 0)
15932             {
15933               switch (modrm.mod)
15934                 {
15935                 case 0:
15936                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
15937                   if (modrm.rm != 6)
15938                     /* No displacement. */
15939                     break;
15940                   /* Fall through.  */
15941                 case 2:
15942                   /* 2 byte displacement.  */
15943                   bytes_before_imm += 2;
15944                   break;
15945                 case 1:
15946                   /* 1 byte displacement: when decoding the third source,
15947                      don't increase bytes_before_imm as this has already
15948                      been incremented by one in OP_E_memory while decoding
15949                      the second source operand.  */
15950                   if (opnum == 0)
15951                     bytes_before_imm++;
15952
15953                   break;
15954                 }
15955             }
15956         }
15957     }
15958
15959   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
15960   return codep [bytes_before_imm];
15961 }
15962
15963 static void
15964 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
15965 {
15966   const char **names;
15967
15968   if (reg == -1 && modrm.mod != 3)
15969     {
15970       OP_E_memory (bytemode, sizeflag);
15971       return;
15972     }
15973   else
15974     {
15975       if (reg == -1)
15976         {
15977           reg = modrm.rm;
15978           USED_REX (REX_B);
15979           if (rex & REX_B)
15980             reg += 8;
15981         }
15982       if (address_mode != mode_64bit)
15983         reg &= 7;
15984     }
15985
15986   switch (vex.length)
15987     {
15988     case 128:
15989       names = names_xmm;
15990       break;
15991     case 256:
15992       names = names_ymm;
15993       break;
15994     default:
15995       abort ();
15996     }
15997   oappend (names[reg]);
15998 }
15999
16000 static void
16001 OP_EX_VexImmW (int bytemode, int sizeflag)
16002 {
16003   int reg = -1;
16004   static unsigned char vex_imm8;
16005
16006   if (vex_w_done == 0)
16007     {
16008       vex_w_done = 1;
16009
16010       /* Skip mod/rm byte.  */
16011       MODRM_CHECK;
16012       codep++;
16013
16014       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16015
16016       if (vex.w)
16017           reg = vex_imm8 >> 4;
16018
16019       OP_EX_VexReg (bytemode, sizeflag, reg);
16020     }
16021   else if (vex_w_done == 1)
16022     {
16023       vex_w_done = 2;
16024
16025       if (!vex.w)
16026           reg = vex_imm8 >> 4;
16027
16028       OP_EX_VexReg (bytemode, sizeflag, reg);
16029     }
16030   else
16031     {
16032       /* Output the imm8 directly.  */
16033       scratchbuf[0] = '$';
16034       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16035       oappend_maybe_intel (scratchbuf);
16036       scratchbuf[0] = '\0';
16037       codep++;
16038     }
16039 }
16040
16041 static void
16042 OP_Vex_2src (int bytemode, int sizeflag)
16043 {
16044   if (modrm.mod == 3)
16045     {
16046       int reg = modrm.rm;
16047       USED_REX (REX_B);
16048       if (rex & REX_B)
16049         reg += 8;
16050       oappend (names_xmm[reg]);
16051     }
16052   else
16053     {
16054       if (intel_syntax
16055           && (bytemode == v_mode || bytemode == v_swap_mode))
16056         {
16057           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16058           used_prefixes |= (prefixes & PREFIX_DATA);
16059         }
16060       OP_E (bytemode, sizeflag);
16061     }
16062 }
16063
16064 static void
16065 OP_Vex_2src_1 (int bytemode, int sizeflag)
16066 {
16067   if (modrm.mod == 3)
16068     {
16069       /* Skip mod/rm byte.   */
16070       MODRM_CHECK;
16071       codep++;
16072     }
16073
16074   if (vex.w)
16075     {
16076       unsigned int reg = vex.register_specifier;
16077       vex.register_specifier = 0;
16078
16079       if (address_mode != mode_64bit)
16080         reg &= 7;
16081       oappend (names_xmm[reg]);
16082     }
16083   else
16084     OP_Vex_2src (bytemode, sizeflag);
16085 }
16086
16087 static void
16088 OP_Vex_2src_2 (int bytemode, int sizeflag)
16089 {
16090   if (vex.w)
16091     OP_Vex_2src (bytemode, sizeflag);
16092   else
16093     {
16094       unsigned int reg = vex.register_specifier;
16095       vex.register_specifier = 0;
16096
16097       if (address_mode != mode_64bit)
16098         reg &= 7;
16099       oappend (names_xmm[reg]);
16100     }
16101 }
16102
16103 static void
16104 OP_EX_VexW (int bytemode, int sizeflag)
16105 {
16106   int reg = -1;
16107
16108   if (!vex_w_done)
16109     {
16110       /* Skip mod/rm byte.  */
16111       MODRM_CHECK;
16112       codep++;
16113
16114       if (vex.w)
16115         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16116     }
16117   else
16118     {
16119       if (!vex.w)
16120         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16121     }
16122
16123   OP_EX_VexReg (bytemode, sizeflag, reg);
16124
16125   if (vex_w_done)
16126     codep++;
16127   vex_w_done = 1;
16128 }
16129
16130 static void
16131 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16132 {
16133   int reg;
16134   const char **names;
16135
16136   FETCH_DATA (the_info, codep + 1);
16137   reg = *codep++;
16138
16139   if (bytemode != x_mode)
16140     abort ();
16141
16142   reg >>= 4;
16143   if (address_mode != mode_64bit)
16144     reg &= 7;
16145
16146   switch (vex.length)
16147     {
16148     case 128:
16149       names = names_xmm;
16150       break;
16151     case 256:
16152       names = names_ymm;
16153       break;
16154     default:
16155       abort ();
16156     }
16157   oappend (names[reg]);
16158 }
16159
16160 static void
16161 OP_XMM_VexW (int bytemode, int sizeflag)
16162 {
16163   /* Turn off the REX.W bit since it is used for swapping operands
16164      now.  */
16165   rex &= ~REX_W;
16166   OP_XMM (bytemode, sizeflag);
16167 }
16168
16169 static void
16170 OP_EX_Vex (int bytemode, int sizeflag)
16171 {
16172   if (modrm.mod != 3)
16173     need_vex_reg = 0;
16174   OP_EX (bytemode, sizeflag);
16175 }
16176
16177 static void
16178 OP_XMM_Vex (int bytemode, int sizeflag)
16179 {
16180   if (modrm.mod != 3)
16181     need_vex_reg = 0;
16182   OP_XMM (bytemode, sizeflag);
16183 }
16184
16185 static struct op vex_cmp_op[] =
16186 {
16187   { STRING_COMMA_LEN ("eq") },
16188   { STRING_COMMA_LEN ("lt") },
16189   { STRING_COMMA_LEN ("le") },
16190   { STRING_COMMA_LEN ("unord") },
16191   { STRING_COMMA_LEN ("neq") },
16192   { STRING_COMMA_LEN ("nlt") },
16193   { STRING_COMMA_LEN ("nle") },
16194   { STRING_COMMA_LEN ("ord") },
16195   { STRING_COMMA_LEN ("eq_uq") },
16196   { STRING_COMMA_LEN ("nge") },
16197   { STRING_COMMA_LEN ("ngt") },
16198   { STRING_COMMA_LEN ("false") },
16199   { STRING_COMMA_LEN ("neq_oq") },
16200   { STRING_COMMA_LEN ("ge") },
16201   { STRING_COMMA_LEN ("gt") },
16202   { STRING_COMMA_LEN ("true") },
16203   { STRING_COMMA_LEN ("eq_os") },
16204   { STRING_COMMA_LEN ("lt_oq") },
16205   { STRING_COMMA_LEN ("le_oq") },
16206   { STRING_COMMA_LEN ("unord_s") },
16207   { STRING_COMMA_LEN ("neq_us") },
16208   { STRING_COMMA_LEN ("nlt_uq") },
16209   { STRING_COMMA_LEN ("nle_uq") },
16210   { STRING_COMMA_LEN ("ord_s") },
16211   { STRING_COMMA_LEN ("eq_us") },
16212   { STRING_COMMA_LEN ("nge_uq") },
16213   { STRING_COMMA_LEN ("ngt_uq") },
16214   { STRING_COMMA_LEN ("false_os") },
16215   { STRING_COMMA_LEN ("neq_os") },
16216   { STRING_COMMA_LEN ("ge_oq") },
16217   { STRING_COMMA_LEN ("gt_oq") },
16218   { STRING_COMMA_LEN ("true_us") },
16219 };
16220
16221 static void
16222 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16223 {
16224   unsigned int cmp_type;
16225
16226   FETCH_DATA (the_info, codep + 1);
16227   cmp_type = *codep++ & 0xff;
16228   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16229     {
16230       char suffix [3];
16231       char *p = mnemonicendp - 2;
16232       suffix[0] = p[0];
16233       suffix[1] = p[1];
16234       suffix[2] = '\0';
16235       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16236       mnemonicendp += vex_cmp_op[cmp_type].len;
16237     }
16238   else
16239     {
16240       /* We have a reserved extension byte.  Output it directly.  */
16241       scratchbuf[0] = '$';
16242       print_operand_value (scratchbuf + 1, 1, cmp_type);
16243       oappend_maybe_intel (scratchbuf);
16244       scratchbuf[0] = '\0';
16245     }
16246 }
16247
16248 static void
16249 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16250              int sizeflag ATTRIBUTE_UNUSED)
16251 {
16252   unsigned int cmp_type;
16253
16254   if (!vex.evex)
16255     abort ();
16256
16257   FETCH_DATA (the_info, codep + 1);
16258   cmp_type = *codep++ & 0xff;
16259   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16260      If it's the case, print suffix, otherwise - print the immediate.  */
16261   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16262       && cmp_type != 3
16263       && cmp_type != 7)
16264     {
16265       char suffix [3];
16266       char *p = mnemonicendp - 2;
16267
16268       /* vpcmp* can have both one- and two-lettered suffix.  */
16269       if (p[0] == 'p')
16270         {
16271           p++;
16272           suffix[0] = p[0];
16273           suffix[1] = '\0';
16274         }
16275       else
16276         {
16277           suffix[0] = p[0];
16278           suffix[1] = p[1];
16279           suffix[2] = '\0';
16280         }
16281
16282       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16283       mnemonicendp += simd_cmp_op[cmp_type].len;
16284     }
16285   else
16286     {
16287       /* We have a reserved extension byte.  Output it directly.  */
16288       scratchbuf[0] = '$';
16289       print_operand_value (scratchbuf + 1, 1, cmp_type);
16290       oappend_maybe_intel (scratchbuf);
16291       scratchbuf[0] = '\0';
16292     }
16293 }
16294
16295 static const struct op xop_cmp_op[] =
16296 {
16297   { STRING_COMMA_LEN ("lt") },
16298   { STRING_COMMA_LEN ("le") },
16299   { STRING_COMMA_LEN ("gt") },
16300   { STRING_COMMA_LEN ("ge") },
16301   { STRING_COMMA_LEN ("eq") },
16302   { STRING_COMMA_LEN ("neq") },
16303   { STRING_COMMA_LEN ("false") },
16304   { STRING_COMMA_LEN ("true") }
16305 };
16306
16307 static void
16308 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16309              int sizeflag ATTRIBUTE_UNUSED)
16310 {
16311   unsigned int cmp_type;
16312
16313   FETCH_DATA (the_info, codep + 1);
16314   cmp_type = *codep++ & 0xff;
16315   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16316     {
16317       char suffix[3];
16318       char *p = mnemonicendp - 2;
16319
16320       /* vpcom* can have both one- and two-lettered suffix.  */
16321       if (p[0] == 'm')
16322         {
16323           p++;
16324           suffix[0] = p[0];
16325           suffix[1] = '\0';
16326         }
16327       else
16328         {
16329           suffix[0] = p[0];
16330           suffix[1] = p[1];
16331           suffix[2] = '\0';
16332         }
16333
16334       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16335       mnemonicendp += xop_cmp_op[cmp_type].len;
16336     }
16337   else
16338     {
16339       /* We have a reserved extension byte.  Output it directly.  */
16340       scratchbuf[0] = '$';
16341       print_operand_value (scratchbuf + 1, 1, cmp_type);
16342       oappend_maybe_intel (scratchbuf);
16343       scratchbuf[0] = '\0';
16344     }
16345 }
16346
16347 static const struct op pclmul_op[] =
16348 {
16349   { STRING_COMMA_LEN ("lql") },
16350   { STRING_COMMA_LEN ("hql") },
16351   { STRING_COMMA_LEN ("lqh") },
16352   { STRING_COMMA_LEN ("hqh") }
16353 };
16354
16355 static void
16356 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16357               int sizeflag ATTRIBUTE_UNUSED)
16358 {
16359   unsigned int pclmul_type;
16360
16361   FETCH_DATA (the_info, codep + 1);
16362   pclmul_type = *codep++ & 0xff;
16363   switch (pclmul_type)
16364     {
16365     case 0x10:
16366       pclmul_type = 2;
16367       break;
16368     case 0x11:
16369       pclmul_type = 3;
16370       break;
16371     default:
16372       break;
16373     }
16374   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16375     {
16376       char suffix [4];
16377       char *p = mnemonicendp - 3;
16378       suffix[0] = p[0];
16379       suffix[1] = p[1];
16380       suffix[2] = p[2];
16381       suffix[3] = '\0';
16382       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16383       mnemonicendp += pclmul_op[pclmul_type].len;
16384     }
16385   else
16386     {
16387       /* We have a reserved extension byte.  Output it directly.  */
16388       scratchbuf[0] = '$';
16389       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16390       oappend_maybe_intel (scratchbuf);
16391       scratchbuf[0] = '\0';
16392     }
16393 }
16394
16395 static void
16396 MOVBE_Fixup (int bytemode, int sizeflag)
16397 {
16398   /* Add proper suffix to "movbe".  */
16399   char *p = mnemonicendp;
16400
16401   switch (bytemode)
16402     {
16403     case v_mode:
16404       if (intel_syntax)
16405         goto skip;
16406
16407       USED_REX (REX_W);
16408       if (sizeflag & SUFFIX_ALWAYS)
16409         {
16410           if (rex & REX_W)
16411             *p++ = 'q';
16412           else
16413             {
16414               if (sizeflag & DFLAG)
16415                 *p++ = 'l';
16416               else
16417                 *p++ = 'w';
16418               used_prefixes |= (prefixes & PREFIX_DATA);
16419             }
16420         }
16421       break;
16422     default:
16423       oappend (INTERNAL_DISASSEMBLER_ERROR);
16424       break;
16425     }
16426   mnemonicendp = p;
16427   *p = '\0';
16428
16429  skip:
16430   OP_M (bytemode, sizeflag);
16431 }
16432
16433 static void
16434 MOVSXD_Fixup (int bytemode, int sizeflag)
16435 {
16436   /* Add proper suffix to "movsxd".  */
16437   char *p = mnemonicendp;
16438
16439   switch (bytemode)
16440     {
16441     case movsxd_mode:
16442       if (intel_syntax)
16443         {
16444           *p++ = 'x';
16445           *p++ = 'd';
16446           goto skip;
16447         }
16448
16449       USED_REX (REX_W);
16450       if (rex & REX_W)
16451         {
16452           *p++ = 'l';
16453           *p++ = 'q';
16454         }
16455       else
16456         {
16457           *p++ = 'x';
16458           *p++ = 'd';
16459         }
16460       break;
16461     default:
16462       oappend (INTERNAL_DISASSEMBLER_ERROR);
16463       break;
16464     }
16465
16466  skip:
16467   mnemonicendp = p;
16468   *p = '\0';
16469   OP_E (bytemode, sizeflag);
16470 }
16471
16472 static void
16473 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16474 {
16475   int reg;
16476   const char **names;
16477
16478   /* Skip mod/rm byte.  */
16479   MODRM_CHECK;
16480   codep++;
16481
16482   if (rex & REX_W)
16483     names = names64;
16484   else
16485     names = names32;
16486
16487   reg = modrm.rm;
16488   USED_REX (REX_B);
16489   if (rex & REX_B)
16490     reg += 8;
16491
16492   oappend (names[reg]);
16493 }
16494
16495 static void
16496 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16497 {
16498   const char **names;
16499   unsigned int reg = vex.register_specifier;
16500   vex.register_specifier = 0;
16501
16502   if (rex & REX_W)
16503     names = names64;
16504   else
16505     names = names32;
16506
16507   if (address_mode != mode_64bit)
16508     reg &= 7;
16509   oappend (names[reg]);
16510 }
16511
16512 static void
16513 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16514 {
16515   if (!vex.evex
16516       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16517     abort ();
16518
16519   USED_REX (REX_R);
16520   if ((rex & REX_R) != 0 || !vex.r)
16521     {
16522       BadOp ();
16523       return;
16524     }
16525
16526   oappend (names_mask [modrm.reg]);
16527 }
16528
16529 static void
16530 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16531 {
16532   if (modrm.mod == 3 && vex.b)
16533     switch (bytemode)
16534       {
16535       case evex_rounding_64_mode:
16536         if (address_mode != mode_64bit)
16537           {
16538             oappend ("(bad)");
16539             break;
16540           }
16541         /* Fall through.  */
16542       case evex_rounding_mode:
16543         oappend (names_rounding[vex.ll]);
16544         break;
16545       case evex_sae_mode:
16546         oappend ("{sae}");
16547         break;
16548       default:
16549         abort ();
16550         break;
16551       }
16552 }