opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void BND_Fixup (int, int);
 111 static void NOTRACK_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void PCMPESTR_Fixup (int, int);
 120 static void OP_LWPCB_E (int, int);
 121 static void OP_LWP_E (int, int);
 122 static void OP_Vex_2src_1 (int, int);
 123 static void OP_Vex_2src_2 (int, int);
 124
 125 static void MOVBE_Fixup (int, int);
 126
 127 static void OP_Mask (int, int);
 128
 129 struct dis_private {
 130   /* Points to first byte not fetched.  */
 131   bfd_byte *max_fetched;
 132   bfd_byte the_buffer[MAX_MNEM_SIZE];
 133   bfd_vma insn_start;
 134   int orig_sizeflag;
 135   OPCODES_SIGJMP_BUF bailout;
 136 };
 137
 138 enum address_mode
 139 {
 140   mode_16bit,
 141   mode_32bit,
 142   mode_64bit
 143 };
 144
 145 enum address_mode address_mode;
 146
 147 /* Flags for the prefixes for the current instruction.  See below.  */
 148 static int prefixes;
 149
 150 /* REX prefix the current instruction.  See below.  */
 151 static int rex;
 152 /* Bits of REX we've already used.  */
 153 static int rex_used;
 154 /* REX bits in original REX prefix ignored.  */
 155 static int rex_ignored;
 156 /* Mark parts used in the REX prefix.  When we are testing for
 157    empty prefix (for 8bit register REX extension), just mask it
 158    out.  Otherwise test for REX bit is excuse for existence of REX
 159    only in case value is nonzero.  */
 160 #define USED_REX(value)                                 \
 161   {                                                     \
 162     if (value)                                          \
 163       {                                                 \
 164         if ((rex & value))                              \
 165           rex_used |= (value) | REX_OPCODE;             \
 166       }                                                 \
 167     else                                                \
 168       rex_used |= REX_OPCODE;                           \
 169   }
 170
 171 /* Flags for prefixes which we somehow handled when printing the
 172    current instruction.  */
 173 static int used_prefixes;
 174
 175 /* Flags stored in PREFIXES.  */
 176 #define PREFIX_REPZ 1
 177 #define PREFIX_REPNZ 2
 178 #define PREFIX_LOCK 4
 179 #define PREFIX_CS 8
 180 #define PREFIX_SS 0x10
 181 #define PREFIX_DS 0x20
 182 #define PREFIX_ES 0x40
 183 #define PREFIX_FS 0x80
 184 #define PREFIX_GS 0x100
 185 #define PREFIX_DATA 0x200
 186 #define PREFIX_ADDR 0x400
 187 #define PREFIX_FWAIT 0x800
 188
 189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 190    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 191    on error.  */
 192 #define FETCH_DATA(info, addr) \
 193   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 194    ? 1 : fetch_data ((info), (addr)))
 195
 196 static int
 197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 198 {
 199   int status;
 200   struct dis_private *priv = (struct dis_private *) info->private_data;
 201   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 202
 203   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 204     status = (*info->read_memory_func) (start,
 205                                         priv->max_fetched,
 206                                         addr - priv->max_fetched,
 207                                         info);
 208   else
 209     status = -1;
 210   if (status != 0)
 211     {
 212       /* If we did manage to read at least one byte, then
 213          print_insn_i386 will do something sensible.  Otherwise, print
 214          an error.  We do that here because this is where we know
 215          STATUS.  */
 216       if (priv->max_fetched == priv->the_buffer)
 217         (*info->memory_error_func) (status, start, info);
 218       OPCODES_SIGLONGJMP (priv->bailout, 1);
 219     }
 220   else
 221     priv->max_fetched = addr;
 222   return 1;
 223 }
 224
 225 /* Possible values for prefix requirement.  */
 226 #define PREFIX_IGNORED_SHIFT    16
 227 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 232
 233 /* Opcode prefixes.  */
 234 #define PREFIX_OPCODE           (PREFIX_REPZ \
 235                                  | PREFIX_REPNZ \
 236                                  | PREFIX_DATA)
 237
 238 /* Prefixes ignored.  */
 239 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 240                                  | PREFIX_IGNORED_REPNZ \
 241                                  | PREFIX_IGNORED_DATA)
 242
 243 #define XX { NULL, 0 }
 244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 245
 246 #define Eb { OP_E, b_mode }
 247 #define Ebnd { OP_E, bnd_mode }
 248 #define EbS { OP_E, b_swap_mode }
 249 #define EbndS { OP_E, bnd_swap_mode }
 250 #define Ev { OP_E, v_mode }
 251 #define Eva { OP_E, va_mode }
 252 #define Ev_bnd { OP_E, v_bnd_mode }
 253 #define EvS { OP_E, v_swap_mode }
 254 #define Ed { OP_E, d_mode }
 255 #define Edq { OP_E, dq_mode }
 256 #define Edqw { OP_E, dqw_mode }
 257 #define Edqb { OP_E, dqb_mode }
 258 #define Edb { OP_E, db_mode }
 259 #define Edw { OP_E, dw_mode }
 260 #define Edqd { OP_E, dqd_mode }
 261 #define Eq { OP_E, q_mode }
 262 #define indirEv { OP_indirE, indir_v_mode }
 263 #define indirEp { OP_indirE, f_mode }
 264 #define stackEv { OP_E, stack_v_mode }
 265 #define Em { OP_E, m_mode }
 266 #define Ew { OP_E, w_mode }
 267 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 268 #define Ma { OP_M, a_mode }
 269 #define Mb { OP_M, b_mode }
 270 #define Md { OP_M, d_mode }
 271 #define Mo { OP_M, o_mode }
 272 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 273 #define Mq { OP_M, q_mode }
 274 #define Mv_bnd { OP_M, v_bndmk_mode }
 275 #define Mx { OP_M, x_mode }
 276 #define Mxmm { OP_M, xmm_mode }
 277 #define Gb { OP_G, b_mode }
 278 #define Gbnd { OP_G, bnd_mode }
 279 #define Gv { OP_G, v_mode }
 280 #define Gd { OP_G, d_mode }
 281 #define Gdq { OP_G, dq_mode }
 282 #define Gm { OP_G, m_mode }
 283 #define Gva { OP_G, va_mode }
 284 #define Gw { OP_G, w_mode }
 285 #define Rd { OP_R, d_mode }
 286 #define Rdq { OP_R, dq_mode }
 287 #define Rm { OP_R, m_mode }
 288 #define Ib { OP_I, b_mode }
 289 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 290 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 291 #define Iv { OP_I, v_mode }
 292 #define sIv { OP_sI, v_mode }
 293 #define Iv64 { OP_I64, v_mode }
 294 #define Id { OP_I, d_mode }
 295 #define Iw { OP_I, w_mode }
 296 #define I1 { OP_I, const_1_mode }
 297 #define Jb { OP_J, b_mode }
 298 #define Jv { OP_J, v_mode }
 299 #define Jdqw { OP_J, dqw_mode }
 300 #define Cm { OP_C, m_mode }
 301 #define Dm { OP_D, m_mode }
 302 #define Td { OP_T, d_mode }
 303 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 304
 305 #define RMeAX { OP_REG, eAX_reg }
 306 #define RMeBX { OP_REG, eBX_reg }
 307 #define RMeCX { OP_REG, eCX_reg }
 308 #define RMeDX { OP_REG, eDX_reg }
 309 #define RMeSP { OP_REG, eSP_reg }
 310 #define RMeBP { OP_REG, eBP_reg }
 311 #define RMeSI { OP_REG, eSI_reg }
 312 #define RMeDI { OP_REG, eDI_reg }
 313 #define RMrAX { OP_REG, rAX_reg }
 314 #define RMrBX { OP_REG, rBX_reg }
 315 #define RMrCX { OP_REG, rCX_reg }
 316 #define RMrDX { OP_REG, rDX_reg }
 317 #define RMrSP { OP_REG, rSP_reg }
 318 #define RMrBP { OP_REG, rBP_reg }
 319 #define RMrSI { OP_REG, rSI_reg }
 320 #define RMrDI { OP_REG, rDI_reg }
 321 #define RMAL { OP_REG, al_reg }
 322 #define RMCL { OP_REG, cl_reg }
 323 #define RMDL { OP_REG, dl_reg }
 324 #define RMBL { OP_REG, bl_reg }
 325 #define RMAH { OP_REG, ah_reg }
 326 #define RMCH { OP_REG, ch_reg }
 327 #define RMDH { OP_REG, dh_reg }
 328 #define RMBH { OP_REG, bh_reg }
 329 #define RMAX { OP_REG, ax_reg }
 330 #define RMDX { OP_REG, dx_reg }
 331
 332 #define eAX { OP_IMREG, eAX_reg }
 333 #define eBX { OP_IMREG, eBX_reg }
 334 #define eCX { OP_IMREG, eCX_reg }
 335 #define eDX { OP_IMREG, eDX_reg }
 336 #define eSP { OP_IMREG, eSP_reg }
 337 #define eBP { OP_IMREG, eBP_reg }
 338 #define eSI { OP_IMREG, eSI_reg }
 339 #define eDI { OP_IMREG, eDI_reg }
 340 #define AL { OP_IMREG, al_reg }
 341 #define CL { OP_IMREG, cl_reg }
 342 #define DL { OP_IMREG, dl_reg }
 343 #define BL { OP_IMREG, bl_reg }
 344 #define AH { OP_IMREG, ah_reg }
 345 #define CH { OP_IMREG, ch_reg }
 346 #define DH { OP_IMREG, dh_reg }
 347 #define BH { OP_IMREG, bh_reg }
 348 #define AX { OP_IMREG, ax_reg }
 349 #define DX { OP_IMREG, dx_reg }
 350 #define zAX { OP_IMREG, z_mode_ax_reg }
 351 #define indirDX { OP_IMREG, indir_dx_reg }
 352
 353 #define Sw { OP_SEG, w_mode }
 354 #define Sv { OP_SEG, v_mode }
 355 #define Ap { OP_DIR, 0 }
 356 #define Ob { OP_OFF64, b_mode }
 357 #define Ov { OP_OFF64, v_mode }
 358 #define Xb { OP_DSreg, eSI_reg }
 359 #define Xv { OP_DSreg, eSI_reg }
 360 #define Xz { OP_DSreg, eSI_reg }
 361 #define Yb { OP_ESreg, eDI_reg }
 362 #define Yv { OP_ESreg, eDI_reg }
 363 #define DSBX { OP_DSreg, eBX_reg }
 364
 365 #define es { OP_REG, es_reg }
 366 #define ss { OP_REG, ss_reg }
 367 #define cs { OP_REG, cs_reg }
 368 #define ds { OP_REG, ds_reg }
 369 #define fs { OP_REG, fs_reg }
 370 #define gs { OP_REG, gs_reg }
 371
 372 #define MX { OP_MMX, 0 }
 373 #define XM { OP_XMM, 0 }
 374 #define XMScalar { OP_XMM, scalar_mode }
 375 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 376 #define XMM { OP_XMM, xmm_mode }
 377 #define XMxmmq { OP_XMM, xmmq_mode }
 378 #define EM { OP_EM, v_mode }
 379 #define EMS { OP_EM, v_swap_mode }
 380 #define EMd { OP_EM, d_mode }
 381 #define EMx { OP_EM, x_mode }
 382 #define EXbScalar { OP_EX, b_scalar_mode }
 383 #define EXw { OP_EX, w_mode }
 384 #define EXwScalar { OP_EX, w_scalar_mode }
 385 #define EXd { OP_EX, d_mode }
 386 #define EXdScalar { OP_EX, d_scalar_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXq { OP_EX, q_mode }
 389 #define EXqScalar { OP_EX, q_scalar_mode }
 390 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 391 #define EXqS { OP_EX, q_swap_mode }
 392 #define EXx { OP_EX, x_mode }
 393 #define EXxS { OP_EX, x_swap_mode }
 394 #define EXxmm { OP_EX, xmm_mode }
 395 #define EXymm { OP_EX, ymm_mode }
 396 #define EXxmmq { OP_EX, xmmq_mode }
 397 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 398 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 399 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 400 #define EXxmm_md { OP_EX, xmm_md_mode }
 401 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 402 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 403 #define EXxmmdw { OP_EX, xmmdw_mode }
 404 #define EXxmmqd { OP_EX, xmmqd_mode }
 405 #define EXymmq { OP_EX, ymmq_mode }
 406 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 410 #define MS { OP_MS, v_mode }
 411 #define XS { OP_XS, v_mode }
 412 #define EMCq { OP_EMC, q_mode }
 413 #define MXC { OP_MXC, 0 }
 414 #define OPSUF { OP_3DNowSuffix, 0 }
 415 #define CMP { CMP_Fixup, 0 }
 416 #define XMM0 { XMM_Fixup, 0 }
 417 #define FXSAVE { FXSAVE_Fixup, 0 }
 418 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 419 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 420
 421 #define Vex { OP_VEX, vex_mode }
 422 #define VexScalar { OP_VEX, vex_scalar_mode }
 423 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 424 #define Vex128 { OP_VEX, vex128_mode }
 425 #define Vex256 { OP_VEX, vex256_mode }
 426 #define VexGdq { OP_VEX, dq_mode }
 427 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 429 #define EXVexW { OP_EX_VexW, x_mode }
 430 #define EXdVexW { OP_EX_VexW, d_mode }
 431 #define EXqVexW { OP_EX_VexW, q_mode }
 432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 433 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 434 #define XMVexW { OP_XMM_VexW, 0 }
 435 #define XMVexI4 { OP_REG_VexI4, x_mode }
 436 #define PCLMUL { PCLMUL_Fixup, 0 }
 437 #define VCMP { VCMP_Fixup, 0 }
 438 #define VPCMP { VPCMP_Fixup, 0 }
 439 #define VPCOM { VPCOM_Fixup, 0 }
 440
 441 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 442 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 444
 445 #define XMask { OP_Mask, mask_mode }
 446 #define MaskG { OP_G, mask_mode }
 447 #define MaskE { OP_E, mask_mode }
 448 #define MaskBDE { OP_E, mask_bd_mode }
 449 #define MaskR { OP_R, mask_mode }
 450 #define MaskVex { OP_VEX, mask_mode }
 451
 452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 456
 457 /* Used handle "rep" prefix for string instructions.  */
 458 #define Xbr { REP_Fixup, eSI_reg }
 459 #define Xvr { REP_Fixup, eSI_reg }
 460 #define Ybr { REP_Fixup, eDI_reg }
 461 #define Yvr { REP_Fixup, eDI_reg }
 462 #define Yzr { REP_Fixup, eDI_reg }
 463 #define indirDXr { REP_Fixup, indir_dx_reg }
 464 #define ALr { REP_Fixup, al_reg }
 465 #define eAXr { REP_Fixup, eAX_reg }
 466
 467 /* Used handle HLE prefix for lockable instructions.  */
 468 #define Ebh1 { HLE_Fixup1, b_mode }
 469 #define Evh1 { HLE_Fixup1, v_mode }
 470 #define Ebh2 { HLE_Fixup2, b_mode }
 471 #define Evh2 { HLE_Fixup2, v_mode }
 472 #define Ebh3 { HLE_Fixup3, b_mode }
 473 #define Evh3 { HLE_Fixup3, v_mode }
 474
 475 #define BND { BND_Fixup, 0 }
 476 #define NOTRACK { NOTRACK_Fixup, 0 }
 477
 478 #define cond_jump_flag { NULL, cond_jump_mode }
 479 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 480
 481 /* bits in sizeflag */
 482 #define SUFFIX_ALWAYS 4
 483 #define AFLAG 2
 484 #define DFLAG 1
 485
 486 enum
 487 {
 488   /* byte operand */
 489   b_mode = 1,
 490   /* byte operand with operand swapped */
 491   b_swap_mode,
 492   /* byte operand, sign extend like 'T' suffix */
 493   b_T_mode,
 494   /* operand size depends on prefixes */
 495   v_mode,
 496   /* operand size depends on prefixes with operand swapped */
 497   v_swap_mode,
 498   /* operand size depends on address prefix */
 499   va_mode,
 500   /* word operand */
 501   w_mode,
 502   /* double word operand  */
 503   d_mode,
 504   /* double word operand with operand swapped */
 505   d_swap_mode,
 506   /* quad word operand */
 507   q_mode,
 508   /* quad word operand with operand swapped */
 509   q_swap_mode,
 510   /* ten-byte operand */
 511   t_mode,
 512   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 513      broadcast enabled.  */
 514   x_mode,
 515   /* Similar to x_mode, but with different EVEX mem shifts.  */
 516   evex_x_gscat_mode,
 517   /* Similar to x_mode, but with disabled broadcast.  */
 518   evex_x_nobcst_mode,
 519   /* Similar to x_mode, but with operands swapped and disabled broadcast
 520      in EVEX.  */
 521   x_swap_mode,
 522   /* 16-byte XMM operand */
 523   xmm_mode,
 524   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 525      memory operand (depending on vector length).  Broadcast isn't
 526      allowed.  */
 527   xmmq_mode,
 528   /* Same as xmmq_mode, but broadcast is allowed.  */
 529   evex_half_bcst_xmmq_mode,
 530   /* XMM register or byte memory operand */
 531   xmm_mb_mode,
 532   /* XMM register or word memory operand */
 533   xmm_mw_mode,
 534   /* XMM register or double word memory operand */
 535   xmm_md_mode,
 536   /* XMM register or quad word memory operand */
 537   xmm_mq_mode,
 538   /* XMM register or double/quad word memory operand, depending on
 539      VEX.W.  */
 540   xmm_mdq_mode,
 541   /* 16-byte XMM, word, double word or quad word operand.  */
 542   xmmdw_mode,
 543   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 544   xmmqd_mode,
 545   /* 32-byte YMM operand */
 546   ymm_mode,
 547   /* quad word, ymmword or zmmword memory operand.  */
 548   ymmq_mode,
 549   /* 32-byte YMM or 16-byte word operand */
 550   ymmxmm_mode,
 551   /* d_mode in 32bit, q_mode in 64bit mode.  */
 552   m_mode,
 553   /* pair of v_mode operands */
 554   a_mode,
 555   cond_jump_mode,
 556   loop_jcxz_mode,
 557   v_bnd_mode,
 558   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 559   v_bndmk_mode,
 560   /* operand size depends on REX prefixes.  */
 561   dq_mode,
 562   /* registers like dq_mode, memory like w_mode, displacements like
 563      v_mode without considering Intel64 ISA.  */
 564   dqw_mode,
 565   /* bounds operand */
 566   bnd_mode,
 567   /* bounds operand with operand swapped */
 568   bnd_swap_mode,
 569   /* 4- or 6-byte pointer operand */
 570   f_mode,
 571   const_1_mode,
 572   /* v_mode for indirect branch opcodes.  */
 573   indir_v_mode,
 574   /* v_mode for stack-related opcodes.  */
 575   stack_v_mode,
 576   /* non-quad operand size depends on prefixes */
 577   z_mode,
 578   /* 16-byte operand */
 579   o_mode,
 580   /* registers like dq_mode, memory like b_mode.  */
 581   dqb_mode,
 582   /* registers like d_mode, memory like b_mode.  */
 583   db_mode,
 584   /* registers like d_mode, memory like w_mode.  */
 585   dw_mode,
 586   /* registers like dq_mode, memory like d_mode.  */
 587   dqd_mode,
 588   /* normal vex mode */
 589   vex_mode,
 590   /* 128bit vex mode */
 591   vex128_mode,
 592   /* 256bit vex mode */
 593   vex256_mode,
 594   /* operand size depends on the VEX.W bit.  */
 595   vex_w_dq_mode,
 596
 597   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 598   vex_vsib_d_w_dq_mode,
 599   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 600   vex_vsib_d_w_d_mode,
 601   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 602   vex_vsib_q_w_dq_mode,
 603   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 604   vex_vsib_q_w_d_mode,
 605
 606   /* scalar, ignore vector length.  */
 607   scalar_mode,
 608   /* like b_mode, ignore vector length.  */
 609   b_scalar_mode,
 610   /* like w_mode, ignore vector length.  */
 611   w_scalar_mode,
 612   /* like d_mode, ignore vector length.  */
 613   d_scalar_mode,
 614   /* like d_swap_mode, ignore vector length.  */
 615   d_scalar_swap_mode,
 616   /* like q_mode, ignore vector length.  */
 617   q_scalar_mode,
 618   /* like q_swap_mode, ignore vector length.  */
 619   q_scalar_swap_mode,
 620   /* like vex_mode, ignore vector length.  */
 621   vex_scalar_mode,
 622   /* like vex_w_dq_mode, ignore vector length.  */
 623   vex_scalar_w_dq_mode,
 624
 625   /* Static rounding.  */
 626   evex_rounding_mode,
 627   /* Static rounding, 64-bit mode only.  */
 628   evex_rounding_64_mode,
 629   /* Supress all exceptions.  */
 630   evex_sae_mode,
 631
 632   /* Mask register operand.  */
 633   mask_mode,
 634   /* Mask register operand.  */
 635   mask_bd_mode,
 636
 637   es_reg,
 638   cs_reg,
 639   ss_reg,
 640   ds_reg,
 641   fs_reg,
 642   gs_reg,
 643
 644   eAX_reg,
 645   eCX_reg,
 646   eDX_reg,
 647   eBX_reg,
 648   eSP_reg,
 649   eBP_reg,
 650   eSI_reg,
 651   eDI_reg,
 652
 653   al_reg,
 654   cl_reg,
 655   dl_reg,
 656   bl_reg,
 657   ah_reg,
 658   ch_reg,
 659   dh_reg,
 660   bh_reg,
 661
 662   ax_reg,
 663   cx_reg,
 664   dx_reg,
 665   bx_reg,
 666   sp_reg,
 667   bp_reg,
 668   si_reg,
 669   di_reg,
 670
 671   rAX_reg,
 672   rCX_reg,
 673   rDX_reg,
 674   rBX_reg,
 675   rSP_reg,
 676   rBP_reg,
 677   rSI_reg,
 678   rDI_reg,
 679
 680   z_mode_ax_reg,
 681   indir_dx_reg
 682 };
 683
 684 enum
 685 {
 686   FLOATCODE = 1,
 687   USE_REG_TABLE,
 688   USE_MOD_TABLE,
 689   USE_RM_TABLE,
 690   USE_PREFIX_TABLE,
 691   USE_X86_64_TABLE,
 692   USE_3BYTE_TABLE,
 693   USE_XOP_8F_TABLE,
 694   USE_VEX_C4_TABLE,
 695   USE_VEX_C5_TABLE,
 696   USE_VEX_LEN_TABLE,
 697   USE_VEX_W_TABLE,
 698   USE_EVEX_TABLE,
 699   USE_EVEX_LEN_TABLE
 700 };
 701
 702 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 703
 704 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 705 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 706 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 707 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 708 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 709 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 710 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 711 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 712 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 713 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 714 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 715 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 716 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 717 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 718 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 719 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 720
 721 enum
 722 {
 723   REG_80 = 0,
 724   REG_81,
 725   REG_83,
 726   REG_8F,
 727   REG_C0,
 728   REG_C1,
 729   REG_C6,
 730   REG_C7,
 731   REG_D0,
 732   REG_D1,
 733   REG_D2,
 734   REG_D3,
 735   REG_F6,
 736   REG_F7,
 737   REG_FE,
 738   REG_FF,
 739   REG_0F00,
 740   REG_0F01,
 741   REG_0F0D,
 742   REG_0F18,
 743   REG_0F1C_P_0_MOD_0,
 744   REG_0F1E_P_1_MOD_3,
 745   REG_0F71,
 746   REG_0F72,
 747   REG_0F73,
 748   REG_0FA6,
 749   REG_0FA7,
 750   REG_0FAE,
 751   REG_0FBA,
 752   REG_0FC7,
 753   REG_VEX_0F71,
 754   REG_VEX_0F72,
 755   REG_VEX_0F73,
 756   REG_VEX_0FAE,
 757   REG_VEX_0F38F3,
 758   REG_XOP_LWPCB,
 759   REG_XOP_LWP,
 760   REG_XOP_TBM_01,
 761   REG_XOP_TBM_02,
 762
 763   REG_EVEX_0F71,
 764   REG_EVEX_0F72,
 765   REG_EVEX_0F73,
 766   REG_EVEX_0F38C6,
 767   REG_EVEX_0F38C7
 768 };
 769
 770 enum
 771 {
 772   MOD_8D = 0,
 773   MOD_C6_REG_7,
 774   MOD_C7_REG_7,
 775   MOD_FF_REG_3,
 776   MOD_FF_REG_5,
 777   MOD_0F01_REG_0,
 778   MOD_0F01_REG_1,
 779   MOD_0F01_REG_2,
 780   MOD_0F01_REG_3,
 781   MOD_0F01_REG_5,
 782   MOD_0F01_REG_7,
 783   MOD_0F12_PREFIX_0,
 784   MOD_0F13,
 785   MOD_0F16_PREFIX_0,
 786   MOD_0F17,
 787   MOD_0F18_REG_0,
 788   MOD_0F18_REG_1,
 789   MOD_0F18_REG_2,
 790   MOD_0F18_REG_3,
 791   MOD_0F18_REG_4,
 792   MOD_0F18_REG_5,
 793   MOD_0F18_REG_6,
 794   MOD_0F18_REG_7,
 795   MOD_0F1A_PREFIX_0,
 796   MOD_0F1B_PREFIX_0,
 797   MOD_0F1B_PREFIX_1,
 798   MOD_0F1C_PREFIX_0,
 799   MOD_0F1E_PREFIX_1,
 800   MOD_0F24,
 801   MOD_0F26,
 802   MOD_0F2B_PREFIX_0,
 803   MOD_0F2B_PREFIX_1,
 804   MOD_0F2B_PREFIX_2,
 805   MOD_0F2B_PREFIX_3,
 806   MOD_0F51,
 807   MOD_0F71_REG_2,
 808   MOD_0F71_REG_4,
 809   MOD_0F71_REG_6,
 810   MOD_0F72_REG_2,
 811   MOD_0F72_REG_4,
 812   MOD_0F72_REG_6,
 813   MOD_0F73_REG_2,
 814   MOD_0F73_REG_3,
 815   MOD_0F73_REG_6,
 816   MOD_0F73_REG_7,
 817   MOD_0FAE_REG_0,
 818   MOD_0FAE_REG_1,
 819   MOD_0FAE_REG_2,
 820   MOD_0FAE_REG_3,
 821   MOD_0FAE_REG_4,
 822   MOD_0FAE_REG_5,
 823   MOD_0FAE_REG_6,
 824   MOD_0FAE_REG_7,
 825   MOD_0FB2,
 826   MOD_0FB4,
 827   MOD_0FB5,
 828   MOD_0FC3,
 829   MOD_0FC7_REG_3,
 830   MOD_0FC7_REG_4,
 831   MOD_0FC7_REG_5,
 832   MOD_0FC7_REG_6,
 833   MOD_0FC7_REG_7,
 834   MOD_0FD7,
 835   MOD_0FE7_PREFIX_2,
 836   MOD_0FF0_PREFIX_3,
 837   MOD_0F382A_PREFIX_2,
 838   MOD_0F38F5_PREFIX_2,
 839   MOD_0F38F6_PREFIX_0,
 840   MOD_0F38F8_PREFIX_1,
 841   MOD_0F38F8_PREFIX_2,
 842   MOD_0F38F8_PREFIX_3,
 843   MOD_0F38F9_PREFIX_0,
 844   MOD_62_32BIT,
 845   MOD_C4_32BIT,
 846   MOD_C5_32BIT,
 847   MOD_VEX_0F12_PREFIX_0,
 848   MOD_VEX_0F13,
 849   MOD_VEX_0F16_PREFIX_0,
 850   MOD_VEX_0F17,
 851   MOD_VEX_0F2B,
 852   MOD_VEX_W_0_0F41_P_0_LEN_1,
 853   MOD_VEX_W_1_0F41_P_0_LEN_1,
 854   MOD_VEX_W_0_0F41_P_2_LEN_1,
 855   MOD_VEX_W_1_0F41_P_2_LEN_1,
 856   MOD_VEX_W_0_0F42_P_0_LEN_1,
 857   MOD_VEX_W_1_0F42_P_0_LEN_1,
 858   MOD_VEX_W_0_0F42_P_2_LEN_1,
 859   MOD_VEX_W_1_0F42_P_2_LEN_1,
 860   MOD_VEX_W_0_0F44_P_0_LEN_1,
 861   MOD_VEX_W_1_0F44_P_0_LEN_1,
 862   MOD_VEX_W_0_0F44_P_2_LEN_1,
 863   MOD_VEX_W_1_0F44_P_2_LEN_1,
 864   MOD_VEX_W_0_0F45_P_0_LEN_1,
 865   MOD_VEX_W_1_0F45_P_0_LEN_1,
 866   MOD_VEX_W_0_0F45_P_2_LEN_1,
 867   MOD_VEX_W_1_0F45_P_2_LEN_1,
 868   MOD_VEX_W_0_0F46_P_0_LEN_1,
 869   MOD_VEX_W_1_0F46_P_0_LEN_1,
 870   MOD_VEX_W_0_0F46_P_2_LEN_1,
 871   MOD_VEX_W_1_0F46_P_2_LEN_1,
 872   MOD_VEX_W_0_0F47_P_0_LEN_1,
 873   MOD_VEX_W_1_0F47_P_0_LEN_1,
 874   MOD_VEX_W_0_0F47_P_2_LEN_1,
 875   MOD_VEX_W_1_0F47_P_2_LEN_1,
 876   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 877   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 878   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 879   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 880   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 881   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 882   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 883   MOD_VEX_0F50,
 884   MOD_VEX_0F71_REG_2,
 885   MOD_VEX_0F71_REG_4,
 886   MOD_VEX_0F71_REG_6,
 887   MOD_VEX_0F72_REG_2,
 888   MOD_VEX_0F72_REG_4,
 889   MOD_VEX_0F72_REG_6,
 890   MOD_VEX_0F73_REG_2,
 891   MOD_VEX_0F73_REG_3,
 892   MOD_VEX_0F73_REG_6,
 893   MOD_VEX_0F73_REG_7,
 894   MOD_VEX_W_0_0F91_P_0_LEN_0,
 895   MOD_VEX_W_1_0F91_P_0_LEN_0,
 896   MOD_VEX_W_0_0F91_P_2_LEN_0,
 897   MOD_VEX_W_1_0F91_P_2_LEN_0,
 898   MOD_VEX_W_0_0F92_P_0_LEN_0,
 899   MOD_VEX_W_0_0F92_P_2_LEN_0,
 900   MOD_VEX_0F92_P_3_LEN_0,
 901   MOD_VEX_W_0_0F93_P_0_LEN_0,
 902   MOD_VEX_W_0_0F93_P_2_LEN_0,
 903   MOD_VEX_0F93_P_3_LEN_0,
 904   MOD_VEX_W_0_0F98_P_0_LEN_0,
 905   MOD_VEX_W_1_0F98_P_0_LEN_0,
 906   MOD_VEX_W_0_0F98_P_2_LEN_0,
 907   MOD_VEX_W_1_0F98_P_2_LEN_0,
 908   MOD_VEX_W_0_0F99_P_0_LEN_0,
 909   MOD_VEX_W_1_0F99_P_0_LEN_0,
 910   MOD_VEX_W_0_0F99_P_2_LEN_0,
 911   MOD_VEX_W_1_0F99_P_2_LEN_0,
 912   MOD_VEX_0FAE_REG_2,
 913   MOD_VEX_0FAE_REG_3,
 914   MOD_VEX_0FD7_PREFIX_2,
 915   MOD_VEX_0FE7_PREFIX_2,
 916   MOD_VEX_0FF0_PREFIX_3,
 917   MOD_VEX_0F381A_PREFIX_2,
 918   MOD_VEX_0F382A_PREFIX_2,
 919   MOD_VEX_0F382C_PREFIX_2,
 920   MOD_VEX_0F382D_PREFIX_2,
 921   MOD_VEX_0F382E_PREFIX_2,
 922   MOD_VEX_0F382F_PREFIX_2,
 923   MOD_VEX_0F385A_PREFIX_2,
 924   MOD_VEX_0F388C_PREFIX_2,
 925   MOD_VEX_0F388E_PREFIX_2,
 926   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 927   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 928   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 929   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 930   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 931   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 932   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 933   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 934
 935   MOD_EVEX_0F12_PREFIX_0,
 936   MOD_EVEX_0F16_PREFIX_0,
 937   MOD_EVEX_0F38C6_REG_1,
 938   MOD_EVEX_0F38C6_REG_2,
 939   MOD_EVEX_0F38C6_REG_5,
 940   MOD_EVEX_0F38C6_REG_6,
 941   MOD_EVEX_0F38C7_REG_1,
 942   MOD_EVEX_0F38C7_REG_2,
 943   MOD_EVEX_0F38C7_REG_5,
 944   MOD_EVEX_0F38C7_REG_6
 945 };
 946
 947 enum
 948 {
 949   RM_C6_REG_7 = 0,
 950   RM_C7_REG_7,
 951   RM_0F01_REG_0,
 952   RM_0F01_REG_1,
 953   RM_0F01_REG_2,
 954   RM_0F01_REG_3,
 955   RM_0F01_REG_5_MOD_3,
 956   RM_0F01_REG_7_MOD_3,
 957   RM_0F1E_P_1_MOD_3_REG_7,
 958   RM_0FAE_REG_6_MOD_3_P_0,
 959   RM_0FAE_REG_7_MOD_3,
 960 };
 961
 962 enum
 963 {
 964   PREFIX_90 = 0,
 965   PREFIX_0F01_REG_5_MOD_0,
 966   PREFIX_0F01_REG_5_MOD_3_RM_0,
 967   PREFIX_0F01_REG_5_MOD_3_RM_2,
 968   PREFIX_0F01_REG_7_MOD_3_RM_2,
 969   PREFIX_0F01_REG_7_MOD_3_RM_3,
 970   PREFIX_0F09,
 971   PREFIX_0F10,
 972   PREFIX_0F11,
 973   PREFIX_0F12,
 974   PREFIX_0F16,
 975   PREFIX_0F1A,
 976   PREFIX_0F1B,
 977   PREFIX_0F1C,
 978   PREFIX_0F1E,
 979   PREFIX_0F2A,
 980   PREFIX_0F2B,
 981   PREFIX_0F2C,
 982   PREFIX_0F2D,
 983   PREFIX_0F2E,
 984   PREFIX_0F2F,
 985   PREFIX_0F51,
 986   PREFIX_0F52,
 987   PREFIX_0F53,
 988   PREFIX_0F58,
 989   PREFIX_0F59,
 990   PREFIX_0F5A,
 991   PREFIX_0F5B,
 992   PREFIX_0F5C,
 993   PREFIX_0F5D,
 994   PREFIX_0F5E,
 995   PREFIX_0F5F,
 996   PREFIX_0F60,
 997   PREFIX_0F61,
 998   PREFIX_0F62,
 999   PREFIX_0F6C,
1000   PREFIX_0F6D,
1001   PREFIX_0F6F,
1002   PREFIX_0F70,
1003   PREFIX_0F73_REG_3,
1004   PREFIX_0F73_REG_7,
1005   PREFIX_0F78,
1006   PREFIX_0F79,
1007   PREFIX_0F7C,
1008   PREFIX_0F7D,
1009   PREFIX_0F7E,
1010   PREFIX_0F7F,
1011   PREFIX_0FAE_REG_0_MOD_3,
1012   PREFIX_0FAE_REG_1_MOD_3,
1013   PREFIX_0FAE_REG_2_MOD_3,
1014   PREFIX_0FAE_REG_3_MOD_3,
1015   PREFIX_0FAE_REG_4_MOD_0,
1016   PREFIX_0FAE_REG_4_MOD_3,
1017   PREFIX_0FAE_REG_5_MOD_0,
1018   PREFIX_0FAE_REG_5_MOD_3,
1019   PREFIX_0FAE_REG_6_MOD_0,
1020   PREFIX_0FAE_REG_6_MOD_3,
1021   PREFIX_0FAE_REG_7_MOD_0,
1022   PREFIX_0FB8,
1023   PREFIX_0FBC,
1024   PREFIX_0FBD,
1025   PREFIX_0FC2,
1026   PREFIX_0FC3_MOD_0,
1027   PREFIX_0FC7_REG_6_MOD_0,
1028   PREFIX_0FC7_REG_6_MOD_3,
1029   PREFIX_0FC7_REG_7_MOD_3,
1030   PREFIX_0FD0,
1031   PREFIX_0FD6,
1032   PREFIX_0FE6,
1033   PREFIX_0FE7,
1034   PREFIX_0FF0,
1035   PREFIX_0FF7,
1036   PREFIX_0F3810,
1037   PREFIX_0F3814,
1038   PREFIX_0F3815,
1039   PREFIX_0F3817,
1040   PREFIX_0F3820,
1041   PREFIX_0F3821,
1042   PREFIX_0F3822,
1043   PREFIX_0F3823,
1044   PREFIX_0F3824,
1045   PREFIX_0F3825,
1046   PREFIX_0F3828,
1047   PREFIX_0F3829,
1048   PREFIX_0F382A,
1049   PREFIX_0F382B,
1050   PREFIX_0F3830,
1051   PREFIX_0F3831,
1052   PREFIX_0F3832,
1053   PREFIX_0F3833,
1054   PREFIX_0F3834,
1055   PREFIX_0F3835,
1056   PREFIX_0F3837,
1057   PREFIX_0F3838,
1058   PREFIX_0F3839,
1059   PREFIX_0F383A,
1060   PREFIX_0F383B,
1061   PREFIX_0F383C,
1062   PREFIX_0F383D,
1063   PREFIX_0F383E,
1064   PREFIX_0F383F,
1065   PREFIX_0F3840,
1066   PREFIX_0F3841,
1067   PREFIX_0F3880,
1068   PREFIX_0F3881,
1069   PREFIX_0F3882,
1070   PREFIX_0F38C8,
1071   PREFIX_0F38C9,
1072   PREFIX_0F38CA,
1073   PREFIX_0F38CB,
1074   PREFIX_0F38CC,
1075   PREFIX_0F38CD,
1076   PREFIX_0F38CF,
1077   PREFIX_0F38DB,
1078   PREFIX_0F38DC,
1079   PREFIX_0F38DD,
1080   PREFIX_0F38DE,
1081   PREFIX_0F38DF,
1082   PREFIX_0F38F0,
1083   PREFIX_0F38F1,
1084   PREFIX_0F38F5,
1085   PREFIX_0F38F6,
1086   PREFIX_0F38F8,
1087   PREFIX_0F38F9,
1088   PREFIX_0F3A08,
1089   PREFIX_0F3A09,
1090   PREFIX_0F3A0A,
1091   PREFIX_0F3A0B,
1092   PREFIX_0F3A0C,
1093   PREFIX_0F3A0D,
1094   PREFIX_0F3A0E,
1095   PREFIX_0F3A14,
1096   PREFIX_0F3A15,
1097   PREFIX_0F3A16,
1098   PREFIX_0F3A17,
1099   PREFIX_0F3A20,
1100   PREFIX_0F3A21,
1101   PREFIX_0F3A22,
1102   PREFIX_0F3A40,
1103   PREFIX_0F3A41,
1104   PREFIX_0F3A42,
1105   PREFIX_0F3A44,
1106   PREFIX_0F3A60,
1107   PREFIX_0F3A61,
1108   PREFIX_0F3A62,
1109   PREFIX_0F3A63,
1110   PREFIX_0F3ACC,
1111   PREFIX_0F3ACE,
1112   PREFIX_0F3ACF,
1113   PREFIX_0F3ADF,
1114   PREFIX_VEX_0F10,
1115   PREFIX_VEX_0F11,
1116   PREFIX_VEX_0F12,
1117   PREFIX_VEX_0F16,
1118   PREFIX_VEX_0F2A,
1119   PREFIX_VEX_0F2C,
1120   PREFIX_VEX_0F2D,
1121   PREFIX_VEX_0F2E,
1122   PREFIX_VEX_0F2F,
1123   PREFIX_VEX_0F41,
1124   PREFIX_VEX_0F42,
1125   PREFIX_VEX_0F44,
1126   PREFIX_VEX_0F45,
1127   PREFIX_VEX_0F46,
1128   PREFIX_VEX_0F47,
1129   PREFIX_VEX_0F4A,
1130   PREFIX_VEX_0F4B,
1131   PREFIX_VEX_0F51,
1132   PREFIX_VEX_0F52,
1133   PREFIX_VEX_0F53,
1134   PREFIX_VEX_0F58,
1135   PREFIX_VEX_0F59,
1136   PREFIX_VEX_0F5A,
1137   PREFIX_VEX_0F5B,
1138   PREFIX_VEX_0F5C,
1139   PREFIX_VEX_0F5D,
1140   PREFIX_VEX_0F5E,
1141   PREFIX_VEX_0F5F,
1142   PREFIX_VEX_0F60,
1143   PREFIX_VEX_0F61,
1144   PREFIX_VEX_0F62,
1145   PREFIX_VEX_0F63,
1146   PREFIX_VEX_0F64,
1147   PREFIX_VEX_0F65,
1148   PREFIX_VEX_0F66,
1149   PREFIX_VEX_0F67,
1150   PREFIX_VEX_0F68,
1151   PREFIX_VEX_0F69,
1152   PREFIX_VEX_0F6A,
1153   PREFIX_VEX_0F6B,
1154   PREFIX_VEX_0F6C,
1155   PREFIX_VEX_0F6D,
1156   PREFIX_VEX_0F6E,
1157   PREFIX_VEX_0F6F,
1158   PREFIX_VEX_0F70,
1159   PREFIX_VEX_0F71_REG_2,
1160   PREFIX_VEX_0F71_REG_4,
1161   PREFIX_VEX_0F71_REG_6,
1162   PREFIX_VEX_0F72_REG_2,
1163   PREFIX_VEX_0F72_REG_4,
1164   PREFIX_VEX_0F72_REG_6,
1165   PREFIX_VEX_0F73_REG_2,
1166   PREFIX_VEX_0F73_REG_3,
1167   PREFIX_VEX_0F73_REG_6,
1168   PREFIX_VEX_0F73_REG_7,
1169   PREFIX_VEX_0F74,
1170   PREFIX_VEX_0F75,
1171   PREFIX_VEX_0F76,
1172   PREFIX_VEX_0F77,
1173   PREFIX_VEX_0F7C,
1174   PREFIX_VEX_0F7D,
1175   PREFIX_VEX_0F7E,
1176   PREFIX_VEX_0F7F,
1177   PREFIX_VEX_0F90,
1178   PREFIX_VEX_0F91,
1179   PREFIX_VEX_0F92,
1180   PREFIX_VEX_0F93,
1181   PREFIX_VEX_0F98,
1182   PREFIX_VEX_0F99,
1183   PREFIX_VEX_0FC2,
1184   PREFIX_VEX_0FC4,
1185   PREFIX_VEX_0FC5,
1186   PREFIX_VEX_0FD0,
1187   PREFIX_VEX_0FD1,
1188   PREFIX_VEX_0FD2,
1189   PREFIX_VEX_0FD3,
1190   PREFIX_VEX_0FD4,
1191   PREFIX_VEX_0FD5,
1192   PREFIX_VEX_0FD6,
1193   PREFIX_VEX_0FD7,
1194   PREFIX_VEX_0FD8,
1195   PREFIX_VEX_0FD9,
1196   PREFIX_VEX_0FDA,
1197   PREFIX_VEX_0FDB,
1198   PREFIX_VEX_0FDC,
1199   PREFIX_VEX_0FDD,
1200   PREFIX_VEX_0FDE,
1201   PREFIX_VEX_0FDF,
1202   PREFIX_VEX_0FE0,
1203   PREFIX_VEX_0FE1,
1204   PREFIX_VEX_0FE2,
1205   PREFIX_VEX_0FE3,
1206   PREFIX_VEX_0FE4,
1207   PREFIX_VEX_0FE5,
1208   PREFIX_VEX_0FE6,
1209   PREFIX_VEX_0FE7,
1210   PREFIX_VEX_0FE8,
1211   PREFIX_VEX_0FE9,
1212   PREFIX_VEX_0FEA,
1213   PREFIX_VEX_0FEB,
1214   PREFIX_VEX_0FEC,
1215   PREFIX_VEX_0FED,
1216   PREFIX_VEX_0FEE,
1217   PREFIX_VEX_0FEF,
1218   PREFIX_VEX_0FF0,
1219   PREFIX_VEX_0FF1,
1220   PREFIX_VEX_0FF2,
1221   PREFIX_VEX_0FF3,
1222   PREFIX_VEX_0FF4,
1223   PREFIX_VEX_0FF5,
1224   PREFIX_VEX_0FF6,
1225   PREFIX_VEX_0FF7,
1226   PREFIX_VEX_0FF8,
1227   PREFIX_VEX_0FF9,
1228   PREFIX_VEX_0FFA,
1229   PREFIX_VEX_0FFB,
1230   PREFIX_VEX_0FFC,
1231   PREFIX_VEX_0FFD,
1232   PREFIX_VEX_0FFE,
1233   PREFIX_VEX_0F3800,
1234   PREFIX_VEX_0F3801,
1235   PREFIX_VEX_0F3802,
1236   PREFIX_VEX_0F3803,
1237   PREFIX_VEX_0F3804,
1238   PREFIX_VEX_0F3805,
1239   PREFIX_VEX_0F3806,
1240   PREFIX_VEX_0F3807,
1241   PREFIX_VEX_0F3808,
1242   PREFIX_VEX_0F3809,
1243   PREFIX_VEX_0F380A,
1244   PREFIX_VEX_0F380B,
1245   PREFIX_VEX_0F380C,
1246   PREFIX_VEX_0F380D,
1247   PREFIX_VEX_0F380E,
1248   PREFIX_VEX_0F380F,
1249   PREFIX_VEX_0F3813,
1250   PREFIX_VEX_0F3816,
1251   PREFIX_VEX_0F3817,
1252   PREFIX_VEX_0F3818,
1253   PREFIX_VEX_0F3819,
1254   PREFIX_VEX_0F381A,
1255   PREFIX_VEX_0F381C,
1256   PREFIX_VEX_0F381D,
1257   PREFIX_VEX_0F381E,
1258   PREFIX_VEX_0F3820,
1259   PREFIX_VEX_0F3821,
1260   PREFIX_VEX_0F3822,
1261   PREFIX_VEX_0F3823,
1262   PREFIX_VEX_0F3824,
1263   PREFIX_VEX_0F3825,
1264   PREFIX_VEX_0F3828,
1265   PREFIX_VEX_0F3829,
1266   PREFIX_VEX_0F382A,
1267   PREFIX_VEX_0F382B,
1268   PREFIX_VEX_0F382C,
1269   PREFIX_VEX_0F382D,
1270   PREFIX_VEX_0F382E,
1271   PREFIX_VEX_0F382F,
1272   PREFIX_VEX_0F3830,
1273   PREFIX_VEX_0F3831,
1274   PREFIX_VEX_0F3832,
1275   PREFIX_VEX_0F3833,
1276   PREFIX_VEX_0F3834,
1277   PREFIX_VEX_0F3835,
1278   PREFIX_VEX_0F3836,
1279   PREFIX_VEX_0F3837,
1280   PREFIX_VEX_0F3838,
1281   PREFIX_VEX_0F3839,
1282   PREFIX_VEX_0F383A,
1283   PREFIX_VEX_0F383B,
1284   PREFIX_VEX_0F383C,
1285   PREFIX_VEX_0F383D,
1286   PREFIX_VEX_0F383E,
1287   PREFIX_VEX_0F383F,
1288   PREFIX_VEX_0F3840,
1289   PREFIX_VEX_0F3841,
1290   PREFIX_VEX_0F3845,
1291   PREFIX_VEX_0F3846,
1292   PREFIX_VEX_0F3847,
1293   PREFIX_VEX_0F3858,
1294   PREFIX_VEX_0F3859,
1295   PREFIX_VEX_0F385A,
1296   PREFIX_VEX_0F3878,
1297   PREFIX_VEX_0F3879,
1298   PREFIX_VEX_0F388C,
1299   PREFIX_VEX_0F388E,
1300   PREFIX_VEX_0F3890,
1301   PREFIX_VEX_0F3891,
1302   PREFIX_VEX_0F3892,
1303   PREFIX_VEX_0F3893,
1304   PREFIX_VEX_0F3896,
1305   PREFIX_VEX_0F3897,
1306   PREFIX_VEX_0F3898,
1307   PREFIX_VEX_0F3899,
1308   PREFIX_VEX_0F389A,
1309   PREFIX_VEX_0F389B,
1310   PREFIX_VEX_0F389C,
1311   PREFIX_VEX_0F389D,
1312   PREFIX_VEX_0F389E,
1313   PREFIX_VEX_0F389F,
1314   PREFIX_VEX_0F38A6,
1315   PREFIX_VEX_0F38A7,
1316   PREFIX_VEX_0F38A8,
1317   PREFIX_VEX_0F38A9,
1318   PREFIX_VEX_0F38AA,
1319   PREFIX_VEX_0F38AB,
1320   PREFIX_VEX_0F38AC,
1321   PREFIX_VEX_0F38AD,
1322   PREFIX_VEX_0F38AE,
1323   PREFIX_VEX_0F38AF,
1324   PREFIX_VEX_0F38B6,
1325   PREFIX_VEX_0F38B7,
1326   PREFIX_VEX_0F38B8,
1327   PREFIX_VEX_0F38B9,
1328   PREFIX_VEX_0F38BA,
1329   PREFIX_VEX_0F38BB,
1330   PREFIX_VEX_0F38BC,
1331   PREFIX_VEX_0F38BD,
1332   PREFIX_VEX_0F38BE,
1333   PREFIX_VEX_0F38BF,
1334   PREFIX_VEX_0F38CF,
1335   PREFIX_VEX_0F38DB,
1336   PREFIX_VEX_0F38DC,
1337   PREFIX_VEX_0F38DD,
1338   PREFIX_VEX_0F38DE,
1339   PREFIX_VEX_0F38DF,
1340   PREFIX_VEX_0F38F2,
1341   PREFIX_VEX_0F38F3_REG_1,
1342   PREFIX_VEX_0F38F3_REG_2,
1343   PREFIX_VEX_0F38F3_REG_3,
1344   PREFIX_VEX_0F38F5,
1345   PREFIX_VEX_0F38F6,
1346   PREFIX_VEX_0F38F7,
1347   PREFIX_VEX_0F3A00,
1348   PREFIX_VEX_0F3A01,
1349   PREFIX_VEX_0F3A02,
1350   PREFIX_VEX_0F3A04,
1351   PREFIX_VEX_0F3A05,
1352   PREFIX_VEX_0F3A06,
1353   PREFIX_VEX_0F3A08,
1354   PREFIX_VEX_0F3A09,
1355   PREFIX_VEX_0F3A0A,
1356   PREFIX_VEX_0F3A0B,
1357   PREFIX_VEX_0F3A0C,
1358   PREFIX_VEX_0F3A0D,
1359   PREFIX_VEX_0F3A0E,
1360   PREFIX_VEX_0F3A0F,
1361   PREFIX_VEX_0F3A14,
1362   PREFIX_VEX_0F3A15,
1363   PREFIX_VEX_0F3A16,
1364   PREFIX_VEX_0F3A17,
1365   PREFIX_VEX_0F3A18,
1366   PREFIX_VEX_0F3A19,
1367   PREFIX_VEX_0F3A1D,
1368   PREFIX_VEX_0F3A20,
1369   PREFIX_VEX_0F3A21,
1370   PREFIX_VEX_0F3A22,
1371   PREFIX_VEX_0F3A30,
1372   PREFIX_VEX_0F3A31,
1373   PREFIX_VEX_0F3A32,
1374   PREFIX_VEX_0F3A33,
1375   PREFIX_VEX_0F3A38,
1376   PREFIX_VEX_0F3A39,
1377   PREFIX_VEX_0F3A40,
1378   PREFIX_VEX_0F3A41,
1379   PREFIX_VEX_0F3A42,
1380   PREFIX_VEX_0F3A44,
1381   PREFIX_VEX_0F3A46,
1382   PREFIX_VEX_0F3A48,
1383   PREFIX_VEX_0F3A49,
1384   PREFIX_VEX_0F3A4A,
1385   PREFIX_VEX_0F3A4B,
1386   PREFIX_VEX_0F3A4C,
1387   PREFIX_VEX_0F3A5C,
1388   PREFIX_VEX_0F3A5D,
1389   PREFIX_VEX_0F3A5E,
1390   PREFIX_VEX_0F3A5F,
1391   PREFIX_VEX_0F3A60,
1392   PREFIX_VEX_0F3A61,
1393   PREFIX_VEX_0F3A62,
1394   PREFIX_VEX_0F3A63,
1395   PREFIX_VEX_0F3A68,
1396   PREFIX_VEX_0F3A69,
1397   PREFIX_VEX_0F3A6A,
1398   PREFIX_VEX_0F3A6B,
1399   PREFIX_VEX_0F3A6C,
1400   PREFIX_VEX_0F3A6D,
1401   PREFIX_VEX_0F3A6E,
1402   PREFIX_VEX_0F3A6F,
1403   PREFIX_VEX_0F3A78,
1404   PREFIX_VEX_0F3A79,
1405   PREFIX_VEX_0F3A7A,
1406   PREFIX_VEX_0F3A7B,
1407   PREFIX_VEX_0F3A7C,
1408   PREFIX_VEX_0F3A7D,
1409   PREFIX_VEX_0F3A7E,
1410   PREFIX_VEX_0F3A7F,
1411   PREFIX_VEX_0F3ACE,
1412   PREFIX_VEX_0F3ACF,
1413   PREFIX_VEX_0F3ADF,
1414   PREFIX_VEX_0F3AF0,
1415
1416   PREFIX_EVEX_0F10,
1417   PREFIX_EVEX_0F11,
1418   PREFIX_EVEX_0F12,
1419   PREFIX_EVEX_0F13,
1420   PREFIX_EVEX_0F14,
1421   PREFIX_EVEX_0F15,
1422   PREFIX_EVEX_0F16,
1423   PREFIX_EVEX_0F17,
1424   PREFIX_EVEX_0F28,
1425   PREFIX_EVEX_0F29,
1426   PREFIX_EVEX_0F2A,
1427   PREFIX_EVEX_0F2B,
1428   PREFIX_EVEX_0F2C,
1429   PREFIX_EVEX_0F2D,
1430   PREFIX_EVEX_0F2E,
1431   PREFIX_EVEX_0F2F,
1432   PREFIX_EVEX_0F51,
1433   PREFIX_EVEX_0F54,
1434   PREFIX_EVEX_0F55,
1435   PREFIX_EVEX_0F56,
1436   PREFIX_EVEX_0F57,
1437   PREFIX_EVEX_0F58,
1438   PREFIX_EVEX_0F59,
1439   PREFIX_EVEX_0F5A,
1440   PREFIX_EVEX_0F5B,
1441   PREFIX_EVEX_0F5C,
1442   PREFIX_EVEX_0F5D,
1443   PREFIX_EVEX_0F5E,
1444   PREFIX_EVEX_0F5F,
1445   PREFIX_EVEX_0F60,
1446   PREFIX_EVEX_0F61,
1447   PREFIX_EVEX_0F62,
1448   PREFIX_EVEX_0F63,
1449   PREFIX_EVEX_0F64,
1450   PREFIX_EVEX_0F65,
1451   PREFIX_EVEX_0F66,
1452   PREFIX_EVEX_0F67,
1453   PREFIX_EVEX_0F68,
1454   PREFIX_EVEX_0F69,
1455   PREFIX_EVEX_0F6A,
1456   PREFIX_EVEX_0F6B,
1457   PREFIX_EVEX_0F6C,
1458   PREFIX_EVEX_0F6D,
1459   PREFIX_EVEX_0F6E,
1460   PREFIX_EVEX_0F6F,
1461   PREFIX_EVEX_0F70,
1462   PREFIX_EVEX_0F71_REG_2,
1463   PREFIX_EVEX_0F71_REG_4,
1464   PREFIX_EVEX_0F71_REG_6,
1465   PREFIX_EVEX_0F72_REG_0,
1466   PREFIX_EVEX_0F72_REG_1,
1467   PREFIX_EVEX_0F72_REG_2,
1468   PREFIX_EVEX_0F72_REG_4,
1469   PREFIX_EVEX_0F72_REG_6,
1470   PREFIX_EVEX_0F73_REG_2,
1471   PREFIX_EVEX_0F73_REG_3,
1472   PREFIX_EVEX_0F73_REG_6,
1473   PREFIX_EVEX_0F73_REG_7,
1474   PREFIX_EVEX_0F74,
1475   PREFIX_EVEX_0F75,
1476   PREFIX_EVEX_0F76,
1477   PREFIX_EVEX_0F78,
1478   PREFIX_EVEX_0F79,
1479   PREFIX_EVEX_0F7A,
1480   PREFIX_EVEX_0F7B,
1481   PREFIX_EVEX_0F7E,
1482   PREFIX_EVEX_0F7F,
1483   PREFIX_EVEX_0FC2,
1484   PREFIX_EVEX_0FC4,
1485   PREFIX_EVEX_0FC5,
1486   PREFIX_EVEX_0FC6,
1487   PREFIX_EVEX_0FD1,
1488   PREFIX_EVEX_0FD2,
1489   PREFIX_EVEX_0FD3,
1490   PREFIX_EVEX_0FD4,
1491   PREFIX_EVEX_0FD5,
1492   PREFIX_EVEX_0FD6,
1493   PREFIX_EVEX_0FD8,
1494   PREFIX_EVEX_0FD9,
1495   PREFIX_EVEX_0FDA,
1496   PREFIX_EVEX_0FDB,
1497   PREFIX_EVEX_0FDC,
1498   PREFIX_EVEX_0FDD,
1499   PREFIX_EVEX_0FDE,
1500   PREFIX_EVEX_0FDF,
1501   PREFIX_EVEX_0FE0,
1502   PREFIX_EVEX_0FE1,
1503   PREFIX_EVEX_0FE2,
1504   PREFIX_EVEX_0FE3,
1505   PREFIX_EVEX_0FE4,
1506   PREFIX_EVEX_0FE5,
1507   PREFIX_EVEX_0FE6,
1508   PREFIX_EVEX_0FE7,
1509   PREFIX_EVEX_0FE8,
1510   PREFIX_EVEX_0FE9,
1511   PREFIX_EVEX_0FEA,
1512   PREFIX_EVEX_0FEB,
1513   PREFIX_EVEX_0FEC,
1514   PREFIX_EVEX_0FED,
1515   PREFIX_EVEX_0FEE,
1516   PREFIX_EVEX_0FEF,
1517   PREFIX_EVEX_0FF1,
1518   PREFIX_EVEX_0FF2,
1519   PREFIX_EVEX_0FF3,
1520   PREFIX_EVEX_0FF4,
1521   PREFIX_EVEX_0FF5,
1522   PREFIX_EVEX_0FF6,
1523   PREFIX_EVEX_0FF8,
1524   PREFIX_EVEX_0FF9,
1525   PREFIX_EVEX_0FFA,
1526   PREFIX_EVEX_0FFB,
1527   PREFIX_EVEX_0FFC,
1528   PREFIX_EVEX_0FFD,
1529   PREFIX_EVEX_0FFE,
1530   PREFIX_EVEX_0F3800,
1531   PREFIX_EVEX_0F3804,
1532   PREFIX_EVEX_0F380B,
1533   PREFIX_EVEX_0F380C,
1534   PREFIX_EVEX_0F380D,
1535   PREFIX_EVEX_0F3810,
1536   PREFIX_EVEX_0F3811,
1537   PREFIX_EVEX_0F3812,
1538   PREFIX_EVEX_0F3813,
1539   PREFIX_EVEX_0F3814,
1540   PREFIX_EVEX_0F3815,
1541   PREFIX_EVEX_0F3816,
1542   PREFIX_EVEX_0F3818,
1543   PREFIX_EVEX_0F3819,
1544   PREFIX_EVEX_0F381A,
1545   PREFIX_EVEX_0F381B,
1546   PREFIX_EVEX_0F381C,
1547   PREFIX_EVEX_0F381D,
1548   PREFIX_EVEX_0F381E,
1549   PREFIX_EVEX_0F381F,
1550   PREFIX_EVEX_0F3820,
1551   PREFIX_EVEX_0F3821,
1552   PREFIX_EVEX_0F3822,
1553   PREFIX_EVEX_0F3823,
1554   PREFIX_EVEX_0F3824,
1555   PREFIX_EVEX_0F3825,
1556   PREFIX_EVEX_0F3826,
1557   PREFIX_EVEX_0F3827,
1558   PREFIX_EVEX_0F3828,
1559   PREFIX_EVEX_0F3829,
1560   PREFIX_EVEX_0F382A,
1561   PREFIX_EVEX_0F382B,
1562   PREFIX_EVEX_0F382C,
1563   PREFIX_EVEX_0F382D,
1564   PREFIX_EVEX_0F3830,
1565   PREFIX_EVEX_0F3831,
1566   PREFIX_EVEX_0F3832,
1567   PREFIX_EVEX_0F3833,
1568   PREFIX_EVEX_0F3834,
1569   PREFIX_EVEX_0F3835,
1570   PREFIX_EVEX_0F3836,
1571   PREFIX_EVEX_0F3837,
1572   PREFIX_EVEX_0F3838,
1573   PREFIX_EVEX_0F3839,
1574   PREFIX_EVEX_0F383A,
1575   PREFIX_EVEX_0F383B,
1576   PREFIX_EVEX_0F383C,
1577   PREFIX_EVEX_0F383D,
1578   PREFIX_EVEX_0F383E,
1579   PREFIX_EVEX_0F383F,
1580   PREFIX_EVEX_0F3840,
1581   PREFIX_EVEX_0F3842,
1582   PREFIX_EVEX_0F3843,
1583   PREFIX_EVEX_0F3844,
1584   PREFIX_EVEX_0F3845,
1585   PREFIX_EVEX_0F3846,
1586   PREFIX_EVEX_0F3847,
1587   PREFIX_EVEX_0F384C,
1588   PREFIX_EVEX_0F384D,
1589   PREFIX_EVEX_0F384E,
1590   PREFIX_EVEX_0F384F,
1591   PREFIX_EVEX_0F3850,
1592   PREFIX_EVEX_0F3851,
1593   PREFIX_EVEX_0F3852,
1594   PREFIX_EVEX_0F3853,
1595   PREFIX_EVEX_0F3854,
1596   PREFIX_EVEX_0F3855,
1597   PREFIX_EVEX_0F3858,
1598   PREFIX_EVEX_0F3859,
1599   PREFIX_EVEX_0F385A,
1600   PREFIX_EVEX_0F385B,
1601   PREFIX_EVEX_0F3862,
1602   PREFIX_EVEX_0F3863,
1603   PREFIX_EVEX_0F3864,
1604   PREFIX_EVEX_0F3865,
1605   PREFIX_EVEX_0F3866,
1606   PREFIX_EVEX_0F3868,
1607   PREFIX_EVEX_0F3870,
1608   PREFIX_EVEX_0F3871,
1609   PREFIX_EVEX_0F3872,
1610   PREFIX_EVEX_0F3873,
1611   PREFIX_EVEX_0F3875,
1612   PREFIX_EVEX_0F3876,
1613   PREFIX_EVEX_0F3877,
1614   PREFIX_EVEX_0F3878,
1615   PREFIX_EVEX_0F3879,
1616   PREFIX_EVEX_0F387A,
1617   PREFIX_EVEX_0F387B,
1618   PREFIX_EVEX_0F387C,
1619   PREFIX_EVEX_0F387D,
1620   PREFIX_EVEX_0F387E,
1621   PREFIX_EVEX_0F387F,
1622   PREFIX_EVEX_0F3883,
1623   PREFIX_EVEX_0F3888,
1624   PREFIX_EVEX_0F3889,
1625   PREFIX_EVEX_0F388A,
1626   PREFIX_EVEX_0F388B,
1627   PREFIX_EVEX_0F388D,
1628   PREFIX_EVEX_0F388F,
1629   PREFIX_EVEX_0F3890,
1630   PREFIX_EVEX_0F3891,
1631   PREFIX_EVEX_0F3892,
1632   PREFIX_EVEX_0F3893,
1633   PREFIX_EVEX_0F3896,
1634   PREFIX_EVEX_0F3897,
1635   PREFIX_EVEX_0F3898,
1636   PREFIX_EVEX_0F3899,
1637   PREFIX_EVEX_0F389A,
1638   PREFIX_EVEX_0F389B,
1639   PREFIX_EVEX_0F389C,
1640   PREFIX_EVEX_0F389D,
1641   PREFIX_EVEX_0F389E,
1642   PREFIX_EVEX_0F389F,
1643   PREFIX_EVEX_0F38A0,
1644   PREFIX_EVEX_0F38A1,
1645   PREFIX_EVEX_0F38A2,
1646   PREFIX_EVEX_0F38A3,
1647   PREFIX_EVEX_0F38A6,
1648   PREFIX_EVEX_0F38A7,
1649   PREFIX_EVEX_0F38A8,
1650   PREFIX_EVEX_0F38A9,
1651   PREFIX_EVEX_0F38AA,
1652   PREFIX_EVEX_0F38AB,
1653   PREFIX_EVEX_0F38AC,
1654   PREFIX_EVEX_0F38AD,
1655   PREFIX_EVEX_0F38AE,
1656   PREFIX_EVEX_0F38AF,
1657   PREFIX_EVEX_0F38B4,
1658   PREFIX_EVEX_0F38B5,
1659   PREFIX_EVEX_0F38B6,
1660   PREFIX_EVEX_0F38B7,
1661   PREFIX_EVEX_0F38B8,
1662   PREFIX_EVEX_0F38B9,
1663   PREFIX_EVEX_0F38BA,
1664   PREFIX_EVEX_0F38BB,
1665   PREFIX_EVEX_0F38BC,
1666   PREFIX_EVEX_0F38BD,
1667   PREFIX_EVEX_0F38BE,
1668   PREFIX_EVEX_0F38BF,
1669   PREFIX_EVEX_0F38C4,
1670   PREFIX_EVEX_0F38C6_REG_1,
1671   PREFIX_EVEX_0F38C6_REG_2,
1672   PREFIX_EVEX_0F38C6_REG_5,
1673   PREFIX_EVEX_0F38C6_REG_6,
1674   PREFIX_EVEX_0F38C7_REG_1,
1675   PREFIX_EVEX_0F38C7_REG_2,
1676   PREFIX_EVEX_0F38C7_REG_5,
1677   PREFIX_EVEX_0F38C7_REG_6,
1678   PREFIX_EVEX_0F38C8,
1679   PREFIX_EVEX_0F38CA,
1680   PREFIX_EVEX_0F38CB,
1681   PREFIX_EVEX_0F38CC,
1682   PREFIX_EVEX_0F38CD,
1683   PREFIX_EVEX_0F38CF,
1684   PREFIX_EVEX_0F38DC,
1685   PREFIX_EVEX_0F38DD,
1686   PREFIX_EVEX_0F38DE,
1687   PREFIX_EVEX_0F38DF,
1688
1689   PREFIX_EVEX_0F3A00,
1690   PREFIX_EVEX_0F3A01,
1691   PREFIX_EVEX_0F3A03,
1692   PREFIX_EVEX_0F3A04,
1693   PREFIX_EVEX_0F3A05,
1694   PREFIX_EVEX_0F3A08,
1695   PREFIX_EVEX_0F3A09,
1696   PREFIX_EVEX_0F3A0A,
1697   PREFIX_EVEX_0F3A0B,
1698   PREFIX_EVEX_0F3A0F,
1699   PREFIX_EVEX_0F3A14,
1700   PREFIX_EVEX_0F3A15,
1701   PREFIX_EVEX_0F3A16,
1702   PREFIX_EVEX_0F3A17,
1703   PREFIX_EVEX_0F3A18,
1704   PREFIX_EVEX_0F3A19,
1705   PREFIX_EVEX_0F3A1A,
1706   PREFIX_EVEX_0F3A1B,
1707   PREFIX_EVEX_0F3A1D,
1708   PREFIX_EVEX_0F3A1E,
1709   PREFIX_EVEX_0F3A1F,
1710   PREFIX_EVEX_0F3A20,
1711   PREFIX_EVEX_0F3A21,
1712   PREFIX_EVEX_0F3A22,
1713   PREFIX_EVEX_0F3A23,
1714   PREFIX_EVEX_0F3A25,
1715   PREFIX_EVEX_0F3A26,
1716   PREFIX_EVEX_0F3A27,
1717   PREFIX_EVEX_0F3A38,
1718   PREFIX_EVEX_0F3A39,
1719   PREFIX_EVEX_0F3A3A,
1720   PREFIX_EVEX_0F3A3B,
1721   PREFIX_EVEX_0F3A3E,
1722   PREFIX_EVEX_0F3A3F,
1723   PREFIX_EVEX_0F3A42,
1724   PREFIX_EVEX_0F3A43,
1725   PREFIX_EVEX_0F3A44,
1726   PREFIX_EVEX_0F3A50,
1727   PREFIX_EVEX_0F3A51,
1728   PREFIX_EVEX_0F3A54,
1729   PREFIX_EVEX_0F3A55,
1730   PREFIX_EVEX_0F3A56,
1731   PREFIX_EVEX_0F3A57,
1732   PREFIX_EVEX_0F3A66,
1733   PREFIX_EVEX_0F3A67,
1734   PREFIX_EVEX_0F3A70,
1735   PREFIX_EVEX_0F3A71,
1736   PREFIX_EVEX_0F3A72,
1737   PREFIX_EVEX_0F3A73,
1738   PREFIX_EVEX_0F3ACE,
1739   PREFIX_EVEX_0F3ACF
1740 };
1741
1742 enum
1743 {
1744   X86_64_06 = 0,
1745   X86_64_07,
1746   X86_64_0D,
1747   X86_64_16,
1748   X86_64_17,
1749   X86_64_1E,
1750   X86_64_1F,
1751   X86_64_27,
1752   X86_64_2F,
1753   X86_64_37,
1754   X86_64_3F,
1755   X86_64_60,
1756   X86_64_61,
1757   X86_64_62,
1758   X86_64_63,
1759   X86_64_6D,
1760   X86_64_6F,
1761   X86_64_82,
1762   X86_64_9A,
1763   X86_64_C4,
1764   X86_64_C5,
1765   X86_64_CE,
1766   X86_64_D4,
1767   X86_64_D5,
1768   X86_64_E8,
1769   X86_64_E9,
1770   X86_64_EA,
1771   X86_64_0F01_REG_0,
1772   X86_64_0F01_REG_1,
1773   X86_64_0F01_REG_2,
1774   X86_64_0F01_REG_3
1775 };
1776
1777 enum
1778 {
1779   THREE_BYTE_0F38 = 0,
1780   THREE_BYTE_0F3A
1781 };
1782
1783 enum
1784 {
1785   XOP_08 = 0,
1786   XOP_09,
1787   XOP_0A
1788 };
1789
1790 enum
1791 {
1792   VEX_0F = 0,
1793   VEX_0F38,
1794   VEX_0F3A
1795 };
1796
1797 enum
1798 {
1799   EVEX_0F = 0,
1800   EVEX_0F38,
1801   EVEX_0F3A
1802 };
1803
1804 enum
1805 {
1806   VEX_LEN_0F12_P_0_M_0 = 0,
1807   VEX_LEN_0F12_P_0_M_1,
1808   VEX_LEN_0F12_P_2,
1809   VEX_LEN_0F13_M_0,
1810   VEX_LEN_0F16_P_0_M_0,
1811   VEX_LEN_0F16_P_0_M_1,
1812   VEX_LEN_0F16_P_2,
1813   VEX_LEN_0F17_M_0,
1814   VEX_LEN_0F41_P_0,
1815   VEX_LEN_0F41_P_2,
1816   VEX_LEN_0F42_P_0,
1817   VEX_LEN_0F42_P_2,
1818   VEX_LEN_0F44_P_0,
1819   VEX_LEN_0F44_P_2,
1820   VEX_LEN_0F45_P_0,
1821   VEX_LEN_0F45_P_2,
1822   VEX_LEN_0F46_P_0,
1823   VEX_LEN_0F46_P_2,
1824   VEX_LEN_0F47_P_0,
1825   VEX_LEN_0F47_P_2,
1826   VEX_LEN_0F4A_P_0,
1827   VEX_LEN_0F4A_P_2,
1828   VEX_LEN_0F4B_P_0,
1829   VEX_LEN_0F4B_P_2,
1830   VEX_LEN_0F6E_P_2,
1831   VEX_LEN_0F77_P_0,
1832   VEX_LEN_0F7E_P_1,
1833   VEX_LEN_0F7E_P_2,
1834   VEX_LEN_0F90_P_0,
1835   VEX_LEN_0F90_P_2,
1836   VEX_LEN_0F91_P_0,
1837   VEX_LEN_0F91_P_2,
1838   VEX_LEN_0F92_P_0,
1839   VEX_LEN_0F92_P_2,
1840   VEX_LEN_0F92_P_3,
1841   VEX_LEN_0F93_P_0,
1842   VEX_LEN_0F93_P_2,
1843   VEX_LEN_0F93_P_3,
1844   VEX_LEN_0F98_P_0,
1845   VEX_LEN_0F98_P_2,
1846   VEX_LEN_0F99_P_0,
1847   VEX_LEN_0F99_P_2,
1848   VEX_LEN_0FAE_R_2_M_0,
1849   VEX_LEN_0FAE_R_3_M_0,
1850   VEX_LEN_0FC4_P_2,
1851   VEX_LEN_0FC5_P_2,
1852   VEX_LEN_0FD6_P_2,
1853   VEX_LEN_0FF7_P_2,
1854   VEX_LEN_0F3816_P_2,
1855   VEX_LEN_0F3819_P_2,
1856   VEX_LEN_0F381A_P_2_M_0,
1857   VEX_LEN_0F3836_P_2,
1858   VEX_LEN_0F3841_P_2,
1859   VEX_LEN_0F385A_P_2_M_0,
1860   VEX_LEN_0F38DB_P_2,
1861   VEX_LEN_0F38F2_P_0,
1862   VEX_LEN_0F38F3_R_1_P_0,
1863   VEX_LEN_0F38F3_R_2_P_0,
1864   VEX_LEN_0F38F3_R_3_P_0,
1865   VEX_LEN_0F38F5_P_0,
1866   VEX_LEN_0F38F5_P_1,
1867   VEX_LEN_0F38F5_P_3,
1868   VEX_LEN_0F38F6_P_3,
1869   VEX_LEN_0F38F7_P_0,
1870   VEX_LEN_0F38F7_P_1,
1871   VEX_LEN_0F38F7_P_2,
1872   VEX_LEN_0F38F7_P_3,
1873   VEX_LEN_0F3A00_P_2,
1874   VEX_LEN_0F3A01_P_2,
1875   VEX_LEN_0F3A06_P_2,
1876   VEX_LEN_0F3A14_P_2,
1877   VEX_LEN_0F3A15_P_2,
1878   VEX_LEN_0F3A16_P_2,
1879   VEX_LEN_0F3A17_P_2,
1880   VEX_LEN_0F3A18_P_2,
1881   VEX_LEN_0F3A19_P_2,
1882   VEX_LEN_0F3A20_P_2,
1883   VEX_LEN_0F3A21_P_2,
1884   VEX_LEN_0F3A22_P_2,
1885   VEX_LEN_0F3A30_P_2,
1886   VEX_LEN_0F3A31_P_2,
1887   VEX_LEN_0F3A32_P_2,
1888   VEX_LEN_0F3A33_P_2,
1889   VEX_LEN_0F3A38_P_2,
1890   VEX_LEN_0F3A39_P_2,
1891   VEX_LEN_0F3A41_P_2,
1892   VEX_LEN_0F3A46_P_2,
1893   VEX_LEN_0F3A60_P_2,
1894   VEX_LEN_0F3A61_P_2,
1895   VEX_LEN_0F3A62_P_2,
1896   VEX_LEN_0F3A63_P_2,
1897   VEX_LEN_0F3A6A_P_2,
1898   VEX_LEN_0F3A6B_P_2,
1899   VEX_LEN_0F3A6E_P_2,
1900   VEX_LEN_0F3A6F_P_2,
1901   VEX_LEN_0F3A7A_P_2,
1902   VEX_LEN_0F3A7B_P_2,
1903   VEX_LEN_0F3A7E_P_2,
1904   VEX_LEN_0F3A7F_P_2,
1905   VEX_LEN_0F3ADF_P_2,
1906   VEX_LEN_0F3AF0_P_3,
1907   VEX_LEN_0FXOP_08_CC,
1908   VEX_LEN_0FXOP_08_CD,
1909   VEX_LEN_0FXOP_08_CE,
1910   VEX_LEN_0FXOP_08_CF,
1911   VEX_LEN_0FXOP_08_EC,
1912   VEX_LEN_0FXOP_08_ED,
1913   VEX_LEN_0FXOP_08_EE,
1914   VEX_LEN_0FXOP_08_EF,
1915   VEX_LEN_0FXOP_09_80,
1916   VEX_LEN_0FXOP_09_81
1917 };
1918
1919 enum
1920 {
1921   EVEX_LEN_0F6E_P_2 = 0,
1922   EVEX_LEN_0F7E_P_1,
1923   EVEX_LEN_0F7E_P_2,
1924   EVEX_LEN_0FD6_P_2,
1925   EVEX_LEN_0F3819_P_2_W_0,
1926   EVEX_LEN_0F3819_P_2_W_1,
1927   EVEX_LEN_0F381A_P_2_W_0,
1928   EVEX_LEN_0F381A_P_2_W_1,
1929   EVEX_LEN_0F381B_P_2_W_0,
1930   EVEX_LEN_0F381B_P_2_W_1,
1931   EVEX_LEN_0F385A_P_2_W_0,
1932   EVEX_LEN_0F385A_P_2_W_1,
1933   EVEX_LEN_0F385B_P_2_W_0,
1934   EVEX_LEN_0F385B_P_2_W_1,
1935   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1936   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1937   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1938   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1939   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1940   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1941   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1942   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1943   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1944   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1945   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1946   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1947   EVEX_LEN_0F3A18_P_2_W_0,
1948   EVEX_LEN_0F3A18_P_2_W_1,
1949   EVEX_LEN_0F3A19_P_2_W_0,
1950   EVEX_LEN_0F3A19_P_2_W_1,
1951   EVEX_LEN_0F3A1A_P_2_W_0,
1952   EVEX_LEN_0F3A1A_P_2_W_1,
1953   EVEX_LEN_0F3A1B_P_2_W_0,
1954   EVEX_LEN_0F3A1B_P_2_W_1,
1955   EVEX_LEN_0F3A23_P_2_W_0,
1956   EVEX_LEN_0F3A23_P_2_W_1,
1957   EVEX_LEN_0F3A38_P_2_W_0,
1958   EVEX_LEN_0F3A38_P_2_W_1,
1959   EVEX_LEN_0F3A39_P_2_W_0,
1960   EVEX_LEN_0F3A39_P_2_W_1,
1961   EVEX_LEN_0F3A3A_P_2_W_0,
1962   EVEX_LEN_0F3A3A_P_2_W_1,
1963   EVEX_LEN_0F3A3B_P_2_W_0,
1964   EVEX_LEN_0F3A3B_P_2_W_1,
1965   EVEX_LEN_0F3A43_P_2_W_0,
1966   EVEX_LEN_0F3A43_P_2_W_1
1967 };
1968
1969 enum
1970 {
1971   VEX_W_0F41_P_0_LEN_1 = 0,
1972   VEX_W_0F41_P_2_LEN_1,
1973   VEX_W_0F42_P_0_LEN_1,
1974   VEX_W_0F42_P_2_LEN_1,
1975   VEX_W_0F44_P_0_LEN_0,
1976   VEX_W_0F44_P_2_LEN_0,
1977   VEX_W_0F45_P_0_LEN_1,
1978   VEX_W_0F45_P_2_LEN_1,
1979   VEX_W_0F46_P_0_LEN_1,
1980   VEX_W_0F46_P_2_LEN_1,
1981   VEX_W_0F47_P_0_LEN_1,
1982   VEX_W_0F47_P_2_LEN_1,
1983   VEX_W_0F4A_P_0_LEN_1,
1984   VEX_W_0F4A_P_2_LEN_1,
1985   VEX_W_0F4B_P_0_LEN_1,
1986   VEX_W_0F4B_P_2_LEN_1,
1987   VEX_W_0F90_P_0_LEN_0,
1988   VEX_W_0F90_P_2_LEN_0,
1989   VEX_W_0F91_P_0_LEN_0,
1990   VEX_W_0F91_P_2_LEN_0,
1991   VEX_W_0F92_P_0_LEN_0,
1992   VEX_W_0F92_P_2_LEN_0,
1993   VEX_W_0F93_P_0_LEN_0,
1994   VEX_W_0F93_P_2_LEN_0,
1995   VEX_W_0F98_P_0_LEN_0,
1996   VEX_W_0F98_P_2_LEN_0,
1997   VEX_W_0F99_P_0_LEN_0,
1998   VEX_W_0F99_P_2_LEN_0,
1999   VEX_W_0F380C_P_2,
2000   VEX_W_0F380D_P_2,
2001   VEX_W_0F380E_P_2,
2002   VEX_W_0F380F_P_2,
2003   VEX_W_0F3816_P_2,
2004   VEX_W_0F3818_P_2,
2005   VEX_W_0F3819_P_2,
2006   VEX_W_0F381A_P_2_M_0,
2007   VEX_W_0F382C_P_2_M_0,
2008   VEX_W_0F382D_P_2_M_0,
2009   VEX_W_0F382E_P_2_M_0,
2010   VEX_W_0F382F_P_2_M_0,
2011   VEX_W_0F3836_P_2,
2012   VEX_W_0F3846_P_2,
2013   VEX_W_0F3858_P_2,
2014   VEX_W_0F3859_P_2,
2015   VEX_W_0F385A_P_2_M_0,
2016   VEX_W_0F3878_P_2,
2017   VEX_W_0F3879_P_2,
2018   VEX_W_0F38CF_P_2,
2019   VEX_W_0F3A00_P_2,
2020   VEX_W_0F3A01_P_2,
2021   VEX_W_0F3A02_P_2,
2022   VEX_W_0F3A04_P_2,
2023   VEX_W_0F3A05_P_2,
2024   VEX_W_0F3A06_P_2,
2025   VEX_W_0F3A18_P_2,
2026   VEX_W_0F3A19_P_2,
2027   VEX_W_0F3A30_P_2_LEN_0,
2028   VEX_W_0F3A31_P_2_LEN_0,
2029   VEX_W_0F3A32_P_2_LEN_0,
2030   VEX_W_0F3A33_P_2_LEN_0,
2031   VEX_W_0F3A38_P_2,
2032   VEX_W_0F3A39_P_2,
2033   VEX_W_0F3A46_P_2,
2034   VEX_W_0F3A48_P_2,
2035   VEX_W_0F3A49_P_2,
2036   VEX_W_0F3A4A_P_2,
2037   VEX_W_0F3A4B_P_2,
2038   VEX_W_0F3A4C_P_2,
2039   VEX_W_0F3ACE_P_2,
2040   VEX_W_0F3ACF_P_2,
2041
2042   EVEX_W_0F10_P_0,
2043   EVEX_W_0F10_P_1,
2044   EVEX_W_0F10_P_2,
2045   EVEX_W_0F10_P_3,
2046   EVEX_W_0F11_P_0,
2047   EVEX_W_0F11_P_1,
2048   EVEX_W_0F11_P_2,
2049   EVEX_W_0F11_P_3,
2050   EVEX_W_0F12_P_0_M_0,
2051   EVEX_W_0F12_P_0_M_1,
2052   EVEX_W_0F12_P_1,
2053   EVEX_W_0F12_P_2,
2054   EVEX_W_0F12_P_3,
2055   EVEX_W_0F13_P_0,
2056   EVEX_W_0F13_P_2,
2057   EVEX_W_0F14_P_0,
2058   EVEX_W_0F14_P_2,
2059   EVEX_W_0F15_P_0,
2060   EVEX_W_0F15_P_2,
2061   EVEX_W_0F16_P_0_M_0,
2062   EVEX_W_0F16_P_0_M_1,
2063   EVEX_W_0F16_P_1,
2064   EVEX_W_0F16_P_2,
2065   EVEX_W_0F17_P_0,
2066   EVEX_W_0F17_P_2,
2067   EVEX_W_0F28_P_0,
2068   EVEX_W_0F28_P_2,
2069   EVEX_W_0F29_P_0,
2070   EVEX_W_0F29_P_2,
2071   EVEX_W_0F2A_P_3,
2072   EVEX_W_0F2B_P_0,
2073   EVEX_W_0F2B_P_2,
2074   EVEX_W_0F2E_P_0,
2075   EVEX_W_0F2E_P_2,
2076   EVEX_W_0F2F_P_0,
2077   EVEX_W_0F2F_P_2,
2078   EVEX_W_0F51_P_0,
2079   EVEX_W_0F51_P_1,
2080   EVEX_W_0F51_P_2,
2081   EVEX_W_0F51_P_3,
2082   EVEX_W_0F54_P_0,
2083   EVEX_W_0F54_P_2,
2084   EVEX_W_0F55_P_0,
2085   EVEX_W_0F55_P_2,
2086   EVEX_W_0F56_P_0,
2087   EVEX_W_0F56_P_2,
2088   EVEX_W_0F57_P_0,
2089   EVEX_W_0F57_P_2,
2090   EVEX_W_0F58_P_0,
2091   EVEX_W_0F58_P_1,
2092   EVEX_W_0F58_P_2,
2093   EVEX_W_0F58_P_3,
2094   EVEX_W_0F59_P_0,
2095   EVEX_W_0F59_P_1,
2096   EVEX_W_0F59_P_2,
2097   EVEX_W_0F59_P_3,
2098   EVEX_W_0F5A_P_0,
2099   EVEX_W_0F5A_P_1,
2100   EVEX_W_0F5A_P_2,
2101   EVEX_W_0F5A_P_3,
2102   EVEX_W_0F5B_P_0,
2103   EVEX_W_0F5B_P_1,
2104   EVEX_W_0F5B_P_2,
2105   EVEX_W_0F5C_P_0,
2106   EVEX_W_0F5C_P_1,
2107   EVEX_W_0F5C_P_2,
2108   EVEX_W_0F5C_P_3,
2109   EVEX_W_0F5D_P_0,
2110   EVEX_W_0F5D_P_1,
2111   EVEX_W_0F5D_P_2,
2112   EVEX_W_0F5D_P_3,
2113   EVEX_W_0F5E_P_0,
2114   EVEX_W_0F5E_P_1,
2115   EVEX_W_0F5E_P_2,
2116   EVEX_W_0F5E_P_3,
2117   EVEX_W_0F5F_P_0,
2118   EVEX_W_0F5F_P_1,
2119   EVEX_W_0F5F_P_2,
2120   EVEX_W_0F5F_P_3,
2121   EVEX_W_0F62_P_2,
2122   EVEX_W_0F66_P_2,
2123   EVEX_W_0F6A_P_2,
2124   EVEX_W_0F6B_P_2,
2125   EVEX_W_0F6C_P_2,
2126   EVEX_W_0F6D_P_2,
2127   EVEX_W_0F6F_P_1,
2128   EVEX_W_0F6F_P_2,
2129   EVEX_W_0F6F_P_3,
2130   EVEX_W_0F70_P_2,
2131   EVEX_W_0F72_R_2_P_2,
2132   EVEX_W_0F72_R_6_P_2,
2133   EVEX_W_0F73_R_2_P_2,
2134   EVEX_W_0F73_R_6_P_2,
2135   EVEX_W_0F76_P_2,
2136   EVEX_W_0F78_P_0,
2137   EVEX_W_0F78_P_2,
2138   EVEX_W_0F79_P_0,
2139   EVEX_W_0F79_P_2,
2140   EVEX_W_0F7A_P_1,
2141   EVEX_W_0F7A_P_2,
2142   EVEX_W_0F7A_P_3,
2143   EVEX_W_0F7B_P_2,
2144   EVEX_W_0F7B_P_3,
2145   EVEX_W_0F7E_P_1,
2146   EVEX_W_0F7F_P_1,
2147   EVEX_W_0F7F_P_2,
2148   EVEX_W_0F7F_P_3,
2149   EVEX_W_0FC2_P_0,
2150   EVEX_W_0FC2_P_1,
2151   EVEX_W_0FC2_P_2,
2152   EVEX_W_0FC2_P_3,
2153   EVEX_W_0FC6_P_0,
2154   EVEX_W_0FC6_P_2,
2155   EVEX_W_0FD2_P_2,
2156   EVEX_W_0FD3_P_2,
2157   EVEX_W_0FD4_P_2,
2158   EVEX_W_0FD6_P_2,
2159   EVEX_W_0FE6_P_1,
2160   EVEX_W_0FE6_P_2,
2161   EVEX_W_0FE6_P_3,
2162   EVEX_W_0FE7_P_2,
2163   EVEX_W_0FF2_P_2,
2164   EVEX_W_0FF3_P_2,
2165   EVEX_W_0FF4_P_2,
2166   EVEX_W_0FFA_P_2,
2167   EVEX_W_0FFB_P_2,
2168   EVEX_W_0FFE_P_2,
2169   EVEX_W_0F380C_P_2,
2170   EVEX_W_0F380D_P_2,
2171   EVEX_W_0F3810_P_1,
2172   EVEX_W_0F3810_P_2,
2173   EVEX_W_0F3811_P_1,
2174   EVEX_W_0F3811_P_2,
2175   EVEX_W_0F3812_P_1,
2176   EVEX_W_0F3812_P_2,
2177   EVEX_W_0F3813_P_1,
2178   EVEX_W_0F3813_P_2,
2179   EVEX_W_0F3814_P_1,
2180   EVEX_W_0F3815_P_1,
2181   EVEX_W_0F3818_P_2,
2182   EVEX_W_0F3819_P_2,
2183   EVEX_W_0F381A_P_2,
2184   EVEX_W_0F381B_P_2,
2185   EVEX_W_0F381E_P_2,
2186   EVEX_W_0F381F_P_2,
2187   EVEX_W_0F3820_P_1,
2188   EVEX_W_0F3821_P_1,
2189   EVEX_W_0F3822_P_1,
2190   EVEX_W_0F3823_P_1,
2191   EVEX_W_0F3824_P_1,
2192   EVEX_W_0F3825_P_1,
2193   EVEX_W_0F3825_P_2,
2194   EVEX_W_0F3826_P_1,
2195   EVEX_W_0F3826_P_2,
2196   EVEX_W_0F3828_P_1,
2197   EVEX_W_0F3828_P_2,
2198   EVEX_W_0F3829_P_1,
2199   EVEX_W_0F3829_P_2,
2200   EVEX_W_0F382A_P_1,
2201   EVEX_W_0F382A_P_2,
2202   EVEX_W_0F382B_P_2,
2203   EVEX_W_0F3830_P_1,
2204   EVEX_W_0F3831_P_1,
2205   EVEX_W_0F3832_P_1,
2206   EVEX_W_0F3833_P_1,
2207   EVEX_W_0F3834_P_1,
2208   EVEX_W_0F3835_P_1,
2209   EVEX_W_0F3835_P_2,
2210   EVEX_W_0F3837_P_2,
2211   EVEX_W_0F3838_P_1,
2212   EVEX_W_0F3839_P_1,
2213   EVEX_W_0F383A_P_1,
2214   EVEX_W_0F3840_P_2,
2215   EVEX_W_0F3852_P_1,
2216   EVEX_W_0F3854_P_2,
2217   EVEX_W_0F3855_P_2,
2218   EVEX_W_0F3858_P_2,
2219   EVEX_W_0F3859_P_2,
2220   EVEX_W_0F385A_P_2,
2221   EVEX_W_0F385B_P_2,
2222   EVEX_W_0F3862_P_2,
2223   EVEX_W_0F3863_P_2,
2224   EVEX_W_0F3866_P_2,
2225   EVEX_W_0F3868_P_3,
2226   EVEX_W_0F3870_P_2,
2227   EVEX_W_0F3871_P_2,
2228   EVEX_W_0F3872_P_1,
2229   EVEX_W_0F3872_P_2,
2230   EVEX_W_0F3872_P_3,
2231   EVEX_W_0F3873_P_2,
2232   EVEX_W_0F3875_P_2,
2233   EVEX_W_0F3878_P_2,
2234   EVEX_W_0F3879_P_2,
2235   EVEX_W_0F387A_P_2,
2236   EVEX_W_0F387B_P_2,
2237   EVEX_W_0F387D_P_2,
2238   EVEX_W_0F3883_P_2,
2239   EVEX_W_0F388D_P_2,
2240   EVEX_W_0F3891_P_2,
2241   EVEX_W_0F3893_P_2,
2242   EVEX_W_0F38A1_P_2,
2243   EVEX_W_0F38A3_P_2,
2244   EVEX_W_0F38C7_R_1_P_2,
2245   EVEX_W_0F38C7_R_2_P_2,
2246   EVEX_W_0F38C7_R_5_P_2,
2247   EVEX_W_0F38C7_R_6_P_2,
2248
2249   EVEX_W_0F3A00_P_2,
2250   EVEX_W_0F3A01_P_2,
2251   EVEX_W_0F3A04_P_2,
2252   EVEX_W_0F3A05_P_2,
2253   EVEX_W_0F3A08_P_2,
2254   EVEX_W_0F3A09_P_2,
2255   EVEX_W_0F3A0A_P_2,
2256   EVEX_W_0F3A0B_P_2,
2257   EVEX_W_0F3A18_P_2,
2258   EVEX_W_0F3A19_P_2,
2259   EVEX_W_0F3A1A_P_2,
2260   EVEX_W_0F3A1B_P_2,
2261   EVEX_W_0F3A1D_P_2,
2262   EVEX_W_0F3A21_P_2,
2263   EVEX_W_0F3A23_P_2,
2264   EVEX_W_0F3A38_P_2,
2265   EVEX_W_0F3A39_P_2,
2266   EVEX_W_0F3A3A_P_2,
2267   EVEX_W_0F3A3B_P_2,
2268   EVEX_W_0F3A3E_P_2,
2269   EVEX_W_0F3A3F_P_2,
2270   EVEX_W_0F3A42_P_2,
2271   EVEX_W_0F3A43_P_2,
2272   EVEX_W_0F3A50_P_2,
2273   EVEX_W_0F3A51_P_2,
2274   EVEX_W_0F3A56_P_2,
2275   EVEX_W_0F3A57_P_2,
2276   EVEX_W_0F3A66_P_2,
2277   EVEX_W_0F3A67_P_2,
2278   EVEX_W_0F3A70_P_2,
2279   EVEX_W_0F3A71_P_2,
2280   EVEX_W_0F3A72_P_2,
2281   EVEX_W_0F3A73_P_2,
2282   EVEX_W_0F3ACE_P_2,
2283   EVEX_W_0F3ACF_P_2
2284 };
2285
2286 typedef void (*op_rtn) (int bytemode, int sizeflag);
2287
2288 struct dis386 {
2289   const char *name;
2290   struct
2291     {
2292       op_rtn rtn;
2293       int bytemode;
2294     } op[MAX_OPERANDS];
2295   unsigned int prefix_requirement;
2296 };
2297
2298 /* Upper case letters in the instruction names here are macros.
2299    'A' => print 'b' if no register operands or suffix_always is true
2300    'B' => print 'b' if suffix_always is true
2301    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2302           size prefix
2303    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2304           suffix_always is true
2305    'E' => print 'e' if 32-bit form of jcxz
2306    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2307    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2308    'H' => print ",pt" or ",pn" branch hint
2309    'I' => honor following macro letter even in Intel mode (implemented only
2310           for some of the macro letters)
2311    'J' => print 'l'
2312    'K' => print 'd' or 'q' if rex prefix is present.
2313    'L' => print 'l' if suffix_always is true
2314    'M' => print 'r' if intel_mnemonic is false.
2315    'N' => print 'n' if instruction has no wait "prefix"
2316    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2317    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2318           or suffix_always is true.  print 'q' if rex prefix is present.
2319    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2320           is true
2321    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2322    'S' => print 'w', 'l' or 'q' if suffix_always is true
2323    'T' => print 'q' in 64bit mode if instruction has no operand size
2324           prefix and behave as 'P' otherwise
2325    'U' => print 'q' in 64bit mode if instruction has no operand size
2326           prefix and behave as 'Q' otherwise
2327    'V' => print 'q' in 64bit mode if instruction has no operand size
2328           prefix and behave as 'S' otherwise
2329    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2330    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2331    'Y' unused.
2332    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2333    '!' => change condition from true to false or from false to true.
2334    '%' => add 1 upper case letter to the macro.
2335    '^' => print 'w' or 'l' depending on operand size prefix or
2336           suffix_always is true (lcall/ljmp).
2337    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2338           on operand size prefix.
2339    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2340           has no operand size prefix for AMD64 ISA, behave as 'P'
2341           otherwise
2342
2343    2 upper case letter macros:
2344    "XY" => print 'x' or 'y' if suffix_always is true or no register
2345            operands and no broadcast.
2346    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2347            register operands and no broadcast.
2348    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2349    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2350            or suffix_always is true
2351    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2352    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2353    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2354    "LW" => print 'd', 'q' depending on the VEX.W bit
2355    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2356            an operand size prefix, or suffix_always is true.  print
2357            'q' if rex prefix is present.
2358
2359    Many of the above letters print nothing in Intel mode.  See "putop"
2360    for the details.
2361
2362    Braces '{' and '}', and vertical bars '|', indicate alternative
2363    mnemonic strings for AT&T and Intel.  */
2364
2365 static const struct dis386 dis386[] = {
2366   /* 00 */
2367   { "addB",             { Ebh1, Gb }, 0 },
2368   { "addS",             { Evh1, Gv }, 0 },
2369   { "addB",             { Gb, EbS }, 0 },
2370   { "addS",             { Gv, EvS }, 0 },
2371   { "addB",             { AL, Ib }, 0 },
2372   { "addS",             { eAX, Iv }, 0 },
2373   { X86_64_TABLE (X86_64_06) },
2374   { X86_64_TABLE (X86_64_07) },
2375   /* 08 */
2376   { "orB",              { Ebh1, Gb }, 0 },
2377   { "orS",              { Evh1, Gv }, 0 },
2378   { "orB",              { Gb, EbS }, 0 },
2379   { "orS",              { Gv, EvS }, 0 },
2380   { "orB",              { AL, Ib }, 0 },
2381   { "orS",              { eAX, Iv }, 0 },
2382   { X86_64_TABLE (X86_64_0D) },
2383   { Bad_Opcode },       /* 0x0f extended opcode escape */
2384   /* 10 */
2385   { "adcB",             { Ebh1, Gb }, 0 },
2386   { "adcS",             { Evh1, Gv }, 0 },
2387   { "adcB",             { Gb, EbS }, 0 },
2388   { "adcS",             { Gv, EvS }, 0 },
2389   { "adcB",             { AL, Ib }, 0 },
2390   { "adcS",             { eAX, Iv }, 0 },
2391   { X86_64_TABLE (X86_64_16) },
2392   { X86_64_TABLE (X86_64_17) },
2393   /* 18 */
2394   { "sbbB",             { Ebh1, Gb }, 0 },
2395   { "sbbS",             { Evh1, Gv }, 0 },
2396   { "sbbB",             { Gb, EbS }, 0 },
2397   { "sbbS",             { Gv, EvS }, 0 },
2398   { "sbbB",             { AL, Ib }, 0 },
2399   { "sbbS",             { eAX, Iv }, 0 },
2400   { X86_64_TABLE (X86_64_1E) },
2401   { X86_64_TABLE (X86_64_1F) },
2402   /* 20 */
2403   { "andB",             { Ebh1, Gb }, 0 },
2404   { "andS",             { Evh1, Gv }, 0 },
2405   { "andB",             { Gb, EbS }, 0 },
2406   { "andS",             { Gv, EvS }, 0 },
2407   { "andB",             { AL, Ib }, 0 },
2408   { "andS",             { eAX, Iv }, 0 },
2409   { Bad_Opcode },       /* SEG ES prefix */
2410   { X86_64_TABLE (X86_64_27) },
2411   /* 28 */
2412   { "subB",             { Ebh1, Gb }, 0 },
2413   { "subS",             { Evh1, Gv }, 0 },
2414   { "subB",             { Gb, EbS }, 0 },
2415   { "subS",             { Gv, EvS }, 0 },
2416   { "subB",             { AL, Ib }, 0 },
2417   { "subS",             { eAX, Iv }, 0 },
2418   { Bad_Opcode },       /* SEG CS prefix */
2419   { X86_64_TABLE (X86_64_2F) },
2420   /* 30 */
2421   { "xorB",             { Ebh1, Gb }, 0 },
2422   { "xorS",             { Evh1, Gv }, 0 },
2423   { "xorB",             { Gb, EbS }, 0 },
2424   { "xorS",             { Gv, EvS }, 0 },
2425   { "xorB",             { AL, Ib }, 0 },
2426   { "xorS",             { eAX, Iv }, 0 },
2427   { Bad_Opcode },       /* SEG SS prefix */
2428   { X86_64_TABLE (X86_64_37) },
2429   /* 38 */
2430   { "cmpB",             { Eb, Gb }, 0 },
2431   { "cmpS",             { Ev, Gv }, 0 },
2432   { "cmpB",             { Gb, EbS }, 0 },
2433   { "cmpS",             { Gv, EvS }, 0 },
2434   { "cmpB",             { AL, Ib }, 0 },
2435   { "cmpS",             { eAX, Iv }, 0 },
2436   { Bad_Opcode },       /* SEG DS prefix */
2437   { X86_64_TABLE (X86_64_3F) },
2438   /* 40 */
2439   { "inc{S|}",          { RMeAX }, 0 },
2440   { "inc{S|}",          { RMeCX }, 0 },
2441   { "inc{S|}",          { RMeDX }, 0 },
2442   { "inc{S|}",          { RMeBX }, 0 },
2443   { "inc{S|}",          { RMeSP }, 0 },
2444   { "inc{S|}",          { RMeBP }, 0 },
2445   { "inc{S|}",          { RMeSI }, 0 },
2446   { "inc{S|}",          { RMeDI }, 0 },
2447   /* 48 */
2448   { "dec{S|}",          { RMeAX }, 0 },
2449   { "dec{S|}",          { RMeCX }, 0 },
2450   { "dec{S|}",          { RMeDX }, 0 },
2451   { "dec{S|}",          { RMeBX }, 0 },
2452   { "dec{S|}",          { RMeSP }, 0 },
2453   { "dec{S|}",          { RMeBP }, 0 },
2454   { "dec{S|}",          { RMeSI }, 0 },
2455   { "dec{S|}",          { RMeDI }, 0 },
2456   /* 50 */
2457   { "pushV",            { RMrAX }, 0 },
2458   { "pushV",            { RMrCX }, 0 },
2459   { "pushV",            { RMrDX }, 0 },
2460   { "pushV",            { RMrBX }, 0 },
2461   { "pushV",            { RMrSP }, 0 },
2462   { "pushV",            { RMrBP }, 0 },
2463   { "pushV",            { RMrSI }, 0 },
2464   { "pushV",            { RMrDI }, 0 },
2465   /* 58 */
2466   { "popV",             { RMrAX }, 0 },
2467   { "popV",             { RMrCX }, 0 },
2468   { "popV",             { RMrDX }, 0 },
2469   { "popV",             { RMrBX }, 0 },
2470   { "popV",             { RMrSP }, 0 },
2471   { "popV",             { RMrBP }, 0 },
2472   { "popV",             { RMrSI }, 0 },
2473   { "popV",             { RMrDI }, 0 },
2474   /* 60 */
2475   { X86_64_TABLE (X86_64_60) },
2476   { X86_64_TABLE (X86_64_61) },
2477   { X86_64_TABLE (X86_64_62) },
2478   { X86_64_TABLE (X86_64_63) },
2479   { Bad_Opcode },       /* seg fs */
2480   { Bad_Opcode },       /* seg gs */
2481   { Bad_Opcode },       /* op size prefix */
2482   { Bad_Opcode },       /* adr size prefix */
2483   /* 68 */
2484   { "pushT",            { sIv }, 0 },
2485   { "imulS",            { Gv, Ev, Iv }, 0 },
2486   { "pushT",            { sIbT }, 0 },
2487   { "imulS",            { Gv, Ev, sIb }, 0 },
2488   { "ins{b|}",          { Ybr, indirDX }, 0 },
2489   { X86_64_TABLE (X86_64_6D) },
2490   { "outs{b|}",         { indirDXr, Xb }, 0 },
2491   { X86_64_TABLE (X86_64_6F) },
2492   /* 70 */
2493   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2494   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2495   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2496   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2497   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2498   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2499   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2500   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2501   /* 78 */
2502   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2503   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2504   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2505   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2506   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2507   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2508   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2509   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2510   /* 80 */
2511   { REG_TABLE (REG_80) },
2512   { REG_TABLE (REG_81) },
2513   { X86_64_TABLE (X86_64_82) },
2514   { REG_TABLE (REG_83) },
2515   { "testB",            { Eb, Gb }, 0 },
2516   { "testS",            { Ev, Gv }, 0 },
2517   { "xchgB",            { Ebh2, Gb }, 0 },
2518   { "xchgS",            { Evh2, Gv }, 0 },
2519   /* 88 */
2520   { "movB",             { Ebh3, Gb }, 0 },
2521   { "movS",             { Evh3, Gv }, 0 },
2522   { "movB",             { Gb, EbS }, 0 },
2523   { "movS",             { Gv, EvS }, 0 },
2524   { "movD",             { Sv, Sw }, 0 },
2525   { MOD_TABLE (MOD_8D) },
2526   { "movD",             { Sw, Sv }, 0 },
2527   { REG_TABLE (REG_8F) },
2528   /* 90 */
2529   { PREFIX_TABLE (PREFIX_90) },
2530   { "xchgS",            { RMeCX, eAX }, 0 },
2531   { "xchgS",            { RMeDX, eAX }, 0 },
2532   { "xchgS",            { RMeBX, eAX }, 0 },
2533   { "xchgS",            { RMeSP, eAX }, 0 },
2534   { "xchgS",            { RMeBP, eAX }, 0 },
2535   { "xchgS",            { RMeSI, eAX }, 0 },
2536   { "xchgS",            { RMeDI, eAX }, 0 },
2537   /* 98 */
2538   { "cW{t|}R",          { XX }, 0 },
2539   { "cR{t|}O",          { XX }, 0 },
2540   { X86_64_TABLE (X86_64_9A) },
2541   { Bad_Opcode },       /* fwait */
2542   { "pushfT",           { XX }, 0 },
2543   { "popfT",            { XX }, 0 },
2544   { "sahf",             { XX }, 0 },
2545   { "lahf",             { XX }, 0 },
2546   /* a0 */
2547   { "mov%LB",           { AL, Ob }, 0 },
2548   { "mov%LS",           { eAX, Ov }, 0 },
2549   { "mov%LB",           { Ob, AL }, 0 },
2550   { "mov%LS",           { Ov, eAX }, 0 },
2551   { "movs{b|}",         { Ybr, Xb }, 0 },
2552   { "movs{R|}",         { Yvr, Xv }, 0 },
2553   { "cmps{b|}",         { Xb, Yb }, 0 },
2554   { "cmps{R|}",         { Xv, Yv }, 0 },
2555   /* a8 */
2556   { "testB",            { AL, Ib }, 0 },
2557   { "testS",            { eAX, Iv }, 0 },
2558   { "stosB",            { Ybr, AL }, 0 },
2559   { "stosS",            { Yvr, eAX }, 0 },
2560   { "lodsB",            { ALr, Xb }, 0 },
2561   { "lodsS",            { eAXr, Xv }, 0 },
2562   { "scasB",            { AL, Yb }, 0 },
2563   { "scasS",            { eAX, Yv }, 0 },
2564   /* b0 */
2565   { "movB",             { RMAL, Ib }, 0 },
2566   { "movB",             { RMCL, Ib }, 0 },
2567   { "movB",             { RMDL, Ib }, 0 },
2568   { "movB",             { RMBL, Ib }, 0 },
2569   { "movB",             { RMAH, Ib }, 0 },
2570   { "movB",             { RMCH, Ib }, 0 },
2571   { "movB",             { RMDH, Ib }, 0 },
2572   { "movB",             { RMBH, Ib }, 0 },
2573   /* b8 */
2574   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2575   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2576   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2577   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2578   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2579   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2580   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2581   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2582   /* c0 */
2583   { REG_TABLE (REG_C0) },
2584   { REG_TABLE (REG_C1) },
2585   { "retT",             { Iw, BND }, 0 },
2586   { "retT",             { BND }, 0 },
2587   { X86_64_TABLE (X86_64_C4) },
2588   { X86_64_TABLE (X86_64_C5) },
2589   { REG_TABLE (REG_C6) },
2590   { REG_TABLE (REG_C7) },
2591   /* c8 */
2592   { "enterT",           { Iw, Ib }, 0 },
2593   { "leaveT",           { XX }, 0 },
2594   { "Jret{|f}P",        { Iw }, 0 },
2595   { "Jret{|f}P",        { XX }, 0 },
2596   { "int3",             { XX }, 0 },
2597   { "int",              { Ib }, 0 },
2598   { X86_64_TABLE (X86_64_CE) },
2599   { "iret%LP",          { XX }, 0 },
2600   /* d0 */
2601   { REG_TABLE (REG_D0) },
2602   { REG_TABLE (REG_D1) },
2603   { REG_TABLE (REG_D2) },
2604   { REG_TABLE (REG_D3) },
2605   { X86_64_TABLE (X86_64_D4) },
2606   { X86_64_TABLE (X86_64_D5) },
2607   { Bad_Opcode },
2608   { "xlat",             { DSBX }, 0 },
2609   /* d8 */
2610   { FLOAT },
2611   { FLOAT },
2612   { FLOAT },
2613   { FLOAT },
2614   { FLOAT },
2615   { FLOAT },
2616   { FLOAT },
2617   { FLOAT },
2618   /* e0 */
2619   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2620   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2621   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2622   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2623   { "inB",              { AL, Ib }, 0 },
2624   { "inG",              { zAX, Ib }, 0 },
2625   { "outB",             { Ib, AL }, 0 },
2626   { "outG",             { Ib, zAX }, 0 },
2627   /* e8 */
2628   { X86_64_TABLE (X86_64_E8) },
2629   { X86_64_TABLE (X86_64_E9) },
2630   { X86_64_TABLE (X86_64_EA) },
2631   { "jmp",              { Jb, BND }, 0 },
2632   { "inB",              { AL, indirDX }, 0 },
2633   { "inG",              { zAX, indirDX }, 0 },
2634   { "outB",             { indirDX, AL }, 0 },
2635   { "outG",             { indirDX, zAX }, 0 },
2636   /* f0 */
2637   { Bad_Opcode },       /* lock prefix */
2638   { "icebp",            { XX }, 0 },
2639   { Bad_Opcode },       /* repne */
2640   { Bad_Opcode },       /* repz */
2641   { "hlt",              { XX }, 0 },
2642   { "cmc",              { XX }, 0 },
2643   { REG_TABLE (REG_F6) },
2644   { REG_TABLE (REG_F7) },
2645   /* f8 */
2646   { "clc",              { XX }, 0 },
2647   { "stc",              { XX }, 0 },
2648   { "cli",              { XX }, 0 },
2649   { "sti",              { XX }, 0 },
2650   { "cld",              { XX }, 0 },
2651   { "std",              { XX }, 0 },
2652   { REG_TABLE (REG_FE) },
2653   { REG_TABLE (REG_FF) },
2654 };
2655
2656 static const struct dis386 dis386_twobyte[] = {
2657   /* 00 */
2658   { REG_TABLE (REG_0F00 ) },
2659   { REG_TABLE (REG_0F01 ) },
2660   { "larS",             { Gv, Ew }, 0 },
2661   { "lslS",             { Gv, Ew }, 0 },
2662   { Bad_Opcode },
2663   { "syscall",          { XX }, 0 },
2664   { "clts",             { XX }, 0 },
2665   { "sysret%LP",                { XX }, 0 },
2666   /* 08 */
2667   { "invd",             { XX }, 0 },
2668   { PREFIX_TABLE (PREFIX_0F09) },
2669   { Bad_Opcode },
2670   { "ud2",              { XX }, 0 },
2671   { Bad_Opcode },
2672   { REG_TABLE (REG_0F0D) },
2673   { "femms",            { XX }, 0 },
2674   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2675   /* 10 */
2676   { PREFIX_TABLE (PREFIX_0F10) },
2677   { PREFIX_TABLE (PREFIX_0F11) },
2678   { PREFIX_TABLE (PREFIX_0F12) },
2679   { MOD_TABLE (MOD_0F13) },
2680   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2681   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2682   { PREFIX_TABLE (PREFIX_0F16) },
2683   { MOD_TABLE (MOD_0F17) },
2684   /* 18 */
2685   { REG_TABLE (REG_0F18) },
2686   { "nopQ",             { Ev }, 0 },
2687   { PREFIX_TABLE (PREFIX_0F1A) },
2688   { PREFIX_TABLE (PREFIX_0F1B) },
2689   { PREFIX_TABLE (PREFIX_0F1C) },
2690   { "nopQ",             { Ev }, 0 },
2691   { PREFIX_TABLE (PREFIX_0F1E) },
2692   { "nopQ",             { Ev }, 0 },
2693   /* 20 */
2694   { "movZ",             { Rm, Cm }, 0 },
2695   { "movZ",             { Rm, Dm }, 0 },
2696   { "movZ",             { Cm, Rm }, 0 },
2697   { "movZ",             { Dm, Rm }, 0 },
2698   { MOD_TABLE (MOD_0F24) },
2699   { Bad_Opcode },
2700   { MOD_TABLE (MOD_0F26) },
2701   { Bad_Opcode },
2702   /* 28 */
2703   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2704   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2705   { PREFIX_TABLE (PREFIX_0F2A) },
2706   { PREFIX_TABLE (PREFIX_0F2B) },
2707   { PREFIX_TABLE (PREFIX_0F2C) },
2708   { PREFIX_TABLE (PREFIX_0F2D) },
2709   { PREFIX_TABLE (PREFIX_0F2E) },
2710   { PREFIX_TABLE (PREFIX_0F2F) },
2711   /* 30 */
2712   { "wrmsr",            { XX }, 0 },
2713   { "rdtsc",            { XX }, 0 },
2714   { "rdmsr",            { XX }, 0 },
2715   { "rdpmc",            { XX }, 0 },
2716   { "sysenter",         { XX }, 0 },
2717   { "sysexit",          { XX }, 0 },
2718   { Bad_Opcode },
2719   { "getsec",           { XX }, 0 },
2720   /* 38 */
2721   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2722   { Bad_Opcode },
2723   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2724   { Bad_Opcode },
2725   { Bad_Opcode },
2726   { Bad_Opcode },
2727   { Bad_Opcode },
2728   { Bad_Opcode },
2729   /* 40 */
2730   { "cmovoS",           { Gv, Ev }, 0 },
2731   { "cmovnoS",          { Gv, Ev }, 0 },
2732   { "cmovbS",           { Gv, Ev }, 0 },
2733   { "cmovaeS",          { Gv, Ev }, 0 },
2734   { "cmoveS",           { Gv, Ev }, 0 },
2735   { "cmovneS",          { Gv, Ev }, 0 },
2736   { "cmovbeS",          { Gv, Ev }, 0 },
2737   { "cmovaS",           { Gv, Ev }, 0 },
2738   /* 48 */
2739   { "cmovsS",           { Gv, Ev }, 0 },
2740   { "cmovnsS",          { Gv, Ev }, 0 },
2741   { "cmovpS",           { Gv, Ev }, 0 },
2742   { "cmovnpS",          { Gv, Ev }, 0 },
2743   { "cmovlS",           { Gv, Ev }, 0 },
2744   { "cmovgeS",          { Gv, Ev }, 0 },
2745   { "cmovleS",          { Gv, Ev }, 0 },
2746   { "cmovgS",           { Gv, Ev }, 0 },
2747   /* 50 */
2748   { MOD_TABLE (MOD_0F51) },
2749   { PREFIX_TABLE (PREFIX_0F51) },
2750   { PREFIX_TABLE (PREFIX_0F52) },
2751   { PREFIX_TABLE (PREFIX_0F53) },
2752   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2753   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2754   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2755   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2756   /* 58 */
2757   { PREFIX_TABLE (PREFIX_0F58) },
2758   { PREFIX_TABLE (PREFIX_0F59) },
2759   { PREFIX_TABLE (PREFIX_0F5A) },
2760   { PREFIX_TABLE (PREFIX_0F5B) },
2761   { PREFIX_TABLE (PREFIX_0F5C) },
2762   { PREFIX_TABLE (PREFIX_0F5D) },
2763   { PREFIX_TABLE (PREFIX_0F5E) },
2764   { PREFIX_TABLE (PREFIX_0F5F) },
2765   /* 60 */
2766   { PREFIX_TABLE (PREFIX_0F60) },
2767   { PREFIX_TABLE (PREFIX_0F61) },
2768   { PREFIX_TABLE (PREFIX_0F62) },
2769   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2770   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2771   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2772   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2773   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2774   /* 68 */
2775   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2776   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2777   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2778   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2779   { PREFIX_TABLE (PREFIX_0F6C) },
2780   { PREFIX_TABLE (PREFIX_0F6D) },
2781   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2782   { PREFIX_TABLE (PREFIX_0F6F) },
2783   /* 70 */
2784   { PREFIX_TABLE (PREFIX_0F70) },
2785   { REG_TABLE (REG_0F71) },
2786   { REG_TABLE (REG_0F72) },
2787   { REG_TABLE (REG_0F73) },
2788   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2789   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2790   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2791   { "emms",             { XX }, PREFIX_OPCODE },
2792   /* 78 */
2793   { PREFIX_TABLE (PREFIX_0F78) },
2794   { PREFIX_TABLE (PREFIX_0F79) },
2795   { Bad_Opcode },
2796   { Bad_Opcode },
2797   { PREFIX_TABLE (PREFIX_0F7C) },
2798   { PREFIX_TABLE (PREFIX_0F7D) },
2799   { PREFIX_TABLE (PREFIX_0F7E) },
2800   { PREFIX_TABLE (PREFIX_0F7F) },
2801   /* 80 */
2802   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2803   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2804   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2805   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2806   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2807   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2808   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2809   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2810   /* 88 */
2811   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2812   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2813   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2814   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2815   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2816   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2817   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2818   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2819   /* 90 */
2820   { "seto",             { Eb }, 0 },
2821   { "setno",            { Eb }, 0 },
2822   { "setb",             { Eb }, 0 },
2823   { "setae",            { Eb }, 0 },
2824   { "sete",             { Eb }, 0 },
2825   { "setne",            { Eb }, 0 },
2826   { "setbe",            { Eb }, 0 },
2827   { "seta",             { Eb }, 0 },
2828   /* 98 */
2829   { "sets",             { Eb }, 0 },
2830   { "setns",            { Eb }, 0 },
2831   { "setp",             { Eb }, 0 },
2832   { "setnp",            { Eb }, 0 },
2833   { "setl",             { Eb }, 0 },
2834   { "setge",            { Eb }, 0 },
2835   { "setle",            { Eb }, 0 },
2836   { "setg",             { Eb }, 0 },
2837   /* a0 */
2838   { "pushT",            { fs }, 0 },
2839   { "popT",             { fs }, 0 },
2840   { "cpuid",            { XX }, 0 },
2841   { "btS",              { Ev, Gv }, 0 },
2842   { "shldS",            { Ev, Gv, Ib }, 0 },
2843   { "shldS",            { Ev, Gv, CL }, 0 },
2844   { REG_TABLE (REG_0FA6) },
2845   { REG_TABLE (REG_0FA7) },
2846   /* a8 */
2847   { "pushT",            { gs }, 0 },
2848   { "popT",             { gs }, 0 },
2849   { "rsm",              { XX }, 0 },
2850   { "btsS",             { Evh1, Gv }, 0 },
2851   { "shrdS",            { Ev, Gv, Ib }, 0 },
2852   { "shrdS",            { Ev, Gv, CL }, 0 },
2853   { REG_TABLE (REG_0FAE) },
2854   { "imulS",            { Gv, Ev }, 0 },
2855   /* b0 */
2856   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2857   { "cmpxchgS",         { Evh1, Gv }, 0 },
2858   { MOD_TABLE (MOD_0FB2) },
2859   { "btrS",             { Evh1, Gv }, 0 },
2860   { MOD_TABLE (MOD_0FB4) },
2861   { MOD_TABLE (MOD_0FB5) },
2862   { "movz{bR|x}",       { Gv, Eb }, 0 },
2863   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2864   /* b8 */
2865   { PREFIX_TABLE (PREFIX_0FB8) },
2866   { "ud1S",             { Gv, Ev }, 0 },
2867   { REG_TABLE (REG_0FBA) },
2868   { "btcS",             { Evh1, Gv }, 0 },
2869   { PREFIX_TABLE (PREFIX_0FBC) },
2870   { PREFIX_TABLE (PREFIX_0FBD) },
2871   { "movs{bR|x}",       { Gv, Eb }, 0 },
2872   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2873   /* c0 */
2874   { "xaddB",            { Ebh1, Gb }, 0 },
2875   { "xaddS",            { Evh1, Gv }, 0 },
2876   { PREFIX_TABLE (PREFIX_0FC2) },
2877   { MOD_TABLE (MOD_0FC3) },
2878   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2879   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2880   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2881   { REG_TABLE (REG_0FC7) },
2882   /* c8 */
2883   { "bswap",            { RMeAX }, 0 },
2884   { "bswap",            { RMeCX }, 0 },
2885   { "bswap",            { RMeDX }, 0 },
2886   { "bswap",            { RMeBX }, 0 },
2887   { "bswap",            { RMeSP }, 0 },
2888   { "bswap",            { RMeBP }, 0 },
2889   { "bswap",            { RMeSI }, 0 },
2890   { "bswap",            { RMeDI }, 0 },
2891   /* d0 */
2892   { PREFIX_TABLE (PREFIX_0FD0) },
2893   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2894   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2895   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2896   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2897   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2898   { PREFIX_TABLE (PREFIX_0FD6) },
2899   { MOD_TABLE (MOD_0FD7) },
2900   /* d8 */
2901   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2902   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2903   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2904   { "pand",             { MX, EM }, PREFIX_OPCODE },
2905   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2906   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2907   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2908   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2909   /* e0 */
2910   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2911   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2912   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2913   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2914   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2915   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2916   { PREFIX_TABLE (PREFIX_0FE6) },
2917   { PREFIX_TABLE (PREFIX_0FE7) },
2918   /* e8 */
2919   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2920   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2921   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2922   { "por",              { MX, EM }, PREFIX_OPCODE },
2923   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2924   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2925   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2926   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2927   /* f0 */
2928   { PREFIX_TABLE (PREFIX_0FF0) },
2929   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2930   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2931   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2932   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2933   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2934   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2935   { PREFIX_TABLE (PREFIX_0FF7) },
2936   /* f8 */
2937   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2938   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2939   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2940   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2941   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2942   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2943   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2944   { "ud0S",             { Gv, Ev }, 0 },
2945 };
2946
2947 static const unsigned char onebyte_has_modrm[256] = {
2948   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2949   /*       -------------------------------        */
2950   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2951   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2952   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2953   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2954   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2955   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2956   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2957   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2958   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2959   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2960   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2961   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2962   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2963   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2964   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2965   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2966   /*       -------------------------------        */
2967   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2968 };
2969
2970 static const unsigned char twobyte_has_modrm[256] = {
2971   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2972   /*       -------------------------------        */
2973   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2974   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2975   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2976   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2977   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2978   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2979   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2980   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2981   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2982   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2983   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2984   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2985   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2986   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2987   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2988   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2989   /*       -------------------------------        */
2990   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2991 };
2992
2993 static char obuf[100];
2994 static char *obufp;
2995 static char *mnemonicendp;
2996 static char scratchbuf[100];
2997 static unsigned char *start_codep;
2998 static unsigned char *insn_codep;
2999 static unsigned char *codep;
3000 static unsigned char *end_codep;
3001 static int last_lock_prefix;
3002 static int last_repz_prefix;
3003 static int last_repnz_prefix;
3004 static int last_data_prefix;
3005 static int last_addr_prefix;
3006 static int last_rex_prefix;
3007 static int last_seg_prefix;
3008 static int fwait_prefix;
3009 /* The active segment register prefix.  */
3010 static int active_seg_prefix;
3011 #define MAX_CODE_LENGTH 15
3012 /* We can up to 14 prefixes since the maximum instruction length is
3013    15bytes.  */
3014 static int all_prefixes[MAX_CODE_LENGTH - 1];
3015 static disassemble_info *the_info;
3016 static struct
3017   {
3018     int mod;
3019     int reg;
3020     int rm;
3021   }
3022 modrm;
3023 static unsigned char need_modrm;
3024 static struct
3025   {
3026     int scale;
3027     int index;
3028     int base;
3029   }
3030 sib;
3031 static struct
3032   {
3033     int register_specifier;
3034     int length;
3035     int prefix;
3036     int w;
3037     int evex;
3038     int r;
3039     int v;
3040     int mask_register_specifier;
3041     int zeroing;
3042     int ll;
3043     int b;
3044   }
3045 vex;
3046 static unsigned char need_vex;
3047 static unsigned char need_vex_reg;
3048 static unsigned char vex_w_done;
3049
3050 struct op
3051   {
3052     const char *name;
3053     unsigned int len;
3054   };
3055
3056 /* If we are accessing mod/rm/reg without need_modrm set, then the
3057    values are stale.  Hitting this abort likely indicates that you
3058    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3059 #define MODRM_CHECK  if (!need_modrm) abort ()
3060
3061 static const char **names64;
3062 static const char **names32;
3063 static const char **names16;
3064 static const char **names8;
3065 static const char **names8rex;
3066 static const char **names_seg;
3067 static const char *index64;
3068 static const char *index32;
3069 static const char **index16;
3070 static const char **names_bnd;
3071
3072 static const char *intel_names64[] = {
3073   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3074   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3075 };
3076 static const char *intel_names32[] = {
3077   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3078   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3079 };
3080 static const char *intel_names16[] = {
3081   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3082   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3083 };
3084 static const char *intel_names8[] = {
3085   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3086 };
3087 static const char *intel_names8rex[] = {
3088   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3089   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3090 };
3091 static const char *intel_names_seg[] = {
3092   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3093 };
3094 static const char *intel_index64 = "riz";
3095 static const char *intel_index32 = "eiz";
3096 static const char *intel_index16[] = {
3097   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3098 };
3099
3100 static const char *att_names64[] = {
3101   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3102   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3103 };
3104 static const char *att_names32[] = {
3105   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3106   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3107 };
3108 static const char *att_names16[] = {
3109   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3110   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3111 };
3112 static const char *att_names8[] = {
3113   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3114 };
3115 static const char *att_names8rex[] = {
3116   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3117   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3118 };
3119 static const char *att_names_seg[] = {
3120   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3121 };
3122 static const char *att_index64 = "%riz";
3123 static const char *att_index32 = "%eiz";
3124 static const char *att_index16[] = {
3125   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3126 };
3127
3128 static const char **names_mm;
3129 static const char *intel_names_mm[] = {
3130   "mm0", "mm1", "mm2", "mm3",
3131   "mm4", "mm5", "mm6", "mm7"
3132 };
3133 static const char *att_names_mm[] = {
3134   "%mm0", "%mm1", "%mm2", "%mm3",
3135   "%mm4", "%mm5", "%mm6", "%mm7"
3136 };
3137
3138 static const char *intel_names_bnd[] = {
3139   "bnd0", "bnd1", "bnd2", "bnd3"
3140 };
3141
3142 static const char *att_names_bnd[] = {
3143   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3144 };
3145
3146 static const char **names_xmm;
3147 static const char *intel_names_xmm[] = {
3148   "xmm0", "xmm1", "xmm2", "xmm3",
3149   "xmm4", "xmm5", "xmm6", "xmm7",
3150   "xmm8", "xmm9", "xmm10", "xmm11",
3151   "xmm12", "xmm13", "xmm14", "xmm15",
3152   "xmm16", "xmm17", "xmm18", "xmm19",
3153   "xmm20", "xmm21", "xmm22", "xmm23",
3154   "xmm24", "xmm25", "xmm26", "xmm27",
3155   "xmm28", "xmm29", "xmm30", "xmm31"
3156 };
3157 static const char *att_names_xmm[] = {
3158   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3159   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3160   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3161   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3162   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3163   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3164   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3165   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3166 };
3167
3168 static const char **names_ymm;
3169 static const char *intel_names_ymm[] = {
3170   "ymm0", "ymm1", "ymm2", "ymm3",
3171   "ymm4", "ymm5", "ymm6", "ymm7",
3172   "ymm8", "ymm9", "ymm10", "ymm11",
3173   "ymm12", "ymm13", "ymm14", "ymm15",
3174   "ymm16", "ymm17", "ymm18", "ymm19",
3175   "ymm20", "ymm21", "ymm22", "ymm23",
3176   "ymm24", "ymm25", "ymm26", "ymm27",
3177   "ymm28", "ymm29", "ymm30", "ymm31"
3178 };
3179 static const char *att_names_ymm[] = {
3180   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3181   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3182   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3183   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3184   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3185   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3186   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3187   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3188 };
3189
3190 static const char **names_zmm;
3191 static const char *intel_names_zmm[] = {
3192   "zmm0", "zmm1", "zmm2", "zmm3",
3193   "zmm4", "zmm5", "zmm6", "zmm7",
3194   "zmm8", "zmm9", "zmm10", "zmm11",
3195   "zmm12", "zmm13", "zmm14", "zmm15",
3196   "zmm16", "zmm17", "zmm18", "zmm19",
3197   "zmm20", "zmm21", "zmm22", "zmm23",
3198   "zmm24", "zmm25", "zmm26", "zmm27",
3199   "zmm28", "zmm29", "zmm30", "zmm31"
3200 };
3201 static const char *att_names_zmm[] = {
3202   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3203   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3204   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3205   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3206   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3207   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3208   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3209   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3210 };
3211
3212 static const char **names_mask;
3213 static const char *intel_names_mask[] = {
3214   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3215 };
3216 static const char *att_names_mask[] = {
3217   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3218 };
3219
3220 static const char *names_rounding[] =
3221 {
3222   "{rn-sae}",
3223   "{rd-sae}",
3224   "{ru-sae}",
3225   "{rz-sae}"
3226 };
3227
3228 static const struct dis386 reg_table[][8] = {
3229   /* REG_80 */
3230   {
3231     { "addA",   { Ebh1, Ib }, 0 },
3232     { "orA",    { Ebh1, Ib }, 0 },
3233     { "adcA",   { Ebh1, Ib }, 0 },
3234     { "sbbA",   { Ebh1, Ib }, 0 },
3235     { "andA",   { Ebh1, Ib }, 0 },
3236     { "subA",   { Ebh1, Ib }, 0 },
3237     { "xorA",   { Ebh1, Ib }, 0 },
3238     { "cmpA",   { Eb, Ib }, 0 },
3239   },
3240   /* REG_81 */
3241   {
3242     { "addQ",   { Evh1, Iv }, 0 },
3243     { "orQ",    { Evh1, Iv }, 0 },
3244     { "adcQ",   { Evh1, Iv }, 0 },
3245     { "sbbQ",   { Evh1, Iv }, 0 },
3246     { "andQ",   { Evh1, Iv }, 0 },
3247     { "subQ",   { Evh1, Iv }, 0 },
3248     { "xorQ",   { Evh1, Iv }, 0 },
3249     { "cmpQ",   { Ev, Iv }, 0 },
3250   },
3251   /* REG_83 */
3252   {
3253     { "addQ",   { Evh1, sIb }, 0 },
3254     { "orQ",    { Evh1, sIb }, 0 },
3255     { "adcQ",   { Evh1, sIb }, 0 },
3256     { "sbbQ",   { Evh1, sIb }, 0 },
3257     { "andQ",   { Evh1, sIb }, 0 },
3258     { "subQ",   { Evh1, sIb }, 0 },
3259     { "xorQ",   { Evh1, sIb }, 0 },
3260     { "cmpQ",   { Ev, sIb }, 0 },
3261   },
3262   /* REG_8F */
3263   {
3264     { "popU",   { stackEv }, 0 },
3265     { XOP_8F_TABLE (XOP_09) },
3266     { Bad_Opcode },
3267     { Bad_Opcode },
3268     { Bad_Opcode },
3269     { XOP_8F_TABLE (XOP_09) },
3270   },
3271   /* REG_C0 */
3272   {
3273     { "rolA",   { Eb, Ib }, 0 },
3274     { "rorA",   { Eb, Ib }, 0 },
3275     { "rclA",   { Eb, Ib }, 0 },
3276     { "rcrA",   { Eb, Ib }, 0 },
3277     { "shlA",   { Eb, Ib }, 0 },
3278     { "shrA",   { Eb, Ib }, 0 },
3279     { "shlA",   { Eb, Ib }, 0 },
3280     { "sarA",   { Eb, Ib }, 0 },
3281   },
3282   /* REG_C1 */
3283   {
3284     { "rolQ",   { Ev, Ib }, 0 },
3285     { "rorQ",   { Ev, Ib }, 0 },
3286     { "rclQ",   { Ev, Ib }, 0 },
3287     { "rcrQ",   { Ev, Ib }, 0 },
3288     { "shlQ",   { Ev, Ib }, 0 },
3289     { "shrQ",   { Ev, Ib }, 0 },
3290     { "shlQ",   { Ev, Ib }, 0 },
3291     { "sarQ",   { Ev, Ib }, 0 },
3292   },
3293   /* REG_C6 */
3294   {
3295     { "movA",   { Ebh3, Ib }, 0 },
3296     { Bad_Opcode },
3297     { Bad_Opcode },
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { Bad_Opcode },
3301     { Bad_Opcode },
3302     { MOD_TABLE (MOD_C6_REG_7) },
3303   },
3304   /* REG_C7 */
3305   {
3306     { "movQ",   { Evh3, Iv }, 0 },
3307     { Bad_Opcode },
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { Bad_Opcode },
3311     { Bad_Opcode },
3312     { Bad_Opcode },
3313     { MOD_TABLE (MOD_C7_REG_7) },
3314   },
3315   /* REG_D0 */
3316   {
3317     { "rolA",   { Eb, I1 }, 0 },
3318     { "rorA",   { Eb, I1 }, 0 },
3319     { "rclA",   { Eb, I1 }, 0 },
3320     { "rcrA",   { Eb, I1 }, 0 },
3321     { "shlA",   { Eb, I1 }, 0 },
3322     { "shrA",   { Eb, I1 }, 0 },
3323     { "shlA",   { Eb, I1 }, 0 },
3324     { "sarA",   { Eb, I1 }, 0 },
3325   },
3326   /* REG_D1 */
3327   {
3328     { "rolQ",   { Ev, I1 }, 0 },
3329     { "rorQ",   { Ev, I1 }, 0 },
3330     { "rclQ",   { Ev, I1 }, 0 },
3331     { "rcrQ",   { Ev, I1 }, 0 },
3332     { "shlQ",   { Ev, I1 }, 0 },
3333     { "shrQ",   { Ev, I1 }, 0 },
3334     { "shlQ",   { Ev, I1 }, 0 },
3335     { "sarQ",   { Ev, I1 }, 0 },
3336   },
3337   /* REG_D2 */
3338   {
3339     { "rolA",   { Eb, CL }, 0 },
3340     { "rorA",   { Eb, CL }, 0 },
3341     { "rclA",   { Eb, CL }, 0 },
3342     { "rcrA",   { Eb, CL }, 0 },
3343     { "shlA",   { Eb, CL }, 0 },
3344     { "shrA",   { Eb, CL }, 0 },
3345     { "shlA",   { Eb, CL }, 0 },
3346     { "sarA",   { Eb, CL }, 0 },
3347   },
3348   /* REG_D3 */
3349   {
3350     { "rolQ",   { Ev, CL }, 0 },
3351     { "rorQ",   { Ev, CL }, 0 },
3352     { "rclQ",   { Ev, CL }, 0 },
3353     { "rcrQ",   { Ev, CL }, 0 },
3354     { "shlQ",   { Ev, CL }, 0 },
3355     { "shrQ",   { Ev, CL }, 0 },
3356     { "shlQ",   { Ev, CL }, 0 },
3357     { "sarQ",   { Ev, CL }, 0 },
3358   },
3359   /* REG_F6 */
3360   {
3361     { "testA",  { Eb, Ib }, 0 },
3362     { "testA",  { Eb, Ib }, 0 },
3363     { "notA",   { Ebh1 }, 0 },
3364     { "negA",   { Ebh1 }, 0 },
3365     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3366     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3367     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3368     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3369   },
3370   /* REG_F7 */
3371   {
3372     { "testQ",  { Ev, Iv }, 0 },
3373     { "testQ",  { Ev, Iv }, 0 },
3374     { "notQ",   { Evh1 }, 0 },
3375     { "negQ",   { Evh1 }, 0 },
3376     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3377     { "imulQ",  { Ev }, 0 },
3378     { "divQ",   { Ev }, 0 },
3379     { "idivQ",  { Ev }, 0 },
3380   },
3381   /* REG_FE */
3382   {
3383     { "incA",   { Ebh1 }, 0 },
3384     { "decA",   { Ebh1 }, 0 },
3385   },
3386   /* REG_FF */
3387   {
3388     { "incQ",   { Evh1 }, 0 },
3389     { "decQ",   { Evh1 }, 0 },
3390     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3391     { MOD_TABLE (MOD_FF_REG_3) },
3392     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3393     { MOD_TABLE (MOD_FF_REG_5) },
3394     { "pushU",  { stackEv }, 0 },
3395     { Bad_Opcode },
3396   },
3397   /* REG_0F00 */
3398   {
3399     { "sldtD",  { Sv }, 0 },
3400     { "strD",   { Sv }, 0 },
3401     { "lldt",   { Ew }, 0 },
3402     { "ltr",    { Ew }, 0 },
3403     { "verr",   { Ew }, 0 },
3404     { "verw",   { Ew }, 0 },
3405     { Bad_Opcode },
3406     { Bad_Opcode },
3407   },
3408   /* REG_0F01 */
3409   {
3410     { MOD_TABLE (MOD_0F01_REG_0) },
3411     { MOD_TABLE (MOD_0F01_REG_1) },
3412     { MOD_TABLE (MOD_0F01_REG_2) },
3413     { MOD_TABLE (MOD_0F01_REG_3) },
3414     { "smswD",  { Sv }, 0 },
3415     { MOD_TABLE (MOD_0F01_REG_5) },
3416     { "lmsw",   { Ew }, 0 },
3417     { MOD_TABLE (MOD_0F01_REG_7) },
3418   },
3419   /* REG_0F0D */
3420   {
3421     { "prefetch",       { Mb }, 0 },
3422     { "prefetchw",      { Mb }, 0 },
3423     { "prefetchwt1",    { Mb }, 0 },
3424     { "prefetch",       { Mb }, 0 },
3425     { "prefetch",       { Mb }, 0 },
3426     { "prefetch",       { Mb }, 0 },
3427     { "prefetch",       { Mb }, 0 },
3428     { "prefetch",       { Mb }, 0 },
3429   },
3430   /* REG_0F18 */
3431   {
3432     { MOD_TABLE (MOD_0F18_REG_0) },
3433     { MOD_TABLE (MOD_0F18_REG_1) },
3434     { MOD_TABLE (MOD_0F18_REG_2) },
3435     { MOD_TABLE (MOD_0F18_REG_3) },
3436     { MOD_TABLE (MOD_0F18_REG_4) },
3437     { MOD_TABLE (MOD_0F18_REG_5) },
3438     { MOD_TABLE (MOD_0F18_REG_6) },
3439     { MOD_TABLE (MOD_0F18_REG_7) },
3440   },
3441   /* REG_0F1C_P_0_MOD_0 */
3442   {
3443     { "cldemote",       { Mb }, 0 },
3444     { "nopQ",           { Ev }, 0 },
3445     { "nopQ",           { Ev }, 0 },
3446     { "nopQ",           { Ev }, 0 },
3447     { "nopQ",           { Ev }, 0 },
3448     { "nopQ",           { Ev }, 0 },
3449     { "nopQ",           { Ev }, 0 },
3450     { "nopQ",           { Ev }, 0 },
3451   },
3452   /* REG_0F1E_P_1_MOD_3 */
3453   {
3454     { "nopQ",           { Ev }, 0 },
3455     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3456     { "nopQ",           { Ev }, 0 },
3457     { "nopQ",           { Ev }, 0 },
3458     { "nopQ",           { Ev }, 0 },
3459     { "nopQ",           { Ev }, 0 },
3460     { "nopQ",           { Ev }, 0 },
3461     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3462   },
3463   /* REG_0F71 */
3464   {
3465     { Bad_Opcode },
3466     { Bad_Opcode },
3467     { MOD_TABLE (MOD_0F71_REG_2) },
3468     { Bad_Opcode },
3469     { MOD_TABLE (MOD_0F71_REG_4) },
3470     { Bad_Opcode },
3471     { MOD_TABLE (MOD_0F71_REG_6) },
3472   },
3473   /* REG_0F72 */
3474   {
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { MOD_TABLE (MOD_0F72_REG_2) },
3478     { Bad_Opcode },
3479     { MOD_TABLE (MOD_0F72_REG_4) },
3480     { Bad_Opcode },
3481     { MOD_TABLE (MOD_0F72_REG_6) },
3482   },
3483   /* REG_0F73 */
3484   {
3485     { Bad_Opcode },
3486     { Bad_Opcode },
3487     { MOD_TABLE (MOD_0F73_REG_2) },
3488     { MOD_TABLE (MOD_0F73_REG_3) },
3489     { Bad_Opcode },
3490     { Bad_Opcode },
3491     { MOD_TABLE (MOD_0F73_REG_6) },
3492     { MOD_TABLE (MOD_0F73_REG_7) },
3493   },
3494   /* REG_0FA6 */
3495   {
3496     { "montmul",        { { OP_0f07, 0 } }, 0 },
3497     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3498     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3499   },
3500   /* REG_0FA7 */
3501   {
3502     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3503     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3504     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3505     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3506     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3507     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3508   },
3509   /* REG_0FAE */
3510   {
3511     { MOD_TABLE (MOD_0FAE_REG_0) },
3512     { MOD_TABLE (MOD_0FAE_REG_1) },
3513     { MOD_TABLE (MOD_0FAE_REG_2) },
3514     { MOD_TABLE (MOD_0FAE_REG_3) },
3515     { MOD_TABLE (MOD_0FAE_REG_4) },
3516     { MOD_TABLE (MOD_0FAE_REG_5) },
3517     { MOD_TABLE (MOD_0FAE_REG_6) },
3518     { MOD_TABLE (MOD_0FAE_REG_7) },
3519   },
3520   /* REG_0FBA */
3521   {
3522     { Bad_Opcode },
3523     { Bad_Opcode },
3524     { Bad_Opcode },
3525     { Bad_Opcode },
3526     { "btQ",    { Ev, Ib }, 0 },
3527     { "btsQ",   { Evh1, Ib }, 0 },
3528     { "btrQ",   { Evh1, Ib }, 0 },
3529     { "btcQ",   { Evh1, Ib }, 0 },
3530   },
3531   /* REG_0FC7 */
3532   {
3533     { Bad_Opcode },
3534     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3535     { Bad_Opcode },
3536     { MOD_TABLE (MOD_0FC7_REG_3) },
3537     { MOD_TABLE (MOD_0FC7_REG_4) },
3538     { MOD_TABLE (MOD_0FC7_REG_5) },
3539     { MOD_TABLE (MOD_0FC7_REG_6) },
3540     { MOD_TABLE (MOD_0FC7_REG_7) },
3541   },
3542   /* REG_VEX_0F71 */
3543   {
3544     { Bad_Opcode },
3545     { Bad_Opcode },
3546     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3547     { Bad_Opcode },
3548     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3549     { Bad_Opcode },
3550     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3551   },
3552   /* REG_VEX_0F72 */
3553   {
3554     { Bad_Opcode },
3555     { Bad_Opcode },
3556     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3557     { Bad_Opcode },
3558     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3559     { Bad_Opcode },
3560     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3561   },
3562   /* REG_VEX_0F73 */
3563   {
3564     { Bad_Opcode },
3565     { Bad_Opcode },
3566     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3567     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3568     { Bad_Opcode },
3569     { Bad_Opcode },
3570     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3571     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3572   },
3573   /* REG_VEX_0FAE */
3574   {
3575     { Bad_Opcode },
3576     { Bad_Opcode },
3577     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3578     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3579   },
3580   /* REG_VEX_0F38F3 */
3581   {
3582     { Bad_Opcode },
3583     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3584     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3585     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3586   },
3587   /* REG_XOP_LWPCB */
3588   {
3589     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3590     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3591   },
3592   /* REG_XOP_LWP */
3593   {
3594     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3595     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3596   },
3597   /* REG_XOP_TBM_01 */
3598   {
3599     { Bad_Opcode },
3600     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3601     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3602     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3603     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3604     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3605     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3606     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3607   },
3608   /* REG_XOP_TBM_02 */
3609   {
3610     { Bad_Opcode },
3611     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3612     { Bad_Opcode },
3613     { Bad_Opcode },
3614     { Bad_Opcode },
3615     { Bad_Opcode },
3616     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3617   },
3618
3619 #include "i386-dis-evex-reg.h"
3620 };
3621
3622 static const struct dis386 prefix_table[][4] = {
3623   /* PREFIX_90 */
3624   {
3625     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3626     { "pause", { XX }, 0 },
3627     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3628     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3629   },
3630
3631   /* PREFIX_0F01_REG_5_MOD_0 */
3632   {
3633     { Bad_Opcode },
3634     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3635   },
3636
3637   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3638   {
3639     { Bad_Opcode },
3640     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3641   },
3642
3643   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3644   {
3645     { Bad_Opcode },
3646     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3647   },
3648
3649   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3650   {
3651     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3652     { "mcommit",        { Skip_MODRM }, 0 },
3653   },
3654
3655   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3656   {
3657     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3658   },
3659
3660   /* PREFIX_0F09 */
3661   {
3662     { "wbinvd",   { XX }, 0 },
3663     { "wbnoinvd", { XX }, 0 },
3664   },
3665
3666   /* PREFIX_0F10 */
3667   {
3668     { "movups", { XM, EXx }, PREFIX_OPCODE },
3669     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3670     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3671     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3672   },
3673
3674   /* PREFIX_0F11 */
3675   {
3676     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3677     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3678     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3679     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3680   },
3681
3682   /* PREFIX_0F12 */
3683   {
3684     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3685     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3686     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3687     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3688   },
3689
3690   /* PREFIX_0F16 */
3691   {
3692     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3693     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3694     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3695   },
3696
3697   /* PREFIX_0F1A */
3698   {
3699     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3700     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3701     { "bndmov", { Gbnd, Ebnd }, 0 },
3702     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3703   },
3704
3705   /* PREFIX_0F1B */
3706   {
3707     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3708     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3709     { "bndmov", { EbndS, Gbnd }, 0 },
3710     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3711   },
3712
3713   /* PREFIX_0F1C */
3714   {
3715     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3716     { "nopQ",   { Ev }, PREFIX_OPCODE },
3717     { "nopQ",   { Ev }, PREFIX_OPCODE },
3718     { "nopQ",   { Ev }, PREFIX_OPCODE },
3719   },
3720
3721   /* PREFIX_0F1E */
3722   {
3723     { "nopQ",   { Ev }, PREFIX_OPCODE },
3724     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3725     { "nopQ",   { Ev }, PREFIX_OPCODE },
3726     { "nopQ",   { Ev }, PREFIX_OPCODE },
3727   },
3728
3729   /* PREFIX_0F2A */
3730   {
3731     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3732     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3733     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3734     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3735   },
3736
3737   /* PREFIX_0F2B */
3738   {
3739     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3740     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3741     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3742     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3743   },
3744
3745   /* PREFIX_0F2C */
3746   {
3747     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3748     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3749     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3750     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3751   },
3752
3753   /* PREFIX_0F2D */
3754   {
3755     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3756     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3757     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3758     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3759   },
3760
3761   /* PREFIX_0F2E */
3762   {
3763     { "ucomiss",{ XM, EXd }, 0 },
3764     { Bad_Opcode },
3765     { "ucomisd",{ XM, EXq }, 0 },
3766   },
3767
3768   /* PREFIX_0F2F */
3769   {
3770     { "comiss", { XM, EXd }, 0 },
3771     { Bad_Opcode },
3772     { "comisd", { XM, EXq }, 0 },
3773   },
3774
3775   /* PREFIX_0F51 */
3776   {
3777     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3778     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3779     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3780     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3781   },
3782
3783   /* PREFIX_0F52 */
3784   {
3785     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3786     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3787   },
3788
3789   /* PREFIX_0F53 */
3790   {
3791     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3792     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3793   },
3794
3795   /* PREFIX_0F58 */
3796   {
3797     { "addps", { XM, EXx }, PREFIX_OPCODE },
3798     { "addss", { XM, EXd }, PREFIX_OPCODE },
3799     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3800     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3801   },
3802
3803   /* PREFIX_0F59 */
3804   {
3805     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3806     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3807     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3808     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3809   },
3810
3811   /* PREFIX_0F5A */
3812   {
3813     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3814     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3815     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3816     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3817   },
3818
3819   /* PREFIX_0F5B */
3820   {
3821     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3822     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3823     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3824   },
3825
3826   /* PREFIX_0F5C */
3827   {
3828     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3829     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3830     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3831     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3832   },
3833
3834   /* PREFIX_0F5D */
3835   {
3836     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3837     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3838     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3839     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3840   },
3841
3842   /* PREFIX_0F5E */
3843   {
3844     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3845     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3846     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3847     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3848   },
3849
3850   /* PREFIX_0F5F */
3851   {
3852     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3853     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3854     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3855     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3856   },
3857
3858   /* PREFIX_0F60 */
3859   {
3860     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3861     { Bad_Opcode },
3862     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3863   },
3864
3865   /* PREFIX_0F61 */
3866   {
3867     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3868     { Bad_Opcode },
3869     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3870   },
3871
3872   /* PREFIX_0F62 */
3873   {
3874     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3875     { Bad_Opcode },
3876     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3877   },
3878
3879   /* PREFIX_0F6C */
3880   {
3881     { Bad_Opcode },
3882     { Bad_Opcode },
3883     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3884   },
3885
3886   /* PREFIX_0F6D */
3887   {
3888     { Bad_Opcode },
3889     { Bad_Opcode },
3890     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3891   },
3892
3893   /* PREFIX_0F6F */
3894   {
3895     { "movq",   { MX, EM }, PREFIX_OPCODE },
3896     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3897     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3898   },
3899
3900   /* PREFIX_0F70 */
3901   {
3902     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3903     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3904     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3905     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3906   },
3907
3908   /* PREFIX_0F73_REG_3 */
3909   {
3910     { Bad_Opcode },
3911     { Bad_Opcode },
3912     { "psrldq", { XS, Ib }, 0 },
3913   },
3914
3915   /* PREFIX_0F73_REG_7 */
3916   {
3917     { Bad_Opcode },
3918     { Bad_Opcode },
3919     { "pslldq", { XS, Ib }, 0 },
3920   },
3921
3922   /* PREFIX_0F78 */
3923   {
3924     {"vmread",  { Em, Gm }, 0 },
3925     { Bad_Opcode },
3926     {"extrq",   { XS, Ib, Ib }, 0 },
3927     {"insertq", { XM, XS, Ib, Ib }, 0 },
3928   },
3929
3930   /* PREFIX_0F79 */
3931   {
3932     {"vmwrite", { Gm, Em }, 0 },
3933     { Bad_Opcode },
3934     {"extrq",   { XM, XS }, 0 },
3935     {"insertq", { XM, XS }, 0 },
3936   },
3937
3938   /* PREFIX_0F7C */
3939   {
3940     { Bad_Opcode },
3941     { Bad_Opcode },
3942     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3943     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3944   },
3945
3946   /* PREFIX_0F7D */
3947   {
3948     { Bad_Opcode },
3949     { Bad_Opcode },
3950     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3951     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3952   },
3953
3954   /* PREFIX_0F7E */
3955   {
3956     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3957     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3958     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3959   },
3960
3961   /* PREFIX_0F7F */
3962   {
3963     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3964     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3965     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3966   },
3967
3968   /* PREFIX_0FAE_REG_0_MOD_3 */
3969   {
3970     { Bad_Opcode },
3971     { "rdfsbase", { Ev }, 0 },
3972   },
3973
3974   /* PREFIX_0FAE_REG_1_MOD_3 */
3975   {
3976     { Bad_Opcode },
3977     { "rdgsbase", { Ev }, 0 },
3978   },
3979
3980   /* PREFIX_0FAE_REG_2_MOD_3 */
3981   {
3982     { Bad_Opcode },
3983     { "wrfsbase", { Ev }, 0 },
3984   },
3985
3986   /* PREFIX_0FAE_REG_3_MOD_3 */
3987   {
3988     { Bad_Opcode },
3989     { "wrgsbase", { Ev }, 0 },
3990   },
3991
3992   /* PREFIX_0FAE_REG_4_MOD_0 */
3993   {
3994     { "xsave",  { FXSAVE }, 0 },
3995     { "ptwrite%LQ", { Edq }, 0 },
3996   },
3997
3998   /* PREFIX_0FAE_REG_4_MOD_3 */
3999   {
4000     { Bad_Opcode },
4001     { "ptwrite%LQ", { Edq }, 0 },
4002   },
4003
4004   /* PREFIX_0FAE_REG_5_MOD_0 */
4005   {
4006     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4007   },
4008
4009   /* PREFIX_0FAE_REG_5_MOD_3 */
4010   {
4011     { "lfence",         { Skip_MODRM }, 0 },
4012     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4013   },
4014
4015   /* PREFIX_0FAE_REG_6_MOD_0 */
4016   {
4017     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4018     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4019     { "clwb",   { Mb }, PREFIX_OPCODE },
4020   },
4021
4022   /* PREFIX_0FAE_REG_6_MOD_3 */
4023   {
4024     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
4025     { "umonitor",       { Eva }, PREFIX_OPCODE },
4026     { "tpause", { Edq }, PREFIX_OPCODE },
4027     { "umwait", { Edq }, PREFIX_OPCODE },
4028   },
4029
4030   /* PREFIX_0FAE_REG_7_MOD_0 */
4031   {
4032     { "clflush",        { Mb }, 0 },
4033     { Bad_Opcode },
4034     { "clflushopt",     { Mb }, 0 },
4035   },
4036
4037   /* PREFIX_0FB8 */
4038   {
4039     { Bad_Opcode },
4040     { "popcntS", { Gv, Ev }, 0 },
4041   },
4042
4043   /* PREFIX_0FBC */
4044   {
4045     { "bsfS",   { Gv, Ev }, 0 },
4046     { "tzcntS", { Gv, Ev }, 0 },
4047     { "bsfS",   { Gv, Ev }, 0 },
4048   },
4049
4050   /* PREFIX_0FBD */
4051   {
4052     { "bsrS",   { Gv, Ev }, 0 },
4053     { "lzcntS", { Gv, Ev }, 0 },
4054     { "bsrS",   { Gv, Ev }, 0 },
4055   },
4056
4057   /* PREFIX_0FC2 */
4058   {
4059     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4060     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4061     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4062     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4063   },
4064
4065   /* PREFIX_0FC3_MOD_0 */
4066   {
4067     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4068   },
4069
4070   /* PREFIX_0FC7_REG_6_MOD_0 */
4071   {
4072     { "vmptrld",{ Mq }, 0 },
4073     { "vmxon",  { Mq }, 0 },
4074     { "vmclear",{ Mq }, 0 },
4075   },
4076
4077   /* PREFIX_0FC7_REG_6_MOD_3 */
4078   {
4079     { "rdrand", { Ev }, 0 },
4080     { Bad_Opcode },
4081     { "rdrand", { Ev }, 0 }
4082   },
4083
4084   /* PREFIX_0FC7_REG_7_MOD_3 */
4085   {
4086     { "rdseed", { Ev }, 0 },
4087     { "rdpid",  { Em }, 0 },
4088     { "rdseed", { Ev }, 0 },
4089   },
4090
4091   /* PREFIX_0FD0 */
4092   {
4093     { Bad_Opcode },
4094     { Bad_Opcode },
4095     { "addsubpd", { XM, EXx }, 0 },
4096     { "addsubps", { XM, EXx }, 0 },
4097   },
4098
4099   /* PREFIX_0FD6 */
4100   {
4101     { Bad_Opcode },
4102     { "movq2dq",{ XM, MS }, 0 },
4103     { "movq",   { EXqS, XM }, 0 },
4104     { "movdq2q",{ MX, XS }, 0 },
4105   },
4106
4107   /* PREFIX_0FE6 */
4108   {
4109     { Bad_Opcode },
4110     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4111     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4112     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4113   },
4114
4115   /* PREFIX_0FE7 */
4116   {
4117     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4118     { Bad_Opcode },
4119     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4120   },
4121
4122   /* PREFIX_0FF0 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { Bad_Opcode },
4127     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4128   },
4129
4130   /* PREFIX_0FF7 */
4131   {
4132     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4133     { Bad_Opcode },
4134     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4135   },
4136
4137   /* PREFIX_0F3810 */
4138   {
4139     { Bad_Opcode },
4140     { Bad_Opcode },
4141     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4142   },
4143
4144   /* PREFIX_0F3814 */
4145   {
4146     { Bad_Opcode },
4147     { Bad_Opcode },
4148     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4149   },
4150
4151   /* PREFIX_0F3815 */
4152   {
4153     { Bad_Opcode },
4154     { Bad_Opcode },
4155     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4156   },
4157
4158   /* PREFIX_0F3817 */
4159   {
4160     { Bad_Opcode },
4161     { Bad_Opcode },
4162     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4163   },
4164
4165   /* PREFIX_0F3820 */
4166   {
4167     { Bad_Opcode },
4168     { Bad_Opcode },
4169     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4170   },
4171
4172   /* PREFIX_0F3821 */
4173   {
4174     { Bad_Opcode },
4175     { Bad_Opcode },
4176     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4177   },
4178
4179   /* PREFIX_0F3822 */
4180   {
4181     { Bad_Opcode },
4182     { Bad_Opcode },
4183     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4184   },
4185
4186   /* PREFIX_0F3823 */
4187   {
4188     { Bad_Opcode },
4189     { Bad_Opcode },
4190     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4191   },
4192
4193   /* PREFIX_0F3824 */
4194   {
4195     { Bad_Opcode },
4196     { Bad_Opcode },
4197     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4198   },
4199
4200   /* PREFIX_0F3825 */
4201   {
4202     { Bad_Opcode },
4203     { Bad_Opcode },
4204     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4205   },
4206
4207   /* PREFIX_0F3828 */
4208   {
4209     { Bad_Opcode },
4210     { Bad_Opcode },
4211     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4212   },
4213
4214   /* PREFIX_0F3829 */
4215   {
4216     { Bad_Opcode },
4217     { Bad_Opcode },
4218     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4219   },
4220
4221   /* PREFIX_0F382A */
4222   {
4223     { Bad_Opcode },
4224     { Bad_Opcode },
4225     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4226   },
4227
4228   /* PREFIX_0F382B */
4229   {
4230     { Bad_Opcode },
4231     { Bad_Opcode },
4232     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4233   },
4234
4235   /* PREFIX_0F3830 */
4236   {
4237     { Bad_Opcode },
4238     { Bad_Opcode },
4239     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4240   },
4241
4242   /* PREFIX_0F3831 */
4243   {
4244     { Bad_Opcode },
4245     { Bad_Opcode },
4246     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4247   },
4248
4249   /* PREFIX_0F3832 */
4250   {
4251     { Bad_Opcode },
4252     { Bad_Opcode },
4253     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4254   },
4255
4256   /* PREFIX_0F3833 */
4257   {
4258     { Bad_Opcode },
4259     { Bad_Opcode },
4260     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4261   },
4262
4263   /* PREFIX_0F3834 */
4264   {
4265     { Bad_Opcode },
4266     { Bad_Opcode },
4267     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4268   },
4269
4270   /* PREFIX_0F3835 */
4271   {
4272     { Bad_Opcode },
4273     { Bad_Opcode },
4274     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4275   },
4276
4277   /* PREFIX_0F3837 */
4278   {
4279     { Bad_Opcode },
4280     { Bad_Opcode },
4281     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4282   },
4283
4284   /* PREFIX_0F3838 */
4285   {
4286     { Bad_Opcode },
4287     { Bad_Opcode },
4288     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4289   },
4290
4291   /* PREFIX_0F3839 */
4292   {
4293     { Bad_Opcode },
4294     { Bad_Opcode },
4295     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4296   },
4297
4298   /* PREFIX_0F383A */
4299   {
4300     { Bad_Opcode },
4301     { Bad_Opcode },
4302     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4303   },
4304
4305   /* PREFIX_0F383B */
4306   {
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4310   },
4311
4312   /* PREFIX_0F383C */
4313   {
4314     { Bad_Opcode },
4315     { Bad_Opcode },
4316     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4317   },
4318
4319   /* PREFIX_0F383D */
4320   {
4321     { Bad_Opcode },
4322     { Bad_Opcode },
4323     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4324   },
4325
4326   /* PREFIX_0F383E */
4327   {
4328     { Bad_Opcode },
4329     { Bad_Opcode },
4330     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4331   },
4332
4333   /* PREFIX_0F383F */
4334   {
4335     { Bad_Opcode },
4336     { Bad_Opcode },
4337     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4338   },
4339
4340   /* PREFIX_0F3840 */
4341   {
4342     { Bad_Opcode },
4343     { Bad_Opcode },
4344     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4345   },
4346
4347   /* PREFIX_0F3841 */
4348   {
4349     { Bad_Opcode },
4350     { Bad_Opcode },
4351     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4352   },
4353
4354   /* PREFIX_0F3880 */
4355   {
4356     { Bad_Opcode },
4357     { Bad_Opcode },
4358     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4359   },
4360
4361   /* PREFIX_0F3881 */
4362   {
4363     { Bad_Opcode },
4364     { Bad_Opcode },
4365     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4366   },
4367
4368   /* PREFIX_0F3882 */
4369   {
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4373   },
4374
4375   /* PREFIX_0F38C8 */
4376   {
4377     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4378   },
4379
4380   /* PREFIX_0F38C9 */
4381   {
4382     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4383   },
4384
4385   /* PREFIX_0F38CA */
4386   {
4387     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4388   },
4389
4390   /* PREFIX_0F38CB */
4391   {
4392     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4393   },
4394
4395   /* PREFIX_0F38CC */
4396   {
4397     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4398   },
4399
4400   /* PREFIX_0F38CD */
4401   {
4402     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4403   },
4404
4405   /* PREFIX_0F38CF */
4406   {
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4410   },
4411
4412   /* PREFIX_0F38DB */
4413   {
4414     { Bad_Opcode },
4415     { Bad_Opcode },
4416     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4417   },
4418
4419   /* PREFIX_0F38DC */
4420   {
4421     { Bad_Opcode },
4422     { Bad_Opcode },
4423     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4424   },
4425
4426   /* PREFIX_0F38DD */
4427   {
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4431   },
4432
4433   /* PREFIX_0F38DE */
4434   {
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4438   },
4439
4440   /* PREFIX_0F38DF */
4441   {
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4445   },
4446
4447   /* PREFIX_0F38F0 */
4448   {
4449     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4450     { Bad_Opcode },
4451     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4452     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4453   },
4454
4455   /* PREFIX_0F38F1 */
4456   {
4457     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4458     { Bad_Opcode },
4459     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4460     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4461   },
4462
4463   /* PREFIX_0F38F5 */
4464   {
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4468   },
4469
4470   /* PREFIX_0F38F6 */
4471   {
4472     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4473     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4474     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4475     { Bad_Opcode },
4476   },
4477
4478   /* PREFIX_0F38F8 */
4479   {
4480     { Bad_Opcode },
4481     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4482     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4483     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4484   },
4485
4486   /* PREFIX_0F38F9 */
4487   {
4488     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4489   },
4490
4491   /* PREFIX_0F3A08 */
4492   {
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4496   },
4497
4498   /* PREFIX_0F3A09 */
4499   {
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4503   },
4504
4505   /* PREFIX_0F3A0A */
4506   {
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4510   },
4511
4512   /* PREFIX_0F3A0B */
4513   {
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4517   },
4518
4519   /* PREFIX_0F3A0C */
4520   {
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4524   },
4525
4526   /* PREFIX_0F3A0D */
4527   {
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4531   },
4532
4533   /* PREFIX_0F3A0E */
4534   {
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4538   },
4539
4540   /* PREFIX_0F3A14 */
4541   {
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4545   },
4546
4547   /* PREFIX_0F3A15 */
4548   {
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4552   },
4553
4554   /* PREFIX_0F3A16 */
4555   {
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4559   },
4560
4561   /* PREFIX_0F3A17 */
4562   {
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4566   },
4567
4568   /* PREFIX_0F3A20 */
4569   {
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4573   },
4574
4575   /* PREFIX_0F3A21 */
4576   {
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4580   },
4581
4582   /* PREFIX_0F3A22 */
4583   {
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4587   },
4588
4589   /* PREFIX_0F3A40 */
4590   {
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4594   },
4595
4596   /* PREFIX_0F3A41 */
4597   {
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4601   },
4602
4603   /* PREFIX_0F3A42 */
4604   {
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4608   },
4609
4610   /* PREFIX_0F3A44 */
4611   {
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4615   },
4616
4617   /* PREFIX_0F3A60 */
4618   {
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4622   },
4623
4624   /* PREFIX_0F3A61 */
4625   {
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4629   },
4630
4631   /* PREFIX_0F3A62 */
4632   {
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4636   },
4637
4638   /* PREFIX_0F3A63 */
4639   {
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4643   },
4644
4645   /* PREFIX_0F3ACC */
4646   {
4647     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4648   },
4649
4650   /* PREFIX_0F3ACE */
4651   {
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4655   },
4656
4657   /* PREFIX_0F3ACF */
4658   {
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4662   },
4663
4664   /* PREFIX_0F3ADF */
4665   {
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4669   },
4670
4671   /* PREFIX_VEX_0F10 */
4672   {
4673     { "vmovups",        { XM, EXx }, 0 },
4674     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4675     { "vmovupd",        { XM, EXx }, 0 },
4676     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4677   },
4678
4679   /* PREFIX_VEX_0F11 */
4680   {
4681     { "vmovups",        { EXxS, XM }, 0 },
4682     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4683     { "vmovupd",        { EXxS, XM }, 0 },
4684     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4685   },
4686
4687   /* PREFIX_VEX_0F12 */
4688   {
4689     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4690     { "vmovsldup",      { XM, EXx }, 0 },
4691     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4692     { "vmovddup",       { XM, EXymmq }, 0 },
4693   },
4694
4695   /* PREFIX_VEX_0F16 */
4696   {
4697     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4698     { "vmovshdup",      { XM, EXx }, 0 },
4699     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4700   },
4701
4702   /* PREFIX_VEX_0F2A */
4703   {
4704     { Bad_Opcode },
4705     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4706     { Bad_Opcode },
4707     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4708   },
4709
4710   /* PREFIX_VEX_0F2C */
4711   {
4712     { Bad_Opcode },
4713     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4714     { Bad_Opcode },
4715     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4716   },
4717
4718   /* PREFIX_VEX_0F2D */
4719   {
4720     { Bad_Opcode },
4721     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4722     { Bad_Opcode },
4723     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4724   },
4725
4726   /* PREFIX_VEX_0F2E */
4727   {
4728     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4729     { Bad_Opcode },
4730     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4731   },
4732
4733   /* PREFIX_VEX_0F2F */
4734   {
4735     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4736     { Bad_Opcode },
4737     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4738   },
4739
4740   /* PREFIX_VEX_0F41 */
4741   {
4742     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4743     { Bad_Opcode },
4744     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4745   },
4746
4747   /* PREFIX_VEX_0F42 */
4748   {
4749     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4750     { Bad_Opcode },
4751     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4752   },
4753
4754   /* PREFIX_VEX_0F44 */
4755   {
4756     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4757     { Bad_Opcode },
4758     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4759   },
4760
4761   /* PREFIX_VEX_0F45 */
4762   {
4763     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4764     { Bad_Opcode },
4765     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4766   },
4767
4768   /* PREFIX_VEX_0F46 */
4769   {
4770     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4771     { Bad_Opcode },
4772     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4773   },
4774
4775   /* PREFIX_VEX_0F47 */
4776   {
4777     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4778     { Bad_Opcode },
4779     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4780   },
4781
4782   /* PREFIX_VEX_0F4A */
4783   {
4784     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4785     { Bad_Opcode },
4786     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4787   },
4788
4789   /* PREFIX_VEX_0F4B */
4790   {
4791     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4792     { Bad_Opcode },
4793     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4794   },
4795
4796   /* PREFIX_VEX_0F51 */
4797   {
4798     { "vsqrtps",        { XM, EXx }, 0 },
4799     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4800     { "vsqrtpd",        { XM, EXx }, 0 },
4801     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4802   },
4803
4804   /* PREFIX_VEX_0F52 */
4805   {
4806     { "vrsqrtps",       { XM, EXx }, 0 },
4807     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4808   },
4809
4810   /* PREFIX_VEX_0F53 */
4811   {
4812     { "vrcpps",         { XM, EXx }, 0 },
4813     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4814   },
4815
4816   /* PREFIX_VEX_0F58 */
4817   {
4818     { "vaddps",         { XM, Vex, EXx }, 0 },
4819     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4820     { "vaddpd",         { XM, Vex, EXx }, 0 },
4821     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4822   },
4823
4824   /* PREFIX_VEX_0F59 */
4825   {
4826     { "vmulps",         { XM, Vex, EXx }, 0 },
4827     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4828     { "vmulpd",         { XM, Vex, EXx }, 0 },
4829     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4830   },
4831
4832   /* PREFIX_VEX_0F5A */
4833   {
4834     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4835     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4836     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4837     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4838   },
4839
4840   /* PREFIX_VEX_0F5B */
4841   {
4842     { "vcvtdq2ps",      { XM, EXx }, 0 },
4843     { "vcvttps2dq",     { XM, EXx }, 0 },
4844     { "vcvtps2dq",      { XM, EXx }, 0 },
4845   },
4846
4847   /* PREFIX_VEX_0F5C */
4848   {
4849     { "vsubps",         { XM, Vex, EXx }, 0 },
4850     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4851     { "vsubpd",         { XM, Vex, EXx }, 0 },
4852     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4853   },
4854
4855   /* PREFIX_VEX_0F5D */
4856   {
4857     { "vminps",         { XM, Vex, EXx }, 0 },
4858     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4859     { "vminpd",         { XM, Vex, EXx }, 0 },
4860     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4861   },
4862
4863   /* PREFIX_VEX_0F5E */
4864   {
4865     { "vdivps",         { XM, Vex, EXx }, 0 },
4866     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4867     { "vdivpd",         { XM, Vex, EXx }, 0 },
4868     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4869   },
4870
4871   /* PREFIX_VEX_0F5F */
4872   {
4873     { "vmaxps",         { XM, Vex, EXx }, 0 },
4874     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4875     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4876     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4877   },
4878
4879   /* PREFIX_VEX_0F60 */
4880   {
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4884   },
4885
4886   /* PREFIX_VEX_0F61 */
4887   {
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4891   },
4892
4893   /* PREFIX_VEX_0F62 */
4894   {
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4898   },
4899
4900   /* PREFIX_VEX_0F63 */
4901   {
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4905   },
4906
4907   /* PREFIX_VEX_0F64 */
4908   {
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4912   },
4913
4914   /* PREFIX_VEX_0F65 */
4915   {
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4919   },
4920
4921   /* PREFIX_VEX_0F66 */
4922   {
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4926   },
4927
4928   /* PREFIX_VEX_0F67 */
4929   {
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4933   },
4934
4935   /* PREFIX_VEX_0F68 */
4936   {
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4940   },
4941
4942   /* PREFIX_VEX_0F69 */
4943   {
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4947   },
4948
4949   /* PREFIX_VEX_0F6A */
4950   {
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4954   },
4955
4956   /* PREFIX_VEX_0F6B */
4957   {
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4961   },
4962
4963   /* PREFIX_VEX_0F6C */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4968   },
4969
4970   /* PREFIX_VEX_0F6D */
4971   {
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4975   },
4976
4977   /* PREFIX_VEX_0F6E */
4978   {
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4982   },
4983
4984   /* PREFIX_VEX_0F6F */
4985   {
4986     { Bad_Opcode },
4987     { "vmovdqu",        { XM, EXx }, 0 },
4988     { "vmovdqa",        { XM, EXx }, 0 },
4989   },
4990
4991   /* PREFIX_VEX_0F70 */
4992   {
4993     { Bad_Opcode },
4994     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4995     { "vpshufd",        { XM, EXx, Ib }, 0 },
4996     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4997   },
4998
4999   /* PREFIX_VEX_0F71_REG_2 */
5000   {
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { "vpsrlw",         { Vex, XS, Ib }, 0 },
5004   },
5005
5006   /* PREFIX_VEX_0F71_REG_4 */
5007   {
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { "vpsraw",         { Vex, XS, Ib }, 0 },
5011   },
5012
5013   /* PREFIX_VEX_0F71_REG_6 */
5014   {
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { "vpsllw",         { Vex, XS, Ib }, 0 },
5018   },
5019
5020   /* PREFIX_VEX_0F72_REG_2 */
5021   {
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { "vpsrld",         { Vex, XS, Ib }, 0 },
5025   },
5026
5027   /* PREFIX_VEX_0F72_REG_4 */
5028   {
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { "vpsrad",         { Vex, XS, Ib }, 0 },
5032   },
5033
5034   /* PREFIX_VEX_0F72_REG_6 */
5035   {
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { "vpslld",         { Vex, XS, Ib }, 0 },
5039   },
5040
5041   /* PREFIX_VEX_0F73_REG_2 */
5042   {
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5046   },
5047
5048   /* PREFIX_VEX_0F73_REG_3 */
5049   {
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5053   },
5054
5055   /* PREFIX_VEX_0F73_REG_6 */
5056   {
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { "vpsllq",         { Vex, XS, Ib }, 0 },
5060   },
5061
5062   /* PREFIX_VEX_0F73_REG_7 */
5063   {
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { "vpslldq",        { Vex, XS, Ib }, 0 },
5067   },
5068
5069   /* PREFIX_VEX_0F74 */
5070   {
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5074   },
5075
5076   /* PREFIX_VEX_0F75 */
5077   {
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5081   },
5082
5083   /* PREFIX_VEX_0F76 */
5084   {
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5088   },
5089
5090   /* PREFIX_VEX_0F77 */
5091   {
5092     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5093   },
5094
5095   /* PREFIX_VEX_0F7C */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5100     { "vhaddps",        { XM, Vex, EXx }, 0 },
5101   },
5102
5103   /* PREFIX_VEX_0F7D */
5104   {
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5108     { "vhsubps",        { XM, Vex, EXx }, 0 },
5109   },
5110
5111   /* PREFIX_VEX_0F7E */
5112   {
5113     { Bad_Opcode },
5114     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5115     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5116   },
5117
5118   /* PREFIX_VEX_0F7F */
5119   {
5120     { Bad_Opcode },
5121     { "vmovdqu",        { EXxS, XM }, 0 },
5122     { "vmovdqa",        { EXxS, XM }, 0 },
5123   },
5124
5125   /* PREFIX_VEX_0F90 */
5126   {
5127     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5128     { Bad_Opcode },
5129     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5130   },
5131
5132   /* PREFIX_VEX_0F91 */
5133   {
5134     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5135     { Bad_Opcode },
5136     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5137   },
5138
5139   /* PREFIX_VEX_0F92 */
5140   {
5141     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5142     { Bad_Opcode },
5143     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5144     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5145   },
5146
5147   /* PREFIX_VEX_0F93 */
5148   {
5149     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5150     { Bad_Opcode },
5151     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5152     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5153   },
5154
5155   /* PREFIX_VEX_0F98 */
5156   {
5157     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5158     { Bad_Opcode },
5159     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5160   },
5161
5162   /* PREFIX_VEX_0F99 */
5163   {
5164     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5165     { Bad_Opcode },
5166     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5167   },
5168
5169   /* PREFIX_VEX_0FC2 */
5170   {
5171     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5172     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5173     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5174     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5175   },
5176
5177   /* PREFIX_VEX_0FC4 */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5182   },
5183
5184   /* PREFIX_VEX_0FC5 */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5189   },
5190
5191   /* PREFIX_VEX_0FD0 */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5196     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5197   },
5198
5199   /* PREFIX_VEX_0FD1 */
5200   {
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5204   },
5205
5206   /* PREFIX_VEX_0FD2 */
5207   {
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5211   },
5212
5213   /* PREFIX_VEX_0FD3 */
5214   {
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5218   },
5219
5220   /* PREFIX_VEX_0FD4 */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { "vpaddq",         { XM, Vex, EXx }, 0 },
5225   },
5226
5227   /* PREFIX_VEX_0FD5 */
5228   {
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { "vpmullw",        { XM, Vex, EXx }, 0 },
5232   },
5233
5234   /* PREFIX_VEX_0FD6 */
5235   {
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5239   },
5240
5241   /* PREFIX_VEX_0FD7 */
5242   {
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5246   },
5247
5248   /* PREFIX_VEX_0FD8 */
5249   {
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5253   },
5254
5255   /* PREFIX_VEX_0FD9 */
5256   {
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5260   },
5261
5262   /* PREFIX_VEX_0FDA */
5263   {
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { "vpminub",        { XM, Vex, EXx }, 0 },
5267   },
5268
5269   /* PREFIX_VEX_0FDB */
5270   {
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { "vpand",          { XM, Vex, EXx }, 0 },
5274   },
5275
5276   /* PREFIX_VEX_0FDC */
5277   {
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5281   },
5282
5283   /* PREFIX_VEX_0FDD */
5284   {
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5288   },
5289
5290   /* PREFIX_VEX_0FDE */
5291   {
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5295   },
5296
5297   /* PREFIX_VEX_0FDF */
5298   {
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { "vpandn",         { XM, Vex, EXx }, 0 },
5302   },
5303
5304   /* PREFIX_VEX_0FE0 */
5305   {
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { "vpavgb",         { XM, Vex, EXx }, 0 },
5309   },
5310
5311   /* PREFIX_VEX_0FE1 */
5312   {
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5316   },
5317
5318   /* PREFIX_VEX_0FE2 */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5323   },
5324
5325   /* PREFIX_VEX_0FE3 */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { "vpavgw",         { XM, Vex, EXx }, 0 },
5330   },
5331
5332   /* PREFIX_VEX_0FE4 */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5337   },
5338
5339   /* PREFIX_VEX_0FE5 */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5344   },
5345
5346   /* PREFIX_VEX_0FE6 */
5347   {
5348     { Bad_Opcode },
5349     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5350     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5351     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5352   },
5353
5354   /* PREFIX_VEX_0FE7 */
5355   {
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5359   },
5360
5361   /* PREFIX_VEX_0FE8 */
5362   {
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5366   },
5367
5368   /* PREFIX_VEX_0FE9 */
5369   {
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5373   },
5374
5375   /* PREFIX_VEX_0FEA */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { "vpminsw",        { XM, Vex, EXx }, 0 },
5380   },
5381
5382   /* PREFIX_VEX_0FEB */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { "vpor",           { XM, Vex, EXx }, 0 },
5387   },
5388
5389   /* PREFIX_VEX_0FEC */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5394   },
5395
5396   /* PREFIX_VEX_0FED */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5401   },
5402
5403   /* PREFIX_VEX_0FEE */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5408   },
5409
5410   /* PREFIX_VEX_0FEF */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { "vpxor",          { XM, Vex, EXx }, 0 },
5415   },
5416
5417   /* PREFIX_VEX_0FF0 */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5423   },
5424
5425   /* PREFIX_VEX_0FF1 */
5426   {
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5430   },
5431
5432   /* PREFIX_VEX_0FF2 */
5433   {
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5437   },
5438
5439   /* PREFIX_VEX_0FF3 */
5440   {
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5444   },
5445
5446   /* PREFIX_VEX_0FF4 */
5447   {
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5451   },
5452
5453   /* PREFIX_VEX_0FF5 */
5454   {
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5458   },
5459
5460   /* PREFIX_VEX_0FF6 */
5461   {
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5465   },
5466
5467   /* PREFIX_VEX_0FF7 */
5468   {
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5472   },
5473
5474   /* PREFIX_VEX_0FF8 */
5475   {
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { "vpsubb",         { XM, Vex, EXx }, 0 },
5479   },
5480
5481   /* PREFIX_VEX_0FF9 */
5482   {
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { "vpsubw",         { XM, Vex, EXx }, 0 },
5486   },
5487
5488   /* PREFIX_VEX_0FFA */
5489   {
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { "vpsubd",         { XM, Vex, EXx }, 0 },
5493   },
5494
5495   /* PREFIX_VEX_0FFB */
5496   {
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { "vpsubq",         { XM, Vex, EXx }, 0 },
5500   },
5501
5502   /* PREFIX_VEX_0FFC */
5503   {
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { "vpaddb",         { XM, Vex, EXx }, 0 },
5507   },
5508
5509   /* PREFIX_VEX_0FFD */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { "vpaddw",         { XM, Vex, EXx }, 0 },
5514   },
5515
5516   /* PREFIX_VEX_0FFE */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { "vpaddd",         { XM, Vex, EXx }, 0 },
5521   },
5522
5523   /* PREFIX_VEX_0F3800 */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { "vpshufb",        { XM, Vex, EXx }, 0 },
5528   },
5529
5530   /* PREFIX_VEX_0F3801 */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { "vphaddw",        { XM, Vex, EXx }, 0 },
5535   },
5536
5537   /* PREFIX_VEX_0F3802 */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { "vphaddd",        { XM, Vex, EXx }, 0 },
5542   },
5543
5544   /* PREFIX_VEX_0F3803 */
5545   {
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5549   },
5550
5551   /* PREFIX_VEX_0F3804 */
5552   {
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5556   },
5557
5558   /* PREFIX_VEX_0F3805 */
5559   {
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { "vphsubw",        { XM, Vex, EXx }, 0 },
5563   },
5564
5565   /* PREFIX_VEX_0F3806 */
5566   {
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { "vphsubd",        { XM, Vex, EXx }, 0 },
5570   },
5571
5572   /* PREFIX_VEX_0F3807 */
5573   {
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5577   },
5578
5579   /* PREFIX_VEX_0F3808 */
5580   {
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { "vpsignb",        { XM, Vex, EXx }, 0 },
5584   },
5585
5586   /* PREFIX_VEX_0F3809 */
5587   {
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { "vpsignw",        { XM, Vex, EXx }, 0 },
5591   },
5592
5593   /* PREFIX_VEX_0F380A */
5594   {
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { "vpsignd",        { XM, Vex, EXx }, 0 },
5598   },
5599
5600   /* PREFIX_VEX_0F380B */
5601   {
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5605   },
5606
5607   /* PREFIX_VEX_0F380C */
5608   {
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5612   },
5613
5614   /* PREFIX_VEX_0F380D */
5615   {
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5619   },
5620
5621   /* PREFIX_VEX_0F380E */
5622   {
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5626   },
5627
5628   /* PREFIX_VEX_0F380F */
5629   {
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5633   },
5634
5635   /* PREFIX_VEX_0F3813 */
5636   {
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5640   },
5641
5642   /* PREFIX_VEX_0F3816 */
5643   {
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5647   },
5648
5649   /* PREFIX_VEX_0F3817 */
5650   {
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { "vptest",         { XM, EXx }, 0 },
5654   },
5655
5656   /* PREFIX_VEX_0F3818 */
5657   {
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5661   },
5662
5663   /* PREFIX_VEX_0F3819 */
5664   {
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5668   },
5669
5670   /* PREFIX_VEX_0F381A */
5671   {
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5675   },
5676
5677   /* PREFIX_VEX_0F381C */
5678   {
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { "vpabsb",         { XM, EXx }, 0 },
5682   },
5683
5684   /* PREFIX_VEX_0F381D */
5685   {
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { "vpabsw",         { XM, EXx }, 0 },
5689   },
5690
5691   /* PREFIX_VEX_0F381E */
5692   {
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { "vpabsd",         { XM, EXx }, 0 },
5696   },
5697
5698   /* PREFIX_VEX_0F3820 */
5699   {
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5703   },
5704
5705   /* PREFIX_VEX_0F3821 */
5706   {
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5710   },
5711
5712   /* PREFIX_VEX_0F3822 */
5713   {
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5717   },
5718
5719   /* PREFIX_VEX_0F3823 */
5720   {
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5724   },
5725
5726   /* PREFIX_VEX_0F3824 */
5727   {
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5731   },
5732
5733   /* PREFIX_VEX_0F3825 */
5734   {
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5738   },
5739
5740   /* PREFIX_VEX_0F3828 */
5741   {
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5745   },
5746
5747   /* PREFIX_VEX_0F3829 */
5748   {
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5752   },
5753
5754   /* PREFIX_VEX_0F382A */
5755   {
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5759   },
5760
5761   /* PREFIX_VEX_0F382B */
5762   {
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5766   },
5767
5768   /* PREFIX_VEX_0F382C */
5769   {
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5773   },
5774
5775   /* PREFIX_VEX_0F382D */
5776   {
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5780   },
5781
5782   /* PREFIX_VEX_0F382E */
5783   {
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5787   },
5788
5789   /* PREFIX_VEX_0F382F */
5790   {
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5794   },
5795
5796   /* PREFIX_VEX_0F3830 */
5797   {
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5801   },
5802
5803   /* PREFIX_VEX_0F3831 */
5804   {
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5808   },
5809
5810   /* PREFIX_VEX_0F3832 */
5811   {
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5815   },
5816
5817   /* PREFIX_VEX_0F3833 */
5818   {
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5822   },
5823
5824   /* PREFIX_VEX_0F3834 */
5825   {
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5829   },
5830
5831   /* PREFIX_VEX_0F3835 */
5832   {
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5836   },
5837
5838   /* PREFIX_VEX_0F3836 */
5839   {
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5843   },
5844
5845   /* PREFIX_VEX_0F3837 */
5846   {
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5850   },
5851
5852   /* PREFIX_VEX_0F3838 */
5853   {
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { "vpminsb",        { XM, Vex, EXx }, 0 },
5857   },
5858
5859   /* PREFIX_VEX_0F3839 */
5860   {
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { "vpminsd",        { XM, Vex, EXx }, 0 },
5864   },
5865
5866   /* PREFIX_VEX_0F383A */
5867   {
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { "vpminuw",        { XM, Vex, EXx }, 0 },
5871   },
5872
5873   /* PREFIX_VEX_0F383B */
5874   {
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { "vpminud",        { XM, Vex, EXx }, 0 },
5878   },
5879
5880   /* PREFIX_VEX_0F383C */
5881   {
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5885   },
5886
5887   /* PREFIX_VEX_0F383D */
5888   {
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5892   },
5893
5894   /* PREFIX_VEX_0F383E */
5895   {
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5899   },
5900
5901   /* PREFIX_VEX_0F383F */
5902   {
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5906   },
5907
5908   /* PREFIX_VEX_0F3840 */
5909   {
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { "vpmulld",        { XM, Vex, EXx }, 0 },
5913   },
5914
5915   /* PREFIX_VEX_0F3841 */
5916   {
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5920   },
5921
5922   /* PREFIX_VEX_0F3845 */
5923   {
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5927   },
5928
5929   /* PREFIX_VEX_0F3846 */
5930   {
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5934   },
5935
5936   /* PREFIX_VEX_0F3847 */
5937   {
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5941   },
5942
5943   /* PREFIX_VEX_0F3858 */
5944   {
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5948   },
5949
5950   /* PREFIX_VEX_0F3859 */
5951   {
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5955   },
5956
5957   /* PREFIX_VEX_0F385A */
5958   {
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5962   },
5963
5964   /* PREFIX_VEX_0F3878 */
5965   {
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5969   },
5970
5971   /* PREFIX_VEX_0F3879 */
5972   {
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5976   },
5977
5978   /* PREFIX_VEX_0F388C */
5979   {
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5983   },
5984
5985   /* PREFIX_VEX_0F388E */
5986   {
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5990   },
5991
5992   /* PREFIX_VEX_0F3890 */
5993   {
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5997   },
5998
5999   /* PREFIX_VEX_0F3891 */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6004   },
6005
6006   /* PREFIX_VEX_0F3892 */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6011   },
6012
6013   /* PREFIX_VEX_0F3893 */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6018   },
6019
6020   /* PREFIX_VEX_0F3896 */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6025   },
6026
6027   /* PREFIX_VEX_0F3897 */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6032   },
6033
6034   /* PREFIX_VEX_0F3898 */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6039   },
6040
6041   /* PREFIX_VEX_0F3899 */
6042   {
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6046   },
6047
6048   /* PREFIX_VEX_0F389A */
6049   {
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6053   },
6054
6055   /* PREFIX_VEX_0F389B */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6060   },
6061
6062   /* PREFIX_VEX_0F389C */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6067   },
6068
6069   /* PREFIX_VEX_0F389D */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6074   },
6075
6076   /* PREFIX_VEX_0F389E */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6081   },
6082
6083   /* PREFIX_VEX_0F389F */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6088   },
6089
6090   /* PREFIX_VEX_0F38A6 */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6095     { Bad_Opcode },
6096   },
6097
6098   /* PREFIX_VEX_0F38A7 */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6103   },
6104
6105   /* PREFIX_VEX_0F38A8 */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6110   },
6111
6112   /* PREFIX_VEX_0F38A9 */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6117   },
6118
6119   /* PREFIX_VEX_0F38AA */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6124   },
6125
6126   /* PREFIX_VEX_0F38AB */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6131   },
6132
6133   /* PREFIX_VEX_0F38AC */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6138   },
6139
6140   /* PREFIX_VEX_0F38AD */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6145   },
6146
6147   /* PREFIX_VEX_0F38AE */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6152   },
6153
6154   /* PREFIX_VEX_0F38AF */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6159   },
6160
6161   /* PREFIX_VEX_0F38B6 */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6166   },
6167
6168   /* PREFIX_VEX_0F38B7 */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6173   },
6174
6175   /* PREFIX_VEX_0F38B8 */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6180   },
6181
6182   /* PREFIX_VEX_0F38B9 */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6187   },
6188
6189   /* PREFIX_VEX_0F38BA */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6194   },
6195
6196   /* PREFIX_VEX_0F38BB */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6201   },
6202
6203   /* PREFIX_VEX_0F38BC */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6208   },
6209
6210   /* PREFIX_VEX_0F38BD */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6215   },
6216
6217   /* PREFIX_VEX_0F38BE */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6222   },
6223
6224   /* PREFIX_VEX_0F38BF */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6229   },
6230
6231   /* PREFIX_VEX_0F38CF */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6236   },
6237
6238   /* PREFIX_VEX_0F38DB */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6243   },
6244
6245   /* PREFIX_VEX_0F38DC */
6246   {
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { "vaesenc",        { XM, Vex, EXx }, 0 },
6250   },
6251
6252   /* PREFIX_VEX_0F38DD */
6253   {
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6257   },
6258
6259   /* PREFIX_VEX_0F38DE */
6260   {
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { "vaesdec",        { XM, Vex, EXx }, 0 },
6264   },
6265
6266   /* PREFIX_VEX_0F38DF */
6267   {
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6271   },
6272
6273   /* PREFIX_VEX_0F38F2 */
6274   {
6275     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6276   },
6277
6278   /* PREFIX_VEX_0F38F3_REG_1 */
6279   {
6280     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6281   },
6282
6283   /* PREFIX_VEX_0F38F3_REG_2 */
6284   {
6285     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6286   },
6287
6288   /* PREFIX_VEX_0F38F3_REG_3 */
6289   {
6290     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6291   },
6292
6293   /* PREFIX_VEX_0F38F5 */
6294   {
6295     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6296     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6297     { Bad_Opcode },
6298     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6299   },
6300
6301   /* PREFIX_VEX_0F38F6 */
6302   {
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6307   },
6308
6309   /* PREFIX_VEX_0F38F7 */
6310   {
6311     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6312     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6313     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6314     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6315   },
6316
6317   /* PREFIX_VEX_0F3A00 */
6318   {
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6322   },
6323
6324   /* PREFIX_VEX_0F3A01 */
6325   {
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6329   },
6330
6331   /* PREFIX_VEX_0F3A02 */
6332   {
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6336   },
6337
6338   /* PREFIX_VEX_0F3A04 */
6339   {
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6343   },
6344
6345   /* PREFIX_VEX_0F3A05 */
6346   {
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6350   },
6351
6352   /* PREFIX_VEX_0F3A06 */
6353   {
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6357   },
6358
6359   /* PREFIX_VEX_0F3A08 */
6360   {
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { "vroundps",       { XM, EXx, Ib }, 0 },
6364   },
6365
6366   /* PREFIX_VEX_0F3A09 */
6367   {
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { "vroundpd",       { XM, EXx, Ib }, 0 },
6371   },
6372
6373   /* PREFIX_VEX_0F3A0A */
6374   {
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6378   },
6379
6380   /* PREFIX_VEX_0F3A0B */
6381   {
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6385   },
6386
6387   /* PREFIX_VEX_0F3A0C */
6388   {
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6392   },
6393
6394   /* PREFIX_VEX_0F3A0D */
6395   {
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6399   },
6400
6401   /* PREFIX_VEX_0F3A0E */
6402   {
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6406   },
6407
6408   /* PREFIX_VEX_0F3A0F */
6409   {
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6413   },
6414
6415   /* PREFIX_VEX_0F3A14 */
6416   {
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6420   },
6421
6422   /* PREFIX_VEX_0F3A15 */
6423   {
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6427   },
6428
6429   /* PREFIX_VEX_0F3A16 */
6430   {
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6434   },
6435
6436   /* PREFIX_VEX_0F3A17 */
6437   {
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6441   },
6442
6443   /* PREFIX_VEX_0F3A18 */
6444   {
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6448   },
6449
6450   /* PREFIX_VEX_0F3A19 */
6451   {
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6455   },
6456
6457   /* PREFIX_VEX_0F3A1D */
6458   {
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6462   },
6463
6464   /* PREFIX_VEX_0F3A20 */
6465   {
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6469   },
6470
6471   /* PREFIX_VEX_0F3A21 */
6472   {
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6476   },
6477
6478   /* PREFIX_VEX_0F3A22 */
6479   {
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6483   },
6484
6485   /* PREFIX_VEX_0F3A30 */
6486   {
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6490   },
6491
6492   /* PREFIX_VEX_0F3A31 */
6493   {
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6497   },
6498
6499   /* PREFIX_VEX_0F3A32 */
6500   {
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6504   },
6505
6506   /* PREFIX_VEX_0F3A33 */
6507   {
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6511   },
6512
6513   /* PREFIX_VEX_0F3A38 */
6514   {
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6518   },
6519
6520   /* PREFIX_VEX_0F3A39 */
6521   {
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6525   },
6526
6527   /* PREFIX_VEX_0F3A40 */
6528   {
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6532   },
6533
6534   /* PREFIX_VEX_0F3A41 */
6535   {
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6539   },
6540
6541   /* PREFIX_VEX_0F3A42 */
6542   {
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6546   },
6547
6548   /* PREFIX_VEX_0F3A44 */
6549   {
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6553   },
6554
6555   /* PREFIX_VEX_0F3A46 */
6556   {
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6560   },
6561
6562   /* PREFIX_VEX_0F3A48 */
6563   {
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6567   },
6568
6569   /* PREFIX_VEX_0F3A49 */
6570   {
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6574   },
6575
6576   /* PREFIX_VEX_0F3A4A */
6577   {
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6581   },
6582
6583   /* PREFIX_VEX_0F3A4B */
6584   {
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6588   },
6589
6590   /* PREFIX_VEX_0F3A4C */
6591   {
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6595   },
6596
6597   /* PREFIX_VEX_0F3A5C */
6598   {
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6602   },
6603
6604   /* PREFIX_VEX_0F3A5D */
6605   {
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6609   },
6610
6611   /* PREFIX_VEX_0F3A5E */
6612   {
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6616   },
6617
6618   /* PREFIX_VEX_0F3A5F */
6619   {
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6623   },
6624
6625   /* PREFIX_VEX_0F3A60 */
6626   {
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6630     { Bad_Opcode },
6631   },
6632
6633   /* PREFIX_VEX_0F3A61 */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6638   },
6639
6640   /* PREFIX_VEX_0F3A62 */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6645   },
6646
6647   /* PREFIX_VEX_0F3A63 */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6652   },
6653
6654   /* PREFIX_VEX_0F3A68 */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6659   },
6660
6661   /* PREFIX_VEX_0F3A69 */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6666   },
6667
6668   /* PREFIX_VEX_0F3A6A */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6673   },
6674
6675   /* PREFIX_VEX_0F3A6B */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6680   },
6681
6682   /* PREFIX_VEX_0F3A6C */
6683   {
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6687   },
6688
6689   /* PREFIX_VEX_0F3A6D */
6690   {
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6694   },
6695
6696   /* PREFIX_VEX_0F3A6E */
6697   {
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6701   },
6702
6703   /* PREFIX_VEX_0F3A6F */
6704   {
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6708   },
6709
6710   /* PREFIX_VEX_0F3A78 */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6715   },
6716
6717   /* PREFIX_VEX_0F3A79 */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6722   },
6723
6724   /* PREFIX_VEX_0F3A7A */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6729   },
6730
6731   /* PREFIX_VEX_0F3A7B */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6736   },
6737
6738   /* PREFIX_VEX_0F3A7C */
6739   {
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6743     { Bad_Opcode },
6744   },
6745
6746   /* PREFIX_VEX_0F3A7D */
6747   {
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6751   },
6752
6753   /* PREFIX_VEX_0F3A7E */
6754   {
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6758   },
6759
6760   /* PREFIX_VEX_0F3A7F */
6761   {
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6765   },
6766
6767   /* PREFIX_VEX_0F3ACE */
6768   {
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6772   },
6773
6774   /* PREFIX_VEX_0F3ACF */
6775   {
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6779   },
6780
6781   /* PREFIX_VEX_0F3ADF */
6782   {
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6786   },
6787
6788   /* PREFIX_VEX_0F3AF0 */
6789   {
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6794   },
6795
6796 #include "i386-dis-evex-prefix.h"
6797 };
6798
6799 static const struct dis386 x86_64_table[][2] = {
6800   /* X86_64_06 */
6801   {
6802     { "pushP", { es }, 0 },
6803   },
6804
6805   /* X86_64_07 */
6806   {
6807     { "popP", { es }, 0 },
6808   },
6809
6810   /* X86_64_0D */
6811   {
6812     { "pushP", { cs }, 0 },
6813   },
6814
6815   /* X86_64_16 */
6816   {
6817     { "pushP", { ss }, 0 },
6818   },
6819
6820   /* X86_64_17 */
6821   {
6822     { "popP", { ss }, 0 },
6823   },
6824
6825   /* X86_64_1E */
6826   {
6827     { "pushP", { ds }, 0 },
6828   },
6829
6830   /* X86_64_1F */
6831   {
6832     { "popP", { ds }, 0 },
6833   },
6834
6835   /* X86_64_27 */
6836   {
6837     { "daa", { XX }, 0 },
6838   },
6839
6840   /* X86_64_2F */
6841   {
6842     { "das", { XX }, 0 },
6843   },
6844
6845   /* X86_64_37 */
6846   {
6847     { "aaa", { XX }, 0 },
6848   },
6849
6850   /* X86_64_3F */
6851   {
6852     { "aas", { XX }, 0 },
6853   },
6854
6855   /* X86_64_60 */
6856   {
6857     { "pushaP", { XX }, 0 },
6858   },
6859
6860   /* X86_64_61 */
6861   {
6862     { "popaP", { XX }, 0 },
6863   },
6864
6865   /* X86_64_62 */
6866   {
6867     { MOD_TABLE (MOD_62_32BIT) },
6868     { EVEX_TABLE (EVEX_0F) },
6869   },
6870
6871   /* X86_64_63 */
6872   {
6873     { "arpl", { Ew, Gw }, 0 },
6874     { "movs{lq|xd}", { Gv, Ed }, 0 },
6875   },
6876
6877   /* X86_64_6D */
6878   {
6879     { "ins{R|}", { Yzr, indirDX }, 0 },
6880     { "ins{G|}", { Yzr, indirDX }, 0 },
6881   },
6882
6883   /* X86_64_6F */
6884   {
6885     { "outs{R|}", { indirDXr, Xz }, 0 },
6886     { "outs{G|}", { indirDXr, Xz }, 0 },
6887   },
6888
6889   /* X86_64_82 */
6890   {
6891     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6892     { REG_TABLE (REG_80) },
6893   },
6894
6895   /* X86_64_9A */
6896   {
6897     { "Jcall{T|}", { Ap }, 0 },
6898   },
6899
6900   /* X86_64_C4 */
6901   {
6902     { MOD_TABLE (MOD_C4_32BIT) },
6903     { VEX_C4_TABLE (VEX_0F) },
6904   },
6905
6906   /* X86_64_C5 */
6907   {
6908     { MOD_TABLE (MOD_C5_32BIT) },
6909     { VEX_C5_TABLE (VEX_0F) },
6910   },
6911
6912   /* X86_64_CE */
6913   {
6914     { "into", { XX }, 0 },
6915   },
6916
6917   /* X86_64_D4 */
6918   {
6919     { "aam", { Ib }, 0 },
6920   },
6921
6922   /* X86_64_D5 */
6923   {
6924     { "aad", { Ib }, 0 },
6925   },
6926
6927   /* X86_64_E8 */
6928   {
6929     { "callP",          { Jv, BND }, 0 },
6930     { "call@",          { Jv, BND }, 0 }
6931   },
6932
6933   /* X86_64_E9 */
6934   {
6935     { "jmpP",           { Jv, BND }, 0 },
6936     { "jmp@",           { Jv, BND }, 0 }
6937   },
6938
6939   /* X86_64_EA */
6940   {
6941     { "Jjmp{T|}", { Ap }, 0 },
6942   },
6943
6944   /* X86_64_0F01_REG_0 */
6945   {
6946     { "sgdt{Q|IQ}", { M }, 0 },
6947     { "sgdt", { M }, 0 },
6948   },
6949
6950   /* X86_64_0F01_REG_1 */
6951   {
6952     { "sidt{Q|IQ}", { M }, 0 },
6953     { "sidt", { M }, 0 },
6954   },
6955
6956   /* X86_64_0F01_REG_2 */
6957   {
6958     { "lgdt{Q|Q}", { M }, 0 },
6959     { "lgdt", { M }, 0 },
6960   },
6961
6962   /* X86_64_0F01_REG_3 */
6963   {
6964     { "lidt{Q|Q}", { M }, 0 },
6965     { "lidt", { M }, 0 },
6966   },
6967 };
6968
6969 static const struct dis386 three_byte_table[][256] = {
6970
6971   /* THREE_BYTE_0F38 */
6972   {
6973     /* 00 */
6974     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6975     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6976     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6977     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6978     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6979     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6980     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6981     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6982     /* 08 */
6983     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6984     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6985     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6986     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     /* 10 */
6992     { PREFIX_TABLE (PREFIX_0F3810) },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { PREFIX_TABLE (PREFIX_0F3814) },
6997     { PREFIX_TABLE (PREFIX_0F3815) },
6998     { Bad_Opcode },
6999     { PREFIX_TABLE (PREFIX_0F3817) },
7000     /* 18 */
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7006     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7007     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7008     { Bad_Opcode },
7009     /* 20 */
7010     { PREFIX_TABLE (PREFIX_0F3820) },
7011     { PREFIX_TABLE (PREFIX_0F3821) },
7012     { PREFIX_TABLE (PREFIX_0F3822) },
7013     { PREFIX_TABLE (PREFIX_0F3823) },
7014     { PREFIX_TABLE (PREFIX_0F3824) },
7015     { PREFIX_TABLE (PREFIX_0F3825) },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     /* 28 */
7019     { PREFIX_TABLE (PREFIX_0F3828) },
7020     { PREFIX_TABLE (PREFIX_0F3829) },
7021     { PREFIX_TABLE (PREFIX_0F382A) },
7022     { PREFIX_TABLE (PREFIX_0F382B) },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     /* 30 */
7028     { PREFIX_TABLE (PREFIX_0F3830) },
7029     { PREFIX_TABLE (PREFIX_0F3831) },
7030     { PREFIX_TABLE (PREFIX_0F3832) },
7031     { PREFIX_TABLE (PREFIX_0F3833) },
7032     { PREFIX_TABLE (PREFIX_0F3834) },
7033     { PREFIX_TABLE (PREFIX_0F3835) },
7034     { Bad_Opcode },
7035     { PREFIX_TABLE (PREFIX_0F3837) },
7036     /* 38 */
7037     { PREFIX_TABLE (PREFIX_0F3838) },
7038     { PREFIX_TABLE (PREFIX_0F3839) },
7039     { PREFIX_TABLE (PREFIX_0F383A) },
7040     { PREFIX_TABLE (PREFIX_0F383B) },
7041     { PREFIX_TABLE (PREFIX_0F383C) },
7042     { PREFIX_TABLE (PREFIX_0F383D) },
7043     { PREFIX_TABLE (PREFIX_0F383E) },
7044     { PREFIX_TABLE (PREFIX_0F383F) },
7045     /* 40 */
7046     { PREFIX_TABLE (PREFIX_0F3840) },
7047     { PREFIX_TABLE (PREFIX_0F3841) },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     /* 48 */
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     /* 50 */
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     /* 58 */
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     /* 60 */
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     /* 68 */
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     /* 70 */
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     /* 78 */
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     /* 80 */
7118     { PREFIX_TABLE (PREFIX_0F3880) },
7119     { PREFIX_TABLE (PREFIX_0F3881) },
7120     { PREFIX_TABLE (PREFIX_0F3882) },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     /* 88 */
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     /* 90 */
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     /* 98 */
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     /* a0 */
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     /* a8 */
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     /* b0 */
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     /* b8 */
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     /* c0 */
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* c8 */
7199     { PREFIX_TABLE (PREFIX_0F38C8) },
7200     { PREFIX_TABLE (PREFIX_0F38C9) },
7201     { PREFIX_TABLE (PREFIX_0F38CA) },
7202     { PREFIX_TABLE (PREFIX_0F38CB) },
7203     { PREFIX_TABLE (PREFIX_0F38CC) },
7204     { PREFIX_TABLE (PREFIX_0F38CD) },
7205     { Bad_Opcode },
7206     { PREFIX_TABLE (PREFIX_0F38CF) },
7207     /* d0 */
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     /* d8 */
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { PREFIX_TABLE (PREFIX_0F38DB) },
7221     { PREFIX_TABLE (PREFIX_0F38DC) },
7222     { PREFIX_TABLE (PREFIX_0F38DD) },
7223     { PREFIX_TABLE (PREFIX_0F38DE) },
7224     { PREFIX_TABLE (PREFIX_0F38DF) },
7225     /* e0 */
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     /* e8 */
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     /* f0 */
7244     { PREFIX_TABLE (PREFIX_0F38F0) },
7245     { PREFIX_TABLE (PREFIX_0F38F1) },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { PREFIX_TABLE (PREFIX_0F38F5) },
7250     { PREFIX_TABLE (PREFIX_0F38F6) },
7251     { Bad_Opcode },
7252     /* f8 */
7253     { PREFIX_TABLE (PREFIX_0F38F8) },
7254     { PREFIX_TABLE (PREFIX_0F38F9) },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261   },
7262   /* THREE_BYTE_0F3A */
7263   {
7264     /* 00 */
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     /* 08 */
7274     { PREFIX_TABLE (PREFIX_0F3A08) },
7275     { PREFIX_TABLE (PREFIX_0F3A09) },
7276     { PREFIX_TABLE (PREFIX_0F3A0A) },
7277     { PREFIX_TABLE (PREFIX_0F3A0B) },
7278     { PREFIX_TABLE (PREFIX_0F3A0C) },
7279     { PREFIX_TABLE (PREFIX_0F3A0D) },
7280     { PREFIX_TABLE (PREFIX_0F3A0E) },
7281     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7282     /* 10 */
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { PREFIX_TABLE (PREFIX_0F3A14) },
7288     { PREFIX_TABLE (PREFIX_0F3A15) },
7289     { PREFIX_TABLE (PREFIX_0F3A16) },
7290     { PREFIX_TABLE (PREFIX_0F3A17) },
7291     /* 18 */
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     /* 20 */
7301     { PREFIX_TABLE (PREFIX_0F3A20) },
7302     { PREFIX_TABLE (PREFIX_0F3A21) },
7303     { PREFIX_TABLE (PREFIX_0F3A22) },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     /* 28 */
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     /* 30 */
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     /* 38 */
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     /* 40 */
7337     { PREFIX_TABLE (PREFIX_0F3A40) },
7338     { PREFIX_TABLE (PREFIX_0F3A41) },
7339     { PREFIX_TABLE (PREFIX_0F3A42) },
7340     { Bad_Opcode },
7341     { PREFIX_TABLE (PREFIX_0F3A44) },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     /* 48 */
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     /* 50 */
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     /* 58 */
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     /* 60 */
7373     { PREFIX_TABLE (PREFIX_0F3A60) },
7374     { PREFIX_TABLE (PREFIX_0F3A61) },
7375     { PREFIX_TABLE (PREFIX_0F3A62) },
7376     { PREFIX_TABLE (PREFIX_0F3A63) },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     /* 68 */
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     /* 70 */
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     /* 78 */
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     /* 80 */
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     /* 88 */
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     /* 90 */
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     /* 98 */
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     /* a0 */
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     /* a8 */
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     /* b0 */
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     /* b8 */
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     /* c0 */
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     /* c8 */
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { PREFIX_TABLE (PREFIX_0F3ACC) },
7495     { Bad_Opcode },
7496     { PREFIX_TABLE (PREFIX_0F3ACE) },
7497     { PREFIX_TABLE (PREFIX_0F3ACF) },
7498     /* d0 */
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     /* d8 */
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { PREFIX_TABLE (PREFIX_0F3ADF) },
7516     /* e0 */
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     /* e8 */
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     /* f0 */
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     /* f8 */
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552   },
7553 };
7554
7555 static const struct dis386 xop_table[][256] = {
7556   /* XOP_08 */
7557   {
7558     /* 00 */
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     /* 08 */
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     /* 10 */
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     /* 18 */
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     /* 20 */
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     /* 28 */
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     /* 30 */
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     /* 38 */
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     /* 40 */
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     /* 48 */
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     /* 50 */
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     /* 58 */
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     /* 60 */
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     /* 68 */
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     /* 70 */
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     /* 78 */
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     /* 80 */
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7709     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7710     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7711     /* 88 */
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7719     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7720     /* 90 */
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7727     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7728     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7729     /* 98 */
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7737     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7738     /* a0 */
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7742     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7746     { Bad_Opcode },
7747     /* a8 */
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     /* b0 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7764     { Bad_Opcode },
7765     /* b8 */
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     /* c0 */
7775     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7776     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7777     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7778     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     /* c8 */
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7789     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7790     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7791     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7792     /* d0 */
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     /* d8 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     /* e0 */
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     /* e8 */
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7825     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7826     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7827     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7828     /* f0 */
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     /* f8 */
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846   },
7847   /* XOP_09 */
7848   {
7849     /* 00 */
7850     { Bad_Opcode },
7851     { REG_TABLE (REG_XOP_TBM_01) },
7852     { REG_TABLE (REG_XOP_TBM_02) },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     /* 08 */
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     /* 10 */
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { REG_TABLE (REG_XOP_LWPCB) },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     /* 18 */
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     /* 20 */
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     /* 28 */
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     /* 30 */
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     /* 38 */
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     /* 40 */
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     /* 48 */
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     /* 50 */
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     /* 58 */
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     /* 60 */
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     /* 68 */
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     /* 70 */
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     /* 78 */
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     /* 80 */
7994     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7995     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7996     { "vfrczss",        { XM, EXd }, 0 },
7997     { "vfrczsd",        { XM, EXq }, 0 },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     /* 88 */
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     /* 90 */
8012     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8013     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8014     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8019     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8020     /* 98 */
8021     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8022     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8023     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8024     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     /* a0 */
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     /* a8 */
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     /* b0 */
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     /* b8 */
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     /* c0 */
8066     { Bad_Opcode },
8067     { "vphaddbw",       { XM, EXxmm }, 0 },
8068     { "vphaddbd",       { XM, EXxmm }, 0 },
8069     { "vphaddbq",       { XM, EXxmm }, 0 },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { "vphaddwd",       { XM, EXxmm }, 0 },
8073     { "vphaddwq",       { XM, EXxmm }, 0 },
8074     /* c8 */
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { "vphadddq",       { XM, EXxmm }, 0 },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     /* d0 */
8084     { Bad_Opcode },
8085     { "vphaddubw",      { XM, EXxmm }, 0 },
8086     { "vphaddubd",      { XM, EXxmm }, 0 },
8087     { "vphaddubq",      { XM, EXxmm }, 0 },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { "vphadduwd",      { XM, EXxmm }, 0 },
8091     { "vphadduwq",      { XM, EXxmm }, 0 },
8092     /* d8 */
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { "vphaddudq",      { XM, EXxmm }, 0 },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     /* e0 */
8102     { Bad_Opcode },
8103     { "vphsubbw",       { XM, EXxmm }, 0 },
8104     { "vphsubwd",       { XM, EXxmm }, 0 },
8105     { "vphsubdq",       { XM, EXxmm }, 0 },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     /* e8 */
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     /* f0 */
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     /* f8 */
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137   },
8138   /* XOP_0A */
8139   {
8140     /* 00 */
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     /* 08 */
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     /* 10 */
8159     { "bextrS", { Gdq, Edq, Id }, 0 },
8160     { Bad_Opcode },
8161     { REG_TABLE (REG_XOP_LWP) },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     /* 18 */
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     /* 20 */
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     /* 28 */
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     /* 30 */
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     /* 38 */
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     /* 40 */
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     /* 48 */
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     /* 50 */
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     /* 58 */
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     /* 60 */
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     /* 68 */
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     /* 70 */
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     /* 78 */
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     /* 80 */
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     /* 88 */
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     /* 90 */
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     /* 98 */
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     /* a0 */
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     /* a8 */
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     /* b0 */
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     /* b8 */
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     /* c0 */
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     /* c8 */
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     /* d0 */
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     /* d8 */
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     /* e0 */
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     /* e8 */
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     /* f0 */
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     /* f8 */
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428   },
8429 };
8430
8431 static const struct dis386 vex_table[][256] = {
8432   /* VEX_0F */
8433   {
8434     /* 00 */
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     /* 08 */
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     /* 10 */
8453     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8454     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8455     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8456     { MOD_TABLE (MOD_VEX_0F13) },
8457     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8458     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8459     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8460     { MOD_TABLE (MOD_VEX_0F17) },
8461     /* 18 */
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     /* 20 */
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     /* 28 */
8480     { "vmovapX",        { XM, EXx }, 0 },
8481     { "vmovapX",        { EXxS, XM }, 0 },
8482     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8483     { MOD_TABLE (MOD_VEX_0F2B) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8485     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8486     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8487     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8488     /* 30 */
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     /* 38 */
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     /* 40 */
8507     { Bad_Opcode },
8508     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8509     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8510     { Bad_Opcode },
8511     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8515     /* 48 */
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8519     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     /* 50 */
8525     { MOD_TABLE (MOD_VEX_0F50) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8529     { "vandpX",         { XM, Vex, EXx }, 0 },
8530     { "vandnpX",        { XM, Vex, EXx }, 0 },
8531     { "vorpX",          { XM, Vex, EXx }, 0 },
8532     { "vxorpX",         { XM, Vex, EXx }, 0 },
8533     /* 58 */
8534     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8542     /* 60 */
8543     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8550     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8551     /* 68 */
8552     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8558     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8559     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8560     /* 70 */
8561     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8562     { REG_TABLE (REG_VEX_0F71) },
8563     { REG_TABLE (REG_VEX_0F72) },
8564     { REG_TABLE (REG_VEX_0F73) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8569     /* 78 */
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8578     /* 80 */
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     /* 88 */
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     /* 90 */
8597     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     /* 98 */
8606     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8607     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     /* a0 */
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     /* a8 */
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { REG_TABLE (REG_VEX_0FAE) },
8631     { Bad_Opcode },
8632     /* b0 */
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     /* b8 */
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     /* c0 */
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8654     { Bad_Opcode },
8655     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8656     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8657     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8658     { Bad_Opcode },
8659     /* c8 */
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     /* d0 */
8669     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8677     /* d8 */
8678     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8686     /* e0 */
8687     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8695     /* e8 */
8696     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8704     /* f0 */
8705     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8713     /* f8 */
8714     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8721     { Bad_Opcode },
8722   },
8723   /* VEX_0F38 */
8724   {
8725     /* 00 */
8726     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8734     /* 08 */
8735     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8743     /* 10 */
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8752     /* 18 */
8753     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8756     { Bad_Opcode },
8757     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8760     { Bad_Opcode },
8761     /* 20 */
8762     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     /* 28 */
8771     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8779     /* 30 */
8780     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8788     /* 38 */
8789     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8797     /* 40 */
8798     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8806     /* 48 */
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     /* 50 */
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     /* 58 */
8825     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     /* 60 */
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     /* 68 */
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     /* 70 */
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     /* 78 */
8861     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8862     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     /* 80 */
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     /* 88 */
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8884     { Bad_Opcode },
8885     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8886     { Bad_Opcode },
8887     /* 90 */
8888     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8896     /* 98 */
8897     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8905     /* a0 */
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8914     /* a8 */
8915     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8923     /* b0 */
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8932     /* b8 */
8933     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8941     /* c0 */
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     /* c8 */
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8959     /* d0 */
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     /* d8 */
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8977     /* e0 */
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     /* e8 */
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     /* f0 */
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8999     { REG_TABLE (REG_VEX_0F38F3) },
9000     { Bad_Opcode },
9001     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9004     /* f8 */
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013   },
9014   /* VEX_0F3A */
9015   {
9016     /* 00 */
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9020     { Bad_Opcode },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9024     { Bad_Opcode },
9025     /* 08 */
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9034     /* 10 */
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9043     /* 18 */
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     /* 20 */
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     /* 28 */
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     /* 30 */
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     /* 38 */
9080     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9081     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     /* 40 */
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9092     { Bad_Opcode },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9094     { Bad_Opcode },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9096     { Bad_Opcode },
9097     /* 48 */
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     /* 50 */
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     /* 58 */
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9124     /* 60 */
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     /* 68 */
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9142     /* 70 */
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     /* 78 */
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9160     /* 80 */
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     /* 88 */
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     /* 90 */
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     /* 98 */
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     /* a0 */
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     /* a8 */
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     /* b0 */
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     /* b8 */
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     /* c0 */
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     /* c8 */
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9249     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9250     /* d0 */
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     /* d8 */
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9268     /* e0 */
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     /* e8 */
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     /* f0 */
9287     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     /* f8 */
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304   },
9305 };
9306
9307 #include "i386-dis-evex.h"
9308
9309 static const struct dis386 vex_len_table[][2] = {
9310   /* VEX_LEN_0F12_P_0_M_0 */
9311   {
9312     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9313   },
9314
9315   /* VEX_LEN_0F12_P_0_M_1 */
9316   {
9317     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9318   },
9319
9320   /* VEX_LEN_0F12_P_2 */
9321   {
9322     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9323   },
9324
9325   /* VEX_LEN_0F13_M_0 */
9326   {
9327     { "vmovlpX",        { EXq, XM }, 0 },
9328   },
9329
9330   /* VEX_LEN_0F16_P_0_M_0 */
9331   {
9332     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9333   },
9334
9335   /* VEX_LEN_0F16_P_0_M_1 */
9336   {
9337     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9338   },
9339
9340   /* VEX_LEN_0F16_P_2 */
9341   {
9342     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9343   },
9344
9345   /* VEX_LEN_0F17_M_0 */
9346   {
9347     { "vmovhpX",        { EXq, XM }, 0 },
9348   },
9349
9350   /* VEX_LEN_0F41_P_0 */
9351   {
9352     { Bad_Opcode },
9353     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9354   },
9355   /* VEX_LEN_0F41_P_2 */
9356   {
9357     { Bad_Opcode },
9358     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9359   },
9360   /* VEX_LEN_0F42_P_0 */
9361   {
9362     { Bad_Opcode },
9363     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9364   },
9365   /* VEX_LEN_0F42_P_2 */
9366   {
9367     { Bad_Opcode },
9368     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9369   },
9370   /* VEX_LEN_0F44_P_0 */
9371   {
9372     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9373   },
9374   /* VEX_LEN_0F44_P_2 */
9375   {
9376     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9377   },
9378   /* VEX_LEN_0F45_P_0 */
9379   {
9380     { Bad_Opcode },
9381     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9382   },
9383   /* VEX_LEN_0F45_P_2 */
9384   {
9385     { Bad_Opcode },
9386     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9387   },
9388   /* VEX_LEN_0F46_P_0 */
9389   {
9390     { Bad_Opcode },
9391     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9392   },
9393   /* VEX_LEN_0F46_P_2 */
9394   {
9395     { Bad_Opcode },
9396     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9397   },
9398   /* VEX_LEN_0F47_P_0 */
9399   {
9400     { Bad_Opcode },
9401     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9402   },
9403   /* VEX_LEN_0F47_P_2 */
9404   {
9405     { Bad_Opcode },
9406     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9407   },
9408   /* VEX_LEN_0F4A_P_0 */
9409   {
9410     { Bad_Opcode },
9411     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9412   },
9413   /* VEX_LEN_0F4A_P_2 */
9414   {
9415     { Bad_Opcode },
9416     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9417   },
9418   /* VEX_LEN_0F4B_P_0 */
9419   {
9420     { Bad_Opcode },
9421     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9422   },
9423   /* VEX_LEN_0F4B_P_2 */
9424   {
9425     { Bad_Opcode },
9426     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9427   },
9428
9429   /* VEX_LEN_0F6E_P_2 */
9430   {
9431     { "vmovK",          { XMScalar, Edq }, 0 },
9432   },
9433
9434   /* VEX_LEN_0F77_P_1 */
9435   {
9436     { "vzeroupper",     { XX }, 0 },
9437     { "vzeroall",       { XX }, 0 },
9438   },
9439
9440   /* VEX_LEN_0F7E_P_1 */
9441   {
9442     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9443   },
9444
9445   /* VEX_LEN_0F7E_P_2 */
9446   {
9447     { "vmovK",          { Edq, XMScalar }, 0 },
9448   },
9449
9450   /* VEX_LEN_0F90_P_0 */
9451   {
9452     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9453   },
9454
9455   /* VEX_LEN_0F90_P_2 */
9456   {
9457     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9458   },
9459
9460   /* VEX_LEN_0F91_P_0 */
9461   {
9462     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9463   },
9464
9465   /* VEX_LEN_0F91_P_2 */
9466   {
9467     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9468   },
9469
9470   /* VEX_LEN_0F92_P_0 */
9471   {
9472     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9473   },
9474
9475   /* VEX_LEN_0F92_P_2 */
9476   {
9477     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9478   },
9479
9480   /* VEX_LEN_0F92_P_3 */
9481   {
9482     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9483   },
9484
9485   /* VEX_LEN_0F93_P_0 */
9486   {
9487     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9488   },
9489
9490   /* VEX_LEN_0F93_P_2 */
9491   {
9492     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9493   },
9494
9495   /* VEX_LEN_0F93_P_3 */
9496   {
9497     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9498   },
9499
9500   /* VEX_LEN_0F98_P_0 */
9501   {
9502     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9503   },
9504
9505   /* VEX_LEN_0F98_P_2 */
9506   {
9507     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9508   },
9509
9510   /* VEX_LEN_0F99_P_0 */
9511   {
9512     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9513   },
9514
9515   /* VEX_LEN_0F99_P_2 */
9516   {
9517     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9518   },
9519
9520   /* VEX_LEN_0FAE_R_2_M_0 */
9521   {
9522     { "vldmxcsr",       { Md }, 0 },
9523   },
9524
9525   /* VEX_LEN_0FAE_R_3_M_0 */
9526   {
9527     { "vstmxcsr",       { Md }, 0 },
9528   },
9529
9530   /* VEX_LEN_0FC4_P_2 */
9531   {
9532     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9533   },
9534
9535   /* VEX_LEN_0FC5_P_2 */
9536   {
9537     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9538   },
9539
9540   /* VEX_LEN_0FD6_P_2 */
9541   {
9542     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9543   },
9544
9545   /* VEX_LEN_0FF7_P_2 */
9546   {
9547     { "vmaskmovdqu",    { XM, XS }, 0 },
9548   },
9549
9550   /* VEX_LEN_0F3816_P_2 */
9551   {
9552     { Bad_Opcode },
9553     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9554   },
9555
9556   /* VEX_LEN_0F3819_P_2 */
9557   {
9558     { Bad_Opcode },
9559     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9560   },
9561
9562   /* VEX_LEN_0F381A_P_2_M_0 */
9563   {
9564     { Bad_Opcode },
9565     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9566   },
9567
9568   /* VEX_LEN_0F3836_P_2 */
9569   {
9570     { Bad_Opcode },
9571     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9572   },
9573
9574   /* VEX_LEN_0F3841_P_2 */
9575   {
9576     { "vphminposuw",    { XM, EXx }, 0 },
9577   },
9578
9579   /* VEX_LEN_0F385A_P_2_M_0 */
9580   {
9581     { Bad_Opcode },
9582     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9583   },
9584
9585   /* VEX_LEN_0F38DB_P_2 */
9586   {
9587     { "vaesimc",        { XM, EXx }, 0 },
9588   },
9589
9590   /* VEX_LEN_0F38F2_P_0 */
9591   {
9592     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9593   },
9594
9595   /* VEX_LEN_0F38F3_R_1_P_0 */
9596   {
9597     { "blsrS",          { VexGdq, Edq }, 0 },
9598   },
9599
9600   /* VEX_LEN_0F38F3_R_2_P_0 */
9601   {
9602     { "blsmskS",        { VexGdq, Edq }, 0 },
9603   },
9604
9605   /* VEX_LEN_0F38F3_R_3_P_0 */
9606   {
9607     { "blsiS",          { VexGdq, Edq }, 0 },
9608   },
9609
9610   /* VEX_LEN_0F38F5_P_0 */
9611   {
9612     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9613   },
9614
9615   /* VEX_LEN_0F38F5_P_1 */
9616   {
9617     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9618   },
9619
9620   /* VEX_LEN_0F38F5_P_3 */
9621   {
9622     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9623   },
9624
9625   /* VEX_LEN_0F38F6_P_3 */
9626   {
9627     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9628   },
9629
9630   /* VEX_LEN_0F38F7_P_0 */
9631   {
9632     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9633   },
9634
9635   /* VEX_LEN_0F38F7_P_1 */
9636   {
9637     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9638   },
9639
9640   /* VEX_LEN_0F38F7_P_2 */
9641   {
9642     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9643   },
9644
9645   /* VEX_LEN_0F38F7_P_3 */
9646   {
9647     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9648   },
9649
9650   /* VEX_LEN_0F3A00_P_2 */
9651   {
9652     { Bad_Opcode },
9653     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9654   },
9655
9656   /* VEX_LEN_0F3A01_P_2 */
9657   {
9658     { Bad_Opcode },
9659     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9660   },
9661
9662   /* VEX_LEN_0F3A06_P_2 */
9663   {
9664     { Bad_Opcode },
9665     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9666   },
9667
9668   /* VEX_LEN_0F3A14_P_2 */
9669   {
9670     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9671   },
9672
9673   /* VEX_LEN_0F3A15_P_2 */
9674   {
9675     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9676   },
9677
9678   /* VEX_LEN_0F3A16_P_2  */
9679   {
9680     { "vpextrK",        { Edq, XM, Ib }, 0 },
9681   },
9682
9683   /* VEX_LEN_0F3A17_P_2 */
9684   {
9685     { "vextractps",     { Edqd, XM, Ib }, 0 },
9686   },
9687
9688   /* VEX_LEN_0F3A18_P_2 */
9689   {
9690     { Bad_Opcode },
9691     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9692   },
9693
9694   /* VEX_LEN_0F3A19_P_2 */
9695   {
9696     { Bad_Opcode },
9697     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9698   },
9699
9700   /* VEX_LEN_0F3A20_P_2 */
9701   {
9702     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9703   },
9704
9705   /* VEX_LEN_0F3A21_P_2 */
9706   {
9707     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9708   },
9709
9710   /* VEX_LEN_0F3A22_P_2 */
9711   {
9712     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9713   },
9714
9715   /* VEX_LEN_0F3A30_P_2 */
9716   {
9717     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9718   },
9719
9720   /* VEX_LEN_0F3A31_P_2 */
9721   {
9722     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9723   },
9724
9725   /* VEX_LEN_0F3A32_P_2 */
9726   {
9727     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9728   },
9729
9730   /* VEX_LEN_0F3A33_P_2 */
9731   {
9732     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9733   },
9734
9735   /* VEX_LEN_0F3A38_P_2 */
9736   {
9737     { Bad_Opcode },
9738     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9739   },
9740
9741   /* VEX_LEN_0F3A39_P_2 */
9742   {
9743     { Bad_Opcode },
9744     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9745   },
9746
9747   /* VEX_LEN_0F3A41_P_2 */
9748   {
9749     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9750   },
9751
9752   /* VEX_LEN_0F3A46_P_2 */
9753   {
9754     { Bad_Opcode },
9755     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9756   },
9757
9758   /* VEX_LEN_0F3A60_P_2 */
9759   {
9760     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9761   },
9762
9763   /* VEX_LEN_0F3A61_P_2 */
9764   {
9765     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9766   },
9767
9768   /* VEX_LEN_0F3A62_P_2 */
9769   {
9770     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9771   },
9772
9773   /* VEX_LEN_0F3A63_P_2 */
9774   {
9775     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9776   },
9777
9778   /* VEX_LEN_0F3A6A_P_2 */
9779   {
9780     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9781   },
9782
9783   /* VEX_LEN_0F3A6B_P_2 */
9784   {
9785     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9786   },
9787
9788   /* VEX_LEN_0F3A6E_P_2 */
9789   {
9790     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9791   },
9792
9793   /* VEX_LEN_0F3A6F_P_2 */
9794   {
9795     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9796   },
9797
9798   /* VEX_LEN_0F3A7A_P_2 */
9799   {
9800     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9801   },
9802
9803   /* VEX_LEN_0F3A7B_P_2 */
9804   {
9805     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9806   },
9807
9808   /* VEX_LEN_0F3A7E_P_2 */
9809   {
9810     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9811   },
9812
9813   /* VEX_LEN_0F3A7F_P_2 */
9814   {
9815     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9816   },
9817
9818   /* VEX_LEN_0F3ADF_P_2 */
9819   {
9820     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9821   },
9822
9823   /* VEX_LEN_0F3AF0_P_3 */
9824   {
9825     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9826   },
9827
9828   /* VEX_LEN_0FXOP_08_CC */
9829   {
9830      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9831   },
9832
9833   /* VEX_LEN_0FXOP_08_CD */
9834   {
9835      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9836   },
9837
9838   /* VEX_LEN_0FXOP_08_CE */
9839   {
9840      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9841   },
9842
9843   /* VEX_LEN_0FXOP_08_CF */
9844   {
9845      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9846   },
9847
9848   /* VEX_LEN_0FXOP_08_EC */
9849   {
9850      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9851   },
9852
9853   /* VEX_LEN_0FXOP_08_ED */
9854   {
9855      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9856   },
9857
9858   /* VEX_LEN_0FXOP_08_EE */
9859   {
9860      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9861   },
9862
9863   /* VEX_LEN_0FXOP_08_EF */
9864   {
9865      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9866   },
9867
9868   /* VEX_LEN_0FXOP_09_80 */
9869   {
9870     { "vfrczps",        { XM, EXxmm }, 0 },
9871     { "vfrczps",        { XM, EXymmq }, 0 },
9872   },
9873
9874   /* VEX_LEN_0FXOP_09_81 */
9875   {
9876     { "vfrczpd",        { XM, EXxmm }, 0 },
9877     { "vfrczpd",        { XM, EXymmq }, 0 },
9878   },
9879 };
9880
9881 #include "i386-dis-evex-len.h"
9882
9883 static const struct dis386 vex_w_table[][2] = {
9884   {
9885     /* VEX_W_0F41_P_0_LEN_1 */
9886     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9887     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9888   },
9889   {
9890     /* VEX_W_0F41_P_2_LEN_1 */
9891     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9892     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9893   },
9894   {
9895     /* VEX_W_0F42_P_0_LEN_1 */
9896     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9897     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9898   },
9899   {
9900     /* VEX_W_0F42_P_2_LEN_1 */
9901     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9902     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9903   },
9904   {
9905     /* VEX_W_0F44_P_0_LEN_0 */
9906     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9907     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9908   },
9909   {
9910     /* VEX_W_0F44_P_2_LEN_0 */
9911     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9912     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9913   },
9914   {
9915     /* VEX_W_0F45_P_0_LEN_1 */
9916     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9917     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9918   },
9919   {
9920     /* VEX_W_0F45_P_2_LEN_1 */
9921     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9922     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9923   },
9924   {
9925     /* VEX_W_0F46_P_0_LEN_1 */
9926     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9927     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9928   },
9929   {
9930     /* VEX_W_0F46_P_2_LEN_1 */
9931     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9932     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9933   },
9934   {
9935     /* VEX_W_0F47_P_0_LEN_1 */
9936     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9937     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9938   },
9939   {
9940     /* VEX_W_0F47_P_2_LEN_1 */
9941     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9942     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9943   },
9944   {
9945     /* VEX_W_0F4A_P_0_LEN_1 */
9946     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9947     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9948   },
9949   {
9950     /* VEX_W_0F4A_P_2_LEN_1 */
9951     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9952     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9953   },
9954   {
9955     /* VEX_W_0F4B_P_0_LEN_1 */
9956     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9957     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9958   },
9959   {
9960     /* VEX_W_0F4B_P_2_LEN_1 */
9961     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9962   },
9963   {
9964     /* VEX_W_0F90_P_0_LEN_0 */
9965     { "kmovw",          { MaskG, MaskE }, 0 },
9966     { "kmovq",          { MaskG, MaskE }, 0 },
9967   },
9968   {
9969     /* VEX_W_0F90_P_2_LEN_0 */
9970     { "kmovb",          { MaskG, MaskBDE }, 0 },
9971     { "kmovd",          { MaskG, MaskBDE }, 0 },
9972   },
9973   {
9974     /* VEX_W_0F91_P_0_LEN_0 */
9975     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9976     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9977   },
9978   {
9979     /* VEX_W_0F91_P_2_LEN_0 */
9980     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9981     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9982   },
9983   {
9984     /* VEX_W_0F92_P_0_LEN_0 */
9985     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9986   },
9987   {
9988     /* VEX_W_0F92_P_2_LEN_0 */
9989     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9990   },
9991   {
9992     /* VEX_W_0F93_P_0_LEN_0 */
9993     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9994   },
9995   {
9996     /* VEX_W_0F93_P_2_LEN_0 */
9997     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9998   },
9999   {
10000     /* VEX_W_0F98_P_0_LEN_0 */
10001     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10002     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10003   },
10004   {
10005     /* VEX_W_0F98_P_2_LEN_0 */
10006     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10007     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10008   },
10009   {
10010     /* VEX_W_0F99_P_0_LEN_0 */
10011     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10012     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10013   },
10014   {
10015     /* VEX_W_0F99_P_2_LEN_0 */
10016     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10017     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10018   },
10019   {
10020     /* VEX_W_0F380C_P_2  */
10021     { "vpermilps",      { XM, Vex, EXx }, 0 },
10022   },
10023   {
10024     /* VEX_W_0F380D_P_2  */
10025     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10026   },
10027   {
10028     /* VEX_W_0F380E_P_2  */
10029     { "vtestps",        { XM, EXx }, 0 },
10030   },
10031   {
10032     /* VEX_W_0F380F_P_2  */
10033     { "vtestpd",        { XM, EXx }, 0 },
10034   },
10035   {
10036     /* VEX_W_0F3816_P_2  */
10037     { "vpermps",        { XM, Vex, EXx }, 0 },
10038   },
10039   {
10040     /* VEX_W_0F3818_P_2 */
10041     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10042   },
10043   {
10044     /* VEX_W_0F3819_P_2 */
10045     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10046   },
10047   {
10048     /* VEX_W_0F381A_P_2_M_0 */
10049     { "vbroadcastf128", { XM, Mxmm }, 0 },
10050   },
10051   {
10052     /* VEX_W_0F382C_P_2_M_0 */
10053     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10054   },
10055   {
10056     /* VEX_W_0F382D_P_2_M_0 */
10057     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10058   },
10059   {
10060     /* VEX_W_0F382E_P_2_M_0 */
10061     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10062   },
10063   {
10064     /* VEX_W_0F382F_P_2_M_0 */
10065     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10066   },
10067   {
10068     /* VEX_W_0F3836_P_2  */
10069     { "vpermd",         { XM, Vex, EXx }, 0 },
10070   },
10071   {
10072     /* VEX_W_0F3846_P_2 */
10073     { "vpsravd",        { XM, Vex, EXx }, 0 },
10074   },
10075   {
10076     /* VEX_W_0F3858_P_2 */
10077     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10078   },
10079   {
10080     /* VEX_W_0F3859_P_2 */
10081     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10082   },
10083   {
10084     /* VEX_W_0F385A_P_2_M_0 */
10085     { "vbroadcasti128", { XM, Mxmm }, 0 },
10086   },
10087   {
10088     /* VEX_W_0F3878_P_2 */
10089     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10090   },
10091   {
10092     /* VEX_W_0F3879_P_2 */
10093     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10094   },
10095   {
10096     /* VEX_W_0F38CF_P_2 */
10097     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10098   },
10099   {
10100     /* VEX_W_0F3A00_P_2 */
10101     { Bad_Opcode },
10102     { "vpermq",         { XM, EXx, Ib }, 0 },
10103   },
10104   {
10105     /* VEX_W_0F3A01_P_2 */
10106     { Bad_Opcode },
10107     { "vpermpd",        { XM, EXx, Ib }, 0 },
10108   },
10109   {
10110     /* VEX_W_0F3A02_P_2 */
10111     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10112   },
10113   {
10114     /* VEX_W_0F3A04_P_2 */
10115     { "vpermilps",      { XM, EXx, Ib }, 0 },
10116   },
10117   {
10118     /* VEX_W_0F3A05_P_2 */
10119     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10120   },
10121   {
10122     /* VEX_W_0F3A06_P_2 */
10123     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10124   },
10125   {
10126     /* VEX_W_0F3A18_P_2 */
10127     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10128   },
10129   {
10130     /* VEX_W_0F3A19_P_2 */
10131     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10132   },
10133   {
10134     /* VEX_W_0F3A30_P_2_LEN_0 */
10135     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10136     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10137   },
10138   {
10139     /* VEX_W_0F3A31_P_2_LEN_0 */
10140     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10141     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10142   },
10143   {
10144     /* VEX_W_0F3A32_P_2_LEN_0 */
10145     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10146     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10147   },
10148   {
10149     /* VEX_W_0F3A33_P_2_LEN_0 */
10150     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10151     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10152   },
10153   {
10154     /* VEX_W_0F3A38_P_2 */
10155     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10156   },
10157   {
10158     /* VEX_W_0F3A39_P_2 */
10159     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10160   },
10161   {
10162     /* VEX_W_0F3A46_P_2 */
10163     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10164   },
10165   {
10166     /* VEX_W_0F3A48_P_2 */
10167     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10168     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10169   },
10170   {
10171     /* VEX_W_0F3A49_P_2 */
10172     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10173     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10174   },
10175   {
10176     /* VEX_W_0F3A4A_P_2 */
10177     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10178   },
10179   {
10180     /* VEX_W_0F3A4B_P_2 */
10181     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10182   },
10183   {
10184     /* VEX_W_0F3A4C_P_2 */
10185     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10186   },
10187   {
10188     /* VEX_W_0F3ACE_P_2 */
10189     { Bad_Opcode },
10190     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10191   },
10192   {
10193     /* VEX_W_0F3ACF_P_2 */
10194     { Bad_Opcode },
10195     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10196   },
10197
10198 #include "i386-dis-evex-w.h"
10199 };
10200
10201 static const struct dis386 mod_table[][2] = {
10202   {
10203     /* MOD_8D */
10204     { "leaS",           { Gv, M }, 0 },
10205   },
10206   {
10207     /* MOD_C6_REG_7 */
10208     { Bad_Opcode },
10209     { RM_TABLE (RM_C6_REG_7) },
10210   },
10211   {
10212     /* MOD_C7_REG_7 */
10213     { Bad_Opcode },
10214     { RM_TABLE (RM_C7_REG_7) },
10215   },
10216   {
10217     /* MOD_FF_REG_3 */
10218     { "Jcall^", { indirEp }, 0 },
10219   },
10220   {
10221     /* MOD_FF_REG_5 */
10222     { "Jjmp^", { indirEp }, 0 },
10223   },
10224   {
10225     /* MOD_0F01_REG_0 */
10226     { X86_64_TABLE (X86_64_0F01_REG_0) },
10227     { RM_TABLE (RM_0F01_REG_0) },
10228   },
10229   {
10230     /* MOD_0F01_REG_1 */
10231     { X86_64_TABLE (X86_64_0F01_REG_1) },
10232     { RM_TABLE (RM_0F01_REG_1) },
10233   },
10234   {
10235     /* MOD_0F01_REG_2 */
10236     { X86_64_TABLE (X86_64_0F01_REG_2) },
10237     { RM_TABLE (RM_0F01_REG_2) },
10238   },
10239   {
10240     /* MOD_0F01_REG_3 */
10241     { X86_64_TABLE (X86_64_0F01_REG_3) },
10242     { RM_TABLE (RM_0F01_REG_3) },
10243   },
10244   {
10245     /* MOD_0F01_REG_5 */
10246     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10247     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10248   },
10249   {
10250     /* MOD_0F01_REG_7 */
10251     { "invlpg",         { Mb }, 0 },
10252     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10253   },
10254   {
10255     /* MOD_0F12_PREFIX_0 */
10256     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10257     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10258   },
10259   {
10260     /* MOD_0F13 */
10261     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10262   },
10263   {
10264     /* MOD_0F16_PREFIX_0 */
10265     { "movhps",         { XM, EXq }, 0 },
10266     { "movlhps",        { XM, EXq }, 0 },
10267   },
10268   {
10269     /* MOD_0F17 */
10270     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10271   },
10272   {
10273     /* MOD_0F18_REG_0 */
10274     { "prefetchnta",    { Mb }, 0 },
10275   },
10276   {
10277     /* MOD_0F18_REG_1 */
10278     { "prefetcht0",     { Mb }, 0 },
10279   },
10280   {
10281     /* MOD_0F18_REG_2 */
10282     { "prefetcht1",     { Mb }, 0 },
10283   },
10284   {
10285     /* MOD_0F18_REG_3 */
10286     { "prefetcht2",     { Mb }, 0 },
10287   },
10288   {
10289     /* MOD_0F18_REG_4 */
10290     { "nop/reserved",   { Mb }, 0 },
10291   },
10292   {
10293     /* MOD_0F18_REG_5 */
10294     { "nop/reserved",   { Mb }, 0 },
10295   },
10296   {
10297     /* MOD_0F18_REG_6 */
10298     { "nop/reserved",   { Mb }, 0 },
10299   },
10300   {
10301     /* MOD_0F18_REG_7 */
10302     { "nop/reserved",   { Mb }, 0 },
10303   },
10304   {
10305     /* MOD_0F1A_PREFIX_0 */
10306     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10307     { "nopQ",           { Ev }, 0 },
10308   },
10309   {
10310     /* MOD_0F1B_PREFIX_0 */
10311     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10312     { "nopQ",           { Ev }, 0 },
10313   },
10314   {
10315     /* MOD_0F1B_PREFIX_1 */
10316     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10317     { "nopQ",           { Ev }, 0 },
10318   },
10319   {
10320     /* MOD_0F1C_PREFIX_0 */
10321     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10322     { "nopQ",           { Ev }, 0 },
10323   },
10324   {
10325     /* MOD_0F1E_PREFIX_1 */
10326     { "nopQ",           { Ev }, 0 },
10327     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10328   },
10329   {
10330     /* MOD_0F24 */
10331     { Bad_Opcode },
10332     { "movL",           { Rd, Td }, 0 },
10333   },
10334   {
10335     /* MOD_0F26 */
10336     { Bad_Opcode },
10337     { "movL",           { Td, Rd }, 0 },
10338   },
10339   {
10340     /* MOD_0F2B_PREFIX_0 */
10341     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10342   },
10343   {
10344     /* MOD_0F2B_PREFIX_1 */
10345     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10346   },
10347   {
10348     /* MOD_0F2B_PREFIX_2 */
10349     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10350   },
10351   {
10352     /* MOD_0F2B_PREFIX_3 */
10353     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10354   },
10355   {
10356     /* MOD_0F51 */
10357     { Bad_Opcode },
10358     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10359   },
10360   {
10361     /* MOD_0F71_REG_2 */
10362     { Bad_Opcode },
10363     { "psrlw",          { MS, Ib }, 0 },
10364   },
10365   {
10366     /* MOD_0F71_REG_4 */
10367     { Bad_Opcode },
10368     { "psraw",          { MS, Ib }, 0 },
10369   },
10370   {
10371     /* MOD_0F71_REG_6 */
10372     { Bad_Opcode },
10373     { "psllw",          { MS, Ib }, 0 },
10374   },
10375   {
10376     /* MOD_0F72_REG_2 */
10377     { Bad_Opcode },
10378     { "psrld",          { MS, Ib }, 0 },
10379   },
10380   {
10381     /* MOD_0F72_REG_4 */
10382     { Bad_Opcode },
10383     { "psrad",          { MS, Ib }, 0 },
10384   },
10385   {
10386     /* MOD_0F72_REG_6 */
10387     { Bad_Opcode },
10388     { "pslld",          { MS, Ib }, 0 },
10389   },
10390   {
10391     /* MOD_0F73_REG_2 */
10392     { Bad_Opcode },
10393     { "psrlq",          { MS, Ib }, 0 },
10394   },
10395   {
10396     /* MOD_0F73_REG_3 */
10397     { Bad_Opcode },
10398     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10399   },
10400   {
10401     /* MOD_0F73_REG_6 */
10402     { Bad_Opcode },
10403     { "psllq",          { MS, Ib }, 0 },
10404   },
10405   {
10406     /* MOD_0F73_REG_7 */
10407     { Bad_Opcode },
10408     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10409   },
10410   {
10411     /* MOD_0FAE_REG_0 */
10412     { "fxsave",         { FXSAVE }, 0 },
10413     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10414   },
10415   {
10416     /* MOD_0FAE_REG_1 */
10417     { "fxrstor",        { FXSAVE }, 0 },
10418     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10419   },
10420   {
10421     /* MOD_0FAE_REG_2 */
10422     { "ldmxcsr",        { Md }, 0 },
10423     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10424   },
10425   {
10426     /* MOD_0FAE_REG_3 */
10427     { "stmxcsr",        { Md }, 0 },
10428     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10429   },
10430   {
10431     /* MOD_0FAE_REG_4 */
10432     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10433     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10434   },
10435   {
10436     /* MOD_0FAE_REG_5 */
10437     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10438     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10439   },
10440   {
10441     /* MOD_0FAE_REG_6 */
10442     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10443     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10444   },
10445   {
10446     /* MOD_0FAE_REG_7 */
10447     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10448     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10449   },
10450   {
10451     /* MOD_0FB2 */
10452     { "lssS",           { Gv, Mp }, 0 },
10453   },
10454   {
10455     /* MOD_0FB4 */
10456     { "lfsS",           { Gv, Mp }, 0 },
10457   },
10458   {
10459     /* MOD_0FB5 */
10460     { "lgsS",           { Gv, Mp }, 0 },
10461   },
10462   {
10463     /* MOD_0FC3 */
10464     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10465   },
10466   {
10467     /* MOD_0FC7_REG_3 */
10468     { "xrstors",        { FXSAVE }, 0 },
10469   },
10470   {
10471     /* MOD_0FC7_REG_4 */
10472     { "xsavec",         { FXSAVE }, 0 },
10473   },
10474   {
10475     /* MOD_0FC7_REG_5 */
10476     { "xsaves",         { FXSAVE }, 0 },
10477   },
10478   {
10479     /* MOD_0FC7_REG_6 */
10480     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10481     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10482   },
10483   {
10484     /* MOD_0FC7_REG_7 */
10485     { "vmptrst",        { Mq }, 0 },
10486     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10487   },
10488   {
10489     /* MOD_0FD7 */
10490     { Bad_Opcode },
10491     { "pmovmskb",       { Gdq, MS }, 0 },
10492   },
10493   {
10494     /* MOD_0FE7_PREFIX_2 */
10495     { "movntdq",        { Mx, XM }, 0 },
10496   },
10497   {
10498     /* MOD_0FF0_PREFIX_3 */
10499     { "lddqu",          { XM, M }, 0 },
10500   },
10501   {
10502     /* MOD_0F382A_PREFIX_2 */
10503     { "movntdqa",       { XM, Mx }, 0 },
10504   },
10505   {
10506     /* MOD_0F38F5_PREFIX_2 */
10507     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10508   },
10509   {
10510     /* MOD_0F38F6_PREFIX_0 */
10511     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10512   },
10513   {
10514     /* MOD_0F38F8_PREFIX_1 */
10515     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10516   },
10517   {
10518     /* MOD_0F38F8_PREFIX_2 */
10519     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10520   },
10521   {
10522     /* MOD_0F38F8_PREFIX_3 */
10523     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10524   },
10525   {
10526     /* MOD_0F38F9_PREFIX_0 */
10527     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10528   },
10529   {
10530     /* MOD_62_32BIT */
10531     { "bound{S|}",      { Gv, Ma }, 0 },
10532     { EVEX_TABLE (EVEX_0F) },
10533   },
10534   {
10535     /* MOD_C4_32BIT */
10536     { "lesS",           { Gv, Mp }, 0 },
10537     { VEX_C4_TABLE (VEX_0F) },
10538   },
10539   {
10540     /* MOD_C5_32BIT */
10541     { "ldsS",           { Gv, Mp }, 0 },
10542     { VEX_C5_TABLE (VEX_0F) },
10543   },
10544   {
10545     /* MOD_VEX_0F12_PREFIX_0 */
10546     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10547     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10548   },
10549   {
10550     /* MOD_VEX_0F13 */
10551     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10552   },
10553   {
10554     /* MOD_VEX_0F16_PREFIX_0 */
10555     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10556     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10557   },
10558   {
10559     /* MOD_VEX_0F17 */
10560     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10561   },
10562   {
10563     /* MOD_VEX_0F2B */
10564     { "vmovntpX",       { Mx, XM }, 0 },
10565   },
10566   {
10567     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10568     { Bad_Opcode },
10569     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10570   },
10571   {
10572     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10573     { Bad_Opcode },
10574     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10575   },
10576   {
10577     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10578     { Bad_Opcode },
10579     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10580   },
10581   {
10582     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10583     { Bad_Opcode },
10584     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10585   },
10586   {
10587     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10588     { Bad_Opcode },
10589     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10590   },
10591   {
10592     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10593     { Bad_Opcode },
10594     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10595   },
10596   {
10597     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10598     { Bad_Opcode },
10599     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10600   },
10601   {
10602     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10603     { Bad_Opcode },
10604     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10605   },
10606   {
10607     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10608     { Bad_Opcode },
10609     { "knotw",          { MaskG, MaskR }, 0 },
10610   },
10611   {
10612     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10613     { Bad_Opcode },
10614     { "knotq",          { MaskG, MaskR }, 0 },
10615   },
10616   {
10617     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10618     { Bad_Opcode },
10619     { "knotb",          { MaskG, MaskR }, 0 },
10620   },
10621   {
10622     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10623     { Bad_Opcode },
10624     { "knotd",          { MaskG, MaskR }, 0 },
10625   },
10626   {
10627     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10628     { Bad_Opcode },
10629     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10630   },
10631   {
10632     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10633     { Bad_Opcode },
10634     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10635   },
10636   {
10637     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10638     { Bad_Opcode },
10639     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10640   },
10641   {
10642     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10643     { Bad_Opcode },
10644     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10645   },
10646  {
10647     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10648     { Bad_Opcode },
10649     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10650   },
10651   {
10652     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10653     { Bad_Opcode },
10654     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10655   },
10656   {
10657     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10658     { Bad_Opcode },
10659     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10660   },
10661   {
10662     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10663     { Bad_Opcode },
10664     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10665   },
10666   {
10667     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10668     { Bad_Opcode },
10669     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10670   },
10671   {
10672     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10673     { Bad_Opcode },
10674     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10675   },
10676   {
10677     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10678     { Bad_Opcode },
10679     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10680   },
10681   {
10682     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10683     { Bad_Opcode },
10684     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10685   },
10686   {
10687     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10688     { Bad_Opcode },
10689     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10690   },
10691   {
10692     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10693     { Bad_Opcode },
10694     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10695   },
10696   {
10697     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10698     { Bad_Opcode },
10699     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10700   },
10701   {
10702     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10703     { Bad_Opcode },
10704     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10705   },
10706   {
10707     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10708     { Bad_Opcode },
10709     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10710   },
10711   {
10712     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10713     { Bad_Opcode },
10714     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10715   },
10716   {
10717     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10718     { Bad_Opcode },
10719     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10720   },
10721   {
10722     /* MOD_VEX_0F50 */
10723     { Bad_Opcode },
10724     { "vmovmskpX",      { Gdq, XS }, 0 },
10725   },
10726   {
10727     /* MOD_VEX_0F71_REG_2 */
10728     { Bad_Opcode },
10729     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10730   },
10731   {
10732     /* MOD_VEX_0F71_REG_4 */
10733     { Bad_Opcode },
10734     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10735   },
10736   {
10737     /* MOD_VEX_0F71_REG_6 */
10738     { Bad_Opcode },
10739     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10740   },
10741   {
10742     /* MOD_VEX_0F72_REG_2 */
10743     { Bad_Opcode },
10744     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10745   },
10746   {
10747     /* MOD_VEX_0F72_REG_4 */
10748     { Bad_Opcode },
10749     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10750   },
10751   {
10752     /* MOD_VEX_0F72_REG_6 */
10753     { Bad_Opcode },
10754     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10755   },
10756   {
10757     /* MOD_VEX_0F73_REG_2 */
10758     { Bad_Opcode },
10759     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10760   },
10761   {
10762     /* MOD_VEX_0F73_REG_3 */
10763     { Bad_Opcode },
10764     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10765   },
10766   {
10767     /* MOD_VEX_0F73_REG_6 */
10768     { Bad_Opcode },
10769     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10770   },
10771   {
10772     /* MOD_VEX_0F73_REG_7 */
10773     { Bad_Opcode },
10774     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10775   },
10776   {
10777     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10778     { "kmovw",          { Ew, MaskG }, 0 },
10779     { Bad_Opcode },
10780   },
10781   {
10782     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10783     { "kmovq",          { Eq, MaskG }, 0 },
10784     { Bad_Opcode },
10785   },
10786   {
10787     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10788     { "kmovb",          { Eb, MaskG }, 0 },
10789     { Bad_Opcode },
10790   },
10791   {
10792     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10793     { "kmovd",          { Ed, MaskG }, 0 },
10794     { Bad_Opcode },
10795   },
10796   {
10797     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10798     { Bad_Opcode },
10799     { "kmovw",          { MaskG, Rdq }, 0 },
10800   },
10801   {
10802     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10803     { Bad_Opcode },
10804     { "kmovb",          { MaskG, Rdq }, 0 },
10805   },
10806   {
10807     /* MOD_VEX_0F92_P_3_LEN_0 */
10808     { Bad_Opcode },
10809     { "kmovK",          { MaskG, Rdq }, 0 },
10810   },
10811   {
10812     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10813     { Bad_Opcode },
10814     { "kmovw",          { Gdq, MaskR }, 0 },
10815   },
10816   {
10817     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10818     { Bad_Opcode },
10819     { "kmovb",          { Gdq, MaskR }, 0 },
10820   },
10821   {
10822     /* MOD_VEX_0F93_P_3_LEN_0 */
10823     { Bad_Opcode },
10824     { "kmovK",          { Gdq, MaskR }, 0 },
10825   },
10826   {
10827     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10828     { Bad_Opcode },
10829     { "kortestw", { MaskG, MaskR }, 0 },
10830   },
10831   {
10832     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10833     { Bad_Opcode },
10834     { "kortestq", { MaskG, MaskR }, 0 },
10835   },
10836   {
10837     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10838     { Bad_Opcode },
10839     { "kortestb", { MaskG, MaskR }, 0 },
10840   },
10841   {
10842     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10843     { Bad_Opcode },
10844     { "kortestd", { MaskG, MaskR }, 0 },
10845   },
10846   {
10847     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10848     { Bad_Opcode },
10849     { "ktestw", { MaskG, MaskR }, 0 },
10850   },
10851   {
10852     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10853     { Bad_Opcode },
10854     { "ktestq", { MaskG, MaskR }, 0 },
10855   },
10856   {
10857     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10858     { Bad_Opcode },
10859     { "ktestb", { MaskG, MaskR }, 0 },
10860   },
10861   {
10862     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10863     { Bad_Opcode },
10864     { "ktestd", { MaskG, MaskR }, 0 },
10865   },
10866   {
10867     /* MOD_VEX_0FAE_REG_2 */
10868     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10869   },
10870   {
10871     /* MOD_VEX_0FAE_REG_3 */
10872     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10873   },
10874   {
10875     /* MOD_VEX_0FD7_PREFIX_2 */
10876     { Bad_Opcode },
10877     { "vpmovmskb",      { Gdq, XS }, 0 },
10878   },
10879   {
10880     /* MOD_VEX_0FE7_PREFIX_2 */
10881     { "vmovntdq",       { Mx, XM }, 0 },
10882   },
10883   {
10884     /* MOD_VEX_0FF0_PREFIX_3 */
10885     { "vlddqu",         { XM, M }, 0 },
10886   },
10887   {
10888     /* MOD_VEX_0F381A_PREFIX_2 */
10889     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10890   },
10891   {
10892     /* MOD_VEX_0F382A_PREFIX_2 */
10893     { "vmovntdqa",      { XM, Mx }, 0 },
10894   },
10895   {
10896     /* MOD_VEX_0F382C_PREFIX_2 */
10897     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10898   },
10899   {
10900     /* MOD_VEX_0F382D_PREFIX_2 */
10901     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10902   },
10903   {
10904     /* MOD_VEX_0F382E_PREFIX_2 */
10905     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10906   },
10907   {
10908     /* MOD_VEX_0F382F_PREFIX_2 */
10909     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10910   },
10911   {
10912     /* MOD_VEX_0F385A_PREFIX_2 */
10913     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10914   },
10915   {
10916     /* MOD_VEX_0F388C_PREFIX_2 */
10917     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10918   },
10919   {
10920     /* MOD_VEX_0F388E_PREFIX_2 */
10921     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10922   },
10923   {
10924     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10925     { Bad_Opcode },
10926     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10927   },
10928   {
10929     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10930     { Bad_Opcode },
10931     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10932   },
10933   {
10934     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10935     { Bad_Opcode },
10936     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10937   },
10938   {
10939     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10940     { Bad_Opcode },
10941     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10942   },
10943   {
10944     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10945     { Bad_Opcode },
10946     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10947   },
10948   {
10949     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10950     { Bad_Opcode },
10951     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10952   },
10953   {
10954     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10955     { Bad_Opcode },
10956     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10957   },
10958   {
10959     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10960     { Bad_Opcode },
10961     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10962   },
10963
10964 #include "i386-dis-evex-mod.h"
10965 };
10966
10967 static const struct dis386 rm_table[][8] = {
10968   {
10969     /* RM_C6_REG_7 */
10970     { "xabort",         { Skip_MODRM, Ib }, 0 },
10971   },
10972   {
10973     /* RM_C7_REG_7 */
10974     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10975   },
10976   {
10977     /* RM_0F01_REG_0 */
10978     { "enclv",          { Skip_MODRM }, 0 },
10979     { "vmcall",         { Skip_MODRM }, 0 },
10980     { "vmlaunch",       { Skip_MODRM }, 0 },
10981     { "vmresume",       { Skip_MODRM }, 0 },
10982     { "vmxoff",         { Skip_MODRM }, 0 },
10983     { "pconfig",        { Skip_MODRM }, 0 },
10984   },
10985   {
10986     /* RM_0F01_REG_1 */
10987     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10988     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10989     { "clac",           { Skip_MODRM }, 0 },
10990     { "stac",           { Skip_MODRM }, 0 },
10991     { Bad_Opcode },
10992     { Bad_Opcode },
10993     { Bad_Opcode },
10994     { "encls",          { Skip_MODRM }, 0 },
10995   },
10996   {
10997     /* RM_0F01_REG_2 */
10998     { "xgetbv",         { Skip_MODRM }, 0 },
10999     { "xsetbv",         { Skip_MODRM }, 0 },
11000     { Bad_Opcode },
11001     { Bad_Opcode },
11002     { "vmfunc",         { Skip_MODRM }, 0 },
11003     { "xend",           { Skip_MODRM }, 0 },
11004     { "xtest",          { Skip_MODRM }, 0 },
11005     { "enclu",          { Skip_MODRM }, 0 },
11006   },
11007   {
11008     /* RM_0F01_REG_3 */
11009     { "vmrun",          { Skip_MODRM }, 0 },
11010     { "vmmcall",        { Skip_MODRM }, 0 },
11011     { "vmload",         { Skip_MODRM }, 0 },
11012     { "vmsave",         { Skip_MODRM }, 0 },
11013     { "stgi",           { Skip_MODRM }, 0 },
11014     { "clgi",           { Skip_MODRM }, 0 },
11015     { "skinit",         { Skip_MODRM }, 0 },
11016     { "invlpga",        { Skip_MODRM }, 0 },
11017   },
11018   {
11019     /* RM_0F01_REG_5_MOD_3 */
11020     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11021     { Bad_Opcode },
11022     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11023     { Bad_Opcode },
11024     { Bad_Opcode },
11025     { Bad_Opcode },
11026     { "rdpkru",         { Skip_MODRM }, 0 },
11027     { "wrpkru",         { Skip_MODRM }, 0 },
11028   },
11029   {
11030     /* RM_0F01_REG_7_MOD_3 */
11031     { "swapgs",         { Skip_MODRM }, 0  },
11032     { "rdtscp",         { Skip_MODRM }, 0  },
11033     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11034     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11035     { "clzero",         { Skip_MODRM }, 0  },
11036     { "rdpru",          { Skip_MODRM }, 0  },
11037   },
11038   {
11039     /* RM_0F1E_P_1_MOD_3_REG_7 */
11040     { "nopQ",           { Ev }, 0 },
11041     { "nopQ",           { Ev }, 0 },
11042     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11043     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11044     { "nopQ",           { Ev }, 0 },
11045     { "nopQ",           { Ev }, 0 },
11046     { "nopQ",           { Ev }, 0 },
11047     { "nopQ",           { Ev }, 0 },
11048   },
11049   {
11050     /* RM_0FAE_REG_6_MOD_3 */
11051     { "mfence",         { Skip_MODRM }, 0 },
11052   },
11053   {
11054     /* RM_0FAE_REG_7_MOD_3 */
11055     { "sfence",         { Skip_MODRM }, 0 },
11056
11057   },
11058 };
11059
11060 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11061
11062 /* We use the high bit to indicate different name for the same
11063    prefix.  */
11064 #define REP_PREFIX      (0xf3 | 0x100)
11065 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11066 #define XRELEASE_PREFIX (0xf3 | 0x400)
11067 #define BND_PREFIX      (0xf2 | 0x400)
11068 #define NOTRACK_PREFIX  (0x3e | 0x100)
11069
11070 static int
11071 ckprefix (void)
11072 {
11073   int newrex, i, length;
11074   rex = 0;
11075   rex_ignored = 0;
11076   prefixes = 0;
11077   used_prefixes = 0;
11078   rex_used = 0;
11079   last_lock_prefix = -1;
11080   last_repz_prefix = -1;
11081   last_repnz_prefix = -1;
11082   last_data_prefix = -1;
11083   last_addr_prefix = -1;
11084   last_rex_prefix = -1;
11085   last_seg_prefix = -1;
11086   fwait_prefix = -1;
11087   active_seg_prefix = 0;
11088   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11089     all_prefixes[i] = 0;
11090   i = 0;
11091   length = 0;
11092   /* The maximum instruction length is 15bytes.  */
11093   while (length < MAX_CODE_LENGTH - 1)
11094     {
11095       FETCH_DATA (the_info, codep + 1);
11096       newrex = 0;
11097       switch (*codep)
11098         {
11099         /* REX prefixes family.  */
11100         case 0x40:
11101         case 0x41:
11102         case 0x42:
11103         case 0x43:
11104         case 0x44:
11105         case 0x45:
11106         case 0x46:
11107         case 0x47:
11108         case 0x48:
11109         case 0x49:
11110         case 0x4a:
11111         case 0x4b:
11112         case 0x4c:
11113         case 0x4d:
11114         case 0x4e:
11115         case 0x4f:
11116           if (address_mode == mode_64bit)
11117             newrex = *codep;
11118           else
11119             return 1;
11120           last_rex_prefix = i;
11121           break;
11122         case 0xf3:
11123           prefixes |= PREFIX_REPZ;
11124           last_repz_prefix = i;
11125           break;
11126         case 0xf2:
11127           prefixes |= PREFIX_REPNZ;
11128           last_repnz_prefix = i;
11129           break;
11130         case 0xf0:
11131           prefixes |= PREFIX_LOCK;
11132           last_lock_prefix = i;
11133           break;
11134         case 0x2e:
11135           prefixes |= PREFIX_CS;
11136           last_seg_prefix = i;
11137           active_seg_prefix = PREFIX_CS;
11138           break;
11139         case 0x36:
11140           prefixes |= PREFIX_SS;
11141           last_seg_prefix = i;
11142           active_seg_prefix = PREFIX_SS;
11143           break;
11144         case 0x3e:
11145           prefixes |= PREFIX_DS;
11146           last_seg_prefix = i;
11147           active_seg_prefix = PREFIX_DS;
11148           break;
11149         case 0x26:
11150           prefixes |= PREFIX_ES;
11151           last_seg_prefix = i;
11152           active_seg_prefix = PREFIX_ES;
11153           break;
11154         case 0x64:
11155           prefixes |= PREFIX_FS;
11156           last_seg_prefix = i;
11157           active_seg_prefix = PREFIX_FS;
11158           break;
11159         case 0x65:
11160           prefixes |= PREFIX_GS;
11161           last_seg_prefix = i;
11162           active_seg_prefix = PREFIX_GS;
11163           break;
11164         case 0x66:
11165           prefixes |= PREFIX_DATA;
11166           last_data_prefix = i;
11167           break;
11168         case 0x67:
11169           prefixes |= PREFIX_ADDR;
11170           last_addr_prefix = i;
11171           break;
11172         case FWAIT_OPCODE:
11173           /* fwait is really an instruction.  If there are prefixes
11174              before the fwait, they belong to the fwait, *not* to the
11175              following instruction.  */
11176           fwait_prefix = i;
11177           if (prefixes || rex)
11178             {
11179               prefixes |= PREFIX_FWAIT;
11180               codep++;
11181               /* This ensures that the previous REX prefixes are noticed
11182                  as unused prefixes, as in the return case below.  */
11183               rex_used = rex;
11184               return 1;
11185             }
11186           prefixes = PREFIX_FWAIT;
11187           break;
11188         default:
11189           return 1;
11190         }
11191       /* Rex is ignored when followed by another prefix.  */
11192       if (rex)
11193         {
11194           rex_used = rex;
11195           return 1;
11196         }
11197       if (*codep != FWAIT_OPCODE)
11198         all_prefixes[i++] = *codep;
11199       rex = newrex;
11200       codep++;
11201       length++;
11202     }
11203   return 0;
11204 }
11205
11206 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11207    prefix byte.  */
11208
11209 static const char *
11210 prefix_name (int pref, int sizeflag)
11211 {
11212   static const char *rexes [16] =
11213     {
11214       "rex",            /* 0x40 */
11215       "rex.B",          /* 0x41 */
11216       "rex.X",          /* 0x42 */
11217       "rex.XB",         /* 0x43 */
11218       "rex.R",          /* 0x44 */
11219       "rex.RB",         /* 0x45 */
11220       "rex.RX",         /* 0x46 */
11221       "rex.RXB",        /* 0x47 */
11222       "rex.W",          /* 0x48 */
11223       "rex.WB",         /* 0x49 */
11224       "rex.WX",         /* 0x4a */
11225       "rex.WXB",        /* 0x4b */
11226       "rex.WR",         /* 0x4c */
11227       "rex.WRB",        /* 0x4d */
11228       "rex.WRX",        /* 0x4e */
11229       "rex.WRXB",       /* 0x4f */
11230     };
11231
11232   switch (pref)
11233     {
11234     /* REX prefixes family.  */
11235     case 0x40:
11236     case 0x41:
11237     case 0x42:
11238     case 0x43:
11239     case 0x44:
11240     case 0x45:
11241     case 0x46:
11242     case 0x47:
11243     case 0x48:
11244     case 0x49:
11245     case 0x4a:
11246     case 0x4b:
11247     case 0x4c:
11248     case 0x4d:
11249     case 0x4e:
11250     case 0x4f:
11251       return rexes [pref - 0x40];
11252     case 0xf3:
11253       return "repz";
11254     case 0xf2:
11255       return "repnz";
11256     case 0xf0:
11257       return "lock";
11258     case 0x2e:
11259       return "cs";
11260     case 0x36:
11261       return "ss";
11262     case 0x3e:
11263       return "ds";
11264     case 0x26:
11265       return "es";
11266     case 0x64:
11267       return "fs";
11268     case 0x65:
11269       return "gs";
11270     case 0x66:
11271       return (sizeflag & DFLAG) ? "data16" : "data32";
11272     case 0x67:
11273       if (address_mode == mode_64bit)
11274         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11275       else
11276         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11277     case FWAIT_OPCODE:
11278       return "fwait";
11279     case REP_PREFIX:
11280       return "rep";
11281     case XACQUIRE_PREFIX:
11282       return "xacquire";
11283     case XRELEASE_PREFIX:
11284       return "xrelease";
11285     case BND_PREFIX:
11286       return "bnd";
11287     case NOTRACK_PREFIX:
11288       return "notrack";
11289     default:
11290       return NULL;
11291     }
11292 }
11293
11294 static char op_out[MAX_OPERANDS][100];
11295 static int op_ad, op_index[MAX_OPERANDS];
11296 static int two_source_ops;
11297 static bfd_vma op_address[MAX_OPERANDS];
11298 static bfd_vma op_riprel[MAX_OPERANDS];
11299 static bfd_vma start_pc;
11300
11301 /*
11302  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11303  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11304  *   section of the "Virtual 8086 Mode" chapter.)
11305  * 'pc' should be the address of this instruction, it will
11306  *   be used to print the target address if this is a relative jump or call
11307  * The function returns the length of this instruction in bytes.
11308  */
11309
11310 static char intel_syntax;
11311 static char intel_mnemonic = !SYSV386_COMPAT;
11312 static char open_char;
11313 static char close_char;
11314 static char separator_char;
11315 static char scale_char;
11316
11317 enum x86_64_isa
11318 {
11319   amd64 = 0,
11320   intel64
11321 };
11322
11323 static enum x86_64_isa isa64;
11324
11325 /* Here for backwards compatibility.  When gdb stops using
11326    print_insn_i386_att and print_insn_i386_intel these functions can
11327    disappear, and print_insn_i386 be merged into print_insn.  */
11328 int
11329 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11330 {
11331   intel_syntax = 0;
11332
11333   return print_insn (pc, info);
11334 }
11335
11336 int
11337 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11338 {
11339   intel_syntax = 1;
11340
11341   return print_insn (pc, info);
11342 }
11343
11344 int
11345 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11346 {
11347   intel_syntax = -1;
11348
11349   return print_insn (pc, info);
11350 }
11351
11352 void
11353 print_i386_disassembler_options (FILE *stream)
11354 {
11355   fprintf (stream, _("\n\
11356 The following i386/x86-64 specific disassembler options are supported for use\n\
11357 with the -M switch (multiple options should be separated by commas):\n"));
11358
11359   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11360   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11361   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11362   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11363   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11364   fprintf (stream, _("  att-mnemonic\n"
11365                      "              Display instruction in AT&T mnemonic\n"));
11366   fprintf (stream, _("  intel-mnemonic\n"
11367                      "              Display instruction in Intel mnemonic\n"));
11368   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11369   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11370   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11371   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11372   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11373   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11374   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11375   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11376 }
11377
11378 /* Bad opcode.  */
11379 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11380
11381 /* Get a pointer to struct dis386 with a valid name.  */
11382
11383 static const struct dis386 *
11384 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11385 {
11386   int vindex, vex_table_index;
11387
11388   if (dp->name != NULL)
11389     return dp;
11390
11391   switch (dp->op[0].bytemode)
11392     {
11393     case USE_REG_TABLE:
11394       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11395       break;
11396
11397     case USE_MOD_TABLE:
11398       vindex = modrm.mod == 0x3 ? 1 : 0;
11399       dp = &mod_table[dp->op[1].bytemode][vindex];
11400       break;
11401
11402     case USE_RM_TABLE:
11403       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11404       break;
11405
11406     case USE_PREFIX_TABLE:
11407       if (need_vex)
11408         {
11409           /* The prefix in VEX is implicit.  */
11410           switch (vex.prefix)
11411             {
11412             case 0:
11413               vindex = 0;
11414               break;
11415             case REPE_PREFIX_OPCODE:
11416               vindex = 1;
11417               break;
11418             case DATA_PREFIX_OPCODE:
11419               vindex = 2;
11420               break;
11421             case REPNE_PREFIX_OPCODE:
11422               vindex = 3;
11423               break;
11424             default:
11425               abort ();
11426               break;
11427             }
11428         }
11429       else
11430         {
11431           int last_prefix = -1;
11432           int prefix = 0;
11433           vindex = 0;
11434           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11435              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11436              last one wins.  */
11437           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11438             {
11439               if (last_repz_prefix > last_repnz_prefix)
11440                 {
11441                   vindex = 1;
11442                   prefix = PREFIX_REPZ;
11443                   last_prefix = last_repz_prefix;
11444                 }
11445               else
11446                 {
11447                   vindex = 3;
11448                   prefix = PREFIX_REPNZ;
11449                   last_prefix = last_repnz_prefix;
11450                 }
11451
11452               /* Check if prefix should be ignored.  */
11453               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11454                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11455                    & prefix) != 0)
11456                 vindex = 0;
11457             }
11458
11459           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11460             {
11461               vindex = 2;
11462               prefix = PREFIX_DATA;
11463               last_prefix = last_data_prefix;
11464             }
11465
11466           if (vindex != 0)
11467             {
11468               used_prefixes |= prefix;
11469               all_prefixes[last_prefix] = 0;
11470             }
11471         }
11472       dp = &prefix_table[dp->op[1].bytemode][vindex];
11473       break;
11474
11475     case USE_X86_64_TABLE:
11476       vindex = address_mode == mode_64bit ? 1 : 0;
11477       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11478       break;
11479
11480     case USE_3BYTE_TABLE:
11481       FETCH_DATA (info, codep + 2);
11482       vindex = *codep++;
11483       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11484       end_codep = codep;
11485       modrm.mod = (*codep >> 6) & 3;
11486       modrm.reg = (*codep >> 3) & 7;
11487       modrm.rm = *codep & 7;
11488       break;
11489
11490     case USE_VEX_LEN_TABLE:
11491       if (!need_vex)
11492         abort ();
11493
11494       switch (vex.length)
11495         {
11496         case 128:
11497           vindex = 0;
11498           break;
11499         case 256:
11500           vindex = 1;
11501           break;
11502         default:
11503           abort ();
11504           break;
11505         }
11506
11507       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11508       break;
11509
11510     case USE_EVEX_LEN_TABLE:
11511       if (!vex.evex)
11512         abort ();
11513
11514       switch (vex.length)
11515         {
11516         case 128:
11517           vindex = 0;
11518           break;
11519         case 256:
11520           vindex = 1;
11521           break;
11522         case 512:
11523           vindex = 2;
11524           break;
11525         default:
11526           abort ();
11527           break;
11528         }
11529
11530       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11531       break;
11532
11533     case USE_XOP_8F_TABLE:
11534       FETCH_DATA (info, codep + 3);
11535       /* All bits in the REX prefix are ignored.  */
11536       rex_ignored = rex;
11537       rex = ~(*codep >> 5) & 0x7;
11538
11539       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11540       switch ((*codep & 0x1f))
11541         {
11542         default:
11543           dp = &bad_opcode;
11544           return dp;
11545         case 0x8:
11546           vex_table_index = XOP_08;
11547           break;
11548         case 0x9:
11549           vex_table_index = XOP_09;
11550           break;
11551         case 0xa:
11552           vex_table_index = XOP_0A;
11553           break;
11554         }
11555       codep++;
11556       vex.w = *codep & 0x80;
11557       if (vex.w && address_mode == mode_64bit)
11558         rex |= REX_W;
11559
11560       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11561       if (address_mode != mode_64bit)
11562         {
11563           /* In 16/32-bit mode REX_B is silently ignored.  */
11564           rex &= ~REX_B;
11565         }
11566
11567       vex.length = (*codep & 0x4) ? 256 : 128;
11568       switch ((*codep & 0x3))
11569         {
11570         case 0:
11571           break;
11572         case 1:
11573           vex.prefix = DATA_PREFIX_OPCODE;
11574           break;
11575         case 2:
11576           vex.prefix = REPE_PREFIX_OPCODE;
11577           break;
11578         case 3:
11579           vex.prefix = REPNE_PREFIX_OPCODE;
11580           break;
11581         }
11582       need_vex = 1;
11583       need_vex_reg = 1;
11584       codep++;
11585       vindex = *codep++;
11586       dp = &xop_table[vex_table_index][vindex];
11587
11588       end_codep = codep;
11589       FETCH_DATA (info, codep + 1);
11590       modrm.mod = (*codep >> 6) & 3;
11591       modrm.reg = (*codep >> 3) & 7;
11592       modrm.rm = *codep & 7;
11593       break;
11594
11595     case USE_VEX_C4_TABLE:
11596       /* VEX prefix.  */
11597       FETCH_DATA (info, codep + 3);
11598       /* All bits in the REX prefix are ignored.  */
11599       rex_ignored = rex;
11600       rex = ~(*codep >> 5) & 0x7;
11601       switch ((*codep & 0x1f))
11602         {
11603         default:
11604           dp = &bad_opcode;
11605           return dp;
11606         case 0x1:
11607           vex_table_index = VEX_0F;
11608           break;
11609         case 0x2:
11610           vex_table_index = VEX_0F38;
11611           break;
11612         case 0x3:
11613           vex_table_index = VEX_0F3A;
11614           break;
11615         }
11616       codep++;
11617       vex.w = *codep & 0x80;
11618       if (address_mode == mode_64bit)
11619         {
11620           if (vex.w)
11621             rex |= REX_W;
11622         }
11623       else
11624         {
11625           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11626              is ignored, other REX bits are 0 and the highest bit in
11627              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11628           rex = 0;
11629         }
11630       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11631       vex.length = (*codep & 0x4) ? 256 : 128;
11632       switch ((*codep & 0x3))
11633         {
11634         case 0:
11635           break;
11636         case 1:
11637           vex.prefix = DATA_PREFIX_OPCODE;
11638           break;
11639         case 2:
11640           vex.prefix = REPE_PREFIX_OPCODE;
11641           break;
11642         case 3:
11643           vex.prefix = REPNE_PREFIX_OPCODE;
11644           break;
11645         }
11646       need_vex = 1;
11647       need_vex_reg = 1;
11648       codep++;
11649       vindex = *codep++;
11650       dp = &vex_table[vex_table_index][vindex];
11651       end_codep = codep;
11652       /* There is no MODRM byte for VEX0F 77.  */
11653       if (vex_table_index != VEX_0F || vindex != 0x77)
11654         {
11655           FETCH_DATA (info, codep + 1);
11656           modrm.mod = (*codep >> 6) & 3;
11657           modrm.reg = (*codep >> 3) & 7;
11658           modrm.rm = *codep & 7;
11659         }
11660       break;
11661
11662     case USE_VEX_C5_TABLE:
11663       /* VEX prefix.  */
11664       FETCH_DATA (info, codep + 2);
11665       /* All bits in the REX prefix are ignored.  */
11666       rex_ignored = rex;
11667       rex = (*codep & 0x80) ? 0 : REX_R;
11668
11669       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11670          VEX.vvvv is 1.  */
11671       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11672       vex.length = (*codep & 0x4) ? 256 : 128;
11673       switch ((*codep & 0x3))
11674         {
11675         case 0:
11676           break;
11677         case 1:
11678           vex.prefix = DATA_PREFIX_OPCODE;
11679           break;
11680         case 2:
11681           vex.prefix = REPE_PREFIX_OPCODE;
11682           break;
11683         case 3:
11684           vex.prefix = REPNE_PREFIX_OPCODE;
11685           break;
11686         }
11687       need_vex = 1;
11688       need_vex_reg = 1;
11689       codep++;
11690       vindex = *codep++;
11691       dp = &vex_table[dp->op[1].bytemode][vindex];
11692       end_codep = codep;
11693       /* There is no MODRM byte for VEX 77.  */
11694       if (vindex != 0x77)
11695         {
11696           FETCH_DATA (info, codep + 1);
11697           modrm.mod = (*codep >> 6) & 3;
11698           modrm.reg = (*codep >> 3) & 7;
11699           modrm.rm = *codep & 7;
11700         }
11701       break;
11702
11703     case USE_VEX_W_TABLE:
11704       if (!need_vex)
11705         abort ();
11706
11707       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11708       break;
11709
11710     case USE_EVEX_TABLE:
11711       two_source_ops = 0;
11712       /* EVEX prefix.  */
11713       vex.evex = 1;
11714       FETCH_DATA (info, codep + 4);
11715       /* All bits in the REX prefix are ignored.  */
11716       rex_ignored = rex;
11717       /* The first byte after 0x62.  */
11718       rex = ~(*codep >> 5) & 0x7;
11719       vex.r = *codep & 0x10;
11720       switch ((*codep & 0xf))
11721         {
11722         default:
11723           return &bad_opcode;
11724         case 0x1:
11725           vex_table_index = EVEX_0F;
11726           break;
11727         case 0x2:
11728           vex_table_index = EVEX_0F38;
11729           break;
11730         case 0x3:
11731           vex_table_index = EVEX_0F3A;
11732           break;
11733         }
11734
11735       /* The second byte after 0x62.  */
11736       codep++;
11737       vex.w = *codep & 0x80;
11738       if (vex.w && address_mode == mode_64bit)
11739         rex |= REX_W;
11740
11741       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11742
11743       /* The U bit.  */
11744       if (!(*codep & 0x4))
11745         return &bad_opcode;
11746
11747       switch ((*codep & 0x3))
11748         {
11749         case 0:
11750           break;
11751         case 1:
11752           vex.prefix = DATA_PREFIX_OPCODE;
11753           break;
11754         case 2:
11755           vex.prefix = REPE_PREFIX_OPCODE;
11756           break;
11757         case 3:
11758           vex.prefix = REPNE_PREFIX_OPCODE;
11759           break;
11760         }
11761
11762       /* The third byte after 0x62.  */
11763       codep++;
11764
11765       /* Remember the static rounding bits.  */
11766       vex.ll = (*codep >> 5) & 3;
11767       vex.b = (*codep & 0x10) != 0;
11768
11769       vex.v = *codep & 0x8;
11770       vex.mask_register_specifier = *codep & 0x7;
11771       vex.zeroing = *codep & 0x80;
11772
11773       if (address_mode != mode_64bit)
11774         {
11775           /* In 16/32-bit mode silently ignore following bits.  */
11776           rex &= ~REX_B;
11777           vex.r = 1;
11778           vex.v = 1;
11779         }
11780
11781       need_vex = 1;
11782       need_vex_reg = 1;
11783       codep++;
11784       vindex = *codep++;
11785       dp = &evex_table[vex_table_index][vindex];
11786       end_codep = codep;
11787       FETCH_DATA (info, codep + 1);
11788       modrm.mod = (*codep >> 6) & 3;
11789       modrm.reg = (*codep >> 3) & 7;
11790       modrm.rm = *codep & 7;
11791
11792       /* Set vector length.  */
11793       if (modrm.mod == 3 && vex.b)
11794         vex.length = 512;
11795       else
11796         {
11797           switch (vex.ll)
11798             {
11799             case 0x0:
11800               vex.length = 128;
11801               break;
11802             case 0x1:
11803               vex.length = 256;
11804               break;
11805             case 0x2:
11806               vex.length = 512;
11807               break;
11808             default:
11809               return &bad_opcode;
11810             }
11811         }
11812       break;
11813
11814     case 0:
11815       dp = &bad_opcode;
11816       break;
11817
11818     default:
11819       abort ();
11820     }
11821
11822   if (dp->name != NULL)
11823     return dp;
11824   else
11825     return get_valid_dis386 (dp, info);
11826 }
11827
11828 static void
11829 get_sib (disassemble_info *info, int sizeflag)
11830 {
11831   /* If modrm.mod == 3, operand must be register.  */
11832   if (need_modrm
11833       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11834       && modrm.mod != 3
11835       && modrm.rm == 4)
11836     {
11837       FETCH_DATA (info, codep + 2);
11838       sib.index = (codep [1] >> 3) & 7;
11839       sib.scale = (codep [1] >> 6) & 3;
11840       sib.base = codep [1] & 7;
11841     }
11842 }
11843
11844 static int
11845 print_insn (bfd_vma pc, disassemble_info *info)
11846 {
11847   const struct dis386 *dp;
11848   int i;
11849   char *op_txt[MAX_OPERANDS];
11850   int needcomma;
11851   int sizeflag, orig_sizeflag;
11852   const char *p;
11853   struct dis_private priv;
11854   int prefix_length;
11855
11856   priv.orig_sizeflag = AFLAG | DFLAG;
11857   if ((info->mach & bfd_mach_i386_i386) != 0)
11858     address_mode = mode_32bit;
11859   else if (info->mach == bfd_mach_i386_i8086)
11860     {
11861       address_mode = mode_16bit;
11862       priv.orig_sizeflag = 0;
11863     }
11864   else
11865     address_mode = mode_64bit;
11866
11867   if (intel_syntax == (char) -1)
11868     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11869
11870   for (p = info->disassembler_options; p != NULL; )
11871     {
11872       if (CONST_STRNEQ (p, "amd64"))
11873         isa64 = amd64;
11874       else if (CONST_STRNEQ (p, "intel64"))
11875         isa64 = intel64;
11876       else if (CONST_STRNEQ (p, "x86-64"))
11877         {
11878           address_mode = mode_64bit;
11879           priv.orig_sizeflag = AFLAG | DFLAG;
11880         }
11881       else if (CONST_STRNEQ (p, "i386"))
11882         {
11883           address_mode = mode_32bit;
11884           priv.orig_sizeflag = AFLAG | DFLAG;
11885         }
11886       else if (CONST_STRNEQ (p, "i8086"))
11887         {
11888           address_mode = mode_16bit;
11889           priv.orig_sizeflag = 0;
11890         }
11891       else if (CONST_STRNEQ (p, "intel"))
11892         {
11893           intel_syntax = 1;
11894           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11895             intel_mnemonic = 1;
11896         }
11897       else if (CONST_STRNEQ (p, "att"))
11898         {
11899           intel_syntax = 0;
11900           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11901             intel_mnemonic = 0;
11902         }
11903       else if (CONST_STRNEQ (p, "addr"))
11904         {
11905           if (address_mode == mode_64bit)
11906             {
11907               if (p[4] == '3' && p[5] == '2')
11908                 priv.orig_sizeflag &= ~AFLAG;
11909               else if (p[4] == '6' && p[5] == '4')
11910                 priv.orig_sizeflag |= AFLAG;
11911             }
11912           else
11913             {
11914               if (p[4] == '1' && p[5] == '6')
11915                 priv.orig_sizeflag &= ~AFLAG;
11916               else if (p[4] == '3' && p[5] == '2')
11917                 priv.orig_sizeflag |= AFLAG;
11918             }
11919         }
11920       else if (CONST_STRNEQ (p, "data"))
11921         {
11922           if (p[4] == '1' && p[5] == '6')
11923             priv.orig_sizeflag &= ~DFLAG;
11924           else if (p[4] == '3' && p[5] == '2')
11925             priv.orig_sizeflag |= DFLAG;
11926         }
11927       else if (CONST_STRNEQ (p, "suffix"))
11928         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11929
11930       p = strchr (p, ',');
11931       if (p != NULL)
11932         p++;
11933     }
11934
11935   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11936     {
11937       (*info->fprintf_func) (info->stream,
11938                              _("64-bit address is disabled"));
11939       return -1;
11940     }
11941
11942   if (intel_syntax)
11943     {
11944       names64 = intel_names64;
11945       names32 = intel_names32;
11946       names16 = intel_names16;
11947       names8 = intel_names8;
11948       names8rex = intel_names8rex;
11949       names_seg = intel_names_seg;
11950       names_mm = intel_names_mm;
11951       names_bnd = intel_names_bnd;
11952       names_xmm = intel_names_xmm;
11953       names_ymm = intel_names_ymm;
11954       names_zmm = intel_names_zmm;
11955       index64 = intel_index64;
11956       index32 = intel_index32;
11957       names_mask = intel_names_mask;
11958       index16 = intel_index16;
11959       open_char = '[';
11960       close_char = ']';
11961       separator_char = '+';
11962       scale_char = '*';
11963     }
11964   else
11965     {
11966       names64 = att_names64;
11967       names32 = att_names32;
11968       names16 = att_names16;
11969       names8 = att_names8;
11970       names8rex = att_names8rex;
11971       names_seg = att_names_seg;
11972       names_mm = att_names_mm;
11973       names_bnd = att_names_bnd;
11974       names_xmm = att_names_xmm;
11975       names_ymm = att_names_ymm;
11976       names_zmm = att_names_zmm;
11977       index64 = att_index64;
11978       index32 = att_index32;
11979       names_mask = att_names_mask;
11980       index16 = att_index16;
11981       open_char = '(';
11982       close_char =  ')';
11983       separator_char = ',';
11984       scale_char = ',';
11985     }
11986
11987   /* The output looks better if we put 7 bytes on a line, since that
11988      puts most long word instructions on a single line.  Use 8 bytes
11989      for Intel L1OM.  */
11990   if ((info->mach & bfd_mach_l1om) != 0)
11991     info->bytes_per_line = 8;
11992   else
11993     info->bytes_per_line = 7;
11994
11995   info->private_data = &priv;
11996   priv.max_fetched = priv.the_buffer;
11997   priv.insn_start = pc;
11998
11999   obuf[0] = 0;
12000   for (i = 0; i < MAX_OPERANDS; ++i)
12001     {
12002       op_out[i][0] = 0;
12003       op_index[i] = -1;
12004     }
12005
12006   the_info = info;
12007   start_pc = pc;
12008   start_codep = priv.the_buffer;
12009   codep = priv.the_buffer;
12010
12011   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12012     {
12013       const char *name;
12014
12015       /* Getting here means we tried for data but didn't get it.  That
12016          means we have an incomplete instruction of some sort.  Just
12017          print the first byte as a prefix or a .byte pseudo-op.  */
12018       if (codep > priv.the_buffer)
12019         {
12020           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12021           if (name != NULL)
12022             (*info->fprintf_func) (info->stream, "%s", name);
12023           else
12024             {
12025               /* Just print the first byte as a .byte instruction.  */
12026               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12027                                      (unsigned int) priv.the_buffer[0]);
12028             }
12029
12030           return 1;
12031         }
12032
12033       return -1;
12034     }
12035
12036   obufp = obuf;
12037   sizeflag = priv.orig_sizeflag;
12038
12039   if (!ckprefix () || rex_used)
12040     {
12041       /* Too many prefixes or unused REX prefixes.  */
12042       for (i = 0;
12043            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12044            i++)
12045         (*info->fprintf_func) (info->stream, "%s%s",
12046                                i == 0 ? "" : " ",
12047                                prefix_name (all_prefixes[i], sizeflag));
12048       return i;
12049     }
12050
12051   insn_codep = codep;
12052
12053   FETCH_DATA (info, codep + 1);
12054   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12055
12056   if (((prefixes & PREFIX_FWAIT)
12057        && ((*codep < 0xd8) || (*codep > 0xdf))))
12058     {
12059       /* Handle prefixes before fwait.  */
12060       for (i = 0; i < fwait_prefix && all_prefixes[i];
12061            i++)
12062         (*info->fprintf_func) (info->stream, "%s ",
12063                                prefix_name (all_prefixes[i], sizeflag));
12064       (*info->fprintf_func) (info->stream, "fwait");
12065       return i + 1;
12066     }
12067
12068   if (*codep == 0x0f)
12069     {
12070       unsigned char threebyte;
12071
12072       codep++;
12073       FETCH_DATA (info, codep + 1);
12074       threebyte = *codep;
12075       dp = &dis386_twobyte[threebyte];
12076       need_modrm = twobyte_has_modrm[*codep];
12077       codep++;
12078     }
12079   else
12080     {
12081       dp = &dis386[*codep];
12082       need_modrm = onebyte_has_modrm[*codep];
12083       codep++;
12084     }
12085
12086   /* Save sizeflag for printing the extra prefixes later before updating
12087      it for mnemonic and operand processing.  The prefix names depend
12088      only on the address mode.  */
12089   orig_sizeflag = sizeflag;
12090   if (prefixes & PREFIX_ADDR)
12091     sizeflag ^= AFLAG;
12092   if ((prefixes & PREFIX_DATA))
12093     sizeflag ^= DFLAG;
12094
12095   end_codep = codep;
12096   if (need_modrm)
12097     {
12098       FETCH_DATA (info, codep + 1);
12099       modrm.mod = (*codep >> 6) & 3;
12100       modrm.reg = (*codep >> 3) & 7;
12101       modrm.rm = *codep & 7;
12102     }
12103
12104   need_vex = 0;
12105   need_vex_reg = 0;
12106   vex_w_done = 0;
12107   memset (&vex, 0, sizeof (vex));
12108
12109   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12110     {
12111       get_sib (info, sizeflag);
12112       dofloat (sizeflag);
12113     }
12114   else
12115     {
12116       dp = get_valid_dis386 (dp, info);
12117       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12118         {
12119           get_sib (info, sizeflag);
12120           for (i = 0; i < MAX_OPERANDS; ++i)
12121             {
12122               obufp = op_out[i];
12123               op_ad = MAX_OPERANDS - 1 - i;
12124               if (dp->op[i].rtn)
12125                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12126               /* For EVEX instruction after the last operand masking
12127                  should be printed.  */
12128               if (i == 0 && vex.evex)
12129                 {
12130                   /* Don't print {%k0}.  */
12131                   if (vex.mask_register_specifier)
12132                     {
12133                       oappend ("{");
12134                       oappend (names_mask[vex.mask_register_specifier]);
12135                       oappend ("}");
12136                     }
12137                   if (vex.zeroing)
12138                     oappend ("{z}");
12139                 }
12140             }
12141         }
12142     }
12143
12144   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12145      are all 0s in inverted form.  */
12146   if (need_vex && vex.register_specifier != 0)
12147     {
12148       (*info->fprintf_func) (info->stream, "(bad)");
12149       return end_codep - priv.the_buffer;
12150     }
12151
12152   /* Check if the REX prefix is used.  */
12153   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12154     all_prefixes[last_rex_prefix] = 0;
12155
12156   /* Check if the SEG prefix is used.  */
12157   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12158                    | PREFIX_FS | PREFIX_GS)) != 0
12159       && (used_prefixes & active_seg_prefix) != 0)
12160     all_prefixes[last_seg_prefix] = 0;
12161
12162   /* Check if the ADDR prefix is used.  */
12163   if ((prefixes & PREFIX_ADDR) != 0
12164       && (used_prefixes & PREFIX_ADDR) != 0)
12165     all_prefixes[last_addr_prefix] = 0;
12166
12167   /* Check if the DATA prefix is used.  */
12168   if ((prefixes & PREFIX_DATA) != 0
12169       && (used_prefixes & PREFIX_DATA) != 0)
12170     all_prefixes[last_data_prefix] = 0;
12171
12172   /* Print the extra prefixes.  */
12173   prefix_length = 0;
12174   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12175     if (all_prefixes[i])
12176       {
12177         const char *name;
12178         name = prefix_name (all_prefixes[i], orig_sizeflag);
12179         if (name == NULL)
12180           abort ();
12181         prefix_length += strlen (name) + 1;
12182         (*info->fprintf_func) (info->stream, "%s ", name);
12183       }
12184
12185   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12186      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12187      used by putop and MMX/SSE operand and may be overriden by the
12188      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12189      separately.  */
12190   if (dp->prefix_requirement == PREFIX_OPCODE
12191       && dp != &bad_opcode
12192       && (((prefixes
12193             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12194            && (used_prefixes
12195                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12196           || ((((prefixes
12197                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12198                 == PREFIX_DATA)
12199                && (used_prefixes & PREFIX_DATA) == 0))))
12200     {
12201       (*info->fprintf_func) (info->stream, "(bad)");
12202       return end_codep - priv.the_buffer;
12203     }
12204
12205   /* Check maximum code length.  */
12206   if ((codep - start_codep) > MAX_CODE_LENGTH)
12207     {
12208       (*info->fprintf_func) (info->stream, "(bad)");
12209       return MAX_CODE_LENGTH;
12210     }
12211
12212   obufp = mnemonicendp;
12213   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12214     oappend (" ");
12215   oappend (" ");
12216   (*info->fprintf_func) (info->stream, "%s", obuf);
12217
12218   /* The enter and bound instructions are printed with operands in the same
12219      order as the intel book; everything else is printed in reverse order.  */
12220   if (intel_syntax || two_source_ops)
12221     {
12222       bfd_vma riprel;
12223
12224       for (i = 0; i < MAX_OPERANDS; ++i)
12225         op_txt[i] = op_out[i];
12226
12227       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12228           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12229         {
12230           op_txt[2] = op_out[3];
12231           op_txt[3] = op_out[2];
12232         }
12233
12234       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12235         {
12236           op_ad = op_index[i];
12237           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12238           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12239           riprel = op_riprel[i];
12240           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12241           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12242         }
12243     }
12244   else
12245     {
12246       for (i = 0; i < MAX_OPERANDS; ++i)
12247         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12248     }
12249
12250   needcomma = 0;
12251   for (i = 0; i < MAX_OPERANDS; ++i)
12252     if (*op_txt[i])
12253       {
12254         if (needcomma)
12255           (*info->fprintf_func) (info->stream, ",");
12256         if (op_index[i] != -1 && !op_riprel[i])
12257           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12258         else
12259           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12260         needcomma = 1;
12261       }
12262
12263   for (i = 0; i < MAX_OPERANDS; i++)
12264     if (op_index[i] != -1 && op_riprel[i])
12265       {
12266         (*info->fprintf_func) (info->stream, "        # ");
12267         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12268                                                 + op_address[op_index[i]]), info);
12269         break;
12270       }
12271   return codep - priv.the_buffer;
12272 }
12273
12274 static const char *float_mem[] = {
12275   /* d8 */
12276   "fadd{s|}",
12277   "fmul{s|}",
12278   "fcom{s|}",
12279   "fcomp{s|}",
12280   "fsub{s|}",
12281   "fsubr{s|}",
12282   "fdiv{s|}",
12283   "fdivr{s|}",
12284   /* d9 */
12285   "fld{s|}",
12286   "(bad)",
12287   "fst{s|}",
12288   "fstp{s|}",
12289   "fldenvIC",
12290   "fldcw",
12291   "fNstenvIC",
12292   "fNstcw",
12293   /* da */
12294   "fiadd{l|}",
12295   "fimul{l|}",
12296   "ficom{l|}",
12297   "ficomp{l|}",
12298   "fisub{l|}",
12299   "fisubr{l|}",
12300   "fidiv{l|}",
12301   "fidivr{l|}",
12302   /* db */
12303   "fild{l|}",
12304   "fisttp{l|}",
12305   "fist{l|}",
12306   "fistp{l|}",
12307   "(bad)",
12308   "fld{t||t|}",
12309   "(bad)",
12310   "fstp{t||t|}",
12311   /* dc */
12312   "fadd{l|}",
12313   "fmul{l|}",
12314   "fcom{l|}",
12315   "fcomp{l|}",
12316   "fsub{l|}",
12317   "fsubr{l|}",
12318   "fdiv{l|}",
12319   "fdivr{l|}",
12320   /* dd */
12321   "fld{l|}",
12322   "fisttp{ll|}",
12323   "fst{l||}",
12324   "fstp{l|}",
12325   "frstorIC",
12326   "(bad)",
12327   "fNsaveIC",
12328   "fNstsw",
12329   /* de */
12330   "fiadd{s|}",
12331   "fimul{s|}",
12332   "ficom{s|}",
12333   "ficomp{s|}",
12334   "fisub{s|}",
12335   "fisubr{s|}",
12336   "fidiv{s|}",
12337   "fidivr{s|}",
12338   /* df */
12339   "fild{s|}",
12340   "fisttp{s|}",
12341   "fist{s|}",
12342   "fistp{s|}",
12343   "fbld",
12344   "fild{ll|}",
12345   "fbstp",
12346   "fistp{ll|}",
12347 };
12348
12349 static const unsigned char float_mem_mode[] = {
12350   /* d8 */
12351   d_mode,
12352   d_mode,
12353   d_mode,
12354   d_mode,
12355   d_mode,
12356   d_mode,
12357   d_mode,
12358   d_mode,
12359   /* d9 */
12360   d_mode,
12361   0,
12362   d_mode,
12363   d_mode,
12364   0,
12365   w_mode,
12366   0,
12367   w_mode,
12368   /* da */
12369   d_mode,
12370   d_mode,
12371   d_mode,
12372   d_mode,
12373   d_mode,
12374   d_mode,
12375   d_mode,
12376   d_mode,
12377   /* db */
12378   d_mode,
12379   d_mode,
12380   d_mode,
12381   d_mode,
12382   0,
12383   t_mode,
12384   0,
12385   t_mode,
12386   /* dc */
12387   q_mode,
12388   q_mode,
12389   q_mode,
12390   q_mode,
12391   q_mode,
12392   q_mode,
12393   q_mode,
12394   q_mode,
12395   /* dd */
12396   q_mode,
12397   q_mode,
12398   q_mode,
12399   q_mode,
12400   0,
12401   0,
12402   0,
12403   w_mode,
12404   /* de */
12405   w_mode,
12406   w_mode,
12407   w_mode,
12408   w_mode,
12409   w_mode,
12410   w_mode,
12411   w_mode,
12412   w_mode,
12413   /* df */
12414   w_mode,
12415   w_mode,
12416   w_mode,
12417   w_mode,
12418   t_mode,
12419   q_mode,
12420   t_mode,
12421   q_mode
12422 };
12423
12424 #define ST { OP_ST, 0 }
12425 #define STi { OP_STi, 0 }
12426
12427 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12428 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12429 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12430 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12431 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12432 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12433 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12434 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12435 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12436
12437 static const struct dis386 float_reg[][8] = {
12438   /* d8 */
12439   {
12440     { "fadd",   { ST, STi }, 0 },
12441     { "fmul",   { ST, STi }, 0 },
12442     { "fcom",   { STi }, 0 },
12443     { "fcomp",  { STi }, 0 },
12444     { "fsub",   { ST, STi }, 0 },
12445     { "fsubr",  { ST, STi }, 0 },
12446     { "fdiv",   { ST, STi }, 0 },
12447     { "fdivr",  { ST, STi }, 0 },
12448   },
12449   /* d9 */
12450   {
12451     { "fld",    { STi }, 0 },
12452     { "fxch",   { STi }, 0 },
12453     { FGRPd9_2 },
12454     { Bad_Opcode },
12455     { FGRPd9_4 },
12456     { FGRPd9_5 },
12457     { FGRPd9_6 },
12458     { FGRPd9_7 },
12459   },
12460   /* da */
12461   {
12462     { "fcmovb", { ST, STi }, 0 },
12463     { "fcmove", { ST, STi }, 0 },
12464     { "fcmovbe",{ ST, STi }, 0 },
12465     { "fcmovu", { ST, STi }, 0 },
12466     { Bad_Opcode },
12467     { FGRPda_5 },
12468     { Bad_Opcode },
12469     { Bad_Opcode },
12470   },
12471   /* db */
12472   {
12473     { "fcmovnb",{ ST, STi }, 0 },
12474     { "fcmovne",{ ST, STi }, 0 },
12475     { "fcmovnbe",{ ST, STi }, 0 },
12476     { "fcmovnu",{ ST, STi }, 0 },
12477     { FGRPdb_4 },
12478     { "fucomi", { ST, STi }, 0 },
12479     { "fcomi",  { ST, STi }, 0 },
12480     { Bad_Opcode },
12481   },
12482   /* dc */
12483   {
12484     { "fadd",   { STi, ST }, 0 },
12485     { "fmul",   { STi, ST }, 0 },
12486     { Bad_Opcode },
12487     { Bad_Opcode },
12488     { "fsub{!M|r}",     { STi, ST }, 0 },
12489     { "fsub{M|}",       { STi, ST }, 0 },
12490     { "fdiv{!M|r}",     { STi, ST }, 0 },
12491     { "fdiv{M|}",       { STi, ST }, 0 },
12492   },
12493   /* dd */
12494   {
12495     { "ffree",  { STi }, 0 },
12496     { Bad_Opcode },
12497     { "fst",    { STi }, 0 },
12498     { "fstp",   { STi }, 0 },
12499     { "fucom",  { STi }, 0 },
12500     { "fucomp", { STi }, 0 },
12501     { Bad_Opcode },
12502     { Bad_Opcode },
12503   },
12504   /* de */
12505   {
12506     { "faddp",  { STi, ST }, 0 },
12507     { "fmulp",  { STi, ST }, 0 },
12508     { Bad_Opcode },
12509     { FGRPde_3 },
12510     { "fsub{!M|r}p",    { STi, ST }, 0 },
12511     { "fsub{M|}p",      { STi, ST }, 0 },
12512     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12513     { "fdiv{M|}p",      { STi, ST }, 0 },
12514   },
12515   /* df */
12516   {
12517     { "ffreep", { STi }, 0 },
12518     { Bad_Opcode },
12519     { Bad_Opcode },
12520     { Bad_Opcode },
12521     { FGRPdf_4 },
12522     { "fucomip", { ST, STi }, 0 },
12523     { "fcomip", { ST, STi }, 0 },
12524     { Bad_Opcode },
12525   },
12526 };
12527
12528 static char *fgrps[][8] = {
12529   /* Bad opcode 0 */
12530   {
12531     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12532   },
12533
12534   /* d9_2  1 */
12535   {
12536     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12537   },
12538
12539   /* d9_4  2 */
12540   {
12541     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12542   },
12543
12544   /* d9_5  3 */
12545   {
12546     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12547   },
12548
12549   /* d9_6  4 */
12550   {
12551     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12552   },
12553
12554   /* d9_7  5 */
12555   {
12556     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12557   },
12558
12559   /* da_5  6 */
12560   {
12561     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12562   },
12563
12564   /* db_4  7 */
12565   {
12566     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12567     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12568   },
12569
12570   /* de_3  8 */
12571   {
12572     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12573   },
12574
12575   /* df_4  9 */
12576   {
12577     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12578   },
12579 };
12580
12581 static void
12582 swap_operand (void)
12583 {
12584   mnemonicendp[0] = '.';
12585   mnemonicendp[1] = 's';
12586   mnemonicendp += 2;
12587 }
12588
12589 static void
12590 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12591                int sizeflag ATTRIBUTE_UNUSED)
12592 {
12593   /* Skip mod/rm byte.  */
12594   MODRM_CHECK;
12595   codep++;
12596 }
12597
12598 static void
12599 dofloat (int sizeflag)
12600 {
12601   const struct dis386 *dp;
12602   unsigned char floatop;
12603
12604   floatop = codep[-1];
12605
12606   if (modrm.mod != 3)
12607     {
12608       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12609
12610       putop (float_mem[fp_indx], sizeflag);
12611       obufp = op_out[0];
12612       op_ad = 2;
12613       OP_E (float_mem_mode[fp_indx], sizeflag);
12614       return;
12615     }
12616   /* Skip mod/rm byte.  */
12617   MODRM_CHECK;
12618   codep++;
12619
12620   dp = &float_reg[floatop - 0xd8][modrm.reg];
12621   if (dp->name == NULL)
12622     {
12623       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12624
12625       /* Instruction fnstsw is only one with strange arg.  */
12626       if (floatop == 0xdf && codep[-1] == 0xe0)
12627         strcpy (op_out[0], names16[0]);
12628     }
12629   else
12630     {
12631       putop (dp->name, sizeflag);
12632
12633       obufp = op_out[0];
12634       op_ad = 2;
12635       if (dp->op[0].rtn)
12636         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12637
12638       obufp = op_out[1];
12639       op_ad = 1;
12640       if (dp->op[1].rtn)
12641         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12642     }
12643 }
12644
12645 /* Like oappend (below), but S is a string starting with '%'.
12646    In Intel syntax, the '%' is elided.  */
12647 static void
12648 oappend_maybe_intel (const char *s)
12649 {
12650   oappend (s + intel_syntax);
12651 }
12652
12653 static void
12654 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12655 {
12656   oappend_maybe_intel ("%st");
12657 }
12658
12659 static void
12660 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12661 {
12662   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12663   oappend_maybe_intel (scratchbuf);
12664 }
12665
12666 /* Capital letters in template are macros.  */
12667 static int
12668 putop (const char *in_template, int sizeflag)
12669 {
12670   const char *p;
12671   int alt = 0;
12672   int cond = 1;
12673   unsigned int l = 0, len = 1;
12674   char last[4];
12675
12676 #define SAVE_LAST(c)                    \
12677   if (l < len && l < sizeof (last))     \
12678     last[l++] = c;                      \
12679   else                                  \
12680     abort ();
12681
12682   for (p = in_template; *p; p++)
12683     {
12684       switch (*p)
12685         {
12686         default:
12687           *obufp++ = *p;
12688           break;
12689         case '%':
12690           len++;
12691           break;
12692         case '!':
12693           cond = 0;
12694           break;
12695         case '{':
12696           if (intel_syntax)
12697             {
12698               while (*++p != '|')
12699                 if (*p == '}' || *p == '\0')
12700                   abort ();
12701             }
12702           /* Fall through.  */
12703         case 'I':
12704           alt = 1;
12705           continue;
12706         case '|':
12707           while (*++p != '}')
12708             {
12709               if (*p == '\0')
12710                 abort ();
12711             }
12712           break;
12713         case '}':
12714           break;
12715         case 'A':
12716           if (intel_syntax)
12717             break;
12718           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12719             *obufp++ = 'b';
12720           break;
12721         case 'B':
12722           if (l == 0 && len == 1)
12723             {
12724 case_B:
12725               if (intel_syntax)
12726                 break;
12727               if (sizeflag & SUFFIX_ALWAYS)
12728                 *obufp++ = 'b';
12729             }
12730           else
12731             {
12732               if (l != 1
12733                   || len != 2
12734                   || last[0] != 'L')
12735                 {
12736                   SAVE_LAST (*p);
12737                   break;
12738                 }
12739
12740               if (address_mode == mode_64bit
12741                   && !(prefixes & PREFIX_ADDR))
12742                 {
12743                   *obufp++ = 'a';
12744                   *obufp++ = 'b';
12745                   *obufp++ = 's';
12746                 }
12747
12748               goto case_B;
12749             }
12750           break;
12751         case 'C':
12752           if (intel_syntax && !alt)
12753             break;
12754           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12755             {
12756               if (sizeflag & DFLAG)
12757                 *obufp++ = intel_syntax ? 'd' : 'l';
12758               else
12759                 *obufp++ = intel_syntax ? 'w' : 's';
12760               used_prefixes |= (prefixes & PREFIX_DATA);
12761             }
12762           break;
12763         case 'D':
12764           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12765             break;
12766           USED_REX (REX_W);
12767           if (modrm.mod == 3)
12768             {
12769               if (rex & REX_W)
12770                 *obufp++ = 'q';
12771               else
12772                 {
12773                   if (sizeflag & DFLAG)
12774                     *obufp++ = intel_syntax ? 'd' : 'l';
12775                   else
12776                     *obufp++ = 'w';
12777                   used_prefixes |= (prefixes & PREFIX_DATA);
12778                 }
12779             }
12780           else
12781             *obufp++ = 'w';
12782           break;
12783         case 'E':               /* For jcxz/jecxz */
12784           if (address_mode == mode_64bit)
12785             {
12786               if (sizeflag & AFLAG)
12787                 *obufp++ = 'r';
12788               else
12789                 *obufp++ = 'e';
12790             }
12791           else
12792             if (sizeflag & AFLAG)
12793               *obufp++ = 'e';
12794           used_prefixes |= (prefixes & PREFIX_ADDR);
12795           break;
12796         case 'F':
12797           if (intel_syntax)
12798             break;
12799           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12800             {
12801               if (sizeflag & AFLAG)
12802                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12803               else
12804                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12805               used_prefixes |= (prefixes & PREFIX_ADDR);
12806             }
12807           break;
12808         case 'G':
12809           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12810             break;
12811           if ((rex & REX_W) || (sizeflag & DFLAG))
12812             *obufp++ = 'l';
12813           else
12814             *obufp++ = 'w';
12815           if (!(rex & REX_W))
12816             used_prefixes |= (prefixes & PREFIX_DATA);
12817           break;
12818         case 'H':
12819           if (intel_syntax)
12820             break;
12821           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12822               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12823             {
12824               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12825               *obufp++ = ',';
12826               *obufp++ = 'p';
12827               if (prefixes & PREFIX_DS)
12828                 *obufp++ = 't';
12829               else
12830                 *obufp++ = 'n';
12831             }
12832           break;
12833         case 'J':
12834           if (intel_syntax)
12835             break;
12836           *obufp++ = 'l';
12837           break;
12838         case 'K':
12839           USED_REX (REX_W);
12840           if (rex & REX_W)
12841             *obufp++ = 'q';
12842           else
12843             *obufp++ = 'd';
12844           break;
12845         case 'Z':
12846           if (l != 0 || len != 1)
12847             {
12848               if (l != 1 || len != 2 || last[0] != 'X')
12849                 {
12850                   SAVE_LAST (*p);
12851                   break;
12852                 }
12853               if (!need_vex || !vex.evex)
12854                 abort ();
12855               if (intel_syntax
12856                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12857                 break;
12858               switch (vex.length)
12859                 {
12860                 case 128:
12861                   *obufp++ = 'x';
12862                   break;
12863                 case 256:
12864                   *obufp++ = 'y';
12865                   break;
12866                 case 512:
12867                   *obufp++ = 'z';
12868                   break;
12869                 default:
12870                   abort ();
12871                 }
12872               break;
12873             }
12874           if (intel_syntax)
12875             break;
12876           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12877             {
12878               *obufp++ = 'q';
12879               break;
12880             }
12881           /* Fall through.  */
12882           goto case_L;
12883         case 'L':
12884           if (l != 0 || len != 1)
12885             {
12886               SAVE_LAST (*p);
12887               break;
12888             }
12889 case_L:
12890           if (intel_syntax)
12891             break;
12892           if (sizeflag & SUFFIX_ALWAYS)
12893             *obufp++ = 'l';
12894           break;
12895         case 'M':
12896           if (intel_mnemonic != cond)
12897             *obufp++ = 'r';
12898           break;
12899         case 'N':
12900           if ((prefixes & PREFIX_FWAIT) == 0)
12901             *obufp++ = 'n';
12902           else
12903             used_prefixes |= PREFIX_FWAIT;
12904           break;
12905         case 'O':
12906           USED_REX (REX_W);
12907           if (rex & REX_W)
12908             *obufp++ = 'o';
12909           else if (intel_syntax && (sizeflag & DFLAG))
12910             *obufp++ = 'q';
12911           else
12912             *obufp++ = 'd';
12913           if (!(rex & REX_W))
12914             used_prefixes |= (prefixes & PREFIX_DATA);
12915           break;
12916         case '&':
12917           if (!intel_syntax
12918               && address_mode == mode_64bit
12919               && isa64 == intel64)
12920             {
12921               *obufp++ = 'q';
12922               break;
12923             }
12924           /* Fall through.  */
12925         case 'T':
12926           if (!intel_syntax
12927               && address_mode == mode_64bit
12928               && ((sizeflag & DFLAG) || (rex & REX_W)))
12929             {
12930               *obufp++ = 'q';
12931               break;
12932             }
12933           /* Fall through.  */
12934           goto case_P;
12935         case 'P':
12936           if (l == 0 && len == 1)
12937             {
12938 case_P:
12939               if (intel_syntax)
12940                 {
12941                   if ((rex & REX_W) == 0
12942                       && (prefixes & PREFIX_DATA))
12943                     {
12944                       if ((sizeflag & DFLAG) == 0)
12945                         *obufp++ = 'w';
12946                       used_prefixes |= (prefixes & PREFIX_DATA);
12947                     }
12948                   break;
12949                 }
12950               if ((prefixes & PREFIX_DATA)
12951                   || (rex & REX_W)
12952                   || (sizeflag & SUFFIX_ALWAYS))
12953                 {
12954                   USED_REX (REX_W);
12955                   if (rex & REX_W)
12956                     *obufp++ = 'q';
12957                   else
12958                     {
12959                       if (sizeflag & DFLAG)
12960                         *obufp++ = 'l';
12961                       else
12962                         *obufp++ = 'w';
12963                       used_prefixes |= (prefixes & PREFIX_DATA);
12964                     }
12965                 }
12966             }
12967           else
12968             {
12969               if (l != 1 || len != 2 || last[0] != 'L')
12970                 {
12971                   SAVE_LAST (*p);
12972                   break;
12973                 }
12974
12975               if ((prefixes & PREFIX_DATA)
12976                   || (rex & REX_W)
12977                   || (sizeflag & SUFFIX_ALWAYS))
12978                 {
12979                   USED_REX (REX_W);
12980                   if (rex & REX_W)
12981                     *obufp++ = 'q';
12982                   else
12983                     {
12984                       if (sizeflag & DFLAG)
12985                         *obufp++ = intel_syntax ? 'd' : 'l';
12986                       else
12987                         *obufp++ = 'w';
12988                       used_prefixes |= (prefixes & PREFIX_DATA);
12989                     }
12990                 }
12991             }
12992           break;
12993         case 'U':
12994           if (intel_syntax)
12995             break;
12996           if (address_mode == mode_64bit
12997               && ((sizeflag & DFLAG) || (rex & REX_W)))
12998             {
12999               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13000                 *obufp++ = 'q';
13001               break;
13002             }
13003           /* Fall through.  */
13004           goto case_Q;
13005         case 'Q':
13006           if (l == 0 && len == 1)
13007             {
13008 case_Q:
13009               if (intel_syntax && !alt)
13010                 break;
13011               USED_REX (REX_W);
13012               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13013                 {
13014                   if (rex & REX_W)
13015                     *obufp++ = 'q';
13016                   else
13017                     {
13018                       if (sizeflag & DFLAG)
13019                         *obufp++ = intel_syntax ? 'd' : 'l';
13020                       else
13021                         *obufp++ = 'w';
13022                       used_prefixes |= (prefixes & PREFIX_DATA);
13023                     }
13024                 }
13025             }
13026           else
13027             {
13028               if (l != 1 || len != 2 || last[0] != 'L')
13029                 {
13030                   SAVE_LAST (*p);
13031                   break;
13032                 }
13033               if (intel_syntax
13034                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13035                 break;
13036               if ((rex & REX_W))
13037                 {
13038                   USED_REX (REX_W);
13039                   *obufp++ = 'q';
13040                 }
13041               else
13042                 *obufp++ = 'l';
13043             }
13044           break;
13045         case 'R':
13046           USED_REX (REX_W);
13047           if (rex & REX_W)
13048             *obufp++ = 'q';
13049           else if (sizeflag & DFLAG)
13050             {
13051               if (intel_syntax)
13052                   *obufp++ = 'd';
13053               else
13054                   *obufp++ = 'l';
13055             }
13056           else
13057             *obufp++ = 'w';
13058           if (intel_syntax && !p[1]
13059               && ((rex & REX_W) || (sizeflag & DFLAG)))
13060             *obufp++ = 'e';
13061           if (!(rex & REX_W))
13062             used_prefixes |= (prefixes & PREFIX_DATA);
13063           break;
13064         case 'V':
13065           if (l == 0 && len == 1)
13066             {
13067               if (intel_syntax)
13068                 break;
13069               if (address_mode == mode_64bit
13070                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13071                 {
13072                   if (sizeflag & SUFFIX_ALWAYS)
13073                     *obufp++ = 'q';
13074                   break;
13075                 }
13076             }
13077           else
13078             {
13079               if (l != 1
13080                   || len != 2
13081                   || last[0] != 'L')
13082                 {
13083                   SAVE_LAST (*p);
13084                   break;
13085                 }
13086
13087               if (rex & REX_W)
13088                 {
13089                   *obufp++ = 'a';
13090                   *obufp++ = 'b';
13091                   *obufp++ = 's';
13092                 }
13093             }
13094           /* Fall through.  */
13095           goto case_S;
13096         case 'S':
13097           if (l == 0 && len == 1)
13098             {
13099 case_S:
13100               if (intel_syntax)
13101                 break;
13102               if (sizeflag & SUFFIX_ALWAYS)
13103                 {
13104                   if (rex & REX_W)
13105                     *obufp++ = 'q';
13106                   else
13107                     {
13108                       if (sizeflag & DFLAG)
13109                         *obufp++ = 'l';
13110                       else
13111                         *obufp++ = 'w';
13112                       used_prefixes |= (prefixes & PREFIX_DATA);
13113                     }
13114                 }
13115             }
13116           else
13117             {
13118               if (l != 1
13119                   || len != 2
13120                   || last[0] != 'L')
13121                 {
13122                   SAVE_LAST (*p);
13123                   break;
13124                 }
13125
13126               if (address_mode == mode_64bit
13127                   && !(prefixes & PREFIX_ADDR))
13128                 {
13129                   *obufp++ = 'a';
13130                   *obufp++ = 'b';
13131                   *obufp++ = 's';
13132                 }
13133
13134               goto case_S;
13135             }
13136           break;
13137         case 'X':
13138           if (l != 0 || len != 1)
13139             {
13140               SAVE_LAST (*p);
13141               break;
13142             }
13143           if (need_vex && vex.prefix)
13144             {
13145               if (vex.prefix == DATA_PREFIX_OPCODE)
13146                 *obufp++ = 'd';
13147               else
13148                 *obufp++ = 's';
13149             }
13150           else
13151             {
13152               if (prefixes & PREFIX_DATA)
13153                 *obufp++ = 'd';
13154               else
13155                 *obufp++ = 's';
13156               used_prefixes |= (prefixes & PREFIX_DATA);
13157             }
13158           break;
13159         case 'Y':
13160           if (l == 0 && len == 1)
13161             abort ();
13162           else
13163             {
13164               if (l != 1 || len != 2 || last[0] != 'X')
13165                 {
13166                   SAVE_LAST (*p);
13167                   break;
13168                 }
13169               if (!need_vex)
13170                 abort ();
13171               if (intel_syntax
13172                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13173                 break;
13174               switch (vex.length)
13175                 {
13176                 case 128:
13177                   *obufp++ = 'x';
13178                   break;
13179                 case 256:
13180                   *obufp++ = 'y';
13181                   break;
13182                 case 512:
13183                   if (!vex.evex)
13184                 default:
13185                     abort ();
13186                 }
13187             }
13188           break;
13189         case 'W':
13190           if (l == 0 && len == 1)
13191             {
13192               /* operand size flag for cwtl, cbtw */
13193               USED_REX (REX_W);
13194               if (rex & REX_W)
13195                 {
13196                   if (intel_syntax)
13197                     *obufp++ = 'd';
13198                   else
13199                     *obufp++ = 'l';
13200                 }
13201               else if (sizeflag & DFLAG)
13202                 *obufp++ = 'w';
13203               else
13204                 *obufp++ = 'b';
13205               if (!(rex & REX_W))
13206                 used_prefixes |= (prefixes & PREFIX_DATA);
13207             }
13208           else
13209             {
13210               if (l != 1
13211                   || len != 2
13212                   || (last[0] != 'X'
13213                       && last[0] != 'L'))
13214                 {
13215                   SAVE_LAST (*p);
13216                   break;
13217                 }
13218               if (!need_vex)
13219                 abort ();
13220               if (last[0] == 'X')
13221                 *obufp++ = vex.w ? 'd': 's';
13222               else
13223                 *obufp++ = vex.w ? 'q': 'd';
13224             }
13225           break;
13226         case '^':
13227           if (intel_syntax)
13228             break;
13229           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13230             {
13231               if (sizeflag & DFLAG)
13232                 *obufp++ = 'l';
13233               else
13234                 *obufp++ = 'w';
13235               used_prefixes |= (prefixes & PREFIX_DATA);
13236             }
13237           break;
13238         case '@':
13239           if (intel_syntax)
13240             break;
13241           if (address_mode == mode_64bit
13242               && (isa64 == intel64
13243                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13244               *obufp++ = 'q';
13245           else if ((prefixes & PREFIX_DATA))
13246             {
13247               if (!(sizeflag & DFLAG))
13248                 *obufp++ = 'w';
13249               used_prefixes |= (prefixes & PREFIX_DATA);
13250             }
13251           break;
13252         }
13253       alt = 0;
13254     }
13255   *obufp = 0;
13256   mnemonicendp = obufp;
13257   return 0;
13258 }
13259
13260 static void
13261 oappend (const char *s)
13262 {
13263   obufp = stpcpy (obufp, s);
13264 }
13265
13266 static void
13267 append_seg (void)
13268 {
13269   /* Only print the active segment register.  */
13270   if (!active_seg_prefix)
13271     return;
13272
13273   used_prefixes |= active_seg_prefix;
13274   switch (active_seg_prefix)
13275     {
13276     case PREFIX_CS:
13277       oappend_maybe_intel ("%cs:");
13278       break;
13279     case PREFIX_DS:
13280       oappend_maybe_intel ("%ds:");
13281       break;
13282     case PREFIX_SS:
13283       oappend_maybe_intel ("%ss:");
13284       break;
13285     case PREFIX_ES:
13286       oappend_maybe_intel ("%es:");
13287       break;
13288     case PREFIX_FS:
13289       oappend_maybe_intel ("%fs:");
13290       break;
13291     case PREFIX_GS:
13292       oappend_maybe_intel ("%gs:");
13293       break;
13294     default:
13295       break;
13296     }
13297 }
13298
13299 static void
13300 OP_indirE (int bytemode, int sizeflag)
13301 {
13302   if (!intel_syntax)
13303     oappend ("*");
13304   OP_E (bytemode, sizeflag);
13305 }
13306
13307 static void
13308 print_operand_value (char *buf, int hex, bfd_vma disp)
13309 {
13310   if (address_mode == mode_64bit)
13311     {
13312       if (hex)
13313         {
13314           char tmp[30];
13315           int i;
13316           buf[0] = '0';
13317           buf[1] = 'x';
13318           sprintf_vma (tmp, disp);
13319           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13320           strcpy (buf + 2, tmp + i);
13321         }
13322       else
13323         {
13324           bfd_signed_vma v = disp;
13325           char tmp[30];
13326           int i;
13327           if (v < 0)
13328             {
13329               *(buf++) = '-';
13330               v = -disp;
13331               /* Check for possible overflow on 0x8000000000000000.  */
13332               if (v < 0)
13333                 {
13334                   strcpy (buf, "9223372036854775808");
13335                   return;
13336                 }
13337             }
13338           if (!v)
13339             {
13340               strcpy (buf, "0");
13341               return;
13342             }
13343
13344           i = 0;
13345           tmp[29] = 0;
13346           while (v)
13347             {
13348               tmp[28 - i] = (v % 10) + '0';
13349               v /= 10;
13350               i++;
13351             }
13352           strcpy (buf, tmp + 29 - i);
13353         }
13354     }
13355   else
13356     {
13357       if (hex)
13358         sprintf (buf, "0x%x", (unsigned int) disp);
13359       else
13360         sprintf (buf, "%d", (int) disp);
13361     }
13362 }
13363
13364 /* Put DISP in BUF as signed hex number.  */
13365
13366 static void
13367 print_displacement (char *buf, bfd_vma disp)
13368 {
13369   bfd_signed_vma val = disp;
13370   char tmp[30];
13371   int i, j = 0;
13372
13373   if (val < 0)
13374     {
13375       buf[j++] = '-';
13376       val = -disp;
13377
13378       /* Check for possible overflow.  */
13379       if (val < 0)
13380         {
13381           switch (address_mode)
13382             {
13383             case mode_64bit:
13384               strcpy (buf + j, "0x8000000000000000");
13385               break;
13386             case mode_32bit:
13387               strcpy (buf + j, "0x80000000");
13388               break;
13389             case mode_16bit:
13390               strcpy (buf + j, "0x8000");
13391               break;
13392             }
13393           return;
13394         }
13395     }
13396
13397   buf[j++] = '0';
13398   buf[j++] = 'x';
13399
13400   sprintf_vma (tmp, (bfd_vma) val);
13401   for (i = 0; tmp[i] == '0'; i++)
13402     continue;
13403   if (tmp[i] == '\0')
13404     i--;
13405   strcpy (buf + j, tmp + i);
13406 }
13407
13408 static void
13409 intel_operand_size (int bytemode, int sizeflag)
13410 {
13411   if (vex.evex
13412       && vex.b
13413       && (bytemode == x_mode
13414           || bytemode == evex_half_bcst_xmmq_mode))
13415     {
13416       if (vex.w)
13417         oappend ("QWORD PTR ");
13418       else
13419         oappend ("DWORD PTR ");
13420       return;
13421     }
13422   switch (bytemode)
13423     {
13424     case b_mode:
13425     case b_swap_mode:
13426     case dqb_mode:
13427     case db_mode:
13428       oappend ("BYTE PTR ");
13429       break;
13430     case w_mode:
13431     case dw_mode:
13432     case dqw_mode:
13433       oappend ("WORD PTR ");
13434       break;
13435     case indir_v_mode:
13436       if (address_mode == mode_64bit && isa64 == intel64)
13437         {
13438           oappend ("QWORD PTR ");
13439           break;
13440         }
13441       /* Fall through.  */
13442     case stack_v_mode:
13443       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13444         {
13445           oappend ("QWORD PTR ");
13446           break;
13447         }
13448       /* Fall through.  */
13449     case v_mode:
13450     case v_swap_mode:
13451     case dq_mode:
13452       USED_REX (REX_W);
13453       if (rex & REX_W)
13454         oappend ("QWORD PTR ");
13455       else
13456         {
13457           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13458             oappend ("DWORD PTR ");
13459           else
13460             oappend ("WORD PTR ");
13461           used_prefixes |= (prefixes & PREFIX_DATA);
13462         }
13463       break;
13464     case z_mode:
13465       if ((rex & REX_W) || (sizeflag & DFLAG))
13466         *obufp++ = 'D';
13467       oappend ("WORD PTR ");
13468       if (!(rex & REX_W))
13469         used_prefixes |= (prefixes & PREFIX_DATA);
13470       break;
13471     case a_mode:
13472       if (sizeflag & DFLAG)
13473         oappend ("QWORD PTR ");
13474       else
13475         oappend ("DWORD PTR ");
13476       used_prefixes |= (prefixes & PREFIX_DATA);
13477       break;
13478     case d_mode:
13479     case d_scalar_mode:
13480     case d_scalar_swap_mode:
13481     case d_swap_mode:
13482     case dqd_mode:
13483       oappend ("DWORD PTR ");
13484       break;
13485     case q_mode:
13486     case q_scalar_mode:
13487     case q_scalar_swap_mode:
13488     case q_swap_mode:
13489       oappend ("QWORD PTR ");
13490       break;
13491     case m_mode:
13492       if (address_mode == mode_64bit)
13493         oappend ("QWORD PTR ");
13494       else
13495         oappend ("DWORD PTR ");
13496       break;
13497     case f_mode:
13498       if (sizeflag & DFLAG)
13499         oappend ("FWORD PTR ");
13500       else
13501         oappend ("DWORD PTR ");
13502       used_prefixes |= (prefixes & PREFIX_DATA);
13503       break;
13504     case t_mode:
13505       oappend ("TBYTE PTR ");
13506       break;
13507     case x_mode:
13508     case x_swap_mode:
13509     case evex_x_gscat_mode:
13510     case evex_x_nobcst_mode:
13511     case b_scalar_mode:
13512     case w_scalar_mode:
13513       if (need_vex)
13514         {
13515           switch (vex.length)
13516             {
13517             case 128:
13518               oappend ("XMMWORD PTR ");
13519               break;
13520             case 256:
13521               oappend ("YMMWORD PTR ");
13522               break;
13523             case 512:
13524               oappend ("ZMMWORD PTR ");
13525               break;
13526             default:
13527               abort ();
13528             }
13529         }
13530       else
13531         oappend ("XMMWORD PTR ");
13532       break;
13533     case xmm_mode:
13534       oappend ("XMMWORD PTR ");
13535       break;
13536     case ymm_mode:
13537       oappend ("YMMWORD PTR ");
13538       break;
13539     case xmmq_mode:
13540     case evex_half_bcst_xmmq_mode:
13541       if (!need_vex)
13542         abort ();
13543
13544       switch (vex.length)
13545         {
13546         case 128:
13547           oappend ("QWORD PTR ");
13548           break;
13549         case 256:
13550           oappend ("XMMWORD PTR ");
13551           break;
13552         case 512:
13553           oappend ("YMMWORD PTR ");
13554           break;
13555         default:
13556           abort ();
13557         }
13558       break;
13559     case xmm_mb_mode:
13560       if (!need_vex)
13561         abort ();
13562
13563       switch (vex.length)
13564         {
13565         case 128:
13566         case 256:
13567         case 512:
13568           oappend ("BYTE PTR ");
13569           break;
13570         default:
13571           abort ();
13572         }
13573       break;
13574     case xmm_mw_mode:
13575       if (!need_vex)
13576         abort ();
13577
13578       switch (vex.length)
13579         {
13580         case 128:
13581         case 256:
13582         case 512:
13583           oappend ("WORD PTR ");
13584           break;
13585         default:
13586           abort ();
13587         }
13588       break;
13589     case xmm_md_mode:
13590       if (!need_vex)
13591         abort ();
13592
13593       switch (vex.length)
13594         {
13595         case 128:
13596         case 256:
13597         case 512:
13598           oappend ("DWORD PTR ");
13599           break;
13600         default:
13601           abort ();
13602         }
13603       break;
13604     case xmm_mq_mode:
13605       if (!need_vex)
13606         abort ();
13607
13608       switch (vex.length)
13609         {
13610         case 128:
13611         case 256:
13612         case 512:
13613           oappend ("QWORD PTR ");
13614           break;
13615         default:
13616           abort ();
13617         }
13618       break;
13619     case xmmdw_mode:
13620       if (!need_vex)
13621         abort ();
13622
13623       switch (vex.length)
13624         {
13625         case 128:
13626           oappend ("WORD PTR ");
13627           break;
13628         case 256:
13629           oappend ("DWORD PTR ");
13630           break;
13631         case 512:
13632           oappend ("QWORD PTR ");
13633           break;
13634         default:
13635           abort ();
13636         }
13637       break;
13638     case xmmqd_mode:
13639       if (!need_vex)
13640         abort ();
13641
13642       switch (vex.length)
13643         {
13644         case 128:
13645           oappend ("DWORD PTR ");
13646           break;
13647         case 256:
13648           oappend ("QWORD PTR ");
13649           break;
13650         case 512:
13651           oappend ("XMMWORD PTR ");
13652           break;
13653         default:
13654           abort ();
13655         }
13656       break;
13657     case ymmq_mode:
13658       if (!need_vex)
13659         abort ();
13660
13661       switch (vex.length)
13662         {
13663         case 128:
13664           oappend ("QWORD PTR ");
13665           break;
13666         case 256:
13667           oappend ("YMMWORD PTR ");
13668           break;
13669         case 512:
13670           oappend ("ZMMWORD PTR ");
13671           break;
13672         default:
13673           abort ();
13674         }
13675       break;
13676     case ymmxmm_mode:
13677       if (!need_vex)
13678         abort ();
13679
13680       switch (vex.length)
13681         {
13682         case 128:
13683         case 256:
13684           oappend ("XMMWORD PTR ");
13685           break;
13686         default:
13687           abort ();
13688         }
13689       break;
13690     case o_mode:
13691       oappend ("OWORD PTR ");
13692       break;
13693     case xmm_mdq_mode:
13694     case vex_w_dq_mode:
13695     case vex_scalar_w_dq_mode:
13696       if (!need_vex)
13697         abort ();
13698
13699       if (vex.w)
13700         oappend ("QWORD PTR ");
13701       else
13702         oappend ("DWORD PTR ");
13703       break;
13704     case vex_vsib_d_w_dq_mode:
13705     case vex_vsib_q_w_dq_mode:
13706       if (!need_vex)
13707         abort ();
13708
13709       if (!vex.evex)
13710         {
13711           if (vex.w)
13712             oappend ("QWORD PTR ");
13713           else
13714             oappend ("DWORD PTR ");
13715         }
13716       else
13717         {
13718           switch (vex.length)
13719             {
13720             case 128:
13721               oappend ("XMMWORD PTR ");
13722               break;
13723             case 256:
13724               oappend ("YMMWORD PTR ");
13725               break;
13726             case 512:
13727               oappend ("ZMMWORD PTR ");
13728               break;
13729             default:
13730               abort ();
13731             }
13732         }
13733       break;
13734     case vex_vsib_q_w_d_mode:
13735     case vex_vsib_d_w_d_mode:
13736       if (!need_vex || !vex.evex)
13737         abort ();
13738
13739       switch (vex.length)
13740         {
13741         case 128:
13742           oappend ("QWORD PTR ");
13743           break;
13744         case 256:
13745           oappend ("XMMWORD PTR ");
13746           break;
13747         case 512:
13748           oappend ("YMMWORD PTR ");
13749           break;
13750         default:
13751           abort ();
13752         }
13753
13754       break;
13755     case mask_bd_mode:
13756       if (!need_vex || vex.length != 128)
13757         abort ();
13758       if (vex.w)
13759         oappend ("DWORD PTR ");
13760       else
13761         oappend ("BYTE PTR ");
13762       break;
13763     case mask_mode:
13764       if (!need_vex)
13765         abort ();
13766       if (vex.w)
13767         oappend ("QWORD PTR ");
13768       else
13769         oappend ("WORD PTR ");
13770       break;
13771     case v_bnd_mode:
13772     case v_bndmk_mode:
13773     default:
13774       break;
13775     }
13776 }
13777
13778 static void
13779 OP_E_register (int bytemode, int sizeflag)
13780 {
13781   int reg = modrm.rm;
13782   const char **names;
13783
13784   USED_REX (REX_B);
13785   if ((rex & REX_B))
13786     reg += 8;
13787
13788   if ((sizeflag & SUFFIX_ALWAYS)
13789       && (bytemode == b_swap_mode
13790           || bytemode == bnd_swap_mode
13791           || bytemode == v_swap_mode))
13792     swap_operand ();
13793
13794   switch (bytemode)
13795     {
13796     case b_mode:
13797     case b_swap_mode:
13798       USED_REX (0);
13799       if (rex)
13800         names = names8rex;
13801       else
13802         names = names8;
13803       break;
13804     case w_mode:
13805       names = names16;
13806       break;
13807     case d_mode:
13808     case dw_mode:
13809     case db_mode:
13810       names = names32;
13811       break;
13812     case q_mode:
13813       names = names64;
13814       break;
13815     case m_mode:
13816     case v_bnd_mode:
13817       names = address_mode == mode_64bit ? names64 : names32;
13818       break;
13819     case bnd_mode:
13820     case bnd_swap_mode:
13821       if (reg > 0x3)
13822         {
13823           oappend ("(bad)");
13824           return;
13825         }
13826       names = names_bnd;
13827       break;
13828     case indir_v_mode:
13829       if (address_mode == mode_64bit && isa64 == intel64)
13830         {
13831           names = names64;
13832           break;
13833         }
13834       /* Fall through.  */
13835     case stack_v_mode:
13836       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13837         {
13838           names = names64;
13839           break;
13840         }
13841       bytemode = v_mode;
13842       /* Fall through.  */
13843     case v_mode:
13844     case v_swap_mode:
13845     case dq_mode:
13846     case dqb_mode:
13847     case dqd_mode:
13848     case dqw_mode:
13849       USED_REX (REX_W);
13850       if (rex & REX_W)
13851         names = names64;
13852       else
13853         {
13854           if ((sizeflag & DFLAG)
13855               || (bytemode != v_mode
13856                   && bytemode != v_swap_mode))
13857             names = names32;
13858           else
13859             names = names16;
13860           used_prefixes |= (prefixes & PREFIX_DATA);
13861         }
13862       break;
13863     case va_mode:
13864       names = (address_mode == mode_64bit
13865                ? names64 : names32);
13866       if (!(prefixes & PREFIX_ADDR))
13867         names = (address_mode == mode_16bit
13868                      ? names16 : names);
13869       else
13870         {
13871           /* Remove "addr16/addr32".  */
13872           all_prefixes[last_addr_prefix] = 0;
13873           names = (address_mode != mode_32bit
13874                        ? names32 : names16);
13875           used_prefixes |= PREFIX_ADDR;
13876         }
13877       break;
13878     case mask_bd_mode:
13879     case mask_mode:
13880       if (reg > 0x7)
13881         {
13882           oappend ("(bad)");
13883           return;
13884         }
13885       names = names_mask;
13886       break;
13887     case 0:
13888       return;
13889     default:
13890       oappend (INTERNAL_DISASSEMBLER_ERROR);
13891       return;
13892     }
13893   oappend (names[reg]);
13894 }
13895
13896 static void
13897 OP_E_memory (int bytemode, int sizeflag)
13898 {
13899   bfd_vma disp = 0;
13900   int add = (rex & REX_B) ? 8 : 0;
13901   int riprel = 0;
13902   int shift;
13903
13904   if (vex.evex)
13905     {
13906       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13907       if (vex.b
13908           && bytemode != x_mode
13909           && bytemode != xmmq_mode
13910           && bytemode != evex_half_bcst_xmmq_mode)
13911         {
13912           BadOp ();
13913           return;
13914         }
13915       switch (bytemode)
13916         {
13917         case dqw_mode:
13918         case dw_mode:
13919           shift = 1;
13920           break;
13921         case dqb_mode:
13922         case db_mode:
13923           shift = 0;
13924           break;
13925         case dq_mode:
13926           if (address_mode != mode_64bit)
13927             {
13928               shift = 2;
13929               break;
13930             }
13931             /* fall through */
13932         case vex_vsib_d_w_dq_mode:
13933         case vex_vsib_d_w_d_mode:
13934         case vex_vsib_q_w_dq_mode:
13935         case vex_vsib_q_w_d_mode:
13936         case evex_x_gscat_mode:
13937         case xmm_mdq_mode:
13938           shift = vex.w ? 3 : 2;
13939           break;
13940         case x_mode:
13941         case evex_half_bcst_xmmq_mode:
13942         case xmmq_mode:
13943           if (vex.b)
13944             {
13945               shift = vex.w ? 3 : 2;
13946               break;
13947             }
13948           /* Fall through.  */
13949         case xmmqd_mode:
13950         case xmmdw_mode:
13951         case ymmq_mode:
13952         case evex_x_nobcst_mode:
13953         case x_swap_mode:
13954           switch (vex.length)
13955             {
13956             case 128:
13957               shift = 4;
13958               break;
13959             case 256:
13960               shift = 5;
13961               break;
13962             case 512:
13963               shift = 6;
13964               break;
13965             default:
13966               abort ();
13967             }
13968           break;
13969         case ymm_mode:
13970           shift = 5;
13971           break;
13972         case xmm_mode:
13973           shift = 4;
13974           break;
13975         case xmm_mq_mode:
13976         case q_mode:
13977         case q_scalar_mode:
13978         case q_swap_mode:
13979         case q_scalar_swap_mode:
13980           shift = 3;
13981           break;
13982         case dqd_mode:
13983         case xmm_md_mode:
13984         case d_mode:
13985         case d_scalar_mode:
13986         case d_swap_mode:
13987         case d_scalar_swap_mode:
13988           shift = 2;
13989           break;
13990         case w_scalar_mode:
13991         case xmm_mw_mode:
13992           shift = 1;
13993           break;
13994         case b_scalar_mode:
13995         case xmm_mb_mode:
13996           shift = 0;
13997           break;
13998         default:
13999           abort ();
14000         }
14001       /* Make necessary corrections to shift for modes that need it.
14002          For these modes we currently have shift 4, 5 or 6 depending on
14003          vex.length (it corresponds to xmmword, ymmword or zmmword
14004          operand).  We might want to make it 3, 4 or 5 (e.g. for
14005          xmmq_mode).  In case of broadcast enabled the corrections
14006          aren't needed, as element size is always 32 or 64 bits.  */
14007       if (!vex.b
14008           && (bytemode == xmmq_mode
14009               || bytemode == evex_half_bcst_xmmq_mode))
14010         shift -= 1;
14011       else if (bytemode == xmmqd_mode)
14012         shift -= 2;
14013       else if (bytemode == xmmdw_mode)
14014         shift -= 3;
14015       else if (bytemode == ymmq_mode && vex.length == 128)
14016         shift -= 1;
14017     }
14018   else
14019     shift = 0;
14020
14021   USED_REX (REX_B);
14022   if (intel_syntax)
14023     intel_operand_size (bytemode, sizeflag);
14024   append_seg ();
14025
14026   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14027     {
14028       /* 32/64 bit address mode */
14029       int havedisp;
14030       int havesib;
14031       int havebase;
14032       int haveindex;
14033       int needindex;
14034       int needaddr32;
14035       int base, rbase;
14036       int vindex = 0;
14037       int scale = 0;
14038       int addr32flag = !((sizeflag & AFLAG)
14039                          || bytemode == v_bnd_mode
14040                          || bytemode == v_bndmk_mode
14041                          || bytemode == bnd_mode
14042                          || bytemode == bnd_swap_mode);
14043       const char **indexes64 = names64;
14044       const char **indexes32 = names32;
14045
14046       havesib = 0;
14047       havebase = 1;
14048       haveindex = 0;
14049       base = modrm.rm;
14050
14051       if (base == 4)
14052         {
14053           havesib = 1;
14054           vindex = sib.index;
14055           USED_REX (REX_X);
14056           if (rex & REX_X)
14057             vindex += 8;
14058           switch (bytemode)
14059             {
14060             case vex_vsib_d_w_dq_mode:
14061             case vex_vsib_d_w_d_mode:
14062             case vex_vsib_q_w_dq_mode:
14063             case vex_vsib_q_w_d_mode:
14064               if (!need_vex)
14065                 abort ();
14066               if (vex.evex)
14067                 {
14068                   if (!vex.v)
14069                     vindex += 16;
14070                 }
14071
14072               haveindex = 1;
14073               switch (vex.length)
14074                 {
14075                 case 128:
14076                   indexes64 = indexes32 = names_xmm;
14077                   break;
14078                 case 256:
14079                   if (!vex.w
14080                       || bytemode == vex_vsib_q_w_dq_mode
14081                       || bytemode == vex_vsib_q_w_d_mode)
14082                     indexes64 = indexes32 = names_ymm;
14083                   else
14084                     indexes64 = indexes32 = names_xmm;
14085                   break;
14086                 case 512:
14087                   if (!vex.w
14088                       || bytemode == vex_vsib_q_w_dq_mode
14089                       || bytemode == vex_vsib_q_w_d_mode)
14090                     indexes64 = indexes32 = names_zmm;
14091                   else
14092                     indexes64 = indexes32 = names_ymm;
14093                   break;
14094                 default:
14095                   abort ();
14096                 }
14097               break;
14098             default:
14099               haveindex = vindex != 4;
14100               break;
14101             }
14102           scale = sib.scale;
14103           base = sib.base;
14104           codep++;
14105         }
14106       rbase = base + add;
14107
14108       switch (modrm.mod)
14109         {
14110         case 0:
14111           if (base == 5)
14112             {
14113               havebase = 0;
14114               if (address_mode == mode_64bit && !havesib)
14115                 riprel = 1;
14116               disp = get32s ();
14117               if (riprel && bytemode == v_bndmk_mode)
14118                 {
14119                   oappend ("(bad)");
14120                   return;
14121                 }
14122             }
14123           break;
14124         case 1:
14125           FETCH_DATA (the_info, codep + 1);
14126           disp = *codep++;
14127           if ((disp & 0x80) != 0)
14128             disp -= 0x100;
14129           if (vex.evex && shift > 0)
14130             disp <<= shift;
14131           break;
14132         case 2:
14133           disp = get32s ();
14134           break;
14135         }
14136
14137       needindex = 0;
14138       needaddr32 = 0;
14139       if (havesib
14140           && !havebase
14141           && !haveindex
14142           && address_mode != mode_16bit)
14143         {
14144           if (address_mode == mode_64bit)
14145             {
14146               /* Display eiz instead of addr32.  */
14147               needindex = addr32flag;
14148               needaddr32 = 1;
14149             }
14150           else
14151             {
14152               /* In 32-bit mode, we need index register to tell [offset]
14153                  from [eiz*1 + offset].  */
14154               needindex = 1;
14155             }
14156         }
14157
14158       havedisp = (havebase
14159                   || needindex
14160                   || (havesib && (haveindex || scale != 0)));
14161
14162       if (!intel_syntax)
14163         if (modrm.mod != 0 || base == 5)
14164           {
14165             if (havedisp || riprel)
14166               print_displacement (scratchbuf, disp);
14167             else
14168               print_operand_value (scratchbuf, 1, disp);
14169             oappend (scratchbuf);
14170             if (riprel)
14171               {
14172                 set_op (disp, 1);
14173                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14174               }
14175           }
14176
14177       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14178           && (bytemode != v_bnd_mode)
14179           && (bytemode != v_bndmk_mode)
14180           && (bytemode != bnd_mode)
14181           && (bytemode != bnd_swap_mode))
14182         used_prefixes |= PREFIX_ADDR;
14183
14184       if (havedisp || (intel_syntax && riprel))
14185         {
14186           *obufp++ = open_char;
14187           if (intel_syntax && riprel)
14188             {
14189               set_op (disp, 1);
14190               oappend (!addr32flag ? "rip" : "eip");
14191             }
14192           *obufp = '\0';
14193           if (havebase)
14194             oappend (address_mode == mode_64bit && !addr32flag
14195                      ? names64[rbase] : names32[rbase]);
14196           if (havesib)
14197             {
14198               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14199                  print index to tell base + index from base.  */
14200               if (scale != 0
14201                   || needindex
14202                   || haveindex
14203                   || (havebase && base != ESP_REG_NUM))
14204                 {
14205                   if (!intel_syntax || havebase)
14206                     {
14207                       *obufp++ = separator_char;
14208                       *obufp = '\0';
14209                     }
14210                   if (haveindex)
14211                     oappend (address_mode == mode_64bit && !addr32flag
14212                              ? indexes64[vindex] : indexes32[vindex]);
14213                   else
14214                     oappend (address_mode == mode_64bit && !addr32flag
14215                              ? index64 : index32);
14216
14217                   *obufp++ = scale_char;
14218                   *obufp = '\0';
14219                   sprintf (scratchbuf, "%d", 1 << scale);
14220                   oappend (scratchbuf);
14221                 }
14222             }
14223           if (intel_syntax
14224               && (disp || modrm.mod != 0 || base == 5))
14225             {
14226               if (!havedisp || (bfd_signed_vma) disp >= 0)
14227                 {
14228                   *obufp++ = '+';
14229                   *obufp = '\0';
14230                 }
14231               else if (modrm.mod != 1 && disp != -disp)
14232                 {
14233                   *obufp++ = '-';
14234                   *obufp = '\0';
14235                   disp = - (bfd_signed_vma) disp;
14236                 }
14237
14238               if (havedisp)
14239                 print_displacement (scratchbuf, disp);
14240               else
14241                 print_operand_value (scratchbuf, 1, disp);
14242               oappend (scratchbuf);
14243             }
14244
14245           *obufp++ = close_char;
14246           *obufp = '\0';
14247         }
14248       else if (intel_syntax)
14249         {
14250           if (modrm.mod != 0 || base == 5)
14251             {
14252               if (!active_seg_prefix)
14253                 {
14254                   oappend (names_seg[ds_reg - es_reg]);
14255                   oappend (":");
14256                 }
14257               print_operand_value (scratchbuf, 1, disp);
14258               oappend (scratchbuf);
14259             }
14260         }
14261     }
14262   else
14263     {
14264       /* 16 bit address mode */
14265       used_prefixes |= prefixes & PREFIX_ADDR;
14266       switch (modrm.mod)
14267         {
14268         case 0:
14269           if (modrm.rm == 6)
14270             {
14271               disp = get16 ();
14272               if ((disp & 0x8000) != 0)
14273                 disp -= 0x10000;
14274             }
14275           break;
14276         case 1:
14277           FETCH_DATA (the_info, codep + 1);
14278           disp = *codep++;
14279           if ((disp & 0x80) != 0)
14280             disp -= 0x100;
14281           if (vex.evex && shift > 0)
14282             disp <<= shift;
14283           break;
14284         case 2:
14285           disp = get16 ();
14286           if ((disp & 0x8000) != 0)
14287             disp -= 0x10000;
14288           break;
14289         }
14290
14291       if (!intel_syntax)
14292         if (modrm.mod != 0 || modrm.rm == 6)
14293           {
14294             print_displacement (scratchbuf, disp);
14295             oappend (scratchbuf);
14296           }
14297
14298       if (modrm.mod != 0 || modrm.rm != 6)
14299         {
14300           *obufp++ = open_char;
14301           *obufp = '\0';
14302           oappend (index16[modrm.rm]);
14303           if (intel_syntax
14304               && (disp || modrm.mod != 0 || modrm.rm == 6))
14305             {
14306               if ((bfd_signed_vma) disp >= 0)
14307                 {
14308                   *obufp++ = '+';
14309                   *obufp = '\0';
14310                 }
14311               else if (modrm.mod != 1)
14312                 {
14313                   *obufp++ = '-';
14314                   *obufp = '\0';
14315                   disp = - (bfd_signed_vma) disp;
14316                 }
14317
14318               print_displacement (scratchbuf, disp);
14319               oappend (scratchbuf);
14320             }
14321
14322           *obufp++ = close_char;
14323           *obufp = '\0';
14324         }
14325       else if (intel_syntax)
14326         {
14327           if (!active_seg_prefix)
14328             {
14329               oappend (names_seg[ds_reg - es_reg]);
14330               oappend (":");
14331             }
14332           print_operand_value (scratchbuf, 1, disp & 0xffff);
14333           oappend (scratchbuf);
14334         }
14335     }
14336   if (vex.evex && vex.b
14337       && (bytemode == x_mode
14338           || bytemode == xmmq_mode
14339           || bytemode == evex_half_bcst_xmmq_mode))
14340     {
14341       if (vex.w
14342           || bytemode == xmmq_mode
14343           || bytemode == evex_half_bcst_xmmq_mode)
14344         {
14345           switch (vex.length)
14346             {
14347             case 128:
14348               oappend ("{1to2}");
14349               break;
14350             case 256:
14351               oappend ("{1to4}");
14352               break;
14353             case 512:
14354               oappend ("{1to8}");
14355               break;
14356             default:
14357               abort ();
14358             }
14359         }
14360       else
14361         {
14362           switch (vex.length)
14363             {
14364             case 128:
14365               oappend ("{1to4}");
14366               break;
14367             case 256:
14368               oappend ("{1to8}");
14369               break;
14370             case 512:
14371               oappend ("{1to16}");
14372               break;
14373             default:
14374               abort ();
14375             }
14376         }
14377     }
14378 }
14379
14380 static void
14381 OP_E (int bytemode, int sizeflag)
14382 {
14383   /* Skip mod/rm byte.  */
14384   MODRM_CHECK;
14385   codep++;
14386
14387   if (modrm.mod == 3)
14388     OP_E_register (bytemode, sizeflag);
14389   else
14390     OP_E_memory (bytemode, sizeflag);
14391 }
14392
14393 static void
14394 OP_G (int bytemode, int sizeflag)
14395 {
14396   int add = 0;
14397   const char **names;
14398   USED_REX (REX_R);
14399   if (rex & REX_R)
14400     add += 8;
14401   switch (bytemode)
14402     {
14403     case b_mode:
14404       USED_REX (0);
14405       if (rex)
14406         oappend (names8rex[modrm.reg + add]);
14407       else
14408         oappend (names8[modrm.reg + add]);
14409       break;
14410     case w_mode:
14411       oappend (names16[modrm.reg + add]);
14412       break;
14413     case d_mode:
14414     case db_mode:
14415     case dw_mode:
14416       oappend (names32[modrm.reg + add]);
14417       break;
14418     case q_mode:
14419       oappend (names64[modrm.reg + add]);
14420       break;
14421     case bnd_mode:
14422       if (modrm.reg > 0x3)
14423         {
14424           oappend ("(bad)");
14425           return;
14426         }
14427       oappend (names_bnd[modrm.reg]);
14428       break;
14429     case v_mode:
14430     case dq_mode:
14431     case dqb_mode:
14432     case dqd_mode:
14433     case dqw_mode:
14434       USED_REX (REX_W);
14435       if (rex & REX_W)
14436         oappend (names64[modrm.reg + add]);
14437       else
14438         {
14439           if ((sizeflag & DFLAG) || bytemode != v_mode)
14440             oappend (names32[modrm.reg + add]);
14441           else
14442             oappend (names16[modrm.reg + add]);
14443           used_prefixes |= (prefixes & PREFIX_DATA);
14444         }
14445       break;
14446     case va_mode:
14447       names = (address_mode == mode_64bit
14448                ? names64 : names32);
14449       if (!(prefixes & PREFIX_ADDR))
14450         {
14451           if (address_mode == mode_16bit)
14452             names = names16;
14453         }
14454       else
14455         {
14456           /* Remove "addr16/addr32".  */
14457           all_prefixes[last_addr_prefix] = 0;
14458           names = (address_mode != mode_32bit
14459                        ? names32 : names16);
14460           used_prefixes |= PREFIX_ADDR;
14461         }
14462       oappend (names[modrm.reg + add]);
14463       break;
14464     case m_mode:
14465       if (address_mode == mode_64bit)
14466         oappend (names64[modrm.reg + add]);
14467       else
14468         oappend (names32[modrm.reg + add]);
14469       break;
14470     case mask_bd_mode:
14471     case mask_mode:
14472       if ((modrm.reg + add) > 0x7)
14473         {
14474           oappend ("(bad)");
14475           return;
14476         }
14477       oappend (names_mask[modrm.reg + add]);
14478       break;
14479     default:
14480       oappend (INTERNAL_DISASSEMBLER_ERROR);
14481       break;
14482     }
14483 }
14484
14485 static bfd_vma
14486 get64 (void)
14487 {
14488   bfd_vma x;
14489 #ifdef BFD64
14490   unsigned int a;
14491   unsigned int b;
14492
14493   FETCH_DATA (the_info, codep + 8);
14494   a = *codep++ & 0xff;
14495   a |= (*codep++ & 0xff) << 8;
14496   a |= (*codep++ & 0xff) << 16;
14497   a |= (*codep++ & 0xffu) << 24;
14498   b = *codep++ & 0xff;
14499   b |= (*codep++ & 0xff) << 8;
14500   b |= (*codep++ & 0xff) << 16;
14501   b |= (*codep++ & 0xffu) << 24;
14502   x = a + ((bfd_vma) b << 32);
14503 #else
14504   abort ();
14505   x = 0;
14506 #endif
14507   return x;
14508 }
14509
14510 static bfd_signed_vma
14511 get32 (void)
14512 {
14513   bfd_signed_vma x = 0;
14514
14515   FETCH_DATA (the_info, codep + 4);
14516   x = *codep++ & (bfd_signed_vma) 0xff;
14517   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14518   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14519   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14520   return x;
14521 }
14522
14523 static bfd_signed_vma
14524 get32s (void)
14525 {
14526   bfd_signed_vma x = 0;
14527
14528   FETCH_DATA (the_info, codep + 4);
14529   x = *codep++ & (bfd_signed_vma) 0xff;
14530   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14531   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14532   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14533
14534   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14535
14536   return x;
14537 }
14538
14539 static int
14540 get16 (void)
14541 {
14542   int x = 0;
14543
14544   FETCH_DATA (the_info, codep + 2);
14545   x = *codep++ & 0xff;
14546   x |= (*codep++ & 0xff) << 8;
14547   return x;
14548 }
14549
14550 static void
14551 set_op (bfd_vma op, int riprel)
14552 {
14553   op_index[op_ad] = op_ad;
14554   if (address_mode == mode_64bit)
14555     {
14556       op_address[op_ad] = op;
14557       op_riprel[op_ad] = riprel;
14558     }
14559   else
14560     {
14561       /* Mask to get a 32-bit address.  */
14562       op_address[op_ad] = op & 0xffffffff;
14563       op_riprel[op_ad] = riprel & 0xffffffff;
14564     }
14565 }
14566
14567 static void
14568 OP_REG (int code, int sizeflag)
14569 {
14570   const char *s;
14571   int add;
14572
14573   switch (code)
14574     {
14575     case es_reg: case ss_reg: case cs_reg:
14576     case ds_reg: case fs_reg: case gs_reg:
14577       oappend (names_seg[code - es_reg]);
14578       return;
14579     }
14580
14581   USED_REX (REX_B);
14582   if (rex & REX_B)
14583     add = 8;
14584   else
14585     add = 0;
14586
14587   switch (code)
14588     {
14589     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14590     case sp_reg: case bp_reg: case si_reg: case di_reg:
14591       s = names16[code - ax_reg + add];
14592       break;
14593     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14594     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14595       USED_REX (0);
14596       if (rex)
14597         s = names8rex[code - al_reg + add];
14598       else
14599         s = names8[code - al_reg];
14600       break;
14601     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14602     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14603       if (address_mode == mode_64bit
14604           && ((sizeflag & DFLAG) || (rex & REX_W)))
14605         {
14606           s = names64[code - rAX_reg + add];
14607           break;
14608         }
14609       code += eAX_reg - rAX_reg;
14610       /* Fall through.  */
14611     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14612     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14613       USED_REX (REX_W);
14614       if (rex & REX_W)
14615         s = names64[code - eAX_reg + add];
14616       else
14617         {
14618           if (sizeflag & DFLAG)
14619             s = names32[code - eAX_reg + add];
14620           else
14621             s = names16[code - eAX_reg + add];
14622           used_prefixes |= (prefixes & PREFIX_DATA);
14623         }
14624       break;
14625     default:
14626       s = INTERNAL_DISASSEMBLER_ERROR;
14627       break;
14628     }
14629   oappend (s);
14630 }
14631
14632 static void
14633 OP_IMREG (int code, int sizeflag)
14634 {
14635   const char *s;
14636
14637   switch (code)
14638     {
14639     case indir_dx_reg:
14640       if (intel_syntax)
14641         s = "dx";
14642       else
14643         s = "(%dx)";
14644       break;
14645     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14646     case sp_reg: case bp_reg: case si_reg: case di_reg:
14647       s = names16[code - ax_reg];
14648       break;
14649     case es_reg: case ss_reg: case cs_reg:
14650     case ds_reg: case fs_reg: case gs_reg:
14651       s = names_seg[code - es_reg];
14652       break;
14653     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14654     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14655       USED_REX (0);
14656       if (rex)
14657         s = names8rex[code - al_reg];
14658       else
14659         s = names8[code - al_reg];
14660       break;
14661     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14662     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14663       USED_REX (REX_W);
14664       if (rex & REX_W)
14665         s = names64[code - eAX_reg];
14666       else
14667         {
14668           if (sizeflag & DFLAG)
14669             s = names32[code - eAX_reg];
14670           else
14671             s = names16[code - eAX_reg];
14672           used_prefixes |= (prefixes & PREFIX_DATA);
14673         }
14674       break;
14675     case z_mode_ax_reg:
14676       if ((rex & REX_W) || (sizeflag & DFLAG))
14677         s = *names32;
14678       else
14679         s = *names16;
14680       if (!(rex & REX_W))
14681         used_prefixes |= (prefixes & PREFIX_DATA);
14682       break;
14683     default:
14684       s = INTERNAL_DISASSEMBLER_ERROR;
14685       break;
14686     }
14687   oappend (s);
14688 }
14689
14690 static void
14691 OP_I (int bytemode, int sizeflag)
14692 {
14693   bfd_signed_vma op;
14694   bfd_signed_vma mask = -1;
14695
14696   switch (bytemode)
14697     {
14698     case b_mode:
14699       FETCH_DATA (the_info, codep + 1);
14700       op = *codep++;
14701       mask = 0xff;
14702       break;
14703     case v_mode:
14704       USED_REX (REX_W);
14705       if (rex & REX_W)
14706         op = get32s ();
14707       else
14708         {
14709           if (sizeflag & DFLAG)
14710             {
14711               op = get32 ();
14712               mask = 0xffffffff;
14713             }
14714           else
14715             {
14716               op = get16 ();
14717               mask = 0xfffff;
14718             }
14719           used_prefixes |= (prefixes & PREFIX_DATA);
14720         }
14721       break;
14722     case d_mode:
14723       mask = 0xffffffff;
14724       op = get32 ();
14725       break;
14726     case w_mode:
14727       mask = 0xfffff;
14728       op = get16 ();
14729       break;
14730     case const_1_mode:
14731       if (intel_syntax)
14732         oappend ("1");
14733       return;
14734     default:
14735       oappend (INTERNAL_DISASSEMBLER_ERROR);
14736       return;
14737     }
14738
14739   op &= mask;
14740   scratchbuf[0] = '$';
14741   print_operand_value (scratchbuf + 1, 1, op);
14742   oappend_maybe_intel (scratchbuf);
14743   scratchbuf[0] = '\0';
14744 }
14745
14746 static void
14747 OP_I64 (int bytemode, int sizeflag)
14748 {
14749   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14750     {
14751       OP_I (bytemode, sizeflag);
14752       return;
14753     }
14754
14755   USED_REX (REX_W);
14756
14757   scratchbuf[0] = '$';
14758   print_operand_value (scratchbuf + 1, 1, get64 ());
14759   oappend_maybe_intel (scratchbuf);
14760   scratchbuf[0] = '\0';
14761 }
14762
14763 static void
14764 OP_sI (int bytemode, int sizeflag)
14765 {
14766   bfd_signed_vma op;
14767
14768   switch (bytemode)
14769     {
14770     case b_mode:
14771     case b_T_mode:
14772       FETCH_DATA (the_info, codep + 1);
14773       op = *codep++;
14774       if ((op & 0x80) != 0)
14775         op -= 0x100;
14776       if (bytemode == b_T_mode)
14777         {
14778           if (address_mode != mode_64bit
14779               || !((sizeflag & DFLAG) || (rex & REX_W)))
14780             {
14781               /* The operand-size prefix is overridden by a REX prefix.  */
14782               if ((sizeflag & DFLAG) || (rex & REX_W))
14783                 op &= 0xffffffff;
14784               else
14785                 op &= 0xffff;
14786           }
14787         }
14788       else
14789         {
14790           if (!(rex & REX_W))
14791             {
14792               if (sizeflag & DFLAG)
14793                 op &= 0xffffffff;
14794               else
14795                 op &= 0xffff;
14796             }
14797         }
14798       break;
14799     case v_mode:
14800       /* The operand-size prefix is overridden by a REX prefix.  */
14801       if ((sizeflag & DFLAG) || (rex & REX_W))
14802         op = get32s ();
14803       else
14804         op = get16 ();
14805       break;
14806     default:
14807       oappend (INTERNAL_DISASSEMBLER_ERROR);
14808       return;
14809     }
14810
14811   scratchbuf[0] = '$';
14812   print_operand_value (scratchbuf + 1, 1, op);
14813   oappend_maybe_intel (scratchbuf);
14814 }
14815
14816 static void
14817 OP_J (int bytemode, int sizeflag)
14818 {
14819   bfd_vma disp;
14820   bfd_vma mask = -1;
14821   bfd_vma segment = 0;
14822
14823   switch (bytemode)
14824     {
14825     case b_mode:
14826       FETCH_DATA (the_info, codep + 1);
14827       disp = *codep++;
14828       if ((disp & 0x80) != 0)
14829         disp -= 0x100;
14830       break;
14831     case v_mode:
14832       if (isa64 == amd64)
14833     case dqw_mode:
14834         USED_REX (REX_W);
14835       if ((sizeflag & DFLAG)
14836           || (address_mode == mode_64bit
14837               && ((isa64 != amd64 && bytemode != dqw_mode)
14838                   || (rex & REX_W))))
14839         disp = get32s ();
14840       else
14841         {
14842           disp = get16 ();
14843           if ((disp & 0x8000) != 0)
14844             disp -= 0x10000;
14845           /* In 16bit mode, address is wrapped around at 64k within
14846              the same segment.  Otherwise, a data16 prefix on a jump
14847              instruction means that the pc is masked to 16 bits after
14848              the displacement is added!  */
14849           mask = 0xffff;
14850           if ((prefixes & PREFIX_DATA) == 0)
14851             segment = ((start_pc + (codep - start_codep))
14852                        & ~((bfd_vma) 0xffff));
14853         }
14854       if (address_mode != mode_64bit
14855           || (isa64 == amd64 && !(rex & REX_W)))
14856         used_prefixes |= (prefixes & PREFIX_DATA);
14857       break;
14858     default:
14859       oappend (INTERNAL_DISASSEMBLER_ERROR);
14860       return;
14861     }
14862   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14863   set_op (disp, 0);
14864   print_operand_value (scratchbuf, 1, disp);
14865   oappend (scratchbuf);
14866 }
14867
14868 static void
14869 OP_SEG (int bytemode, int sizeflag)
14870 {
14871   if (bytemode == w_mode)
14872     oappend (names_seg[modrm.reg]);
14873   else
14874     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14875 }
14876
14877 static void
14878 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14879 {
14880   int seg, offset;
14881
14882   if (sizeflag & DFLAG)
14883     {
14884       offset = get32 ();
14885       seg = get16 ();
14886     }
14887   else
14888     {
14889       offset = get16 ();
14890       seg = get16 ();
14891     }
14892   used_prefixes |= (prefixes & PREFIX_DATA);
14893   if (intel_syntax)
14894     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14895   else
14896     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14897   oappend (scratchbuf);
14898 }
14899
14900 static void
14901 OP_OFF (int bytemode, int sizeflag)
14902 {
14903   bfd_vma off;
14904
14905   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14906     intel_operand_size (bytemode, sizeflag);
14907   append_seg ();
14908
14909   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14910     off = get32 ();
14911   else
14912     off = get16 ();
14913
14914   if (intel_syntax)
14915     {
14916       if (!active_seg_prefix)
14917         {
14918           oappend (names_seg[ds_reg - es_reg]);
14919           oappend (":");
14920         }
14921     }
14922   print_operand_value (scratchbuf, 1, off);
14923   oappend (scratchbuf);
14924 }
14925
14926 static void
14927 OP_OFF64 (int bytemode, int sizeflag)
14928 {
14929   bfd_vma off;
14930
14931   if (address_mode != mode_64bit
14932       || (prefixes & PREFIX_ADDR))
14933     {
14934       OP_OFF (bytemode, sizeflag);
14935       return;
14936     }
14937
14938   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14939     intel_operand_size (bytemode, sizeflag);
14940   append_seg ();
14941
14942   off = get64 ();
14943
14944   if (intel_syntax)
14945     {
14946       if (!active_seg_prefix)
14947         {
14948           oappend (names_seg[ds_reg - es_reg]);
14949           oappend (":");
14950         }
14951     }
14952   print_operand_value (scratchbuf, 1, off);
14953   oappend (scratchbuf);
14954 }
14955
14956 static void
14957 ptr_reg (int code, int sizeflag)
14958 {
14959   const char *s;
14960
14961   *obufp++ = open_char;
14962   used_prefixes |= (prefixes & PREFIX_ADDR);
14963   if (address_mode == mode_64bit)
14964     {
14965       if (!(sizeflag & AFLAG))
14966         s = names32[code - eAX_reg];
14967       else
14968         s = names64[code - eAX_reg];
14969     }
14970   else if (sizeflag & AFLAG)
14971     s = names32[code - eAX_reg];
14972   else
14973     s = names16[code - eAX_reg];
14974   oappend (s);
14975   *obufp++ = close_char;
14976   *obufp = 0;
14977 }
14978
14979 static void
14980 OP_ESreg (int code, int sizeflag)
14981 {
14982   if (intel_syntax)
14983     {
14984       switch (codep[-1])
14985         {
14986         case 0x6d:      /* insw/insl */
14987           intel_operand_size (z_mode, sizeflag);
14988           break;
14989         case 0xa5:      /* movsw/movsl/movsq */
14990         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14991         case 0xab:      /* stosw/stosl */
14992         case 0xaf:      /* scasw/scasl */
14993           intel_operand_size (v_mode, sizeflag);
14994           break;
14995         default:
14996           intel_operand_size (b_mode, sizeflag);
14997         }
14998     }
14999   oappend_maybe_intel ("%es:");
15000   ptr_reg (code, sizeflag);
15001 }
15002
15003 static void
15004 OP_DSreg (int code, int sizeflag)
15005 {
15006   if (intel_syntax)
15007     {
15008       switch (codep[-1])
15009         {
15010         case 0x6f:      /* outsw/outsl */
15011           intel_operand_size (z_mode, sizeflag);
15012           break;
15013         case 0xa5:      /* movsw/movsl/movsq */
15014         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15015         case 0xad:      /* lodsw/lodsl/lodsq */
15016           intel_operand_size (v_mode, sizeflag);
15017           break;
15018         default:
15019           intel_operand_size (b_mode, sizeflag);
15020         }
15021     }
15022   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15023      default segment register DS is printed.  */
15024   if (!active_seg_prefix)
15025     active_seg_prefix = PREFIX_DS;
15026   append_seg ();
15027   ptr_reg (code, sizeflag);
15028 }
15029
15030 static void
15031 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15032 {
15033   int add;
15034   if (rex & REX_R)
15035     {
15036       USED_REX (REX_R);
15037       add = 8;
15038     }
15039   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15040     {
15041       all_prefixes[last_lock_prefix] = 0;
15042       used_prefixes |= PREFIX_LOCK;
15043       add = 8;
15044     }
15045   else
15046     add = 0;
15047   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15048   oappend_maybe_intel (scratchbuf);
15049 }
15050
15051 static void
15052 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15053 {
15054   int add;
15055   USED_REX (REX_R);
15056   if (rex & REX_R)
15057     add = 8;
15058   else
15059     add = 0;
15060   if (intel_syntax)
15061     sprintf (scratchbuf, "db%d", modrm.reg + add);
15062   else
15063     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15064   oappend (scratchbuf);
15065 }
15066
15067 static void
15068 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15069 {
15070   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15071   oappend_maybe_intel (scratchbuf);
15072 }
15073
15074 static void
15075 OP_R (int bytemode, int sizeflag)
15076 {
15077   /* Skip mod/rm byte.  */
15078   MODRM_CHECK;
15079   codep++;
15080   OP_E_register (bytemode, sizeflag);
15081 }
15082
15083 static void
15084 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15085 {
15086   int reg = modrm.reg;
15087   const char **names;
15088
15089   used_prefixes |= (prefixes & PREFIX_DATA);
15090   if (prefixes & PREFIX_DATA)
15091     {
15092       names = names_xmm;
15093       USED_REX (REX_R);
15094       if (rex & REX_R)
15095         reg += 8;
15096     }
15097   else
15098     names = names_mm;
15099   oappend (names[reg]);
15100 }
15101
15102 static void
15103 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15104 {
15105   int reg = modrm.reg;
15106   const char **names;
15107
15108   USED_REX (REX_R);
15109   if (rex & REX_R)
15110     reg += 8;
15111   if (vex.evex)
15112     {
15113       if (!vex.r)
15114         reg += 16;
15115     }
15116
15117   if (need_vex
15118       && bytemode != xmm_mode
15119       && bytemode != xmmq_mode
15120       && bytemode != evex_half_bcst_xmmq_mode
15121       && bytemode != ymm_mode
15122       && bytemode != scalar_mode)
15123     {
15124       switch (vex.length)
15125         {
15126         case 128:
15127           names = names_xmm;
15128           break;
15129         case 256:
15130           if (vex.w
15131               || (bytemode != vex_vsib_q_w_dq_mode
15132                   && bytemode != vex_vsib_q_w_d_mode))
15133             names = names_ymm;
15134           else
15135             names = names_xmm;
15136           break;
15137         case 512:
15138           names = names_zmm;
15139           break;
15140         default:
15141           abort ();
15142         }
15143     }
15144   else if (bytemode == xmmq_mode
15145            || bytemode == evex_half_bcst_xmmq_mode)
15146     {
15147       switch (vex.length)
15148         {
15149         case 128:
15150         case 256:
15151           names = names_xmm;
15152           break;
15153         case 512:
15154           names = names_ymm;
15155           break;
15156         default:
15157           abort ();
15158         }
15159     }
15160   else if (bytemode == ymm_mode)
15161     names = names_ymm;
15162   else
15163     names = names_xmm;
15164   oappend (names[reg]);
15165 }
15166
15167 static void
15168 OP_EM (int bytemode, int sizeflag)
15169 {
15170   int reg;
15171   const char **names;
15172
15173   if (modrm.mod != 3)
15174     {
15175       if (intel_syntax
15176           && (bytemode == v_mode || bytemode == v_swap_mode))
15177         {
15178           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15179           used_prefixes |= (prefixes & PREFIX_DATA);
15180         }
15181       OP_E (bytemode, sizeflag);
15182       return;
15183     }
15184
15185   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15186     swap_operand ();
15187
15188   /* Skip mod/rm byte.  */
15189   MODRM_CHECK;
15190   codep++;
15191   used_prefixes |= (prefixes & PREFIX_DATA);
15192   reg = modrm.rm;
15193   if (prefixes & PREFIX_DATA)
15194     {
15195       names = names_xmm;
15196       USED_REX (REX_B);
15197       if (rex & REX_B)
15198         reg += 8;
15199     }
15200   else
15201     names = names_mm;
15202   oappend (names[reg]);
15203 }
15204
15205 /* cvt* are the only instructions in sse2 which have
15206    both SSE and MMX operands and also have 0x66 prefix
15207    in their opcode. 0x66 was originally used to differentiate
15208    between SSE and MMX instruction(operands). So we have to handle the
15209    cvt* separately using OP_EMC and OP_MXC */
15210 static void
15211 OP_EMC (int bytemode, int sizeflag)
15212 {
15213   if (modrm.mod != 3)
15214     {
15215       if (intel_syntax && bytemode == v_mode)
15216         {
15217           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15218           used_prefixes |= (prefixes & PREFIX_DATA);
15219         }
15220       OP_E (bytemode, sizeflag);
15221       return;
15222     }
15223
15224   /* Skip mod/rm byte.  */
15225   MODRM_CHECK;
15226   codep++;
15227   used_prefixes |= (prefixes & PREFIX_DATA);
15228   oappend (names_mm[modrm.rm]);
15229 }
15230
15231 static void
15232 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15233 {
15234   used_prefixes |= (prefixes & PREFIX_DATA);
15235   oappend (names_mm[modrm.reg]);
15236 }
15237
15238 static void
15239 OP_EX (int bytemode, int sizeflag)
15240 {
15241   int reg;
15242   const char **names;
15243
15244   /* Skip mod/rm byte.  */
15245   MODRM_CHECK;
15246   codep++;
15247
15248   if (modrm.mod != 3)
15249     {
15250       OP_E_memory (bytemode, sizeflag);
15251       return;
15252     }
15253
15254   reg = modrm.rm;
15255   USED_REX (REX_B);
15256   if (rex & REX_B)
15257     reg += 8;
15258   if (vex.evex)
15259     {
15260       USED_REX (REX_X);
15261       if ((rex & REX_X))
15262         reg += 16;
15263     }
15264
15265   if ((sizeflag & SUFFIX_ALWAYS)
15266       && (bytemode == x_swap_mode
15267           || bytemode == d_swap_mode
15268           || bytemode == d_scalar_swap_mode
15269           || bytemode == q_swap_mode
15270           || bytemode == q_scalar_swap_mode))
15271     swap_operand ();
15272
15273   if (need_vex
15274       && bytemode != xmm_mode
15275       && bytemode != xmmdw_mode
15276       && bytemode != xmmqd_mode
15277       && bytemode != xmm_mb_mode
15278       && bytemode != xmm_mw_mode
15279       && bytemode != xmm_md_mode
15280       && bytemode != xmm_mq_mode
15281       && bytemode != xmm_mdq_mode
15282       && bytemode != xmmq_mode
15283       && bytemode != evex_half_bcst_xmmq_mode
15284       && bytemode != ymm_mode
15285       && bytemode != d_scalar_mode
15286       && bytemode != d_scalar_swap_mode
15287       && bytemode != q_scalar_mode
15288       && bytemode != q_scalar_swap_mode
15289       && bytemode != vex_scalar_w_dq_mode)
15290     {
15291       switch (vex.length)
15292         {
15293         case 128:
15294           names = names_xmm;
15295           break;
15296         case 256:
15297           names = names_ymm;
15298           break;
15299         case 512:
15300           names = names_zmm;
15301           break;
15302         default:
15303           abort ();
15304         }
15305     }
15306   else if (bytemode == xmmq_mode
15307            || bytemode == evex_half_bcst_xmmq_mode)
15308     {
15309       switch (vex.length)
15310         {
15311         case 128:
15312         case 256:
15313           names = names_xmm;
15314           break;
15315         case 512:
15316           names = names_ymm;
15317           break;
15318         default:
15319           abort ();
15320         }
15321     }
15322   else if (bytemode == ymm_mode)
15323     names = names_ymm;
15324   else
15325     names = names_xmm;
15326   oappend (names[reg]);
15327 }
15328
15329 static void
15330 OP_MS (int bytemode, int sizeflag)
15331 {
15332   if (modrm.mod == 3)
15333     OP_EM (bytemode, sizeflag);
15334   else
15335     BadOp ();
15336 }
15337
15338 static void
15339 OP_XS (int bytemode, int sizeflag)
15340 {
15341   if (modrm.mod == 3)
15342     OP_EX (bytemode, sizeflag);
15343   else
15344     BadOp ();
15345 }
15346
15347 static void
15348 OP_M (int bytemode, int sizeflag)
15349 {
15350   if (modrm.mod == 3)
15351     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15352     BadOp ();
15353   else
15354     OP_E (bytemode, sizeflag);
15355 }
15356
15357 static void
15358 OP_0f07 (int bytemode, int sizeflag)
15359 {
15360   if (modrm.mod != 3 || modrm.rm != 0)
15361     BadOp ();
15362   else
15363     OP_E (bytemode, sizeflag);
15364 }
15365
15366 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15367    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15368
15369 static void
15370 NOP_Fixup1 (int bytemode, int sizeflag)
15371 {
15372   if ((prefixes & PREFIX_DATA) != 0
15373       || (rex != 0
15374           && rex != 0x48
15375           && address_mode == mode_64bit))
15376     OP_REG (bytemode, sizeflag);
15377   else
15378     strcpy (obuf, "nop");
15379 }
15380
15381 static void
15382 NOP_Fixup2 (int bytemode, int sizeflag)
15383 {
15384   if ((prefixes & PREFIX_DATA) != 0
15385       || (rex != 0
15386           && rex != 0x48
15387           && address_mode == mode_64bit))
15388     OP_IMREG (bytemode, sizeflag);
15389 }
15390
15391 static const char *const Suffix3DNow[] = {
15392 /* 00 */        NULL,           NULL,           NULL,           NULL,
15393 /* 04 */        NULL,           NULL,           NULL,           NULL,
15394 /* 08 */        NULL,           NULL,           NULL,           NULL,
15395 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15396 /* 10 */        NULL,           NULL,           NULL,           NULL,
15397 /* 14 */        NULL,           NULL,           NULL,           NULL,
15398 /* 18 */        NULL,           NULL,           NULL,           NULL,
15399 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15400 /* 20 */        NULL,           NULL,           NULL,           NULL,
15401 /* 24 */        NULL,           NULL,           NULL,           NULL,
15402 /* 28 */        NULL,           NULL,           NULL,           NULL,
15403 /* 2C */        NULL,           NULL,           NULL,           NULL,
15404 /* 30 */        NULL,           NULL,           NULL,           NULL,
15405 /* 34 */        NULL,           NULL,           NULL,           NULL,
15406 /* 38 */        NULL,           NULL,           NULL,           NULL,
15407 /* 3C */        NULL,           NULL,           NULL,           NULL,
15408 /* 40 */        NULL,           NULL,           NULL,           NULL,
15409 /* 44 */        NULL,           NULL,           NULL,           NULL,
15410 /* 48 */        NULL,           NULL,           NULL,           NULL,
15411 /* 4C */        NULL,           NULL,           NULL,           NULL,
15412 /* 50 */        NULL,           NULL,           NULL,           NULL,
15413 /* 54 */        NULL,           NULL,           NULL,           NULL,
15414 /* 58 */        NULL,           NULL,           NULL,           NULL,
15415 /* 5C */        NULL,           NULL,           NULL,           NULL,
15416 /* 60 */        NULL,           NULL,           NULL,           NULL,
15417 /* 64 */        NULL,           NULL,           NULL,           NULL,
15418 /* 68 */        NULL,           NULL,           NULL,           NULL,
15419 /* 6C */        NULL,           NULL,           NULL,           NULL,
15420 /* 70 */        NULL,           NULL,           NULL,           NULL,
15421 /* 74 */        NULL,           NULL,           NULL,           NULL,
15422 /* 78 */        NULL,           NULL,           NULL,           NULL,
15423 /* 7C */        NULL,           NULL,           NULL,           NULL,
15424 /* 80 */        NULL,           NULL,           NULL,           NULL,
15425 /* 84 */        NULL,           NULL,           NULL,           NULL,
15426 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15427 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15428 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15429 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15430 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15431 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15432 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15433 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15434 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15435 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15436 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15437 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15438 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15439 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15440 /* C0 */        NULL,           NULL,           NULL,           NULL,
15441 /* C4 */        NULL,           NULL,           NULL,           NULL,
15442 /* C8 */        NULL,           NULL,           NULL,           NULL,
15443 /* CC */        NULL,           NULL,           NULL,           NULL,
15444 /* D0 */        NULL,           NULL,           NULL,           NULL,
15445 /* D4 */        NULL,           NULL,           NULL,           NULL,
15446 /* D8 */        NULL,           NULL,           NULL,           NULL,
15447 /* DC */        NULL,           NULL,           NULL,           NULL,
15448 /* E0 */        NULL,           NULL,           NULL,           NULL,
15449 /* E4 */        NULL,           NULL,           NULL,           NULL,
15450 /* E8 */        NULL,           NULL,           NULL,           NULL,
15451 /* EC */        NULL,           NULL,           NULL,           NULL,
15452 /* F0 */        NULL,           NULL,           NULL,           NULL,
15453 /* F4 */        NULL,           NULL,           NULL,           NULL,
15454 /* F8 */        NULL,           NULL,           NULL,           NULL,
15455 /* FC */        NULL,           NULL,           NULL,           NULL,
15456 };
15457
15458 static void
15459 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15460 {
15461   const char *mnemonic;
15462
15463   FETCH_DATA (the_info, codep + 1);
15464   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15465      place where an 8-bit immediate would normally go.  ie. the last
15466      byte of the instruction.  */
15467   obufp = mnemonicendp;
15468   mnemonic = Suffix3DNow[*codep++ & 0xff];
15469   if (mnemonic)
15470     oappend (mnemonic);
15471   else
15472     {
15473       /* Since a variable sized modrm/sib chunk is between the start
15474          of the opcode (0x0f0f) and the opcode suffix, we need to do
15475          all the modrm processing first, and don't know until now that
15476          we have a bad opcode.  This necessitates some cleaning up.  */
15477       op_out[0][0] = '\0';
15478       op_out[1][0] = '\0';
15479       BadOp ();
15480     }
15481   mnemonicendp = obufp;
15482 }
15483
15484 static struct op simd_cmp_op[] =
15485 {
15486   { STRING_COMMA_LEN ("eq") },
15487   { STRING_COMMA_LEN ("lt") },
15488   { STRING_COMMA_LEN ("le") },
15489   { STRING_COMMA_LEN ("unord") },
15490   { STRING_COMMA_LEN ("neq") },
15491   { STRING_COMMA_LEN ("nlt") },
15492   { STRING_COMMA_LEN ("nle") },
15493   { STRING_COMMA_LEN ("ord") }
15494 };
15495
15496 static void
15497 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15498 {
15499   unsigned int cmp_type;
15500
15501   FETCH_DATA (the_info, codep + 1);
15502   cmp_type = *codep++ & 0xff;
15503   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15504     {
15505       char suffix [3];
15506       char *p = mnemonicendp - 2;
15507       suffix[0] = p[0];
15508       suffix[1] = p[1];
15509       suffix[2] = '\0';
15510       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15511       mnemonicendp += simd_cmp_op[cmp_type].len;
15512     }
15513   else
15514     {
15515       /* We have a reserved extension byte.  Output it directly.  */
15516       scratchbuf[0] = '$';
15517       print_operand_value (scratchbuf + 1, 1, cmp_type);
15518       oappend_maybe_intel (scratchbuf);
15519       scratchbuf[0] = '\0';
15520     }
15521 }
15522
15523 static void
15524 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15525 {
15526   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15527   if (!intel_syntax)
15528     {
15529       strcpy (op_out[0], names32[0]);
15530       strcpy (op_out[1], names32[1]);
15531       if (bytemode == eBX_reg)
15532         strcpy (op_out[2], names32[3]);
15533       two_source_ops = 1;
15534     }
15535   /* Skip mod/rm byte.  */
15536   MODRM_CHECK;
15537   codep++;
15538 }
15539
15540 static void
15541 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15542             int sizeflag ATTRIBUTE_UNUSED)
15543 {
15544   /* monitor %{e,r,}ax,%ecx,%edx"  */
15545   if (!intel_syntax)
15546     {
15547       const char **names = (address_mode == mode_64bit
15548                             ? names64 : names32);
15549
15550       if (prefixes & PREFIX_ADDR)
15551         {
15552           /* Remove "addr16/addr32".  */
15553           all_prefixes[last_addr_prefix] = 0;
15554           names = (address_mode != mode_32bit
15555                    ? names32 : names16);
15556           used_prefixes |= PREFIX_ADDR;
15557         }
15558       else if (address_mode == mode_16bit)
15559         names = names16;
15560       strcpy (op_out[0], names[0]);
15561       strcpy (op_out[1], names32[1]);
15562       strcpy (op_out[2], names32[2]);
15563       two_source_ops = 1;
15564     }
15565   /* Skip mod/rm byte.  */
15566   MODRM_CHECK;
15567   codep++;
15568 }
15569
15570 static void
15571 BadOp (void)
15572 {
15573   /* Throw away prefixes and 1st. opcode byte.  */
15574   codep = insn_codep + 1;
15575   oappend ("(bad)");
15576 }
15577
15578 static void
15579 REP_Fixup (int bytemode, int sizeflag)
15580 {
15581   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15582      lods and stos.  */
15583   if (prefixes & PREFIX_REPZ)
15584     all_prefixes[last_repz_prefix] = REP_PREFIX;
15585
15586   switch (bytemode)
15587     {
15588     case al_reg:
15589     case eAX_reg:
15590     case indir_dx_reg:
15591       OP_IMREG (bytemode, sizeflag);
15592       break;
15593     case eDI_reg:
15594       OP_ESreg (bytemode, sizeflag);
15595       break;
15596     case eSI_reg:
15597       OP_DSreg (bytemode, sizeflag);
15598       break;
15599     default:
15600       abort ();
15601       break;
15602     }
15603 }
15604
15605 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15606    "bnd".  */
15607
15608 static void
15609 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15610 {
15611   if (prefixes & PREFIX_REPNZ)
15612     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15613 }
15614
15615 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15616    "notrack".  */
15617
15618 static void
15619 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15620                int sizeflag ATTRIBUTE_UNUSED)
15621 {
15622   if (active_seg_prefix == PREFIX_DS
15623       && (address_mode != mode_64bit || last_data_prefix < 0))
15624     {
15625       /* NOTRACK prefix is only valid on indirect branch instructions.
15626          NB: DATA prefix is unsupported for Intel64.  */
15627       active_seg_prefix = 0;
15628       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15629     }
15630 }
15631
15632 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15633    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15634  */
15635
15636 static void
15637 HLE_Fixup1 (int bytemode, int sizeflag)
15638 {
15639   if (modrm.mod != 3
15640       && (prefixes & PREFIX_LOCK) != 0)
15641     {
15642       if (prefixes & PREFIX_REPZ)
15643         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15644       if (prefixes & PREFIX_REPNZ)
15645         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15646     }
15647
15648   OP_E (bytemode, sizeflag);
15649 }
15650
15651 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15652    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15653  */
15654
15655 static void
15656 HLE_Fixup2 (int bytemode, int sizeflag)
15657 {
15658   if (modrm.mod != 3)
15659     {
15660       if (prefixes & PREFIX_REPZ)
15661         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15662       if (prefixes & PREFIX_REPNZ)
15663         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15664     }
15665
15666   OP_E (bytemode, sizeflag);
15667 }
15668
15669 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15670    "xrelease" for memory operand.  No check for LOCK prefix.   */
15671
15672 static void
15673 HLE_Fixup3 (int bytemode, int sizeflag)
15674 {
15675   if (modrm.mod != 3
15676       && last_repz_prefix > last_repnz_prefix
15677       && (prefixes & PREFIX_REPZ) != 0)
15678     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15679
15680   OP_E (bytemode, sizeflag);
15681 }
15682
15683 static void
15684 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15685 {
15686   USED_REX (REX_W);
15687   if (rex & REX_W)
15688     {
15689       /* Change cmpxchg8b to cmpxchg16b.  */
15690       char *p = mnemonicendp - 2;
15691       mnemonicendp = stpcpy (p, "16b");
15692       bytemode = o_mode;
15693     }
15694   else if ((prefixes & PREFIX_LOCK) != 0)
15695     {
15696       if (prefixes & PREFIX_REPZ)
15697         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15698       if (prefixes & PREFIX_REPNZ)
15699         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15700     }
15701
15702   OP_M (bytemode, sizeflag);
15703 }
15704
15705 static void
15706 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15707 {
15708   const char **names;
15709
15710   if (need_vex)
15711     {
15712       switch (vex.length)
15713         {
15714         case 128:
15715           names = names_xmm;
15716           break;
15717         case 256:
15718           names = names_ymm;
15719           break;
15720         default:
15721           abort ();
15722         }
15723     }
15724   else
15725     names = names_xmm;
15726   oappend (names[reg]);
15727 }
15728
15729 static void
15730 CRC32_Fixup (int bytemode, int sizeflag)
15731 {
15732   /* Add proper suffix to "crc32".  */
15733   char *p = mnemonicendp;
15734
15735   switch (bytemode)
15736     {
15737     case b_mode:
15738       if (intel_syntax)
15739         goto skip;
15740
15741       *p++ = 'b';
15742       break;
15743     case v_mode:
15744       if (intel_syntax)
15745         goto skip;
15746
15747       USED_REX (REX_W);
15748       if (rex & REX_W)
15749         *p++ = 'q';
15750       else
15751         {
15752           if (sizeflag & DFLAG)
15753             *p++ = 'l';
15754           else
15755             *p++ = 'w';
15756           used_prefixes |= (prefixes & PREFIX_DATA);
15757         }
15758       break;
15759     default:
15760       oappend (INTERNAL_DISASSEMBLER_ERROR);
15761       break;
15762     }
15763   mnemonicendp = p;
15764   *p = '\0';
15765
15766 skip:
15767   if (modrm.mod == 3)
15768     {
15769       int add;
15770
15771       /* Skip mod/rm byte.  */
15772       MODRM_CHECK;
15773       codep++;
15774
15775       USED_REX (REX_B);
15776       add = (rex & REX_B) ? 8 : 0;
15777       if (bytemode == b_mode)
15778         {
15779           USED_REX (0);
15780           if (rex)
15781             oappend (names8rex[modrm.rm + add]);
15782           else
15783             oappend (names8[modrm.rm + add]);
15784         }
15785       else
15786         {
15787           USED_REX (REX_W);
15788           if (rex & REX_W)
15789             oappend (names64[modrm.rm + add]);
15790           else if ((prefixes & PREFIX_DATA))
15791             oappend (names16[modrm.rm + add]);
15792           else
15793             oappend (names32[modrm.rm + add]);
15794         }
15795     }
15796   else
15797     OP_E (bytemode, sizeflag);
15798 }
15799
15800 static void
15801 FXSAVE_Fixup (int bytemode, int sizeflag)
15802 {
15803   /* Add proper suffix to "fxsave" and "fxrstor".  */
15804   USED_REX (REX_W);
15805   if (rex & REX_W)
15806     {
15807       char *p = mnemonicendp;
15808       *p++ = '6';
15809       *p++ = '4';
15810       *p = '\0';
15811       mnemonicendp = p;
15812     }
15813   OP_M (bytemode, sizeflag);
15814 }
15815
15816 static void
15817 PCMPESTR_Fixup (int bytemode, int sizeflag)
15818 {
15819   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15820   if (!intel_syntax)
15821     {
15822       char *p = mnemonicendp;
15823
15824       USED_REX (REX_W);
15825       if (rex & REX_W)
15826         *p++ = 'q';
15827       else if (sizeflag & SUFFIX_ALWAYS)
15828         *p++ = 'l';
15829
15830       *p = '\0';
15831       mnemonicendp = p;
15832     }
15833
15834   OP_EX (bytemode, sizeflag);
15835 }
15836
15837 /* Display the destination register operand for instructions with
15838    VEX. */
15839
15840 static void
15841 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15842 {
15843   int reg;
15844   const char **names;
15845
15846   if (!need_vex)
15847     abort ();
15848
15849   if (!need_vex_reg)
15850     return;
15851
15852   reg = vex.register_specifier;
15853   vex.register_specifier = 0;
15854   if (address_mode != mode_64bit)
15855     reg &= 7;
15856   else if (vex.evex && !vex.v)
15857     reg += 16;
15858
15859   if (bytemode == vex_scalar_mode)
15860     {
15861       oappend (names_xmm[reg]);
15862       return;
15863     }
15864
15865   switch (vex.length)
15866     {
15867     case 128:
15868       switch (bytemode)
15869         {
15870         case vex_mode:
15871         case vex128_mode:
15872         case vex_vsib_q_w_dq_mode:
15873         case vex_vsib_q_w_d_mode:
15874           names = names_xmm;
15875           break;
15876         case dq_mode:
15877           if (rex & REX_W)
15878             names = names64;
15879           else
15880             names = names32;
15881           break;
15882         case mask_bd_mode:
15883         case mask_mode:
15884           if (reg > 0x7)
15885             {
15886               oappend ("(bad)");
15887               return;
15888             }
15889           names = names_mask;
15890           break;
15891         default:
15892           abort ();
15893           return;
15894         }
15895       break;
15896     case 256:
15897       switch (bytemode)
15898         {
15899         case vex_mode:
15900         case vex256_mode:
15901           names = names_ymm;
15902           break;
15903         case vex_vsib_q_w_dq_mode:
15904         case vex_vsib_q_w_d_mode:
15905           names = vex.w ? names_ymm : names_xmm;
15906           break;
15907         case mask_bd_mode:
15908         case mask_mode:
15909           if (reg > 0x7)
15910             {
15911               oappend ("(bad)");
15912               return;
15913             }
15914           names = names_mask;
15915           break;
15916         default:
15917           /* See PR binutils/20893 for a reproducer.  */
15918           oappend ("(bad)");
15919           return;
15920         }
15921       break;
15922     case 512:
15923       names = names_zmm;
15924       break;
15925     default:
15926       abort ();
15927       break;
15928     }
15929   oappend (names[reg]);
15930 }
15931
15932 /* Get the VEX immediate byte without moving codep.  */
15933
15934 static unsigned char
15935 get_vex_imm8 (int sizeflag, int opnum)
15936 {
15937   int bytes_before_imm = 0;
15938
15939   if (modrm.mod != 3)
15940     {
15941       /* There are SIB/displacement bytes.  */
15942       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15943         {
15944           /* 32/64 bit address mode */
15945           int base = modrm.rm;
15946
15947           /* Check SIB byte.  */
15948           if (base == 4)
15949             {
15950               FETCH_DATA (the_info, codep + 1);
15951               base = *codep & 7;
15952               /* When decoding the third source, don't increase
15953                  bytes_before_imm as this has already been incremented
15954                  by one in OP_E_memory while decoding the second
15955                  source operand.  */
15956               if (opnum == 0)
15957                 bytes_before_imm++;
15958             }
15959
15960           /* Don't increase bytes_before_imm when decoding the third source,
15961              it has already been incremented by OP_E_memory while decoding
15962              the second source operand.  */
15963           if (opnum == 0)
15964             {
15965               switch (modrm.mod)
15966                 {
15967                   case 0:
15968                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
15969                        SIB == 5, there is a 4 byte displacement.  */
15970                     if (base != 5)
15971                       /* No displacement. */
15972                       break;
15973                     /* Fall through.  */
15974                   case 2:
15975                     /* 4 byte displacement.  */
15976                     bytes_before_imm += 4;
15977                     break;
15978                   case 1:
15979                     /* 1 byte displacement.  */
15980                     bytes_before_imm++;
15981                     break;
15982                 }
15983             }
15984         }
15985       else
15986         {
15987           /* 16 bit address mode */
15988           /* Don't increase bytes_before_imm when decoding the third source,
15989              it has already been incremented by OP_E_memory while decoding
15990              the second source operand.  */
15991           if (opnum == 0)
15992             {
15993               switch (modrm.mod)
15994                 {
15995                 case 0:
15996                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
15997                   if (modrm.rm != 6)
15998                     /* No displacement. */
15999                     break;
16000                   /* Fall through.  */
16001                 case 2:
16002                   /* 2 byte displacement.  */
16003                   bytes_before_imm += 2;
16004                   break;
16005                 case 1:
16006                   /* 1 byte displacement: when decoding the third source,
16007                      don't increase bytes_before_imm as this has already
16008                      been incremented by one in OP_E_memory while decoding
16009                      the second source operand.  */
16010                   if (opnum == 0)
16011                     bytes_before_imm++;
16012
16013                   break;
16014                 }
16015             }
16016         }
16017     }
16018
16019   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16020   return codep [bytes_before_imm];
16021 }
16022
16023 static void
16024 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16025 {
16026   const char **names;
16027
16028   if (reg == -1 && modrm.mod != 3)
16029     {
16030       OP_E_memory (bytemode, sizeflag);
16031       return;
16032     }
16033   else
16034     {
16035       if (reg == -1)
16036         {
16037           reg = modrm.rm;
16038           USED_REX (REX_B);
16039           if (rex & REX_B)
16040             reg += 8;
16041         }
16042       if (address_mode != mode_64bit)
16043         reg &= 7;
16044     }
16045
16046   switch (vex.length)
16047     {
16048     case 128:
16049       names = names_xmm;
16050       break;
16051     case 256:
16052       names = names_ymm;
16053       break;
16054     default:
16055       abort ();
16056     }
16057   oappend (names[reg]);
16058 }
16059
16060 static void
16061 OP_EX_VexImmW (int bytemode, int sizeflag)
16062 {
16063   int reg = -1;
16064   static unsigned char vex_imm8;
16065
16066   if (vex_w_done == 0)
16067     {
16068       vex_w_done = 1;
16069
16070       /* Skip mod/rm byte.  */
16071       MODRM_CHECK;
16072       codep++;
16073
16074       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16075
16076       if (vex.w)
16077           reg = vex_imm8 >> 4;
16078
16079       OP_EX_VexReg (bytemode, sizeflag, reg);
16080     }
16081   else if (vex_w_done == 1)
16082     {
16083       vex_w_done = 2;
16084
16085       if (!vex.w)
16086           reg = vex_imm8 >> 4;
16087
16088       OP_EX_VexReg (bytemode, sizeflag, reg);
16089     }
16090   else
16091     {
16092       /* Output the imm8 directly.  */
16093       scratchbuf[0] = '$';
16094       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16095       oappend_maybe_intel (scratchbuf);
16096       scratchbuf[0] = '\0';
16097       codep++;
16098     }
16099 }
16100
16101 static void
16102 OP_Vex_2src (int bytemode, int sizeflag)
16103 {
16104   if (modrm.mod == 3)
16105     {
16106       int reg = modrm.rm;
16107       USED_REX (REX_B);
16108       if (rex & REX_B)
16109         reg += 8;
16110       oappend (names_xmm[reg]);
16111     }
16112   else
16113     {
16114       if (intel_syntax
16115           && (bytemode == v_mode || bytemode == v_swap_mode))
16116         {
16117           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16118           used_prefixes |= (prefixes & PREFIX_DATA);
16119         }
16120       OP_E (bytemode, sizeflag);
16121     }
16122 }
16123
16124 static void
16125 OP_Vex_2src_1 (int bytemode, int sizeflag)
16126 {
16127   if (modrm.mod == 3)
16128     {
16129       /* Skip mod/rm byte.   */
16130       MODRM_CHECK;
16131       codep++;
16132     }
16133
16134   if (vex.w)
16135     {
16136       unsigned int reg = vex.register_specifier;
16137       vex.register_specifier = 0;
16138
16139       if (address_mode != mode_64bit)
16140         reg &= 7;
16141       oappend (names_xmm[reg]);
16142     }
16143   else
16144     OP_Vex_2src (bytemode, sizeflag);
16145 }
16146
16147 static void
16148 OP_Vex_2src_2 (int bytemode, int sizeflag)
16149 {
16150   if (vex.w)
16151     OP_Vex_2src (bytemode, sizeflag);
16152   else
16153     {
16154       unsigned int reg = vex.register_specifier;
16155       vex.register_specifier = 0;
16156
16157       if (address_mode != mode_64bit)
16158         reg &= 7;
16159       oappend (names_xmm[reg]);
16160     }
16161 }
16162
16163 static void
16164 OP_EX_VexW (int bytemode, int sizeflag)
16165 {
16166   int reg = -1;
16167
16168   if (!vex_w_done)
16169     {
16170       /* Skip mod/rm byte.  */
16171       MODRM_CHECK;
16172       codep++;
16173
16174       if (vex.w)
16175         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16176     }
16177   else
16178     {
16179       if (!vex.w)
16180         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16181     }
16182
16183   OP_EX_VexReg (bytemode, sizeflag, reg);
16184
16185   if (vex_w_done)
16186     codep++;
16187   vex_w_done = 1;
16188 }
16189
16190 static void
16191 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16192 {
16193   int reg;
16194   const char **names;
16195
16196   FETCH_DATA (the_info, codep + 1);
16197   reg = *codep++;
16198
16199   if (bytemode != x_mode)
16200     abort ();
16201
16202   reg >>= 4;
16203   if (address_mode != mode_64bit)
16204     reg &= 7;
16205
16206   switch (vex.length)
16207     {
16208     case 128:
16209       names = names_xmm;
16210       break;
16211     case 256:
16212       names = names_ymm;
16213       break;
16214     default:
16215       abort ();
16216     }
16217   oappend (names[reg]);
16218 }
16219
16220 static void
16221 OP_XMM_VexW (int bytemode, int sizeflag)
16222 {
16223   /* Turn off the REX.W bit since it is used for swapping operands
16224      now.  */
16225   rex &= ~REX_W;
16226   OP_XMM (bytemode, sizeflag);
16227 }
16228
16229 static void
16230 OP_EX_Vex (int bytemode, int sizeflag)
16231 {
16232   if (modrm.mod != 3)
16233     need_vex_reg = 0;
16234   OP_EX (bytemode, sizeflag);
16235 }
16236
16237 static void
16238 OP_XMM_Vex (int bytemode, int sizeflag)
16239 {
16240   if (modrm.mod != 3)
16241     need_vex_reg = 0;
16242   OP_XMM (bytemode, sizeflag);
16243 }
16244
16245 static struct op vex_cmp_op[] =
16246 {
16247   { STRING_COMMA_LEN ("eq") },
16248   { STRING_COMMA_LEN ("lt") },
16249   { STRING_COMMA_LEN ("le") },
16250   { STRING_COMMA_LEN ("unord") },
16251   { STRING_COMMA_LEN ("neq") },
16252   { STRING_COMMA_LEN ("nlt") },
16253   { STRING_COMMA_LEN ("nle") },
16254   { STRING_COMMA_LEN ("ord") },
16255   { STRING_COMMA_LEN ("eq_uq") },
16256   { STRING_COMMA_LEN ("nge") },
16257   { STRING_COMMA_LEN ("ngt") },
16258   { STRING_COMMA_LEN ("false") },
16259   { STRING_COMMA_LEN ("neq_oq") },
16260   { STRING_COMMA_LEN ("ge") },
16261   { STRING_COMMA_LEN ("gt") },
16262   { STRING_COMMA_LEN ("true") },
16263   { STRING_COMMA_LEN ("eq_os") },
16264   { STRING_COMMA_LEN ("lt_oq") },
16265   { STRING_COMMA_LEN ("le_oq") },
16266   { STRING_COMMA_LEN ("unord_s") },
16267   { STRING_COMMA_LEN ("neq_us") },
16268   { STRING_COMMA_LEN ("nlt_uq") },
16269   { STRING_COMMA_LEN ("nle_uq") },
16270   { STRING_COMMA_LEN ("ord_s") },
16271   { STRING_COMMA_LEN ("eq_us") },
16272   { STRING_COMMA_LEN ("nge_uq") },
16273   { STRING_COMMA_LEN ("ngt_uq") },
16274   { STRING_COMMA_LEN ("false_os") },
16275   { STRING_COMMA_LEN ("neq_os") },
16276   { STRING_COMMA_LEN ("ge_oq") },
16277   { STRING_COMMA_LEN ("gt_oq") },
16278   { STRING_COMMA_LEN ("true_us") },
16279 };
16280
16281 static void
16282 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16283 {
16284   unsigned int cmp_type;
16285
16286   FETCH_DATA (the_info, codep + 1);
16287   cmp_type = *codep++ & 0xff;
16288   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16289     {
16290       char suffix [3];
16291       char *p = mnemonicendp - 2;
16292       suffix[0] = p[0];
16293       suffix[1] = p[1];
16294       suffix[2] = '\0';
16295       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16296       mnemonicendp += vex_cmp_op[cmp_type].len;
16297     }
16298   else
16299     {
16300       /* We have a reserved extension byte.  Output it directly.  */
16301       scratchbuf[0] = '$';
16302       print_operand_value (scratchbuf + 1, 1, cmp_type);
16303       oappend_maybe_intel (scratchbuf);
16304       scratchbuf[0] = '\0';
16305     }
16306 }
16307
16308 static void
16309 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16310              int sizeflag ATTRIBUTE_UNUSED)
16311 {
16312   unsigned int cmp_type;
16313
16314   if (!vex.evex)
16315     abort ();
16316
16317   FETCH_DATA (the_info, codep + 1);
16318   cmp_type = *codep++ & 0xff;
16319   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16320      If it's the case, print suffix, otherwise - print the immediate.  */
16321   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16322       && cmp_type != 3
16323       && cmp_type != 7)
16324     {
16325       char suffix [3];
16326       char *p = mnemonicendp - 2;
16327
16328       /* vpcmp* can have both one- and two-lettered suffix.  */
16329       if (p[0] == 'p')
16330         {
16331           p++;
16332           suffix[0] = p[0];
16333           suffix[1] = '\0';
16334         }
16335       else
16336         {
16337           suffix[0] = p[0];
16338           suffix[1] = p[1];
16339           suffix[2] = '\0';
16340         }
16341
16342       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16343       mnemonicendp += simd_cmp_op[cmp_type].len;
16344     }
16345   else
16346     {
16347       /* We have a reserved extension byte.  Output it directly.  */
16348       scratchbuf[0] = '$';
16349       print_operand_value (scratchbuf + 1, 1, cmp_type);
16350       oappend_maybe_intel (scratchbuf);
16351       scratchbuf[0] = '\0';
16352     }
16353 }
16354
16355 static const struct op xop_cmp_op[] =
16356 {
16357   { STRING_COMMA_LEN ("lt") },
16358   { STRING_COMMA_LEN ("le") },
16359   { STRING_COMMA_LEN ("gt") },
16360   { STRING_COMMA_LEN ("ge") },
16361   { STRING_COMMA_LEN ("eq") },
16362   { STRING_COMMA_LEN ("neq") },
16363   { STRING_COMMA_LEN ("false") },
16364   { STRING_COMMA_LEN ("true") }
16365 };
16366
16367 static void
16368 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16369              int sizeflag ATTRIBUTE_UNUSED)
16370 {
16371   unsigned int cmp_type;
16372
16373   FETCH_DATA (the_info, codep + 1);
16374   cmp_type = *codep++ & 0xff;
16375   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16376     {
16377       char suffix[3];
16378       char *p = mnemonicendp - 2;
16379
16380       /* vpcom* can have both one- and two-lettered suffix.  */
16381       if (p[0] == 'm')
16382         {
16383           p++;
16384           suffix[0] = p[0];
16385           suffix[1] = '\0';
16386         }
16387       else
16388         {
16389           suffix[0] = p[0];
16390           suffix[1] = p[1];
16391           suffix[2] = '\0';
16392         }
16393
16394       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16395       mnemonicendp += xop_cmp_op[cmp_type].len;
16396     }
16397   else
16398     {
16399       /* We have a reserved extension byte.  Output it directly.  */
16400       scratchbuf[0] = '$';
16401       print_operand_value (scratchbuf + 1, 1, cmp_type);
16402       oappend_maybe_intel (scratchbuf);
16403       scratchbuf[0] = '\0';
16404     }
16405 }
16406
16407 static const struct op pclmul_op[] =
16408 {
16409   { STRING_COMMA_LEN ("lql") },
16410   { STRING_COMMA_LEN ("hql") },
16411   { STRING_COMMA_LEN ("lqh") },
16412   { STRING_COMMA_LEN ("hqh") }
16413 };
16414
16415 static void
16416 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16417               int sizeflag ATTRIBUTE_UNUSED)
16418 {
16419   unsigned int pclmul_type;
16420
16421   FETCH_DATA (the_info, codep + 1);
16422   pclmul_type = *codep++ & 0xff;
16423   switch (pclmul_type)
16424     {
16425     case 0x10:
16426       pclmul_type = 2;
16427       break;
16428     case 0x11:
16429       pclmul_type = 3;
16430       break;
16431     default:
16432       break;
16433     }
16434   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16435     {
16436       char suffix [4];
16437       char *p = mnemonicendp - 3;
16438       suffix[0] = p[0];
16439       suffix[1] = p[1];
16440       suffix[2] = p[2];
16441       suffix[3] = '\0';
16442       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16443       mnemonicendp += pclmul_op[pclmul_type].len;
16444     }
16445   else
16446     {
16447       /* We have a reserved extension byte.  Output it directly.  */
16448       scratchbuf[0] = '$';
16449       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16450       oappend_maybe_intel (scratchbuf);
16451       scratchbuf[0] = '\0';
16452     }
16453 }
16454
16455 static void
16456 MOVBE_Fixup (int bytemode, int sizeflag)
16457 {
16458   /* Add proper suffix to "movbe".  */
16459   char *p = mnemonicendp;
16460
16461   switch (bytemode)
16462     {
16463     case v_mode:
16464       if (intel_syntax)
16465         goto skip;
16466
16467       USED_REX (REX_W);
16468       if (sizeflag & SUFFIX_ALWAYS)
16469         {
16470           if (rex & REX_W)
16471             *p++ = 'q';
16472           else
16473             {
16474               if (sizeflag & DFLAG)
16475                 *p++ = 'l';
16476               else
16477                 *p++ = 'w';
16478               used_prefixes |= (prefixes & PREFIX_DATA);
16479             }
16480         }
16481       break;
16482     default:
16483       oappend (INTERNAL_DISASSEMBLER_ERROR);
16484       break;
16485     }
16486   mnemonicendp = p;
16487   *p = '\0';
16488
16489 skip:
16490   OP_M (bytemode, sizeflag);
16491 }
16492
16493 static void
16494 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16495 {
16496   int reg;
16497   const char **names;
16498
16499   /* Skip mod/rm byte.  */
16500   MODRM_CHECK;
16501   codep++;
16502
16503   if (rex & REX_W)
16504     names = names64;
16505   else
16506     names = names32;
16507
16508   reg = modrm.rm;
16509   USED_REX (REX_B);
16510   if (rex & REX_B)
16511     reg += 8;
16512
16513   oappend (names[reg]);
16514 }
16515
16516 static void
16517 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16518 {
16519   const char **names;
16520   unsigned int reg = vex.register_specifier;
16521   vex.register_specifier = 0;
16522
16523   if (rex & REX_W)
16524     names = names64;
16525   else
16526     names = names32;
16527
16528   if (address_mode != mode_64bit)
16529     reg &= 7;
16530   oappend (names[reg]);
16531 }
16532
16533 static void
16534 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16535 {
16536   if (!vex.evex
16537       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16538     abort ();
16539
16540   USED_REX (REX_R);
16541   if ((rex & REX_R) != 0 || !vex.r)
16542     {
16543       BadOp ();
16544       return;
16545     }
16546
16547   oappend (names_mask [modrm.reg]);
16548 }
16549
16550 static void
16551 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16552 {
16553   if (!vex.evex
16554       || (bytemode != evex_rounding_mode
16555           && bytemode != evex_rounding_64_mode
16556           && bytemode != evex_sae_mode))
16557     abort ();
16558   if (modrm.mod == 3 && vex.b)
16559     switch (bytemode)
16560       {
16561       case evex_rounding_64_mode:
16562         if (address_mode != mode_64bit)
16563           {
16564             oappend ("(bad)");
16565             break;
16566           }
16567         /* Fall through.  */
16568       case evex_rounding_mode:
16569         oappend (names_rounding[vex.ll]);
16570         break;
16571       case evex_sae_mode:
16572         oappend ("{sae}");
16573         break;
16574       default:
16575         break;
16576       }
16577 }