opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void SEP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127 static void MOVSXD_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define EbndS { OP_E, bnd_swap_mode }
 252 #define Ev { OP_E, v_mode }
 253 #define Eva { OP_E, va_mode }
 254 #define Ev_bnd { OP_E, v_bnd_mode }
 255 #define EvS { OP_E, v_swap_mode }
 256 #define Ed { OP_E, d_mode }
 257 #define Edq { OP_E, dq_mode }
 258 #define Edqw { OP_E, dqw_mode }
 259 #define Edqb { OP_E, dqb_mode }
 260 #define Edb { OP_E, db_mode }
 261 #define Edw { OP_E, dw_mode }
 262 #define Edqd { OP_E, dqd_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iv64 { OP_I64, v_mode }
 296 #define Id { OP_I, d_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Jdqw { OP_J, dqw_mode }
 302 #define Cm { OP_C, m_mode }
 303 #define Dm { OP_D, m_mode }
 304 #define Td { OP_T, d_mode }
 305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 306
 307 #define RMeAX { OP_REG, eAX_reg }
 308 #define RMeBX { OP_REG, eBX_reg }
 309 #define RMeCX { OP_REG, eCX_reg }
 310 #define RMeDX { OP_REG, eDX_reg }
 311 #define RMeSP { OP_REG, eSP_reg }
 312 #define RMeBP { OP_REG, eBP_reg }
 313 #define RMeSI { OP_REG, eSI_reg }
 314 #define RMeDI { OP_REG, eDI_reg }
 315 #define RMrAX { OP_REG, rAX_reg }
 316 #define RMrBX { OP_REG, rBX_reg }
 317 #define RMrCX { OP_REG, rCX_reg }
 318 #define RMrDX { OP_REG, rDX_reg }
 319 #define RMrSP { OP_REG, rSP_reg }
 320 #define RMrBP { OP_REG, rBP_reg }
 321 #define RMrSI { OP_REG, rSI_reg }
 322 #define RMrDI { OP_REG, rDI_reg }
 323 #define RMAL { OP_REG, al_reg }
 324 #define RMCL { OP_REG, cl_reg }
 325 #define RMDL { OP_REG, dl_reg }
 326 #define RMBL { OP_REG, bl_reg }
 327 #define RMAH { OP_REG, ah_reg }
 328 #define RMCH { OP_REG, ch_reg }
 329 #define RMDH { OP_REG, dh_reg }
 330 #define RMBH { OP_REG, bh_reg }
 331 #define RMAX { OP_REG, ax_reg }
 332 #define RMDX { OP_REG, dx_reg }
 333
 334 #define eAX { OP_IMREG, eAX_reg }
 335 #define eBX { OP_IMREG, eBX_reg }
 336 #define eCX { OP_IMREG, eCX_reg }
 337 #define eDX { OP_IMREG, eDX_reg }
 338 #define eSP { OP_IMREG, eSP_reg }
 339 #define eBP { OP_IMREG, eBP_reg }
 340 #define eSI { OP_IMREG, eSI_reg }
 341 #define eDI { OP_IMREG, eDI_reg }
 342 #define AL { OP_IMREG, al_reg }
 343 #define CL { OP_IMREG, cl_reg }
 344 #define DL { OP_IMREG, dl_reg }
 345 #define BL { OP_IMREG, bl_reg }
 346 #define AH { OP_IMREG, ah_reg }
 347 #define CH { OP_IMREG, ch_reg }
 348 #define DH { OP_IMREG, dh_reg }
 349 #define BH { OP_IMREG, bh_reg }
 350 #define AX { OP_IMREG, ax_reg }
 351 #define DX { OP_IMREG, dx_reg }
 352 #define zAX { OP_IMREG, z_mode_ax_reg }
 353 #define indirDX { OP_IMREG, indir_dx_reg }
 354
 355 #define Sw { OP_SEG, w_mode }
 356 #define Sv { OP_SEG, v_mode }
 357 #define Ap { OP_DIR, 0 }
 358 #define Ob { OP_OFF64, b_mode }
 359 #define Ov { OP_OFF64, v_mode }
 360 #define Xb { OP_DSreg, eSI_reg }
 361 #define Xv { OP_DSreg, eSI_reg }
 362 #define Xz { OP_DSreg, eSI_reg }
 363 #define Yb { OP_ESreg, eDI_reg }
 364 #define Yv { OP_ESreg, eDI_reg }
 365 #define DSBX { OP_DSreg, eBX_reg }
 366
 367 #define es { OP_REG, es_reg }
 368 #define ss { OP_REG, ss_reg }
 369 #define cs { OP_REG, cs_reg }
 370 #define ds { OP_REG, ds_reg }
 371 #define fs { OP_REG, fs_reg }
 372 #define gs { OP_REG, gs_reg }
 373
 374 #define MX { OP_MMX, 0 }
 375 #define XM { OP_XMM, 0 }
 376 #define XMScalar { OP_XMM, scalar_mode }
 377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 378 #define XMM { OP_XMM, xmm_mode }
 379 #define XMxmmq { OP_XMM, xmmq_mode }
 380 #define EM { OP_EM, v_mode }
 381 #define EMS { OP_EM, v_swap_mode }
 382 #define EMd { OP_EM, d_mode }
 383 #define EMx { OP_EM, x_mode }
 384 #define EXbScalar { OP_EX, b_scalar_mode }
 385 #define EXw { OP_EX, w_mode }
 386 #define EXwScalar { OP_EX, w_scalar_mode }
 387 #define EXd { OP_EX, d_mode }
 388 #define EXdScalar { OP_EX, d_scalar_mode }
 389 #define EXdS { OP_EX, d_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmmdw { OP_EX, xmmdw_mode }
 405 #define EXxmmqd { OP_EX, xmmqd_mode }
 406 #define EXymmq { OP_EX, ymmq_mode }
 407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 410 #define MS { OP_MS, v_mode }
 411 #define XS { OP_XS, v_mode }
 412 #define EMCq { OP_EMC, q_mode }
 413 #define MXC { OP_MXC, 0 }
 414 #define OPSUF { OP_3DNowSuffix, 0 }
 415 #define SEP { SEP_Fixup, 0 }
 416 #define CMP { CMP_Fixup, 0 }
 417 #define XMM0 { XMM_Fixup, 0 }
 418 #define FXSAVE { FXSAVE_Fixup, 0 }
 419 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 420 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 421
 422 #define Vex { OP_VEX, vex_mode }
 423 #define VexScalar { OP_VEX, vex_scalar_mode }
 424 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 425 #define Vex128 { OP_VEX, vex128_mode }
 426 #define Vex256 { OP_VEX, vex256_mode }
 427 #define VexGdq { OP_VEX, dq_mode }
 428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 429 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 430 #define EXVexW { OP_EX_VexW, x_mode }
 431 #define EXdVexW { OP_EX_VexW, d_mode }
 432 #define EXqVexW { OP_EX_VexW, q_mode }
 433 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 435 #define XMVexW { OP_XMM_VexW, 0 }
 436 #define XMVexI4 { OP_REG_VexI4, x_mode }
 437 #define PCLMUL { PCLMUL_Fixup, 0 }
 438 #define VCMP { VCMP_Fixup, 0 }
 439 #define VPCMP { VPCMP_Fixup, 0 }
 440 #define VPCOM { VPCOM_Fixup, 0 }
 441
 442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 443 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 444 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 445
 446 #define XMask { OP_Mask, mask_mode }
 447 #define MaskG { OP_G, mask_mode }
 448 #define MaskE { OP_E, mask_mode }
 449 #define MaskBDE { OP_E, mask_bd_mode }
 450 #define MaskR { OP_R, mask_mode }
 451 #define MaskVex { OP_VEX, mask_mode }
 452
 453 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 454 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 455 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 456 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 457
 458 /* Used handle "rep" prefix for string instructions.  */
 459 #define Xbr { REP_Fixup, eSI_reg }
 460 #define Xvr { REP_Fixup, eSI_reg }
 461 #define Ybr { REP_Fixup, eDI_reg }
 462 #define Yvr { REP_Fixup, eDI_reg }
 463 #define Yzr { REP_Fixup, eDI_reg }
 464 #define indirDXr { REP_Fixup, indir_dx_reg }
 465 #define ALr { REP_Fixup, al_reg }
 466 #define eAXr { REP_Fixup, eAX_reg }
 467
 468 /* Used handle HLE prefix for lockable instructions.  */
 469 #define Ebh1 { HLE_Fixup1, b_mode }
 470 #define Evh1 { HLE_Fixup1, v_mode }
 471 #define Ebh2 { HLE_Fixup2, b_mode }
 472 #define Evh2 { HLE_Fixup2, v_mode }
 473 #define Ebh3 { HLE_Fixup3, b_mode }
 474 #define Evh3 { HLE_Fixup3, v_mode }
 475
 476 #define BND { BND_Fixup, 0 }
 477 #define NOTRACK { NOTRACK_Fixup, 0 }
 478
 479 #define cond_jump_flag { NULL, cond_jump_mode }
 480 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 481
 482 /* bits in sizeflag */
 483 #define SUFFIX_ALWAYS 4
 484 #define AFLAG 2
 485 #define DFLAG 1
 486
 487 enum
 488 {
 489   /* byte operand */
 490   b_mode = 1,
 491   /* byte operand with operand swapped */
 492   b_swap_mode,
 493   /* byte operand, sign extend like 'T' suffix */
 494   b_T_mode,
 495   /* operand size depends on prefixes */
 496   v_mode,
 497   /* operand size depends on prefixes with operand swapped */
 498   v_swap_mode,
 499   /* operand size depends on address prefix */
 500   va_mode,
 501   /* word operand */
 502   w_mode,
 503   /* double word operand  */
 504   d_mode,
 505   /* double word operand with operand swapped */
 506   d_swap_mode,
 507   /* quad word operand */
 508   q_mode,
 509   /* quad word operand with operand swapped */
 510   q_swap_mode,
 511   /* ten-byte operand */
 512   t_mode,
 513   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 514      broadcast enabled.  */
 515   x_mode,
 516   /* Similar to x_mode, but with different EVEX mem shifts.  */
 517   evex_x_gscat_mode,
 518   /* Similar to x_mode, but with disabled broadcast.  */
 519   evex_x_nobcst_mode,
 520   /* Similar to x_mode, but with operands swapped and disabled broadcast
 521      in EVEX.  */
 522   x_swap_mode,
 523   /* 16-byte XMM operand */
 524   xmm_mode,
 525   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 526      memory operand (depending on vector length).  Broadcast isn't
 527      allowed.  */
 528   xmmq_mode,
 529   /* Same as xmmq_mode, but broadcast is allowed.  */
 530   evex_half_bcst_xmmq_mode,
 531   /* XMM register or byte memory operand */
 532   xmm_mb_mode,
 533   /* XMM register or word memory operand */
 534   xmm_mw_mode,
 535   /* XMM register or double word memory operand */
 536   xmm_md_mode,
 537   /* XMM register or quad word memory operand */
 538   xmm_mq_mode,
 539   /* 16-byte XMM, word, double word or quad word operand.  */
 540   xmmdw_mode,
 541   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 542   xmmqd_mode,
 543   /* 32-byte YMM operand */
 544   ymm_mode,
 545   /* quad word, ymmword or zmmword memory operand.  */
 546   ymmq_mode,
 547   /* 32-byte YMM or 16-byte word operand */
 548   ymmxmm_mode,
 549   /* d_mode in 32bit, q_mode in 64bit mode.  */
 550   m_mode,
 551   /* pair of v_mode operands */
 552   a_mode,
 553   cond_jump_mode,
 554   loop_jcxz_mode,
 555   movsxd_mode,
 556   v_bnd_mode,
 557   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 558   v_bndmk_mode,
 559   /* operand size depends on REX prefixes.  */
 560   dq_mode,
 561   /* registers like dq_mode, memory like w_mode, displacements like
 562      v_mode without considering Intel64 ISA.  */
 563   dqw_mode,
 564   /* bounds operand */
 565   bnd_mode,
 566   /* bounds operand with operand swapped */
 567   bnd_swap_mode,
 568   /* 4- or 6-byte pointer operand */
 569   f_mode,
 570   const_1_mode,
 571   /* v_mode for indirect branch opcodes.  */
 572   indir_v_mode,
 573   /* v_mode for stack-related opcodes.  */
 574   stack_v_mode,
 575   /* non-quad operand size depends on prefixes */
 576   z_mode,
 577   /* 16-byte operand */
 578   o_mode,
 579   /* registers like dq_mode, memory like b_mode.  */
 580   dqb_mode,
 581   /* registers like d_mode, memory like b_mode.  */
 582   db_mode,
 583   /* registers like d_mode, memory like w_mode.  */
 584   dw_mode,
 585   /* registers like dq_mode, memory like d_mode.  */
 586   dqd_mode,
 587   /* normal vex mode */
 588   vex_mode,
 589   /* 128bit vex mode */
 590   vex128_mode,
 591   /* 256bit vex mode */
 592   vex256_mode,
 593
 594   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 595   vex_vsib_d_w_dq_mode,
 596   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 597   vex_vsib_d_w_d_mode,
 598   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 599   vex_vsib_q_w_dq_mode,
 600   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 601   vex_vsib_q_w_d_mode,
 602
 603   /* scalar, ignore vector length.  */
 604   scalar_mode,
 605   /* like b_mode, ignore vector length.  */
 606   b_scalar_mode,
 607   /* like w_mode, ignore vector length.  */
 608   w_scalar_mode,
 609   /* like d_mode, ignore vector length.  */
 610   d_scalar_mode,
 611   /* like d_swap_mode, ignore vector length.  */
 612   d_scalar_swap_mode,
 613   /* like q_mode, ignore vector length.  */
 614   q_scalar_mode,
 615   /* like q_swap_mode, ignore vector length.  */
 616   q_scalar_swap_mode,
 617   /* like vex_mode, ignore vector length.  */
 618   vex_scalar_mode,
 619   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 620   vex_scalar_w_dq_mode,
 621
 622   /* Static rounding.  */
 623   evex_rounding_mode,
 624   /* Static rounding, 64-bit mode only.  */
 625   evex_rounding_64_mode,
 626   /* Supress all exceptions.  */
 627   evex_sae_mode,
 628
 629   /* Mask register operand.  */
 630   mask_mode,
 631   /* Mask register operand.  */
 632   mask_bd_mode,
 633
 634   es_reg,
 635   cs_reg,
 636   ss_reg,
 637   ds_reg,
 638   fs_reg,
 639   gs_reg,
 640
 641   eAX_reg,
 642   eCX_reg,
 643   eDX_reg,
 644   eBX_reg,
 645   eSP_reg,
 646   eBP_reg,
 647   eSI_reg,
 648   eDI_reg,
 649
 650   al_reg,
 651   cl_reg,
 652   dl_reg,
 653   bl_reg,
 654   ah_reg,
 655   ch_reg,
 656   dh_reg,
 657   bh_reg,
 658
 659   ax_reg,
 660   cx_reg,
 661   dx_reg,
 662   bx_reg,
 663   sp_reg,
 664   bp_reg,
 665   si_reg,
 666   di_reg,
 667
 668   rAX_reg,
 669   rCX_reg,
 670   rDX_reg,
 671   rBX_reg,
 672   rSP_reg,
 673   rBP_reg,
 674   rSI_reg,
 675   rDI_reg,
 676
 677   z_mode_ax_reg,
 678   indir_dx_reg
 679 };
 680
 681 enum
 682 {
 683   FLOATCODE = 1,
 684   USE_REG_TABLE,
 685   USE_MOD_TABLE,
 686   USE_RM_TABLE,
 687   USE_PREFIX_TABLE,
 688   USE_X86_64_TABLE,
 689   USE_3BYTE_TABLE,
 690   USE_XOP_8F_TABLE,
 691   USE_VEX_C4_TABLE,
 692   USE_VEX_C5_TABLE,
 693   USE_VEX_LEN_TABLE,
 694   USE_VEX_W_TABLE,
 695   USE_EVEX_TABLE,
 696   USE_EVEX_LEN_TABLE
 697 };
 698
 699 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 700
 701 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 702 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 703 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 704 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 705 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 706 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 707 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 708 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 709 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 710 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 711 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 712 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 713 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 714 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 715 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 716 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 717
 718 enum
 719 {
 720   REG_80 = 0,
 721   REG_81,
 722   REG_83,
 723   REG_8F,
 724   REG_C0,
 725   REG_C1,
 726   REG_C6,
 727   REG_C7,
 728   REG_D0,
 729   REG_D1,
 730   REG_D2,
 731   REG_D3,
 732   REG_F6,
 733   REG_F7,
 734   REG_FE,
 735   REG_FF,
 736   REG_0F00,
 737   REG_0F01,
 738   REG_0F0D,
 739   REG_0F18,
 740   REG_0F1C_P_0_MOD_0,
 741   REG_0F1E_P_1_MOD_3,
 742   REG_0F71,
 743   REG_0F72,
 744   REG_0F73,
 745   REG_0FA6,
 746   REG_0FA7,
 747   REG_0FAE,
 748   REG_0FBA,
 749   REG_0FC7,
 750   REG_VEX_0F71,
 751   REG_VEX_0F72,
 752   REG_VEX_0F73,
 753   REG_VEX_0FAE,
 754   REG_VEX_0F38F3,
 755   REG_XOP_LWPCB,
 756   REG_XOP_LWP,
 757   REG_XOP_TBM_01,
 758   REG_XOP_TBM_02,
 759
 760   REG_EVEX_0F71,
 761   REG_EVEX_0F72,
 762   REG_EVEX_0F73,
 763   REG_EVEX_0F38C6,
 764   REG_EVEX_0F38C7
 765 };
 766
 767 enum
 768 {
 769   MOD_8D = 0,
 770   MOD_C6_REG_7,
 771   MOD_C7_REG_7,
 772   MOD_FF_REG_3,
 773   MOD_FF_REG_5,
 774   MOD_0F01_REG_0,
 775   MOD_0F01_REG_1,
 776   MOD_0F01_REG_2,
 777   MOD_0F01_REG_3,
 778   MOD_0F01_REG_5,
 779   MOD_0F01_REG_7,
 780   MOD_0F12_PREFIX_0,
 781   MOD_0F13,
 782   MOD_0F16_PREFIX_0,
 783   MOD_0F17,
 784   MOD_0F18_REG_0,
 785   MOD_0F18_REG_1,
 786   MOD_0F18_REG_2,
 787   MOD_0F18_REG_3,
 788   MOD_0F18_REG_4,
 789   MOD_0F18_REG_5,
 790   MOD_0F18_REG_6,
 791   MOD_0F18_REG_7,
 792   MOD_0F1A_PREFIX_0,
 793   MOD_0F1B_PREFIX_0,
 794   MOD_0F1B_PREFIX_1,
 795   MOD_0F1C_PREFIX_0,
 796   MOD_0F1E_PREFIX_1,
 797   MOD_0F24,
 798   MOD_0F26,
 799   MOD_0F2B_PREFIX_0,
 800   MOD_0F2B_PREFIX_1,
 801   MOD_0F2B_PREFIX_2,
 802   MOD_0F2B_PREFIX_3,
 803   MOD_0F51,
 804   MOD_0F71_REG_2,
 805   MOD_0F71_REG_4,
 806   MOD_0F71_REG_6,
 807   MOD_0F72_REG_2,
 808   MOD_0F72_REG_4,
 809   MOD_0F72_REG_6,
 810   MOD_0F73_REG_2,
 811   MOD_0F73_REG_3,
 812   MOD_0F73_REG_6,
 813   MOD_0F73_REG_7,
 814   MOD_0FAE_REG_0,
 815   MOD_0FAE_REG_1,
 816   MOD_0FAE_REG_2,
 817   MOD_0FAE_REG_3,
 818   MOD_0FAE_REG_4,
 819   MOD_0FAE_REG_5,
 820   MOD_0FAE_REG_6,
 821   MOD_0FAE_REG_7,
 822   MOD_0FB2,
 823   MOD_0FB4,
 824   MOD_0FB5,
 825   MOD_0FC3,
 826   MOD_0FC7_REG_3,
 827   MOD_0FC7_REG_4,
 828   MOD_0FC7_REG_5,
 829   MOD_0FC7_REG_6,
 830   MOD_0FC7_REG_7,
 831   MOD_0FD7,
 832   MOD_0FE7_PREFIX_2,
 833   MOD_0FF0_PREFIX_3,
 834   MOD_0F382A_PREFIX_2,
 835   MOD_0F38F5_PREFIX_2,
 836   MOD_0F38F6_PREFIX_0,
 837   MOD_0F38F8_PREFIX_1,
 838   MOD_0F38F8_PREFIX_2,
 839   MOD_0F38F8_PREFIX_3,
 840   MOD_0F38F9_PREFIX_0,
 841   MOD_62_32BIT,
 842   MOD_C4_32BIT,
 843   MOD_C5_32BIT,
 844   MOD_VEX_0F12_PREFIX_0,
 845   MOD_VEX_0F13,
 846   MOD_VEX_0F16_PREFIX_0,
 847   MOD_VEX_0F17,
 848   MOD_VEX_0F2B,
 849   MOD_VEX_W_0_0F41_P_0_LEN_1,
 850   MOD_VEX_W_1_0F41_P_0_LEN_1,
 851   MOD_VEX_W_0_0F41_P_2_LEN_1,
 852   MOD_VEX_W_1_0F41_P_2_LEN_1,
 853   MOD_VEX_W_0_0F42_P_0_LEN_1,
 854   MOD_VEX_W_1_0F42_P_0_LEN_1,
 855   MOD_VEX_W_0_0F42_P_2_LEN_1,
 856   MOD_VEX_W_1_0F42_P_2_LEN_1,
 857   MOD_VEX_W_0_0F44_P_0_LEN_1,
 858   MOD_VEX_W_1_0F44_P_0_LEN_1,
 859   MOD_VEX_W_0_0F44_P_2_LEN_1,
 860   MOD_VEX_W_1_0F44_P_2_LEN_1,
 861   MOD_VEX_W_0_0F45_P_0_LEN_1,
 862   MOD_VEX_W_1_0F45_P_0_LEN_1,
 863   MOD_VEX_W_0_0F45_P_2_LEN_1,
 864   MOD_VEX_W_1_0F45_P_2_LEN_1,
 865   MOD_VEX_W_0_0F46_P_0_LEN_1,
 866   MOD_VEX_W_1_0F46_P_0_LEN_1,
 867   MOD_VEX_W_0_0F46_P_2_LEN_1,
 868   MOD_VEX_W_1_0F46_P_2_LEN_1,
 869   MOD_VEX_W_0_0F47_P_0_LEN_1,
 870   MOD_VEX_W_1_0F47_P_0_LEN_1,
 871   MOD_VEX_W_0_0F47_P_2_LEN_1,
 872   MOD_VEX_W_1_0F47_P_2_LEN_1,
 873   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 874   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 875   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 876   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 877   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 878   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 879   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 880   MOD_VEX_0F50,
 881   MOD_VEX_0F71_REG_2,
 882   MOD_VEX_0F71_REG_4,
 883   MOD_VEX_0F71_REG_6,
 884   MOD_VEX_0F72_REG_2,
 885   MOD_VEX_0F72_REG_4,
 886   MOD_VEX_0F72_REG_6,
 887   MOD_VEX_0F73_REG_2,
 888   MOD_VEX_0F73_REG_3,
 889   MOD_VEX_0F73_REG_6,
 890   MOD_VEX_0F73_REG_7,
 891   MOD_VEX_W_0_0F91_P_0_LEN_0,
 892   MOD_VEX_W_1_0F91_P_0_LEN_0,
 893   MOD_VEX_W_0_0F91_P_2_LEN_0,
 894   MOD_VEX_W_1_0F91_P_2_LEN_0,
 895   MOD_VEX_W_0_0F92_P_0_LEN_0,
 896   MOD_VEX_W_0_0F92_P_2_LEN_0,
 897   MOD_VEX_0F92_P_3_LEN_0,
 898   MOD_VEX_W_0_0F93_P_0_LEN_0,
 899   MOD_VEX_W_0_0F93_P_2_LEN_0,
 900   MOD_VEX_0F93_P_3_LEN_0,
 901   MOD_VEX_W_0_0F98_P_0_LEN_0,
 902   MOD_VEX_W_1_0F98_P_0_LEN_0,
 903   MOD_VEX_W_0_0F98_P_2_LEN_0,
 904   MOD_VEX_W_1_0F98_P_2_LEN_0,
 905   MOD_VEX_W_0_0F99_P_0_LEN_0,
 906   MOD_VEX_W_1_0F99_P_0_LEN_0,
 907   MOD_VEX_W_0_0F99_P_2_LEN_0,
 908   MOD_VEX_W_1_0F99_P_2_LEN_0,
 909   MOD_VEX_0FAE_REG_2,
 910   MOD_VEX_0FAE_REG_3,
 911   MOD_VEX_0FD7_PREFIX_2,
 912   MOD_VEX_0FE7_PREFIX_2,
 913   MOD_VEX_0FF0_PREFIX_3,
 914   MOD_VEX_0F381A_PREFIX_2,
 915   MOD_VEX_0F382A_PREFIX_2,
 916   MOD_VEX_0F382C_PREFIX_2,
 917   MOD_VEX_0F382D_PREFIX_2,
 918   MOD_VEX_0F382E_PREFIX_2,
 919   MOD_VEX_0F382F_PREFIX_2,
 920   MOD_VEX_0F385A_PREFIX_2,
 921   MOD_VEX_0F388C_PREFIX_2,
 922   MOD_VEX_0F388E_PREFIX_2,
 923   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 924   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 925   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 926   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 927   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 928   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 929   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 930   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 931
 932   MOD_EVEX_0F12_PREFIX_0,
 933   MOD_EVEX_0F16_PREFIX_0,
 934   MOD_EVEX_0F38C6_REG_1,
 935   MOD_EVEX_0F38C6_REG_2,
 936   MOD_EVEX_0F38C6_REG_5,
 937   MOD_EVEX_0F38C6_REG_6,
 938   MOD_EVEX_0F38C7_REG_1,
 939   MOD_EVEX_0F38C7_REG_2,
 940   MOD_EVEX_0F38C7_REG_5,
 941   MOD_EVEX_0F38C7_REG_6
 942 };
 943
 944 enum
 945 {
 946   RM_C6_REG_7 = 0,
 947   RM_C7_REG_7,
 948   RM_0F01_REG_0,
 949   RM_0F01_REG_1,
 950   RM_0F01_REG_2,
 951   RM_0F01_REG_3,
 952   RM_0F01_REG_5_MOD_3,
 953   RM_0F01_REG_7_MOD_3,
 954   RM_0F1E_P_1_MOD_3_REG_7,
 955   RM_0FAE_REG_6_MOD_3_P_0,
 956   RM_0FAE_REG_7_MOD_3,
 957 };
 958
 959 enum
 960 {
 961   PREFIX_90 = 0,
 962   PREFIX_0F01_REG_5_MOD_0,
 963   PREFIX_0F01_REG_5_MOD_3_RM_0,
 964   PREFIX_0F01_REG_5_MOD_3_RM_2,
 965   PREFIX_0F01_REG_7_MOD_3_RM_2,
 966   PREFIX_0F01_REG_7_MOD_3_RM_3,
 967   PREFIX_0F09,
 968   PREFIX_0F10,
 969   PREFIX_0F11,
 970   PREFIX_0F12,
 971   PREFIX_0F16,
 972   PREFIX_0F1A,
 973   PREFIX_0F1B,
 974   PREFIX_0F1C,
 975   PREFIX_0F1E,
 976   PREFIX_0F2A,
 977   PREFIX_0F2B,
 978   PREFIX_0F2C,
 979   PREFIX_0F2D,
 980   PREFIX_0F2E,
 981   PREFIX_0F2F,
 982   PREFIX_0F51,
 983   PREFIX_0F52,
 984   PREFIX_0F53,
 985   PREFIX_0F58,
 986   PREFIX_0F59,
 987   PREFIX_0F5A,
 988   PREFIX_0F5B,
 989   PREFIX_0F5C,
 990   PREFIX_0F5D,
 991   PREFIX_0F5E,
 992   PREFIX_0F5F,
 993   PREFIX_0F60,
 994   PREFIX_0F61,
 995   PREFIX_0F62,
 996   PREFIX_0F6C,
 997   PREFIX_0F6D,
 998   PREFIX_0F6F,
 999   PREFIX_0F70,
1000   PREFIX_0F73_REG_3,
1001   PREFIX_0F73_REG_7,
1002   PREFIX_0F78,
1003   PREFIX_0F79,
1004   PREFIX_0F7C,
1005   PREFIX_0F7D,
1006   PREFIX_0F7E,
1007   PREFIX_0F7F,
1008   PREFIX_0FAE_REG_0_MOD_3,
1009   PREFIX_0FAE_REG_1_MOD_3,
1010   PREFIX_0FAE_REG_2_MOD_3,
1011   PREFIX_0FAE_REG_3_MOD_3,
1012   PREFIX_0FAE_REG_4_MOD_0,
1013   PREFIX_0FAE_REG_4_MOD_3,
1014   PREFIX_0FAE_REG_5_MOD_0,
1015   PREFIX_0FAE_REG_5_MOD_3,
1016   PREFIX_0FAE_REG_6_MOD_0,
1017   PREFIX_0FAE_REG_6_MOD_3,
1018   PREFIX_0FAE_REG_7_MOD_0,
1019   PREFIX_0FB8,
1020   PREFIX_0FBC,
1021   PREFIX_0FBD,
1022   PREFIX_0FC2,
1023   PREFIX_0FC3_MOD_0,
1024   PREFIX_0FC7_REG_6_MOD_0,
1025   PREFIX_0FC7_REG_6_MOD_3,
1026   PREFIX_0FC7_REG_7_MOD_3,
1027   PREFIX_0FD0,
1028   PREFIX_0FD6,
1029   PREFIX_0FE6,
1030   PREFIX_0FE7,
1031   PREFIX_0FF0,
1032   PREFIX_0FF7,
1033   PREFIX_0F3810,
1034   PREFIX_0F3814,
1035   PREFIX_0F3815,
1036   PREFIX_0F3817,
1037   PREFIX_0F3820,
1038   PREFIX_0F3821,
1039   PREFIX_0F3822,
1040   PREFIX_0F3823,
1041   PREFIX_0F3824,
1042   PREFIX_0F3825,
1043   PREFIX_0F3828,
1044   PREFIX_0F3829,
1045   PREFIX_0F382A,
1046   PREFIX_0F382B,
1047   PREFIX_0F3830,
1048   PREFIX_0F3831,
1049   PREFIX_0F3832,
1050   PREFIX_0F3833,
1051   PREFIX_0F3834,
1052   PREFIX_0F3835,
1053   PREFIX_0F3837,
1054   PREFIX_0F3838,
1055   PREFIX_0F3839,
1056   PREFIX_0F383A,
1057   PREFIX_0F383B,
1058   PREFIX_0F383C,
1059   PREFIX_0F383D,
1060   PREFIX_0F383E,
1061   PREFIX_0F383F,
1062   PREFIX_0F3840,
1063   PREFIX_0F3841,
1064   PREFIX_0F3880,
1065   PREFIX_0F3881,
1066   PREFIX_0F3882,
1067   PREFIX_0F38C8,
1068   PREFIX_0F38C9,
1069   PREFIX_0F38CA,
1070   PREFIX_0F38CB,
1071   PREFIX_0F38CC,
1072   PREFIX_0F38CD,
1073   PREFIX_0F38CF,
1074   PREFIX_0F38DB,
1075   PREFIX_0F38DC,
1076   PREFIX_0F38DD,
1077   PREFIX_0F38DE,
1078   PREFIX_0F38DF,
1079   PREFIX_0F38F0,
1080   PREFIX_0F38F1,
1081   PREFIX_0F38F5,
1082   PREFIX_0F38F6,
1083   PREFIX_0F38F8,
1084   PREFIX_0F38F9,
1085   PREFIX_0F3A08,
1086   PREFIX_0F3A09,
1087   PREFIX_0F3A0A,
1088   PREFIX_0F3A0B,
1089   PREFIX_0F3A0C,
1090   PREFIX_0F3A0D,
1091   PREFIX_0F3A0E,
1092   PREFIX_0F3A14,
1093   PREFIX_0F3A15,
1094   PREFIX_0F3A16,
1095   PREFIX_0F3A17,
1096   PREFIX_0F3A20,
1097   PREFIX_0F3A21,
1098   PREFIX_0F3A22,
1099   PREFIX_0F3A40,
1100   PREFIX_0F3A41,
1101   PREFIX_0F3A42,
1102   PREFIX_0F3A44,
1103   PREFIX_0F3A60,
1104   PREFIX_0F3A61,
1105   PREFIX_0F3A62,
1106   PREFIX_0F3A63,
1107   PREFIX_0F3ACC,
1108   PREFIX_0F3ACE,
1109   PREFIX_0F3ACF,
1110   PREFIX_0F3ADF,
1111   PREFIX_VEX_0F10,
1112   PREFIX_VEX_0F11,
1113   PREFIX_VEX_0F12,
1114   PREFIX_VEX_0F16,
1115   PREFIX_VEX_0F2A,
1116   PREFIX_VEX_0F2C,
1117   PREFIX_VEX_0F2D,
1118   PREFIX_VEX_0F2E,
1119   PREFIX_VEX_0F2F,
1120   PREFIX_VEX_0F41,
1121   PREFIX_VEX_0F42,
1122   PREFIX_VEX_0F44,
1123   PREFIX_VEX_0F45,
1124   PREFIX_VEX_0F46,
1125   PREFIX_VEX_0F47,
1126   PREFIX_VEX_0F4A,
1127   PREFIX_VEX_0F4B,
1128   PREFIX_VEX_0F51,
1129   PREFIX_VEX_0F52,
1130   PREFIX_VEX_0F53,
1131   PREFIX_VEX_0F58,
1132   PREFIX_VEX_0F59,
1133   PREFIX_VEX_0F5A,
1134   PREFIX_VEX_0F5B,
1135   PREFIX_VEX_0F5C,
1136   PREFIX_VEX_0F5D,
1137   PREFIX_VEX_0F5E,
1138   PREFIX_VEX_0F5F,
1139   PREFIX_VEX_0F60,
1140   PREFIX_VEX_0F61,
1141   PREFIX_VEX_0F62,
1142   PREFIX_VEX_0F63,
1143   PREFIX_VEX_0F64,
1144   PREFIX_VEX_0F65,
1145   PREFIX_VEX_0F66,
1146   PREFIX_VEX_0F67,
1147   PREFIX_VEX_0F68,
1148   PREFIX_VEX_0F69,
1149   PREFIX_VEX_0F6A,
1150   PREFIX_VEX_0F6B,
1151   PREFIX_VEX_0F6C,
1152   PREFIX_VEX_0F6D,
1153   PREFIX_VEX_0F6E,
1154   PREFIX_VEX_0F6F,
1155   PREFIX_VEX_0F70,
1156   PREFIX_VEX_0F71_REG_2,
1157   PREFIX_VEX_0F71_REG_4,
1158   PREFIX_VEX_0F71_REG_6,
1159   PREFIX_VEX_0F72_REG_2,
1160   PREFIX_VEX_0F72_REG_4,
1161   PREFIX_VEX_0F72_REG_6,
1162   PREFIX_VEX_0F73_REG_2,
1163   PREFIX_VEX_0F73_REG_3,
1164   PREFIX_VEX_0F73_REG_6,
1165   PREFIX_VEX_0F73_REG_7,
1166   PREFIX_VEX_0F74,
1167   PREFIX_VEX_0F75,
1168   PREFIX_VEX_0F76,
1169   PREFIX_VEX_0F77,
1170   PREFIX_VEX_0F7C,
1171   PREFIX_VEX_0F7D,
1172   PREFIX_VEX_0F7E,
1173   PREFIX_VEX_0F7F,
1174   PREFIX_VEX_0F90,
1175   PREFIX_VEX_0F91,
1176   PREFIX_VEX_0F92,
1177   PREFIX_VEX_0F93,
1178   PREFIX_VEX_0F98,
1179   PREFIX_VEX_0F99,
1180   PREFIX_VEX_0FC2,
1181   PREFIX_VEX_0FC4,
1182   PREFIX_VEX_0FC5,
1183   PREFIX_VEX_0FD0,
1184   PREFIX_VEX_0FD1,
1185   PREFIX_VEX_0FD2,
1186   PREFIX_VEX_0FD3,
1187   PREFIX_VEX_0FD4,
1188   PREFIX_VEX_0FD5,
1189   PREFIX_VEX_0FD6,
1190   PREFIX_VEX_0FD7,
1191   PREFIX_VEX_0FD8,
1192   PREFIX_VEX_0FD9,
1193   PREFIX_VEX_0FDA,
1194   PREFIX_VEX_0FDB,
1195   PREFIX_VEX_0FDC,
1196   PREFIX_VEX_0FDD,
1197   PREFIX_VEX_0FDE,
1198   PREFIX_VEX_0FDF,
1199   PREFIX_VEX_0FE0,
1200   PREFIX_VEX_0FE1,
1201   PREFIX_VEX_0FE2,
1202   PREFIX_VEX_0FE3,
1203   PREFIX_VEX_0FE4,
1204   PREFIX_VEX_0FE5,
1205   PREFIX_VEX_0FE6,
1206   PREFIX_VEX_0FE7,
1207   PREFIX_VEX_0FE8,
1208   PREFIX_VEX_0FE9,
1209   PREFIX_VEX_0FEA,
1210   PREFIX_VEX_0FEB,
1211   PREFIX_VEX_0FEC,
1212   PREFIX_VEX_0FED,
1213   PREFIX_VEX_0FEE,
1214   PREFIX_VEX_0FEF,
1215   PREFIX_VEX_0FF0,
1216   PREFIX_VEX_0FF1,
1217   PREFIX_VEX_0FF2,
1218   PREFIX_VEX_0FF3,
1219   PREFIX_VEX_0FF4,
1220   PREFIX_VEX_0FF5,
1221   PREFIX_VEX_0FF6,
1222   PREFIX_VEX_0FF7,
1223   PREFIX_VEX_0FF8,
1224   PREFIX_VEX_0FF9,
1225   PREFIX_VEX_0FFA,
1226   PREFIX_VEX_0FFB,
1227   PREFIX_VEX_0FFC,
1228   PREFIX_VEX_0FFD,
1229   PREFIX_VEX_0FFE,
1230   PREFIX_VEX_0F3800,
1231   PREFIX_VEX_0F3801,
1232   PREFIX_VEX_0F3802,
1233   PREFIX_VEX_0F3803,
1234   PREFIX_VEX_0F3804,
1235   PREFIX_VEX_0F3805,
1236   PREFIX_VEX_0F3806,
1237   PREFIX_VEX_0F3807,
1238   PREFIX_VEX_0F3808,
1239   PREFIX_VEX_0F3809,
1240   PREFIX_VEX_0F380A,
1241   PREFIX_VEX_0F380B,
1242   PREFIX_VEX_0F380C,
1243   PREFIX_VEX_0F380D,
1244   PREFIX_VEX_0F380E,
1245   PREFIX_VEX_0F380F,
1246   PREFIX_VEX_0F3813,
1247   PREFIX_VEX_0F3816,
1248   PREFIX_VEX_0F3817,
1249   PREFIX_VEX_0F3818,
1250   PREFIX_VEX_0F3819,
1251   PREFIX_VEX_0F381A,
1252   PREFIX_VEX_0F381C,
1253   PREFIX_VEX_0F381D,
1254   PREFIX_VEX_0F381E,
1255   PREFIX_VEX_0F3820,
1256   PREFIX_VEX_0F3821,
1257   PREFIX_VEX_0F3822,
1258   PREFIX_VEX_0F3823,
1259   PREFIX_VEX_0F3824,
1260   PREFIX_VEX_0F3825,
1261   PREFIX_VEX_0F3828,
1262   PREFIX_VEX_0F3829,
1263   PREFIX_VEX_0F382A,
1264   PREFIX_VEX_0F382B,
1265   PREFIX_VEX_0F382C,
1266   PREFIX_VEX_0F382D,
1267   PREFIX_VEX_0F382E,
1268   PREFIX_VEX_0F382F,
1269   PREFIX_VEX_0F3830,
1270   PREFIX_VEX_0F3831,
1271   PREFIX_VEX_0F3832,
1272   PREFIX_VEX_0F3833,
1273   PREFIX_VEX_0F3834,
1274   PREFIX_VEX_0F3835,
1275   PREFIX_VEX_0F3836,
1276   PREFIX_VEX_0F3837,
1277   PREFIX_VEX_0F3838,
1278   PREFIX_VEX_0F3839,
1279   PREFIX_VEX_0F383A,
1280   PREFIX_VEX_0F383B,
1281   PREFIX_VEX_0F383C,
1282   PREFIX_VEX_0F383D,
1283   PREFIX_VEX_0F383E,
1284   PREFIX_VEX_0F383F,
1285   PREFIX_VEX_0F3840,
1286   PREFIX_VEX_0F3841,
1287   PREFIX_VEX_0F3845,
1288   PREFIX_VEX_0F3846,
1289   PREFIX_VEX_0F3847,
1290   PREFIX_VEX_0F3858,
1291   PREFIX_VEX_0F3859,
1292   PREFIX_VEX_0F385A,
1293   PREFIX_VEX_0F3878,
1294   PREFIX_VEX_0F3879,
1295   PREFIX_VEX_0F388C,
1296   PREFIX_VEX_0F388E,
1297   PREFIX_VEX_0F3890,
1298   PREFIX_VEX_0F3891,
1299   PREFIX_VEX_0F3892,
1300   PREFIX_VEX_0F3893,
1301   PREFIX_VEX_0F3896,
1302   PREFIX_VEX_0F3897,
1303   PREFIX_VEX_0F3898,
1304   PREFIX_VEX_0F3899,
1305   PREFIX_VEX_0F389A,
1306   PREFIX_VEX_0F389B,
1307   PREFIX_VEX_0F389C,
1308   PREFIX_VEX_0F389D,
1309   PREFIX_VEX_0F389E,
1310   PREFIX_VEX_0F389F,
1311   PREFIX_VEX_0F38A6,
1312   PREFIX_VEX_0F38A7,
1313   PREFIX_VEX_0F38A8,
1314   PREFIX_VEX_0F38A9,
1315   PREFIX_VEX_0F38AA,
1316   PREFIX_VEX_0F38AB,
1317   PREFIX_VEX_0F38AC,
1318   PREFIX_VEX_0F38AD,
1319   PREFIX_VEX_0F38AE,
1320   PREFIX_VEX_0F38AF,
1321   PREFIX_VEX_0F38B6,
1322   PREFIX_VEX_0F38B7,
1323   PREFIX_VEX_0F38B8,
1324   PREFIX_VEX_0F38B9,
1325   PREFIX_VEX_0F38BA,
1326   PREFIX_VEX_0F38BB,
1327   PREFIX_VEX_0F38BC,
1328   PREFIX_VEX_0F38BD,
1329   PREFIX_VEX_0F38BE,
1330   PREFIX_VEX_0F38BF,
1331   PREFIX_VEX_0F38CF,
1332   PREFIX_VEX_0F38DB,
1333   PREFIX_VEX_0F38DC,
1334   PREFIX_VEX_0F38DD,
1335   PREFIX_VEX_0F38DE,
1336   PREFIX_VEX_0F38DF,
1337   PREFIX_VEX_0F38F2,
1338   PREFIX_VEX_0F38F3_REG_1,
1339   PREFIX_VEX_0F38F3_REG_2,
1340   PREFIX_VEX_0F38F3_REG_3,
1341   PREFIX_VEX_0F38F5,
1342   PREFIX_VEX_0F38F6,
1343   PREFIX_VEX_0F38F7,
1344   PREFIX_VEX_0F3A00,
1345   PREFIX_VEX_0F3A01,
1346   PREFIX_VEX_0F3A02,
1347   PREFIX_VEX_0F3A04,
1348   PREFIX_VEX_0F3A05,
1349   PREFIX_VEX_0F3A06,
1350   PREFIX_VEX_0F3A08,
1351   PREFIX_VEX_0F3A09,
1352   PREFIX_VEX_0F3A0A,
1353   PREFIX_VEX_0F3A0B,
1354   PREFIX_VEX_0F3A0C,
1355   PREFIX_VEX_0F3A0D,
1356   PREFIX_VEX_0F3A0E,
1357   PREFIX_VEX_0F3A0F,
1358   PREFIX_VEX_0F3A14,
1359   PREFIX_VEX_0F3A15,
1360   PREFIX_VEX_0F3A16,
1361   PREFIX_VEX_0F3A17,
1362   PREFIX_VEX_0F3A18,
1363   PREFIX_VEX_0F3A19,
1364   PREFIX_VEX_0F3A1D,
1365   PREFIX_VEX_0F3A20,
1366   PREFIX_VEX_0F3A21,
1367   PREFIX_VEX_0F3A22,
1368   PREFIX_VEX_0F3A30,
1369   PREFIX_VEX_0F3A31,
1370   PREFIX_VEX_0F3A32,
1371   PREFIX_VEX_0F3A33,
1372   PREFIX_VEX_0F3A38,
1373   PREFIX_VEX_0F3A39,
1374   PREFIX_VEX_0F3A40,
1375   PREFIX_VEX_0F3A41,
1376   PREFIX_VEX_0F3A42,
1377   PREFIX_VEX_0F3A44,
1378   PREFIX_VEX_0F3A46,
1379   PREFIX_VEX_0F3A48,
1380   PREFIX_VEX_0F3A49,
1381   PREFIX_VEX_0F3A4A,
1382   PREFIX_VEX_0F3A4B,
1383   PREFIX_VEX_0F3A4C,
1384   PREFIX_VEX_0F3A5C,
1385   PREFIX_VEX_0F3A5D,
1386   PREFIX_VEX_0F3A5E,
1387   PREFIX_VEX_0F3A5F,
1388   PREFIX_VEX_0F3A60,
1389   PREFIX_VEX_0F3A61,
1390   PREFIX_VEX_0F3A62,
1391   PREFIX_VEX_0F3A63,
1392   PREFIX_VEX_0F3A68,
1393   PREFIX_VEX_0F3A69,
1394   PREFIX_VEX_0F3A6A,
1395   PREFIX_VEX_0F3A6B,
1396   PREFIX_VEX_0F3A6C,
1397   PREFIX_VEX_0F3A6D,
1398   PREFIX_VEX_0F3A6E,
1399   PREFIX_VEX_0F3A6F,
1400   PREFIX_VEX_0F3A78,
1401   PREFIX_VEX_0F3A79,
1402   PREFIX_VEX_0F3A7A,
1403   PREFIX_VEX_0F3A7B,
1404   PREFIX_VEX_0F3A7C,
1405   PREFIX_VEX_0F3A7D,
1406   PREFIX_VEX_0F3A7E,
1407   PREFIX_VEX_0F3A7F,
1408   PREFIX_VEX_0F3ACE,
1409   PREFIX_VEX_0F3ACF,
1410   PREFIX_VEX_0F3ADF,
1411   PREFIX_VEX_0F3AF0,
1412
1413   PREFIX_EVEX_0F10,
1414   PREFIX_EVEX_0F11,
1415   PREFIX_EVEX_0F12,
1416   PREFIX_EVEX_0F13,
1417   PREFIX_EVEX_0F14,
1418   PREFIX_EVEX_0F15,
1419   PREFIX_EVEX_0F16,
1420   PREFIX_EVEX_0F17,
1421   PREFIX_EVEX_0F28,
1422   PREFIX_EVEX_0F29,
1423   PREFIX_EVEX_0F2A,
1424   PREFIX_EVEX_0F2B,
1425   PREFIX_EVEX_0F2C,
1426   PREFIX_EVEX_0F2D,
1427   PREFIX_EVEX_0F2E,
1428   PREFIX_EVEX_0F2F,
1429   PREFIX_EVEX_0F51,
1430   PREFIX_EVEX_0F54,
1431   PREFIX_EVEX_0F55,
1432   PREFIX_EVEX_0F56,
1433   PREFIX_EVEX_0F57,
1434   PREFIX_EVEX_0F58,
1435   PREFIX_EVEX_0F59,
1436   PREFIX_EVEX_0F5A,
1437   PREFIX_EVEX_0F5B,
1438   PREFIX_EVEX_0F5C,
1439   PREFIX_EVEX_0F5D,
1440   PREFIX_EVEX_0F5E,
1441   PREFIX_EVEX_0F5F,
1442   PREFIX_EVEX_0F60,
1443   PREFIX_EVEX_0F61,
1444   PREFIX_EVEX_0F62,
1445   PREFIX_EVEX_0F63,
1446   PREFIX_EVEX_0F64,
1447   PREFIX_EVEX_0F65,
1448   PREFIX_EVEX_0F66,
1449   PREFIX_EVEX_0F67,
1450   PREFIX_EVEX_0F68,
1451   PREFIX_EVEX_0F69,
1452   PREFIX_EVEX_0F6A,
1453   PREFIX_EVEX_0F6B,
1454   PREFIX_EVEX_0F6C,
1455   PREFIX_EVEX_0F6D,
1456   PREFIX_EVEX_0F6E,
1457   PREFIX_EVEX_0F6F,
1458   PREFIX_EVEX_0F70,
1459   PREFIX_EVEX_0F71_REG_2,
1460   PREFIX_EVEX_0F71_REG_4,
1461   PREFIX_EVEX_0F71_REG_6,
1462   PREFIX_EVEX_0F72_REG_0,
1463   PREFIX_EVEX_0F72_REG_1,
1464   PREFIX_EVEX_0F72_REG_2,
1465   PREFIX_EVEX_0F72_REG_4,
1466   PREFIX_EVEX_0F72_REG_6,
1467   PREFIX_EVEX_0F73_REG_2,
1468   PREFIX_EVEX_0F73_REG_3,
1469   PREFIX_EVEX_0F73_REG_6,
1470   PREFIX_EVEX_0F73_REG_7,
1471   PREFIX_EVEX_0F74,
1472   PREFIX_EVEX_0F75,
1473   PREFIX_EVEX_0F76,
1474   PREFIX_EVEX_0F78,
1475   PREFIX_EVEX_0F79,
1476   PREFIX_EVEX_0F7A,
1477   PREFIX_EVEX_0F7B,
1478   PREFIX_EVEX_0F7E,
1479   PREFIX_EVEX_0F7F,
1480   PREFIX_EVEX_0FC2,
1481   PREFIX_EVEX_0FC4,
1482   PREFIX_EVEX_0FC5,
1483   PREFIX_EVEX_0FC6,
1484   PREFIX_EVEX_0FD1,
1485   PREFIX_EVEX_0FD2,
1486   PREFIX_EVEX_0FD3,
1487   PREFIX_EVEX_0FD4,
1488   PREFIX_EVEX_0FD5,
1489   PREFIX_EVEX_0FD6,
1490   PREFIX_EVEX_0FD8,
1491   PREFIX_EVEX_0FD9,
1492   PREFIX_EVEX_0FDA,
1493   PREFIX_EVEX_0FDB,
1494   PREFIX_EVEX_0FDC,
1495   PREFIX_EVEX_0FDD,
1496   PREFIX_EVEX_0FDE,
1497   PREFIX_EVEX_0FDF,
1498   PREFIX_EVEX_0FE0,
1499   PREFIX_EVEX_0FE1,
1500   PREFIX_EVEX_0FE2,
1501   PREFIX_EVEX_0FE3,
1502   PREFIX_EVEX_0FE4,
1503   PREFIX_EVEX_0FE5,
1504   PREFIX_EVEX_0FE6,
1505   PREFIX_EVEX_0FE7,
1506   PREFIX_EVEX_0FE8,
1507   PREFIX_EVEX_0FE9,
1508   PREFIX_EVEX_0FEA,
1509   PREFIX_EVEX_0FEB,
1510   PREFIX_EVEX_0FEC,
1511   PREFIX_EVEX_0FED,
1512   PREFIX_EVEX_0FEE,
1513   PREFIX_EVEX_0FEF,
1514   PREFIX_EVEX_0FF1,
1515   PREFIX_EVEX_0FF2,
1516   PREFIX_EVEX_0FF3,
1517   PREFIX_EVEX_0FF4,
1518   PREFIX_EVEX_0FF5,
1519   PREFIX_EVEX_0FF6,
1520   PREFIX_EVEX_0FF8,
1521   PREFIX_EVEX_0FF9,
1522   PREFIX_EVEX_0FFA,
1523   PREFIX_EVEX_0FFB,
1524   PREFIX_EVEX_0FFC,
1525   PREFIX_EVEX_0FFD,
1526   PREFIX_EVEX_0FFE,
1527   PREFIX_EVEX_0F3800,
1528   PREFIX_EVEX_0F3804,
1529   PREFIX_EVEX_0F380B,
1530   PREFIX_EVEX_0F380C,
1531   PREFIX_EVEX_0F380D,
1532   PREFIX_EVEX_0F3810,
1533   PREFIX_EVEX_0F3811,
1534   PREFIX_EVEX_0F3812,
1535   PREFIX_EVEX_0F3813,
1536   PREFIX_EVEX_0F3814,
1537   PREFIX_EVEX_0F3815,
1538   PREFIX_EVEX_0F3816,
1539   PREFIX_EVEX_0F3818,
1540   PREFIX_EVEX_0F3819,
1541   PREFIX_EVEX_0F381A,
1542   PREFIX_EVEX_0F381B,
1543   PREFIX_EVEX_0F381C,
1544   PREFIX_EVEX_0F381D,
1545   PREFIX_EVEX_0F381E,
1546   PREFIX_EVEX_0F381F,
1547   PREFIX_EVEX_0F3820,
1548   PREFIX_EVEX_0F3821,
1549   PREFIX_EVEX_0F3822,
1550   PREFIX_EVEX_0F3823,
1551   PREFIX_EVEX_0F3824,
1552   PREFIX_EVEX_0F3825,
1553   PREFIX_EVEX_0F3826,
1554   PREFIX_EVEX_0F3827,
1555   PREFIX_EVEX_0F3828,
1556   PREFIX_EVEX_0F3829,
1557   PREFIX_EVEX_0F382A,
1558   PREFIX_EVEX_0F382B,
1559   PREFIX_EVEX_0F382C,
1560   PREFIX_EVEX_0F382D,
1561   PREFIX_EVEX_0F3830,
1562   PREFIX_EVEX_0F3831,
1563   PREFIX_EVEX_0F3832,
1564   PREFIX_EVEX_0F3833,
1565   PREFIX_EVEX_0F3834,
1566   PREFIX_EVEX_0F3835,
1567   PREFIX_EVEX_0F3836,
1568   PREFIX_EVEX_0F3837,
1569   PREFIX_EVEX_0F3838,
1570   PREFIX_EVEX_0F3839,
1571   PREFIX_EVEX_0F383A,
1572   PREFIX_EVEX_0F383B,
1573   PREFIX_EVEX_0F383C,
1574   PREFIX_EVEX_0F383D,
1575   PREFIX_EVEX_0F383E,
1576   PREFIX_EVEX_0F383F,
1577   PREFIX_EVEX_0F3840,
1578   PREFIX_EVEX_0F3842,
1579   PREFIX_EVEX_0F3843,
1580   PREFIX_EVEX_0F3844,
1581   PREFIX_EVEX_0F3845,
1582   PREFIX_EVEX_0F3846,
1583   PREFIX_EVEX_0F3847,
1584   PREFIX_EVEX_0F384C,
1585   PREFIX_EVEX_0F384D,
1586   PREFIX_EVEX_0F384E,
1587   PREFIX_EVEX_0F384F,
1588   PREFIX_EVEX_0F3850,
1589   PREFIX_EVEX_0F3851,
1590   PREFIX_EVEX_0F3852,
1591   PREFIX_EVEX_0F3853,
1592   PREFIX_EVEX_0F3854,
1593   PREFIX_EVEX_0F3855,
1594   PREFIX_EVEX_0F3858,
1595   PREFIX_EVEX_0F3859,
1596   PREFIX_EVEX_0F385A,
1597   PREFIX_EVEX_0F385B,
1598   PREFIX_EVEX_0F3862,
1599   PREFIX_EVEX_0F3863,
1600   PREFIX_EVEX_0F3864,
1601   PREFIX_EVEX_0F3865,
1602   PREFIX_EVEX_0F3866,
1603   PREFIX_EVEX_0F3868,
1604   PREFIX_EVEX_0F3870,
1605   PREFIX_EVEX_0F3871,
1606   PREFIX_EVEX_0F3872,
1607   PREFIX_EVEX_0F3873,
1608   PREFIX_EVEX_0F3875,
1609   PREFIX_EVEX_0F3876,
1610   PREFIX_EVEX_0F3877,
1611   PREFIX_EVEX_0F3878,
1612   PREFIX_EVEX_0F3879,
1613   PREFIX_EVEX_0F387A,
1614   PREFIX_EVEX_0F387B,
1615   PREFIX_EVEX_0F387C,
1616   PREFIX_EVEX_0F387D,
1617   PREFIX_EVEX_0F387E,
1618   PREFIX_EVEX_0F387F,
1619   PREFIX_EVEX_0F3883,
1620   PREFIX_EVEX_0F3888,
1621   PREFIX_EVEX_0F3889,
1622   PREFIX_EVEX_0F388A,
1623   PREFIX_EVEX_0F388B,
1624   PREFIX_EVEX_0F388D,
1625   PREFIX_EVEX_0F388F,
1626   PREFIX_EVEX_0F3890,
1627   PREFIX_EVEX_0F3891,
1628   PREFIX_EVEX_0F3892,
1629   PREFIX_EVEX_0F3893,
1630   PREFIX_EVEX_0F3896,
1631   PREFIX_EVEX_0F3897,
1632   PREFIX_EVEX_0F3898,
1633   PREFIX_EVEX_0F3899,
1634   PREFIX_EVEX_0F389A,
1635   PREFIX_EVEX_0F389B,
1636   PREFIX_EVEX_0F389C,
1637   PREFIX_EVEX_0F389D,
1638   PREFIX_EVEX_0F389E,
1639   PREFIX_EVEX_0F389F,
1640   PREFIX_EVEX_0F38A0,
1641   PREFIX_EVEX_0F38A1,
1642   PREFIX_EVEX_0F38A2,
1643   PREFIX_EVEX_0F38A3,
1644   PREFIX_EVEX_0F38A6,
1645   PREFIX_EVEX_0F38A7,
1646   PREFIX_EVEX_0F38A8,
1647   PREFIX_EVEX_0F38A9,
1648   PREFIX_EVEX_0F38AA,
1649   PREFIX_EVEX_0F38AB,
1650   PREFIX_EVEX_0F38AC,
1651   PREFIX_EVEX_0F38AD,
1652   PREFIX_EVEX_0F38AE,
1653   PREFIX_EVEX_0F38AF,
1654   PREFIX_EVEX_0F38B4,
1655   PREFIX_EVEX_0F38B5,
1656   PREFIX_EVEX_0F38B6,
1657   PREFIX_EVEX_0F38B7,
1658   PREFIX_EVEX_0F38B8,
1659   PREFIX_EVEX_0F38B9,
1660   PREFIX_EVEX_0F38BA,
1661   PREFIX_EVEX_0F38BB,
1662   PREFIX_EVEX_0F38BC,
1663   PREFIX_EVEX_0F38BD,
1664   PREFIX_EVEX_0F38BE,
1665   PREFIX_EVEX_0F38BF,
1666   PREFIX_EVEX_0F38C4,
1667   PREFIX_EVEX_0F38C6_REG_1,
1668   PREFIX_EVEX_0F38C6_REG_2,
1669   PREFIX_EVEX_0F38C6_REG_5,
1670   PREFIX_EVEX_0F38C6_REG_6,
1671   PREFIX_EVEX_0F38C7_REG_1,
1672   PREFIX_EVEX_0F38C7_REG_2,
1673   PREFIX_EVEX_0F38C7_REG_5,
1674   PREFIX_EVEX_0F38C7_REG_6,
1675   PREFIX_EVEX_0F38C8,
1676   PREFIX_EVEX_0F38CA,
1677   PREFIX_EVEX_0F38CB,
1678   PREFIX_EVEX_0F38CC,
1679   PREFIX_EVEX_0F38CD,
1680   PREFIX_EVEX_0F38CF,
1681   PREFIX_EVEX_0F38DC,
1682   PREFIX_EVEX_0F38DD,
1683   PREFIX_EVEX_0F38DE,
1684   PREFIX_EVEX_0F38DF,
1685
1686   PREFIX_EVEX_0F3A00,
1687   PREFIX_EVEX_0F3A01,
1688   PREFIX_EVEX_0F3A03,
1689   PREFIX_EVEX_0F3A04,
1690   PREFIX_EVEX_0F3A05,
1691   PREFIX_EVEX_0F3A08,
1692   PREFIX_EVEX_0F3A09,
1693   PREFIX_EVEX_0F3A0A,
1694   PREFIX_EVEX_0F3A0B,
1695   PREFIX_EVEX_0F3A0F,
1696   PREFIX_EVEX_0F3A14,
1697   PREFIX_EVEX_0F3A15,
1698   PREFIX_EVEX_0F3A16,
1699   PREFIX_EVEX_0F3A17,
1700   PREFIX_EVEX_0F3A18,
1701   PREFIX_EVEX_0F3A19,
1702   PREFIX_EVEX_0F3A1A,
1703   PREFIX_EVEX_0F3A1B,
1704   PREFIX_EVEX_0F3A1D,
1705   PREFIX_EVEX_0F3A1E,
1706   PREFIX_EVEX_0F3A1F,
1707   PREFIX_EVEX_0F3A20,
1708   PREFIX_EVEX_0F3A21,
1709   PREFIX_EVEX_0F3A22,
1710   PREFIX_EVEX_0F3A23,
1711   PREFIX_EVEX_0F3A25,
1712   PREFIX_EVEX_0F3A26,
1713   PREFIX_EVEX_0F3A27,
1714   PREFIX_EVEX_0F3A38,
1715   PREFIX_EVEX_0F3A39,
1716   PREFIX_EVEX_0F3A3A,
1717   PREFIX_EVEX_0F3A3B,
1718   PREFIX_EVEX_0F3A3E,
1719   PREFIX_EVEX_0F3A3F,
1720   PREFIX_EVEX_0F3A42,
1721   PREFIX_EVEX_0F3A43,
1722   PREFIX_EVEX_0F3A44,
1723   PREFIX_EVEX_0F3A50,
1724   PREFIX_EVEX_0F3A51,
1725   PREFIX_EVEX_0F3A54,
1726   PREFIX_EVEX_0F3A55,
1727   PREFIX_EVEX_0F3A56,
1728   PREFIX_EVEX_0F3A57,
1729   PREFIX_EVEX_0F3A66,
1730   PREFIX_EVEX_0F3A67,
1731   PREFIX_EVEX_0F3A70,
1732   PREFIX_EVEX_0F3A71,
1733   PREFIX_EVEX_0F3A72,
1734   PREFIX_EVEX_0F3A73,
1735   PREFIX_EVEX_0F3ACE,
1736   PREFIX_EVEX_0F3ACF
1737 };
1738
1739 enum
1740 {
1741   X86_64_06 = 0,
1742   X86_64_07,
1743   X86_64_0D,
1744   X86_64_16,
1745   X86_64_17,
1746   X86_64_1E,
1747   X86_64_1F,
1748   X86_64_27,
1749   X86_64_2F,
1750   X86_64_37,
1751   X86_64_3F,
1752   X86_64_60,
1753   X86_64_61,
1754   X86_64_62,
1755   X86_64_63,
1756   X86_64_6D,
1757   X86_64_6F,
1758   X86_64_82,
1759   X86_64_9A,
1760   X86_64_C2,
1761   X86_64_C3,
1762   X86_64_C4,
1763   X86_64_C5,
1764   X86_64_CE,
1765   X86_64_D4,
1766   X86_64_D5,
1767   X86_64_E8,
1768   X86_64_E9,
1769   X86_64_EA,
1770   X86_64_0F01_REG_0,
1771   X86_64_0F01_REG_1,
1772   X86_64_0F01_REG_2,
1773   X86_64_0F01_REG_3
1774 };
1775
1776 enum
1777 {
1778   THREE_BYTE_0F38 = 0,
1779   THREE_BYTE_0F3A
1780 };
1781
1782 enum
1783 {
1784   XOP_08 = 0,
1785   XOP_09,
1786   XOP_0A
1787 };
1788
1789 enum
1790 {
1791   VEX_0F = 0,
1792   VEX_0F38,
1793   VEX_0F3A
1794 };
1795
1796 enum
1797 {
1798   EVEX_0F = 0,
1799   EVEX_0F38,
1800   EVEX_0F3A
1801 };
1802
1803 enum
1804 {
1805   VEX_LEN_0F12_P_0_M_0 = 0,
1806   VEX_LEN_0F12_P_0_M_1,
1807   VEX_LEN_0F12_P_2,
1808   VEX_LEN_0F13_M_0,
1809   VEX_LEN_0F16_P_0_M_0,
1810   VEX_LEN_0F16_P_0_M_1,
1811   VEX_LEN_0F16_P_2,
1812   VEX_LEN_0F17_M_0,
1813   VEX_LEN_0F41_P_0,
1814   VEX_LEN_0F41_P_2,
1815   VEX_LEN_0F42_P_0,
1816   VEX_LEN_0F42_P_2,
1817   VEX_LEN_0F44_P_0,
1818   VEX_LEN_0F44_P_2,
1819   VEX_LEN_0F45_P_0,
1820   VEX_LEN_0F45_P_2,
1821   VEX_LEN_0F46_P_0,
1822   VEX_LEN_0F46_P_2,
1823   VEX_LEN_0F47_P_0,
1824   VEX_LEN_0F47_P_2,
1825   VEX_LEN_0F4A_P_0,
1826   VEX_LEN_0F4A_P_2,
1827   VEX_LEN_0F4B_P_0,
1828   VEX_LEN_0F4B_P_2,
1829   VEX_LEN_0F6E_P_2,
1830   VEX_LEN_0F77_P_0,
1831   VEX_LEN_0F7E_P_1,
1832   VEX_LEN_0F7E_P_2,
1833   VEX_LEN_0F90_P_0,
1834   VEX_LEN_0F90_P_2,
1835   VEX_LEN_0F91_P_0,
1836   VEX_LEN_0F91_P_2,
1837   VEX_LEN_0F92_P_0,
1838   VEX_LEN_0F92_P_2,
1839   VEX_LEN_0F92_P_3,
1840   VEX_LEN_0F93_P_0,
1841   VEX_LEN_0F93_P_2,
1842   VEX_LEN_0F93_P_3,
1843   VEX_LEN_0F98_P_0,
1844   VEX_LEN_0F98_P_2,
1845   VEX_LEN_0F99_P_0,
1846   VEX_LEN_0F99_P_2,
1847   VEX_LEN_0FAE_R_2_M_0,
1848   VEX_LEN_0FAE_R_3_M_0,
1849   VEX_LEN_0FC4_P_2,
1850   VEX_LEN_0FC5_P_2,
1851   VEX_LEN_0FD6_P_2,
1852   VEX_LEN_0FF7_P_2,
1853   VEX_LEN_0F3816_P_2,
1854   VEX_LEN_0F3819_P_2,
1855   VEX_LEN_0F381A_P_2_M_0,
1856   VEX_LEN_0F3836_P_2,
1857   VEX_LEN_0F3841_P_2,
1858   VEX_LEN_0F385A_P_2_M_0,
1859   VEX_LEN_0F38DB_P_2,
1860   VEX_LEN_0F38F2_P_0,
1861   VEX_LEN_0F38F3_R_1_P_0,
1862   VEX_LEN_0F38F3_R_2_P_0,
1863   VEX_LEN_0F38F3_R_3_P_0,
1864   VEX_LEN_0F38F5_P_0,
1865   VEX_LEN_0F38F5_P_1,
1866   VEX_LEN_0F38F5_P_3,
1867   VEX_LEN_0F38F6_P_3,
1868   VEX_LEN_0F38F7_P_0,
1869   VEX_LEN_0F38F7_P_1,
1870   VEX_LEN_0F38F7_P_2,
1871   VEX_LEN_0F38F7_P_3,
1872   VEX_LEN_0F3A00_P_2,
1873   VEX_LEN_0F3A01_P_2,
1874   VEX_LEN_0F3A06_P_2,
1875   VEX_LEN_0F3A14_P_2,
1876   VEX_LEN_0F3A15_P_2,
1877   VEX_LEN_0F3A16_P_2,
1878   VEX_LEN_0F3A17_P_2,
1879   VEX_LEN_0F3A18_P_2,
1880   VEX_LEN_0F3A19_P_2,
1881   VEX_LEN_0F3A20_P_2,
1882   VEX_LEN_0F3A21_P_2,
1883   VEX_LEN_0F3A22_P_2,
1884   VEX_LEN_0F3A30_P_2,
1885   VEX_LEN_0F3A31_P_2,
1886   VEX_LEN_0F3A32_P_2,
1887   VEX_LEN_0F3A33_P_2,
1888   VEX_LEN_0F3A38_P_2,
1889   VEX_LEN_0F3A39_P_2,
1890   VEX_LEN_0F3A41_P_2,
1891   VEX_LEN_0F3A46_P_2,
1892   VEX_LEN_0F3A60_P_2,
1893   VEX_LEN_0F3A61_P_2,
1894   VEX_LEN_0F3A62_P_2,
1895   VEX_LEN_0F3A63_P_2,
1896   VEX_LEN_0F3A6A_P_2,
1897   VEX_LEN_0F3A6B_P_2,
1898   VEX_LEN_0F3A6E_P_2,
1899   VEX_LEN_0F3A6F_P_2,
1900   VEX_LEN_0F3A7A_P_2,
1901   VEX_LEN_0F3A7B_P_2,
1902   VEX_LEN_0F3A7E_P_2,
1903   VEX_LEN_0F3A7F_P_2,
1904   VEX_LEN_0F3ADF_P_2,
1905   VEX_LEN_0F3AF0_P_3,
1906   VEX_LEN_0FXOP_08_CC,
1907   VEX_LEN_0FXOP_08_CD,
1908   VEX_LEN_0FXOP_08_CE,
1909   VEX_LEN_0FXOP_08_CF,
1910   VEX_LEN_0FXOP_08_EC,
1911   VEX_LEN_0FXOP_08_ED,
1912   VEX_LEN_0FXOP_08_EE,
1913   VEX_LEN_0FXOP_08_EF,
1914   VEX_LEN_0FXOP_09_80,
1915   VEX_LEN_0FXOP_09_81
1916 };
1917
1918 enum
1919 {
1920   EVEX_LEN_0F6E_P_2 = 0,
1921   EVEX_LEN_0F7E_P_1,
1922   EVEX_LEN_0F7E_P_2,
1923   EVEX_LEN_0FD6_P_2,
1924   EVEX_LEN_0F3819_P_2_W_0,
1925   EVEX_LEN_0F3819_P_2_W_1,
1926   EVEX_LEN_0F381A_P_2_W_0,
1927   EVEX_LEN_0F381A_P_2_W_1,
1928   EVEX_LEN_0F381B_P_2_W_0,
1929   EVEX_LEN_0F381B_P_2_W_1,
1930   EVEX_LEN_0F385A_P_2_W_0,
1931   EVEX_LEN_0F385A_P_2_W_1,
1932   EVEX_LEN_0F385B_P_2_W_0,
1933   EVEX_LEN_0F385B_P_2_W_1,
1934   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1935   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1936   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1937   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1938   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1939   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1940   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1941   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1942   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1943   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1944   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1945   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1946   EVEX_LEN_0F3A18_P_2_W_0,
1947   EVEX_LEN_0F3A18_P_2_W_1,
1948   EVEX_LEN_0F3A19_P_2_W_0,
1949   EVEX_LEN_0F3A19_P_2_W_1,
1950   EVEX_LEN_0F3A1A_P_2_W_0,
1951   EVEX_LEN_0F3A1A_P_2_W_1,
1952   EVEX_LEN_0F3A1B_P_2_W_0,
1953   EVEX_LEN_0F3A1B_P_2_W_1,
1954   EVEX_LEN_0F3A23_P_2_W_0,
1955   EVEX_LEN_0F3A23_P_2_W_1,
1956   EVEX_LEN_0F3A38_P_2_W_0,
1957   EVEX_LEN_0F3A38_P_2_W_1,
1958   EVEX_LEN_0F3A39_P_2_W_0,
1959   EVEX_LEN_0F3A39_P_2_W_1,
1960   EVEX_LEN_0F3A3A_P_2_W_0,
1961   EVEX_LEN_0F3A3A_P_2_W_1,
1962   EVEX_LEN_0F3A3B_P_2_W_0,
1963   EVEX_LEN_0F3A3B_P_2_W_1,
1964   EVEX_LEN_0F3A43_P_2_W_0,
1965   EVEX_LEN_0F3A43_P_2_W_1
1966 };
1967
1968 enum
1969 {
1970   VEX_W_0F41_P_0_LEN_1 = 0,
1971   VEX_W_0F41_P_2_LEN_1,
1972   VEX_W_0F42_P_0_LEN_1,
1973   VEX_W_0F42_P_2_LEN_1,
1974   VEX_W_0F44_P_0_LEN_0,
1975   VEX_W_0F44_P_2_LEN_0,
1976   VEX_W_0F45_P_0_LEN_1,
1977   VEX_W_0F45_P_2_LEN_1,
1978   VEX_W_0F46_P_0_LEN_1,
1979   VEX_W_0F46_P_2_LEN_1,
1980   VEX_W_0F47_P_0_LEN_1,
1981   VEX_W_0F47_P_2_LEN_1,
1982   VEX_W_0F4A_P_0_LEN_1,
1983   VEX_W_0F4A_P_2_LEN_1,
1984   VEX_W_0F4B_P_0_LEN_1,
1985   VEX_W_0F4B_P_2_LEN_1,
1986   VEX_W_0F90_P_0_LEN_0,
1987   VEX_W_0F90_P_2_LEN_0,
1988   VEX_W_0F91_P_0_LEN_0,
1989   VEX_W_0F91_P_2_LEN_0,
1990   VEX_W_0F92_P_0_LEN_0,
1991   VEX_W_0F92_P_2_LEN_0,
1992   VEX_W_0F93_P_0_LEN_0,
1993   VEX_W_0F93_P_2_LEN_0,
1994   VEX_W_0F98_P_0_LEN_0,
1995   VEX_W_0F98_P_2_LEN_0,
1996   VEX_W_0F99_P_0_LEN_0,
1997   VEX_W_0F99_P_2_LEN_0,
1998   VEX_W_0F380C_P_2,
1999   VEX_W_0F380D_P_2,
2000   VEX_W_0F380E_P_2,
2001   VEX_W_0F380F_P_2,
2002   VEX_W_0F3816_P_2,
2003   VEX_W_0F3818_P_2,
2004   VEX_W_0F3819_P_2,
2005   VEX_W_0F381A_P_2_M_0,
2006   VEX_W_0F382C_P_2_M_0,
2007   VEX_W_0F382D_P_2_M_0,
2008   VEX_W_0F382E_P_2_M_0,
2009   VEX_W_0F382F_P_2_M_0,
2010   VEX_W_0F3836_P_2,
2011   VEX_W_0F3846_P_2,
2012   VEX_W_0F3858_P_2,
2013   VEX_W_0F3859_P_2,
2014   VEX_W_0F385A_P_2_M_0,
2015   VEX_W_0F3878_P_2,
2016   VEX_W_0F3879_P_2,
2017   VEX_W_0F38CF_P_2,
2018   VEX_W_0F3A00_P_2,
2019   VEX_W_0F3A01_P_2,
2020   VEX_W_0F3A02_P_2,
2021   VEX_W_0F3A04_P_2,
2022   VEX_W_0F3A05_P_2,
2023   VEX_W_0F3A06_P_2,
2024   VEX_W_0F3A18_P_2,
2025   VEX_W_0F3A19_P_2,
2026   VEX_W_0F3A30_P_2_LEN_0,
2027   VEX_W_0F3A31_P_2_LEN_0,
2028   VEX_W_0F3A32_P_2_LEN_0,
2029   VEX_W_0F3A33_P_2_LEN_0,
2030   VEX_W_0F3A38_P_2,
2031   VEX_W_0F3A39_P_2,
2032   VEX_W_0F3A46_P_2,
2033   VEX_W_0F3A48_P_2,
2034   VEX_W_0F3A49_P_2,
2035   VEX_W_0F3A4A_P_2,
2036   VEX_W_0F3A4B_P_2,
2037   VEX_W_0F3A4C_P_2,
2038   VEX_W_0F3ACE_P_2,
2039   VEX_W_0F3ACF_P_2,
2040
2041   EVEX_W_0F10_P_0,
2042   EVEX_W_0F10_P_1,
2043   EVEX_W_0F10_P_2,
2044   EVEX_W_0F10_P_3,
2045   EVEX_W_0F11_P_0,
2046   EVEX_W_0F11_P_1,
2047   EVEX_W_0F11_P_2,
2048   EVEX_W_0F11_P_3,
2049   EVEX_W_0F12_P_0_M_0,
2050   EVEX_W_0F12_P_0_M_1,
2051   EVEX_W_0F12_P_1,
2052   EVEX_W_0F12_P_2,
2053   EVEX_W_0F12_P_3,
2054   EVEX_W_0F13_P_0,
2055   EVEX_W_0F13_P_2,
2056   EVEX_W_0F14_P_0,
2057   EVEX_W_0F14_P_2,
2058   EVEX_W_0F15_P_0,
2059   EVEX_W_0F15_P_2,
2060   EVEX_W_0F16_P_0_M_0,
2061   EVEX_W_0F16_P_0_M_1,
2062   EVEX_W_0F16_P_1,
2063   EVEX_W_0F16_P_2,
2064   EVEX_W_0F17_P_0,
2065   EVEX_W_0F17_P_2,
2066   EVEX_W_0F28_P_0,
2067   EVEX_W_0F28_P_2,
2068   EVEX_W_0F29_P_0,
2069   EVEX_W_0F29_P_2,
2070   EVEX_W_0F2A_P_3,
2071   EVEX_W_0F2B_P_0,
2072   EVEX_W_0F2B_P_2,
2073   EVEX_W_0F2E_P_0,
2074   EVEX_W_0F2E_P_2,
2075   EVEX_W_0F2F_P_0,
2076   EVEX_W_0F2F_P_2,
2077   EVEX_W_0F51_P_0,
2078   EVEX_W_0F51_P_1,
2079   EVEX_W_0F51_P_2,
2080   EVEX_W_0F51_P_3,
2081   EVEX_W_0F54_P_0,
2082   EVEX_W_0F54_P_2,
2083   EVEX_W_0F55_P_0,
2084   EVEX_W_0F55_P_2,
2085   EVEX_W_0F56_P_0,
2086   EVEX_W_0F56_P_2,
2087   EVEX_W_0F57_P_0,
2088   EVEX_W_0F57_P_2,
2089   EVEX_W_0F58_P_0,
2090   EVEX_W_0F58_P_1,
2091   EVEX_W_0F58_P_2,
2092   EVEX_W_0F58_P_3,
2093   EVEX_W_0F59_P_0,
2094   EVEX_W_0F59_P_1,
2095   EVEX_W_0F59_P_2,
2096   EVEX_W_0F59_P_3,
2097   EVEX_W_0F5A_P_0,
2098   EVEX_W_0F5A_P_1,
2099   EVEX_W_0F5A_P_2,
2100   EVEX_W_0F5A_P_3,
2101   EVEX_W_0F5B_P_0,
2102   EVEX_W_0F5B_P_1,
2103   EVEX_W_0F5B_P_2,
2104   EVEX_W_0F5C_P_0,
2105   EVEX_W_0F5C_P_1,
2106   EVEX_W_0F5C_P_2,
2107   EVEX_W_0F5C_P_3,
2108   EVEX_W_0F5D_P_0,
2109   EVEX_W_0F5D_P_1,
2110   EVEX_W_0F5D_P_2,
2111   EVEX_W_0F5D_P_3,
2112   EVEX_W_0F5E_P_0,
2113   EVEX_W_0F5E_P_1,
2114   EVEX_W_0F5E_P_2,
2115   EVEX_W_0F5E_P_3,
2116   EVEX_W_0F5F_P_0,
2117   EVEX_W_0F5F_P_1,
2118   EVEX_W_0F5F_P_2,
2119   EVEX_W_0F5F_P_3,
2120   EVEX_W_0F62_P_2,
2121   EVEX_W_0F66_P_2,
2122   EVEX_W_0F6A_P_2,
2123   EVEX_W_0F6B_P_2,
2124   EVEX_W_0F6C_P_2,
2125   EVEX_W_0F6D_P_2,
2126   EVEX_W_0F6F_P_1,
2127   EVEX_W_0F6F_P_2,
2128   EVEX_W_0F6F_P_3,
2129   EVEX_W_0F70_P_2,
2130   EVEX_W_0F72_R_2_P_2,
2131   EVEX_W_0F72_R_6_P_2,
2132   EVEX_W_0F73_R_2_P_2,
2133   EVEX_W_0F73_R_6_P_2,
2134   EVEX_W_0F76_P_2,
2135   EVEX_W_0F78_P_0,
2136   EVEX_W_0F78_P_2,
2137   EVEX_W_0F79_P_0,
2138   EVEX_W_0F79_P_2,
2139   EVEX_W_0F7A_P_1,
2140   EVEX_W_0F7A_P_2,
2141   EVEX_W_0F7A_P_3,
2142   EVEX_W_0F7B_P_2,
2143   EVEX_W_0F7B_P_3,
2144   EVEX_W_0F7E_P_1,
2145   EVEX_W_0F7F_P_1,
2146   EVEX_W_0F7F_P_2,
2147   EVEX_W_0F7F_P_3,
2148   EVEX_W_0FC2_P_0,
2149   EVEX_W_0FC2_P_1,
2150   EVEX_W_0FC2_P_2,
2151   EVEX_W_0FC2_P_3,
2152   EVEX_W_0FC6_P_0,
2153   EVEX_W_0FC6_P_2,
2154   EVEX_W_0FD2_P_2,
2155   EVEX_W_0FD3_P_2,
2156   EVEX_W_0FD4_P_2,
2157   EVEX_W_0FD6_P_2,
2158   EVEX_W_0FE6_P_1,
2159   EVEX_W_0FE6_P_2,
2160   EVEX_W_0FE6_P_3,
2161   EVEX_W_0FE7_P_2,
2162   EVEX_W_0FF2_P_2,
2163   EVEX_W_0FF3_P_2,
2164   EVEX_W_0FF4_P_2,
2165   EVEX_W_0FFA_P_2,
2166   EVEX_W_0FFB_P_2,
2167   EVEX_W_0FFE_P_2,
2168   EVEX_W_0F380C_P_2,
2169   EVEX_W_0F380D_P_2,
2170   EVEX_W_0F3810_P_1,
2171   EVEX_W_0F3810_P_2,
2172   EVEX_W_0F3811_P_1,
2173   EVEX_W_0F3811_P_2,
2174   EVEX_W_0F3812_P_1,
2175   EVEX_W_0F3812_P_2,
2176   EVEX_W_0F3813_P_1,
2177   EVEX_W_0F3813_P_2,
2178   EVEX_W_0F3814_P_1,
2179   EVEX_W_0F3815_P_1,
2180   EVEX_W_0F3818_P_2,
2181   EVEX_W_0F3819_P_2,
2182   EVEX_W_0F381A_P_2,
2183   EVEX_W_0F381B_P_2,
2184   EVEX_W_0F381E_P_2,
2185   EVEX_W_0F381F_P_2,
2186   EVEX_W_0F3820_P_1,
2187   EVEX_W_0F3821_P_1,
2188   EVEX_W_0F3822_P_1,
2189   EVEX_W_0F3823_P_1,
2190   EVEX_W_0F3824_P_1,
2191   EVEX_W_0F3825_P_1,
2192   EVEX_W_0F3825_P_2,
2193   EVEX_W_0F3826_P_1,
2194   EVEX_W_0F3826_P_2,
2195   EVEX_W_0F3828_P_1,
2196   EVEX_W_0F3828_P_2,
2197   EVEX_W_0F3829_P_1,
2198   EVEX_W_0F3829_P_2,
2199   EVEX_W_0F382A_P_1,
2200   EVEX_W_0F382A_P_2,
2201   EVEX_W_0F382B_P_2,
2202   EVEX_W_0F3830_P_1,
2203   EVEX_W_0F3831_P_1,
2204   EVEX_W_0F3832_P_1,
2205   EVEX_W_0F3833_P_1,
2206   EVEX_W_0F3834_P_1,
2207   EVEX_W_0F3835_P_1,
2208   EVEX_W_0F3835_P_2,
2209   EVEX_W_0F3837_P_2,
2210   EVEX_W_0F3838_P_1,
2211   EVEX_W_0F3839_P_1,
2212   EVEX_W_0F383A_P_1,
2213   EVEX_W_0F3840_P_2,
2214   EVEX_W_0F3852_P_1,
2215   EVEX_W_0F3854_P_2,
2216   EVEX_W_0F3855_P_2,
2217   EVEX_W_0F3858_P_2,
2218   EVEX_W_0F3859_P_2,
2219   EVEX_W_0F385A_P_2,
2220   EVEX_W_0F385B_P_2,
2221   EVEX_W_0F3862_P_2,
2222   EVEX_W_0F3863_P_2,
2223   EVEX_W_0F3866_P_2,
2224   EVEX_W_0F3868_P_3,
2225   EVEX_W_0F3870_P_2,
2226   EVEX_W_0F3871_P_2,
2227   EVEX_W_0F3872_P_1,
2228   EVEX_W_0F3872_P_2,
2229   EVEX_W_0F3872_P_3,
2230   EVEX_W_0F3873_P_2,
2231   EVEX_W_0F3875_P_2,
2232   EVEX_W_0F3878_P_2,
2233   EVEX_W_0F3879_P_2,
2234   EVEX_W_0F387A_P_2,
2235   EVEX_W_0F387B_P_2,
2236   EVEX_W_0F387D_P_2,
2237   EVEX_W_0F3883_P_2,
2238   EVEX_W_0F388D_P_2,
2239   EVEX_W_0F3891_P_2,
2240   EVEX_W_0F3893_P_2,
2241   EVEX_W_0F38A1_P_2,
2242   EVEX_W_0F38A3_P_2,
2243   EVEX_W_0F38C7_R_1_P_2,
2244   EVEX_W_0F38C7_R_2_P_2,
2245   EVEX_W_0F38C7_R_5_P_2,
2246   EVEX_W_0F38C7_R_6_P_2,
2247
2248   EVEX_W_0F3A00_P_2,
2249   EVEX_W_0F3A01_P_2,
2250   EVEX_W_0F3A04_P_2,
2251   EVEX_W_0F3A05_P_2,
2252   EVEX_W_0F3A08_P_2,
2253   EVEX_W_0F3A09_P_2,
2254   EVEX_W_0F3A0A_P_2,
2255   EVEX_W_0F3A0B_P_2,
2256   EVEX_W_0F3A18_P_2,
2257   EVEX_W_0F3A19_P_2,
2258   EVEX_W_0F3A1A_P_2,
2259   EVEX_W_0F3A1B_P_2,
2260   EVEX_W_0F3A1D_P_2,
2261   EVEX_W_0F3A21_P_2,
2262   EVEX_W_0F3A23_P_2,
2263   EVEX_W_0F3A38_P_2,
2264   EVEX_W_0F3A39_P_2,
2265   EVEX_W_0F3A3A_P_2,
2266   EVEX_W_0F3A3B_P_2,
2267   EVEX_W_0F3A3E_P_2,
2268   EVEX_W_0F3A3F_P_2,
2269   EVEX_W_0F3A42_P_2,
2270   EVEX_W_0F3A43_P_2,
2271   EVEX_W_0F3A50_P_2,
2272   EVEX_W_0F3A51_P_2,
2273   EVEX_W_0F3A56_P_2,
2274   EVEX_W_0F3A57_P_2,
2275   EVEX_W_0F3A66_P_2,
2276   EVEX_W_0F3A67_P_2,
2277   EVEX_W_0F3A70_P_2,
2278   EVEX_W_0F3A71_P_2,
2279   EVEX_W_0F3A72_P_2,
2280   EVEX_W_0F3A73_P_2,
2281   EVEX_W_0F3ACE_P_2,
2282   EVEX_W_0F3ACF_P_2
2283 };
2284
2285 typedef void (*op_rtn) (int bytemode, int sizeflag);
2286
2287 struct dis386 {
2288   const char *name;
2289   struct
2290     {
2291       op_rtn rtn;
2292       int bytemode;
2293     } op[MAX_OPERANDS];
2294   unsigned int prefix_requirement;
2295 };
2296
2297 /* Upper case letters in the instruction names here are macros.
2298    'A' => print 'b' if no register operands or suffix_always is true
2299    'B' => print 'b' if suffix_always is true
2300    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2301           size prefix
2302    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2303           suffix_always is true
2304    'E' => print 'e' if 32-bit form of jcxz
2305    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2306    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2307    'H' => print ",pt" or ",pn" branch hint
2308    'I' => honor following macro letter even in Intel mode (implemented only
2309           for some of the macro letters)
2310    'J' => print 'l'
2311    'K' => print 'd' or 'q' if rex prefix is present.
2312    'L' => print 'l' if suffix_always is true
2313    'M' => print 'r' if intel_mnemonic is false.
2314    'N' => print 'n' if instruction has no wait "prefix"
2315    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2316    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2317           or suffix_always is true.  print 'q' if rex prefix is present.
2318    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2319           is true
2320    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2321    'S' => print 'w', 'l' or 'q' if suffix_always is true
2322    'T' => print 'q' in 64bit mode if instruction has no operand size
2323           prefix and behave as 'P' otherwise
2324    'U' => print 'q' in 64bit mode if instruction has no operand size
2325           prefix and behave as 'Q' otherwise
2326    'V' => print 'q' in 64bit mode if instruction has no operand size
2327           prefix and behave as 'S' otherwise
2328    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2329    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2330    'Y' unused.
2331    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2332    '!' => change condition from true to false or from false to true.
2333    '%' => add 1 upper case letter to the macro.
2334    '^' => print 'w' or 'l' depending on operand size prefix or
2335           suffix_always is true (lcall/ljmp).
2336    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2337           on operand size prefix.
2338    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2339           has no operand size prefix for AMD64 ISA, behave as 'P'
2340           otherwise
2341
2342    2 upper case letter macros:
2343    "XY" => print 'x' or 'y' if suffix_always is true or no register
2344            operands and no broadcast.
2345    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2346            register operands and no broadcast.
2347    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2348    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2349            or suffix_always is true
2350    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2351    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2352    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2353    "LW" => print 'd', 'q' depending on the VEX.W bit
2354    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2355            an operand size prefix, or suffix_always is true.  print
2356            'q' if rex prefix is present.
2357
2358    Many of the above letters print nothing in Intel mode.  See "putop"
2359    for the details.
2360
2361    Braces '{' and '}', and vertical bars '|', indicate alternative
2362    mnemonic strings for AT&T and Intel.  */
2363
2364 static const struct dis386 dis386[] = {
2365   /* 00 */
2366   { "addB",             { Ebh1, Gb }, 0 },
2367   { "addS",             { Evh1, Gv }, 0 },
2368   { "addB",             { Gb, EbS }, 0 },
2369   { "addS",             { Gv, EvS }, 0 },
2370   { "addB",             { AL, Ib }, 0 },
2371   { "addS",             { eAX, Iv }, 0 },
2372   { X86_64_TABLE (X86_64_06) },
2373   { X86_64_TABLE (X86_64_07) },
2374   /* 08 */
2375   { "orB",              { Ebh1, Gb }, 0 },
2376   { "orS",              { Evh1, Gv }, 0 },
2377   { "orB",              { Gb, EbS }, 0 },
2378   { "orS",              { Gv, EvS }, 0 },
2379   { "orB",              { AL, Ib }, 0 },
2380   { "orS",              { eAX, Iv }, 0 },
2381   { X86_64_TABLE (X86_64_0D) },
2382   { Bad_Opcode },       /* 0x0f extended opcode escape */
2383   /* 10 */
2384   { "adcB",             { Ebh1, Gb }, 0 },
2385   { "adcS",             { Evh1, Gv }, 0 },
2386   { "adcB",             { Gb, EbS }, 0 },
2387   { "adcS",             { Gv, EvS }, 0 },
2388   { "adcB",             { AL, Ib }, 0 },
2389   { "adcS",             { eAX, Iv }, 0 },
2390   { X86_64_TABLE (X86_64_16) },
2391   { X86_64_TABLE (X86_64_17) },
2392   /* 18 */
2393   { "sbbB",             { Ebh1, Gb }, 0 },
2394   { "sbbS",             { Evh1, Gv }, 0 },
2395   { "sbbB",             { Gb, EbS }, 0 },
2396   { "sbbS",             { Gv, EvS }, 0 },
2397   { "sbbB",             { AL, Ib }, 0 },
2398   { "sbbS",             { eAX, Iv }, 0 },
2399   { X86_64_TABLE (X86_64_1E) },
2400   { X86_64_TABLE (X86_64_1F) },
2401   /* 20 */
2402   { "andB",             { Ebh1, Gb }, 0 },
2403   { "andS",             { Evh1, Gv }, 0 },
2404   { "andB",             { Gb, EbS }, 0 },
2405   { "andS",             { Gv, EvS }, 0 },
2406   { "andB",             { AL, Ib }, 0 },
2407   { "andS",             { eAX, Iv }, 0 },
2408   { Bad_Opcode },       /* SEG ES prefix */
2409   { X86_64_TABLE (X86_64_27) },
2410   /* 28 */
2411   { "subB",             { Ebh1, Gb }, 0 },
2412   { "subS",             { Evh1, Gv }, 0 },
2413   { "subB",             { Gb, EbS }, 0 },
2414   { "subS",             { Gv, EvS }, 0 },
2415   { "subB",             { AL, Ib }, 0 },
2416   { "subS",             { eAX, Iv }, 0 },
2417   { Bad_Opcode },       /* SEG CS prefix */
2418   { X86_64_TABLE (X86_64_2F) },
2419   /* 30 */
2420   { "xorB",             { Ebh1, Gb }, 0 },
2421   { "xorS",             { Evh1, Gv }, 0 },
2422   { "xorB",             { Gb, EbS }, 0 },
2423   { "xorS",             { Gv, EvS }, 0 },
2424   { "xorB",             { AL, Ib }, 0 },
2425   { "xorS",             { eAX, Iv }, 0 },
2426   { Bad_Opcode },       /* SEG SS prefix */
2427   { X86_64_TABLE (X86_64_37) },
2428   /* 38 */
2429   { "cmpB",             { Eb, Gb }, 0 },
2430   { "cmpS",             { Ev, Gv }, 0 },
2431   { "cmpB",             { Gb, EbS }, 0 },
2432   { "cmpS",             { Gv, EvS }, 0 },
2433   { "cmpB",             { AL, Ib }, 0 },
2434   { "cmpS",             { eAX, Iv }, 0 },
2435   { Bad_Opcode },       /* SEG DS prefix */
2436   { X86_64_TABLE (X86_64_3F) },
2437   /* 40 */
2438   { "inc{S|}",          { RMeAX }, 0 },
2439   { "inc{S|}",          { RMeCX }, 0 },
2440   { "inc{S|}",          { RMeDX }, 0 },
2441   { "inc{S|}",          { RMeBX }, 0 },
2442   { "inc{S|}",          { RMeSP }, 0 },
2443   { "inc{S|}",          { RMeBP }, 0 },
2444   { "inc{S|}",          { RMeSI }, 0 },
2445   { "inc{S|}",          { RMeDI }, 0 },
2446   /* 48 */
2447   { "dec{S|}",          { RMeAX }, 0 },
2448   { "dec{S|}",          { RMeCX }, 0 },
2449   { "dec{S|}",          { RMeDX }, 0 },
2450   { "dec{S|}",          { RMeBX }, 0 },
2451   { "dec{S|}",          { RMeSP }, 0 },
2452   { "dec{S|}",          { RMeBP }, 0 },
2453   { "dec{S|}",          { RMeSI }, 0 },
2454   { "dec{S|}",          { RMeDI }, 0 },
2455   /* 50 */
2456   { "pushV",            { RMrAX }, 0 },
2457   { "pushV",            { RMrCX }, 0 },
2458   { "pushV",            { RMrDX }, 0 },
2459   { "pushV",            { RMrBX }, 0 },
2460   { "pushV",            { RMrSP }, 0 },
2461   { "pushV",            { RMrBP }, 0 },
2462   { "pushV",            { RMrSI }, 0 },
2463   { "pushV",            { RMrDI }, 0 },
2464   /* 58 */
2465   { "popV",             { RMrAX }, 0 },
2466   { "popV",             { RMrCX }, 0 },
2467   { "popV",             { RMrDX }, 0 },
2468   { "popV",             { RMrBX }, 0 },
2469   { "popV",             { RMrSP }, 0 },
2470   { "popV",             { RMrBP }, 0 },
2471   { "popV",             { RMrSI }, 0 },
2472   { "popV",             { RMrDI }, 0 },
2473   /* 60 */
2474   { X86_64_TABLE (X86_64_60) },
2475   { X86_64_TABLE (X86_64_61) },
2476   { X86_64_TABLE (X86_64_62) },
2477   { X86_64_TABLE (X86_64_63) },
2478   { Bad_Opcode },       /* seg fs */
2479   { Bad_Opcode },       /* seg gs */
2480   { Bad_Opcode },       /* op size prefix */
2481   { Bad_Opcode },       /* adr size prefix */
2482   /* 68 */
2483   { "pushT",            { sIv }, 0 },
2484   { "imulS",            { Gv, Ev, Iv }, 0 },
2485   { "pushT",            { sIbT }, 0 },
2486   { "imulS",            { Gv, Ev, sIb }, 0 },
2487   { "ins{b|}",          { Ybr, indirDX }, 0 },
2488   { X86_64_TABLE (X86_64_6D) },
2489   { "outs{b|}",         { indirDXr, Xb }, 0 },
2490   { X86_64_TABLE (X86_64_6F) },
2491   /* 70 */
2492   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2493   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2494   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2495   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2496   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2497   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2498   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2499   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2500   /* 78 */
2501   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2502   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2503   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2504   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2505   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2506   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2507   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2508   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2509   /* 80 */
2510   { REG_TABLE (REG_80) },
2511   { REG_TABLE (REG_81) },
2512   { X86_64_TABLE (X86_64_82) },
2513   { REG_TABLE (REG_83) },
2514   { "testB",            { Eb, Gb }, 0 },
2515   { "testS",            { Ev, Gv }, 0 },
2516   { "xchgB",            { Ebh2, Gb }, 0 },
2517   { "xchgS",            { Evh2, Gv }, 0 },
2518   /* 88 */
2519   { "movB",             { Ebh3, Gb }, 0 },
2520   { "movS",             { Evh3, Gv }, 0 },
2521   { "movB",             { Gb, EbS }, 0 },
2522   { "movS",             { Gv, EvS }, 0 },
2523   { "movD",             { Sv, Sw }, 0 },
2524   { MOD_TABLE (MOD_8D) },
2525   { "movD",             { Sw, Sv }, 0 },
2526   { REG_TABLE (REG_8F) },
2527   /* 90 */
2528   { PREFIX_TABLE (PREFIX_90) },
2529   { "xchgS",            { RMeCX, eAX }, 0 },
2530   { "xchgS",            { RMeDX, eAX }, 0 },
2531   { "xchgS",            { RMeBX, eAX }, 0 },
2532   { "xchgS",            { RMeSP, eAX }, 0 },
2533   { "xchgS",            { RMeBP, eAX }, 0 },
2534   { "xchgS",            { RMeSI, eAX }, 0 },
2535   { "xchgS",            { RMeDI, eAX }, 0 },
2536   /* 98 */
2537   { "cW{t|}R",          { XX }, 0 },
2538   { "cR{t|}O",          { XX }, 0 },
2539   { X86_64_TABLE (X86_64_9A) },
2540   { Bad_Opcode },       /* fwait */
2541   { "pushfT",           { XX }, 0 },
2542   { "popfT",            { XX }, 0 },
2543   { "sahf",             { XX }, 0 },
2544   { "lahf",             { XX }, 0 },
2545   /* a0 */
2546   { "mov%LB",           { AL, Ob }, 0 },
2547   { "mov%LS",           { eAX, Ov }, 0 },
2548   { "mov%LB",           { Ob, AL }, 0 },
2549   { "mov%LS",           { Ov, eAX }, 0 },
2550   { "movs{b|}",         { Ybr, Xb }, 0 },
2551   { "movs{R|}",         { Yvr, Xv }, 0 },
2552   { "cmps{b|}",         { Xb, Yb }, 0 },
2553   { "cmps{R|}",         { Xv, Yv }, 0 },
2554   /* a8 */
2555   { "testB",            { AL, Ib }, 0 },
2556   { "testS",            { eAX, Iv }, 0 },
2557   { "stosB",            { Ybr, AL }, 0 },
2558   { "stosS",            { Yvr, eAX }, 0 },
2559   { "lodsB",            { ALr, Xb }, 0 },
2560   { "lodsS",            { eAXr, Xv }, 0 },
2561   { "scasB",            { AL, Yb }, 0 },
2562   { "scasS",            { eAX, Yv }, 0 },
2563   /* b0 */
2564   { "movB",             { RMAL, Ib }, 0 },
2565   { "movB",             { RMCL, Ib }, 0 },
2566   { "movB",             { RMDL, Ib }, 0 },
2567   { "movB",             { RMBL, Ib }, 0 },
2568   { "movB",             { RMAH, Ib }, 0 },
2569   { "movB",             { RMCH, Ib }, 0 },
2570   { "movB",             { RMDH, Ib }, 0 },
2571   { "movB",             { RMBH, Ib }, 0 },
2572   /* b8 */
2573   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2574   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2575   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2576   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2577   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2578   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2579   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2580   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2581   /* c0 */
2582   { REG_TABLE (REG_C0) },
2583   { REG_TABLE (REG_C1) },
2584   { X86_64_TABLE (X86_64_C2) },
2585   { X86_64_TABLE (X86_64_C3) },
2586   { X86_64_TABLE (X86_64_C4) },
2587   { X86_64_TABLE (X86_64_C5) },
2588   { REG_TABLE (REG_C6) },
2589   { REG_TABLE (REG_C7) },
2590   /* c8 */
2591   { "enterT",           { Iw, Ib }, 0 },
2592   { "leaveT",           { XX }, 0 },
2593   { "Jret{|f}P",        { Iw }, 0 },
2594   { "Jret{|f}P",        { XX }, 0 },
2595   { "int3",             { XX }, 0 },
2596   { "int",              { Ib }, 0 },
2597   { X86_64_TABLE (X86_64_CE) },
2598   { "iret%LP",          { XX }, 0 },
2599   /* d0 */
2600   { REG_TABLE (REG_D0) },
2601   { REG_TABLE (REG_D1) },
2602   { REG_TABLE (REG_D2) },
2603   { REG_TABLE (REG_D3) },
2604   { X86_64_TABLE (X86_64_D4) },
2605   { X86_64_TABLE (X86_64_D5) },
2606   { Bad_Opcode },
2607   { "xlat",             { DSBX }, 0 },
2608   /* d8 */
2609   { FLOAT },
2610   { FLOAT },
2611   { FLOAT },
2612   { FLOAT },
2613   { FLOAT },
2614   { FLOAT },
2615   { FLOAT },
2616   { FLOAT },
2617   /* e0 */
2618   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2619   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2620   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2621   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2622   { "inB",              { AL, Ib }, 0 },
2623   { "inG",              { zAX, Ib }, 0 },
2624   { "outB",             { Ib, AL }, 0 },
2625   { "outG",             { Ib, zAX }, 0 },
2626   /* e8 */
2627   { X86_64_TABLE (X86_64_E8) },
2628   { X86_64_TABLE (X86_64_E9) },
2629   { X86_64_TABLE (X86_64_EA) },
2630   { "jmp",              { Jb, BND }, 0 },
2631   { "inB",              { AL, indirDX }, 0 },
2632   { "inG",              { zAX, indirDX }, 0 },
2633   { "outB",             { indirDX, AL }, 0 },
2634   { "outG",             { indirDX, zAX }, 0 },
2635   /* f0 */
2636   { Bad_Opcode },       /* lock prefix */
2637   { "icebp",            { XX }, 0 },
2638   { Bad_Opcode },       /* repne */
2639   { Bad_Opcode },       /* repz */
2640   { "hlt",              { XX }, 0 },
2641   { "cmc",              { XX }, 0 },
2642   { REG_TABLE (REG_F6) },
2643   { REG_TABLE (REG_F7) },
2644   /* f8 */
2645   { "clc",              { XX }, 0 },
2646   { "stc",              { XX }, 0 },
2647   { "cli",              { XX }, 0 },
2648   { "sti",              { XX }, 0 },
2649   { "cld",              { XX }, 0 },
2650   { "std",              { XX }, 0 },
2651   { REG_TABLE (REG_FE) },
2652   { REG_TABLE (REG_FF) },
2653 };
2654
2655 static const struct dis386 dis386_twobyte[] = {
2656   /* 00 */
2657   { REG_TABLE (REG_0F00 ) },
2658   { REG_TABLE (REG_0F01 ) },
2659   { "larS",             { Gv, Ew }, 0 },
2660   { "lslS",             { Gv, Ew }, 0 },
2661   { Bad_Opcode },
2662   { "syscall",          { XX }, 0 },
2663   { "clts",             { XX }, 0 },
2664   { "sysret%LP",                { XX }, 0 },
2665   /* 08 */
2666   { "invd",             { XX }, 0 },
2667   { PREFIX_TABLE (PREFIX_0F09) },
2668   { Bad_Opcode },
2669   { "ud2",              { XX }, 0 },
2670   { Bad_Opcode },
2671   { REG_TABLE (REG_0F0D) },
2672   { "femms",            { XX }, 0 },
2673   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2674   /* 10 */
2675   { PREFIX_TABLE (PREFIX_0F10) },
2676   { PREFIX_TABLE (PREFIX_0F11) },
2677   { PREFIX_TABLE (PREFIX_0F12) },
2678   { MOD_TABLE (MOD_0F13) },
2679   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2680   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2681   { PREFIX_TABLE (PREFIX_0F16) },
2682   { MOD_TABLE (MOD_0F17) },
2683   /* 18 */
2684   { REG_TABLE (REG_0F18) },
2685   { "nopQ",             { Ev }, 0 },
2686   { PREFIX_TABLE (PREFIX_0F1A) },
2687   { PREFIX_TABLE (PREFIX_0F1B) },
2688   { PREFIX_TABLE (PREFIX_0F1C) },
2689   { "nopQ",             { Ev }, 0 },
2690   { PREFIX_TABLE (PREFIX_0F1E) },
2691   { "nopQ",             { Ev }, 0 },
2692   /* 20 */
2693   { "movZ",             { Rm, Cm }, 0 },
2694   { "movZ",             { Rm, Dm }, 0 },
2695   { "movZ",             { Cm, Rm }, 0 },
2696   { "movZ",             { Dm, Rm }, 0 },
2697   { MOD_TABLE (MOD_0F24) },
2698   { Bad_Opcode },
2699   { MOD_TABLE (MOD_0F26) },
2700   { Bad_Opcode },
2701   /* 28 */
2702   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2703   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2704   { PREFIX_TABLE (PREFIX_0F2A) },
2705   { PREFIX_TABLE (PREFIX_0F2B) },
2706   { PREFIX_TABLE (PREFIX_0F2C) },
2707   { PREFIX_TABLE (PREFIX_0F2D) },
2708   { PREFIX_TABLE (PREFIX_0F2E) },
2709   { PREFIX_TABLE (PREFIX_0F2F) },
2710   /* 30 */
2711   { "wrmsr",            { XX }, 0 },
2712   { "rdtsc",            { XX }, 0 },
2713   { "rdmsr",            { XX }, 0 },
2714   { "rdpmc",            { XX }, 0 },
2715   { "sysenter",         { SEP }, 0 },
2716   { "sysexit",          { SEP }, 0 },
2717   { Bad_Opcode },
2718   { "getsec",           { XX }, 0 },
2719   /* 38 */
2720   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2721   { Bad_Opcode },
2722   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2723   { Bad_Opcode },
2724   { Bad_Opcode },
2725   { Bad_Opcode },
2726   { Bad_Opcode },
2727   { Bad_Opcode },
2728   /* 40 */
2729   { "cmovoS",           { Gv, Ev }, 0 },
2730   { "cmovnoS",          { Gv, Ev }, 0 },
2731   { "cmovbS",           { Gv, Ev }, 0 },
2732   { "cmovaeS",          { Gv, Ev }, 0 },
2733   { "cmoveS",           { Gv, Ev }, 0 },
2734   { "cmovneS",          { Gv, Ev }, 0 },
2735   { "cmovbeS",          { Gv, Ev }, 0 },
2736   { "cmovaS",           { Gv, Ev }, 0 },
2737   /* 48 */
2738   { "cmovsS",           { Gv, Ev }, 0 },
2739   { "cmovnsS",          { Gv, Ev }, 0 },
2740   { "cmovpS",           { Gv, Ev }, 0 },
2741   { "cmovnpS",          { Gv, Ev }, 0 },
2742   { "cmovlS",           { Gv, Ev }, 0 },
2743   { "cmovgeS",          { Gv, Ev }, 0 },
2744   { "cmovleS",          { Gv, Ev }, 0 },
2745   { "cmovgS",           { Gv, Ev }, 0 },
2746   /* 50 */
2747   { MOD_TABLE (MOD_0F51) },
2748   { PREFIX_TABLE (PREFIX_0F51) },
2749   { PREFIX_TABLE (PREFIX_0F52) },
2750   { PREFIX_TABLE (PREFIX_0F53) },
2751   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2752   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2753   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2754   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2755   /* 58 */
2756   { PREFIX_TABLE (PREFIX_0F58) },
2757   { PREFIX_TABLE (PREFIX_0F59) },
2758   { PREFIX_TABLE (PREFIX_0F5A) },
2759   { PREFIX_TABLE (PREFIX_0F5B) },
2760   { PREFIX_TABLE (PREFIX_0F5C) },
2761   { PREFIX_TABLE (PREFIX_0F5D) },
2762   { PREFIX_TABLE (PREFIX_0F5E) },
2763   { PREFIX_TABLE (PREFIX_0F5F) },
2764   /* 60 */
2765   { PREFIX_TABLE (PREFIX_0F60) },
2766   { PREFIX_TABLE (PREFIX_0F61) },
2767   { PREFIX_TABLE (PREFIX_0F62) },
2768   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2769   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2770   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2771   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2772   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2773   /* 68 */
2774   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2775   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2776   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2777   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2778   { PREFIX_TABLE (PREFIX_0F6C) },
2779   { PREFIX_TABLE (PREFIX_0F6D) },
2780   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2781   { PREFIX_TABLE (PREFIX_0F6F) },
2782   /* 70 */
2783   { PREFIX_TABLE (PREFIX_0F70) },
2784   { REG_TABLE (REG_0F71) },
2785   { REG_TABLE (REG_0F72) },
2786   { REG_TABLE (REG_0F73) },
2787   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2788   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2789   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2790   { "emms",             { XX }, PREFIX_OPCODE },
2791   /* 78 */
2792   { PREFIX_TABLE (PREFIX_0F78) },
2793   { PREFIX_TABLE (PREFIX_0F79) },
2794   { Bad_Opcode },
2795   { Bad_Opcode },
2796   { PREFIX_TABLE (PREFIX_0F7C) },
2797   { PREFIX_TABLE (PREFIX_0F7D) },
2798   { PREFIX_TABLE (PREFIX_0F7E) },
2799   { PREFIX_TABLE (PREFIX_0F7F) },
2800   /* 80 */
2801   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2802   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2803   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2804   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2805   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2806   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2807   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2808   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2809   /* 88 */
2810   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2811   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2812   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2813   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2814   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2815   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2816   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2817   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2818   /* 90 */
2819   { "seto",             { Eb }, 0 },
2820   { "setno",            { Eb }, 0 },
2821   { "setb",             { Eb }, 0 },
2822   { "setae",            { Eb }, 0 },
2823   { "sete",             { Eb }, 0 },
2824   { "setne",            { Eb }, 0 },
2825   { "setbe",            { Eb }, 0 },
2826   { "seta",             { Eb }, 0 },
2827   /* 98 */
2828   { "sets",             { Eb }, 0 },
2829   { "setns",            { Eb }, 0 },
2830   { "setp",             { Eb }, 0 },
2831   { "setnp",            { Eb }, 0 },
2832   { "setl",             { Eb }, 0 },
2833   { "setge",            { Eb }, 0 },
2834   { "setle",            { Eb }, 0 },
2835   { "setg",             { Eb }, 0 },
2836   /* a0 */
2837   { "pushT",            { fs }, 0 },
2838   { "popT",             { fs }, 0 },
2839   { "cpuid",            { XX }, 0 },
2840   { "btS",              { Ev, Gv }, 0 },
2841   { "shldS",            { Ev, Gv, Ib }, 0 },
2842   { "shldS",            { Ev, Gv, CL }, 0 },
2843   { REG_TABLE (REG_0FA6) },
2844   { REG_TABLE (REG_0FA7) },
2845   /* a8 */
2846   { "pushT",            { gs }, 0 },
2847   { "popT",             { gs }, 0 },
2848   { "rsm",              { XX }, 0 },
2849   { "btsS",             { Evh1, Gv }, 0 },
2850   { "shrdS",            { Ev, Gv, Ib }, 0 },
2851   { "shrdS",            { Ev, Gv, CL }, 0 },
2852   { REG_TABLE (REG_0FAE) },
2853   { "imulS",            { Gv, Ev }, 0 },
2854   /* b0 */
2855   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2856   { "cmpxchgS",         { Evh1, Gv }, 0 },
2857   { MOD_TABLE (MOD_0FB2) },
2858   { "btrS",             { Evh1, Gv }, 0 },
2859   { MOD_TABLE (MOD_0FB4) },
2860   { MOD_TABLE (MOD_0FB5) },
2861   { "movz{bR|x}",       { Gv, Eb }, 0 },
2862   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2863   /* b8 */
2864   { PREFIX_TABLE (PREFIX_0FB8) },
2865   { "ud1S",             { Gv, Ev }, 0 },
2866   { REG_TABLE (REG_0FBA) },
2867   { "btcS",             { Evh1, Gv }, 0 },
2868   { PREFIX_TABLE (PREFIX_0FBC) },
2869   { PREFIX_TABLE (PREFIX_0FBD) },
2870   { "movs{bR|x}",       { Gv, Eb }, 0 },
2871   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2872   /* c0 */
2873   { "xaddB",            { Ebh1, Gb }, 0 },
2874   { "xaddS",            { Evh1, Gv }, 0 },
2875   { PREFIX_TABLE (PREFIX_0FC2) },
2876   { MOD_TABLE (MOD_0FC3) },
2877   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2878   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2879   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2880   { REG_TABLE (REG_0FC7) },
2881   /* c8 */
2882   { "bswap",            { RMeAX }, 0 },
2883   { "bswap",            { RMeCX }, 0 },
2884   { "bswap",            { RMeDX }, 0 },
2885   { "bswap",            { RMeBX }, 0 },
2886   { "bswap",            { RMeSP }, 0 },
2887   { "bswap",            { RMeBP }, 0 },
2888   { "bswap",            { RMeSI }, 0 },
2889   { "bswap",            { RMeDI }, 0 },
2890   /* d0 */
2891   { PREFIX_TABLE (PREFIX_0FD0) },
2892   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2893   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2894   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2895   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2896   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2897   { PREFIX_TABLE (PREFIX_0FD6) },
2898   { MOD_TABLE (MOD_0FD7) },
2899   /* d8 */
2900   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2901   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2902   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2903   { "pand",             { MX, EM }, PREFIX_OPCODE },
2904   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2905   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2906   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2907   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2908   /* e0 */
2909   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2910   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2911   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2912   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2913   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2914   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2915   { PREFIX_TABLE (PREFIX_0FE6) },
2916   { PREFIX_TABLE (PREFIX_0FE7) },
2917   /* e8 */
2918   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2919   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2920   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2921   { "por",              { MX, EM }, PREFIX_OPCODE },
2922   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2923   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2924   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2925   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2926   /* f0 */
2927   { PREFIX_TABLE (PREFIX_0FF0) },
2928   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2929   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2930   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2931   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2932   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2933   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2934   { PREFIX_TABLE (PREFIX_0FF7) },
2935   /* f8 */
2936   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2937   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2938   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2939   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2940   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2941   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2942   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2943   { "ud0S",             { Gv, Ev }, 0 },
2944 };
2945
2946 static const unsigned char onebyte_has_modrm[256] = {
2947   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2948   /*       -------------------------------        */
2949   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2950   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2951   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2952   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2953   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2954   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2955   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2956   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2957   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2958   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2959   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2960   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2961   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2962   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2963   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2964   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2965   /*       -------------------------------        */
2966   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2967 };
2968
2969 static const unsigned char twobyte_has_modrm[256] = {
2970   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2971   /*       -------------------------------        */
2972   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2973   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2974   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2975   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2976   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2977   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2978   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2979   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2980   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2981   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2982   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2983   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2984   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2985   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2986   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2987   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2988   /*       -------------------------------        */
2989   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2990 };
2991
2992 static char obuf[100];
2993 static char *obufp;
2994 static char *mnemonicendp;
2995 static char scratchbuf[100];
2996 static unsigned char *start_codep;
2997 static unsigned char *insn_codep;
2998 static unsigned char *codep;
2999 static unsigned char *end_codep;
3000 static int last_lock_prefix;
3001 static int last_repz_prefix;
3002 static int last_repnz_prefix;
3003 static int last_data_prefix;
3004 static int last_addr_prefix;
3005 static int last_rex_prefix;
3006 static int last_seg_prefix;
3007 static int fwait_prefix;
3008 /* The active segment register prefix.  */
3009 static int active_seg_prefix;
3010 #define MAX_CODE_LENGTH 15
3011 /* We can up to 14 prefixes since the maximum instruction length is
3012    15bytes.  */
3013 static int all_prefixes[MAX_CODE_LENGTH - 1];
3014 static disassemble_info *the_info;
3015 static struct
3016   {
3017     int mod;
3018     int reg;
3019     int rm;
3020   }
3021 modrm;
3022 static unsigned char need_modrm;
3023 static struct
3024   {
3025     int scale;
3026     int index;
3027     int base;
3028   }
3029 sib;
3030 static struct
3031   {
3032     int register_specifier;
3033     int length;
3034     int prefix;
3035     int w;
3036     int evex;
3037     int r;
3038     int v;
3039     int mask_register_specifier;
3040     int zeroing;
3041     int ll;
3042     int b;
3043   }
3044 vex;
3045 static unsigned char need_vex;
3046 static unsigned char need_vex_reg;
3047 static unsigned char vex_w_done;
3048
3049 struct op
3050   {
3051     const char *name;
3052     unsigned int len;
3053   };
3054
3055 /* If we are accessing mod/rm/reg without need_modrm set, then the
3056    values are stale.  Hitting this abort likely indicates that you
3057    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3058 #define MODRM_CHECK  if (!need_modrm) abort ()
3059
3060 static const char **names64;
3061 static const char **names32;
3062 static const char **names16;
3063 static const char **names8;
3064 static const char **names8rex;
3065 static const char **names_seg;
3066 static const char *index64;
3067 static const char *index32;
3068 static const char **index16;
3069 static const char **names_bnd;
3070
3071 static const char *intel_names64[] = {
3072   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3073   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3074 };
3075 static const char *intel_names32[] = {
3076   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3077   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3078 };
3079 static const char *intel_names16[] = {
3080   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3081   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3082 };
3083 static const char *intel_names8[] = {
3084   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3085 };
3086 static const char *intel_names8rex[] = {
3087   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3088   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3089 };
3090 static const char *intel_names_seg[] = {
3091   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3092 };
3093 static const char *intel_index64 = "riz";
3094 static const char *intel_index32 = "eiz";
3095 static const char *intel_index16[] = {
3096   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3097 };
3098
3099 static const char *att_names64[] = {
3100   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3101   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3102 };
3103 static const char *att_names32[] = {
3104   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3105   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3106 };
3107 static const char *att_names16[] = {
3108   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3109   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3110 };
3111 static const char *att_names8[] = {
3112   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3113 };
3114 static const char *att_names8rex[] = {
3115   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3116   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3117 };
3118 static const char *att_names_seg[] = {
3119   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3120 };
3121 static const char *att_index64 = "%riz";
3122 static const char *att_index32 = "%eiz";
3123 static const char *att_index16[] = {
3124   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3125 };
3126
3127 static const char **names_mm;
3128 static const char *intel_names_mm[] = {
3129   "mm0", "mm1", "mm2", "mm3",
3130   "mm4", "mm5", "mm6", "mm7"
3131 };
3132 static const char *att_names_mm[] = {
3133   "%mm0", "%mm1", "%mm2", "%mm3",
3134   "%mm4", "%mm5", "%mm6", "%mm7"
3135 };
3136
3137 static const char *intel_names_bnd[] = {
3138   "bnd0", "bnd1", "bnd2", "bnd3"
3139 };
3140
3141 static const char *att_names_bnd[] = {
3142   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3143 };
3144
3145 static const char **names_xmm;
3146 static const char *intel_names_xmm[] = {
3147   "xmm0", "xmm1", "xmm2", "xmm3",
3148   "xmm4", "xmm5", "xmm6", "xmm7",
3149   "xmm8", "xmm9", "xmm10", "xmm11",
3150   "xmm12", "xmm13", "xmm14", "xmm15",
3151   "xmm16", "xmm17", "xmm18", "xmm19",
3152   "xmm20", "xmm21", "xmm22", "xmm23",
3153   "xmm24", "xmm25", "xmm26", "xmm27",
3154   "xmm28", "xmm29", "xmm30", "xmm31"
3155 };
3156 static const char *att_names_xmm[] = {
3157   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3158   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3159   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3160   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3161   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3162   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3163   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3164   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3165 };
3166
3167 static const char **names_ymm;
3168 static const char *intel_names_ymm[] = {
3169   "ymm0", "ymm1", "ymm2", "ymm3",
3170   "ymm4", "ymm5", "ymm6", "ymm7",
3171   "ymm8", "ymm9", "ymm10", "ymm11",
3172   "ymm12", "ymm13", "ymm14", "ymm15",
3173   "ymm16", "ymm17", "ymm18", "ymm19",
3174   "ymm20", "ymm21", "ymm22", "ymm23",
3175   "ymm24", "ymm25", "ymm26", "ymm27",
3176   "ymm28", "ymm29", "ymm30", "ymm31"
3177 };
3178 static const char *att_names_ymm[] = {
3179   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3180   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3181   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3182   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3183   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3184   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3185   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3186   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3187 };
3188
3189 static const char **names_zmm;
3190 static const char *intel_names_zmm[] = {
3191   "zmm0", "zmm1", "zmm2", "zmm3",
3192   "zmm4", "zmm5", "zmm6", "zmm7",
3193   "zmm8", "zmm9", "zmm10", "zmm11",
3194   "zmm12", "zmm13", "zmm14", "zmm15",
3195   "zmm16", "zmm17", "zmm18", "zmm19",
3196   "zmm20", "zmm21", "zmm22", "zmm23",
3197   "zmm24", "zmm25", "zmm26", "zmm27",
3198   "zmm28", "zmm29", "zmm30", "zmm31"
3199 };
3200 static const char *att_names_zmm[] = {
3201   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3202   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3203   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3204   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3205   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3206   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3207   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3208   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3209 };
3210
3211 static const char **names_mask;
3212 static const char *intel_names_mask[] = {
3213   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3214 };
3215 static const char *att_names_mask[] = {
3216   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3217 };
3218
3219 static const char *names_rounding[] =
3220 {
3221   "{rn-sae}",
3222   "{rd-sae}",
3223   "{ru-sae}",
3224   "{rz-sae}"
3225 };
3226
3227 static const struct dis386 reg_table[][8] = {
3228   /* REG_80 */
3229   {
3230     { "addA",   { Ebh1, Ib }, 0 },
3231     { "orA",    { Ebh1, Ib }, 0 },
3232     { "adcA",   { Ebh1, Ib }, 0 },
3233     { "sbbA",   { Ebh1, Ib }, 0 },
3234     { "andA",   { Ebh1, Ib }, 0 },
3235     { "subA",   { Ebh1, Ib }, 0 },
3236     { "xorA",   { Ebh1, Ib }, 0 },
3237     { "cmpA",   { Eb, Ib }, 0 },
3238   },
3239   /* REG_81 */
3240   {
3241     { "addQ",   { Evh1, Iv }, 0 },
3242     { "orQ",    { Evh1, Iv }, 0 },
3243     { "adcQ",   { Evh1, Iv }, 0 },
3244     { "sbbQ",   { Evh1, Iv }, 0 },
3245     { "andQ",   { Evh1, Iv }, 0 },
3246     { "subQ",   { Evh1, Iv }, 0 },
3247     { "xorQ",   { Evh1, Iv }, 0 },
3248     { "cmpQ",   { Ev, Iv }, 0 },
3249   },
3250   /* REG_83 */
3251   {
3252     { "addQ",   { Evh1, sIb }, 0 },
3253     { "orQ",    { Evh1, sIb }, 0 },
3254     { "adcQ",   { Evh1, sIb }, 0 },
3255     { "sbbQ",   { Evh1, sIb }, 0 },
3256     { "andQ",   { Evh1, sIb }, 0 },
3257     { "subQ",   { Evh1, sIb }, 0 },
3258     { "xorQ",   { Evh1, sIb }, 0 },
3259     { "cmpQ",   { Ev, sIb }, 0 },
3260   },
3261   /* REG_8F */
3262   {
3263     { "popU",   { stackEv }, 0 },
3264     { XOP_8F_TABLE (XOP_09) },
3265     { Bad_Opcode },
3266     { Bad_Opcode },
3267     { Bad_Opcode },
3268     { XOP_8F_TABLE (XOP_09) },
3269   },
3270   /* REG_C0 */
3271   {
3272     { "rolA",   { Eb, Ib }, 0 },
3273     { "rorA",   { Eb, Ib }, 0 },
3274     { "rclA",   { Eb, Ib }, 0 },
3275     { "rcrA",   { Eb, Ib }, 0 },
3276     { "shlA",   { Eb, Ib }, 0 },
3277     { "shrA",   { Eb, Ib }, 0 },
3278     { "shlA",   { Eb, Ib }, 0 },
3279     { "sarA",   { Eb, Ib }, 0 },
3280   },
3281   /* REG_C1 */
3282   {
3283     { "rolQ",   { Ev, Ib }, 0 },
3284     { "rorQ",   { Ev, Ib }, 0 },
3285     { "rclQ",   { Ev, Ib }, 0 },
3286     { "rcrQ",   { Ev, Ib }, 0 },
3287     { "shlQ",   { Ev, Ib }, 0 },
3288     { "shrQ",   { Ev, Ib }, 0 },
3289     { "shlQ",   { Ev, Ib }, 0 },
3290     { "sarQ",   { Ev, Ib }, 0 },
3291   },
3292   /* REG_C6 */
3293   {
3294     { "movA",   { Ebh3, Ib }, 0 },
3295     { Bad_Opcode },
3296     { Bad_Opcode },
3297     { Bad_Opcode },
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { Bad_Opcode },
3301     { MOD_TABLE (MOD_C6_REG_7) },
3302   },
3303   /* REG_C7 */
3304   {
3305     { "movQ",   { Evh3, Iv }, 0 },
3306     { Bad_Opcode },
3307     { Bad_Opcode },
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { Bad_Opcode },
3311     { Bad_Opcode },
3312     { MOD_TABLE (MOD_C7_REG_7) },
3313   },
3314   /* REG_D0 */
3315   {
3316     { "rolA",   { Eb, I1 }, 0 },
3317     { "rorA",   { Eb, I1 }, 0 },
3318     { "rclA",   { Eb, I1 }, 0 },
3319     { "rcrA",   { Eb, I1 }, 0 },
3320     { "shlA",   { Eb, I1 }, 0 },
3321     { "shrA",   { Eb, I1 }, 0 },
3322     { "shlA",   { Eb, I1 }, 0 },
3323     { "sarA",   { Eb, I1 }, 0 },
3324   },
3325   /* REG_D1 */
3326   {
3327     { "rolQ",   { Ev, I1 }, 0 },
3328     { "rorQ",   { Ev, I1 }, 0 },
3329     { "rclQ",   { Ev, I1 }, 0 },
3330     { "rcrQ",   { Ev, I1 }, 0 },
3331     { "shlQ",   { Ev, I1 }, 0 },
3332     { "shrQ",   { Ev, I1 }, 0 },
3333     { "shlQ",   { Ev, I1 }, 0 },
3334     { "sarQ",   { Ev, I1 }, 0 },
3335   },
3336   /* REG_D2 */
3337   {
3338     { "rolA",   { Eb, CL }, 0 },
3339     { "rorA",   { Eb, CL }, 0 },
3340     { "rclA",   { Eb, CL }, 0 },
3341     { "rcrA",   { Eb, CL }, 0 },
3342     { "shlA",   { Eb, CL }, 0 },
3343     { "shrA",   { Eb, CL }, 0 },
3344     { "shlA",   { Eb, CL }, 0 },
3345     { "sarA",   { Eb, CL }, 0 },
3346   },
3347   /* REG_D3 */
3348   {
3349     { "rolQ",   { Ev, CL }, 0 },
3350     { "rorQ",   { Ev, CL }, 0 },
3351     { "rclQ",   { Ev, CL }, 0 },
3352     { "rcrQ",   { Ev, CL }, 0 },
3353     { "shlQ",   { Ev, CL }, 0 },
3354     { "shrQ",   { Ev, CL }, 0 },
3355     { "shlQ",   { Ev, CL }, 0 },
3356     { "sarQ",   { Ev, CL }, 0 },
3357   },
3358   /* REG_F6 */
3359   {
3360     { "testA",  { Eb, Ib }, 0 },
3361     { "testA",  { Eb, Ib }, 0 },
3362     { "notA",   { Ebh1 }, 0 },
3363     { "negA",   { Ebh1 }, 0 },
3364     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3365     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3366     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3367     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3368   },
3369   /* REG_F7 */
3370   {
3371     { "testQ",  { Ev, Iv }, 0 },
3372     { "testQ",  { Ev, Iv }, 0 },
3373     { "notQ",   { Evh1 }, 0 },
3374     { "negQ",   { Evh1 }, 0 },
3375     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3376     { "imulQ",  { Ev }, 0 },
3377     { "divQ",   { Ev }, 0 },
3378     { "idivQ",  { Ev }, 0 },
3379   },
3380   /* REG_FE */
3381   {
3382     { "incA",   { Ebh1 }, 0 },
3383     { "decA",   { Ebh1 }, 0 },
3384   },
3385   /* REG_FF */
3386   {
3387     { "incQ",   { Evh1 }, 0 },
3388     { "decQ",   { Evh1 }, 0 },
3389     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3390     { MOD_TABLE (MOD_FF_REG_3) },
3391     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3392     { MOD_TABLE (MOD_FF_REG_5) },
3393     { "pushU",  { stackEv }, 0 },
3394     { Bad_Opcode },
3395   },
3396   /* REG_0F00 */
3397   {
3398     { "sldtD",  { Sv }, 0 },
3399     { "strD",   { Sv }, 0 },
3400     { "lldt",   { Ew }, 0 },
3401     { "ltr",    { Ew }, 0 },
3402     { "verr",   { Ew }, 0 },
3403     { "verw",   { Ew }, 0 },
3404     { Bad_Opcode },
3405     { Bad_Opcode },
3406   },
3407   /* REG_0F01 */
3408   {
3409     { MOD_TABLE (MOD_0F01_REG_0) },
3410     { MOD_TABLE (MOD_0F01_REG_1) },
3411     { MOD_TABLE (MOD_0F01_REG_2) },
3412     { MOD_TABLE (MOD_0F01_REG_3) },
3413     { "smswD",  { Sv }, 0 },
3414     { MOD_TABLE (MOD_0F01_REG_5) },
3415     { "lmsw",   { Ew }, 0 },
3416     { MOD_TABLE (MOD_0F01_REG_7) },
3417   },
3418   /* REG_0F0D */
3419   {
3420     { "prefetch",       { Mb }, 0 },
3421     { "prefetchw",      { Mb }, 0 },
3422     { "prefetchwt1",    { Mb }, 0 },
3423     { "prefetch",       { Mb }, 0 },
3424     { "prefetch",       { Mb }, 0 },
3425     { "prefetch",       { Mb }, 0 },
3426     { "prefetch",       { Mb }, 0 },
3427     { "prefetch",       { Mb }, 0 },
3428   },
3429   /* REG_0F18 */
3430   {
3431     { MOD_TABLE (MOD_0F18_REG_0) },
3432     { MOD_TABLE (MOD_0F18_REG_1) },
3433     { MOD_TABLE (MOD_0F18_REG_2) },
3434     { MOD_TABLE (MOD_0F18_REG_3) },
3435     { MOD_TABLE (MOD_0F18_REG_4) },
3436     { MOD_TABLE (MOD_0F18_REG_5) },
3437     { MOD_TABLE (MOD_0F18_REG_6) },
3438     { MOD_TABLE (MOD_0F18_REG_7) },
3439   },
3440   /* REG_0F1C_P_0_MOD_0 */
3441   {
3442     { "cldemote",       { Mb }, 0 },
3443     { "nopQ",           { Ev }, 0 },
3444     { "nopQ",           { Ev }, 0 },
3445     { "nopQ",           { Ev }, 0 },
3446     { "nopQ",           { Ev }, 0 },
3447     { "nopQ",           { Ev }, 0 },
3448     { "nopQ",           { Ev }, 0 },
3449     { "nopQ",           { Ev }, 0 },
3450   },
3451   /* REG_0F1E_P_1_MOD_3 */
3452   {
3453     { "nopQ",           { Ev }, 0 },
3454     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3455     { "nopQ",           { Ev }, 0 },
3456     { "nopQ",           { Ev }, 0 },
3457     { "nopQ",           { Ev }, 0 },
3458     { "nopQ",           { Ev }, 0 },
3459     { "nopQ",           { Ev }, 0 },
3460     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3461   },
3462   /* REG_0F71 */
3463   {
3464     { Bad_Opcode },
3465     { Bad_Opcode },
3466     { MOD_TABLE (MOD_0F71_REG_2) },
3467     { Bad_Opcode },
3468     { MOD_TABLE (MOD_0F71_REG_4) },
3469     { Bad_Opcode },
3470     { MOD_TABLE (MOD_0F71_REG_6) },
3471   },
3472   /* REG_0F72 */
3473   {
3474     { Bad_Opcode },
3475     { Bad_Opcode },
3476     { MOD_TABLE (MOD_0F72_REG_2) },
3477     { Bad_Opcode },
3478     { MOD_TABLE (MOD_0F72_REG_4) },
3479     { Bad_Opcode },
3480     { MOD_TABLE (MOD_0F72_REG_6) },
3481   },
3482   /* REG_0F73 */
3483   {
3484     { Bad_Opcode },
3485     { Bad_Opcode },
3486     { MOD_TABLE (MOD_0F73_REG_2) },
3487     { MOD_TABLE (MOD_0F73_REG_3) },
3488     { Bad_Opcode },
3489     { Bad_Opcode },
3490     { MOD_TABLE (MOD_0F73_REG_6) },
3491     { MOD_TABLE (MOD_0F73_REG_7) },
3492   },
3493   /* REG_0FA6 */
3494   {
3495     { "montmul",        { { OP_0f07, 0 } }, 0 },
3496     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3497     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3498   },
3499   /* REG_0FA7 */
3500   {
3501     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3502     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3503     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3504     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3505     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3506     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3507   },
3508   /* REG_0FAE */
3509   {
3510     { MOD_TABLE (MOD_0FAE_REG_0) },
3511     { MOD_TABLE (MOD_0FAE_REG_1) },
3512     { MOD_TABLE (MOD_0FAE_REG_2) },
3513     { MOD_TABLE (MOD_0FAE_REG_3) },
3514     { MOD_TABLE (MOD_0FAE_REG_4) },
3515     { MOD_TABLE (MOD_0FAE_REG_5) },
3516     { MOD_TABLE (MOD_0FAE_REG_6) },
3517     { MOD_TABLE (MOD_0FAE_REG_7) },
3518   },
3519   /* REG_0FBA */
3520   {
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { Bad_Opcode },
3524     { Bad_Opcode },
3525     { "btQ",    { Ev, Ib }, 0 },
3526     { "btsQ",   { Evh1, Ib }, 0 },
3527     { "btrQ",   { Evh1, Ib }, 0 },
3528     { "btcQ",   { Evh1, Ib }, 0 },
3529   },
3530   /* REG_0FC7 */
3531   {
3532     { Bad_Opcode },
3533     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3534     { Bad_Opcode },
3535     { MOD_TABLE (MOD_0FC7_REG_3) },
3536     { MOD_TABLE (MOD_0FC7_REG_4) },
3537     { MOD_TABLE (MOD_0FC7_REG_5) },
3538     { MOD_TABLE (MOD_0FC7_REG_6) },
3539     { MOD_TABLE (MOD_0FC7_REG_7) },
3540   },
3541   /* REG_VEX_0F71 */
3542   {
3543     { Bad_Opcode },
3544     { Bad_Opcode },
3545     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3546     { Bad_Opcode },
3547     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3548     { Bad_Opcode },
3549     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3550   },
3551   /* REG_VEX_0F72 */
3552   {
3553     { Bad_Opcode },
3554     { Bad_Opcode },
3555     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3556     { Bad_Opcode },
3557     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3558     { Bad_Opcode },
3559     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3560   },
3561   /* REG_VEX_0F73 */
3562   {
3563     { Bad_Opcode },
3564     { Bad_Opcode },
3565     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3566     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3567     { Bad_Opcode },
3568     { Bad_Opcode },
3569     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3570     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3571   },
3572   /* REG_VEX_0FAE */
3573   {
3574     { Bad_Opcode },
3575     { Bad_Opcode },
3576     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3577     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3578   },
3579   /* REG_VEX_0F38F3 */
3580   {
3581     { Bad_Opcode },
3582     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3583     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3584     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3585   },
3586   /* REG_XOP_LWPCB */
3587   {
3588     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3589     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3590   },
3591   /* REG_XOP_LWP */
3592   {
3593     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3594     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3595   },
3596   /* REG_XOP_TBM_01 */
3597   {
3598     { Bad_Opcode },
3599     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3600     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3601     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3602     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3603     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3604     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3605     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3606   },
3607   /* REG_XOP_TBM_02 */
3608   {
3609     { Bad_Opcode },
3610     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3611     { Bad_Opcode },
3612     { Bad_Opcode },
3613     { Bad_Opcode },
3614     { Bad_Opcode },
3615     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3616   },
3617
3618 #include "i386-dis-evex-reg.h"
3619 };
3620
3621 static const struct dis386 prefix_table[][4] = {
3622   /* PREFIX_90 */
3623   {
3624     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3625     { "pause", { XX }, 0 },
3626     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3627     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3628   },
3629
3630   /* PREFIX_0F01_REG_5_MOD_0 */
3631   {
3632     { Bad_Opcode },
3633     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3634   },
3635
3636   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3637   {
3638     { Bad_Opcode },
3639     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3640   },
3641
3642   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3643   {
3644     { Bad_Opcode },
3645     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3646   },
3647
3648   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3649   {
3650     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3651     { "mcommit",        { Skip_MODRM }, 0 },
3652   },
3653
3654   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3655   {
3656     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3657   },
3658
3659   /* PREFIX_0F09 */
3660   {
3661     { "wbinvd",   { XX }, 0 },
3662     { "wbnoinvd", { XX }, 0 },
3663   },
3664
3665   /* PREFIX_0F10 */
3666   {
3667     { "movups", { XM, EXx }, PREFIX_OPCODE },
3668     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3669     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3670     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3671   },
3672
3673   /* PREFIX_0F11 */
3674   {
3675     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3676     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3677     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3678     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3679   },
3680
3681   /* PREFIX_0F12 */
3682   {
3683     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3684     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3685     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3686     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3687   },
3688
3689   /* PREFIX_0F16 */
3690   {
3691     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3692     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3693     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3694   },
3695
3696   /* PREFIX_0F1A */
3697   {
3698     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3699     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3700     { "bndmov", { Gbnd, Ebnd }, 0 },
3701     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3702   },
3703
3704   /* PREFIX_0F1B */
3705   {
3706     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3707     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3708     { "bndmov", { EbndS, Gbnd }, 0 },
3709     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3710   },
3711
3712   /* PREFIX_0F1C */
3713   {
3714     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3715     { "nopQ",   { Ev }, PREFIX_OPCODE },
3716     { "nopQ",   { Ev }, PREFIX_OPCODE },
3717     { "nopQ",   { Ev }, PREFIX_OPCODE },
3718   },
3719
3720   /* PREFIX_0F1E */
3721   {
3722     { "nopQ",   { Ev }, PREFIX_OPCODE },
3723     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3724     { "nopQ",   { Ev }, PREFIX_OPCODE },
3725     { "nopQ",   { Ev }, PREFIX_OPCODE },
3726   },
3727
3728   /* PREFIX_0F2A */
3729   {
3730     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3731     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3732     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3733     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3734   },
3735
3736   /* PREFIX_0F2B */
3737   {
3738     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3739     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3740     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3741     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3742   },
3743
3744   /* PREFIX_0F2C */
3745   {
3746     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3747     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3748     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3749     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3750   },
3751
3752   /* PREFIX_0F2D */
3753   {
3754     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3755     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3756     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3757     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3758   },
3759
3760   /* PREFIX_0F2E */
3761   {
3762     { "ucomiss",{ XM, EXd }, 0 },
3763     { Bad_Opcode },
3764     { "ucomisd",{ XM, EXq }, 0 },
3765   },
3766
3767   /* PREFIX_0F2F */
3768   {
3769     { "comiss", { XM, EXd }, 0 },
3770     { Bad_Opcode },
3771     { "comisd", { XM, EXq }, 0 },
3772   },
3773
3774   /* PREFIX_0F51 */
3775   {
3776     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3777     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3778     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3779     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3780   },
3781
3782   /* PREFIX_0F52 */
3783   {
3784     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3785     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3786   },
3787
3788   /* PREFIX_0F53 */
3789   {
3790     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3791     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3792   },
3793
3794   /* PREFIX_0F58 */
3795   {
3796     { "addps", { XM, EXx }, PREFIX_OPCODE },
3797     { "addss", { XM, EXd }, PREFIX_OPCODE },
3798     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3799     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3800   },
3801
3802   /* PREFIX_0F59 */
3803   {
3804     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3805     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3806     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3807     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3808   },
3809
3810   /* PREFIX_0F5A */
3811   {
3812     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3813     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3814     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3815     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3816   },
3817
3818   /* PREFIX_0F5B */
3819   {
3820     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3821     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3822     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3823   },
3824
3825   /* PREFIX_0F5C */
3826   {
3827     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3828     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3829     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3830     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3831   },
3832
3833   /* PREFIX_0F5D */
3834   {
3835     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3836     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3837     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3838     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3839   },
3840
3841   /* PREFIX_0F5E */
3842   {
3843     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3844     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3845     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3846     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3847   },
3848
3849   /* PREFIX_0F5F */
3850   {
3851     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3852     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3853     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3854     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3855   },
3856
3857   /* PREFIX_0F60 */
3858   {
3859     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3860     { Bad_Opcode },
3861     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3862   },
3863
3864   /* PREFIX_0F61 */
3865   {
3866     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3867     { Bad_Opcode },
3868     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3869   },
3870
3871   /* PREFIX_0F62 */
3872   {
3873     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3874     { Bad_Opcode },
3875     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3876   },
3877
3878   /* PREFIX_0F6C */
3879   {
3880     { Bad_Opcode },
3881     { Bad_Opcode },
3882     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3883   },
3884
3885   /* PREFIX_0F6D */
3886   {
3887     { Bad_Opcode },
3888     { Bad_Opcode },
3889     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3890   },
3891
3892   /* PREFIX_0F6F */
3893   {
3894     { "movq",   { MX, EM }, PREFIX_OPCODE },
3895     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3896     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3897   },
3898
3899   /* PREFIX_0F70 */
3900   {
3901     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3902     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3903     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3904     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3905   },
3906
3907   /* PREFIX_0F73_REG_3 */
3908   {
3909     { Bad_Opcode },
3910     { Bad_Opcode },
3911     { "psrldq", { XS, Ib }, 0 },
3912   },
3913
3914   /* PREFIX_0F73_REG_7 */
3915   {
3916     { Bad_Opcode },
3917     { Bad_Opcode },
3918     { "pslldq", { XS, Ib }, 0 },
3919   },
3920
3921   /* PREFIX_0F78 */
3922   {
3923     {"vmread",  { Em, Gm }, 0 },
3924     { Bad_Opcode },
3925     {"extrq",   { XS, Ib, Ib }, 0 },
3926     {"insertq", { XM, XS, Ib, Ib }, 0 },
3927   },
3928
3929   /* PREFIX_0F79 */
3930   {
3931     {"vmwrite", { Gm, Em }, 0 },
3932     { Bad_Opcode },
3933     {"extrq",   { XM, XS }, 0 },
3934     {"insertq", { XM, XS }, 0 },
3935   },
3936
3937   /* PREFIX_0F7C */
3938   {
3939     { Bad_Opcode },
3940     { Bad_Opcode },
3941     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3942     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3943   },
3944
3945   /* PREFIX_0F7D */
3946   {
3947     { Bad_Opcode },
3948     { Bad_Opcode },
3949     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3950     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3951   },
3952
3953   /* PREFIX_0F7E */
3954   {
3955     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3956     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3957     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3958   },
3959
3960   /* PREFIX_0F7F */
3961   {
3962     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3963     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3964     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3965   },
3966
3967   /* PREFIX_0FAE_REG_0_MOD_3 */
3968   {
3969     { Bad_Opcode },
3970     { "rdfsbase", { Ev }, 0 },
3971   },
3972
3973   /* PREFIX_0FAE_REG_1_MOD_3 */
3974   {
3975     { Bad_Opcode },
3976     { "rdgsbase", { Ev }, 0 },
3977   },
3978
3979   /* PREFIX_0FAE_REG_2_MOD_3 */
3980   {
3981     { Bad_Opcode },
3982     { "wrfsbase", { Ev }, 0 },
3983   },
3984
3985   /* PREFIX_0FAE_REG_3_MOD_3 */
3986   {
3987     { Bad_Opcode },
3988     { "wrgsbase", { Ev }, 0 },
3989   },
3990
3991   /* PREFIX_0FAE_REG_4_MOD_0 */
3992   {
3993     { "xsave",  { FXSAVE }, 0 },
3994     { "ptwrite%LQ", { Edq }, 0 },
3995   },
3996
3997   /* PREFIX_0FAE_REG_4_MOD_3 */
3998   {
3999     { Bad_Opcode },
4000     { "ptwrite%LQ", { Edq }, 0 },
4001   },
4002
4003   /* PREFIX_0FAE_REG_5_MOD_0 */
4004   {
4005     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4006   },
4007
4008   /* PREFIX_0FAE_REG_5_MOD_3 */
4009   {
4010     { "lfence",         { Skip_MODRM }, 0 },
4011     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4012   },
4013
4014   /* PREFIX_0FAE_REG_6_MOD_0 */
4015   {
4016     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4017     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4018     { "clwb",   { Mb }, PREFIX_OPCODE },
4019   },
4020
4021   /* PREFIX_0FAE_REG_6_MOD_3 */
4022   {
4023     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
4024     { "umonitor",       { Eva }, PREFIX_OPCODE },
4025     { "tpause", { Edq }, PREFIX_OPCODE },
4026     { "umwait", { Edq }, PREFIX_OPCODE },
4027   },
4028
4029   /* PREFIX_0FAE_REG_7_MOD_0 */
4030   {
4031     { "clflush",        { Mb }, 0 },
4032     { Bad_Opcode },
4033     { "clflushopt",     { Mb }, 0 },
4034   },
4035
4036   /* PREFIX_0FB8 */
4037   {
4038     { Bad_Opcode },
4039     { "popcntS", { Gv, Ev }, 0 },
4040   },
4041
4042   /* PREFIX_0FBC */
4043   {
4044     { "bsfS",   { Gv, Ev }, 0 },
4045     { "tzcntS", { Gv, Ev }, 0 },
4046     { "bsfS",   { Gv, Ev }, 0 },
4047   },
4048
4049   /* PREFIX_0FBD */
4050   {
4051     { "bsrS",   { Gv, Ev }, 0 },
4052     { "lzcntS", { Gv, Ev }, 0 },
4053     { "bsrS",   { Gv, Ev }, 0 },
4054   },
4055
4056   /* PREFIX_0FC2 */
4057   {
4058     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4059     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4060     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4061     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4062   },
4063
4064   /* PREFIX_0FC3_MOD_0 */
4065   {
4066     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4067   },
4068
4069   /* PREFIX_0FC7_REG_6_MOD_0 */
4070   {
4071     { "vmptrld",{ Mq }, 0 },
4072     { "vmxon",  { Mq }, 0 },
4073     { "vmclear",{ Mq }, 0 },
4074   },
4075
4076   /* PREFIX_0FC7_REG_6_MOD_3 */
4077   {
4078     { "rdrand", { Ev }, 0 },
4079     { Bad_Opcode },
4080     { "rdrand", { Ev }, 0 }
4081   },
4082
4083   /* PREFIX_0FC7_REG_7_MOD_3 */
4084   {
4085     { "rdseed", { Ev }, 0 },
4086     { "rdpid",  { Em }, 0 },
4087     { "rdseed", { Ev }, 0 },
4088   },
4089
4090   /* PREFIX_0FD0 */
4091   {
4092     { Bad_Opcode },
4093     { Bad_Opcode },
4094     { "addsubpd", { XM, EXx }, 0 },
4095     { "addsubps", { XM, EXx }, 0 },
4096   },
4097
4098   /* PREFIX_0FD6 */
4099   {
4100     { Bad_Opcode },
4101     { "movq2dq",{ XM, MS }, 0 },
4102     { "movq",   { EXqS, XM }, 0 },
4103     { "movdq2q",{ MX, XS }, 0 },
4104   },
4105
4106   /* PREFIX_0FE6 */
4107   {
4108     { Bad_Opcode },
4109     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4110     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4111     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4112   },
4113
4114   /* PREFIX_0FE7 */
4115   {
4116     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4117     { Bad_Opcode },
4118     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4119   },
4120
4121   /* PREFIX_0FF0 */
4122   {
4123     { Bad_Opcode },
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4127   },
4128
4129   /* PREFIX_0FF7 */
4130   {
4131     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4132     { Bad_Opcode },
4133     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4134   },
4135
4136   /* PREFIX_0F3810 */
4137   {
4138     { Bad_Opcode },
4139     { Bad_Opcode },
4140     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4141   },
4142
4143   /* PREFIX_0F3814 */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4148   },
4149
4150   /* PREFIX_0F3815 */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4155   },
4156
4157   /* PREFIX_0F3817 */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4162   },
4163
4164   /* PREFIX_0F3820 */
4165   {
4166     { Bad_Opcode },
4167     { Bad_Opcode },
4168     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4169   },
4170
4171   /* PREFIX_0F3821 */
4172   {
4173     { Bad_Opcode },
4174     { Bad_Opcode },
4175     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4176   },
4177
4178   /* PREFIX_0F3822 */
4179   {
4180     { Bad_Opcode },
4181     { Bad_Opcode },
4182     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4183   },
4184
4185   /* PREFIX_0F3823 */
4186   {
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4190   },
4191
4192   /* PREFIX_0F3824 */
4193   {
4194     { Bad_Opcode },
4195     { Bad_Opcode },
4196     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4197   },
4198
4199   /* PREFIX_0F3825 */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4204   },
4205
4206   /* PREFIX_0F3828 */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4211   },
4212
4213   /* PREFIX_0F3829 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4218   },
4219
4220   /* PREFIX_0F382A */
4221   {
4222     { Bad_Opcode },
4223     { Bad_Opcode },
4224     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4225   },
4226
4227   /* PREFIX_0F382B */
4228   {
4229     { Bad_Opcode },
4230     { Bad_Opcode },
4231     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4232   },
4233
4234   /* PREFIX_0F3830 */
4235   {
4236     { Bad_Opcode },
4237     { Bad_Opcode },
4238     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4239   },
4240
4241   /* PREFIX_0F3831 */
4242   {
4243     { Bad_Opcode },
4244     { Bad_Opcode },
4245     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4246   },
4247
4248   /* PREFIX_0F3832 */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4253   },
4254
4255   /* PREFIX_0F3833 */
4256   {
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4260   },
4261
4262   /* PREFIX_0F3834 */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4267   },
4268
4269   /* PREFIX_0F3835 */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4274   },
4275
4276   /* PREFIX_0F3837 */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_0F3838 */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4288   },
4289
4290   /* PREFIX_0F3839 */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4295   },
4296
4297   /* PREFIX_0F383A */
4298   {
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4302   },
4303
4304   /* PREFIX_0F383B */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4309   },
4310
4311   /* PREFIX_0F383C */
4312   {
4313     { Bad_Opcode },
4314     { Bad_Opcode },
4315     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4316   },
4317
4318   /* PREFIX_0F383D */
4319   {
4320     { Bad_Opcode },
4321     { Bad_Opcode },
4322     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4323   },
4324
4325   /* PREFIX_0F383E */
4326   {
4327     { Bad_Opcode },
4328     { Bad_Opcode },
4329     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4330   },
4331
4332   /* PREFIX_0F383F */
4333   {
4334     { Bad_Opcode },
4335     { Bad_Opcode },
4336     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4337   },
4338
4339   /* PREFIX_0F3840 */
4340   {
4341     { Bad_Opcode },
4342     { Bad_Opcode },
4343     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4344   },
4345
4346   /* PREFIX_0F3841 */
4347   {
4348     { Bad_Opcode },
4349     { Bad_Opcode },
4350     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4351   },
4352
4353   /* PREFIX_0F3880 */
4354   {
4355     { Bad_Opcode },
4356     { Bad_Opcode },
4357     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4358   },
4359
4360   /* PREFIX_0F3881 */
4361   {
4362     { Bad_Opcode },
4363     { Bad_Opcode },
4364     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4365   },
4366
4367   /* PREFIX_0F3882 */
4368   {
4369     { Bad_Opcode },
4370     { Bad_Opcode },
4371     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4372   },
4373
4374   /* PREFIX_0F38C8 */
4375   {
4376     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4377   },
4378
4379   /* PREFIX_0F38C9 */
4380   {
4381     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4382   },
4383
4384   /* PREFIX_0F38CA */
4385   {
4386     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4387   },
4388
4389   /* PREFIX_0F38CB */
4390   {
4391     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4392   },
4393
4394   /* PREFIX_0F38CC */
4395   {
4396     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4397   },
4398
4399   /* PREFIX_0F38CD */
4400   {
4401     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4402   },
4403
4404   /* PREFIX_0F38CF */
4405   {
4406     { Bad_Opcode },
4407     { Bad_Opcode },
4408     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4409   },
4410
4411   /* PREFIX_0F38DB */
4412   {
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4416   },
4417
4418   /* PREFIX_0F38DC */
4419   {
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4423   },
4424
4425   /* PREFIX_0F38DD */
4426   {
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4430   },
4431
4432   /* PREFIX_0F38DE */
4433   {
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4437   },
4438
4439   /* PREFIX_0F38DF */
4440   {
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4444   },
4445
4446   /* PREFIX_0F38F0 */
4447   {
4448     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4449     { Bad_Opcode },
4450     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4451     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4452   },
4453
4454   /* PREFIX_0F38F1 */
4455   {
4456     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4457     { Bad_Opcode },
4458     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4459     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4460   },
4461
4462   /* PREFIX_0F38F5 */
4463   {
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4467   },
4468
4469   /* PREFIX_0F38F6 */
4470   {
4471     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4472     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4473     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4474     { Bad_Opcode },
4475   },
4476
4477   /* PREFIX_0F38F8 */
4478   {
4479     { Bad_Opcode },
4480     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4481     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4482     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4483   },
4484
4485   /* PREFIX_0F38F9 */
4486   {
4487     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4488   },
4489
4490   /* PREFIX_0F3A08 */
4491   {
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4495   },
4496
4497   /* PREFIX_0F3A09 */
4498   {
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4502   },
4503
4504   /* PREFIX_0F3A0A */
4505   {
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4509   },
4510
4511   /* PREFIX_0F3A0B */
4512   {
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4516   },
4517
4518   /* PREFIX_0F3A0C */
4519   {
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4523   },
4524
4525   /* PREFIX_0F3A0D */
4526   {
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4530   },
4531
4532   /* PREFIX_0F3A0E */
4533   {
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4537   },
4538
4539   /* PREFIX_0F3A14 */
4540   {
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4544   },
4545
4546   /* PREFIX_0F3A15 */
4547   {
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4551   },
4552
4553   /* PREFIX_0F3A16 */
4554   {
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4558   },
4559
4560   /* PREFIX_0F3A17 */
4561   {
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4565   },
4566
4567   /* PREFIX_0F3A20 */
4568   {
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4572   },
4573
4574   /* PREFIX_0F3A21 */
4575   {
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4579   },
4580
4581   /* PREFIX_0F3A22 */
4582   {
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4586   },
4587
4588   /* PREFIX_0F3A40 */
4589   {
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4593   },
4594
4595   /* PREFIX_0F3A41 */
4596   {
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4600   },
4601
4602   /* PREFIX_0F3A42 */
4603   {
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4607   },
4608
4609   /* PREFIX_0F3A44 */
4610   {
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4614   },
4615
4616   /* PREFIX_0F3A60 */
4617   {
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4621   },
4622
4623   /* PREFIX_0F3A61 */
4624   {
4625     { Bad_Opcode },
4626     { Bad_Opcode },
4627     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4628   },
4629
4630   /* PREFIX_0F3A62 */
4631   {
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4635   },
4636
4637   /* PREFIX_0F3A63 */
4638   {
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4642   },
4643
4644   /* PREFIX_0F3ACC */
4645   {
4646     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4647   },
4648
4649   /* PREFIX_0F3ACE */
4650   {
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4654   },
4655
4656   /* PREFIX_0F3ACF */
4657   {
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4661   },
4662
4663   /* PREFIX_0F3ADF */
4664   {
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4668   },
4669
4670   /* PREFIX_VEX_0F10 */
4671   {
4672     { "vmovups",        { XM, EXx }, 0 },
4673     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4674     { "vmovupd",        { XM, EXx }, 0 },
4675     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4676   },
4677
4678   /* PREFIX_VEX_0F11 */
4679   {
4680     { "vmovups",        { EXxS, XM }, 0 },
4681     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4682     { "vmovupd",        { EXxS, XM }, 0 },
4683     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4684   },
4685
4686   /* PREFIX_VEX_0F12 */
4687   {
4688     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4689     { "vmovsldup",      { XM, EXx }, 0 },
4690     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4691     { "vmovddup",       { XM, EXymmq }, 0 },
4692   },
4693
4694   /* PREFIX_VEX_0F16 */
4695   {
4696     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4697     { "vmovshdup",      { XM, EXx }, 0 },
4698     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4699   },
4700
4701   /* PREFIX_VEX_0F2A */
4702   {
4703     { Bad_Opcode },
4704     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4705     { Bad_Opcode },
4706     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4707   },
4708
4709   /* PREFIX_VEX_0F2C */
4710   {
4711     { Bad_Opcode },
4712     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4713     { Bad_Opcode },
4714     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4715   },
4716
4717   /* PREFIX_VEX_0F2D */
4718   {
4719     { Bad_Opcode },
4720     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4721     { Bad_Opcode },
4722     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4723   },
4724
4725   /* PREFIX_VEX_0F2E */
4726   {
4727     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4728     { Bad_Opcode },
4729     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4730   },
4731
4732   /* PREFIX_VEX_0F2F */
4733   {
4734     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4735     { Bad_Opcode },
4736     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4737   },
4738
4739   /* PREFIX_VEX_0F41 */
4740   {
4741     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4742     { Bad_Opcode },
4743     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4744   },
4745
4746   /* PREFIX_VEX_0F42 */
4747   {
4748     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4749     { Bad_Opcode },
4750     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4751   },
4752
4753   /* PREFIX_VEX_0F44 */
4754   {
4755     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4756     { Bad_Opcode },
4757     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4758   },
4759
4760   /* PREFIX_VEX_0F45 */
4761   {
4762     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4763     { Bad_Opcode },
4764     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4765   },
4766
4767   /* PREFIX_VEX_0F46 */
4768   {
4769     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4770     { Bad_Opcode },
4771     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4772   },
4773
4774   /* PREFIX_VEX_0F47 */
4775   {
4776     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4777     { Bad_Opcode },
4778     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4779   },
4780
4781   /* PREFIX_VEX_0F4A */
4782   {
4783     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4784     { Bad_Opcode },
4785     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4786   },
4787
4788   /* PREFIX_VEX_0F4B */
4789   {
4790     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4791     { Bad_Opcode },
4792     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4793   },
4794
4795   /* PREFIX_VEX_0F51 */
4796   {
4797     { "vsqrtps",        { XM, EXx }, 0 },
4798     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4799     { "vsqrtpd",        { XM, EXx }, 0 },
4800     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4801   },
4802
4803   /* PREFIX_VEX_0F52 */
4804   {
4805     { "vrsqrtps",       { XM, EXx }, 0 },
4806     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4807   },
4808
4809   /* PREFIX_VEX_0F53 */
4810   {
4811     { "vrcpps",         { XM, EXx }, 0 },
4812     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4813   },
4814
4815   /* PREFIX_VEX_0F58 */
4816   {
4817     { "vaddps",         { XM, Vex, EXx }, 0 },
4818     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4819     { "vaddpd",         { XM, Vex, EXx }, 0 },
4820     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4821   },
4822
4823   /* PREFIX_VEX_0F59 */
4824   {
4825     { "vmulps",         { XM, Vex, EXx }, 0 },
4826     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4827     { "vmulpd",         { XM, Vex, EXx }, 0 },
4828     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4829   },
4830
4831   /* PREFIX_VEX_0F5A */
4832   {
4833     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4834     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4835     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4836     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4837   },
4838
4839   /* PREFIX_VEX_0F5B */
4840   {
4841     { "vcvtdq2ps",      { XM, EXx }, 0 },
4842     { "vcvttps2dq",     { XM, EXx }, 0 },
4843     { "vcvtps2dq",      { XM, EXx }, 0 },
4844   },
4845
4846   /* PREFIX_VEX_0F5C */
4847   {
4848     { "vsubps",         { XM, Vex, EXx }, 0 },
4849     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4850     { "vsubpd",         { XM, Vex, EXx }, 0 },
4851     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4852   },
4853
4854   /* PREFIX_VEX_0F5D */
4855   {
4856     { "vminps",         { XM, Vex, EXx }, 0 },
4857     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4858     { "vminpd",         { XM, Vex, EXx }, 0 },
4859     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4860   },
4861
4862   /* PREFIX_VEX_0F5E */
4863   {
4864     { "vdivps",         { XM, Vex, EXx }, 0 },
4865     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4866     { "vdivpd",         { XM, Vex, EXx }, 0 },
4867     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4868   },
4869
4870   /* PREFIX_VEX_0F5F */
4871   {
4872     { "vmaxps",         { XM, Vex, EXx }, 0 },
4873     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4874     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4875     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4876   },
4877
4878   /* PREFIX_VEX_0F60 */
4879   {
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4883   },
4884
4885   /* PREFIX_VEX_0F61 */
4886   {
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4890   },
4891
4892   /* PREFIX_VEX_0F62 */
4893   {
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4897   },
4898
4899   /* PREFIX_VEX_0F63 */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4904   },
4905
4906   /* PREFIX_VEX_0F64 */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4911   },
4912
4913   /* PREFIX_VEX_0F65 */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4918   },
4919
4920   /* PREFIX_VEX_0F66 */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4925   },
4926
4927   /* PREFIX_VEX_0F67 */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4932   },
4933
4934   /* PREFIX_VEX_0F68 */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4939   },
4940
4941   /* PREFIX_VEX_0F69 */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4946   },
4947
4948   /* PREFIX_VEX_0F6A */
4949   {
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4953   },
4954
4955   /* PREFIX_VEX_0F6B */
4956   {
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4960   },
4961
4962   /* PREFIX_VEX_0F6C */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4967   },
4968
4969   /* PREFIX_VEX_0F6D */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4974   },
4975
4976   /* PREFIX_VEX_0F6E */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4981   },
4982
4983   /* PREFIX_VEX_0F6F */
4984   {
4985     { Bad_Opcode },
4986     { "vmovdqu",        { XM, EXx }, 0 },
4987     { "vmovdqa",        { XM, EXx }, 0 },
4988   },
4989
4990   /* PREFIX_VEX_0F70 */
4991   {
4992     { Bad_Opcode },
4993     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4994     { "vpshufd",        { XM, EXx, Ib }, 0 },
4995     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4996   },
4997
4998   /* PREFIX_VEX_0F71_REG_2 */
4999   {
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { "vpsrlw",         { Vex, XS, Ib }, 0 },
5003   },
5004
5005   /* PREFIX_VEX_0F71_REG_4 */
5006   {
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { "vpsraw",         { Vex, XS, Ib }, 0 },
5010   },
5011
5012   /* PREFIX_VEX_0F71_REG_6 */
5013   {
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { "vpsllw",         { Vex, XS, Ib }, 0 },
5017   },
5018
5019   /* PREFIX_VEX_0F72_REG_2 */
5020   {
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { "vpsrld",         { Vex, XS, Ib }, 0 },
5024   },
5025
5026   /* PREFIX_VEX_0F72_REG_4 */
5027   {
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { "vpsrad",         { Vex, XS, Ib }, 0 },
5031   },
5032
5033   /* PREFIX_VEX_0F72_REG_6 */
5034   {
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { "vpslld",         { Vex, XS, Ib }, 0 },
5038   },
5039
5040   /* PREFIX_VEX_0F73_REG_2 */
5041   {
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5045   },
5046
5047   /* PREFIX_VEX_0F73_REG_3 */
5048   {
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5052   },
5053
5054   /* PREFIX_VEX_0F73_REG_6 */
5055   {
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { "vpsllq",         { Vex, XS, Ib }, 0 },
5059   },
5060
5061   /* PREFIX_VEX_0F73_REG_7 */
5062   {
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { "vpslldq",        { Vex, XS, Ib }, 0 },
5066   },
5067
5068   /* PREFIX_VEX_0F74 */
5069   {
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5073   },
5074
5075   /* PREFIX_VEX_0F75 */
5076   {
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5080   },
5081
5082   /* PREFIX_VEX_0F76 */
5083   {
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5087   },
5088
5089   /* PREFIX_VEX_0F77 */
5090   {
5091     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5092   },
5093
5094   /* PREFIX_VEX_0F7C */
5095   {
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5099     { "vhaddps",        { XM, Vex, EXx }, 0 },
5100   },
5101
5102   /* PREFIX_VEX_0F7D */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5107     { "vhsubps",        { XM, Vex, EXx }, 0 },
5108   },
5109
5110   /* PREFIX_VEX_0F7E */
5111   {
5112     { Bad_Opcode },
5113     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5114     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5115   },
5116
5117   /* PREFIX_VEX_0F7F */
5118   {
5119     { Bad_Opcode },
5120     { "vmovdqu",        { EXxS, XM }, 0 },
5121     { "vmovdqa",        { EXxS, XM }, 0 },
5122   },
5123
5124   /* PREFIX_VEX_0F90 */
5125   {
5126     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5127     { Bad_Opcode },
5128     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5129   },
5130
5131   /* PREFIX_VEX_0F91 */
5132   {
5133     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5134     { Bad_Opcode },
5135     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5136   },
5137
5138   /* PREFIX_VEX_0F92 */
5139   {
5140     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5141     { Bad_Opcode },
5142     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5143     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5144   },
5145
5146   /* PREFIX_VEX_0F93 */
5147   {
5148     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5149     { Bad_Opcode },
5150     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5151     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5152   },
5153
5154   /* PREFIX_VEX_0F98 */
5155   {
5156     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5157     { Bad_Opcode },
5158     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5159   },
5160
5161   /* PREFIX_VEX_0F99 */
5162   {
5163     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5164     { Bad_Opcode },
5165     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5166   },
5167
5168   /* PREFIX_VEX_0FC2 */
5169   {
5170     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5171     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5172     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5173     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5174   },
5175
5176   /* PREFIX_VEX_0FC4 */
5177   {
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5181   },
5182
5183   /* PREFIX_VEX_0FC5 */
5184   {
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5188   },
5189
5190   /* PREFIX_VEX_0FD0 */
5191   {
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5195     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5196   },
5197
5198   /* PREFIX_VEX_0FD1 */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5203   },
5204
5205   /* PREFIX_VEX_0FD2 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5210   },
5211
5212   /* PREFIX_VEX_0FD3 */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5217   },
5218
5219   /* PREFIX_VEX_0FD4 */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { "vpaddq",         { XM, Vex, EXx }, 0 },
5224   },
5225
5226   /* PREFIX_VEX_0FD5 */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { "vpmullw",        { XM, Vex, EXx }, 0 },
5231   },
5232
5233   /* PREFIX_VEX_0FD6 */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5238   },
5239
5240   /* PREFIX_VEX_0FD7 */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5245   },
5246
5247   /* PREFIX_VEX_0FD8 */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5252   },
5253
5254   /* PREFIX_VEX_0FD9 */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5259   },
5260
5261   /* PREFIX_VEX_0FDA */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { "vpminub",        { XM, Vex, EXx }, 0 },
5266   },
5267
5268   /* PREFIX_VEX_0FDB */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { "vpand",          { XM, Vex, EXx }, 0 },
5273   },
5274
5275   /* PREFIX_VEX_0FDC */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5280   },
5281
5282   /* PREFIX_VEX_0FDD */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5287   },
5288
5289   /* PREFIX_VEX_0FDE */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5294   },
5295
5296   /* PREFIX_VEX_0FDF */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { "vpandn",         { XM, Vex, EXx }, 0 },
5301   },
5302
5303   /* PREFIX_VEX_0FE0 */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { "vpavgb",         { XM, Vex, EXx }, 0 },
5308   },
5309
5310   /* PREFIX_VEX_0FE1 */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5315   },
5316
5317   /* PREFIX_VEX_0FE2 */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5322   },
5323
5324   /* PREFIX_VEX_0FE3 */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { "vpavgw",         { XM, Vex, EXx }, 0 },
5329   },
5330
5331   /* PREFIX_VEX_0FE4 */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5336   },
5337
5338   /* PREFIX_VEX_0FE5 */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5343   },
5344
5345   /* PREFIX_VEX_0FE6 */
5346   {
5347     { Bad_Opcode },
5348     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5349     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5350     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5351   },
5352
5353   /* PREFIX_VEX_0FE7 */
5354   {
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5358   },
5359
5360   /* PREFIX_VEX_0FE8 */
5361   {
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5365   },
5366
5367   /* PREFIX_VEX_0FE9 */
5368   {
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5372   },
5373
5374   /* PREFIX_VEX_0FEA */
5375   {
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { "vpminsw",        { XM, Vex, EXx }, 0 },
5379   },
5380
5381   /* PREFIX_VEX_0FEB */
5382   {
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { "vpor",           { XM, Vex, EXx }, 0 },
5386   },
5387
5388   /* PREFIX_VEX_0FEC */
5389   {
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5393   },
5394
5395   /* PREFIX_VEX_0FED */
5396   {
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5400   },
5401
5402   /* PREFIX_VEX_0FEE */
5403   {
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5407   },
5408
5409   /* PREFIX_VEX_0FEF */
5410   {
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { "vpxor",          { XM, Vex, EXx }, 0 },
5414   },
5415
5416   /* PREFIX_VEX_0FF0 */
5417   {
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5422   },
5423
5424   /* PREFIX_VEX_0FF1 */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5429   },
5430
5431   /* PREFIX_VEX_0FF2 */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5436   },
5437
5438   /* PREFIX_VEX_0FF3 */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5443   },
5444
5445   /* PREFIX_VEX_0FF4 */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5450   },
5451
5452   /* PREFIX_VEX_0FF5 */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5457   },
5458
5459   /* PREFIX_VEX_0FF6 */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5464   },
5465
5466   /* PREFIX_VEX_0FF7 */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5471   },
5472
5473   /* PREFIX_VEX_0FF8 */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { "vpsubb",         { XM, Vex, EXx }, 0 },
5478   },
5479
5480   /* PREFIX_VEX_0FF9 */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { "vpsubw",         { XM, Vex, EXx }, 0 },
5485   },
5486
5487   /* PREFIX_VEX_0FFA */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { "vpsubd",         { XM, Vex, EXx }, 0 },
5492   },
5493
5494   /* PREFIX_VEX_0FFB */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { "vpsubq",         { XM, Vex, EXx }, 0 },
5499   },
5500
5501   /* PREFIX_VEX_0FFC */
5502   {
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { "vpaddb",         { XM, Vex, EXx }, 0 },
5506   },
5507
5508   /* PREFIX_VEX_0FFD */
5509   {
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { "vpaddw",         { XM, Vex, EXx }, 0 },
5513   },
5514
5515   /* PREFIX_VEX_0FFE */
5516   {
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { "vpaddd",         { XM, Vex, EXx }, 0 },
5520   },
5521
5522   /* PREFIX_VEX_0F3800 */
5523   {
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { "vpshufb",        { XM, Vex, EXx }, 0 },
5527   },
5528
5529   /* PREFIX_VEX_0F3801 */
5530   {
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { "vphaddw",        { XM, Vex, EXx }, 0 },
5534   },
5535
5536   /* PREFIX_VEX_0F3802 */
5537   {
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { "vphaddd",        { XM, Vex, EXx }, 0 },
5541   },
5542
5543   /* PREFIX_VEX_0F3803 */
5544   {
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5548   },
5549
5550   /* PREFIX_VEX_0F3804 */
5551   {
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5555   },
5556
5557   /* PREFIX_VEX_0F3805 */
5558   {
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { "vphsubw",        { XM, Vex, EXx }, 0 },
5562   },
5563
5564   /* PREFIX_VEX_0F3806 */
5565   {
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { "vphsubd",        { XM, Vex, EXx }, 0 },
5569   },
5570
5571   /* PREFIX_VEX_0F3807 */
5572   {
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5576   },
5577
5578   /* PREFIX_VEX_0F3808 */
5579   {
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { "vpsignb",        { XM, Vex, EXx }, 0 },
5583   },
5584
5585   /* PREFIX_VEX_0F3809 */
5586   {
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { "vpsignw",        { XM, Vex, EXx }, 0 },
5590   },
5591
5592   /* PREFIX_VEX_0F380A */
5593   {
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { "vpsignd",        { XM, Vex, EXx }, 0 },
5597   },
5598
5599   /* PREFIX_VEX_0F380B */
5600   {
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5604   },
5605
5606   /* PREFIX_VEX_0F380C */
5607   {
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5611   },
5612
5613   /* PREFIX_VEX_0F380D */
5614   {
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5618   },
5619
5620   /* PREFIX_VEX_0F380E */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5625   },
5626
5627   /* PREFIX_VEX_0F380F */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5632   },
5633
5634   /* PREFIX_VEX_0F3813 */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5639   },
5640
5641   /* PREFIX_VEX_0F3816 */
5642   {
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5646   },
5647
5648   /* PREFIX_VEX_0F3817 */
5649   {
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { "vptest",         { XM, EXx }, 0 },
5653   },
5654
5655   /* PREFIX_VEX_0F3818 */
5656   {
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5660   },
5661
5662   /* PREFIX_VEX_0F3819 */
5663   {
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5667   },
5668
5669   /* PREFIX_VEX_0F381A */
5670   {
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5674   },
5675
5676   /* PREFIX_VEX_0F381C */
5677   {
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { "vpabsb",         { XM, EXx }, 0 },
5681   },
5682
5683   /* PREFIX_VEX_0F381D */
5684   {
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { "vpabsw",         { XM, EXx }, 0 },
5688   },
5689
5690   /* PREFIX_VEX_0F381E */
5691   {
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { "vpabsd",         { XM, EXx }, 0 },
5695   },
5696
5697   /* PREFIX_VEX_0F3820 */
5698   {
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5702   },
5703
5704   /* PREFIX_VEX_0F3821 */
5705   {
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5709   },
5710
5711   /* PREFIX_VEX_0F3822 */
5712   {
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5716   },
5717
5718   /* PREFIX_VEX_0F3823 */
5719   {
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5723   },
5724
5725   /* PREFIX_VEX_0F3824 */
5726   {
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5730   },
5731
5732   /* PREFIX_VEX_0F3825 */
5733   {
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5737   },
5738
5739   /* PREFIX_VEX_0F3828 */
5740   {
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5744   },
5745
5746   /* PREFIX_VEX_0F3829 */
5747   {
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5751   },
5752
5753   /* PREFIX_VEX_0F382A */
5754   {
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5758   },
5759
5760   /* PREFIX_VEX_0F382B */
5761   {
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5765   },
5766
5767   /* PREFIX_VEX_0F382C */
5768   {
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5772   },
5773
5774   /* PREFIX_VEX_0F382D */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5779   },
5780
5781   /* PREFIX_VEX_0F382E */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5786   },
5787
5788   /* PREFIX_VEX_0F382F */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5793   },
5794
5795   /* PREFIX_VEX_0F3830 */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5800   },
5801
5802   /* PREFIX_VEX_0F3831 */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5807   },
5808
5809   /* PREFIX_VEX_0F3832 */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5814   },
5815
5816   /* PREFIX_VEX_0F3833 */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5821   },
5822
5823   /* PREFIX_VEX_0F3834 */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5828   },
5829
5830   /* PREFIX_VEX_0F3835 */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5835   },
5836
5837   /* PREFIX_VEX_0F3836 */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5842   },
5843
5844   /* PREFIX_VEX_0F3837 */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5849   },
5850
5851   /* PREFIX_VEX_0F3838 */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { "vpminsb",        { XM, Vex, EXx }, 0 },
5856   },
5857
5858   /* PREFIX_VEX_0F3839 */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { "vpminsd",        { XM, Vex, EXx }, 0 },
5863   },
5864
5865   /* PREFIX_VEX_0F383A */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { "vpminuw",        { XM, Vex, EXx }, 0 },
5870   },
5871
5872   /* PREFIX_VEX_0F383B */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { "vpminud",        { XM, Vex, EXx }, 0 },
5877   },
5878
5879   /* PREFIX_VEX_0F383C */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5884   },
5885
5886   /* PREFIX_VEX_0F383D */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5891   },
5892
5893   /* PREFIX_VEX_0F383E */
5894   {
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5898   },
5899
5900   /* PREFIX_VEX_0F383F */
5901   {
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5905   },
5906
5907   /* PREFIX_VEX_0F3840 */
5908   {
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { "vpmulld",        { XM, Vex, EXx }, 0 },
5912   },
5913
5914   /* PREFIX_VEX_0F3841 */
5915   {
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5919   },
5920
5921   /* PREFIX_VEX_0F3845 */
5922   {
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5926   },
5927
5928   /* PREFIX_VEX_0F3846 */
5929   {
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5933   },
5934
5935   /* PREFIX_VEX_0F3847 */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5940   },
5941
5942   /* PREFIX_VEX_0F3858 */
5943   {
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5947   },
5948
5949   /* PREFIX_VEX_0F3859 */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5954   },
5955
5956   /* PREFIX_VEX_0F385A */
5957   {
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5961   },
5962
5963   /* PREFIX_VEX_0F3878 */
5964   {
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5968   },
5969
5970   /* PREFIX_VEX_0F3879 */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5975   },
5976
5977   /* PREFIX_VEX_0F388C */
5978   {
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5982   },
5983
5984   /* PREFIX_VEX_0F388E */
5985   {
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5989   },
5990
5991   /* PREFIX_VEX_0F3890 */
5992   {
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5996   },
5997
5998   /* PREFIX_VEX_0F3891 */
5999   {
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6003   },
6004
6005   /* PREFIX_VEX_0F3892 */
6006   {
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6010   },
6011
6012   /* PREFIX_VEX_0F3893 */
6013   {
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6017   },
6018
6019   /* PREFIX_VEX_0F3896 */
6020   {
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6024   },
6025
6026   /* PREFIX_VEX_0F3897 */
6027   {
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6031   },
6032
6033   /* PREFIX_VEX_0F3898 */
6034   {
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6038   },
6039
6040   /* PREFIX_VEX_0F3899 */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6045   },
6046
6047   /* PREFIX_VEX_0F389A */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6052   },
6053
6054   /* PREFIX_VEX_0F389B */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6059   },
6060
6061   /* PREFIX_VEX_0F389C */
6062   {
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6066   },
6067
6068   /* PREFIX_VEX_0F389D */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6073   },
6074
6075   /* PREFIX_VEX_0F389E */
6076   {
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6080   },
6081
6082   /* PREFIX_VEX_0F389F */
6083   {
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6087   },
6088
6089   /* PREFIX_VEX_0F38A6 */
6090   {
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6094     { Bad_Opcode },
6095   },
6096
6097   /* PREFIX_VEX_0F38A7 */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6102   },
6103
6104   /* PREFIX_VEX_0F38A8 */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6109   },
6110
6111   /* PREFIX_VEX_0F38A9 */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6116   },
6117
6118   /* PREFIX_VEX_0F38AA */
6119   {
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6123   },
6124
6125   /* PREFIX_VEX_0F38AB */
6126   {
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6130   },
6131
6132   /* PREFIX_VEX_0F38AC */
6133   {
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6137   },
6138
6139   /* PREFIX_VEX_0F38AD */
6140   {
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6144   },
6145
6146   /* PREFIX_VEX_0F38AE */
6147   {
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6151   },
6152
6153   /* PREFIX_VEX_0F38AF */
6154   {
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6158   },
6159
6160   /* PREFIX_VEX_0F38B6 */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6165   },
6166
6167   /* PREFIX_VEX_0F38B7 */
6168   {
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6172   },
6173
6174   /* PREFIX_VEX_0F38B8 */
6175   {
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6179   },
6180
6181   /* PREFIX_VEX_0F38B9 */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6186   },
6187
6188   /* PREFIX_VEX_0F38BA */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6193   },
6194
6195   /* PREFIX_VEX_0F38BB */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6200   },
6201
6202   /* PREFIX_VEX_0F38BC */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6207   },
6208
6209   /* PREFIX_VEX_0F38BD */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6214   },
6215
6216   /* PREFIX_VEX_0F38BE */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6221   },
6222
6223   /* PREFIX_VEX_0F38BF */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6228   },
6229
6230   /* PREFIX_VEX_0F38CF */
6231   {
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6235   },
6236
6237   /* PREFIX_VEX_0F38DB */
6238   {
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6242   },
6243
6244   /* PREFIX_VEX_0F38DC */
6245   {
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { "vaesenc",        { XM, Vex, EXx }, 0 },
6249   },
6250
6251   /* PREFIX_VEX_0F38DD */
6252   {
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6256   },
6257
6258   /* PREFIX_VEX_0F38DE */
6259   {
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { "vaesdec",        { XM, Vex, EXx }, 0 },
6263   },
6264
6265   /* PREFIX_VEX_0F38DF */
6266   {
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6270   },
6271
6272   /* PREFIX_VEX_0F38F2 */
6273   {
6274     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6275   },
6276
6277   /* PREFIX_VEX_0F38F3_REG_1 */
6278   {
6279     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6280   },
6281
6282   /* PREFIX_VEX_0F38F3_REG_2 */
6283   {
6284     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6285   },
6286
6287   /* PREFIX_VEX_0F38F3_REG_3 */
6288   {
6289     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6290   },
6291
6292   /* PREFIX_VEX_0F38F5 */
6293   {
6294     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6295     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6296     { Bad_Opcode },
6297     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6298   },
6299
6300   /* PREFIX_VEX_0F38F6 */
6301   {
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6306   },
6307
6308   /* PREFIX_VEX_0F38F7 */
6309   {
6310     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6311     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6312     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6313     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6314   },
6315
6316   /* PREFIX_VEX_0F3A00 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6321   },
6322
6323   /* PREFIX_VEX_0F3A01 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6328   },
6329
6330   /* PREFIX_VEX_0F3A02 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6335   },
6336
6337   /* PREFIX_VEX_0F3A04 */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6342   },
6343
6344   /* PREFIX_VEX_0F3A05 */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6349   },
6350
6351   /* PREFIX_VEX_0F3A06 */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6356   },
6357
6358   /* PREFIX_VEX_0F3A08 */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { "vroundps",       { XM, EXx, Ib }, 0 },
6363   },
6364
6365   /* PREFIX_VEX_0F3A09 */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { "vroundpd",       { XM, EXx, Ib }, 0 },
6370   },
6371
6372   /* PREFIX_VEX_0F3A0A */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6377   },
6378
6379   /* PREFIX_VEX_0F3A0B */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6384   },
6385
6386   /* PREFIX_VEX_0F3A0C */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6391   },
6392
6393   /* PREFIX_VEX_0F3A0D */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6398   },
6399
6400   /* PREFIX_VEX_0F3A0E */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6405   },
6406
6407   /* PREFIX_VEX_0F3A0F */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6412   },
6413
6414   /* PREFIX_VEX_0F3A14 */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6419   },
6420
6421   /* PREFIX_VEX_0F3A15 */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6426   },
6427
6428   /* PREFIX_VEX_0F3A16 */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6433   },
6434
6435   /* PREFIX_VEX_0F3A17 */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6440   },
6441
6442   /* PREFIX_VEX_0F3A18 */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6447   },
6448
6449   /* PREFIX_VEX_0F3A19 */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6454   },
6455
6456   /* PREFIX_VEX_0F3A1D */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6461   },
6462
6463   /* PREFIX_VEX_0F3A20 */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6468   },
6469
6470   /* PREFIX_VEX_0F3A21 */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6475   },
6476
6477   /* PREFIX_VEX_0F3A22 */
6478   {
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6482   },
6483
6484   /* PREFIX_VEX_0F3A30 */
6485   {
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6489   },
6490
6491   /* PREFIX_VEX_0F3A31 */
6492   {
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6496   },
6497
6498   /* PREFIX_VEX_0F3A32 */
6499   {
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6503   },
6504
6505   /* PREFIX_VEX_0F3A33 */
6506   {
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6510   },
6511
6512   /* PREFIX_VEX_0F3A38 */
6513   {
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6517   },
6518
6519   /* PREFIX_VEX_0F3A39 */
6520   {
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6524   },
6525
6526   /* PREFIX_VEX_0F3A40 */
6527   {
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6531   },
6532
6533   /* PREFIX_VEX_0F3A41 */
6534   {
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6538   },
6539
6540   /* PREFIX_VEX_0F3A42 */
6541   {
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6545   },
6546
6547   /* PREFIX_VEX_0F3A44 */
6548   {
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6552   },
6553
6554   /* PREFIX_VEX_0F3A46 */
6555   {
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6559   },
6560
6561   /* PREFIX_VEX_0F3A48 */
6562   {
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6566   },
6567
6568   /* PREFIX_VEX_0F3A49 */
6569   {
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6573   },
6574
6575   /* PREFIX_VEX_0F3A4A */
6576   {
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6580   },
6581
6582   /* PREFIX_VEX_0F3A4B */
6583   {
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6587   },
6588
6589   /* PREFIX_VEX_0F3A4C */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6594   },
6595
6596   /* PREFIX_VEX_0F3A5C */
6597   {
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6601   },
6602
6603   /* PREFIX_VEX_0F3A5D */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6608   },
6609
6610   /* PREFIX_VEX_0F3A5E */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6615   },
6616
6617   /* PREFIX_VEX_0F3A5F */
6618   {
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6622   },
6623
6624   /* PREFIX_VEX_0F3A60 */
6625   {
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6629     { Bad_Opcode },
6630   },
6631
6632   /* PREFIX_VEX_0F3A61 */
6633   {
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6637   },
6638
6639   /* PREFIX_VEX_0F3A62 */
6640   {
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6644   },
6645
6646   /* PREFIX_VEX_0F3A63 */
6647   {
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6651   },
6652
6653   /* PREFIX_VEX_0F3A68 */
6654   {
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6658   },
6659
6660   /* PREFIX_VEX_0F3A69 */
6661   {
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6665   },
6666
6667   /* PREFIX_VEX_0F3A6A */
6668   {
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6672   },
6673
6674   /* PREFIX_VEX_0F3A6B */
6675   {
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6679   },
6680
6681   /* PREFIX_VEX_0F3A6C */
6682   {
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6686   },
6687
6688   /* PREFIX_VEX_0F3A6D */
6689   {
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6693   },
6694
6695   /* PREFIX_VEX_0F3A6E */
6696   {
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6700   },
6701
6702   /* PREFIX_VEX_0F3A6F */
6703   {
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6707   },
6708
6709   /* PREFIX_VEX_0F3A78 */
6710   {
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6714   },
6715
6716   /* PREFIX_VEX_0F3A79 */
6717   {
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6721   },
6722
6723   /* PREFIX_VEX_0F3A7A */
6724   {
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6728   },
6729
6730   /* PREFIX_VEX_0F3A7B */
6731   {
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6735   },
6736
6737   /* PREFIX_VEX_0F3A7C */
6738   {
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6742     { Bad_Opcode },
6743   },
6744
6745   /* PREFIX_VEX_0F3A7D */
6746   {
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6750   },
6751
6752   /* PREFIX_VEX_0F3A7E */
6753   {
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6757   },
6758
6759   /* PREFIX_VEX_0F3A7F */
6760   {
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6764   },
6765
6766   /* PREFIX_VEX_0F3ACE */
6767   {
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6771   },
6772
6773   /* PREFIX_VEX_0F3ACF */
6774   {
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6778   },
6779
6780   /* PREFIX_VEX_0F3ADF */
6781   {
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6785   },
6786
6787   /* PREFIX_VEX_0F3AF0 */
6788   {
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6793   },
6794
6795 #include "i386-dis-evex-prefix.h"
6796 };
6797
6798 static const struct dis386 x86_64_table[][2] = {
6799   /* X86_64_06 */
6800   {
6801     { "pushP", { es }, 0 },
6802   },
6803
6804   /* X86_64_07 */
6805   {
6806     { "popP", { es }, 0 },
6807   },
6808
6809   /* X86_64_0D */
6810   {
6811     { "pushP", { cs }, 0 },
6812   },
6813
6814   /* X86_64_16 */
6815   {
6816     { "pushP", { ss }, 0 },
6817   },
6818
6819   /* X86_64_17 */
6820   {
6821     { "popP", { ss }, 0 },
6822   },
6823
6824   /* X86_64_1E */
6825   {
6826     { "pushP", { ds }, 0 },
6827   },
6828
6829   /* X86_64_1F */
6830   {
6831     { "popP", { ds }, 0 },
6832   },
6833
6834   /* X86_64_27 */
6835   {
6836     { "daa", { XX }, 0 },
6837   },
6838
6839   /* X86_64_2F */
6840   {
6841     { "das", { XX }, 0 },
6842   },
6843
6844   /* X86_64_37 */
6845   {
6846     { "aaa", { XX }, 0 },
6847   },
6848
6849   /* X86_64_3F */
6850   {
6851     { "aas", { XX }, 0 },
6852   },
6853
6854   /* X86_64_60 */
6855   {
6856     { "pushaP", { XX }, 0 },
6857   },
6858
6859   /* X86_64_61 */
6860   {
6861     { "popaP", { XX }, 0 },
6862   },
6863
6864   /* X86_64_62 */
6865   {
6866     { MOD_TABLE (MOD_62_32BIT) },
6867     { EVEX_TABLE (EVEX_0F) },
6868   },
6869
6870   /* X86_64_63 */
6871   {
6872     { "arpl", { Ew, Gw }, 0 },
6873     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6874   },
6875
6876   /* X86_64_6D */
6877   {
6878     { "ins{R|}", { Yzr, indirDX }, 0 },
6879     { "ins{G|}", { Yzr, indirDX }, 0 },
6880   },
6881
6882   /* X86_64_6F */
6883   {
6884     { "outs{R|}", { indirDXr, Xz }, 0 },
6885     { "outs{G|}", { indirDXr, Xz }, 0 },
6886   },
6887
6888   /* X86_64_82 */
6889   {
6890     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6891     { REG_TABLE (REG_80) },
6892   },
6893
6894   /* X86_64_9A */
6895   {
6896     { "Jcall{T|}", { Ap }, 0 },
6897   },
6898
6899   /* X86_64_C2 */
6900   {
6901     { "retP",           { Iw, BND }, 0 },
6902     { "ret@",           { Iw, BND }, 0 },
6903   },
6904
6905   /* X86_64_C3 */
6906   {
6907     { "retP",           { BND }, 0 },
6908     { "ret@",           { BND }, 0 },
6909   },
6910
6911   /* X86_64_C4 */
6912   {
6913     { MOD_TABLE (MOD_C4_32BIT) },
6914     { VEX_C4_TABLE (VEX_0F) },
6915   },
6916
6917   /* X86_64_C5 */
6918   {
6919     { MOD_TABLE (MOD_C5_32BIT) },
6920     { VEX_C5_TABLE (VEX_0F) },
6921   },
6922
6923   /* X86_64_CE */
6924   {
6925     { "into", { XX }, 0 },
6926   },
6927
6928   /* X86_64_D4 */
6929   {
6930     { "aam", { Ib }, 0 },
6931   },
6932
6933   /* X86_64_D5 */
6934   {
6935     { "aad", { Ib }, 0 },
6936   },
6937
6938   /* X86_64_E8 */
6939   {
6940     { "callP",          { Jv, BND }, 0 },
6941     { "call@",          { Jv, BND }, 0 }
6942   },
6943
6944   /* X86_64_E9 */
6945   {
6946     { "jmpP",           { Jv, BND }, 0 },
6947     { "jmp@",           { Jv, BND }, 0 }
6948   },
6949
6950   /* X86_64_EA */
6951   {
6952     { "Jjmp{T|}", { Ap }, 0 },
6953   },
6954
6955   /* X86_64_0F01_REG_0 */
6956   {
6957     { "sgdt{Q|IQ}", { M }, 0 },
6958     { "sgdt", { M }, 0 },
6959   },
6960
6961   /* X86_64_0F01_REG_1 */
6962   {
6963     { "sidt{Q|IQ}", { M }, 0 },
6964     { "sidt", { M }, 0 },
6965   },
6966
6967   /* X86_64_0F01_REG_2 */
6968   {
6969     { "lgdt{Q|Q}", { M }, 0 },
6970     { "lgdt", { M }, 0 },
6971   },
6972
6973   /* X86_64_0F01_REG_3 */
6974   {
6975     { "lidt{Q|Q}", { M }, 0 },
6976     { "lidt", { M }, 0 },
6977   },
6978 };
6979
6980 static const struct dis386 three_byte_table[][256] = {
6981
6982   /* THREE_BYTE_0F38 */
6983   {
6984     /* 00 */
6985     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6986     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6987     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6988     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6989     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6990     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6991     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6992     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6993     /* 08 */
6994     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6995     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6996     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6997     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     /* 10 */
7003     { PREFIX_TABLE (PREFIX_0F3810) },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { PREFIX_TABLE (PREFIX_0F3814) },
7008     { PREFIX_TABLE (PREFIX_0F3815) },
7009     { Bad_Opcode },
7010     { PREFIX_TABLE (PREFIX_0F3817) },
7011     /* 18 */
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7017     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7018     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7019     { Bad_Opcode },
7020     /* 20 */
7021     { PREFIX_TABLE (PREFIX_0F3820) },
7022     { PREFIX_TABLE (PREFIX_0F3821) },
7023     { PREFIX_TABLE (PREFIX_0F3822) },
7024     { PREFIX_TABLE (PREFIX_0F3823) },
7025     { PREFIX_TABLE (PREFIX_0F3824) },
7026     { PREFIX_TABLE (PREFIX_0F3825) },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     /* 28 */
7030     { PREFIX_TABLE (PREFIX_0F3828) },
7031     { PREFIX_TABLE (PREFIX_0F3829) },
7032     { PREFIX_TABLE (PREFIX_0F382A) },
7033     { PREFIX_TABLE (PREFIX_0F382B) },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     /* 30 */
7039     { PREFIX_TABLE (PREFIX_0F3830) },
7040     { PREFIX_TABLE (PREFIX_0F3831) },
7041     { PREFIX_TABLE (PREFIX_0F3832) },
7042     { PREFIX_TABLE (PREFIX_0F3833) },
7043     { PREFIX_TABLE (PREFIX_0F3834) },
7044     { PREFIX_TABLE (PREFIX_0F3835) },
7045     { Bad_Opcode },
7046     { PREFIX_TABLE (PREFIX_0F3837) },
7047     /* 38 */
7048     { PREFIX_TABLE (PREFIX_0F3838) },
7049     { PREFIX_TABLE (PREFIX_0F3839) },
7050     { PREFIX_TABLE (PREFIX_0F383A) },
7051     { PREFIX_TABLE (PREFIX_0F383B) },
7052     { PREFIX_TABLE (PREFIX_0F383C) },
7053     { PREFIX_TABLE (PREFIX_0F383D) },
7054     { PREFIX_TABLE (PREFIX_0F383E) },
7055     { PREFIX_TABLE (PREFIX_0F383F) },
7056     /* 40 */
7057     { PREFIX_TABLE (PREFIX_0F3840) },
7058     { PREFIX_TABLE (PREFIX_0F3841) },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     /* 48 */
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     /* 50 */
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     /* 58 */
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     /* 60 */
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     /* 68 */
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     /* 70 */
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     /* 78 */
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     /* 80 */
7129     { PREFIX_TABLE (PREFIX_0F3880) },
7130     { PREFIX_TABLE (PREFIX_0F3881) },
7131     { PREFIX_TABLE (PREFIX_0F3882) },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     /* 88 */
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     /* 90 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     /* 98 */
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* a0 */
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     /* a8 */
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     /* b0 */
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     /* b8 */
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     /* c0 */
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     /* c8 */
7210     { PREFIX_TABLE (PREFIX_0F38C8) },
7211     { PREFIX_TABLE (PREFIX_0F38C9) },
7212     { PREFIX_TABLE (PREFIX_0F38CA) },
7213     { PREFIX_TABLE (PREFIX_0F38CB) },
7214     { PREFIX_TABLE (PREFIX_0F38CC) },
7215     { PREFIX_TABLE (PREFIX_0F38CD) },
7216     { Bad_Opcode },
7217     { PREFIX_TABLE (PREFIX_0F38CF) },
7218     /* d0 */
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     /* d8 */
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { PREFIX_TABLE (PREFIX_0F38DB) },
7232     { PREFIX_TABLE (PREFIX_0F38DC) },
7233     { PREFIX_TABLE (PREFIX_0F38DD) },
7234     { PREFIX_TABLE (PREFIX_0F38DE) },
7235     { PREFIX_TABLE (PREFIX_0F38DF) },
7236     /* e0 */
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     /* e8 */
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     /* f0 */
7255     { PREFIX_TABLE (PREFIX_0F38F0) },
7256     { PREFIX_TABLE (PREFIX_0F38F1) },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { PREFIX_TABLE (PREFIX_0F38F5) },
7261     { PREFIX_TABLE (PREFIX_0F38F6) },
7262     { Bad_Opcode },
7263     /* f8 */
7264     { PREFIX_TABLE (PREFIX_0F38F8) },
7265     { PREFIX_TABLE (PREFIX_0F38F9) },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272   },
7273   /* THREE_BYTE_0F3A */
7274   {
7275     /* 00 */
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     /* 08 */
7285     { PREFIX_TABLE (PREFIX_0F3A08) },
7286     { PREFIX_TABLE (PREFIX_0F3A09) },
7287     { PREFIX_TABLE (PREFIX_0F3A0A) },
7288     { PREFIX_TABLE (PREFIX_0F3A0B) },
7289     { PREFIX_TABLE (PREFIX_0F3A0C) },
7290     { PREFIX_TABLE (PREFIX_0F3A0D) },
7291     { PREFIX_TABLE (PREFIX_0F3A0E) },
7292     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7293     /* 10 */
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { PREFIX_TABLE (PREFIX_0F3A14) },
7299     { PREFIX_TABLE (PREFIX_0F3A15) },
7300     { PREFIX_TABLE (PREFIX_0F3A16) },
7301     { PREFIX_TABLE (PREFIX_0F3A17) },
7302     /* 18 */
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     /* 20 */
7312     { PREFIX_TABLE (PREFIX_0F3A20) },
7313     { PREFIX_TABLE (PREFIX_0F3A21) },
7314     { PREFIX_TABLE (PREFIX_0F3A22) },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     /* 28 */
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     /* 30 */
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     /* 38 */
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     /* 40 */
7348     { PREFIX_TABLE (PREFIX_0F3A40) },
7349     { PREFIX_TABLE (PREFIX_0F3A41) },
7350     { PREFIX_TABLE (PREFIX_0F3A42) },
7351     { Bad_Opcode },
7352     { PREFIX_TABLE (PREFIX_0F3A44) },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     /* 48 */
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     /* 50 */
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     /* 58 */
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     /* 60 */
7384     { PREFIX_TABLE (PREFIX_0F3A60) },
7385     { PREFIX_TABLE (PREFIX_0F3A61) },
7386     { PREFIX_TABLE (PREFIX_0F3A62) },
7387     { PREFIX_TABLE (PREFIX_0F3A63) },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     /* 68 */
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     /* 70 */
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     /* 78 */
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     /* 80 */
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     /* 88 */
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     /* 90 */
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     /* 98 */
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     /* a0 */
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     /* a8 */
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     /* b0 */
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     /* b8 */
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     /* c0 */
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     /* c8 */
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { PREFIX_TABLE (PREFIX_0F3ACC) },
7506     { Bad_Opcode },
7507     { PREFIX_TABLE (PREFIX_0F3ACE) },
7508     { PREFIX_TABLE (PREFIX_0F3ACF) },
7509     /* d0 */
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     /* d8 */
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { PREFIX_TABLE (PREFIX_0F3ADF) },
7527     /* e0 */
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     /* e8 */
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     /* f0 */
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     /* f8 */
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563   },
7564 };
7565
7566 static const struct dis386 xop_table[][256] = {
7567   /* XOP_08 */
7568   {
7569     /* 00 */
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     /* 08 */
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     /* 10 */
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     /* 18 */
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     /* 20 */
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     /* 28 */
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     /* 30 */
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     /* 38 */
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     /* 40 */
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     /* 48 */
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     /* 50 */
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     /* 58 */
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     /* 60 */
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     /* 68 */
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     /* 70 */
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     /* 78 */
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     /* 80 */
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7720     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7721     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7722     /* 88 */
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7730     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7731     /* 90 */
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7738     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7739     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7740     /* 98 */
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7748     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7749     /* a0 */
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7753     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7757     { Bad_Opcode },
7758     /* a8 */
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     /* b0 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7775     { Bad_Opcode },
7776     /* b8 */
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     /* c0 */
7786     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7787     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7788     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7789     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     /* c8 */
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7800     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7801     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7802     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7803     /* d0 */
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     /* d8 */
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     /* e0 */
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     /* e8 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7836     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7837     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7838     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7839     /* f0 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     /* f8 */
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857   },
7858   /* XOP_09 */
7859   {
7860     /* 00 */
7861     { Bad_Opcode },
7862     { REG_TABLE (REG_XOP_TBM_01) },
7863     { REG_TABLE (REG_XOP_TBM_02) },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     /* 08 */
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     /* 10 */
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { REG_TABLE (REG_XOP_LWPCB) },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     /* 18 */
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     /* 20 */
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     /* 28 */
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     /* 30 */
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     /* 38 */
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     /* 40 */
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     /* 48 */
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     /* 50 */
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     /* 58 */
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     /* 60 */
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     /* 68 */
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     /* 70 */
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     /* 78 */
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     /* 80 */
8005     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8006     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8007     { "vfrczss",        { XM, EXd }, 0 },
8008     { "vfrczsd",        { XM, EXq }, 0 },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     /* 88 */
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     /* 90 */
8023     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8024     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8025     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8026     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8027     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8028     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8029     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8030     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8031     /* 98 */
8032     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8033     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8034     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8035     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     /* a0 */
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     /* a8 */
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     /* b0 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* b8 */
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     /* c0 */
8077     { Bad_Opcode },
8078     { "vphaddbw",       { XM, EXxmm }, 0 },
8079     { "vphaddbd",       { XM, EXxmm }, 0 },
8080     { "vphaddbq",       { XM, EXxmm }, 0 },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { "vphaddwd",       { XM, EXxmm }, 0 },
8084     { "vphaddwq",       { XM, EXxmm }, 0 },
8085     /* c8 */
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { "vphadddq",       { XM, EXxmm }, 0 },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     /* d0 */
8095     { Bad_Opcode },
8096     { "vphaddubw",      { XM, EXxmm }, 0 },
8097     { "vphaddubd",      { XM, EXxmm }, 0 },
8098     { "vphaddubq",      { XM, EXxmm }, 0 },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { "vphadduwd",      { XM, EXxmm }, 0 },
8102     { "vphadduwq",      { XM, EXxmm }, 0 },
8103     /* d8 */
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { "vphaddudq",      { XM, EXxmm }, 0 },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     /* e0 */
8113     { Bad_Opcode },
8114     { "vphsubbw",       { XM, EXxmm }, 0 },
8115     { "vphsubwd",       { XM, EXxmm }, 0 },
8116     { "vphsubdq",       { XM, EXxmm }, 0 },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     /* e8 */
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* f0 */
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     /* f8 */
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148   },
8149   /* XOP_0A */
8150   {
8151     /* 00 */
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     /* 08 */
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     /* 10 */
8170     { "bextrS", { Gdq, Edq, Id }, 0 },
8171     { Bad_Opcode },
8172     { REG_TABLE (REG_XOP_LWP) },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     /* 18 */
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     /* 20 */
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     /* 28 */
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     /* 30 */
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     /* 38 */
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     /* 40 */
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     /* 48 */
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     /* 50 */
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     /* 58 */
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     /* 60 */
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     /* 68 */
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     /* 70 */
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     /* 78 */
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     /* 80 */
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     /* 88 */
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     /* 90 */
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     /* 98 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     /* a0 */
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     /* a8 */
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     /* b0 */
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     /* b8 */
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     /* c0 */
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     /* c8 */
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     /* d0 */
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     /* d8 */
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     /* e0 */
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     /* e8 */
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     /* f0 */
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     /* f8 */
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439   },
8440 };
8441
8442 static const struct dis386 vex_table[][256] = {
8443   /* VEX_0F */
8444   {
8445     /* 00 */
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     /* 08 */
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     /* 10 */
8464     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8465     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8466     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8467     { MOD_TABLE (MOD_VEX_0F13) },
8468     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8469     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8470     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8471     { MOD_TABLE (MOD_VEX_0F17) },
8472     /* 18 */
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     /* 20 */
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     /* 28 */
8491     { "vmovapX",        { XM, EXx }, 0 },
8492     { "vmovapX",        { EXxS, XM }, 0 },
8493     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8494     { MOD_TABLE (MOD_VEX_0F2B) },
8495     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8496     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8497     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8498     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8499     /* 30 */
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     /* 38 */
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     /* 40 */
8518     { Bad_Opcode },
8519     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8520     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8521     { Bad_Opcode },
8522     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8526     /* 48 */
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     /* 50 */
8536     { MOD_TABLE (MOD_VEX_0F50) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8540     { "vandpX",         { XM, Vex, EXx }, 0 },
8541     { "vandnpX",        { XM, Vex, EXx }, 0 },
8542     { "vorpX",          { XM, Vex, EXx }, 0 },
8543     { "vxorpX",         { XM, Vex, EXx }, 0 },
8544     /* 58 */
8545     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8550     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8551     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8553     /* 60 */
8554     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8558     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8559     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8560     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8561     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8562     /* 68 */
8563     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8564     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8569     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8571     /* 70 */
8572     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8573     { REG_TABLE (REG_VEX_0F71) },
8574     { REG_TABLE (REG_VEX_0F72) },
8575     { REG_TABLE (REG_VEX_0F73) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8578     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8579     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8580     /* 78 */
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8586     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8587     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8588     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8589     /* 80 */
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     /* 88 */
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     /* 90 */
8608     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     /* 98 */
8617     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8618     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     /* a0 */
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     /* a8 */
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { REG_TABLE (REG_VEX_0FAE) },
8642     { Bad_Opcode },
8643     /* b0 */
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     /* b8 */
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     /* c0 */
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8665     { Bad_Opcode },
8666     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8667     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8668     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8669     { Bad_Opcode },
8670     /* c8 */
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     /* d0 */
8680     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8688     /* d8 */
8689     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8697     /* e0 */
8698     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8706     /* e8 */
8707     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8713     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8715     /* f0 */
8716     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8721     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8722     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8723     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8724     /* f8 */
8725     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8726     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8727     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8728     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8729     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8730     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8731     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8732     { Bad_Opcode },
8733   },
8734   /* VEX_0F38 */
8735   {
8736     /* 00 */
8737     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8745     /* 08 */
8746     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8754     /* 10 */
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8763     /* 18 */
8764     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8767     { Bad_Opcode },
8768     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8771     { Bad_Opcode },
8772     /* 20 */
8773     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     /* 28 */
8782     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8790     /* 30 */
8791     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8799     /* 38 */
8800     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8808     /* 40 */
8809     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8817     /* 48 */
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     /* 50 */
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     /* 58 */
8836     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8837     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8838     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     /* 60 */
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     /* 68 */
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     /* 70 */
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     /* 78 */
8872     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8873     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     /* 80 */
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     /* 88 */
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8895     { Bad_Opcode },
8896     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8897     { Bad_Opcode },
8898     /* 90 */
8899     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8907     /* 98 */
8908     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8916     /* a0 */
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8925     /* a8 */
8926     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8934     /* b0 */
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8943     /* b8 */
8944     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8952     /* c0 */
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     /* c8 */
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8970     /* d0 */
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     /* d8 */
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8988     /* e0 */
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     /* e8 */
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     /* f0 */
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9010     { REG_TABLE (REG_VEX_0F38F3) },
9011     { Bad_Opcode },
9012     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9015     /* f8 */
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024   },
9025   /* VEX_0F3A */
9026   {
9027     /* 00 */
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9031     { Bad_Opcode },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9035     { Bad_Opcode },
9036     /* 08 */
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9045     /* 10 */
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9054     /* 18 */
9055     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     /* 20 */
9064     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9065     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     /* 28 */
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     /* 30 */
9082     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     /* 38 */
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     /* 40 */
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9103     { Bad_Opcode },
9104     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9105     { Bad_Opcode },
9106     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9107     { Bad_Opcode },
9108     /* 48 */
9109     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     /* 50 */
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     /* 58 */
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9135     /* 60 */
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     /* 68 */
9145     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9146     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9147     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9148     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9149     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9150     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9153     /* 70 */
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     /* 78 */
9163     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9164     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9165     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9166     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9167     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9168     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9169     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9170     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9171     /* 80 */
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     /* 88 */
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     /* 90 */
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     /* 98 */
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     /* a0 */
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     /* a8 */
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     /* b0 */
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     /* b8 */
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     /* c0 */
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     /* c8 */
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9260     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9261     /* d0 */
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     /* d8 */
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9279     /* e0 */
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     /* e8 */
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     /* f0 */
9298     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     /* f8 */
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315   },
9316 };
9317
9318 #include "i386-dis-evex.h"
9319
9320 static const struct dis386 vex_len_table[][2] = {
9321   /* VEX_LEN_0F12_P_0_M_0 */
9322   {
9323     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9324   },
9325
9326   /* VEX_LEN_0F12_P_0_M_1 */
9327   {
9328     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9329   },
9330
9331   /* VEX_LEN_0F12_P_2 */
9332   {
9333     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9334   },
9335
9336   /* VEX_LEN_0F13_M_0 */
9337   {
9338     { "vmovlpX",        { EXq, XM }, 0 },
9339   },
9340
9341   /* VEX_LEN_0F16_P_0_M_0 */
9342   {
9343     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9344   },
9345
9346   /* VEX_LEN_0F16_P_0_M_1 */
9347   {
9348     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9349   },
9350
9351   /* VEX_LEN_0F16_P_2 */
9352   {
9353     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9354   },
9355
9356   /* VEX_LEN_0F17_M_0 */
9357   {
9358     { "vmovhpX",        { EXq, XM }, 0 },
9359   },
9360
9361   /* VEX_LEN_0F41_P_0 */
9362   {
9363     { Bad_Opcode },
9364     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9365   },
9366   /* VEX_LEN_0F41_P_2 */
9367   {
9368     { Bad_Opcode },
9369     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9370   },
9371   /* VEX_LEN_0F42_P_0 */
9372   {
9373     { Bad_Opcode },
9374     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9375   },
9376   /* VEX_LEN_0F42_P_2 */
9377   {
9378     { Bad_Opcode },
9379     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9380   },
9381   /* VEX_LEN_0F44_P_0 */
9382   {
9383     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9384   },
9385   /* VEX_LEN_0F44_P_2 */
9386   {
9387     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9388   },
9389   /* VEX_LEN_0F45_P_0 */
9390   {
9391     { Bad_Opcode },
9392     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9393   },
9394   /* VEX_LEN_0F45_P_2 */
9395   {
9396     { Bad_Opcode },
9397     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9398   },
9399   /* VEX_LEN_0F46_P_0 */
9400   {
9401     { Bad_Opcode },
9402     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9403   },
9404   /* VEX_LEN_0F46_P_2 */
9405   {
9406     { Bad_Opcode },
9407     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9408   },
9409   /* VEX_LEN_0F47_P_0 */
9410   {
9411     { Bad_Opcode },
9412     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9413   },
9414   /* VEX_LEN_0F47_P_2 */
9415   {
9416     { Bad_Opcode },
9417     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9418   },
9419   /* VEX_LEN_0F4A_P_0 */
9420   {
9421     { Bad_Opcode },
9422     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9423   },
9424   /* VEX_LEN_0F4A_P_2 */
9425   {
9426     { Bad_Opcode },
9427     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9428   },
9429   /* VEX_LEN_0F4B_P_0 */
9430   {
9431     { Bad_Opcode },
9432     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9433   },
9434   /* VEX_LEN_0F4B_P_2 */
9435   {
9436     { Bad_Opcode },
9437     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9438   },
9439
9440   /* VEX_LEN_0F6E_P_2 */
9441   {
9442     { "vmovK",          { XMScalar, Edq }, 0 },
9443   },
9444
9445   /* VEX_LEN_0F77_P_1 */
9446   {
9447     { "vzeroupper",     { XX }, 0 },
9448     { "vzeroall",       { XX }, 0 },
9449   },
9450
9451   /* VEX_LEN_0F7E_P_1 */
9452   {
9453     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9454   },
9455
9456   /* VEX_LEN_0F7E_P_2 */
9457   {
9458     { "vmovK",          { Edq, XMScalar }, 0 },
9459   },
9460
9461   /* VEX_LEN_0F90_P_0 */
9462   {
9463     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9464   },
9465
9466   /* VEX_LEN_0F90_P_2 */
9467   {
9468     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9469   },
9470
9471   /* VEX_LEN_0F91_P_0 */
9472   {
9473     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9474   },
9475
9476   /* VEX_LEN_0F91_P_2 */
9477   {
9478     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9479   },
9480
9481   /* VEX_LEN_0F92_P_0 */
9482   {
9483     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9484   },
9485
9486   /* VEX_LEN_0F92_P_2 */
9487   {
9488     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9489   },
9490
9491   /* VEX_LEN_0F92_P_3 */
9492   {
9493     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9494   },
9495
9496   /* VEX_LEN_0F93_P_0 */
9497   {
9498     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9499   },
9500
9501   /* VEX_LEN_0F93_P_2 */
9502   {
9503     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9504   },
9505
9506   /* VEX_LEN_0F93_P_3 */
9507   {
9508     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9509   },
9510
9511   /* VEX_LEN_0F98_P_0 */
9512   {
9513     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9514   },
9515
9516   /* VEX_LEN_0F98_P_2 */
9517   {
9518     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9519   },
9520
9521   /* VEX_LEN_0F99_P_0 */
9522   {
9523     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9524   },
9525
9526   /* VEX_LEN_0F99_P_2 */
9527   {
9528     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9529   },
9530
9531   /* VEX_LEN_0FAE_R_2_M_0 */
9532   {
9533     { "vldmxcsr",       { Md }, 0 },
9534   },
9535
9536   /* VEX_LEN_0FAE_R_3_M_0 */
9537   {
9538     { "vstmxcsr",       { Md }, 0 },
9539   },
9540
9541   /* VEX_LEN_0FC4_P_2 */
9542   {
9543     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9544   },
9545
9546   /* VEX_LEN_0FC5_P_2 */
9547   {
9548     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9549   },
9550
9551   /* VEX_LEN_0FD6_P_2 */
9552   {
9553     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9554   },
9555
9556   /* VEX_LEN_0FF7_P_2 */
9557   {
9558     { "vmaskmovdqu",    { XM, XS }, 0 },
9559   },
9560
9561   /* VEX_LEN_0F3816_P_2 */
9562   {
9563     { Bad_Opcode },
9564     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9565   },
9566
9567   /* VEX_LEN_0F3819_P_2 */
9568   {
9569     { Bad_Opcode },
9570     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9571   },
9572
9573   /* VEX_LEN_0F381A_P_2_M_0 */
9574   {
9575     { Bad_Opcode },
9576     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9577   },
9578
9579   /* VEX_LEN_0F3836_P_2 */
9580   {
9581     { Bad_Opcode },
9582     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9583   },
9584
9585   /* VEX_LEN_0F3841_P_2 */
9586   {
9587     { "vphminposuw",    { XM, EXx }, 0 },
9588   },
9589
9590   /* VEX_LEN_0F385A_P_2_M_0 */
9591   {
9592     { Bad_Opcode },
9593     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9594   },
9595
9596   /* VEX_LEN_0F38DB_P_2 */
9597   {
9598     { "vaesimc",        { XM, EXx }, 0 },
9599   },
9600
9601   /* VEX_LEN_0F38F2_P_0 */
9602   {
9603     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9604   },
9605
9606   /* VEX_LEN_0F38F3_R_1_P_0 */
9607   {
9608     { "blsrS",          { VexGdq, Edq }, 0 },
9609   },
9610
9611   /* VEX_LEN_0F38F3_R_2_P_0 */
9612   {
9613     { "blsmskS",        { VexGdq, Edq }, 0 },
9614   },
9615
9616   /* VEX_LEN_0F38F3_R_3_P_0 */
9617   {
9618     { "blsiS",          { VexGdq, Edq }, 0 },
9619   },
9620
9621   /* VEX_LEN_0F38F5_P_0 */
9622   {
9623     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9624   },
9625
9626   /* VEX_LEN_0F38F5_P_1 */
9627   {
9628     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9629   },
9630
9631   /* VEX_LEN_0F38F5_P_3 */
9632   {
9633     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9634   },
9635
9636   /* VEX_LEN_0F38F6_P_3 */
9637   {
9638     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9639   },
9640
9641   /* VEX_LEN_0F38F7_P_0 */
9642   {
9643     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9644   },
9645
9646   /* VEX_LEN_0F38F7_P_1 */
9647   {
9648     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9649   },
9650
9651   /* VEX_LEN_0F38F7_P_2 */
9652   {
9653     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9654   },
9655
9656   /* VEX_LEN_0F38F7_P_3 */
9657   {
9658     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9659   },
9660
9661   /* VEX_LEN_0F3A00_P_2 */
9662   {
9663     { Bad_Opcode },
9664     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9665   },
9666
9667   /* VEX_LEN_0F3A01_P_2 */
9668   {
9669     { Bad_Opcode },
9670     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9671   },
9672
9673   /* VEX_LEN_0F3A06_P_2 */
9674   {
9675     { Bad_Opcode },
9676     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9677   },
9678
9679   /* VEX_LEN_0F3A14_P_2 */
9680   {
9681     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9682   },
9683
9684   /* VEX_LEN_0F3A15_P_2 */
9685   {
9686     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9687   },
9688
9689   /* VEX_LEN_0F3A16_P_2  */
9690   {
9691     { "vpextrK",        { Edq, XM, Ib }, 0 },
9692   },
9693
9694   /* VEX_LEN_0F3A17_P_2 */
9695   {
9696     { "vextractps",     { Edqd, XM, Ib }, 0 },
9697   },
9698
9699   /* VEX_LEN_0F3A18_P_2 */
9700   {
9701     { Bad_Opcode },
9702     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9703   },
9704
9705   /* VEX_LEN_0F3A19_P_2 */
9706   {
9707     { Bad_Opcode },
9708     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9709   },
9710
9711   /* VEX_LEN_0F3A20_P_2 */
9712   {
9713     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9714   },
9715
9716   /* VEX_LEN_0F3A21_P_2 */
9717   {
9718     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9719   },
9720
9721   /* VEX_LEN_0F3A22_P_2 */
9722   {
9723     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9724   },
9725
9726   /* VEX_LEN_0F3A30_P_2 */
9727   {
9728     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9729   },
9730
9731   /* VEX_LEN_0F3A31_P_2 */
9732   {
9733     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9734   },
9735
9736   /* VEX_LEN_0F3A32_P_2 */
9737   {
9738     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9739   },
9740
9741   /* VEX_LEN_0F3A33_P_2 */
9742   {
9743     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9744   },
9745
9746   /* VEX_LEN_0F3A38_P_2 */
9747   {
9748     { Bad_Opcode },
9749     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9750   },
9751
9752   /* VEX_LEN_0F3A39_P_2 */
9753   {
9754     { Bad_Opcode },
9755     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9756   },
9757
9758   /* VEX_LEN_0F3A41_P_2 */
9759   {
9760     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9761   },
9762
9763   /* VEX_LEN_0F3A46_P_2 */
9764   {
9765     { Bad_Opcode },
9766     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9767   },
9768
9769   /* VEX_LEN_0F3A60_P_2 */
9770   {
9771     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9772   },
9773
9774   /* VEX_LEN_0F3A61_P_2 */
9775   {
9776     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9777   },
9778
9779   /* VEX_LEN_0F3A62_P_2 */
9780   {
9781     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9782   },
9783
9784   /* VEX_LEN_0F3A63_P_2 */
9785   {
9786     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9787   },
9788
9789   /* VEX_LEN_0F3A6A_P_2 */
9790   {
9791     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9792   },
9793
9794   /* VEX_LEN_0F3A6B_P_2 */
9795   {
9796     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9797   },
9798
9799   /* VEX_LEN_0F3A6E_P_2 */
9800   {
9801     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9802   },
9803
9804   /* VEX_LEN_0F3A6F_P_2 */
9805   {
9806     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9807   },
9808
9809   /* VEX_LEN_0F3A7A_P_2 */
9810   {
9811     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9812   },
9813
9814   /* VEX_LEN_0F3A7B_P_2 */
9815   {
9816     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9817   },
9818
9819   /* VEX_LEN_0F3A7E_P_2 */
9820   {
9821     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9822   },
9823
9824   /* VEX_LEN_0F3A7F_P_2 */
9825   {
9826     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9827   },
9828
9829   /* VEX_LEN_0F3ADF_P_2 */
9830   {
9831     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9832   },
9833
9834   /* VEX_LEN_0F3AF0_P_3 */
9835   {
9836     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9837   },
9838
9839   /* VEX_LEN_0FXOP_08_CC */
9840   {
9841      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9842   },
9843
9844   /* VEX_LEN_0FXOP_08_CD */
9845   {
9846      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9847   },
9848
9849   /* VEX_LEN_0FXOP_08_CE */
9850   {
9851      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9852   },
9853
9854   /* VEX_LEN_0FXOP_08_CF */
9855   {
9856      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9857   },
9858
9859   /* VEX_LEN_0FXOP_08_EC */
9860   {
9861      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9862   },
9863
9864   /* VEX_LEN_0FXOP_08_ED */
9865   {
9866      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9867   },
9868
9869   /* VEX_LEN_0FXOP_08_EE */
9870   {
9871      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9872   },
9873
9874   /* VEX_LEN_0FXOP_08_EF */
9875   {
9876      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9877   },
9878
9879   /* VEX_LEN_0FXOP_09_80 */
9880   {
9881     { "vfrczps",        { XM, EXxmm }, 0 },
9882     { "vfrczps",        { XM, EXymmq }, 0 },
9883   },
9884
9885   /* VEX_LEN_0FXOP_09_81 */
9886   {
9887     { "vfrczpd",        { XM, EXxmm }, 0 },
9888     { "vfrczpd",        { XM, EXymmq }, 0 },
9889   },
9890 };
9891
9892 #include "i386-dis-evex-len.h"
9893
9894 static const struct dis386 vex_w_table[][2] = {
9895   {
9896     /* VEX_W_0F41_P_0_LEN_1 */
9897     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9898     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9899   },
9900   {
9901     /* VEX_W_0F41_P_2_LEN_1 */
9902     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9903     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9904   },
9905   {
9906     /* VEX_W_0F42_P_0_LEN_1 */
9907     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9908     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9909   },
9910   {
9911     /* VEX_W_0F42_P_2_LEN_1 */
9912     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9913     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9914   },
9915   {
9916     /* VEX_W_0F44_P_0_LEN_0 */
9917     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9918     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9919   },
9920   {
9921     /* VEX_W_0F44_P_2_LEN_0 */
9922     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9923     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9924   },
9925   {
9926     /* VEX_W_0F45_P_0_LEN_1 */
9927     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9928     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9929   },
9930   {
9931     /* VEX_W_0F45_P_2_LEN_1 */
9932     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9933     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9934   },
9935   {
9936     /* VEX_W_0F46_P_0_LEN_1 */
9937     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9938     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9939   },
9940   {
9941     /* VEX_W_0F46_P_2_LEN_1 */
9942     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9943     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9944   },
9945   {
9946     /* VEX_W_0F47_P_0_LEN_1 */
9947     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9948     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9949   },
9950   {
9951     /* VEX_W_0F47_P_2_LEN_1 */
9952     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9953     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9954   },
9955   {
9956     /* VEX_W_0F4A_P_0_LEN_1 */
9957     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9958     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9959   },
9960   {
9961     /* VEX_W_0F4A_P_2_LEN_1 */
9962     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9963     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9964   },
9965   {
9966     /* VEX_W_0F4B_P_0_LEN_1 */
9967     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9968     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9969   },
9970   {
9971     /* VEX_W_0F4B_P_2_LEN_1 */
9972     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9973   },
9974   {
9975     /* VEX_W_0F90_P_0_LEN_0 */
9976     { "kmovw",          { MaskG, MaskE }, 0 },
9977     { "kmovq",          { MaskG, MaskE }, 0 },
9978   },
9979   {
9980     /* VEX_W_0F90_P_2_LEN_0 */
9981     { "kmovb",          { MaskG, MaskBDE }, 0 },
9982     { "kmovd",          { MaskG, MaskBDE }, 0 },
9983   },
9984   {
9985     /* VEX_W_0F91_P_0_LEN_0 */
9986     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9987     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9988   },
9989   {
9990     /* VEX_W_0F91_P_2_LEN_0 */
9991     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9992     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9993   },
9994   {
9995     /* VEX_W_0F92_P_0_LEN_0 */
9996     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9997   },
9998   {
9999     /* VEX_W_0F92_P_2_LEN_0 */
10000     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10001   },
10002   {
10003     /* VEX_W_0F93_P_0_LEN_0 */
10004     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10005   },
10006   {
10007     /* VEX_W_0F93_P_2_LEN_0 */
10008     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10009   },
10010   {
10011     /* VEX_W_0F98_P_0_LEN_0 */
10012     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10013     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10014   },
10015   {
10016     /* VEX_W_0F98_P_2_LEN_0 */
10017     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10018     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10019   },
10020   {
10021     /* VEX_W_0F99_P_0_LEN_0 */
10022     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10023     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10024   },
10025   {
10026     /* VEX_W_0F99_P_2_LEN_0 */
10027     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10028     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10029   },
10030   {
10031     /* VEX_W_0F380C_P_2  */
10032     { "vpermilps",      { XM, Vex, EXx }, 0 },
10033   },
10034   {
10035     /* VEX_W_0F380D_P_2  */
10036     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10037   },
10038   {
10039     /* VEX_W_0F380E_P_2  */
10040     { "vtestps",        { XM, EXx }, 0 },
10041   },
10042   {
10043     /* VEX_W_0F380F_P_2  */
10044     { "vtestpd",        { XM, EXx }, 0 },
10045   },
10046   {
10047     /* VEX_W_0F3816_P_2  */
10048     { "vpermps",        { XM, Vex, EXx }, 0 },
10049   },
10050   {
10051     /* VEX_W_0F3818_P_2 */
10052     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10053   },
10054   {
10055     /* VEX_W_0F3819_P_2 */
10056     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10057   },
10058   {
10059     /* VEX_W_0F381A_P_2_M_0 */
10060     { "vbroadcastf128", { XM, Mxmm }, 0 },
10061   },
10062   {
10063     /* VEX_W_0F382C_P_2_M_0 */
10064     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10065   },
10066   {
10067     /* VEX_W_0F382D_P_2_M_0 */
10068     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10069   },
10070   {
10071     /* VEX_W_0F382E_P_2_M_0 */
10072     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10073   },
10074   {
10075     /* VEX_W_0F382F_P_2_M_0 */
10076     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10077   },
10078   {
10079     /* VEX_W_0F3836_P_2  */
10080     { "vpermd",         { XM, Vex, EXx }, 0 },
10081   },
10082   {
10083     /* VEX_W_0F3846_P_2 */
10084     { "vpsravd",        { XM, Vex, EXx }, 0 },
10085   },
10086   {
10087     /* VEX_W_0F3858_P_2 */
10088     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10089   },
10090   {
10091     /* VEX_W_0F3859_P_2 */
10092     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10093   },
10094   {
10095     /* VEX_W_0F385A_P_2_M_0 */
10096     { "vbroadcasti128", { XM, Mxmm }, 0 },
10097   },
10098   {
10099     /* VEX_W_0F3878_P_2 */
10100     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10101   },
10102   {
10103     /* VEX_W_0F3879_P_2 */
10104     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10105   },
10106   {
10107     /* VEX_W_0F38CF_P_2 */
10108     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10109   },
10110   {
10111     /* VEX_W_0F3A00_P_2 */
10112     { Bad_Opcode },
10113     { "vpermq",         { XM, EXx, Ib }, 0 },
10114   },
10115   {
10116     /* VEX_W_0F3A01_P_2 */
10117     { Bad_Opcode },
10118     { "vpermpd",        { XM, EXx, Ib }, 0 },
10119   },
10120   {
10121     /* VEX_W_0F3A02_P_2 */
10122     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10123   },
10124   {
10125     /* VEX_W_0F3A04_P_2 */
10126     { "vpermilps",      { XM, EXx, Ib }, 0 },
10127   },
10128   {
10129     /* VEX_W_0F3A05_P_2 */
10130     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10131   },
10132   {
10133     /* VEX_W_0F3A06_P_2 */
10134     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10135   },
10136   {
10137     /* VEX_W_0F3A18_P_2 */
10138     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10139   },
10140   {
10141     /* VEX_W_0F3A19_P_2 */
10142     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10143   },
10144   {
10145     /* VEX_W_0F3A30_P_2_LEN_0 */
10146     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10147     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10148   },
10149   {
10150     /* VEX_W_0F3A31_P_2_LEN_0 */
10151     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10152     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10153   },
10154   {
10155     /* VEX_W_0F3A32_P_2_LEN_0 */
10156     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10157     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10158   },
10159   {
10160     /* VEX_W_0F3A33_P_2_LEN_0 */
10161     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10162     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10163   },
10164   {
10165     /* VEX_W_0F3A38_P_2 */
10166     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10167   },
10168   {
10169     /* VEX_W_0F3A39_P_2 */
10170     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10171   },
10172   {
10173     /* VEX_W_0F3A46_P_2 */
10174     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10175   },
10176   {
10177     /* VEX_W_0F3A48_P_2 */
10178     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10179     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10180   },
10181   {
10182     /* VEX_W_0F3A49_P_2 */
10183     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10184     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10185   },
10186   {
10187     /* VEX_W_0F3A4A_P_2 */
10188     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10189   },
10190   {
10191     /* VEX_W_0F3A4B_P_2 */
10192     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10193   },
10194   {
10195     /* VEX_W_0F3A4C_P_2 */
10196     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10197   },
10198   {
10199     /* VEX_W_0F3ACE_P_2 */
10200     { Bad_Opcode },
10201     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10202   },
10203   {
10204     /* VEX_W_0F3ACF_P_2 */
10205     { Bad_Opcode },
10206     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10207   },
10208
10209 #include "i386-dis-evex-w.h"
10210 };
10211
10212 static const struct dis386 mod_table[][2] = {
10213   {
10214     /* MOD_8D */
10215     { "leaS",           { Gv, M }, 0 },
10216   },
10217   {
10218     /* MOD_C6_REG_7 */
10219     { Bad_Opcode },
10220     { RM_TABLE (RM_C6_REG_7) },
10221   },
10222   {
10223     /* MOD_C7_REG_7 */
10224     { Bad_Opcode },
10225     { RM_TABLE (RM_C7_REG_7) },
10226   },
10227   {
10228     /* MOD_FF_REG_3 */
10229     { "Jcall^", { indirEp }, 0 },
10230   },
10231   {
10232     /* MOD_FF_REG_5 */
10233     { "Jjmp^", { indirEp }, 0 },
10234   },
10235   {
10236     /* MOD_0F01_REG_0 */
10237     { X86_64_TABLE (X86_64_0F01_REG_0) },
10238     { RM_TABLE (RM_0F01_REG_0) },
10239   },
10240   {
10241     /* MOD_0F01_REG_1 */
10242     { X86_64_TABLE (X86_64_0F01_REG_1) },
10243     { RM_TABLE (RM_0F01_REG_1) },
10244   },
10245   {
10246     /* MOD_0F01_REG_2 */
10247     { X86_64_TABLE (X86_64_0F01_REG_2) },
10248     { RM_TABLE (RM_0F01_REG_2) },
10249   },
10250   {
10251     /* MOD_0F01_REG_3 */
10252     { X86_64_TABLE (X86_64_0F01_REG_3) },
10253     { RM_TABLE (RM_0F01_REG_3) },
10254   },
10255   {
10256     /* MOD_0F01_REG_5 */
10257     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10258     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10259   },
10260   {
10261     /* MOD_0F01_REG_7 */
10262     { "invlpg",         { Mb }, 0 },
10263     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10264   },
10265   {
10266     /* MOD_0F12_PREFIX_0 */
10267     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10268     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10269   },
10270   {
10271     /* MOD_0F13 */
10272     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10273   },
10274   {
10275     /* MOD_0F16_PREFIX_0 */
10276     { "movhps",         { XM, EXq }, 0 },
10277     { "movlhps",        { XM, EXq }, 0 },
10278   },
10279   {
10280     /* MOD_0F17 */
10281     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10282   },
10283   {
10284     /* MOD_0F18_REG_0 */
10285     { "prefetchnta",    { Mb }, 0 },
10286   },
10287   {
10288     /* MOD_0F18_REG_1 */
10289     { "prefetcht0",     { Mb }, 0 },
10290   },
10291   {
10292     /* MOD_0F18_REG_2 */
10293     { "prefetcht1",     { Mb }, 0 },
10294   },
10295   {
10296     /* MOD_0F18_REG_3 */
10297     { "prefetcht2",     { Mb }, 0 },
10298   },
10299   {
10300     /* MOD_0F18_REG_4 */
10301     { "nop/reserved",   { Mb }, 0 },
10302   },
10303   {
10304     /* MOD_0F18_REG_5 */
10305     { "nop/reserved",   { Mb }, 0 },
10306   },
10307   {
10308     /* MOD_0F18_REG_6 */
10309     { "nop/reserved",   { Mb }, 0 },
10310   },
10311   {
10312     /* MOD_0F18_REG_7 */
10313     { "nop/reserved",   { Mb }, 0 },
10314   },
10315   {
10316     /* MOD_0F1A_PREFIX_0 */
10317     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10318     { "nopQ",           { Ev }, 0 },
10319   },
10320   {
10321     /* MOD_0F1B_PREFIX_0 */
10322     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10323     { "nopQ",           { Ev }, 0 },
10324   },
10325   {
10326     /* MOD_0F1B_PREFIX_1 */
10327     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10328     { "nopQ",           { Ev }, 0 },
10329   },
10330   {
10331     /* MOD_0F1C_PREFIX_0 */
10332     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10333     { "nopQ",           { Ev }, 0 },
10334   },
10335   {
10336     /* MOD_0F1E_PREFIX_1 */
10337     { "nopQ",           { Ev }, 0 },
10338     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10339   },
10340   {
10341     /* MOD_0F24 */
10342     { Bad_Opcode },
10343     { "movL",           { Rd, Td }, 0 },
10344   },
10345   {
10346     /* MOD_0F26 */
10347     { Bad_Opcode },
10348     { "movL",           { Td, Rd }, 0 },
10349   },
10350   {
10351     /* MOD_0F2B_PREFIX_0 */
10352     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10353   },
10354   {
10355     /* MOD_0F2B_PREFIX_1 */
10356     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10357   },
10358   {
10359     /* MOD_0F2B_PREFIX_2 */
10360     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10361   },
10362   {
10363     /* MOD_0F2B_PREFIX_3 */
10364     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10365   },
10366   {
10367     /* MOD_0F51 */
10368     { Bad_Opcode },
10369     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10370   },
10371   {
10372     /* MOD_0F71_REG_2 */
10373     { Bad_Opcode },
10374     { "psrlw",          { MS, Ib }, 0 },
10375   },
10376   {
10377     /* MOD_0F71_REG_4 */
10378     { Bad_Opcode },
10379     { "psraw",          { MS, Ib }, 0 },
10380   },
10381   {
10382     /* MOD_0F71_REG_6 */
10383     { Bad_Opcode },
10384     { "psllw",          { MS, Ib }, 0 },
10385   },
10386   {
10387     /* MOD_0F72_REG_2 */
10388     { Bad_Opcode },
10389     { "psrld",          { MS, Ib }, 0 },
10390   },
10391   {
10392     /* MOD_0F72_REG_4 */
10393     { Bad_Opcode },
10394     { "psrad",          { MS, Ib }, 0 },
10395   },
10396   {
10397     /* MOD_0F72_REG_6 */
10398     { Bad_Opcode },
10399     { "pslld",          { MS, Ib }, 0 },
10400   },
10401   {
10402     /* MOD_0F73_REG_2 */
10403     { Bad_Opcode },
10404     { "psrlq",          { MS, Ib }, 0 },
10405   },
10406   {
10407     /* MOD_0F73_REG_3 */
10408     { Bad_Opcode },
10409     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10410   },
10411   {
10412     /* MOD_0F73_REG_6 */
10413     { Bad_Opcode },
10414     { "psllq",          { MS, Ib }, 0 },
10415   },
10416   {
10417     /* MOD_0F73_REG_7 */
10418     { Bad_Opcode },
10419     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10420   },
10421   {
10422     /* MOD_0FAE_REG_0 */
10423     { "fxsave",         { FXSAVE }, 0 },
10424     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10425   },
10426   {
10427     /* MOD_0FAE_REG_1 */
10428     { "fxrstor",        { FXSAVE }, 0 },
10429     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10430   },
10431   {
10432     /* MOD_0FAE_REG_2 */
10433     { "ldmxcsr",        { Md }, 0 },
10434     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10435   },
10436   {
10437     /* MOD_0FAE_REG_3 */
10438     { "stmxcsr",        { Md }, 0 },
10439     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10440   },
10441   {
10442     /* MOD_0FAE_REG_4 */
10443     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10444     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10445   },
10446   {
10447     /* MOD_0FAE_REG_5 */
10448     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10449     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10450   },
10451   {
10452     /* MOD_0FAE_REG_6 */
10453     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10454     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10455   },
10456   {
10457     /* MOD_0FAE_REG_7 */
10458     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10459     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10460   },
10461   {
10462     /* MOD_0FB2 */
10463     { "lssS",           { Gv, Mp }, 0 },
10464   },
10465   {
10466     /* MOD_0FB4 */
10467     { "lfsS",           { Gv, Mp }, 0 },
10468   },
10469   {
10470     /* MOD_0FB5 */
10471     { "lgsS",           { Gv, Mp }, 0 },
10472   },
10473   {
10474     /* MOD_0FC3 */
10475     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10476   },
10477   {
10478     /* MOD_0FC7_REG_3 */
10479     { "xrstors",        { FXSAVE }, 0 },
10480   },
10481   {
10482     /* MOD_0FC7_REG_4 */
10483     { "xsavec",         { FXSAVE }, 0 },
10484   },
10485   {
10486     /* MOD_0FC7_REG_5 */
10487     { "xsaves",         { FXSAVE }, 0 },
10488   },
10489   {
10490     /* MOD_0FC7_REG_6 */
10491     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10492     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10493   },
10494   {
10495     /* MOD_0FC7_REG_7 */
10496     { "vmptrst",        { Mq }, 0 },
10497     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10498   },
10499   {
10500     /* MOD_0FD7 */
10501     { Bad_Opcode },
10502     { "pmovmskb",       { Gdq, MS }, 0 },
10503   },
10504   {
10505     /* MOD_0FE7_PREFIX_2 */
10506     { "movntdq",        { Mx, XM }, 0 },
10507   },
10508   {
10509     /* MOD_0FF0_PREFIX_3 */
10510     { "lddqu",          { XM, M }, 0 },
10511   },
10512   {
10513     /* MOD_0F382A_PREFIX_2 */
10514     { "movntdqa",       { XM, Mx }, 0 },
10515   },
10516   {
10517     /* MOD_0F38F5_PREFIX_2 */
10518     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10519   },
10520   {
10521     /* MOD_0F38F6_PREFIX_0 */
10522     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10523   },
10524   {
10525     /* MOD_0F38F8_PREFIX_1 */
10526     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10527   },
10528   {
10529     /* MOD_0F38F8_PREFIX_2 */
10530     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10531   },
10532   {
10533     /* MOD_0F38F8_PREFIX_3 */
10534     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10535   },
10536   {
10537     /* MOD_0F38F9_PREFIX_0 */
10538     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10539   },
10540   {
10541     /* MOD_62_32BIT */
10542     { "bound{S|}",      { Gv, Ma }, 0 },
10543     { EVEX_TABLE (EVEX_0F) },
10544   },
10545   {
10546     /* MOD_C4_32BIT */
10547     { "lesS",           { Gv, Mp }, 0 },
10548     { VEX_C4_TABLE (VEX_0F) },
10549   },
10550   {
10551     /* MOD_C5_32BIT */
10552     { "ldsS",           { Gv, Mp }, 0 },
10553     { VEX_C5_TABLE (VEX_0F) },
10554   },
10555   {
10556     /* MOD_VEX_0F12_PREFIX_0 */
10557     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10558     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10559   },
10560   {
10561     /* MOD_VEX_0F13 */
10562     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10563   },
10564   {
10565     /* MOD_VEX_0F16_PREFIX_0 */
10566     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10567     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10568   },
10569   {
10570     /* MOD_VEX_0F17 */
10571     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10572   },
10573   {
10574     /* MOD_VEX_0F2B */
10575     { "vmovntpX",       { Mx, XM }, 0 },
10576   },
10577   {
10578     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10579     { Bad_Opcode },
10580     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10581   },
10582   {
10583     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10584     { Bad_Opcode },
10585     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10586   },
10587   {
10588     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10589     { Bad_Opcode },
10590     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10591   },
10592   {
10593     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10594     { Bad_Opcode },
10595     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10596   },
10597   {
10598     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10599     { Bad_Opcode },
10600     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10601   },
10602   {
10603     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10604     { Bad_Opcode },
10605     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10606   },
10607   {
10608     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10609     { Bad_Opcode },
10610     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10611   },
10612   {
10613     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10614     { Bad_Opcode },
10615     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10616   },
10617   {
10618     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10619     { Bad_Opcode },
10620     { "knotw",          { MaskG, MaskR }, 0 },
10621   },
10622   {
10623     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10624     { Bad_Opcode },
10625     { "knotq",          { MaskG, MaskR }, 0 },
10626   },
10627   {
10628     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10629     { Bad_Opcode },
10630     { "knotb",          { MaskG, MaskR }, 0 },
10631   },
10632   {
10633     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10634     { Bad_Opcode },
10635     { "knotd",          { MaskG, MaskR }, 0 },
10636   },
10637   {
10638     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10639     { Bad_Opcode },
10640     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10641   },
10642   {
10643     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10644     { Bad_Opcode },
10645     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10646   },
10647   {
10648     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10649     { Bad_Opcode },
10650     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10651   },
10652   {
10653     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10654     { Bad_Opcode },
10655     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10656   },
10657  {
10658     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10659     { Bad_Opcode },
10660     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10661   },
10662   {
10663     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10664     { Bad_Opcode },
10665     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10666   },
10667   {
10668     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10669     { Bad_Opcode },
10670     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10671   },
10672   {
10673     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10674     { Bad_Opcode },
10675     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10676   },
10677   {
10678     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10679     { Bad_Opcode },
10680     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10681   },
10682   {
10683     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10684     { Bad_Opcode },
10685     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10686   },
10687   {
10688     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10689     { Bad_Opcode },
10690     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10691   },
10692   {
10693     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10694     { Bad_Opcode },
10695     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10696   },
10697   {
10698     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10699     { Bad_Opcode },
10700     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10701   },
10702   {
10703     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10704     { Bad_Opcode },
10705     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10706   },
10707   {
10708     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10709     { Bad_Opcode },
10710     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10711   },
10712   {
10713     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10714     { Bad_Opcode },
10715     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10716   },
10717   {
10718     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10719     { Bad_Opcode },
10720     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10721   },
10722   {
10723     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10724     { Bad_Opcode },
10725     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10726   },
10727   {
10728     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10729     { Bad_Opcode },
10730     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10731   },
10732   {
10733     /* MOD_VEX_0F50 */
10734     { Bad_Opcode },
10735     { "vmovmskpX",      { Gdq, XS }, 0 },
10736   },
10737   {
10738     /* MOD_VEX_0F71_REG_2 */
10739     { Bad_Opcode },
10740     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10741   },
10742   {
10743     /* MOD_VEX_0F71_REG_4 */
10744     { Bad_Opcode },
10745     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10746   },
10747   {
10748     /* MOD_VEX_0F71_REG_6 */
10749     { Bad_Opcode },
10750     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10751   },
10752   {
10753     /* MOD_VEX_0F72_REG_2 */
10754     { Bad_Opcode },
10755     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10756   },
10757   {
10758     /* MOD_VEX_0F72_REG_4 */
10759     { Bad_Opcode },
10760     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10761   },
10762   {
10763     /* MOD_VEX_0F72_REG_6 */
10764     { Bad_Opcode },
10765     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10766   },
10767   {
10768     /* MOD_VEX_0F73_REG_2 */
10769     { Bad_Opcode },
10770     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10771   },
10772   {
10773     /* MOD_VEX_0F73_REG_3 */
10774     { Bad_Opcode },
10775     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10776   },
10777   {
10778     /* MOD_VEX_0F73_REG_6 */
10779     { Bad_Opcode },
10780     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10781   },
10782   {
10783     /* MOD_VEX_0F73_REG_7 */
10784     { Bad_Opcode },
10785     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10786   },
10787   {
10788     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10789     { "kmovw",          { Ew, MaskG }, 0 },
10790     { Bad_Opcode },
10791   },
10792   {
10793     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10794     { "kmovq",          { Eq, MaskG }, 0 },
10795     { Bad_Opcode },
10796   },
10797   {
10798     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10799     { "kmovb",          { Eb, MaskG }, 0 },
10800     { Bad_Opcode },
10801   },
10802   {
10803     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10804     { "kmovd",          { Ed, MaskG }, 0 },
10805     { Bad_Opcode },
10806   },
10807   {
10808     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10809     { Bad_Opcode },
10810     { "kmovw",          { MaskG, Rdq }, 0 },
10811   },
10812   {
10813     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10814     { Bad_Opcode },
10815     { "kmovb",          { MaskG, Rdq }, 0 },
10816   },
10817   {
10818     /* MOD_VEX_0F92_P_3_LEN_0 */
10819     { Bad_Opcode },
10820     { "kmovK",          { MaskG, Rdq }, 0 },
10821   },
10822   {
10823     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10824     { Bad_Opcode },
10825     { "kmovw",          { Gdq, MaskR }, 0 },
10826   },
10827   {
10828     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10829     { Bad_Opcode },
10830     { "kmovb",          { Gdq, MaskR }, 0 },
10831   },
10832   {
10833     /* MOD_VEX_0F93_P_3_LEN_0 */
10834     { Bad_Opcode },
10835     { "kmovK",          { Gdq, MaskR }, 0 },
10836   },
10837   {
10838     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10839     { Bad_Opcode },
10840     { "kortestw", { MaskG, MaskR }, 0 },
10841   },
10842   {
10843     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10844     { Bad_Opcode },
10845     { "kortestq", { MaskG, MaskR }, 0 },
10846   },
10847   {
10848     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10849     { Bad_Opcode },
10850     { "kortestb", { MaskG, MaskR }, 0 },
10851   },
10852   {
10853     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10854     { Bad_Opcode },
10855     { "kortestd", { MaskG, MaskR }, 0 },
10856   },
10857   {
10858     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10859     { Bad_Opcode },
10860     { "ktestw", { MaskG, MaskR }, 0 },
10861   },
10862   {
10863     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10864     { Bad_Opcode },
10865     { "ktestq", { MaskG, MaskR }, 0 },
10866   },
10867   {
10868     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10869     { Bad_Opcode },
10870     { "ktestb", { MaskG, MaskR }, 0 },
10871   },
10872   {
10873     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10874     { Bad_Opcode },
10875     { "ktestd", { MaskG, MaskR }, 0 },
10876   },
10877   {
10878     /* MOD_VEX_0FAE_REG_2 */
10879     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10880   },
10881   {
10882     /* MOD_VEX_0FAE_REG_3 */
10883     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10884   },
10885   {
10886     /* MOD_VEX_0FD7_PREFIX_2 */
10887     { Bad_Opcode },
10888     { "vpmovmskb",      { Gdq, XS }, 0 },
10889   },
10890   {
10891     /* MOD_VEX_0FE7_PREFIX_2 */
10892     { "vmovntdq",       { Mx, XM }, 0 },
10893   },
10894   {
10895     /* MOD_VEX_0FF0_PREFIX_3 */
10896     { "vlddqu",         { XM, M }, 0 },
10897   },
10898   {
10899     /* MOD_VEX_0F381A_PREFIX_2 */
10900     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10901   },
10902   {
10903     /* MOD_VEX_0F382A_PREFIX_2 */
10904     { "vmovntdqa",      { XM, Mx }, 0 },
10905   },
10906   {
10907     /* MOD_VEX_0F382C_PREFIX_2 */
10908     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10909   },
10910   {
10911     /* MOD_VEX_0F382D_PREFIX_2 */
10912     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10913   },
10914   {
10915     /* MOD_VEX_0F382E_PREFIX_2 */
10916     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10917   },
10918   {
10919     /* MOD_VEX_0F382F_PREFIX_2 */
10920     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10921   },
10922   {
10923     /* MOD_VEX_0F385A_PREFIX_2 */
10924     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10925   },
10926   {
10927     /* MOD_VEX_0F388C_PREFIX_2 */
10928     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10929   },
10930   {
10931     /* MOD_VEX_0F388E_PREFIX_2 */
10932     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10933   },
10934   {
10935     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10936     { Bad_Opcode },
10937     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10938   },
10939   {
10940     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10941     { Bad_Opcode },
10942     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10943   },
10944   {
10945     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10946     { Bad_Opcode },
10947     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10948   },
10949   {
10950     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10951     { Bad_Opcode },
10952     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10953   },
10954   {
10955     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10956     { Bad_Opcode },
10957     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10958   },
10959   {
10960     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10961     { Bad_Opcode },
10962     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10963   },
10964   {
10965     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10966     { Bad_Opcode },
10967     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10968   },
10969   {
10970     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10971     { Bad_Opcode },
10972     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10973   },
10974
10975 #include "i386-dis-evex-mod.h"
10976 };
10977
10978 static const struct dis386 rm_table[][8] = {
10979   {
10980     /* RM_C6_REG_7 */
10981     { "xabort",         { Skip_MODRM, Ib }, 0 },
10982   },
10983   {
10984     /* RM_C7_REG_7 */
10985     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10986   },
10987   {
10988     /* RM_0F01_REG_0 */
10989     { "enclv",          { Skip_MODRM }, 0 },
10990     { "vmcall",         { Skip_MODRM }, 0 },
10991     { "vmlaunch",       { Skip_MODRM }, 0 },
10992     { "vmresume",       { Skip_MODRM }, 0 },
10993     { "vmxoff",         { Skip_MODRM }, 0 },
10994     { "pconfig",        { Skip_MODRM }, 0 },
10995   },
10996   {
10997     /* RM_0F01_REG_1 */
10998     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10999     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11000     { "clac",           { Skip_MODRM }, 0 },
11001     { "stac",           { Skip_MODRM }, 0 },
11002     { Bad_Opcode },
11003     { Bad_Opcode },
11004     { Bad_Opcode },
11005     { "encls",          { Skip_MODRM }, 0 },
11006   },
11007   {
11008     /* RM_0F01_REG_2 */
11009     { "xgetbv",         { Skip_MODRM }, 0 },
11010     { "xsetbv",         { Skip_MODRM }, 0 },
11011     { Bad_Opcode },
11012     { Bad_Opcode },
11013     { "vmfunc",         { Skip_MODRM }, 0 },
11014     { "xend",           { Skip_MODRM }, 0 },
11015     { "xtest",          { Skip_MODRM }, 0 },
11016     { "enclu",          { Skip_MODRM }, 0 },
11017   },
11018   {
11019     /* RM_0F01_REG_3 */
11020     { "vmrun",          { Skip_MODRM }, 0 },
11021     { "vmmcall",        { Skip_MODRM }, 0 },
11022     { "vmload",         { Skip_MODRM }, 0 },
11023     { "vmsave",         { Skip_MODRM }, 0 },
11024     { "stgi",           { Skip_MODRM }, 0 },
11025     { "clgi",           { Skip_MODRM }, 0 },
11026     { "skinit",         { Skip_MODRM }, 0 },
11027     { "invlpga",        { Skip_MODRM }, 0 },
11028   },
11029   {
11030     /* RM_0F01_REG_5_MOD_3 */
11031     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11032     { Bad_Opcode },
11033     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11034     { Bad_Opcode },
11035     { Bad_Opcode },
11036     { Bad_Opcode },
11037     { "rdpkru",         { Skip_MODRM }, 0 },
11038     { "wrpkru",         { Skip_MODRM }, 0 },
11039   },
11040   {
11041     /* RM_0F01_REG_7_MOD_3 */
11042     { "swapgs",         { Skip_MODRM }, 0  },
11043     { "rdtscp",         { Skip_MODRM }, 0  },
11044     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11045     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11046     { "clzero",         { Skip_MODRM }, 0  },
11047     { "rdpru",          { Skip_MODRM }, 0  },
11048   },
11049   {
11050     /* RM_0F1E_P_1_MOD_3_REG_7 */
11051     { "nopQ",           { Ev }, 0 },
11052     { "nopQ",           { Ev }, 0 },
11053     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11054     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11055     { "nopQ",           { Ev }, 0 },
11056     { "nopQ",           { Ev }, 0 },
11057     { "nopQ",           { Ev }, 0 },
11058     { "nopQ",           { Ev }, 0 },
11059   },
11060   {
11061     /* RM_0FAE_REG_6_MOD_3 */
11062     { "mfence",         { Skip_MODRM }, 0 },
11063   },
11064   {
11065     /* RM_0FAE_REG_7_MOD_3 */
11066     { "sfence",         { Skip_MODRM }, 0 },
11067
11068   },
11069 };
11070
11071 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11072
11073 /* We use the high bit to indicate different name for the same
11074    prefix.  */
11075 #define REP_PREFIX      (0xf3 | 0x100)
11076 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11077 #define XRELEASE_PREFIX (0xf3 | 0x400)
11078 #define BND_PREFIX      (0xf2 | 0x400)
11079 #define NOTRACK_PREFIX  (0x3e | 0x100)
11080
11081 /* Remember if the current op is a jump instruction.  */
11082 static bfd_boolean op_is_jump = FALSE;
11083
11084 static int
11085 ckprefix (void)
11086 {
11087   int newrex, i, length;
11088   rex = 0;
11089   rex_ignored = 0;
11090   prefixes = 0;
11091   used_prefixes = 0;
11092   rex_used = 0;
11093   last_lock_prefix = -1;
11094   last_repz_prefix = -1;
11095   last_repnz_prefix = -1;
11096   last_data_prefix = -1;
11097   last_addr_prefix = -1;
11098   last_rex_prefix = -1;
11099   last_seg_prefix = -1;
11100   fwait_prefix = -1;
11101   active_seg_prefix = 0;
11102   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11103     all_prefixes[i] = 0;
11104   i = 0;
11105   length = 0;
11106   /* The maximum instruction length is 15bytes.  */
11107   while (length < MAX_CODE_LENGTH - 1)
11108     {
11109       FETCH_DATA (the_info, codep + 1);
11110       newrex = 0;
11111       switch (*codep)
11112         {
11113         /* REX prefixes family.  */
11114         case 0x40:
11115         case 0x41:
11116         case 0x42:
11117         case 0x43:
11118         case 0x44:
11119         case 0x45:
11120         case 0x46:
11121         case 0x47:
11122         case 0x48:
11123         case 0x49:
11124         case 0x4a:
11125         case 0x4b:
11126         case 0x4c:
11127         case 0x4d:
11128         case 0x4e:
11129         case 0x4f:
11130           if (address_mode == mode_64bit)
11131             newrex = *codep;
11132           else
11133             return 1;
11134           last_rex_prefix = i;
11135           break;
11136         case 0xf3:
11137           prefixes |= PREFIX_REPZ;
11138           last_repz_prefix = i;
11139           break;
11140         case 0xf2:
11141           prefixes |= PREFIX_REPNZ;
11142           last_repnz_prefix = i;
11143           break;
11144         case 0xf0:
11145           prefixes |= PREFIX_LOCK;
11146           last_lock_prefix = i;
11147           break;
11148         case 0x2e:
11149           prefixes |= PREFIX_CS;
11150           last_seg_prefix = i;
11151           active_seg_prefix = PREFIX_CS;
11152           break;
11153         case 0x36:
11154           prefixes |= PREFIX_SS;
11155           last_seg_prefix = i;
11156           active_seg_prefix = PREFIX_SS;
11157           break;
11158         case 0x3e:
11159           prefixes |= PREFIX_DS;
11160           last_seg_prefix = i;
11161           active_seg_prefix = PREFIX_DS;
11162           break;
11163         case 0x26:
11164           prefixes |= PREFIX_ES;
11165           last_seg_prefix = i;
11166           active_seg_prefix = PREFIX_ES;
11167           break;
11168         case 0x64:
11169           prefixes |= PREFIX_FS;
11170           last_seg_prefix = i;
11171           active_seg_prefix = PREFIX_FS;
11172           break;
11173         case 0x65:
11174           prefixes |= PREFIX_GS;
11175           last_seg_prefix = i;
11176           active_seg_prefix = PREFIX_GS;
11177           break;
11178         case 0x66:
11179           prefixes |= PREFIX_DATA;
11180           last_data_prefix = i;
11181           break;
11182         case 0x67:
11183           prefixes |= PREFIX_ADDR;
11184           last_addr_prefix = i;
11185           break;
11186         case FWAIT_OPCODE:
11187           /* fwait is really an instruction.  If there are prefixes
11188              before the fwait, they belong to the fwait, *not* to the
11189              following instruction.  */
11190           fwait_prefix = i;
11191           if (prefixes || rex)
11192             {
11193               prefixes |= PREFIX_FWAIT;
11194               codep++;
11195               /* This ensures that the previous REX prefixes are noticed
11196                  as unused prefixes, as in the return case below.  */
11197               rex_used = rex;
11198               return 1;
11199             }
11200           prefixes = PREFIX_FWAIT;
11201           break;
11202         default:
11203           return 1;
11204         }
11205       /* Rex is ignored when followed by another prefix.  */
11206       if (rex)
11207         {
11208           rex_used = rex;
11209           return 1;
11210         }
11211       if (*codep != FWAIT_OPCODE)
11212         all_prefixes[i++] = *codep;
11213       rex = newrex;
11214       codep++;
11215       length++;
11216     }
11217   return 0;
11218 }
11219
11220 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11221    prefix byte.  */
11222
11223 static const char *
11224 prefix_name (int pref, int sizeflag)
11225 {
11226   static const char *rexes [16] =
11227     {
11228       "rex",            /* 0x40 */
11229       "rex.B",          /* 0x41 */
11230       "rex.X",          /* 0x42 */
11231       "rex.XB",         /* 0x43 */
11232       "rex.R",          /* 0x44 */
11233       "rex.RB",         /* 0x45 */
11234       "rex.RX",         /* 0x46 */
11235       "rex.RXB",        /* 0x47 */
11236       "rex.W",          /* 0x48 */
11237       "rex.WB",         /* 0x49 */
11238       "rex.WX",         /* 0x4a */
11239       "rex.WXB",        /* 0x4b */
11240       "rex.WR",         /* 0x4c */
11241       "rex.WRB",        /* 0x4d */
11242       "rex.WRX",        /* 0x4e */
11243       "rex.WRXB",       /* 0x4f */
11244     };
11245
11246   switch (pref)
11247     {
11248     /* REX prefixes family.  */
11249     case 0x40:
11250     case 0x41:
11251     case 0x42:
11252     case 0x43:
11253     case 0x44:
11254     case 0x45:
11255     case 0x46:
11256     case 0x47:
11257     case 0x48:
11258     case 0x49:
11259     case 0x4a:
11260     case 0x4b:
11261     case 0x4c:
11262     case 0x4d:
11263     case 0x4e:
11264     case 0x4f:
11265       return rexes [pref - 0x40];
11266     case 0xf3:
11267       return "repz";
11268     case 0xf2:
11269       return "repnz";
11270     case 0xf0:
11271       return "lock";
11272     case 0x2e:
11273       return "cs";
11274     case 0x36:
11275       return "ss";
11276     case 0x3e:
11277       return "ds";
11278     case 0x26:
11279       return "es";
11280     case 0x64:
11281       return "fs";
11282     case 0x65:
11283       return "gs";
11284     case 0x66:
11285       return (sizeflag & DFLAG) ? "data16" : "data32";
11286     case 0x67:
11287       if (address_mode == mode_64bit)
11288         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11289       else
11290         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11291     case FWAIT_OPCODE:
11292       return "fwait";
11293     case REP_PREFIX:
11294       return "rep";
11295     case XACQUIRE_PREFIX:
11296       return "xacquire";
11297     case XRELEASE_PREFIX:
11298       return "xrelease";
11299     case BND_PREFIX:
11300       return "bnd";
11301     case NOTRACK_PREFIX:
11302       return "notrack";
11303     default:
11304       return NULL;
11305     }
11306 }
11307
11308 static char op_out[MAX_OPERANDS][100];
11309 static int op_ad, op_index[MAX_OPERANDS];
11310 static int two_source_ops;
11311 static bfd_vma op_address[MAX_OPERANDS];
11312 static bfd_vma op_riprel[MAX_OPERANDS];
11313 static bfd_vma start_pc;
11314
11315 /*
11316  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11317  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11318  *   section of the "Virtual 8086 Mode" chapter.)
11319  * 'pc' should be the address of this instruction, it will
11320  *   be used to print the target address if this is a relative jump or call
11321  * The function returns the length of this instruction in bytes.
11322  */
11323
11324 static char intel_syntax;
11325 static char intel_mnemonic = !SYSV386_COMPAT;
11326 static char open_char;
11327 static char close_char;
11328 static char separator_char;
11329 static char scale_char;
11330
11331 enum x86_64_isa
11332 {
11333   amd64 = 1,
11334   intel64
11335 };
11336
11337 static enum x86_64_isa isa64;
11338
11339 /* Here for backwards compatibility.  When gdb stops using
11340    print_insn_i386_att and print_insn_i386_intel these functions can
11341    disappear, and print_insn_i386 be merged into print_insn.  */
11342 int
11343 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11344 {
11345   intel_syntax = 0;
11346
11347   return print_insn (pc, info);
11348 }
11349
11350 int
11351 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11352 {
11353   intel_syntax = 1;
11354
11355   return print_insn (pc, info);
11356 }
11357
11358 int
11359 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11360 {
11361   intel_syntax = -1;
11362
11363   return print_insn (pc, info);
11364 }
11365
11366 void
11367 print_i386_disassembler_options (FILE *stream)
11368 {
11369   fprintf (stream, _("\n\
11370 The following i386/x86-64 specific disassembler options are supported for use\n\
11371 with the -M switch (multiple options should be separated by commas):\n"));
11372
11373   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11374   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11375   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11376   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11377   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11378   fprintf (stream, _("  att-mnemonic\n"
11379                      "              Display instruction in AT&T mnemonic\n"));
11380   fprintf (stream, _("  intel-mnemonic\n"
11381                      "              Display instruction in Intel mnemonic\n"));
11382   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11383   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11384   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11385   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11386   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11387   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11388   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11389   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11390 }
11391
11392 /* Bad opcode.  */
11393 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11394
11395 /* Get a pointer to struct dis386 with a valid name.  */
11396
11397 static const struct dis386 *
11398 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11399 {
11400   int vindex, vex_table_index;
11401
11402   if (dp->name != NULL)
11403     return dp;
11404
11405   switch (dp->op[0].bytemode)
11406     {
11407     case USE_REG_TABLE:
11408       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11409       break;
11410
11411     case USE_MOD_TABLE:
11412       vindex = modrm.mod == 0x3 ? 1 : 0;
11413       dp = &mod_table[dp->op[1].bytemode][vindex];
11414       break;
11415
11416     case USE_RM_TABLE:
11417       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11418       break;
11419
11420     case USE_PREFIX_TABLE:
11421       if (need_vex)
11422         {
11423           /* The prefix in VEX is implicit.  */
11424           switch (vex.prefix)
11425             {
11426             case 0:
11427               vindex = 0;
11428               break;
11429             case REPE_PREFIX_OPCODE:
11430               vindex = 1;
11431               break;
11432             case DATA_PREFIX_OPCODE:
11433               vindex = 2;
11434               break;
11435             case REPNE_PREFIX_OPCODE:
11436               vindex = 3;
11437               break;
11438             default:
11439               abort ();
11440               break;
11441             }
11442         }
11443       else
11444         {
11445           int last_prefix = -1;
11446           int prefix = 0;
11447           vindex = 0;
11448           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11449              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11450              last one wins.  */
11451           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11452             {
11453               if (last_repz_prefix > last_repnz_prefix)
11454                 {
11455                   vindex = 1;
11456                   prefix = PREFIX_REPZ;
11457                   last_prefix = last_repz_prefix;
11458                 }
11459               else
11460                 {
11461                   vindex = 3;
11462                   prefix = PREFIX_REPNZ;
11463                   last_prefix = last_repnz_prefix;
11464                 }
11465
11466               /* Check if prefix should be ignored.  */
11467               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11468                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11469                    & prefix) != 0)
11470                 vindex = 0;
11471             }
11472
11473           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11474             {
11475               vindex = 2;
11476               prefix = PREFIX_DATA;
11477               last_prefix = last_data_prefix;
11478             }
11479
11480           if (vindex != 0)
11481             {
11482               used_prefixes |= prefix;
11483               all_prefixes[last_prefix] = 0;
11484             }
11485         }
11486       dp = &prefix_table[dp->op[1].bytemode][vindex];
11487       break;
11488
11489     case USE_X86_64_TABLE:
11490       vindex = address_mode == mode_64bit ? 1 : 0;
11491       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11492       break;
11493
11494     case USE_3BYTE_TABLE:
11495       FETCH_DATA (info, codep + 2);
11496       vindex = *codep++;
11497       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11498       end_codep = codep;
11499       modrm.mod = (*codep >> 6) & 3;
11500       modrm.reg = (*codep >> 3) & 7;
11501       modrm.rm = *codep & 7;
11502       break;
11503
11504     case USE_VEX_LEN_TABLE:
11505       if (!need_vex)
11506         abort ();
11507
11508       switch (vex.length)
11509         {
11510         case 128:
11511           vindex = 0;
11512           break;
11513         case 256:
11514           vindex = 1;
11515           break;
11516         default:
11517           abort ();
11518           break;
11519         }
11520
11521       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11522       break;
11523
11524     case USE_EVEX_LEN_TABLE:
11525       if (!vex.evex)
11526         abort ();
11527
11528       switch (vex.length)
11529         {
11530         case 128:
11531           vindex = 0;
11532           break;
11533         case 256:
11534           vindex = 1;
11535           break;
11536         case 512:
11537           vindex = 2;
11538           break;
11539         default:
11540           abort ();
11541           break;
11542         }
11543
11544       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11545       break;
11546
11547     case USE_XOP_8F_TABLE:
11548       FETCH_DATA (info, codep + 3);
11549       /* All bits in the REX prefix are ignored.  */
11550       rex_ignored = rex;
11551       rex = ~(*codep >> 5) & 0x7;
11552
11553       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11554       switch ((*codep & 0x1f))
11555         {
11556         default:
11557           dp = &bad_opcode;
11558           return dp;
11559         case 0x8:
11560           vex_table_index = XOP_08;
11561           break;
11562         case 0x9:
11563           vex_table_index = XOP_09;
11564           break;
11565         case 0xa:
11566           vex_table_index = XOP_0A;
11567           break;
11568         }
11569       codep++;
11570       vex.w = *codep & 0x80;
11571       if (vex.w && address_mode == mode_64bit)
11572         rex |= REX_W;
11573
11574       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11575       if (address_mode != mode_64bit)
11576         {
11577           /* In 16/32-bit mode REX_B is silently ignored.  */
11578           rex &= ~REX_B;
11579         }
11580
11581       vex.length = (*codep & 0x4) ? 256 : 128;
11582       switch ((*codep & 0x3))
11583         {
11584         case 0:
11585           break;
11586         case 1:
11587           vex.prefix = DATA_PREFIX_OPCODE;
11588           break;
11589         case 2:
11590           vex.prefix = REPE_PREFIX_OPCODE;
11591           break;
11592         case 3:
11593           vex.prefix = REPNE_PREFIX_OPCODE;
11594           break;
11595         }
11596       need_vex = 1;
11597       need_vex_reg = 1;
11598       codep++;
11599       vindex = *codep++;
11600       dp = &xop_table[vex_table_index][vindex];
11601
11602       end_codep = codep;
11603       FETCH_DATA (info, codep + 1);
11604       modrm.mod = (*codep >> 6) & 3;
11605       modrm.reg = (*codep >> 3) & 7;
11606       modrm.rm = *codep & 7;
11607       break;
11608
11609     case USE_VEX_C4_TABLE:
11610       /* VEX prefix.  */
11611       FETCH_DATA (info, codep + 3);
11612       /* All bits in the REX prefix are ignored.  */
11613       rex_ignored = rex;
11614       rex = ~(*codep >> 5) & 0x7;
11615       switch ((*codep & 0x1f))
11616         {
11617         default:
11618           dp = &bad_opcode;
11619           return dp;
11620         case 0x1:
11621           vex_table_index = VEX_0F;
11622           break;
11623         case 0x2:
11624           vex_table_index = VEX_0F38;
11625           break;
11626         case 0x3:
11627           vex_table_index = VEX_0F3A;
11628           break;
11629         }
11630       codep++;
11631       vex.w = *codep & 0x80;
11632       if (address_mode == mode_64bit)
11633         {
11634           if (vex.w)
11635             rex |= REX_W;
11636         }
11637       else
11638         {
11639           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11640              is ignored, other REX bits are 0 and the highest bit in
11641              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11642           rex = 0;
11643         }
11644       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11645       vex.length = (*codep & 0x4) ? 256 : 128;
11646       switch ((*codep & 0x3))
11647         {
11648         case 0:
11649           break;
11650         case 1:
11651           vex.prefix = DATA_PREFIX_OPCODE;
11652           break;
11653         case 2:
11654           vex.prefix = REPE_PREFIX_OPCODE;
11655           break;
11656         case 3:
11657           vex.prefix = REPNE_PREFIX_OPCODE;
11658           break;
11659         }
11660       need_vex = 1;
11661       need_vex_reg = 1;
11662       codep++;
11663       vindex = *codep++;
11664       dp = &vex_table[vex_table_index][vindex];
11665       end_codep = codep;
11666       /* There is no MODRM byte for VEX0F 77.  */
11667       if (vex_table_index != VEX_0F || vindex != 0x77)
11668         {
11669           FETCH_DATA (info, codep + 1);
11670           modrm.mod = (*codep >> 6) & 3;
11671           modrm.reg = (*codep >> 3) & 7;
11672           modrm.rm = *codep & 7;
11673         }
11674       break;
11675
11676     case USE_VEX_C5_TABLE:
11677       /* VEX prefix.  */
11678       FETCH_DATA (info, codep + 2);
11679       /* All bits in the REX prefix are ignored.  */
11680       rex_ignored = rex;
11681       rex = (*codep & 0x80) ? 0 : REX_R;
11682
11683       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11684          VEX.vvvv is 1.  */
11685       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11686       vex.length = (*codep & 0x4) ? 256 : 128;
11687       switch ((*codep & 0x3))
11688         {
11689         case 0:
11690           break;
11691         case 1:
11692           vex.prefix = DATA_PREFIX_OPCODE;
11693           break;
11694         case 2:
11695           vex.prefix = REPE_PREFIX_OPCODE;
11696           break;
11697         case 3:
11698           vex.prefix = REPNE_PREFIX_OPCODE;
11699           break;
11700         }
11701       need_vex = 1;
11702       need_vex_reg = 1;
11703       codep++;
11704       vindex = *codep++;
11705       dp = &vex_table[dp->op[1].bytemode][vindex];
11706       end_codep = codep;
11707       /* There is no MODRM byte for VEX 77.  */
11708       if (vindex != 0x77)
11709         {
11710           FETCH_DATA (info, codep + 1);
11711           modrm.mod = (*codep >> 6) & 3;
11712           modrm.reg = (*codep >> 3) & 7;
11713           modrm.rm = *codep & 7;
11714         }
11715       break;
11716
11717     case USE_VEX_W_TABLE:
11718       if (!need_vex)
11719         abort ();
11720
11721       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11722       break;
11723
11724     case USE_EVEX_TABLE:
11725       two_source_ops = 0;
11726       /* EVEX prefix.  */
11727       vex.evex = 1;
11728       FETCH_DATA (info, codep + 4);
11729       /* All bits in the REX prefix are ignored.  */
11730       rex_ignored = rex;
11731       /* The first byte after 0x62.  */
11732       rex = ~(*codep >> 5) & 0x7;
11733       vex.r = *codep & 0x10;
11734       switch ((*codep & 0xf))
11735         {
11736         default:
11737           return &bad_opcode;
11738         case 0x1:
11739           vex_table_index = EVEX_0F;
11740           break;
11741         case 0x2:
11742           vex_table_index = EVEX_0F38;
11743           break;
11744         case 0x3:
11745           vex_table_index = EVEX_0F3A;
11746           break;
11747         }
11748
11749       /* The second byte after 0x62.  */
11750       codep++;
11751       vex.w = *codep & 0x80;
11752       if (vex.w && address_mode == mode_64bit)
11753         rex |= REX_W;
11754
11755       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11756
11757       /* The U bit.  */
11758       if (!(*codep & 0x4))
11759         return &bad_opcode;
11760
11761       switch ((*codep & 0x3))
11762         {
11763         case 0:
11764           break;
11765         case 1:
11766           vex.prefix = DATA_PREFIX_OPCODE;
11767           break;
11768         case 2:
11769           vex.prefix = REPE_PREFIX_OPCODE;
11770           break;
11771         case 3:
11772           vex.prefix = REPNE_PREFIX_OPCODE;
11773           break;
11774         }
11775
11776       /* The third byte after 0x62.  */
11777       codep++;
11778
11779       /* Remember the static rounding bits.  */
11780       vex.ll = (*codep >> 5) & 3;
11781       vex.b = (*codep & 0x10) != 0;
11782
11783       vex.v = *codep & 0x8;
11784       vex.mask_register_specifier = *codep & 0x7;
11785       vex.zeroing = *codep & 0x80;
11786
11787       if (address_mode != mode_64bit)
11788         {
11789           /* In 16/32-bit mode silently ignore following bits.  */
11790           rex &= ~REX_B;
11791           vex.r = 1;
11792           vex.v = 1;
11793         }
11794
11795       need_vex = 1;
11796       need_vex_reg = 1;
11797       codep++;
11798       vindex = *codep++;
11799       dp = &evex_table[vex_table_index][vindex];
11800       end_codep = codep;
11801       FETCH_DATA (info, codep + 1);
11802       modrm.mod = (*codep >> 6) & 3;
11803       modrm.reg = (*codep >> 3) & 7;
11804       modrm.rm = *codep & 7;
11805
11806       /* Set vector length.  */
11807       if (modrm.mod == 3 && vex.b)
11808         vex.length = 512;
11809       else
11810         {
11811           switch (vex.ll)
11812             {
11813             case 0x0:
11814               vex.length = 128;
11815               break;
11816             case 0x1:
11817               vex.length = 256;
11818               break;
11819             case 0x2:
11820               vex.length = 512;
11821               break;
11822             default:
11823               return &bad_opcode;
11824             }
11825         }
11826       break;
11827
11828     case 0:
11829       dp = &bad_opcode;
11830       break;
11831
11832     default:
11833       abort ();
11834     }
11835
11836   if (dp->name != NULL)
11837     return dp;
11838   else
11839     return get_valid_dis386 (dp, info);
11840 }
11841
11842 static void
11843 get_sib (disassemble_info *info, int sizeflag)
11844 {
11845   /* If modrm.mod == 3, operand must be register.  */
11846   if (need_modrm
11847       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11848       && modrm.mod != 3
11849       && modrm.rm == 4)
11850     {
11851       FETCH_DATA (info, codep + 2);
11852       sib.index = (codep [1] >> 3) & 7;
11853       sib.scale = (codep [1] >> 6) & 3;
11854       sib.base = codep [1] & 7;
11855     }
11856 }
11857
11858 static int
11859 print_insn (bfd_vma pc, disassemble_info *info)
11860 {
11861   const struct dis386 *dp;
11862   int i;
11863   char *op_txt[MAX_OPERANDS];
11864   int needcomma;
11865   int sizeflag, orig_sizeflag;
11866   const char *p;
11867   struct dis_private priv;
11868   int prefix_length;
11869
11870   priv.orig_sizeflag = AFLAG | DFLAG;
11871   if ((info->mach & bfd_mach_i386_i386) != 0)
11872     address_mode = mode_32bit;
11873   else if (info->mach == bfd_mach_i386_i8086)
11874     {
11875       address_mode = mode_16bit;
11876       priv.orig_sizeflag = 0;
11877     }
11878   else
11879     address_mode = mode_64bit;
11880
11881   if (intel_syntax == (char) -1)
11882     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11883
11884   for (p = info->disassembler_options; p != NULL; )
11885     {
11886       if (CONST_STRNEQ (p, "amd64"))
11887         isa64 = amd64;
11888       else if (CONST_STRNEQ (p, "intel64"))
11889         isa64 = intel64;
11890       else if (CONST_STRNEQ (p, "x86-64"))
11891         {
11892           address_mode = mode_64bit;
11893           priv.orig_sizeflag = AFLAG | DFLAG;
11894         }
11895       else if (CONST_STRNEQ (p, "i386"))
11896         {
11897           address_mode = mode_32bit;
11898           priv.orig_sizeflag = AFLAG | DFLAG;
11899         }
11900       else if (CONST_STRNEQ (p, "i8086"))
11901         {
11902           address_mode = mode_16bit;
11903           priv.orig_sizeflag = 0;
11904         }
11905       else if (CONST_STRNEQ (p, "intel"))
11906         {
11907           intel_syntax = 1;
11908           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11909             intel_mnemonic = 1;
11910         }
11911       else if (CONST_STRNEQ (p, "att"))
11912         {
11913           intel_syntax = 0;
11914           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11915             intel_mnemonic = 0;
11916         }
11917       else if (CONST_STRNEQ (p, "addr"))
11918         {
11919           if (address_mode == mode_64bit)
11920             {
11921               if (p[4] == '3' && p[5] == '2')
11922                 priv.orig_sizeflag &= ~AFLAG;
11923               else if (p[4] == '6' && p[5] == '4')
11924                 priv.orig_sizeflag |= AFLAG;
11925             }
11926           else
11927             {
11928               if (p[4] == '1' && p[5] == '6')
11929                 priv.orig_sizeflag &= ~AFLAG;
11930               else if (p[4] == '3' && p[5] == '2')
11931                 priv.orig_sizeflag |= AFLAG;
11932             }
11933         }
11934       else if (CONST_STRNEQ (p, "data"))
11935         {
11936           if (p[4] == '1' && p[5] == '6')
11937             priv.orig_sizeflag &= ~DFLAG;
11938           else if (p[4] == '3' && p[5] == '2')
11939             priv.orig_sizeflag |= DFLAG;
11940         }
11941       else if (CONST_STRNEQ (p, "suffix"))
11942         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11943
11944       p = strchr (p, ',');
11945       if (p != NULL)
11946         p++;
11947     }
11948
11949   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11950     {
11951       (*info->fprintf_func) (info->stream,
11952                              _("64-bit address is disabled"));
11953       return -1;
11954     }
11955
11956   if (intel_syntax)
11957     {
11958       names64 = intel_names64;
11959       names32 = intel_names32;
11960       names16 = intel_names16;
11961       names8 = intel_names8;
11962       names8rex = intel_names8rex;
11963       names_seg = intel_names_seg;
11964       names_mm = intel_names_mm;
11965       names_bnd = intel_names_bnd;
11966       names_xmm = intel_names_xmm;
11967       names_ymm = intel_names_ymm;
11968       names_zmm = intel_names_zmm;
11969       index64 = intel_index64;
11970       index32 = intel_index32;
11971       names_mask = intel_names_mask;
11972       index16 = intel_index16;
11973       open_char = '[';
11974       close_char = ']';
11975       separator_char = '+';
11976       scale_char = '*';
11977     }
11978   else
11979     {
11980       names64 = att_names64;
11981       names32 = att_names32;
11982       names16 = att_names16;
11983       names8 = att_names8;
11984       names8rex = att_names8rex;
11985       names_seg = att_names_seg;
11986       names_mm = att_names_mm;
11987       names_bnd = att_names_bnd;
11988       names_xmm = att_names_xmm;
11989       names_ymm = att_names_ymm;
11990       names_zmm = att_names_zmm;
11991       index64 = att_index64;
11992       index32 = att_index32;
11993       names_mask = att_names_mask;
11994       index16 = att_index16;
11995       open_char = '(';
11996       close_char =  ')';
11997       separator_char = ',';
11998       scale_char = ',';
11999     }
12000
12001   /* The output looks better if we put 7 bytes on a line, since that
12002      puts most long word instructions on a single line.  Use 8 bytes
12003      for Intel L1OM.  */
12004   if ((info->mach & bfd_mach_l1om) != 0)
12005     info->bytes_per_line = 8;
12006   else
12007     info->bytes_per_line = 7;
12008
12009   info->private_data = &priv;
12010   priv.max_fetched = priv.the_buffer;
12011   priv.insn_start = pc;
12012
12013   obuf[0] = 0;
12014   for (i = 0; i < MAX_OPERANDS; ++i)
12015     {
12016       op_out[i][0] = 0;
12017       op_index[i] = -1;
12018     }
12019
12020   the_info = info;
12021   start_pc = pc;
12022   start_codep = priv.the_buffer;
12023   codep = priv.the_buffer;
12024
12025   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12026     {
12027       const char *name;
12028
12029       /* Getting here means we tried for data but didn't get it.  That
12030          means we have an incomplete instruction of some sort.  Just
12031          print the first byte as a prefix or a .byte pseudo-op.  */
12032       if (codep > priv.the_buffer)
12033         {
12034           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12035           if (name != NULL)
12036             (*info->fprintf_func) (info->stream, "%s", name);
12037           else
12038             {
12039               /* Just print the first byte as a .byte instruction.  */
12040               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12041                                      (unsigned int) priv.the_buffer[0]);
12042             }
12043
12044           return 1;
12045         }
12046
12047       return -1;
12048     }
12049
12050   obufp = obuf;
12051   sizeflag = priv.orig_sizeflag;
12052
12053   if (!ckprefix () || rex_used)
12054     {
12055       /* Too many prefixes or unused REX prefixes.  */
12056       for (i = 0;
12057            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12058            i++)
12059         (*info->fprintf_func) (info->stream, "%s%s",
12060                                i == 0 ? "" : " ",
12061                                prefix_name (all_prefixes[i], sizeflag));
12062       return i;
12063     }
12064
12065   insn_codep = codep;
12066
12067   FETCH_DATA (info, codep + 1);
12068   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12069
12070   if (((prefixes & PREFIX_FWAIT)
12071        && ((*codep < 0xd8) || (*codep > 0xdf))))
12072     {
12073       /* Handle prefixes before fwait.  */
12074       for (i = 0; i < fwait_prefix && all_prefixes[i];
12075            i++)
12076         (*info->fprintf_func) (info->stream, "%s ",
12077                                prefix_name (all_prefixes[i], sizeflag));
12078       (*info->fprintf_func) (info->stream, "fwait");
12079       return i + 1;
12080     }
12081
12082   if (*codep == 0x0f)
12083     {
12084       unsigned char threebyte;
12085
12086       codep++;
12087       FETCH_DATA (info, codep + 1);
12088       threebyte = *codep;
12089       dp = &dis386_twobyte[threebyte];
12090       need_modrm = twobyte_has_modrm[*codep];
12091       codep++;
12092     }
12093   else
12094     {
12095       dp = &dis386[*codep];
12096       need_modrm = onebyte_has_modrm[*codep];
12097       codep++;
12098     }
12099
12100   /* Save sizeflag for printing the extra prefixes later before updating
12101      it for mnemonic and operand processing.  The prefix names depend
12102      only on the address mode.  */
12103   orig_sizeflag = sizeflag;
12104   if (prefixes & PREFIX_ADDR)
12105     sizeflag ^= AFLAG;
12106   if ((prefixes & PREFIX_DATA))
12107     sizeflag ^= DFLAG;
12108
12109   end_codep = codep;
12110   if (need_modrm)
12111     {
12112       FETCH_DATA (info, codep + 1);
12113       modrm.mod = (*codep >> 6) & 3;
12114       modrm.reg = (*codep >> 3) & 7;
12115       modrm.rm = *codep & 7;
12116     }
12117
12118   need_vex = 0;
12119   need_vex_reg = 0;
12120   vex_w_done = 0;
12121   memset (&vex, 0, sizeof (vex));
12122
12123   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12124     {
12125       get_sib (info, sizeflag);
12126       dofloat (sizeflag);
12127     }
12128   else
12129     {
12130       dp = get_valid_dis386 (dp, info);
12131       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12132         {
12133           get_sib (info, sizeflag);
12134           for (i = 0; i < MAX_OPERANDS; ++i)
12135             {
12136               obufp = op_out[i];
12137               op_ad = MAX_OPERANDS - 1 - i;
12138               if (dp->op[i].rtn)
12139                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12140               /* For EVEX instruction after the last operand masking
12141                  should be printed.  */
12142               if (i == 0 && vex.evex)
12143                 {
12144                   /* Don't print {%k0}.  */
12145                   if (vex.mask_register_specifier)
12146                     {
12147                       oappend ("{");
12148                       oappend (names_mask[vex.mask_register_specifier]);
12149                       oappend ("}");
12150                     }
12151                   if (vex.zeroing)
12152                     oappend ("{z}");
12153                 }
12154             }
12155         }
12156     }
12157
12158   /* Clear instruction information.  */
12159   if (the_info)
12160     {
12161       the_info->insn_info_valid = 0;
12162       the_info->branch_delay_insns = 0;
12163       the_info->data_size = 0;
12164       the_info->insn_type = dis_noninsn;
12165       the_info->target = 0;
12166       the_info->target2 = 0;
12167     }
12168
12169   /* Reset jump operation indicator.  */
12170   op_is_jump = FALSE;
12171
12172   {
12173     int jump_detection = 0;
12174
12175     /* Extract flags.  */
12176     for (i = 0; i < MAX_OPERANDS; ++i)
12177       {
12178         if ((dp->op[i].rtn == OP_J)
12179             || (dp->op[i].rtn == OP_indirE))
12180           jump_detection |= 1;
12181         else if ((dp->op[i].rtn == BND_Fixup)
12182                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12183           jump_detection |= 2;
12184         else if ((dp->op[i].bytemode == cond_jump_mode)
12185                  || (dp->op[i].bytemode == loop_jcxz_mode))
12186           jump_detection |= 4;
12187       }
12188
12189     /* Determine if this is a jump or branch.  */
12190     if ((jump_detection & 0x3) == 0x3)
12191       {
12192         op_is_jump = TRUE;
12193         if (jump_detection & 0x4)
12194           the_info->insn_type = dis_condbranch;
12195         else
12196           the_info->insn_type =
12197             (dp->name && !strncmp(dp->name, "call", 4))
12198             ? dis_jsr : dis_branch;
12199       }
12200   }
12201
12202   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12203      are all 0s in inverted form.  */
12204   if (need_vex && vex.register_specifier != 0)
12205     {
12206       (*info->fprintf_func) (info->stream, "(bad)");
12207       return end_codep - priv.the_buffer;
12208     }
12209
12210   /* Check if the REX prefix is used.  */
12211   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12212     all_prefixes[last_rex_prefix] = 0;
12213
12214   /* Check if the SEG prefix is used.  */
12215   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12216                    | PREFIX_FS | PREFIX_GS)) != 0
12217       && (used_prefixes & active_seg_prefix) != 0)
12218     all_prefixes[last_seg_prefix] = 0;
12219
12220   /* Check if the ADDR prefix is used.  */
12221   if ((prefixes & PREFIX_ADDR) != 0
12222       && (used_prefixes & PREFIX_ADDR) != 0)
12223     all_prefixes[last_addr_prefix] = 0;
12224
12225   /* Check if the DATA prefix is used.  */
12226   if ((prefixes & PREFIX_DATA) != 0
12227       && (used_prefixes & PREFIX_DATA) != 0)
12228     all_prefixes[last_data_prefix] = 0;
12229
12230   /* Print the extra prefixes.  */
12231   prefix_length = 0;
12232   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12233     if (all_prefixes[i])
12234       {
12235         const char *name;
12236         name = prefix_name (all_prefixes[i], orig_sizeflag);
12237         if (name == NULL)
12238           abort ();
12239         prefix_length += strlen (name) + 1;
12240         (*info->fprintf_func) (info->stream, "%s ", name);
12241       }
12242
12243   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12244      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12245      used by putop and MMX/SSE operand and may be overriden by the
12246      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12247      separately.  */
12248   if (dp->prefix_requirement == PREFIX_OPCODE
12249       && dp != &bad_opcode
12250       && (((prefixes
12251             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12252            && (used_prefixes
12253                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12254           || ((((prefixes
12255                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12256                 == PREFIX_DATA)
12257                && (used_prefixes & PREFIX_DATA) == 0))))
12258     {
12259       (*info->fprintf_func) (info->stream, "(bad)");
12260       return end_codep - priv.the_buffer;
12261     }
12262
12263   /* Check maximum code length.  */
12264   if ((codep - start_codep) > MAX_CODE_LENGTH)
12265     {
12266       (*info->fprintf_func) (info->stream, "(bad)");
12267       return MAX_CODE_LENGTH;
12268     }
12269
12270   obufp = mnemonicendp;
12271   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12272     oappend (" ");
12273   oappend (" ");
12274   (*info->fprintf_func) (info->stream, "%s", obuf);
12275
12276   /* The enter and bound instructions are printed with operands in the same
12277      order as the intel book; everything else is printed in reverse order.  */
12278   if (intel_syntax || two_source_ops)
12279     {
12280       bfd_vma riprel;
12281
12282       for (i = 0; i < MAX_OPERANDS; ++i)
12283         op_txt[i] = op_out[i];
12284
12285       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12286           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12287         {
12288           op_txt[2] = op_out[3];
12289           op_txt[3] = op_out[2];
12290         }
12291
12292       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12293         {
12294           op_ad = op_index[i];
12295           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12296           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12297           riprel = op_riprel[i];
12298           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12299           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12300         }
12301     }
12302   else
12303     {
12304       for (i = 0; i < MAX_OPERANDS; ++i)
12305         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12306     }
12307
12308   needcomma = 0;
12309   for (i = 0; i < MAX_OPERANDS; ++i)
12310     if (*op_txt[i])
12311       {
12312         if (needcomma)
12313           (*info->fprintf_func) (info->stream, ",");
12314         if (op_index[i] != -1 && !op_riprel[i])
12315           {
12316             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12317
12318             if (the_info && op_is_jump)
12319               {
12320                 the_info->insn_info_valid = 1;
12321                 the_info->branch_delay_insns = 0;
12322                 the_info->data_size = 0;
12323                 the_info->target = target;
12324                 the_info->target2 = 0;
12325               }
12326             (*info->print_address_func) (target, info);
12327           }
12328         else
12329           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12330         needcomma = 1;
12331       }
12332
12333   for (i = 0; i < MAX_OPERANDS; i++)
12334     if (op_index[i] != -1 && op_riprel[i])
12335       {
12336         (*info->fprintf_func) (info->stream, "        # ");
12337         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12338                                                 + op_address[op_index[i]]), info);
12339         break;
12340       }
12341   return codep - priv.the_buffer;
12342 }
12343
12344 static const char *float_mem[] = {
12345   /* d8 */
12346   "fadd{s|}",
12347   "fmul{s|}",
12348   "fcom{s|}",
12349   "fcomp{s|}",
12350   "fsub{s|}",
12351   "fsubr{s|}",
12352   "fdiv{s|}",
12353   "fdivr{s|}",
12354   /* d9 */
12355   "fld{s|}",
12356   "(bad)",
12357   "fst{s|}",
12358   "fstp{s|}",
12359   "fldenvIC",
12360   "fldcw",
12361   "fNstenvIC",
12362   "fNstcw",
12363   /* da */
12364   "fiadd{l|}",
12365   "fimul{l|}",
12366   "ficom{l|}",
12367   "ficomp{l|}",
12368   "fisub{l|}",
12369   "fisubr{l|}",
12370   "fidiv{l|}",
12371   "fidivr{l|}",
12372   /* db */
12373   "fild{l|}",
12374   "fisttp{l|}",
12375   "fist{l|}",
12376   "fistp{l|}",
12377   "(bad)",
12378   "fld{t||t|}",
12379   "(bad)",
12380   "fstp{t||t|}",
12381   /* dc */
12382   "fadd{l|}",
12383   "fmul{l|}",
12384   "fcom{l|}",
12385   "fcomp{l|}",
12386   "fsub{l|}",
12387   "fsubr{l|}",
12388   "fdiv{l|}",
12389   "fdivr{l|}",
12390   /* dd */
12391   "fld{l|}",
12392   "fisttp{ll|}",
12393   "fst{l||}",
12394   "fstp{l|}",
12395   "frstorIC",
12396   "(bad)",
12397   "fNsaveIC",
12398   "fNstsw",
12399   /* de */
12400   "fiadd{s|}",
12401   "fimul{s|}",
12402   "ficom{s|}",
12403   "ficomp{s|}",
12404   "fisub{s|}",
12405   "fisubr{s|}",
12406   "fidiv{s|}",
12407   "fidivr{s|}",
12408   /* df */
12409   "fild{s|}",
12410   "fisttp{s|}",
12411   "fist{s|}",
12412   "fistp{s|}",
12413   "fbld",
12414   "fild{ll|}",
12415   "fbstp",
12416   "fistp{ll|}",
12417 };
12418
12419 static const unsigned char float_mem_mode[] = {
12420   /* d8 */
12421   d_mode,
12422   d_mode,
12423   d_mode,
12424   d_mode,
12425   d_mode,
12426   d_mode,
12427   d_mode,
12428   d_mode,
12429   /* d9 */
12430   d_mode,
12431   0,
12432   d_mode,
12433   d_mode,
12434   0,
12435   w_mode,
12436   0,
12437   w_mode,
12438   /* da */
12439   d_mode,
12440   d_mode,
12441   d_mode,
12442   d_mode,
12443   d_mode,
12444   d_mode,
12445   d_mode,
12446   d_mode,
12447   /* db */
12448   d_mode,
12449   d_mode,
12450   d_mode,
12451   d_mode,
12452   0,
12453   t_mode,
12454   0,
12455   t_mode,
12456   /* dc */
12457   q_mode,
12458   q_mode,
12459   q_mode,
12460   q_mode,
12461   q_mode,
12462   q_mode,
12463   q_mode,
12464   q_mode,
12465   /* dd */
12466   q_mode,
12467   q_mode,
12468   q_mode,
12469   q_mode,
12470   0,
12471   0,
12472   0,
12473   w_mode,
12474   /* de */
12475   w_mode,
12476   w_mode,
12477   w_mode,
12478   w_mode,
12479   w_mode,
12480   w_mode,
12481   w_mode,
12482   w_mode,
12483   /* df */
12484   w_mode,
12485   w_mode,
12486   w_mode,
12487   w_mode,
12488   t_mode,
12489   q_mode,
12490   t_mode,
12491   q_mode
12492 };
12493
12494 #define ST { OP_ST, 0 }
12495 #define STi { OP_STi, 0 }
12496
12497 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12498 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12499 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12500 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12501 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12502 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12503 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12504 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12505 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12506
12507 static const struct dis386 float_reg[][8] = {
12508   /* d8 */
12509   {
12510     { "fadd",   { ST, STi }, 0 },
12511     { "fmul",   { ST, STi }, 0 },
12512     { "fcom",   { STi }, 0 },
12513     { "fcomp",  { STi }, 0 },
12514     { "fsub",   { ST, STi }, 0 },
12515     { "fsubr",  { ST, STi }, 0 },
12516     { "fdiv",   { ST, STi }, 0 },
12517     { "fdivr",  { ST, STi }, 0 },
12518   },
12519   /* d9 */
12520   {
12521     { "fld",    { STi }, 0 },
12522     { "fxch",   { STi }, 0 },
12523     { FGRPd9_2 },
12524     { Bad_Opcode },
12525     { FGRPd9_4 },
12526     { FGRPd9_5 },
12527     { FGRPd9_6 },
12528     { FGRPd9_7 },
12529   },
12530   /* da */
12531   {
12532     { "fcmovb", { ST, STi }, 0 },
12533     { "fcmove", { ST, STi }, 0 },
12534     { "fcmovbe",{ ST, STi }, 0 },
12535     { "fcmovu", { ST, STi }, 0 },
12536     { Bad_Opcode },
12537     { FGRPda_5 },
12538     { Bad_Opcode },
12539     { Bad_Opcode },
12540   },
12541   /* db */
12542   {
12543     { "fcmovnb",{ ST, STi }, 0 },
12544     { "fcmovne",{ ST, STi }, 0 },
12545     { "fcmovnbe",{ ST, STi }, 0 },
12546     { "fcmovnu",{ ST, STi }, 0 },
12547     { FGRPdb_4 },
12548     { "fucomi", { ST, STi }, 0 },
12549     { "fcomi",  { ST, STi }, 0 },
12550     { Bad_Opcode },
12551   },
12552   /* dc */
12553   {
12554     { "fadd",   { STi, ST }, 0 },
12555     { "fmul",   { STi, ST }, 0 },
12556     { Bad_Opcode },
12557     { Bad_Opcode },
12558     { "fsub{!M|r}",     { STi, ST }, 0 },
12559     { "fsub{M|}",       { STi, ST }, 0 },
12560     { "fdiv{!M|r}",     { STi, ST }, 0 },
12561     { "fdiv{M|}",       { STi, ST }, 0 },
12562   },
12563   /* dd */
12564   {
12565     { "ffree",  { STi }, 0 },
12566     { Bad_Opcode },
12567     { "fst",    { STi }, 0 },
12568     { "fstp",   { STi }, 0 },
12569     { "fucom",  { STi }, 0 },
12570     { "fucomp", { STi }, 0 },
12571     { Bad_Opcode },
12572     { Bad_Opcode },
12573   },
12574   /* de */
12575   {
12576     { "faddp",  { STi, ST }, 0 },
12577     { "fmulp",  { STi, ST }, 0 },
12578     { Bad_Opcode },
12579     { FGRPde_3 },
12580     { "fsub{!M|r}p",    { STi, ST }, 0 },
12581     { "fsub{M|}p",      { STi, ST }, 0 },
12582     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12583     { "fdiv{M|}p",      { STi, ST }, 0 },
12584   },
12585   /* df */
12586   {
12587     { "ffreep", { STi }, 0 },
12588     { Bad_Opcode },
12589     { Bad_Opcode },
12590     { Bad_Opcode },
12591     { FGRPdf_4 },
12592     { "fucomip", { ST, STi }, 0 },
12593     { "fcomip", { ST, STi }, 0 },
12594     { Bad_Opcode },
12595   },
12596 };
12597
12598 static char *fgrps[][8] = {
12599   /* Bad opcode 0 */
12600   {
12601     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12602   },
12603
12604   /* d9_2  1 */
12605   {
12606     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12607   },
12608
12609   /* d9_4  2 */
12610   {
12611     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12612   },
12613
12614   /* d9_5  3 */
12615   {
12616     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12617   },
12618
12619   /* d9_6  4 */
12620   {
12621     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12622   },
12623
12624   /* d9_7  5 */
12625   {
12626     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12627   },
12628
12629   /* da_5  6 */
12630   {
12631     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12632   },
12633
12634   /* db_4  7 */
12635   {
12636     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12637     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12638   },
12639
12640   /* de_3  8 */
12641   {
12642     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12643   },
12644
12645   /* df_4  9 */
12646   {
12647     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12648   },
12649 };
12650
12651 static void
12652 swap_operand (void)
12653 {
12654   mnemonicendp[0] = '.';
12655   mnemonicendp[1] = 's';
12656   mnemonicendp += 2;
12657 }
12658
12659 static void
12660 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12661                int sizeflag ATTRIBUTE_UNUSED)
12662 {
12663   /* Skip mod/rm byte.  */
12664   MODRM_CHECK;
12665   codep++;
12666 }
12667
12668 static void
12669 dofloat (int sizeflag)
12670 {
12671   const struct dis386 *dp;
12672   unsigned char floatop;
12673
12674   floatop = codep[-1];
12675
12676   if (modrm.mod != 3)
12677     {
12678       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12679
12680       putop (float_mem[fp_indx], sizeflag);
12681       obufp = op_out[0];
12682       op_ad = 2;
12683       OP_E (float_mem_mode[fp_indx], sizeflag);
12684       return;
12685     }
12686   /* Skip mod/rm byte.  */
12687   MODRM_CHECK;
12688   codep++;
12689
12690   dp = &float_reg[floatop - 0xd8][modrm.reg];
12691   if (dp->name == NULL)
12692     {
12693       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12694
12695       /* Instruction fnstsw is only one with strange arg.  */
12696       if (floatop == 0xdf && codep[-1] == 0xe0)
12697         strcpy (op_out[0], names16[0]);
12698     }
12699   else
12700     {
12701       putop (dp->name, sizeflag);
12702
12703       obufp = op_out[0];
12704       op_ad = 2;
12705       if (dp->op[0].rtn)
12706         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12707
12708       obufp = op_out[1];
12709       op_ad = 1;
12710       if (dp->op[1].rtn)
12711         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12712     }
12713 }
12714
12715 /* Like oappend (below), but S is a string starting with '%'.
12716    In Intel syntax, the '%' is elided.  */
12717 static void
12718 oappend_maybe_intel (const char *s)
12719 {
12720   oappend (s + intel_syntax);
12721 }
12722
12723 static void
12724 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12725 {
12726   oappend_maybe_intel ("%st");
12727 }
12728
12729 static void
12730 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12731 {
12732   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12733   oappend_maybe_intel (scratchbuf);
12734 }
12735
12736 /* Capital letters in template are macros.  */
12737 static int
12738 putop (const char *in_template, int sizeflag)
12739 {
12740   const char *p;
12741   int alt = 0;
12742   int cond = 1;
12743   unsigned int l = 0, len = 1;
12744   char last[4];
12745
12746 #define SAVE_LAST(c)                    \
12747   if (l < len && l < sizeof (last))     \
12748     last[l++] = c;                      \
12749   else                                  \
12750     abort ();
12751
12752   for (p = in_template; *p; p++)
12753     {
12754       switch (*p)
12755         {
12756         default:
12757           *obufp++ = *p;
12758           break;
12759         case '%':
12760           len++;
12761           break;
12762         case '!':
12763           cond = 0;
12764           break;
12765         case '{':
12766           if (intel_syntax)
12767             {
12768               while (*++p != '|')
12769                 if (*p == '}' || *p == '\0')
12770                   abort ();
12771             }
12772           /* Fall through.  */
12773         case 'I':
12774           alt = 1;
12775           continue;
12776         case '|':
12777           while (*++p != '}')
12778             {
12779               if (*p == '\0')
12780                 abort ();
12781             }
12782           break;
12783         case '}':
12784           break;
12785         case 'A':
12786           if (intel_syntax)
12787             break;
12788           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12789             *obufp++ = 'b';
12790           break;
12791         case 'B':
12792           if (l == 0 && len == 1)
12793             {
12794 case_B:
12795               if (intel_syntax)
12796                 break;
12797               if (sizeflag & SUFFIX_ALWAYS)
12798                 *obufp++ = 'b';
12799             }
12800           else
12801             {
12802               if (l != 1
12803                   || len != 2
12804                   || last[0] != 'L')
12805                 {
12806                   SAVE_LAST (*p);
12807                   break;
12808                 }
12809
12810               if (address_mode == mode_64bit
12811                   && !(prefixes & PREFIX_ADDR))
12812                 {
12813                   *obufp++ = 'a';
12814                   *obufp++ = 'b';
12815                   *obufp++ = 's';
12816                 }
12817
12818               goto case_B;
12819             }
12820           break;
12821         case 'C':
12822           if (intel_syntax && !alt)
12823             break;
12824           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12825             {
12826               if (sizeflag & DFLAG)
12827                 *obufp++ = intel_syntax ? 'd' : 'l';
12828               else
12829                 *obufp++ = intel_syntax ? 'w' : 's';
12830               used_prefixes |= (prefixes & PREFIX_DATA);
12831             }
12832           break;
12833         case 'D':
12834           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12835             break;
12836           USED_REX (REX_W);
12837           if (modrm.mod == 3)
12838             {
12839               if (rex & REX_W)
12840                 *obufp++ = 'q';
12841               else
12842                 {
12843                   if (sizeflag & DFLAG)
12844                     *obufp++ = intel_syntax ? 'd' : 'l';
12845                   else
12846                     *obufp++ = 'w';
12847                   used_prefixes |= (prefixes & PREFIX_DATA);
12848                 }
12849             }
12850           else
12851             *obufp++ = 'w';
12852           break;
12853         case 'E':               /* For jcxz/jecxz */
12854           if (address_mode == mode_64bit)
12855             {
12856               if (sizeflag & AFLAG)
12857                 *obufp++ = 'r';
12858               else
12859                 *obufp++ = 'e';
12860             }
12861           else
12862             if (sizeflag & AFLAG)
12863               *obufp++ = 'e';
12864           used_prefixes |= (prefixes & PREFIX_ADDR);
12865           break;
12866         case 'F':
12867           if (intel_syntax)
12868             break;
12869           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12870             {
12871               if (sizeflag & AFLAG)
12872                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12873               else
12874                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12875               used_prefixes |= (prefixes & PREFIX_ADDR);
12876             }
12877           break;
12878         case 'G':
12879           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12880             break;
12881           if ((rex & REX_W) || (sizeflag & DFLAG))
12882             *obufp++ = 'l';
12883           else
12884             *obufp++ = 'w';
12885           if (!(rex & REX_W))
12886             used_prefixes |= (prefixes & PREFIX_DATA);
12887           break;
12888         case 'H':
12889           if (intel_syntax)
12890             break;
12891           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12892               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12893             {
12894               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12895               *obufp++ = ',';
12896               *obufp++ = 'p';
12897               if (prefixes & PREFIX_DS)
12898                 *obufp++ = 't';
12899               else
12900                 *obufp++ = 'n';
12901             }
12902           break;
12903         case 'J':
12904           if (intel_syntax)
12905             break;
12906           *obufp++ = 'l';
12907           break;
12908         case 'K':
12909           USED_REX (REX_W);
12910           if (rex & REX_W)
12911             *obufp++ = 'q';
12912           else
12913             *obufp++ = 'd';
12914           break;
12915         case 'Z':
12916           if (l != 0 || len != 1)
12917             {
12918               if (l != 1 || len != 2 || last[0] != 'X')
12919                 {
12920                   SAVE_LAST (*p);
12921                   break;
12922                 }
12923               if (!need_vex || !vex.evex)
12924                 abort ();
12925               if (intel_syntax
12926                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12927                 break;
12928               switch (vex.length)
12929                 {
12930                 case 128:
12931                   *obufp++ = 'x';
12932                   break;
12933                 case 256:
12934                   *obufp++ = 'y';
12935                   break;
12936                 case 512:
12937                   *obufp++ = 'z';
12938                   break;
12939                 default:
12940                   abort ();
12941                 }
12942               break;
12943             }
12944           if (intel_syntax)
12945             break;
12946           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12947             {
12948               *obufp++ = 'q';
12949               break;
12950             }
12951           /* Fall through.  */
12952           goto case_L;
12953         case 'L':
12954           if (l != 0 || len != 1)
12955             {
12956               SAVE_LAST (*p);
12957               break;
12958             }
12959 case_L:
12960           if (intel_syntax)
12961             break;
12962           if (sizeflag & SUFFIX_ALWAYS)
12963             *obufp++ = 'l';
12964           break;
12965         case 'M':
12966           if (intel_mnemonic != cond)
12967             *obufp++ = 'r';
12968           break;
12969         case 'N':
12970           if ((prefixes & PREFIX_FWAIT) == 0)
12971             *obufp++ = 'n';
12972           else
12973             used_prefixes |= PREFIX_FWAIT;
12974           break;
12975         case 'O':
12976           USED_REX (REX_W);
12977           if (rex & REX_W)
12978             *obufp++ = 'o';
12979           else if (intel_syntax && (sizeflag & DFLAG))
12980             *obufp++ = 'q';
12981           else
12982             *obufp++ = 'd';
12983           if (!(rex & REX_W))
12984             used_prefixes |= (prefixes & PREFIX_DATA);
12985           break;
12986         case '&':
12987           if (!intel_syntax
12988               && address_mode == mode_64bit
12989               && isa64 == intel64)
12990             {
12991               *obufp++ = 'q';
12992               break;
12993             }
12994           /* Fall through.  */
12995         case 'T':
12996           if (!intel_syntax
12997               && address_mode == mode_64bit
12998               && ((sizeflag & DFLAG) || (rex & REX_W)))
12999             {
13000               *obufp++ = 'q';
13001               break;
13002             }
13003           /* Fall through.  */
13004           goto case_P;
13005         case 'P':
13006           if (l == 0 && len == 1)
13007             {
13008 case_P:
13009               if (intel_syntax)
13010                 {
13011                   if ((rex & REX_W) == 0
13012                       && (prefixes & PREFIX_DATA))
13013                     {
13014                       if ((sizeflag & DFLAG) == 0)
13015                         *obufp++ = 'w';
13016                       used_prefixes |= (prefixes & PREFIX_DATA);
13017                     }
13018                   break;
13019                 }
13020               if ((prefixes & PREFIX_DATA)
13021                   || (rex & REX_W)
13022                   || (sizeflag & SUFFIX_ALWAYS))
13023                 {
13024                   USED_REX (REX_W);
13025                   if (rex & REX_W)
13026                     *obufp++ = 'q';
13027                   else
13028                     {
13029                       if (sizeflag & DFLAG)
13030                         *obufp++ = 'l';
13031                       else
13032                         *obufp++ = 'w';
13033                       used_prefixes |= (prefixes & PREFIX_DATA);
13034                     }
13035                 }
13036             }
13037           else
13038             {
13039               if (l != 1 || len != 2 || last[0] != 'L')
13040                 {
13041                   SAVE_LAST (*p);
13042                   break;
13043                 }
13044
13045               if ((prefixes & PREFIX_DATA)
13046                   || (rex & REX_W)
13047                   || (sizeflag & SUFFIX_ALWAYS))
13048                 {
13049                   USED_REX (REX_W);
13050                   if (rex & REX_W)
13051                     *obufp++ = 'q';
13052                   else
13053                     {
13054                       if (sizeflag & DFLAG)
13055                         *obufp++ = intel_syntax ? 'd' : 'l';
13056                       else
13057                         *obufp++ = 'w';
13058                       used_prefixes |= (prefixes & PREFIX_DATA);
13059                     }
13060                 }
13061             }
13062           break;
13063         case 'U':
13064           if (intel_syntax)
13065             break;
13066           if (address_mode == mode_64bit
13067               && ((sizeflag & DFLAG) || (rex & REX_W)))
13068             {
13069               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13070                 *obufp++ = 'q';
13071               break;
13072             }
13073           /* Fall through.  */
13074           goto case_Q;
13075         case 'Q':
13076           if (l == 0 && len == 1)
13077             {
13078 case_Q:
13079               if (intel_syntax && !alt)
13080                 break;
13081               USED_REX (REX_W);
13082               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13083                 {
13084                   if (rex & REX_W)
13085                     *obufp++ = 'q';
13086                   else
13087                     {
13088                       if (sizeflag & DFLAG)
13089                         *obufp++ = intel_syntax ? 'd' : 'l';
13090                       else
13091                         *obufp++ = 'w';
13092                       used_prefixes |= (prefixes & PREFIX_DATA);
13093                     }
13094                 }
13095             }
13096           else
13097             {
13098               if (l != 1 || len != 2 || last[0] != 'L')
13099                 {
13100                   SAVE_LAST (*p);
13101                   break;
13102                 }
13103               if (intel_syntax
13104                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13105                 break;
13106               if ((rex & REX_W))
13107                 {
13108                   USED_REX (REX_W);
13109                   *obufp++ = 'q';
13110                 }
13111               else
13112                 *obufp++ = 'l';
13113             }
13114           break;
13115         case 'R':
13116           USED_REX (REX_W);
13117           if (rex & REX_W)
13118             *obufp++ = 'q';
13119           else if (sizeflag & DFLAG)
13120             {
13121               if (intel_syntax)
13122                   *obufp++ = 'd';
13123               else
13124                   *obufp++ = 'l';
13125             }
13126           else
13127             *obufp++ = 'w';
13128           if (intel_syntax && !p[1]
13129               && ((rex & REX_W) || (sizeflag & DFLAG)))
13130             *obufp++ = 'e';
13131           if (!(rex & REX_W))
13132             used_prefixes |= (prefixes & PREFIX_DATA);
13133           break;
13134         case 'V':
13135           if (l == 0 && len == 1)
13136             {
13137               if (intel_syntax)
13138                 break;
13139               if (address_mode == mode_64bit
13140                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13141                 {
13142                   if (sizeflag & SUFFIX_ALWAYS)
13143                     *obufp++ = 'q';
13144                   break;
13145                 }
13146             }
13147           else
13148             {
13149               if (l != 1
13150                   || len != 2
13151                   || last[0] != 'L')
13152                 {
13153                   SAVE_LAST (*p);
13154                   break;
13155                 }
13156
13157               if (rex & REX_W)
13158                 {
13159                   *obufp++ = 'a';
13160                   *obufp++ = 'b';
13161                   *obufp++ = 's';
13162                 }
13163             }
13164           /* Fall through.  */
13165           goto case_S;
13166         case 'S':
13167           if (l == 0 && len == 1)
13168             {
13169 case_S:
13170               if (intel_syntax)
13171                 break;
13172               if (sizeflag & SUFFIX_ALWAYS)
13173                 {
13174                   if (rex & REX_W)
13175                     *obufp++ = 'q';
13176                   else
13177                     {
13178                       if (sizeflag & DFLAG)
13179                         *obufp++ = 'l';
13180                       else
13181                         *obufp++ = 'w';
13182                       used_prefixes |= (prefixes & PREFIX_DATA);
13183                     }
13184                 }
13185             }
13186           else
13187             {
13188               if (l != 1
13189                   || len != 2
13190                   || last[0] != 'L')
13191                 {
13192                   SAVE_LAST (*p);
13193                   break;
13194                 }
13195
13196               if (address_mode == mode_64bit
13197                   && !(prefixes & PREFIX_ADDR))
13198                 {
13199                   *obufp++ = 'a';
13200                   *obufp++ = 'b';
13201                   *obufp++ = 's';
13202                 }
13203
13204               goto case_S;
13205             }
13206           break;
13207         case 'X':
13208           if (l != 0 || len != 1)
13209             {
13210               SAVE_LAST (*p);
13211               break;
13212             }
13213           if (need_vex && vex.prefix)
13214             {
13215               if (vex.prefix == DATA_PREFIX_OPCODE)
13216                 *obufp++ = 'd';
13217               else
13218                 *obufp++ = 's';
13219             }
13220           else
13221             {
13222               if (prefixes & PREFIX_DATA)
13223                 *obufp++ = 'd';
13224               else
13225                 *obufp++ = 's';
13226               used_prefixes |= (prefixes & PREFIX_DATA);
13227             }
13228           break;
13229         case 'Y':
13230           if (l == 0 && len == 1)
13231             abort ();
13232           else
13233             {
13234               if (l != 1 || len != 2 || last[0] != 'X')
13235                 {
13236                   SAVE_LAST (*p);
13237                   break;
13238                 }
13239               if (!need_vex)
13240                 abort ();
13241               if (intel_syntax
13242                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13243                 break;
13244               switch (vex.length)
13245                 {
13246                 case 128:
13247                   *obufp++ = 'x';
13248                   break;
13249                 case 256:
13250                   *obufp++ = 'y';
13251                   break;
13252                 case 512:
13253                   if (!vex.evex)
13254                 default:
13255                     abort ();
13256                 }
13257             }
13258           break;
13259         case 'W':
13260           if (l == 0 && len == 1)
13261             {
13262               /* operand size flag for cwtl, cbtw */
13263               USED_REX (REX_W);
13264               if (rex & REX_W)
13265                 {
13266                   if (intel_syntax)
13267                     *obufp++ = 'd';
13268                   else
13269                     *obufp++ = 'l';
13270                 }
13271               else if (sizeflag & DFLAG)
13272                 *obufp++ = 'w';
13273               else
13274                 *obufp++ = 'b';
13275               if (!(rex & REX_W))
13276                 used_prefixes |= (prefixes & PREFIX_DATA);
13277             }
13278           else
13279             {
13280               if (l != 1
13281                   || len != 2
13282                   || (last[0] != 'X'
13283                       && last[0] != 'L'))
13284                 {
13285                   SAVE_LAST (*p);
13286                   break;
13287                 }
13288               if (!need_vex)
13289                 abort ();
13290               if (last[0] == 'X')
13291                 *obufp++ = vex.w ? 'd': 's';
13292               else
13293                 *obufp++ = vex.w ? 'q': 'd';
13294             }
13295           break;
13296         case '^':
13297           if (intel_syntax)
13298             break;
13299           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13300             {
13301               if (sizeflag & DFLAG)
13302                 *obufp++ = 'l';
13303               else
13304                 *obufp++ = 'w';
13305               used_prefixes |= (prefixes & PREFIX_DATA);
13306             }
13307           break;
13308         case '@':
13309           if (intel_syntax)
13310             break;
13311           if (address_mode == mode_64bit
13312               && (isa64 == intel64
13313                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13314               *obufp++ = 'q';
13315           else if ((prefixes & PREFIX_DATA))
13316             {
13317               if (!(sizeflag & DFLAG))
13318                 *obufp++ = 'w';
13319               used_prefixes |= (prefixes & PREFIX_DATA);
13320             }
13321           break;
13322         }
13323       alt = 0;
13324     }
13325   *obufp = 0;
13326   mnemonicendp = obufp;
13327   return 0;
13328 }
13329
13330 static void
13331 oappend (const char *s)
13332 {
13333   obufp = stpcpy (obufp, s);
13334 }
13335
13336 static void
13337 append_seg (void)
13338 {
13339   /* Only print the active segment register.  */
13340   if (!active_seg_prefix)
13341     return;
13342
13343   used_prefixes |= active_seg_prefix;
13344   switch (active_seg_prefix)
13345     {
13346     case PREFIX_CS:
13347       oappend_maybe_intel ("%cs:");
13348       break;
13349     case PREFIX_DS:
13350       oappend_maybe_intel ("%ds:");
13351       break;
13352     case PREFIX_SS:
13353       oappend_maybe_intel ("%ss:");
13354       break;
13355     case PREFIX_ES:
13356       oappend_maybe_intel ("%es:");
13357       break;
13358     case PREFIX_FS:
13359       oappend_maybe_intel ("%fs:");
13360       break;
13361     case PREFIX_GS:
13362       oappend_maybe_intel ("%gs:");
13363       break;
13364     default:
13365       break;
13366     }
13367 }
13368
13369 static void
13370 OP_indirE (int bytemode, int sizeflag)
13371 {
13372   if (!intel_syntax)
13373     oappend ("*");
13374   OP_E (bytemode, sizeflag);
13375 }
13376
13377 static void
13378 print_operand_value (char *buf, int hex, bfd_vma disp)
13379 {
13380   if (address_mode == mode_64bit)
13381     {
13382       if (hex)
13383         {
13384           char tmp[30];
13385           int i;
13386           buf[0] = '0';
13387           buf[1] = 'x';
13388           sprintf_vma (tmp, disp);
13389           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13390           strcpy (buf + 2, tmp + i);
13391         }
13392       else
13393         {
13394           bfd_signed_vma v = disp;
13395           char tmp[30];
13396           int i;
13397           if (v < 0)
13398             {
13399               *(buf++) = '-';
13400               v = -disp;
13401               /* Check for possible overflow on 0x8000000000000000.  */
13402               if (v < 0)
13403                 {
13404                   strcpy (buf, "9223372036854775808");
13405                   return;
13406                 }
13407             }
13408           if (!v)
13409             {
13410               strcpy (buf, "0");
13411               return;
13412             }
13413
13414           i = 0;
13415           tmp[29] = 0;
13416           while (v)
13417             {
13418               tmp[28 - i] = (v % 10) + '0';
13419               v /= 10;
13420               i++;
13421             }
13422           strcpy (buf, tmp + 29 - i);
13423         }
13424     }
13425   else
13426     {
13427       if (hex)
13428         sprintf (buf, "0x%x", (unsigned int) disp);
13429       else
13430         sprintf (buf, "%d", (int) disp);
13431     }
13432 }
13433
13434 /* Put DISP in BUF as signed hex number.  */
13435
13436 static void
13437 print_displacement (char *buf, bfd_vma disp)
13438 {
13439   bfd_signed_vma val = disp;
13440   char tmp[30];
13441   int i, j = 0;
13442
13443   if (val < 0)
13444     {
13445       buf[j++] = '-';
13446       val = -disp;
13447
13448       /* Check for possible overflow.  */
13449       if (val < 0)
13450         {
13451           switch (address_mode)
13452             {
13453             case mode_64bit:
13454               strcpy (buf + j, "0x8000000000000000");
13455               break;
13456             case mode_32bit:
13457               strcpy (buf + j, "0x80000000");
13458               break;
13459             case mode_16bit:
13460               strcpy (buf + j, "0x8000");
13461               break;
13462             }
13463           return;
13464         }
13465     }
13466
13467   buf[j++] = '0';
13468   buf[j++] = 'x';
13469
13470   sprintf_vma (tmp, (bfd_vma) val);
13471   for (i = 0; tmp[i] == '0'; i++)
13472     continue;
13473   if (tmp[i] == '\0')
13474     i--;
13475   strcpy (buf + j, tmp + i);
13476 }
13477
13478 static void
13479 intel_operand_size (int bytemode, int sizeflag)
13480 {
13481   if (vex.evex
13482       && vex.b
13483       && (bytemode == x_mode
13484           || bytemode == evex_half_bcst_xmmq_mode))
13485     {
13486       if (vex.w)
13487         oappend ("QWORD PTR ");
13488       else
13489         oappend ("DWORD PTR ");
13490       return;
13491     }
13492   switch (bytemode)
13493     {
13494     case b_mode:
13495     case b_swap_mode:
13496     case dqb_mode:
13497     case db_mode:
13498       oappend ("BYTE PTR ");
13499       break;
13500     case w_mode:
13501     case dw_mode:
13502     case dqw_mode:
13503       oappend ("WORD PTR ");
13504       break;
13505     case indir_v_mode:
13506       if (address_mode == mode_64bit && isa64 == intel64)
13507         {
13508           oappend ("QWORD PTR ");
13509           break;
13510         }
13511       /* Fall through.  */
13512     case stack_v_mode:
13513       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13514         {
13515           oappend ("QWORD PTR ");
13516           break;
13517         }
13518       /* Fall through.  */
13519     case v_mode:
13520     case v_swap_mode:
13521     case dq_mode:
13522       USED_REX (REX_W);
13523       if (rex & REX_W)
13524         oappend ("QWORD PTR ");
13525       else
13526         {
13527           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13528             oappend ("DWORD PTR ");
13529           else
13530             oappend ("WORD PTR ");
13531           used_prefixes |= (prefixes & PREFIX_DATA);
13532         }
13533       break;
13534     case z_mode:
13535       if ((rex & REX_W) || (sizeflag & DFLAG))
13536         *obufp++ = 'D';
13537       oappend ("WORD PTR ");
13538       if (!(rex & REX_W))
13539         used_prefixes |= (prefixes & PREFIX_DATA);
13540       break;
13541     case a_mode:
13542       if (sizeflag & DFLAG)
13543         oappend ("QWORD PTR ");
13544       else
13545         oappend ("DWORD PTR ");
13546       used_prefixes |= (prefixes & PREFIX_DATA);
13547       break;
13548     case movsxd_mode:
13549       if (!(sizeflag & DFLAG) && isa64 == intel64)
13550         oappend ("WORD PTR ");
13551       else
13552         oappend ("DWORD PTR ");
13553       used_prefixes |= (prefixes & PREFIX_DATA);
13554       break;
13555     case d_mode:
13556     case d_scalar_mode:
13557     case d_scalar_swap_mode:
13558     case d_swap_mode:
13559     case dqd_mode:
13560       oappend ("DWORD PTR ");
13561       break;
13562     case q_mode:
13563     case q_scalar_mode:
13564     case q_scalar_swap_mode:
13565     case q_swap_mode:
13566       oappend ("QWORD PTR ");
13567       break;
13568     case m_mode:
13569       if (address_mode == mode_64bit)
13570         oappend ("QWORD PTR ");
13571       else
13572         oappend ("DWORD PTR ");
13573       break;
13574     case f_mode:
13575       if (sizeflag & DFLAG)
13576         oappend ("FWORD PTR ");
13577       else
13578         oappend ("DWORD PTR ");
13579       used_prefixes |= (prefixes & PREFIX_DATA);
13580       break;
13581     case t_mode:
13582       oappend ("TBYTE PTR ");
13583       break;
13584     case x_mode:
13585     case x_swap_mode:
13586     case evex_x_gscat_mode:
13587     case evex_x_nobcst_mode:
13588     case b_scalar_mode:
13589     case w_scalar_mode:
13590       if (need_vex)
13591         {
13592           switch (vex.length)
13593             {
13594             case 128:
13595               oappend ("XMMWORD PTR ");
13596               break;
13597             case 256:
13598               oappend ("YMMWORD PTR ");
13599               break;
13600             case 512:
13601               oappend ("ZMMWORD PTR ");
13602               break;
13603             default:
13604               abort ();
13605             }
13606         }
13607       else
13608         oappend ("XMMWORD PTR ");
13609       break;
13610     case xmm_mode:
13611       oappend ("XMMWORD PTR ");
13612       break;
13613     case ymm_mode:
13614       oappend ("YMMWORD PTR ");
13615       break;
13616     case xmmq_mode:
13617     case evex_half_bcst_xmmq_mode:
13618       if (!need_vex)
13619         abort ();
13620
13621       switch (vex.length)
13622         {
13623         case 128:
13624           oappend ("QWORD PTR ");
13625           break;
13626         case 256:
13627           oappend ("XMMWORD PTR ");
13628           break;
13629         case 512:
13630           oappend ("YMMWORD PTR ");
13631           break;
13632         default:
13633           abort ();
13634         }
13635       break;
13636     case xmm_mb_mode:
13637       if (!need_vex)
13638         abort ();
13639
13640       switch (vex.length)
13641         {
13642         case 128:
13643         case 256:
13644         case 512:
13645           oappend ("BYTE PTR ");
13646           break;
13647         default:
13648           abort ();
13649         }
13650       break;
13651     case xmm_mw_mode:
13652       if (!need_vex)
13653         abort ();
13654
13655       switch (vex.length)
13656         {
13657         case 128:
13658         case 256:
13659         case 512:
13660           oappend ("WORD PTR ");
13661           break;
13662         default:
13663           abort ();
13664         }
13665       break;
13666     case xmm_md_mode:
13667       if (!need_vex)
13668         abort ();
13669
13670       switch (vex.length)
13671         {
13672         case 128:
13673         case 256:
13674         case 512:
13675           oappend ("DWORD PTR ");
13676           break;
13677         default:
13678           abort ();
13679         }
13680       break;
13681     case xmm_mq_mode:
13682       if (!need_vex)
13683         abort ();
13684
13685       switch (vex.length)
13686         {
13687         case 128:
13688         case 256:
13689         case 512:
13690           oappend ("QWORD PTR ");
13691           break;
13692         default:
13693           abort ();
13694         }
13695       break;
13696     case xmmdw_mode:
13697       if (!need_vex)
13698         abort ();
13699
13700       switch (vex.length)
13701         {
13702         case 128:
13703           oappend ("WORD PTR ");
13704           break;
13705         case 256:
13706           oappend ("DWORD PTR ");
13707           break;
13708         case 512:
13709           oappend ("QWORD PTR ");
13710           break;
13711         default:
13712           abort ();
13713         }
13714       break;
13715     case xmmqd_mode:
13716       if (!need_vex)
13717         abort ();
13718
13719       switch (vex.length)
13720         {
13721         case 128:
13722           oappend ("DWORD PTR ");
13723           break;
13724         case 256:
13725           oappend ("QWORD PTR ");
13726           break;
13727         case 512:
13728           oappend ("XMMWORD PTR ");
13729           break;
13730         default:
13731           abort ();
13732         }
13733       break;
13734     case ymmq_mode:
13735       if (!need_vex)
13736         abort ();
13737
13738       switch (vex.length)
13739         {
13740         case 128:
13741           oappend ("QWORD PTR ");
13742           break;
13743         case 256:
13744           oappend ("YMMWORD PTR ");
13745           break;
13746         case 512:
13747           oappend ("ZMMWORD PTR ");
13748           break;
13749         default:
13750           abort ();
13751         }
13752       break;
13753     case ymmxmm_mode:
13754       if (!need_vex)
13755         abort ();
13756
13757       switch (vex.length)
13758         {
13759         case 128:
13760         case 256:
13761           oappend ("XMMWORD PTR ");
13762           break;
13763         default:
13764           abort ();
13765         }
13766       break;
13767     case o_mode:
13768       oappend ("OWORD PTR ");
13769       break;
13770     case vex_scalar_w_dq_mode:
13771       if (!need_vex)
13772         abort ();
13773
13774       if (vex.w)
13775         oappend ("QWORD PTR ");
13776       else
13777         oappend ("DWORD PTR ");
13778       break;
13779     case vex_vsib_d_w_dq_mode:
13780     case vex_vsib_q_w_dq_mode:
13781       if (!need_vex)
13782         abort ();
13783
13784       if (!vex.evex)
13785         {
13786           if (vex.w)
13787             oappend ("QWORD PTR ");
13788           else
13789             oappend ("DWORD PTR ");
13790         }
13791       else
13792         {
13793           switch (vex.length)
13794             {
13795             case 128:
13796               oappend ("XMMWORD PTR ");
13797               break;
13798             case 256:
13799               oappend ("YMMWORD PTR ");
13800               break;
13801             case 512:
13802               oappend ("ZMMWORD PTR ");
13803               break;
13804             default:
13805               abort ();
13806             }
13807         }
13808       break;
13809     case vex_vsib_q_w_d_mode:
13810     case vex_vsib_d_w_d_mode:
13811       if (!need_vex || !vex.evex)
13812         abort ();
13813
13814       switch (vex.length)
13815         {
13816         case 128:
13817           oappend ("QWORD PTR ");
13818           break;
13819         case 256:
13820           oappend ("XMMWORD PTR ");
13821           break;
13822         case 512:
13823           oappend ("YMMWORD PTR ");
13824           break;
13825         default:
13826           abort ();
13827         }
13828
13829       break;
13830     case mask_bd_mode:
13831       if (!need_vex || vex.length != 128)
13832         abort ();
13833       if (vex.w)
13834         oappend ("DWORD PTR ");
13835       else
13836         oappend ("BYTE PTR ");
13837       break;
13838     case mask_mode:
13839       if (!need_vex)
13840         abort ();
13841       if (vex.w)
13842         oappend ("QWORD PTR ");
13843       else
13844         oappend ("WORD PTR ");
13845       break;
13846     case v_bnd_mode:
13847     case v_bndmk_mode:
13848     default:
13849       break;
13850     }
13851 }
13852
13853 static void
13854 OP_E_register (int bytemode, int sizeflag)
13855 {
13856   int reg = modrm.rm;
13857   const char **names;
13858
13859   USED_REX (REX_B);
13860   if ((rex & REX_B))
13861     reg += 8;
13862
13863   if ((sizeflag & SUFFIX_ALWAYS)
13864       && (bytemode == b_swap_mode
13865           || bytemode == bnd_swap_mode
13866           || bytemode == v_swap_mode))
13867     swap_operand ();
13868
13869   switch (bytemode)
13870     {
13871     case b_mode:
13872     case b_swap_mode:
13873       USED_REX (0);
13874       if (rex)
13875         names = names8rex;
13876       else
13877         names = names8;
13878       break;
13879     case w_mode:
13880       names = names16;
13881       break;
13882     case d_mode:
13883     case dw_mode:
13884     case db_mode:
13885       names = names32;
13886       break;
13887     case q_mode:
13888       names = names64;
13889       break;
13890     case m_mode:
13891     case v_bnd_mode:
13892       names = address_mode == mode_64bit ? names64 : names32;
13893       break;
13894     case bnd_mode:
13895     case bnd_swap_mode:
13896       if (reg > 0x3)
13897         {
13898           oappend ("(bad)");
13899           return;
13900         }
13901       names = names_bnd;
13902       break;
13903     case indir_v_mode:
13904       if (address_mode == mode_64bit && isa64 == intel64)
13905         {
13906           names = names64;
13907           break;
13908         }
13909       /* Fall through.  */
13910     case stack_v_mode:
13911       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13912         {
13913           names = names64;
13914           break;
13915         }
13916       bytemode = v_mode;
13917       /* Fall through.  */
13918     case v_mode:
13919     case v_swap_mode:
13920     case dq_mode:
13921     case dqb_mode:
13922     case dqd_mode:
13923     case dqw_mode:
13924       USED_REX (REX_W);
13925       if (rex & REX_W)
13926         names = names64;
13927       else
13928         {
13929           if ((sizeflag & DFLAG)
13930               || (bytemode != v_mode
13931                   && bytemode != v_swap_mode))
13932             names = names32;
13933           else
13934             names = names16;
13935           used_prefixes |= (prefixes & PREFIX_DATA);
13936         }
13937       break;
13938     case movsxd_mode:
13939       if (!(sizeflag & DFLAG) && isa64 == intel64)
13940         names = names16;
13941       else
13942         names = names32;
13943       used_prefixes |= (prefixes & PREFIX_DATA);
13944       break;
13945     case va_mode:
13946       names = (address_mode == mode_64bit
13947                ? names64 : names32);
13948       if (!(prefixes & PREFIX_ADDR))
13949         names = (address_mode == mode_16bit
13950                      ? names16 : names);
13951       else
13952         {
13953           /* Remove "addr16/addr32".  */
13954           all_prefixes[last_addr_prefix] = 0;
13955           names = (address_mode != mode_32bit
13956                        ? names32 : names16);
13957           used_prefixes |= PREFIX_ADDR;
13958         }
13959       break;
13960     case mask_bd_mode:
13961     case mask_mode:
13962       if (reg > 0x7)
13963         {
13964           oappend ("(bad)");
13965           return;
13966         }
13967       names = names_mask;
13968       break;
13969     case 0:
13970       return;
13971     default:
13972       oappend (INTERNAL_DISASSEMBLER_ERROR);
13973       return;
13974     }
13975   oappend (names[reg]);
13976 }
13977
13978 static void
13979 OP_E_memory (int bytemode, int sizeflag)
13980 {
13981   bfd_vma disp = 0;
13982   int add = (rex & REX_B) ? 8 : 0;
13983   int riprel = 0;
13984   int shift;
13985
13986   if (vex.evex)
13987     {
13988       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13989       if (vex.b
13990           && bytemode != x_mode
13991           && bytemode != xmmq_mode
13992           && bytemode != evex_half_bcst_xmmq_mode)
13993         {
13994           BadOp ();
13995           return;
13996         }
13997       switch (bytemode)
13998         {
13999         case dqw_mode:
14000         case dw_mode:
14001           shift = 1;
14002           break;
14003         case dqb_mode:
14004         case db_mode:
14005           shift = 0;
14006           break;
14007         case dq_mode:
14008           if (address_mode != mode_64bit)
14009             {
14010               shift = 2;
14011               break;
14012             }
14013             /* fall through */
14014         case vex_scalar_w_dq_mode:
14015         case vex_vsib_d_w_dq_mode:
14016         case vex_vsib_d_w_d_mode:
14017         case vex_vsib_q_w_dq_mode:
14018         case vex_vsib_q_w_d_mode:
14019         case evex_x_gscat_mode:
14020           shift = vex.w ? 3 : 2;
14021           break;
14022         case x_mode:
14023         case evex_half_bcst_xmmq_mode:
14024         case xmmq_mode:
14025           if (vex.b)
14026             {
14027               shift = vex.w ? 3 : 2;
14028               break;
14029             }
14030           /* Fall through.  */
14031         case xmmqd_mode:
14032         case xmmdw_mode:
14033         case ymmq_mode:
14034         case evex_x_nobcst_mode:
14035         case x_swap_mode:
14036           switch (vex.length)
14037             {
14038             case 128:
14039               shift = 4;
14040               break;
14041             case 256:
14042               shift = 5;
14043               break;
14044             case 512:
14045               shift = 6;
14046               break;
14047             default:
14048               abort ();
14049             }
14050           break;
14051         case ymm_mode:
14052           shift = 5;
14053           break;
14054         case xmm_mode:
14055           shift = 4;
14056           break;
14057         case xmm_mq_mode:
14058         case q_mode:
14059         case q_scalar_mode:
14060         case q_swap_mode:
14061         case q_scalar_swap_mode:
14062           shift = 3;
14063           break;
14064         case dqd_mode:
14065         case xmm_md_mode:
14066         case d_mode:
14067         case d_scalar_mode:
14068         case d_swap_mode:
14069         case d_scalar_swap_mode:
14070           shift = 2;
14071           break;
14072         case w_scalar_mode:
14073         case xmm_mw_mode:
14074           shift = 1;
14075           break;
14076         case b_scalar_mode:
14077         case xmm_mb_mode:
14078           shift = 0;
14079           break;
14080         default:
14081           abort ();
14082         }
14083       /* Make necessary corrections to shift for modes that need it.
14084          For these modes we currently have shift 4, 5 or 6 depending on
14085          vex.length (it corresponds to xmmword, ymmword or zmmword
14086          operand).  We might want to make it 3, 4 or 5 (e.g. for
14087          xmmq_mode).  In case of broadcast enabled the corrections
14088          aren't needed, as element size is always 32 or 64 bits.  */
14089       if (!vex.b
14090           && (bytemode == xmmq_mode
14091               || bytemode == evex_half_bcst_xmmq_mode))
14092         shift -= 1;
14093       else if (bytemode == xmmqd_mode)
14094         shift -= 2;
14095       else if (bytemode == xmmdw_mode)
14096         shift -= 3;
14097       else if (bytemode == ymmq_mode && vex.length == 128)
14098         shift -= 1;
14099     }
14100   else
14101     shift = 0;
14102
14103   USED_REX (REX_B);
14104   if (intel_syntax)
14105     intel_operand_size (bytemode, sizeflag);
14106   append_seg ();
14107
14108   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14109     {
14110       /* 32/64 bit address mode */
14111       int havedisp;
14112       int havesib;
14113       int havebase;
14114       int haveindex;
14115       int needindex;
14116       int needaddr32;
14117       int base, rbase;
14118       int vindex = 0;
14119       int scale = 0;
14120       int addr32flag = !((sizeflag & AFLAG)
14121                          || bytemode == v_bnd_mode
14122                          || bytemode == v_bndmk_mode
14123                          || bytemode == bnd_mode
14124                          || bytemode == bnd_swap_mode);
14125       const char **indexes64 = names64;
14126       const char **indexes32 = names32;
14127
14128       havesib = 0;
14129       havebase = 1;
14130       haveindex = 0;
14131       base = modrm.rm;
14132
14133       if (base == 4)
14134         {
14135           havesib = 1;
14136           vindex = sib.index;
14137           USED_REX (REX_X);
14138           if (rex & REX_X)
14139             vindex += 8;
14140           switch (bytemode)
14141             {
14142             case vex_vsib_d_w_dq_mode:
14143             case vex_vsib_d_w_d_mode:
14144             case vex_vsib_q_w_dq_mode:
14145             case vex_vsib_q_w_d_mode:
14146               if (!need_vex)
14147                 abort ();
14148               if (vex.evex)
14149                 {
14150                   if (!vex.v)
14151                     vindex += 16;
14152                 }
14153
14154               haveindex = 1;
14155               switch (vex.length)
14156                 {
14157                 case 128:
14158                   indexes64 = indexes32 = names_xmm;
14159                   break;
14160                 case 256:
14161                   if (!vex.w
14162                       || bytemode == vex_vsib_q_w_dq_mode
14163                       || bytemode == vex_vsib_q_w_d_mode)
14164                     indexes64 = indexes32 = names_ymm;
14165                   else
14166                     indexes64 = indexes32 = names_xmm;
14167                   break;
14168                 case 512:
14169                   if (!vex.w
14170                       || bytemode == vex_vsib_q_w_dq_mode
14171                       || bytemode == vex_vsib_q_w_d_mode)
14172                     indexes64 = indexes32 = names_zmm;
14173                   else
14174                     indexes64 = indexes32 = names_ymm;
14175                   break;
14176                 default:
14177                   abort ();
14178                 }
14179               break;
14180             default:
14181               haveindex = vindex != 4;
14182               break;
14183             }
14184           scale = sib.scale;
14185           base = sib.base;
14186           codep++;
14187         }
14188       rbase = base + add;
14189
14190       switch (modrm.mod)
14191         {
14192         case 0:
14193           if (base == 5)
14194             {
14195               havebase = 0;
14196               if (address_mode == mode_64bit && !havesib)
14197                 riprel = 1;
14198               disp = get32s ();
14199               if (riprel && bytemode == v_bndmk_mode)
14200                 {
14201                   oappend ("(bad)");
14202                   return;
14203                 }
14204             }
14205           break;
14206         case 1:
14207           FETCH_DATA (the_info, codep + 1);
14208           disp = *codep++;
14209           if ((disp & 0x80) != 0)
14210             disp -= 0x100;
14211           if (vex.evex && shift > 0)
14212             disp <<= shift;
14213           break;
14214         case 2:
14215           disp = get32s ();
14216           break;
14217         }
14218
14219       needindex = 0;
14220       needaddr32 = 0;
14221       if (havesib
14222           && !havebase
14223           && !haveindex
14224           && address_mode != mode_16bit)
14225         {
14226           if (address_mode == mode_64bit)
14227             {
14228               /* Display eiz instead of addr32.  */
14229               needindex = addr32flag;
14230               needaddr32 = 1;
14231             }
14232           else
14233             {
14234               /* In 32-bit mode, we need index register to tell [offset]
14235                  from [eiz*1 + offset].  */
14236               needindex = 1;
14237             }
14238         }
14239
14240       havedisp = (havebase
14241                   || needindex
14242                   || (havesib && (haveindex || scale != 0)));
14243
14244       if (!intel_syntax)
14245         if (modrm.mod != 0 || base == 5)
14246           {
14247             if (havedisp || riprel)
14248               print_displacement (scratchbuf, disp);
14249             else
14250               print_operand_value (scratchbuf, 1, disp);
14251             oappend (scratchbuf);
14252             if (riprel)
14253               {
14254                 set_op (disp, 1);
14255                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14256               }
14257           }
14258
14259       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14260           && (bytemode != v_bnd_mode)
14261           && (bytemode != v_bndmk_mode)
14262           && (bytemode != bnd_mode)
14263           && (bytemode != bnd_swap_mode))
14264         used_prefixes |= PREFIX_ADDR;
14265
14266       if (havedisp || (intel_syntax && riprel))
14267         {
14268           *obufp++ = open_char;
14269           if (intel_syntax && riprel)
14270             {
14271               set_op (disp, 1);
14272               oappend (!addr32flag ? "rip" : "eip");
14273             }
14274           *obufp = '\0';
14275           if (havebase)
14276             oappend (address_mode == mode_64bit && !addr32flag
14277                      ? names64[rbase] : names32[rbase]);
14278           if (havesib)
14279             {
14280               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14281                  print index to tell base + index from base.  */
14282               if (scale != 0
14283                   || needindex
14284                   || haveindex
14285                   || (havebase && base != ESP_REG_NUM))
14286                 {
14287                   if (!intel_syntax || havebase)
14288                     {
14289                       *obufp++ = separator_char;
14290                       *obufp = '\0';
14291                     }
14292                   if (haveindex)
14293                     oappend (address_mode == mode_64bit && !addr32flag
14294                              ? indexes64[vindex] : indexes32[vindex]);
14295                   else
14296                     oappend (address_mode == mode_64bit && !addr32flag
14297                              ? index64 : index32);
14298
14299                   *obufp++ = scale_char;
14300                   *obufp = '\0';
14301                   sprintf (scratchbuf, "%d", 1 << scale);
14302                   oappend (scratchbuf);
14303                 }
14304             }
14305           if (intel_syntax
14306               && (disp || modrm.mod != 0 || base == 5))
14307             {
14308               if (!havedisp || (bfd_signed_vma) disp >= 0)
14309                 {
14310                   *obufp++ = '+';
14311                   *obufp = '\0';
14312                 }
14313               else if (modrm.mod != 1 && disp != -disp)
14314                 {
14315                   *obufp++ = '-';
14316                   *obufp = '\0';
14317                   disp = - (bfd_signed_vma) disp;
14318                 }
14319
14320               if (havedisp)
14321                 print_displacement (scratchbuf, disp);
14322               else
14323                 print_operand_value (scratchbuf, 1, disp);
14324               oappend (scratchbuf);
14325             }
14326
14327           *obufp++ = close_char;
14328           *obufp = '\0';
14329         }
14330       else if (intel_syntax)
14331         {
14332           if (modrm.mod != 0 || base == 5)
14333             {
14334               if (!active_seg_prefix)
14335                 {
14336                   oappend (names_seg[ds_reg - es_reg]);
14337                   oappend (":");
14338                 }
14339               print_operand_value (scratchbuf, 1, disp);
14340               oappend (scratchbuf);
14341             }
14342         }
14343     }
14344   else
14345     {
14346       /* 16 bit address mode */
14347       used_prefixes |= prefixes & PREFIX_ADDR;
14348       switch (modrm.mod)
14349         {
14350         case 0:
14351           if (modrm.rm == 6)
14352             {
14353               disp = get16 ();
14354               if ((disp & 0x8000) != 0)
14355                 disp -= 0x10000;
14356             }
14357           break;
14358         case 1:
14359           FETCH_DATA (the_info, codep + 1);
14360           disp = *codep++;
14361           if ((disp & 0x80) != 0)
14362             disp -= 0x100;
14363           if (vex.evex && shift > 0)
14364             disp <<= shift;
14365           break;
14366         case 2:
14367           disp = get16 ();
14368           if ((disp & 0x8000) != 0)
14369             disp -= 0x10000;
14370           break;
14371         }
14372
14373       if (!intel_syntax)
14374         if (modrm.mod != 0 || modrm.rm == 6)
14375           {
14376             print_displacement (scratchbuf, disp);
14377             oappend (scratchbuf);
14378           }
14379
14380       if (modrm.mod != 0 || modrm.rm != 6)
14381         {
14382           *obufp++ = open_char;
14383           *obufp = '\0';
14384           oappend (index16[modrm.rm]);
14385           if (intel_syntax
14386               && (disp || modrm.mod != 0 || modrm.rm == 6))
14387             {
14388               if ((bfd_signed_vma) disp >= 0)
14389                 {
14390                   *obufp++ = '+';
14391                   *obufp = '\0';
14392                 }
14393               else if (modrm.mod != 1)
14394                 {
14395                   *obufp++ = '-';
14396                   *obufp = '\0';
14397                   disp = - (bfd_signed_vma) disp;
14398                 }
14399
14400               print_displacement (scratchbuf, disp);
14401               oappend (scratchbuf);
14402             }
14403
14404           *obufp++ = close_char;
14405           *obufp = '\0';
14406         }
14407       else if (intel_syntax)
14408         {
14409           if (!active_seg_prefix)
14410             {
14411               oappend (names_seg[ds_reg - es_reg]);
14412               oappend (":");
14413             }
14414           print_operand_value (scratchbuf, 1, disp & 0xffff);
14415           oappend (scratchbuf);
14416         }
14417     }
14418   if (vex.evex && vex.b
14419       && (bytemode == x_mode
14420           || bytemode == xmmq_mode
14421           || bytemode == evex_half_bcst_xmmq_mode))
14422     {
14423       if (vex.w
14424           || bytemode == xmmq_mode
14425           || bytemode == evex_half_bcst_xmmq_mode)
14426         {
14427           switch (vex.length)
14428             {
14429             case 128:
14430               oappend ("{1to2}");
14431               break;
14432             case 256:
14433               oappend ("{1to4}");
14434               break;
14435             case 512:
14436               oappend ("{1to8}");
14437               break;
14438             default:
14439               abort ();
14440             }
14441         }
14442       else
14443         {
14444           switch (vex.length)
14445             {
14446             case 128:
14447               oappend ("{1to4}");
14448               break;
14449             case 256:
14450               oappend ("{1to8}");
14451               break;
14452             case 512:
14453               oappend ("{1to16}");
14454               break;
14455             default:
14456               abort ();
14457             }
14458         }
14459     }
14460 }
14461
14462 static void
14463 OP_E (int bytemode, int sizeflag)
14464 {
14465   /* Skip mod/rm byte.  */
14466   MODRM_CHECK;
14467   codep++;
14468
14469   if (modrm.mod == 3)
14470     OP_E_register (bytemode, sizeflag);
14471   else
14472     OP_E_memory (bytemode, sizeflag);
14473 }
14474
14475 static void
14476 OP_G (int bytemode, int sizeflag)
14477 {
14478   int add = 0;
14479   const char **names;
14480   USED_REX (REX_R);
14481   if (rex & REX_R)
14482     add += 8;
14483   switch (bytemode)
14484     {
14485     case b_mode:
14486       USED_REX (0);
14487       if (rex)
14488         oappend (names8rex[modrm.reg + add]);
14489       else
14490         oappend (names8[modrm.reg + add]);
14491       break;
14492     case w_mode:
14493       oappend (names16[modrm.reg + add]);
14494       break;
14495     case d_mode:
14496     case db_mode:
14497     case dw_mode:
14498       oappend (names32[modrm.reg + add]);
14499       break;
14500     case q_mode:
14501       oappend (names64[modrm.reg + add]);
14502       break;
14503     case bnd_mode:
14504       if (modrm.reg > 0x3)
14505         {
14506           oappend ("(bad)");
14507           return;
14508         }
14509       oappend (names_bnd[modrm.reg]);
14510       break;
14511     case v_mode:
14512     case dq_mode:
14513     case dqb_mode:
14514     case dqd_mode:
14515     case dqw_mode:
14516     case movsxd_mode:
14517       USED_REX (REX_W);
14518       if (rex & REX_W)
14519         oappend (names64[modrm.reg + add]);
14520       else
14521         {
14522           if ((sizeflag & DFLAG)
14523               || (bytemode != v_mode && bytemode != movsxd_mode))
14524             oappend (names32[modrm.reg + add]);
14525           else
14526             oappend (names16[modrm.reg + add]);
14527           used_prefixes |= (prefixes & PREFIX_DATA);
14528         }
14529       break;
14530     case va_mode:
14531       names = (address_mode == mode_64bit
14532                ? names64 : names32);
14533       if (!(prefixes & PREFIX_ADDR))
14534         {
14535           if (address_mode == mode_16bit)
14536             names = names16;
14537         }
14538       else
14539         {
14540           /* Remove "addr16/addr32".  */
14541           all_prefixes[last_addr_prefix] = 0;
14542           names = (address_mode != mode_32bit
14543                        ? names32 : names16);
14544           used_prefixes |= PREFIX_ADDR;
14545         }
14546       oappend (names[modrm.reg + add]);
14547       break;
14548     case m_mode:
14549       if (address_mode == mode_64bit)
14550         oappend (names64[modrm.reg + add]);
14551       else
14552         oappend (names32[modrm.reg + add]);
14553       break;
14554     case mask_bd_mode:
14555     case mask_mode:
14556       if ((modrm.reg + add) > 0x7)
14557         {
14558           oappend ("(bad)");
14559           return;
14560         }
14561       oappend (names_mask[modrm.reg + add]);
14562       break;
14563     default:
14564       oappend (INTERNAL_DISASSEMBLER_ERROR);
14565       break;
14566     }
14567 }
14568
14569 static bfd_vma
14570 get64 (void)
14571 {
14572   bfd_vma x;
14573 #ifdef BFD64
14574   unsigned int a;
14575   unsigned int b;
14576
14577   FETCH_DATA (the_info, codep + 8);
14578   a = *codep++ & 0xff;
14579   a |= (*codep++ & 0xff) << 8;
14580   a |= (*codep++ & 0xff) << 16;
14581   a |= (*codep++ & 0xffu) << 24;
14582   b = *codep++ & 0xff;
14583   b |= (*codep++ & 0xff) << 8;
14584   b |= (*codep++ & 0xff) << 16;
14585   b |= (*codep++ & 0xffu) << 24;
14586   x = a + ((bfd_vma) b << 32);
14587 #else
14588   abort ();
14589   x = 0;
14590 #endif
14591   return x;
14592 }
14593
14594 static bfd_signed_vma
14595 get32 (void)
14596 {
14597   bfd_signed_vma x = 0;
14598
14599   FETCH_DATA (the_info, codep + 4);
14600   x = *codep++ & (bfd_signed_vma) 0xff;
14601   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14602   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14603   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14604   return x;
14605 }
14606
14607 static bfd_signed_vma
14608 get32s (void)
14609 {
14610   bfd_signed_vma x = 0;
14611
14612   FETCH_DATA (the_info, codep + 4);
14613   x = *codep++ & (bfd_signed_vma) 0xff;
14614   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14615   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14616   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14617
14618   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14619
14620   return x;
14621 }
14622
14623 static int
14624 get16 (void)
14625 {
14626   int x = 0;
14627
14628   FETCH_DATA (the_info, codep + 2);
14629   x = *codep++ & 0xff;
14630   x |= (*codep++ & 0xff) << 8;
14631   return x;
14632 }
14633
14634 static void
14635 set_op (bfd_vma op, int riprel)
14636 {
14637   op_index[op_ad] = op_ad;
14638   if (address_mode == mode_64bit)
14639     {
14640       op_address[op_ad] = op;
14641       op_riprel[op_ad] = riprel;
14642     }
14643   else
14644     {
14645       /* Mask to get a 32-bit address.  */
14646       op_address[op_ad] = op & 0xffffffff;
14647       op_riprel[op_ad] = riprel & 0xffffffff;
14648     }
14649 }
14650
14651 static void
14652 OP_REG (int code, int sizeflag)
14653 {
14654   const char *s;
14655   int add;
14656
14657   switch (code)
14658     {
14659     case es_reg: case ss_reg: case cs_reg:
14660     case ds_reg: case fs_reg: case gs_reg:
14661       oappend (names_seg[code - es_reg]);
14662       return;
14663     }
14664
14665   USED_REX (REX_B);
14666   if (rex & REX_B)
14667     add = 8;
14668   else
14669     add = 0;
14670
14671   switch (code)
14672     {
14673     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14674     case sp_reg: case bp_reg: case si_reg: case di_reg:
14675       s = names16[code - ax_reg + add];
14676       break;
14677     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14678     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14679       USED_REX (0);
14680       if (rex)
14681         s = names8rex[code - al_reg + add];
14682       else
14683         s = names8[code - al_reg];
14684       break;
14685     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14686     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14687       if (address_mode == mode_64bit
14688           && ((sizeflag & DFLAG) || (rex & REX_W)))
14689         {
14690           s = names64[code - rAX_reg + add];
14691           break;
14692         }
14693       code += eAX_reg - rAX_reg;
14694       /* Fall through.  */
14695     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14696     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14697       USED_REX (REX_W);
14698       if (rex & REX_W)
14699         s = names64[code - eAX_reg + add];
14700       else
14701         {
14702           if (sizeflag & DFLAG)
14703             s = names32[code - eAX_reg + add];
14704           else
14705             s = names16[code - eAX_reg + add];
14706           used_prefixes |= (prefixes & PREFIX_DATA);
14707         }
14708       break;
14709     default:
14710       s = INTERNAL_DISASSEMBLER_ERROR;
14711       break;
14712     }
14713   oappend (s);
14714 }
14715
14716 static void
14717 OP_IMREG (int code, int sizeflag)
14718 {
14719   const char *s;
14720
14721   switch (code)
14722     {
14723     case indir_dx_reg:
14724       if (intel_syntax)
14725         s = "dx";
14726       else
14727         s = "(%dx)";
14728       break;
14729     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14730     case sp_reg: case bp_reg: case si_reg: case di_reg:
14731       s = names16[code - ax_reg];
14732       break;
14733     case es_reg: case ss_reg: case cs_reg:
14734     case ds_reg: case fs_reg: case gs_reg:
14735       s = names_seg[code - es_reg];
14736       break;
14737     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14738     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14739       USED_REX (0);
14740       if (rex)
14741         s = names8rex[code - al_reg];
14742       else
14743         s = names8[code - al_reg];
14744       break;
14745     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14746     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14747       USED_REX (REX_W);
14748       if (rex & REX_W)
14749         s = names64[code - eAX_reg];
14750       else
14751         {
14752           if (sizeflag & DFLAG)
14753             s = names32[code - eAX_reg];
14754           else
14755             s = names16[code - eAX_reg];
14756           used_prefixes |= (prefixes & PREFIX_DATA);
14757         }
14758       break;
14759     case z_mode_ax_reg:
14760       if ((rex & REX_W) || (sizeflag & DFLAG))
14761         s = *names32;
14762       else
14763         s = *names16;
14764       if (!(rex & REX_W))
14765         used_prefixes |= (prefixes & PREFIX_DATA);
14766       break;
14767     default:
14768       s = INTERNAL_DISASSEMBLER_ERROR;
14769       break;
14770     }
14771   oappend (s);
14772 }
14773
14774 static void
14775 OP_I (int bytemode, int sizeflag)
14776 {
14777   bfd_signed_vma op;
14778   bfd_signed_vma mask = -1;
14779
14780   switch (bytemode)
14781     {
14782     case b_mode:
14783       FETCH_DATA (the_info, codep + 1);
14784       op = *codep++;
14785       mask = 0xff;
14786       break;
14787     case v_mode:
14788       USED_REX (REX_W);
14789       if (rex & REX_W)
14790         op = get32s ();
14791       else
14792         {
14793           if (sizeflag & DFLAG)
14794             {
14795               op = get32 ();
14796               mask = 0xffffffff;
14797             }
14798           else
14799             {
14800               op = get16 ();
14801               mask = 0xfffff;
14802             }
14803           used_prefixes |= (prefixes & PREFIX_DATA);
14804         }
14805       break;
14806     case d_mode:
14807       mask = 0xffffffff;
14808       op = get32 ();
14809       break;
14810     case w_mode:
14811       mask = 0xfffff;
14812       op = get16 ();
14813       break;
14814     case const_1_mode:
14815       if (intel_syntax)
14816         oappend ("1");
14817       return;
14818     default:
14819       oappend (INTERNAL_DISASSEMBLER_ERROR);
14820       return;
14821     }
14822
14823   op &= mask;
14824   scratchbuf[0] = '$';
14825   print_operand_value (scratchbuf + 1, 1, op);
14826   oappend_maybe_intel (scratchbuf);
14827   scratchbuf[0] = '\0';
14828 }
14829
14830 static void
14831 OP_I64 (int bytemode, int sizeflag)
14832 {
14833   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14834     {
14835       OP_I (bytemode, sizeflag);
14836       return;
14837     }
14838
14839   USED_REX (REX_W);
14840
14841   scratchbuf[0] = '$';
14842   print_operand_value (scratchbuf + 1, 1, get64 ());
14843   oappend_maybe_intel (scratchbuf);
14844   scratchbuf[0] = '\0';
14845 }
14846
14847 static void
14848 OP_sI (int bytemode, int sizeflag)
14849 {
14850   bfd_signed_vma op;
14851
14852   switch (bytemode)
14853     {
14854     case b_mode:
14855     case b_T_mode:
14856       FETCH_DATA (the_info, codep + 1);
14857       op = *codep++;
14858       if ((op & 0x80) != 0)
14859         op -= 0x100;
14860       if (bytemode == b_T_mode)
14861         {
14862           if (address_mode != mode_64bit
14863               || !((sizeflag & DFLAG) || (rex & REX_W)))
14864             {
14865               /* The operand-size prefix is overridden by a REX prefix.  */
14866               if ((sizeflag & DFLAG) || (rex & REX_W))
14867                 op &= 0xffffffff;
14868               else
14869                 op &= 0xffff;
14870           }
14871         }
14872       else
14873         {
14874           if (!(rex & REX_W))
14875             {
14876               if (sizeflag & DFLAG)
14877                 op &= 0xffffffff;
14878               else
14879                 op &= 0xffff;
14880             }
14881         }
14882       break;
14883     case v_mode:
14884       /* The operand-size prefix is overridden by a REX prefix.  */
14885       if ((sizeflag & DFLAG) || (rex & REX_W))
14886         op = get32s ();
14887       else
14888         op = get16 ();
14889       break;
14890     default:
14891       oappend (INTERNAL_DISASSEMBLER_ERROR);
14892       return;
14893     }
14894
14895   scratchbuf[0] = '$';
14896   print_operand_value (scratchbuf + 1, 1, op);
14897   oappend_maybe_intel (scratchbuf);
14898 }
14899
14900 static void
14901 OP_J (int bytemode, int sizeflag)
14902 {
14903   bfd_vma disp;
14904   bfd_vma mask = -1;
14905   bfd_vma segment = 0;
14906
14907   switch (bytemode)
14908     {
14909     case b_mode:
14910       FETCH_DATA (the_info, codep + 1);
14911       disp = *codep++;
14912       if ((disp & 0x80) != 0)
14913         disp -= 0x100;
14914       break;
14915     case v_mode:
14916       if (isa64 != intel64)
14917     case dqw_mode:
14918         USED_REX (REX_W);
14919       if ((sizeflag & DFLAG)
14920           || (address_mode == mode_64bit
14921               && ((isa64 == intel64 && bytemode != dqw_mode)
14922                   || (rex & REX_W))))
14923         disp = get32s ();
14924       else
14925         {
14926           disp = get16 ();
14927           if ((disp & 0x8000) != 0)
14928             disp -= 0x10000;
14929           /* In 16bit mode, address is wrapped around at 64k within
14930              the same segment.  Otherwise, a data16 prefix on a jump
14931              instruction means that the pc is masked to 16 bits after
14932              the displacement is added!  */
14933           mask = 0xffff;
14934           if ((prefixes & PREFIX_DATA) == 0)
14935             segment = ((start_pc + (codep - start_codep))
14936                        & ~((bfd_vma) 0xffff));
14937         }
14938       if (address_mode != mode_64bit
14939           || (isa64 != intel64 && !(rex & REX_W)))
14940         used_prefixes |= (prefixes & PREFIX_DATA);
14941       break;
14942     default:
14943       oappend (INTERNAL_DISASSEMBLER_ERROR);
14944       return;
14945     }
14946   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14947   set_op (disp, 0);
14948   print_operand_value (scratchbuf, 1, disp);
14949   oappend (scratchbuf);
14950 }
14951
14952 static void
14953 OP_SEG (int bytemode, int sizeflag)
14954 {
14955   if (bytemode == w_mode)
14956     oappend (names_seg[modrm.reg]);
14957   else
14958     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14959 }
14960
14961 static void
14962 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14963 {
14964   int seg, offset;
14965
14966   if (sizeflag & DFLAG)
14967     {
14968       offset = get32 ();
14969       seg = get16 ();
14970     }
14971   else
14972     {
14973       offset = get16 ();
14974       seg = get16 ();
14975     }
14976   used_prefixes |= (prefixes & PREFIX_DATA);
14977   if (intel_syntax)
14978     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14979   else
14980     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14981   oappend (scratchbuf);
14982 }
14983
14984 static void
14985 OP_OFF (int bytemode, int sizeflag)
14986 {
14987   bfd_vma off;
14988
14989   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14990     intel_operand_size (bytemode, sizeflag);
14991   append_seg ();
14992
14993   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14994     off = get32 ();
14995   else
14996     off = get16 ();
14997
14998   if (intel_syntax)
14999     {
15000       if (!active_seg_prefix)
15001         {
15002           oappend (names_seg[ds_reg - es_reg]);
15003           oappend (":");
15004         }
15005     }
15006   print_operand_value (scratchbuf, 1, off);
15007   oappend (scratchbuf);
15008 }
15009
15010 static void
15011 OP_OFF64 (int bytemode, int sizeflag)
15012 {
15013   bfd_vma off;
15014
15015   if (address_mode != mode_64bit
15016       || (prefixes & PREFIX_ADDR))
15017     {
15018       OP_OFF (bytemode, sizeflag);
15019       return;
15020     }
15021
15022   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15023     intel_operand_size (bytemode, sizeflag);
15024   append_seg ();
15025
15026   off = get64 ();
15027
15028   if (intel_syntax)
15029     {
15030       if (!active_seg_prefix)
15031         {
15032           oappend (names_seg[ds_reg - es_reg]);
15033           oappend (":");
15034         }
15035     }
15036   print_operand_value (scratchbuf, 1, off);
15037   oappend (scratchbuf);
15038 }
15039
15040 static void
15041 ptr_reg (int code, int sizeflag)
15042 {
15043   const char *s;
15044
15045   *obufp++ = open_char;
15046   used_prefixes |= (prefixes & PREFIX_ADDR);
15047   if (address_mode == mode_64bit)
15048     {
15049       if (!(sizeflag & AFLAG))
15050         s = names32[code - eAX_reg];
15051       else
15052         s = names64[code - eAX_reg];
15053     }
15054   else if (sizeflag & AFLAG)
15055     s = names32[code - eAX_reg];
15056   else
15057     s = names16[code - eAX_reg];
15058   oappend (s);
15059   *obufp++ = close_char;
15060   *obufp = 0;
15061 }
15062
15063 static void
15064 OP_ESreg (int code, int sizeflag)
15065 {
15066   if (intel_syntax)
15067     {
15068       switch (codep[-1])
15069         {
15070         case 0x6d:      /* insw/insl */
15071           intel_operand_size (z_mode, sizeflag);
15072           break;
15073         case 0xa5:      /* movsw/movsl/movsq */
15074         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15075         case 0xab:      /* stosw/stosl */
15076         case 0xaf:      /* scasw/scasl */
15077           intel_operand_size (v_mode, sizeflag);
15078           break;
15079         default:
15080           intel_operand_size (b_mode, sizeflag);
15081         }
15082     }
15083   oappend_maybe_intel ("%es:");
15084   ptr_reg (code, sizeflag);
15085 }
15086
15087 static void
15088 OP_DSreg (int code, int sizeflag)
15089 {
15090   if (intel_syntax)
15091     {
15092       switch (codep[-1])
15093         {
15094         case 0x6f:      /* outsw/outsl */
15095           intel_operand_size (z_mode, sizeflag);
15096           break;
15097         case 0xa5:      /* movsw/movsl/movsq */
15098         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15099         case 0xad:      /* lodsw/lodsl/lodsq */
15100           intel_operand_size (v_mode, sizeflag);
15101           break;
15102         default:
15103           intel_operand_size (b_mode, sizeflag);
15104         }
15105     }
15106   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15107      default segment register DS is printed.  */
15108   if (!active_seg_prefix)
15109     active_seg_prefix = PREFIX_DS;
15110   append_seg ();
15111   ptr_reg (code, sizeflag);
15112 }
15113
15114 static void
15115 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15116 {
15117   int add;
15118   if (rex & REX_R)
15119     {
15120       USED_REX (REX_R);
15121       add = 8;
15122     }
15123   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15124     {
15125       all_prefixes[last_lock_prefix] = 0;
15126       used_prefixes |= PREFIX_LOCK;
15127       add = 8;
15128     }
15129   else
15130     add = 0;
15131   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15132   oappend_maybe_intel (scratchbuf);
15133 }
15134
15135 static void
15136 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15137 {
15138   int add;
15139   USED_REX (REX_R);
15140   if (rex & REX_R)
15141     add = 8;
15142   else
15143     add = 0;
15144   if (intel_syntax)
15145     sprintf (scratchbuf, "db%d", modrm.reg + add);
15146   else
15147     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15148   oappend (scratchbuf);
15149 }
15150
15151 static void
15152 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15153 {
15154   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15155   oappend_maybe_intel (scratchbuf);
15156 }
15157
15158 static void
15159 OP_R (int bytemode, int sizeflag)
15160 {
15161   /* Skip mod/rm byte.  */
15162   MODRM_CHECK;
15163   codep++;
15164   OP_E_register (bytemode, sizeflag);
15165 }
15166
15167 static void
15168 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15169 {
15170   int reg = modrm.reg;
15171   const char **names;
15172
15173   used_prefixes |= (prefixes & PREFIX_DATA);
15174   if (prefixes & PREFIX_DATA)
15175     {
15176       names = names_xmm;
15177       USED_REX (REX_R);
15178       if (rex & REX_R)
15179         reg += 8;
15180     }
15181   else
15182     names = names_mm;
15183   oappend (names[reg]);
15184 }
15185
15186 static void
15187 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15188 {
15189   int reg = modrm.reg;
15190   const char **names;
15191
15192   USED_REX (REX_R);
15193   if (rex & REX_R)
15194     reg += 8;
15195   if (vex.evex)
15196     {
15197       if (!vex.r)
15198         reg += 16;
15199     }
15200
15201   if (need_vex
15202       && bytemode != xmm_mode
15203       && bytemode != xmmq_mode
15204       && bytemode != evex_half_bcst_xmmq_mode
15205       && bytemode != ymm_mode
15206       && bytemode != scalar_mode)
15207     {
15208       switch (vex.length)
15209         {
15210         case 128:
15211           names = names_xmm;
15212           break;
15213         case 256:
15214           if (vex.w
15215               || (bytemode != vex_vsib_q_w_dq_mode
15216                   && bytemode != vex_vsib_q_w_d_mode))
15217             names = names_ymm;
15218           else
15219             names = names_xmm;
15220           break;
15221         case 512:
15222           names = names_zmm;
15223           break;
15224         default:
15225           abort ();
15226         }
15227     }
15228   else if (bytemode == xmmq_mode
15229            || bytemode == evex_half_bcst_xmmq_mode)
15230     {
15231       switch (vex.length)
15232         {
15233         case 128:
15234         case 256:
15235           names = names_xmm;
15236           break;
15237         case 512:
15238           names = names_ymm;
15239           break;
15240         default:
15241           abort ();
15242         }
15243     }
15244   else if (bytemode == ymm_mode)
15245     names = names_ymm;
15246   else
15247     names = names_xmm;
15248   oappend (names[reg]);
15249 }
15250
15251 static void
15252 OP_EM (int bytemode, int sizeflag)
15253 {
15254   int reg;
15255   const char **names;
15256
15257   if (modrm.mod != 3)
15258     {
15259       if (intel_syntax
15260           && (bytemode == v_mode || bytemode == v_swap_mode))
15261         {
15262           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15263           used_prefixes |= (prefixes & PREFIX_DATA);
15264         }
15265       OP_E (bytemode, sizeflag);
15266       return;
15267     }
15268
15269   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15270     swap_operand ();
15271
15272   /* Skip mod/rm byte.  */
15273   MODRM_CHECK;
15274   codep++;
15275   used_prefixes |= (prefixes & PREFIX_DATA);
15276   reg = modrm.rm;
15277   if (prefixes & PREFIX_DATA)
15278     {
15279       names = names_xmm;
15280       USED_REX (REX_B);
15281       if (rex & REX_B)
15282         reg += 8;
15283     }
15284   else
15285     names = names_mm;
15286   oappend (names[reg]);
15287 }
15288
15289 /* cvt* are the only instructions in sse2 which have
15290    both SSE and MMX operands and also have 0x66 prefix
15291    in their opcode. 0x66 was originally used to differentiate
15292    between SSE and MMX instruction(operands). So we have to handle the
15293    cvt* separately using OP_EMC and OP_MXC */
15294 static void
15295 OP_EMC (int bytemode, int sizeflag)
15296 {
15297   if (modrm.mod != 3)
15298     {
15299       if (intel_syntax && bytemode == v_mode)
15300         {
15301           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15302           used_prefixes |= (prefixes & PREFIX_DATA);
15303         }
15304       OP_E (bytemode, sizeflag);
15305       return;
15306     }
15307
15308   /* Skip mod/rm byte.  */
15309   MODRM_CHECK;
15310   codep++;
15311   used_prefixes |= (prefixes & PREFIX_DATA);
15312   oappend (names_mm[modrm.rm]);
15313 }
15314
15315 static void
15316 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15317 {
15318   used_prefixes |= (prefixes & PREFIX_DATA);
15319   oappend (names_mm[modrm.reg]);
15320 }
15321
15322 static void
15323 OP_EX (int bytemode, int sizeflag)
15324 {
15325   int reg;
15326   const char **names;
15327
15328   /* Skip mod/rm byte.  */
15329   MODRM_CHECK;
15330   codep++;
15331
15332   if (modrm.mod != 3)
15333     {
15334       OP_E_memory (bytemode, sizeflag);
15335       return;
15336     }
15337
15338   reg = modrm.rm;
15339   USED_REX (REX_B);
15340   if (rex & REX_B)
15341     reg += 8;
15342   if (vex.evex)
15343     {
15344       USED_REX (REX_X);
15345       if ((rex & REX_X))
15346         reg += 16;
15347     }
15348
15349   if ((sizeflag & SUFFIX_ALWAYS)
15350       && (bytemode == x_swap_mode
15351           || bytemode == d_swap_mode
15352           || bytemode == d_scalar_swap_mode
15353           || bytemode == q_swap_mode
15354           || bytemode == q_scalar_swap_mode))
15355     swap_operand ();
15356
15357   if (need_vex
15358       && bytemode != xmm_mode
15359       && bytemode != xmmdw_mode
15360       && bytemode != xmmqd_mode
15361       && bytemode != xmm_mb_mode
15362       && bytemode != xmm_mw_mode
15363       && bytemode != xmm_md_mode
15364       && bytemode != xmm_mq_mode
15365       && bytemode != xmmq_mode
15366       && bytemode != evex_half_bcst_xmmq_mode
15367       && bytemode != ymm_mode
15368       && bytemode != d_scalar_mode
15369       && bytemode != d_scalar_swap_mode
15370       && bytemode != q_scalar_mode
15371       && bytemode != q_scalar_swap_mode
15372       && bytemode != vex_scalar_w_dq_mode)
15373     {
15374       switch (vex.length)
15375         {
15376         case 128:
15377           names = names_xmm;
15378           break;
15379         case 256:
15380           names = names_ymm;
15381           break;
15382         case 512:
15383           names = names_zmm;
15384           break;
15385         default:
15386           abort ();
15387         }
15388     }
15389   else if (bytemode == xmmq_mode
15390            || bytemode == evex_half_bcst_xmmq_mode)
15391     {
15392       switch (vex.length)
15393         {
15394         case 128:
15395         case 256:
15396           names = names_xmm;
15397           break;
15398         case 512:
15399           names = names_ymm;
15400           break;
15401         default:
15402           abort ();
15403         }
15404     }
15405   else if (bytemode == ymm_mode)
15406     names = names_ymm;
15407   else
15408     names = names_xmm;
15409   oappend (names[reg]);
15410 }
15411
15412 static void
15413 OP_MS (int bytemode, int sizeflag)
15414 {
15415   if (modrm.mod == 3)
15416     OP_EM (bytemode, sizeflag);
15417   else
15418     BadOp ();
15419 }
15420
15421 static void
15422 OP_XS (int bytemode, int sizeflag)
15423 {
15424   if (modrm.mod == 3)
15425     OP_EX (bytemode, sizeflag);
15426   else
15427     BadOp ();
15428 }
15429
15430 static void
15431 OP_M (int bytemode, int sizeflag)
15432 {
15433   if (modrm.mod == 3)
15434     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15435     BadOp ();
15436   else
15437     OP_E (bytemode, sizeflag);
15438 }
15439
15440 static void
15441 OP_0f07 (int bytemode, int sizeflag)
15442 {
15443   if (modrm.mod != 3 || modrm.rm != 0)
15444     BadOp ();
15445   else
15446     OP_E (bytemode, sizeflag);
15447 }
15448
15449 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15450    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15451
15452 static void
15453 NOP_Fixup1 (int bytemode, int sizeflag)
15454 {
15455   if ((prefixes & PREFIX_DATA) != 0
15456       || (rex != 0
15457           && rex != 0x48
15458           && address_mode == mode_64bit))
15459     OP_REG (bytemode, sizeflag);
15460   else
15461     strcpy (obuf, "nop");
15462 }
15463
15464 static void
15465 NOP_Fixup2 (int bytemode, int sizeflag)
15466 {
15467   if ((prefixes & PREFIX_DATA) != 0
15468       || (rex != 0
15469           && rex != 0x48
15470           && address_mode == mode_64bit))
15471     OP_IMREG (bytemode, sizeflag);
15472 }
15473
15474 static const char *const Suffix3DNow[] = {
15475 /* 00 */        NULL,           NULL,           NULL,           NULL,
15476 /* 04 */        NULL,           NULL,           NULL,           NULL,
15477 /* 08 */        NULL,           NULL,           NULL,           NULL,
15478 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15479 /* 10 */        NULL,           NULL,           NULL,           NULL,
15480 /* 14 */        NULL,           NULL,           NULL,           NULL,
15481 /* 18 */        NULL,           NULL,           NULL,           NULL,
15482 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15483 /* 20 */        NULL,           NULL,           NULL,           NULL,
15484 /* 24 */        NULL,           NULL,           NULL,           NULL,
15485 /* 28 */        NULL,           NULL,           NULL,           NULL,
15486 /* 2C */        NULL,           NULL,           NULL,           NULL,
15487 /* 30 */        NULL,           NULL,           NULL,           NULL,
15488 /* 34 */        NULL,           NULL,           NULL,           NULL,
15489 /* 38 */        NULL,           NULL,           NULL,           NULL,
15490 /* 3C */        NULL,           NULL,           NULL,           NULL,
15491 /* 40 */        NULL,           NULL,           NULL,           NULL,
15492 /* 44 */        NULL,           NULL,           NULL,           NULL,
15493 /* 48 */        NULL,           NULL,           NULL,           NULL,
15494 /* 4C */        NULL,           NULL,           NULL,           NULL,
15495 /* 50 */        NULL,           NULL,           NULL,           NULL,
15496 /* 54 */        NULL,           NULL,           NULL,           NULL,
15497 /* 58 */        NULL,           NULL,           NULL,           NULL,
15498 /* 5C */        NULL,           NULL,           NULL,           NULL,
15499 /* 60 */        NULL,           NULL,           NULL,           NULL,
15500 /* 64 */        NULL,           NULL,           NULL,           NULL,
15501 /* 68 */        NULL,           NULL,           NULL,           NULL,
15502 /* 6C */        NULL,           NULL,           NULL,           NULL,
15503 /* 70 */        NULL,           NULL,           NULL,           NULL,
15504 /* 74 */        NULL,           NULL,           NULL,           NULL,
15505 /* 78 */        NULL,           NULL,           NULL,           NULL,
15506 /* 7C */        NULL,           NULL,           NULL,           NULL,
15507 /* 80 */        NULL,           NULL,           NULL,           NULL,
15508 /* 84 */        NULL,           NULL,           NULL,           NULL,
15509 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15510 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15511 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15512 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15513 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15514 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15515 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15516 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15517 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15518 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15519 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15520 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15521 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15522 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15523 /* C0 */        NULL,           NULL,           NULL,           NULL,
15524 /* C4 */        NULL,           NULL,           NULL,           NULL,
15525 /* C8 */        NULL,           NULL,           NULL,           NULL,
15526 /* CC */        NULL,           NULL,           NULL,           NULL,
15527 /* D0 */        NULL,           NULL,           NULL,           NULL,
15528 /* D4 */        NULL,           NULL,           NULL,           NULL,
15529 /* D8 */        NULL,           NULL,           NULL,           NULL,
15530 /* DC */        NULL,           NULL,           NULL,           NULL,
15531 /* E0 */        NULL,           NULL,           NULL,           NULL,
15532 /* E4 */        NULL,           NULL,           NULL,           NULL,
15533 /* E8 */        NULL,           NULL,           NULL,           NULL,
15534 /* EC */        NULL,           NULL,           NULL,           NULL,
15535 /* F0 */        NULL,           NULL,           NULL,           NULL,
15536 /* F4 */        NULL,           NULL,           NULL,           NULL,
15537 /* F8 */        NULL,           NULL,           NULL,           NULL,
15538 /* FC */        NULL,           NULL,           NULL,           NULL,
15539 };
15540
15541 static void
15542 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15543 {
15544   const char *mnemonic;
15545
15546   FETCH_DATA (the_info, codep + 1);
15547   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15548      place where an 8-bit immediate would normally go.  ie. the last
15549      byte of the instruction.  */
15550   obufp = mnemonicendp;
15551   mnemonic = Suffix3DNow[*codep++ & 0xff];
15552   if (mnemonic)
15553     oappend (mnemonic);
15554   else
15555     {
15556       /* Since a variable sized modrm/sib chunk is between the start
15557          of the opcode (0x0f0f) and the opcode suffix, we need to do
15558          all the modrm processing first, and don't know until now that
15559          we have a bad opcode.  This necessitates some cleaning up.  */
15560       op_out[0][0] = '\0';
15561       op_out[1][0] = '\0';
15562       BadOp ();
15563     }
15564   mnemonicendp = obufp;
15565 }
15566
15567 static struct op simd_cmp_op[] =
15568 {
15569   { STRING_COMMA_LEN ("eq") },
15570   { STRING_COMMA_LEN ("lt") },
15571   { STRING_COMMA_LEN ("le") },
15572   { STRING_COMMA_LEN ("unord") },
15573   { STRING_COMMA_LEN ("neq") },
15574   { STRING_COMMA_LEN ("nlt") },
15575   { STRING_COMMA_LEN ("nle") },
15576   { STRING_COMMA_LEN ("ord") }
15577 };
15578
15579 static void
15580 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15581 {
15582   unsigned int cmp_type;
15583
15584   FETCH_DATA (the_info, codep + 1);
15585   cmp_type = *codep++ & 0xff;
15586   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15587     {
15588       char suffix [3];
15589       char *p = mnemonicendp - 2;
15590       suffix[0] = p[0];
15591       suffix[1] = p[1];
15592       suffix[2] = '\0';
15593       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15594       mnemonicendp += simd_cmp_op[cmp_type].len;
15595     }
15596   else
15597     {
15598       /* We have a reserved extension byte.  Output it directly.  */
15599       scratchbuf[0] = '$';
15600       print_operand_value (scratchbuf + 1, 1, cmp_type);
15601       oappend_maybe_intel (scratchbuf);
15602       scratchbuf[0] = '\0';
15603     }
15604 }
15605
15606 static void
15607 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15608 {
15609   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15610   if (!intel_syntax)
15611     {
15612       strcpy (op_out[0], names32[0]);
15613       strcpy (op_out[1], names32[1]);
15614       if (bytemode == eBX_reg)
15615         strcpy (op_out[2], names32[3]);
15616       two_source_ops = 1;
15617     }
15618   /* Skip mod/rm byte.  */
15619   MODRM_CHECK;
15620   codep++;
15621 }
15622
15623 static void
15624 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15625             int sizeflag ATTRIBUTE_UNUSED)
15626 {
15627   /* monitor %{e,r,}ax,%ecx,%edx"  */
15628   if (!intel_syntax)
15629     {
15630       const char **names = (address_mode == mode_64bit
15631                             ? names64 : names32);
15632
15633       if (prefixes & PREFIX_ADDR)
15634         {
15635           /* Remove "addr16/addr32".  */
15636           all_prefixes[last_addr_prefix] = 0;
15637           names = (address_mode != mode_32bit
15638                    ? names32 : names16);
15639           used_prefixes |= PREFIX_ADDR;
15640         }
15641       else if (address_mode == mode_16bit)
15642         names = names16;
15643       strcpy (op_out[0], names[0]);
15644       strcpy (op_out[1], names32[1]);
15645       strcpy (op_out[2], names32[2]);
15646       two_source_ops = 1;
15647     }
15648   /* Skip mod/rm byte.  */
15649   MODRM_CHECK;
15650   codep++;
15651 }
15652
15653 static void
15654 BadOp (void)
15655 {
15656   /* Throw away prefixes and 1st. opcode byte.  */
15657   codep = insn_codep + 1;
15658   oappend ("(bad)");
15659 }
15660
15661 static void
15662 REP_Fixup (int bytemode, int sizeflag)
15663 {
15664   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15665      lods and stos.  */
15666   if (prefixes & PREFIX_REPZ)
15667     all_prefixes[last_repz_prefix] = REP_PREFIX;
15668
15669   switch (bytemode)
15670     {
15671     case al_reg:
15672     case eAX_reg:
15673     case indir_dx_reg:
15674       OP_IMREG (bytemode, sizeflag);
15675       break;
15676     case eDI_reg:
15677       OP_ESreg (bytemode, sizeflag);
15678       break;
15679     case eSI_reg:
15680       OP_DSreg (bytemode, sizeflag);
15681       break;
15682     default:
15683       abort ();
15684       break;
15685     }
15686 }
15687
15688 static void
15689 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15690 {
15691   if ( isa64 != amd64 )
15692     return;
15693
15694   obufp = obuf;
15695   BadOp ();
15696   mnemonicendp = obufp;
15697   ++codep;
15698 }
15699
15700 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15701    "bnd".  */
15702
15703 static void
15704 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15705 {
15706   if (prefixes & PREFIX_REPNZ)
15707     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15708 }
15709
15710 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15711    "notrack".  */
15712
15713 static void
15714 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15715                int sizeflag ATTRIBUTE_UNUSED)
15716 {
15717   if (active_seg_prefix == PREFIX_DS
15718       && (address_mode != mode_64bit || last_data_prefix < 0))
15719     {
15720       /* NOTRACK prefix is only valid on indirect branch instructions.
15721          NB: DATA prefix is unsupported for Intel64.  */
15722       active_seg_prefix = 0;
15723       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15724     }
15725 }
15726
15727 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15728    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15729  */
15730
15731 static void
15732 HLE_Fixup1 (int bytemode, int sizeflag)
15733 {
15734   if (modrm.mod != 3
15735       && (prefixes & PREFIX_LOCK) != 0)
15736     {
15737       if (prefixes & PREFIX_REPZ)
15738         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15739       if (prefixes & PREFIX_REPNZ)
15740         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15741     }
15742
15743   OP_E (bytemode, sizeflag);
15744 }
15745
15746 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15747    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15748  */
15749
15750 static void
15751 HLE_Fixup2 (int bytemode, int sizeflag)
15752 {
15753   if (modrm.mod != 3)
15754     {
15755       if (prefixes & PREFIX_REPZ)
15756         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15757       if (prefixes & PREFIX_REPNZ)
15758         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15759     }
15760
15761   OP_E (bytemode, sizeflag);
15762 }
15763
15764 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15765    "xrelease" for memory operand.  No check for LOCK prefix.   */
15766
15767 static void
15768 HLE_Fixup3 (int bytemode, int sizeflag)
15769 {
15770   if (modrm.mod != 3
15771       && last_repz_prefix > last_repnz_prefix
15772       && (prefixes & PREFIX_REPZ) != 0)
15773     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15774
15775   OP_E (bytemode, sizeflag);
15776 }
15777
15778 static void
15779 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15780 {
15781   USED_REX (REX_W);
15782   if (rex & REX_W)
15783     {
15784       /* Change cmpxchg8b to cmpxchg16b.  */
15785       char *p = mnemonicendp - 2;
15786       mnemonicendp = stpcpy (p, "16b");
15787       bytemode = o_mode;
15788     }
15789   else if ((prefixes & PREFIX_LOCK) != 0)
15790     {
15791       if (prefixes & PREFIX_REPZ)
15792         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15793       if (prefixes & PREFIX_REPNZ)
15794         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15795     }
15796
15797   OP_M (bytemode, sizeflag);
15798 }
15799
15800 static void
15801 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15802 {
15803   const char **names;
15804
15805   if (need_vex)
15806     {
15807       switch (vex.length)
15808         {
15809         case 128:
15810           names = names_xmm;
15811           break;
15812         case 256:
15813           names = names_ymm;
15814           break;
15815         default:
15816           abort ();
15817         }
15818     }
15819   else
15820     names = names_xmm;
15821   oappend (names[reg]);
15822 }
15823
15824 static void
15825 CRC32_Fixup (int bytemode, int sizeflag)
15826 {
15827   /* Add proper suffix to "crc32".  */
15828   char *p = mnemonicendp;
15829
15830   switch (bytemode)
15831     {
15832     case b_mode:
15833       if (intel_syntax)
15834         goto skip;
15835
15836       *p++ = 'b';
15837       break;
15838     case v_mode:
15839       if (intel_syntax)
15840         goto skip;
15841
15842       USED_REX (REX_W);
15843       if (rex & REX_W)
15844         *p++ = 'q';
15845       else
15846         {
15847           if (sizeflag & DFLAG)
15848             *p++ = 'l';
15849           else
15850             *p++ = 'w';
15851           used_prefixes |= (prefixes & PREFIX_DATA);
15852         }
15853       break;
15854     default:
15855       oappend (INTERNAL_DISASSEMBLER_ERROR);
15856       break;
15857     }
15858   mnemonicendp = p;
15859   *p = '\0';
15860
15861 skip:
15862   if (modrm.mod == 3)
15863     {
15864       int add;
15865
15866       /* Skip mod/rm byte.  */
15867       MODRM_CHECK;
15868       codep++;
15869
15870       USED_REX (REX_B);
15871       add = (rex & REX_B) ? 8 : 0;
15872       if (bytemode == b_mode)
15873         {
15874           USED_REX (0);
15875           if (rex)
15876             oappend (names8rex[modrm.rm + add]);
15877           else
15878             oappend (names8[modrm.rm + add]);
15879         }
15880       else
15881         {
15882           USED_REX (REX_W);
15883           if (rex & REX_W)
15884             oappend (names64[modrm.rm + add]);
15885           else if ((prefixes & PREFIX_DATA))
15886             oappend (names16[modrm.rm + add]);
15887           else
15888             oappend (names32[modrm.rm + add]);
15889         }
15890     }
15891   else
15892     OP_E (bytemode, sizeflag);
15893 }
15894
15895 static void
15896 FXSAVE_Fixup (int bytemode, int sizeflag)
15897 {
15898   /* Add proper suffix to "fxsave" and "fxrstor".  */
15899   USED_REX (REX_W);
15900   if (rex & REX_W)
15901     {
15902       char *p = mnemonicendp;
15903       *p++ = '6';
15904       *p++ = '4';
15905       *p = '\0';
15906       mnemonicendp = p;
15907     }
15908   OP_M (bytemode, sizeflag);
15909 }
15910
15911 static void
15912 PCMPESTR_Fixup (int bytemode, int sizeflag)
15913 {
15914   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15915   if (!intel_syntax)
15916     {
15917       char *p = mnemonicendp;
15918
15919       USED_REX (REX_W);
15920       if (rex & REX_W)
15921         *p++ = 'q';
15922       else if (sizeflag & SUFFIX_ALWAYS)
15923         *p++ = 'l';
15924
15925       *p = '\0';
15926       mnemonicendp = p;
15927     }
15928
15929   OP_EX (bytemode, sizeflag);
15930 }
15931
15932 /* Display the destination register operand for instructions with
15933    VEX. */
15934
15935 static void
15936 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15937 {
15938   int reg;
15939   const char **names;
15940
15941   if (!need_vex)
15942     abort ();
15943
15944   if (!need_vex_reg)
15945     return;
15946
15947   reg = vex.register_specifier;
15948   vex.register_specifier = 0;
15949   if (address_mode != mode_64bit)
15950     reg &= 7;
15951   else if (vex.evex && !vex.v)
15952     reg += 16;
15953
15954   if (bytemode == vex_scalar_mode)
15955     {
15956       oappend (names_xmm[reg]);
15957       return;
15958     }
15959
15960   switch (vex.length)
15961     {
15962     case 128:
15963       switch (bytemode)
15964         {
15965         case vex_mode:
15966         case vex128_mode:
15967         case vex_vsib_q_w_dq_mode:
15968         case vex_vsib_q_w_d_mode:
15969           names = names_xmm;
15970           break;
15971         case dq_mode:
15972           if (rex & REX_W)
15973             names = names64;
15974           else
15975             names = names32;
15976           break;
15977         case mask_bd_mode:
15978         case mask_mode:
15979           if (reg > 0x7)
15980             {
15981               oappend ("(bad)");
15982               return;
15983             }
15984           names = names_mask;
15985           break;
15986         default:
15987           abort ();
15988           return;
15989         }
15990       break;
15991     case 256:
15992       switch (bytemode)
15993         {
15994         case vex_mode:
15995         case vex256_mode:
15996           names = names_ymm;
15997           break;
15998         case vex_vsib_q_w_dq_mode:
15999         case vex_vsib_q_w_d_mode:
16000           names = vex.w ? names_ymm : names_xmm;
16001           break;
16002         case mask_bd_mode:
16003         case mask_mode:
16004           if (reg > 0x7)
16005             {
16006               oappend ("(bad)");
16007               return;
16008             }
16009           names = names_mask;
16010           break;
16011         default:
16012           /* See PR binutils/20893 for a reproducer.  */
16013           oappend ("(bad)");
16014           return;
16015         }
16016       break;
16017     case 512:
16018       names = names_zmm;
16019       break;
16020     default:
16021       abort ();
16022       break;
16023     }
16024   oappend (names[reg]);
16025 }
16026
16027 /* Get the VEX immediate byte without moving codep.  */
16028
16029 static unsigned char
16030 get_vex_imm8 (int sizeflag, int opnum)
16031 {
16032   int bytes_before_imm = 0;
16033
16034   if (modrm.mod != 3)
16035     {
16036       /* There are SIB/displacement bytes.  */
16037       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16038         {
16039           /* 32/64 bit address mode */
16040           int base = modrm.rm;
16041
16042           /* Check SIB byte.  */
16043           if (base == 4)
16044             {
16045               FETCH_DATA (the_info, codep + 1);
16046               base = *codep & 7;
16047               /* When decoding the third source, don't increase
16048                  bytes_before_imm as this has already been incremented
16049                  by one in OP_E_memory while decoding the second
16050                  source operand.  */
16051               if (opnum == 0)
16052                 bytes_before_imm++;
16053             }
16054
16055           /* Don't increase bytes_before_imm when decoding the third source,
16056              it has already been incremented by OP_E_memory while decoding
16057              the second source operand.  */
16058           if (opnum == 0)
16059             {
16060               switch (modrm.mod)
16061                 {
16062                   case 0:
16063                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16064                        SIB == 5, there is a 4 byte displacement.  */
16065                     if (base != 5)
16066                       /* No displacement. */
16067                       break;
16068                     /* Fall through.  */
16069                   case 2:
16070                     /* 4 byte displacement.  */
16071                     bytes_before_imm += 4;
16072                     break;
16073                   case 1:
16074                     /* 1 byte displacement.  */
16075                     bytes_before_imm++;
16076                     break;
16077                 }
16078             }
16079         }
16080       else
16081         {
16082           /* 16 bit address mode */
16083           /* Don't increase bytes_before_imm when decoding the third source,
16084              it has already been incremented by OP_E_memory while decoding
16085              the second source operand.  */
16086           if (opnum == 0)
16087             {
16088               switch (modrm.mod)
16089                 {
16090                 case 0:
16091                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16092                   if (modrm.rm != 6)
16093                     /* No displacement. */
16094                     break;
16095                   /* Fall through.  */
16096                 case 2:
16097                   /* 2 byte displacement.  */
16098                   bytes_before_imm += 2;
16099                   break;
16100                 case 1:
16101                   /* 1 byte displacement: when decoding the third source,
16102                      don't increase bytes_before_imm as this has already
16103                      been incremented by one in OP_E_memory while decoding
16104                      the second source operand.  */
16105                   if (opnum == 0)
16106                     bytes_before_imm++;
16107
16108                   break;
16109                 }
16110             }
16111         }
16112     }
16113
16114   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16115   return codep [bytes_before_imm];
16116 }
16117
16118 static void
16119 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16120 {
16121   const char **names;
16122
16123   if (reg == -1 && modrm.mod != 3)
16124     {
16125       OP_E_memory (bytemode, sizeflag);
16126       return;
16127     }
16128   else
16129     {
16130       if (reg == -1)
16131         {
16132           reg = modrm.rm;
16133           USED_REX (REX_B);
16134           if (rex & REX_B)
16135             reg += 8;
16136         }
16137       if (address_mode != mode_64bit)
16138         reg &= 7;
16139     }
16140
16141   switch (vex.length)
16142     {
16143     case 128:
16144       names = names_xmm;
16145       break;
16146     case 256:
16147       names = names_ymm;
16148       break;
16149     default:
16150       abort ();
16151     }
16152   oappend (names[reg]);
16153 }
16154
16155 static void
16156 OP_EX_VexImmW (int bytemode, int sizeflag)
16157 {
16158   int reg = -1;
16159   static unsigned char vex_imm8;
16160
16161   if (vex_w_done == 0)
16162     {
16163       vex_w_done = 1;
16164
16165       /* Skip mod/rm byte.  */
16166       MODRM_CHECK;
16167       codep++;
16168
16169       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16170
16171       if (vex.w)
16172           reg = vex_imm8 >> 4;
16173
16174       OP_EX_VexReg (bytemode, sizeflag, reg);
16175     }
16176   else if (vex_w_done == 1)
16177     {
16178       vex_w_done = 2;
16179
16180       if (!vex.w)
16181           reg = vex_imm8 >> 4;
16182
16183       OP_EX_VexReg (bytemode, sizeflag, reg);
16184     }
16185   else
16186     {
16187       /* Output the imm8 directly.  */
16188       scratchbuf[0] = '$';
16189       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16190       oappend_maybe_intel (scratchbuf);
16191       scratchbuf[0] = '\0';
16192       codep++;
16193     }
16194 }
16195
16196 static void
16197 OP_Vex_2src (int bytemode, int sizeflag)
16198 {
16199   if (modrm.mod == 3)
16200     {
16201       int reg = modrm.rm;
16202       USED_REX (REX_B);
16203       if (rex & REX_B)
16204         reg += 8;
16205       oappend (names_xmm[reg]);
16206     }
16207   else
16208     {
16209       if (intel_syntax
16210           && (bytemode == v_mode || bytemode == v_swap_mode))
16211         {
16212           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16213           used_prefixes |= (prefixes & PREFIX_DATA);
16214         }
16215       OP_E (bytemode, sizeflag);
16216     }
16217 }
16218
16219 static void
16220 OP_Vex_2src_1 (int bytemode, int sizeflag)
16221 {
16222   if (modrm.mod == 3)
16223     {
16224       /* Skip mod/rm byte.   */
16225       MODRM_CHECK;
16226       codep++;
16227     }
16228
16229   if (vex.w)
16230     {
16231       unsigned int reg = vex.register_specifier;
16232       vex.register_specifier = 0;
16233
16234       if (address_mode != mode_64bit)
16235         reg &= 7;
16236       oappend (names_xmm[reg]);
16237     }
16238   else
16239     OP_Vex_2src (bytemode, sizeflag);
16240 }
16241
16242 static void
16243 OP_Vex_2src_2 (int bytemode, int sizeflag)
16244 {
16245   if (vex.w)
16246     OP_Vex_2src (bytemode, sizeflag);
16247   else
16248     {
16249       unsigned int reg = vex.register_specifier;
16250       vex.register_specifier = 0;
16251
16252       if (address_mode != mode_64bit)
16253         reg &= 7;
16254       oappend (names_xmm[reg]);
16255     }
16256 }
16257
16258 static void
16259 OP_EX_VexW (int bytemode, int sizeflag)
16260 {
16261   int reg = -1;
16262
16263   if (!vex_w_done)
16264     {
16265       /* Skip mod/rm byte.  */
16266       MODRM_CHECK;
16267       codep++;
16268
16269       if (vex.w)
16270         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16271     }
16272   else
16273     {
16274       if (!vex.w)
16275         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16276     }
16277
16278   OP_EX_VexReg (bytemode, sizeflag, reg);
16279
16280   if (vex_w_done)
16281     codep++;
16282   vex_w_done = 1;
16283 }
16284
16285 static void
16286 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16287 {
16288   int reg;
16289   const char **names;
16290
16291   FETCH_DATA (the_info, codep + 1);
16292   reg = *codep++;
16293
16294   if (bytemode != x_mode)
16295     abort ();
16296
16297   reg >>= 4;
16298   if (address_mode != mode_64bit)
16299     reg &= 7;
16300
16301   switch (vex.length)
16302     {
16303     case 128:
16304       names = names_xmm;
16305       break;
16306     case 256:
16307       names = names_ymm;
16308       break;
16309     default:
16310       abort ();
16311     }
16312   oappend (names[reg]);
16313 }
16314
16315 static void
16316 OP_XMM_VexW (int bytemode, int sizeflag)
16317 {
16318   /* Turn off the REX.W bit since it is used for swapping operands
16319      now.  */
16320   rex &= ~REX_W;
16321   OP_XMM (bytemode, sizeflag);
16322 }
16323
16324 static void
16325 OP_EX_Vex (int bytemode, int sizeflag)
16326 {
16327   if (modrm.mod != 3)
16328     need_vex_reg = 0;
16329   OP_EX (bytemode, sizeflag);
16330 }
16331
16332 static void
16333 OP_XMM_Vex (int bytemode, int sizeflag)
16334 {
16335   if (modrm.mod != 3)
16336     need_vex_reg = 0;
16337   OP_XMM (bytemode, sizeflag);
16338 }
16339
16340 static struct op vex_cmp_op[] =
16341 {
16342   { STRING_COMMA_LEN ("eq") },
16343   { STRING_COMMA_LEN ("lt") },
16344   { STRING_COMMA_LEN ("le") },
16345   { STRING_COMMA_LEN ("unord") },
16346   { STRING_COMMA_LEN ("neq") },
16347   { STRING_COMMA_LEN ("nlt") },
16348   { STRING_COMMA_LEN ("nle") },
16349   { STRING_COMMA_LEN ("ord") },
16350   { STRING_COMMA_LEN ("eq_uq") },
16351   { STRING_COMMA_LEN ("nge") },
16352   { STRING_COMMA_LEN ("ngt") },
16353   { STRING_COMMA_LEN ("false") },
16354   { STRING_COMMA_LEN ("neq_oq") },
16355   { STRING_COMMA_LEN ("ge") },
16356   { STRING_COMMA_LEN ("gt") },
16357   { STRING_COMMA_LEN ("true") },
16358   { STRING_COMMA_LEN ("eq_os") },
16359   { STRING_COMMA_LEN ("lt_oq") },
16360   { STRING_COMMA_LEN ("le_oq") },
16361   { STRING_COMMA_LEN ("unord_s") },
16362   { STRING_COMMA_LEN ("neq_us") },
16363   { STRING_COMMA_LEN ("nlt_uq") },
16364   { STRING_COMMA_LEN ("nle_uq") },
16365   { STRING_COMMA_LEN ("ord_s") },
16366   { STRING_COMMA_LEN ("eq_us") },
16367   { STRING_COMMA_LEN ("nge_uq") },
16368   { STRING_COMMA_LEN ("ngt_uq") },
16369   { STRING_COMMA_LEN ("false_os") },
16370   { STRING_COMMA_LEN ("neq_os") },
16371   { STRING_COMMA_LEN ("ge_oq") },
16372   { STRING_COMMA_LEN ("gt_oq") },
16373   { STRING_COMMA_LEN ("true_us") },
16374 };
16375
16376 static void
16377 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16378 {
16379   unsigned int cmp_type;
16380
16381   FETCH_DATA (the_info, codep + 1);
16382   cmp_type = *codep++ & 0xff;
16383   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16384     {
16385       char suffix [3];
16386       char *p = mnemonicendp - 2;
16387       suffix[0] = p[0];
16388       suffix[1] = p[1];
16389       suffix[2] = '\0';
16390       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16391       mnemonicendp += vex_cmp_op[cmp_type].len;
16392     }
16393   else
16394     {
16395       /* We have a reserved extension byte.  Output it directly.  */
16396       scratchbuf[0] = '$';
16397       print_operand_value (scratchbuf + 1, 1, cmp_type);
16398       oappend_maybe_intel (scratchbuf);
16399       scratchbuf[0] = '\0';
16400     }
16401 }
16402
16403 static void
16404 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16405              int sizeflag ATTRIBUTE_UNUSED)
16406 {
16407   unsigned int cmp_type;
16408
16409   if (!vex.evex)
16410     abort ();
16411
16412   FETCH_DATA (the_info, codep + 1);
16413   cmp_type = *codep++ & 0xff;
16414   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16415      If it's the case, print suffix, otherwise - print the immediate.  */
16416   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16417       && cmp_type != 3
16418       && cmp_type != 7)
16419     {
16420       char suffix [3];
16421       char *p = mnemonicendp - 2;
16422
16423       /* vpcmp* can have both one- and two-lettered suffix.  */
16424       if (p[0] == 'p')
16425         {
16426           p++;
16427           suffix[0] = p[0];
16428           suffix[1] = '\0';
16429         }
16430       else
16431         {
16432           suffix[0] = p[0];
16433           suffix[1] = p[1];
16434           suffix[2] = '\0';
16435         }
16436
16437       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16438       mnemonicendp += simd_cmp_op[cmp_type].len;
16439     }
16440   else
16441     {
16442       /* We have a reserved extension byte.  Output it directly.  */
16443       scratchbuf[0] = '$';
16444       print_operand_value (scratchbuf + 1, 1, cmp_type);
16445       oappend_maybe_intel (scratchbuf);
16446       scratchbuf[0] = '\0';
16447     }
16448 }
16449
16450 static const struct op xop_cmp_op[] =
16451 {
16452   { STRING_COMMA_LEN ("lt") },
16453   { STRING_COMMA_LEN ("le") },
16454   { STRING_COMMA_LEN ("gt") },
16455   { STRING_COMMA_LEN ("ge") },
16456   { STRING_COMMA_LEN ("eq") },
16457   { STRING_COMMA_LEN ("neq") },
16458   { STRING_COMMA_LEN ("false") },
16459   { STRING_COMMA_LEN ("true") }
16460 };
16461
16462 static void
16463 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16464              int sizeflag ATTRIBUTE_UNUSED)
16465 {
16466   unsigned int cmp_type;
16467
16468   FETCH_DATA (the_info, codep + 1);
16469   cmp_type = *codep++ & 0xff;
16470   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16471     {
16472       char suffix[3];
16473       char *p = mnemonicendp - 2;
16474
16475       /* vpcom* can have both one- and two-lettered suffix.  */
16476       if (p[0] == 'm')
16477         {
16478           p++;
16479           suffix[0] = p[0];
16480           suffix[1] = '\0';
16481         }
16482       else
16483         {
16484           suffix[0] = p[0];
16485           suffix[1] = p[1];
16486           suffix[2] = '\0';
16487         }
16488
16489       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16490       mnemonicendp += xop_cmp_op[cmp_type].len;
16491     }
16492   else
16493     {
16494       /* We have a reserved extension byte.  Output it directly.  */
16495       scratchbuf[0] = '$';
16496       print_operand_value (scratchbuf + 1, 1, cmp_type);
16497       oappend_maybe_intel (scratchbuf);
16498       scratchbuf[0] = '\0';
16499     }
16500 }
16501
16502 static const struct op pclmul_op[] =
16503 {
16504   { STRING_COMMA_LEN ("lql") },
16505   { STRING_COMMA_LEN ("hql") },
16506   { STRING_COMMA_LEN ("lqh") },
16507   { STRING_COMMA_LEN ("hqh") }
16508 };
16509
16510 static void
16511 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16512               int sizeflag ATTRIBUTE_UNUSED)
16513 {
16514   unsigned int pclmul_type;
16515
16516   FETCH_DATA (the_info, codep + 1);
16517   pclmul_type = *codep++ & 0xff;
16518   switch (pclmul_type)
16519     {
16520     case 0x10:
16521       pclmul_type = 2;
16522       break;
16523     case 0x11:
16524       pclmul_type = 3;
16525       break;
16526     default:
16527       break;
16528     }
16529   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16530     {
16531       char suffix [4];
16532       char *p = mnemonicendp - 3;
16533       suffix[0] = p[0];
16534       suffix[1] = p[1];
16535       suffix[2] = p[2];
16536       suffix[3] = '\0';
16537       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16538       mnemonicendp += pclmul_op[pclmul_type].len;
16539     }
16540   else
16541     {
16542       /* We have a reserved extension byte.  Output it directly.  */
16543       scratchbuf[0] = '$';
16544       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16545       oappend_maybe_intel (scratchbuf);
16546       scratchbuf[0] = '\0';
16547     }
16548 }
16549
16550 static void
16551 MOVBE_Fixup (int bytemode, int sizeflag)
16552 {
16553   /* Add proper suffix to "movbe".  */
16554   char *p = mnemonicendp;
16555
16556   switch (bytemode)
16557     {
16558     case v_mode:
16559       if (intel_syntax)
16560         goto skip;
16561
16562       USED_REX (REX_W);
16563       if (sizeflag & SUFFIX_ALWAYS)
16564         {
16565           if (rex & REX_W)
16566             *p++ = 'q';
16567           else
16568             {
16569               if (sizeflag & DFLAG)
16570                 *p++ = 'l';
16571               else
16572                 *p++ = 'w';
16573               used_prefixes |= (prefixes & PREFIX_DATA);
16574             }
16575         }
16576       break;
16577     default:
16578       oappend (INTERNAL_DISASSEMBLER_ERROR);
16579       break;
16580     }
16581   mnemonicendp = p;
16582   *p = '\0';
16583
16584 skip:
16585   OP_M (bytemode, sizeflag);
16586 }
16587
16588 static void
16589 MOVSXD_Fixup (int bytemode, int sizeflag)
16590 {
16591   /* Add proper suffix to "movsxd".  */
16592   char *p = mnemonicendp;
16593
16594   switch (bytemode)
16595     {
16596     case movsxd_mode:
16597       if (intel_syntax)
16598         {
16599           *p++ = 'x';
16600           *p++ = 'd';
16601           goto skip;
16602         }
16603
16604       USED_REX (REX_W);
16605       if (rex & REX_W)
16606         {
16607           *p++ = 'l';
16608           *p++ = 'q';
16609         }
16610       else
16611         {
16612           *p++ = 'x';
16613           *p++ = 'd';
16614         }
16615       break;
16616     default:
16617       oappend (INTERNAL_DISASSEMBLER_ERROR);
16618       break;
16619     }
16620
16621 skip:
16622   mnemonicendp = p;
16623   *p = '\0';
16624   OP_E (bytemode, sizeflag);
16625 }
16626
16627 static void
16628 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16629 {
16630   int reg;
16631   const char **names;
16632
16633   /* Skip mod/rm byte.  */
16634   MODRM_CHECK;
16635   codep++;
16636
16637   if (rex & REX_W)
16638     names = names64;
16639   else
16640     names = names32;
16641
16642   reg = modrm.rm;
16643   USED_REX (REX_B);
16644   if (rex & REX_B)
16645     reg += 8;
16646
16647   oappend (names[reg]);
16648 }
16649
16650 static void
16651 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16652 {
16653   const char **names;
16654   unsigned int reg = vex.register_specifier;
16655   vex.register_specifier = 0;
16656
16657   if (rex & REX_W)
16658     names = names64;
16659   else
16660     names = names32;
16661
16662   if (address_mode != mode_64bit)
16663     reg &= 7;
16664   oappend (names[reg]);
16665 }
16666
16667 static void
16668 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16669 {
16670   if (!vex.evex
16671       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16672     abort ();
16673
16674   USED_REX (REX_R);
16675   if ((rex & REX_R) != 0 || !vex.r)
16676     {
16677       BadOp ();
16678       return;
16679     }
16680
16681   oappend (names_mask [modrm.reg]);
16682 }
16683
16684 static void
16685 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16686 {
16687   if (!vex.evex
16688       || (bytemode != evex_rounding_mode
16689           && bytemode != evex_rounding_64_mode
16690           && bytemode != evex_sae_mode))
16691     abort ();
16692   if (modrm.mod == 3 && vex.b)
16693     switch (bytemode)
16694       {
16695       case evex_rounding_64_mode:
16696         if (address_mode != mode_64bit)
16697           {
16698             oappend ("(bad)");
16699             break;
16700           }
16701         /* Fall through.  */
16702       case evex_rounding_mode:
16703         oappend (names_rounding[vex.ll]);
16704         break;
16705       case evex_sae_mode:
16706         oappend ("{sae}");
16707         break;
16708       default:
16709         break;
16710       }
16711 }