1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void NOP_Fixup1 (int, int);
105 static void NOP_Fixup2 (int, int);
106 static void OP_3DNowSuffix (int, int);
107 static void CMP_Fixup (int, int);
108 static void BadOp (void);
109 static void REP_Fixup (int, int);
110 static void SEP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
127 static void MOVSXD_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte
*max_fetched
;
134 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
137 OPCODES_SIGJMP_BUF bailout
;
147 enum address_mode address_mode
;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* Mark parts used in the REX prefix. When we are testing for
157 empty prefix (for 8bit register REX extension), just mask it
158 out. Otherwise test for REX bit is excuse for existence of REX
159 only in case value is nonzero. */
160 #define USED_REX(value) \
165 rex_used |= (value) | REX_OPCODE; \
168 rex_used |= REX_OPCODE; \
171 /* Flags for prefixes which we somehow handled when printing the
172 current instruction. */
173 static int used_prefixes
;
175 /* Flags stored in PREFIXES. */
176 #define PREFIX_REPZ 1
177 #define PREFIX_REPNZ 2
178 #define PREFIX_LOCK 4
180 #define PREFIX_SS 0x10
181 #define PREFIX_DS 0x20
182 #define PREFIX_ES 0x40
183 #define PREFIX_FS 0x80
184 #define PREFIX_GS 0x100
185 #define PREFIX_DATA 0x200
186 #define PREFIX_ADDR 0x400
187 #define PREFIX_FWAIT 0x800
189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
190 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
192 #define FETCH_DATA(info, addr) \
193 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
194 ? 1 : fetch_data ((info), (addr)))
197 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
200 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
201 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
203 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
204 status
= (*info
->read_memory_func
) (start
,
206 addr
- priv
->max_fetched
,
212 /* If we did manage to read at least one byte, then
213 print_insn_i386 will do something sensible. Otherwise, print
214 an error. We do that here because this is where we know
216 if (priv
->max_fetched
== priv
->the_buffer
)
217 (*info
->memory_error_func
) (status
, start
, info
);
218 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
221 priv
->max_fetched
= addr
;
225 /* Possible values for prefix requirement. */
226 #define PREFIX_IGNORED_SHIFT 16
227 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
228 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
233 /* Opcode prefixes. */
234 #define PREFIX_OPCODE (PREFIX_REPZ \
238 /* Prefixes ignored. */
239 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
240 | PREFIX_IGNORED_REPNZ \
241 | PREFIX_IGNORED_DATA)
243 #define XX { NULL, 0 }
244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
246 #define Eb { OP_E, b_mode }
247 #define Ebnd { OP_E, bnd_mode }
248 #define EbS { OP_E, b_swap_mode }
249 #define EbndS { OP_E, bnd_swap_mode }
250 #define Ev { OP_E, v_mode }
251 #define Eva { OP_E, va_mode }
252 #define Ev_bnd { OP_E, v_bnd_mode }
253 #define EvS { OP_E, v_swap_mode }
254 #define Ed { OP_E, d_mode }
255 #define Edq { OP_E, dq_mode }
256 #define Edqw { OP_E, dqw_mode }
257 #define Edqb { OP_E, dqb_mode }
258 #define Edb { OP_E, db_mode }
259 #define Edw { OP_E, dw_mode }
260 #define Edqd { OP_E, dqd_mode }
261 #define Eq { OP_E, q_mode }
262 #define indirEv { OP_indirE, indir_v_mode }
263 #define indirEp { OP_indirE, f_mode }
264 #define stackEv { OP_E, stack_v_mode }
265 #define Em { OP_E, m_mode }
266 #define Ew { OP_E, w_mode }
267 #define M { OP_M, 0 } /* lea, lgdt, etc. */
268 #define Ma { OP_M, a_mode }
269 #define Mb { OP_M, b_mode }
270 #define Md { OP_M, d_mode }
271 #define Mo { OP_M, o_mode }
272 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
273 #define Mq { OP_M, q_mode }
274 #define Mv_bnd { OP_M, v_bndmk_mode }
275 #define Mx { OP_M, x_mode }
276 #define Mxmm { OP_M, xmm_mode }
277 #define Gb { OP_G, b_mode }
278 #define Gbnd { OP_G, bnd_mode }
279 #define Gv { OP_G, v_mode }
280 #define Gd { OP_G, d_mode }
281 #define Gdq { OP_G, dq_mode }
282 #define Gm { OP_G, m_mode }
283 #define Gva { OP_G, va_mode }
284 #define Gw { OP_G, w_mode }
285 #define Rd { OP_R, d_mode }
286 #define Rdq { OP_R, dq_mode }
287 #define Rm { OP_R, m_mode }
288 #define Ib { OP_I, b_mode }
289 #define sIb { OP_sI, b_mode } /* sign extened byte */
290 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
291 #define Iv { OP_I, v_mode }
292 #define sIv { OP_sI, v_mode }
293 #define Iv64 { OP_I64, v_mode }
294 #define Id { OP_I, d_mode }
295 #define Iw { OP_I, w_mode }
296 #define I1 { OP_I, const_1_mode }
297 #define Jb { OP_J, b_mode }
298 #define Jv { OP_J, v_mode }
299 #define Jdqw { OP_J, dqw_mode }
300 #define Cm { OP_C, m_mode }
301 #define Dm { OP_D, m_mode }
302 #define Td { OP_T, d_mode }
303 #define Skip_MODRM { OP_Skip_MODRM, 0 }
305 #define RMeAX { OP_REG, eAX_reg }
306 #define RMeBX { OP_REG, eBX_reg }
307 #define RMeCX { OP_REG, eCX_reg }
308 #define RMeDX { OP_REG, eDX_reg }
309 #define RMeSP { OP_REG, eSP_reg }
310 #define RMeBP { OP_REG, eBP_reg }
311 #define RMeSI { OP_REG, eSI_reg }
312 #define RMeDI { OP_REG, eDI_reg }
313 #define RMrAX { OP_REG, rAX_reg }
314 #define RMrBX { OP_REG, rBX_reg }
315 #define RMrCX { OP_REG, rCX_reg }
316 #define RMrDX { OP_REG, rDX_reg }
317 #define RMrSP { OP_REG, rSP_reg }
318 #define RMrBP { OP_REG, rBP_reg }
319 #define RMrSI { OP_REG, rSI_reg }
320 #define RMrDI { OP_REG, rDI_reg }
321 #define RMAL { OP_REG, al_reg }
322 #define RMCL { OP_REG, cl_reg }
323 #define RMDL { OP_REG, dl_reg }
324 #define RMBL { OP_REG, bl_reg }
325 #define RMAH { OP_REG, ah_reg }
326 #define RMCH { OP_REG, ch_reg }
327 #define RMDH { OP_REG, dh_reg }
328 #define RMBH { OP_REG, bh_reg }
329 #define RMAX { OP_REG, ax_reg }
330 #define RMDX { OP_REG, dx_reg }
332 #define eAX { OP_IMREG, eAX_reg }
333 #define eBX { OP_IMREG, eBX_reg }
334 #define eCX { OP_IMREG, eCX_reg }
335 #define eDX { OP_IMREG, eDX_reg }
336 #define eSP { OP_IMREG, eSP_reg }
337 #define eBP { OP_IMREG, eBP_reg }
338 #define eSI { OP_IMREG, eSI_reg }
339 #define eDI { OP_IMREG, eDI_reg }
340 #define AL { OP_IMREG, al_reg }
341 #define CL { OP_IMREG, cl_reg }
342 #define DL { OP_IMREG, dl_reg }
343 #define BL { OP_IMREG, bl_reg }
344 #define AH { OP_IMREG, ah_reg }
345 #define CH { OP_IMREG, ch_reg }
346 #define DH { OP_IMREG, dh_reg }
347 #define BH { OP_IMREG, bh_reg }
348 #define AX { OP_IMREG, ax_reg }
349 #define DX { OP_IMREG, dx_reg }
350 #define zAX { OP_IMREG, z_mode_ax_reg }
351 #define indirDX { OP_IMREG, indir_dx_reg }
353 #define Sw { OP_SEG, w_mode }
354 #define Sv { OP_SEG, v_mode }
355 #define Ap { OP_DIR, 0 }
356 #define Ob { OP_OFF64, b_mode }
357 #define Ov { OP_OFF64, v_mode }
358 #define Xb { OP_DSreg, eSI_reg }
359 #define Xv { OP_DSreg, eSI_reg }
360 #define Xz { OP_DSreg, eSI_reg }
361 #define Yb { OP_ESreg, eDI_reg }
362 #define Yv { OP_ESreg, eDI_reg }
363 #define DSBX { OP_DSreg, eBX_reg }
365 #define es { OP_REG, es_reg }
366 #define ss { OP_REG, ss_reg }
367 #define cs { OP_REG, cs_reg }
368 #define ds { OP_REG, ds_reg }
369 #define fs { OP_REG, fs_reg }
370 #define gs { OP_REG, gs_reg }
372 #define MX { OP_MMX, 0 }
373 #define XM { OP_XMM, 0 }
374 #define XMScalar { OP_XMM, scalar_mode }
375 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
376 #define XMM { OP_XMM, xmm_mode }
377 #define XMxmmq { OP_XMM, xmmq_mode }
378 #define EM { OP_EM, v_mode }
379 #define EMS { OP_EM, v_swap_mode }
380 #define EMd { OP_EM, d_mode }
381 #define EMx { OP_EM, x_mode }
382 #define EXbScalar { OP_EX, b_scalar_mode }
383 #define EXw { OP_EX, w_mode }
384 #define EXwScalar { OP_EX, w_scalar_mode }
385 #define EXd { OP_EX, d_mode }
386 #define EXdScalar { OP_EX, d_scalar_mode }
387 #define EXdS { OP_EX, d_swap_mode }
388 #define EXq { OP_EX, q_mode }
389 #define EXqScalar { OP_EX, q_scalar_mode }
390 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
391 #define EXqS { OP_EX, q_swap_mode }
392 #define EXx { OP_EX, x_mode }
393 #define EXxS { OP_EX, x_swap_mode }
394 #define EXxmm { OP_EX, xmm_mode }
395 #define EXymm { OP_EX, ymm_mode }
396 #define EXxmmq { OP_EX, xmmq_mode }
397 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
398 #define EXxmm_mb { OP_EX, xmm_mb_mode }
399 #define EXxmm_mw { OP_EX, xmm_mw_mode }
400 #define EXxmm_md { OP_EX, xmm_md_mode }
401 #define EXxmm_mq { OP_EX, xmm_mq_mode }
402 #define EXxmmdw { OP_EX, xmmdw_mode }
403 #define EXxmmqd { OP_EX, xmmqd_mode }
404 #define EXymmq { OP_EX, ymmq_mode }
405 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
406 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
407 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
408 #define MS { OP_MS, v_mode }
409 #define XS { OP_XS, v_mode }
410 #define EMCq { OP_EMC, q_mode }
411 #define MXC { OP_MXC, 0 }
412 #define OPSUF { OP_3DNowSuffix, 0 }
413 #define SEP { SEP_Fixup, 0 }
414 #define CMP { CMP_Fixup, 0 }
415 #define XMM0 { XMM_Fixup, 0 }
416 #define FXSAVE { FXSAVE_Fixup, 0 }
417 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
418 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
420 #define Vex { OP_VEX, vex_mode }
421 #define VexScalar { OP_VEX, vex_scalar_mode }
422 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
423 #define Vex128 { OP_VEX, vex128_mode }
424 #define Vex256 { OP_VEX, vex256_mode }
425 #define VexGdq { OP_VEX, dq_mode }
426 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
427 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
428 #define EXVexW { OP_EX_VexW, x_mode }
429 #define EXdVexW { OP_EX_VexW, d_mode }
430 #define EXqVexW { OP_EX_VexW, q_mode }
431 #define EXVexImmW { OP_EX_VexImmW, x_mode }
432 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
433 #define XMVexW { OP_XMM_VexW, 0 }
434 #define XMVexI4 { OP_REG_VexI4, x_mode }
435 #define PCLMUL { PCLMUL_Fixup, 0 }
436 #define VCMP { VCMP_Fixup, 0 }
437 #define VPCMP { VPCMP_Fixup, 0 }
438 #define VPCOM { VPCOM_Fixup, 0 }
440 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
441 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
442 #define EXxEVexS { OP_Rounding, evex_sae_mode }
444 #define XMask { OP_Mask, mask_mode }
445 #define MaskG { OP_G, mask_mode }
446 #define MaskE { OP_E, mask_mode }
447 #define MaskBDE { OP_E, mask_bd_mode }
448 #define MaskR { OP_R, mask_mode }
449 #define MaskVex { OP_VEX, mask_mode }
451 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
452 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
453 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
454 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
456 /* Used handle "rep" prefix for string instructions. */
457 #define Xbr { REP_Fixup, eSI_reg }
458 #define Xvr { REP_Fixup, eSI_reg }
459 #define Ybr { REP_Fixup, eDI_reg }
460 #define Yvr { REP_Fixup, eDI_reg }
461 #define Yzr { REP_Fixup, eDI_reg }
462 #define indirDXr { REP_Fixup, indir_dx_reg }
463 #define ALr { REP_Fixup, al_reg }
464 #define eAXr { REP_Fixup, eAX_reg }
466 /* Used handle HLE prefix for lockable instructions. */
467 #define Ebh1 { HLE_Fixup1, b_mode }
468 #define Evh1 { HLE_Fixup1, v_mode }
469 #define Ebh2 { HLE_Fixup2, b_mode }
470 #define Evh2 { HLE_Fixup2, v_mode }
471 #define Ebh3 { HLE_Fixup3, b_mode }
472 #define Evh3 { HLE_Fixup3, v_mode }
474 #define BND { BND_Fixup, 0 }
475 #define NOTRACK { NOTRACK_Fixup, 0 }
477 #define cond_jump_flag { NULL, cond_jump_mode }
478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
480 /* bits in sizeflag */
481 #define SUFFIX_ALWAYS 4
489 /* byte operand with operand swapped */
491 /* byte operand, sign extend like 'T' suffix */
493 /* operand size depends on prefixes */
495 /* operand size depends on prefixes with operand swapped */
497 /* operand size depends on address prefix */
501 /* double word operand */
503 /* double word operand with operand swapped */
505 /* quad word operand */
507 /* quad word operand with operand swapped */
509 /* ten-byte operand */
511 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
512 broadcast enabled. */
514 /* Similar to x_mode, but with different EVEX mem shifts. */
516 /* Similar to x_mode, but with disabled broadcast. */
518 /* Similar to x_mode, but with operands swapped and disabled broadcast
521 /* 16-byte XMM operand */
523 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
524 memory operand (depending on vector length). Broadcast isn't
527 /* Same as xmmq_mode, but broadcast is allowed. */
528 evex_half_bcst_xmmq_mode
,
529 /* XMM register or byte memory operand */
531 /* XMM register or word memory operand */
533 /* XMM register or double word memory operand */
535 /* XMM register or quad word memory operand */
537 /* 16-byte XMM, word, double word or quad word operand. */
539 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
541 /* 32-byte YMM operand */
543 /* quad word, ymmword or zmmword memory operand. */
545 /* 32-byte YMM or 16-byte word operand */
547 /* d_mode in 32bit, q_mode in 64bit mode. */
549 /* pair of v_mode operands */
555 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
557 /* operand size depends on REX prefixes. */
559 /* registers like dq_mode, memory like w_mode, displacements like
560 v_mode without considering Intel64 ISA. */
564 /* bounds operand with operand swapped */
566 /* 4- or 6-byte pointer operand */
569 /* v_mode for indirect branch opcodes. */
571 /* v_mode for stack-related opcodes. */
573 /* non-quad operand size depends on prefixes */
575 /* 16-byte operand */
577 /* registers like dq_mode, memory like b_mode. */
579 /* registers like d_mode, memory like b_mode. */
581 /* registers like d_mode, memory like w_mode. */
583 /* registers like dq_mode, memory like d_mode. */
585 /* normal vex mode */
587 /* 128bit vex mode */
589 /* 256bit vex mode */
592 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
593 vex_vsib_d_w_dq_mode
,
594 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
596 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
597 vex_vsib_q_w_dq_mode
,
598 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
601 /* scalar, ignore vector length. */
603 /* like b_mode, ignore vector length. */
605 /* like w_mode, ignore vector length. */
607 /* like d_mode, ignore vector length. */
609 /* like d_swap_mode, ignore vector length. */
611 /* like q_mode, ignore vector length. */
613 /* like q_swap_mode, ignore vector length. */
615 /* like vex_mode, ignore vector length. */
617 /* Operand size depends on the VEX.W bit, ignore vector length. */
618 vex_scalar_w_dq_mode
,
620 /* Static rounding. */
622 /* Static rounding, 64-bit mode only. */
623 evex_rounding_64_mode
,
624 /* Supress all exceptions. */
627 /* Mask register operand. */
629 /* Mask register operand. */
697 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
699 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
700 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
701 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
702 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
703 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
704 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
705 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
706 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
707 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
708 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
709 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
710 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
711 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
712 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
713 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
714 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
844 MOD_VEX_0F12_PREFIX_0
,
845 MOD_VEX_0F12_PREFIX_2
,
847 MOD_VEX_0F16_PREFIX_0
,
848 MOD_VEX_0F16_PREFIX_2
,
851 MOD_VEX_W_0_0F41_P_0_LEN_1
,
852 MOD_VEX_W_1_0F41_P_0_LEN_1
,
853 MOD_VEX_W_0_0F41_P_2_LEN_1
,
854 MOD_VEX_W_1_0F41_P_2_LEN_1
,
855 MOD_VEX_W_0_0F42_P_0_LEN_1
,
856 MOD_VEX_W_1_0F42_P_0_LEN_1
,
857 MOD_VEX_W_0_0F42_P_2_LEN_1
,
858 MOD_VEX_W_1_0F42_P_2_LEN_1
,
859 MOD_VEX_W_0_0F44_P_0_LEN_1
,
860 MOD_VEX_W_1_0F44_P_0_LEN_1
,
861 MOD_VEX_W_0_0F44_P_2_LEN_1
,
862 MOD_VEX_W_1_0F44_P_2_LEN_1
,
863 MOD_VEX_W_0_0F45_P_0_LEN_1
,
864 MOD_VEX_W_1_0F45_P_0_LEN_1
,
865 MOD_VEX_W_0_0F45_P_2_LEN_1
,
866 MOD_VEX_W_1_0F45_P_2_LEN_1
,
867 MOD_VEX_W_0_0F46_P_0_LEN_1
,
868 MOD_VEX_W_1_0F46_P_0_LEN_1
,
869 MOD_VEX_W_0_0F46_P_2_LEN_1
,
870 MOD_VEX_W_1_0F46_P_2_LEN_1
,
871 MOD_VEX_W_0_0F47_P_0_LEN_1
,
872 MOD_VEX_W_1_0F47_P_0_LEN_1
,
873 MOD_VEX_W_0_0F47_P_2_LEN_1
,
874 MOD_VEX_W_1_0F47_P_2_LEN_1
,
875 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
876 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
877 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
878 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
879 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
880 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
881 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
893 MOD_VEX_W_0_0F91_P_0_LEN_0
,
894 MOD_VEX_W_1_0F91_P_0_LEN_0
,
895 MOD_VEX_W_0_0F91_P_2_LEN_0
,
896 MOD_VEX_W_1_0F91_P_2_LEN_0
,
897 MOD_VEX_W_0_0F92_P_0_LEN_0
,
898 MOD_VEX_W_0_0F92_P_2_LEN_0
,
899 MOD_VEX_0F92_P_3_LEN_0
,
900 MOD_VEX_W_0_0F93_P_0_LEN_0
,
901 MOD_VEX_W_0_0F93_P_2_LEN_0
,
902 MOD_VEX_0F93_P_3_LEN_0
,
903 MOD_VEX_W_0_0F98_P_0_LEN_0
,
904 MOD_VEX_W_1_0F98_P_0_LEN_0
,
905 MOD_VEX_W_0_0F98_P_2_LEN_0
,
906 MOD_VEX_W_1_0F98_P_2_LEN_0
,
907 MOD_VEX_W_0_0F99_P_0_LEN_0
,
908 MOD_VEX_W_1_0F99_P_0_LEN_0
,
909 MOD_VEX_W_0_0F99_P_2_LEN_0
,
910 MOD_VEX_W_1_0F99_P_2_LEN_0
,
913 MOD_VEX_0FD7_PREFIX_2
,
914 MOD_VEX_0FE7_PREFIX_2
,
915 MOD_VEX_0FF0_PREFIX_3
,
916 MOD_VEX_0F381A_PREFIX_2
,
917 MOD_VEX_0F382A_PREFIX_2
,
918 MOD_VEX_0F382C_PREFIX_2
,
919 MOD_VEX_0F382D_PREFIX_2
,
920 MOD_VEX_0F382E_PREFIX_2
,
921 MOD_VEX_0F382F_PREFIX_2
,
922 MOD_VEX_0F385A_PREFIX_2
,
923 MOD_VEX_0F388C_PREFIX_2
,
924 MOD_VEX_0F388E_PREFIX_2
,
925 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
926 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
927 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
928 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
929 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
930 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
931 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
932 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
934 MOD_EVEX_0F12_PREFIX_0
,
935 MOD_EVEX_0F12_PREFIX_2
,
937 MOD_EVEX_0F16_PREFIX_0
,
938 MOD_EVEX_0F16_PREFIX_2
,
941 MOD_EVEX_0F38C6_REG_1
,
942 MOD_EVEX_0F38C6_REG_2
,
943 MOD_EVEX_0F38C6_REG_5
,
944 MOD_EVEX_0F38C6_REG_6
,
945 MOD_EVEX_0F38C7_REG_1
,
946 MOD_EVEX_0F38C7_REG_2
,
947 MOD_EVEX_0F38C7_REG_5
,
948 MOD_EVEX_0F38C7_REG_6
961 RM_0F1E_P_1_MOD_3_REG_7
,
962 RM_0FAE_REG_6_MOD_3_P_0
,
969 PREFIX_0F01_REG_3_RM_1
,
970 PREFIX_0F01_REG_5_MOD_0
,
971 PREFIX_0F01_REG_5_MOD_3_RM_0
,
972 PREFIX_0F01_REG_5_MOD_3_RM_1
,
973 PREFIX_0F01_REG_5_MOD_3_RM_2
,
974 PREFIX_0F01_REG_7_MOD_3_RM_2
,
975 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1017 PREFIX_0FAE_REG_0_MOD_3
,
1018 PREFIX_0FAE_REG_1_MOD_3
,
1019 PREFIX_0FAE_REG_2_MOD_3
,
1020 PREFIX_0FAE_REG_3_MOD_3
,
1021 PREFIX_0FAE_REG_4_MOD_0
,
1022 PREFIX_0FAE_REG_4_MOD_3
,
1023 PREFIX_0FAE_REG_5_MOD_0
,
1024 PREFIX_0FAE_REG_5_MOD_3
,
1025 PREFIX_0FAE_REG_6_MOD_0
,
1026 PREFIX_0FAE_REG_6_MOD_3
,
1027 PREFIX_0FAE_REG_7_MOD_0
,
1033 PREFIX_0FC7_REG_6_MOD_0
,
1034 PREFIX_0FC7_REG_6_MOD_3
,
1035 PREFIX_0FC7_REG_7_MOD_3
,
1165 PREFIX_VEX_0F71_REG_2
,
1166 PREFIX_VEX_0F71_REG_4
,
1167 PREFIX_VEX_0F71_REG_6
,
1168 PREFIX_VEX_0F72_REG_2
,
1169 PREFIX_VEX_0F72_REG_4
,
1170 PREFIX_VEX_0F72_REG_6
,
1171 PREFIX_VEX_0F73_REG_2
,
1172 PREFIX_VEX_0F73_REG_3
,
1173 PREFIX_VEX_0F73_REG_6
,
1174 PREFIX_VEX_0F73_REG_7
,
1347 PREFIX_VEX_0F38F3_REG_1
,
1348 PREFIX_VEX_0F38F3_REG_2
,
1349 PREFIX_VEX_0F38F3_REG_3
,
1457 PREFIX_EVEX_0F71_REG_2
,
1458 PREFIX_EVEX_0F71_REG_4
,
1459 PREFIX_EVEX_0F71_REG_6
,
1460 PREFIX_EVEX_0F72_REG_0
,
1461 PREFIX_EVEX_0F72_REG_1
,
1462 PREFIX_EVEX_0F72_REG_2
,
1463 PREFIX_EVEX_0F72_REG_4
,
1464 PREFIX_EVEX_0F72_REG_6
,
1465 PREFIX_EVEX_0F73_REG_2
,
1466 PREFIX_EVEX_0F73_REG_3
,
1467 PREFIX_EVEX_0F73_REG_6
,
1468 PREFIX_EVEX_0F73_REG_7
,
1664 PREFIX_EVEX_0F38C6_REG_1
,
1665 PREFIX_EVEX_0F38C6_REG_2
,
1666 PREFIX_EVEX_0F38C6_REG_5
,
1667 PREFIX_EVEX_0F38C6_REG_6
,
1668 PREFIX_EVEX_0F38C7_REG_1
,
1669 PREFIX_EVEX_0F38C7_REG_2
,
1670 PREFIX_EVEX_0F38C7_REG_5
,
1671 PREFIX_EVEX_0F38C7_REG_6
,
1775 THREE_BYTE_0F38
= 0,
1802 VEX_LEN_0F12_P_0_M_0
= 0,
1803 VEX_LEN_0F12_P_0_M_1
,
1804 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1806 VEX_LEN_0F16_P_0_M_0
,
1807 VEX_LEN_0F16_P_0_M_1
,
1808 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1844 VEX_LEN_0FAE_R_2_M_0
,
1845 VEX_LEN_0FAE_R_3_M_0
,
1852 VEX_LEN_0F381A_P_2_M_0
,
1855 VEX_LEN_0F385A_P_2_M_0
,
1858 VEX_LEN_0F38F3_R_1_P_0
,
1859 VEX_LEN_0F38F3_R_2_P_0
,
1860 VEX_LEN_0F38F3_R_3_P_0
,
1903 VEX_LEN_0FXOP_08_CC
,
1904 VEX_LEN_0FXOP_08_CD
,
1905 VEX_LEN_0FXOP_08_CE
,
1906 VEX_LEN_0FXOP_08_CF
,
1907 VEX_LEN_0FXOP_08_EC
,
1908 VEX_LEN_0FXOP_08_ED
,
1909 VEX_LEN_0FXOP_08_EE
,
1910 VEX_LEN_0FXOP_08_EF
,
1911 VEX_LEN_0FXOP_09_80
,
1917 EVEX_LEN_0F6E_P_2
= 0,
1921 EVEX_LEN_0F3819_P_2_W_0
,
1922 EVEX_LEN_0F3819_P_2_W_1
,
1923 EVEX_LEN_0F381A_P_2_W_0
,
1924 EVEX_LEN_0F381A_P_2_W_1
,
1925 EVEX_LEN_0F381B_P_2_W_0
,
1926 EVEX_LEN_0F381B_P_2_W_1
,
1927 EVEX_LEN_0F385A_P_2_W_0
,
1928 EVEX_LEN_0F385A_P_2_W_1
,
1929 EVEX_LEN_0F385B_P_2_W_0
,
1930 EVEX_LEN_0F385B_P_2_W_1
,
1931 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1932 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1933 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1934 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1935 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1936 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1937 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1938 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1939 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1940 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1941 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1942 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1943 EVEX_LEN_0F3A18_P_2_W_0
,
1944 EVEX_LEN_0F3A18_P_2_W_1
,
1945 EVEX_LEN_0F3A19_P_2_W_0
,
1946 EVEX_LEN_0F3A19_P_2_W_1
,
1947 EVEX_LEN_0F3A1A_P_2_W_0
,
1948 EVEX_LEN_0F3A1A_P_2_W_1
,
1949 EVEX_LEN_0F3A1B_P_2_W_0
,
1950 EVEX_LEN_0F3A1B_P_2_W_1
,
1951 EVEX_LEN_0F3A23_P_2_W_0
,
1952 EVEX_LEN_0F3A23_P_2_W_1
,
1953 EVEX_LEN_0F3A38_P_2_W_0
,
1954 EVEX_LEN_0F3A38_P_2_W_1
,
1955 EVEX_LEN_0F3A39_P_2_W_0
,
1956 EVEX_LEN_0F3A39_P_2_W_1
,
1957 EVEX_LEN_0F3A3A_P_2_W_0
,
1958 EVEX_LEN_0F3A3A_P_2_W_1
,
1959 EVEX_LEN_0F3A3B_P_2_W_0
,
1960 EVEX_LEN_0F3A3B_P_2_W_1
,
1961 EVEX_LEN_0F3A43_P_2_W_0
,
1962 EVEX_LEN_0F3A43_P_2_W_1
1967 VEX_W_0F41_P_0_LEN_1
= 0,
1968 VEX_W_0F41_P_2_LEN_1
,
1969 VEX_W_0F42_P_0_LEN_1
,
1970 VEX_W_0F42_P_2_LEN_1
,
1971 VEX_W_0F44_P_0_LEN_0
,
1972 VEX_W_0F44_P_2_LEN_0
,
1973 VEX_W_0F45_P_0_LEN_1
,
1974 VEX_W_0F45_P_2_LEN_1
,
1975 VEX_W_0F46_P_0_LEN_1
,
1976 VEX_W_0F46_P_2_LEN_1
,
1977 VEX_W_0F47_P_0_LEN_1
,
1978 VEX_W_0F47_P_2_LEN_1
,
1979 VEX_W_0F4A_P_0_LEN_1
,
1980 VEX_W_0F4A_P_2_LEN_1
,
1981 VEX_W_0F4B_P_0_LEN_1
,
1982 VEX_W_0F4B_P_2_LEN_1
,
1983 VEX_W_0F90_P_0_LEN_0
,
1984 VEX_W_0F90_P_2_LEN_0
,
1985 VEX_W_0F91_P_0_LEN_0
,
1986 VEX_W_0F91_P_2_LEN_0
,
1987 VEX_W_0F92_P_0_LEN_0
,
1988 VEX_W_0F92_P_2_LEN_0
,
1989 VEX_W_0F93_P_0_LEN_0
,
1990 VEX_W_0F93_P_2_LEN_0
,
1991 VEX_W_0F98_P_0_LEN_0
,
1992 VEX_W_0F98_P_2_LEN_0
,
1993 VEX_W_0F99_P_0_LEN_0
,
1994 VEX_W_0F99_P_2_LEN_0
,
2002 VEX_W_0F381A_P_2_M_0
,
2003 VEX_W_0F382C_P_2_M_0
,
2004 VEX_W_0F382D_P_2_M_0
,
2005 VEX_W_0F382E_P_2_M_0
,
2006 VEX_W_0F382F_P_2_M_0
,
2011 VEX_W_0F385A_P_2_M_0
,
2023 VEX_W_0F3A30_P_2_LEN_0
,
2024 VEX_W_0F3A31_P_2_LEN_0
,
2025 VEX_W_0F3A32_P_2_LEN_0
,
2026 VEX_W_0F3A33_P_2_LEN_0
,
2042 EVEX_W_0F12_P_0_M_1
,
2045 EVEX_W_0F16_P_0_M_1
,
2079 EVEX_W_0F72_R_2_P_2
,
2080 EVEX_W_0F72_R_6_P_2
,
2081 EVEX_W_0F73_R_2_P_2
,
2082 EVEX_W_0F73_R_6_P_2
,
2188 EVEX_W_0F38C7_R_1_P_2
,
2189 EVEX_W_0F38C7_R_2_P_2
,
2190 EVEX_W_0F38C7_R_5_P_2
,
2191 EVEX_W_0F38C7_R_6_P_2
,
2230 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2239 unsigned int prefix_requirement
;
2242 /* Upper case letters in the instruction names here are macros.
2243 'A' => print 'b' if no register operands or suffix_always is true
2244 'B' => print 'b' if suffix_always is true
2245 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2247 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2248 suffix_always is true
2249 'E' => print 'e' if 32-bit form of jcxz
2250 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2251 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2252 'H' => print ",pt" or ",pn" branch hint
2255 'K' => print 'd' or 'q' if rex prefix is present.
2256 'L' => print 'l' if suffix_always is true
2257 'M' => print 'r' if intel_mnemonic is false.
2258 'N' => print 'n' if instruction has no wait "prefix"
2259 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2260 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2261 or suffix_always is true. print 'q' if rex prefix is present.
2262 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2264 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2265 'S' => print 'w', 'l' or 'q' if suffix_always is true
2266 'T' => print 'q' in 64bit mode if instruction has no operand size
2267 prefix and behave as 'P' otherwise
2268 'U' => print 'q' in 64bit mode if instruction has no operand size
2269 prefix and behave as 'Q' otherwise
2270 'V' => print 'q' in 64bit mode if instruction has no operand size
2271 prefix and behave as 'S' otherwise
2272 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2273 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2275 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2276 '!' => change condition from true to false or from false to true.
2277 '%' => add 1 upper case letter to the macro.
2278 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2279 prefix or suffix_always is true (lcall/ljmp).
2280 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2281 on operand size prefix.
2282 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2283 has no operand size prefix for AMD64 ISA, behave as 'P'
2286 2 upper case letter macros:
2287 "XY" => print 'x' or 'y' if suffix_always is true or no register
2288 operands and no broadcast.
2289 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2290 register operands and no broadcast.
2291 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2292 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2293 operand or no operand at all in 64bit mode, or if suffix_always
2295 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2296 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2297 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2298 "LW" => print 'd', 'q' depending on the VEX.W bit
2299 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2300 an operand size prefix, or suffix_always is true. print
2301 'q' if rex prefix is present.
2303 Many of the above letters print nothing in Intel mode. See "putop"
2306 Braces '{' and '}', and vertical bars '|', indicate alternative
2307 mnemonic strings for AT&T and Intel. */
2309 static const struct dis386 dis386
[] = {
2311 { "addB", { Ebh1
, Gb
}, 0 },
2312 { "addS", { Evh1
, Gv
}, 0 },
2313 { "addB", { Gb
, EbS
}, 0 },
2314 { "addS", { Gv
, EvS
}, 0 },
2315 { "addB", { AL
, Ib
}, 0 },
2316 { "addS", { eAX
, Iv
}, 0 },
2317 { X86_64_TABLE (X86_64_06
) },
2318 { X86_64_TABLE (X86_64_07
) },
2320 { "orB", { Ebh1
, Gb
}, 0 },
2321 { "orS", { Evh1
, Gv
}, 0 },
2322 { "orB", { Gb
, EbS
}, 0 },
2323 { "orS", { Gv
, EvS
}, 0 },
2324 { "orB", { AL
, Ib
}, 0 },
2325 { "orS", { eAX
, Iv
}, 0 },
2326 { X86_64_TABLE (X86_64_0E
) },
2327 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2329 { "adcB", { Ebh1
, Gb
}, 0 },
2330 { "adcS", { Evh1
, Gv
}, 0 },
2331 { "adcB", { Gb
, EbS
}, 0 },
2332 { "adcS", { Gv
, EvS
}, 0 },
2333 { "adcB", { AL
, Ib
}, 0 },
2334 { "adcS", { eAX
, Iv
}, 0 },
2335 { X86_64_TABLE (X86_64_16
) },
2336 { X86_64_TABLE (X86_64_17
) },
2338 { "sbbB", { Ebh1
, Gb
}, 0 },
2339 { "sbbS", { Evh1
, Gv
}, 0 },
2340 { "sbbB", { Gb
, EbS
}, 0 },
2341 { "sbbS", { Gv
, EvS
}, 0 },
2342 { "sbbB", { AL
, Ib
}, 0 },
2343 { "sbbS", { eAX
, Iv
}, 0 },
2344 { X86_64_TABLE (X86_64_1E
) },
2345 { X86_64_TABLE (X86_64_1F
) },
2347 { "andB", { Ebh1
, Gb
}, 0 },
2348 { "andS", { Evh1
, Gv
}, 0 },
2349 { "andB", { Gb
, EbS
}, 0 },
2350 { "andS", { Gv
, EvS
}, 0 },
2351 { "andB", { AL
, Ib
}, 0 },
2352 { "andS", { eAX
, Iv
}, 0 },
2353 { Bad_Opcode
}, /* SEG ES prefix */
2354 { X86_64_TABLE (X86_64_27
) },
2356 { "subB", { Ebh1
, Gb
}, 0 },
2357 { "subS", { Evh1
, Gv
}, 0 },
2358 { "subB", { Gb
, EbS
}, 0 },
2359 { "subS", { Gv
, EvS
}, 0 },
2360 { "subB", { AL
, Ib
}, 0 },
2361 { "subS", { eAX
, Iv
}, 0 },
2362 { Bad_Opcode
}, /* SEG CS prefix */
2363 { X86_64_TABLE (X86_64_2F
) },
2365 { "xorB", { Ebh1
, Gb
}, 0 },
2366 { "xorS", { Evh1
, Gv
}, 0 },
2367 { "xorB", { Gb
, EbS
}, 0 },
2368 { "xorS", { Gv
, EvS
}, 0 },
2369 { "xorB", { AL
, Ib
}, 0 },
2370 { "xorS", { eAX
, Iv
}, 0 },
2371 { Bad_Opcode
}, /* SEG SS prefix */
2372 { X86_64_TABLE (X86_64_37
) },
2374 { "cmpB", { Eb
, Gb
}, 0 },
2375 { "cmpS", { Ev
, Gv
}, 0 },
2376 { "cmpB", { Gb
, EbS
}, 0 },
2377 { "cmpS", { Gv
, EvS
}, 0 },
2378 { "cmpB", { AL
, Ib
}, 0 },
2379 { "cmpS", { eAX
, Iv
}, 0 },
2380 { Bad_Opcode
}, /* SEG DS prefix */
2381 { X86_64_TABLE (X86_64_3F
) },
2383 { "inc{S|}", { RMeAX
}, 0 },
2384 { "inc{S|}", { RMeCX
}, 0 },
2385 { "inc{S|}", { RMeDX
}, 0 },
2386 { "inc{S|}", { RMeBX
}, 0 },
2387 { "inc{S|}", { RMeSP
}, 0 },
2388 { "inc{S|}", { RMeBP
}, 0 },
2389 { "inc{S|}", { RMeSI
}, 0 },
2390 { "inc{S|}", { RMeDI
}, 0 },
2392 { "dec{S|}", { RMeAX
}, 0 },
2393 { "dec{S|}", { RMeCX
}, 0 },
2394 { "dec{S|}", { RMeDX
}, 0 },
2395 { "dec{S|}", { RMeBX
}, 0 },
2396 { "dec{S|}", { RMeSP
}, 0 },
2397 { "dec{S|}", { RMeBP
}, 0 },
2398 { "dec{S|}", { RMeSI
}, 0 },
2399 { "dec{S|}", { RMeDI
}, 0 },
2401 { "pushV", { RMrAX
}, 0 },
2402 { "pushV", { RMrCX
}, 0 },
2403 { "pushV", { RMrDX
}, 0 },
2404 { "pushV", { RMrBX
}, 0 },
2405 { "pushV", { RMrSP
}, 0 },
2406 { "pushV", { RMrBP
}, 0 },
2407 { "pushV", { RMrSI
}, 0 },
2408 { "pushV", { RMrDI
}, 0 },
2410 { "popV", { RMrAX
}, 0 },
2411 { "popV", { RMrCX
}, 0 },
2412 { "popV", { RMrDX
}, 0 },
2413 { "popV", { RMrBX
}, 0 },
2414 { "popV", { RMrSP
}, 0 },
2415 { "popV", { RMrBP
}, 0 },
2416 { "popV", { RMrSI
}, 0 },
2417 { "popV", { RMrDI
}, 0 },
2419 { X86_64_TABLE (X86_64_60
) },
2420 { X86_64_TABLE (X86_64_61
) },
2421 { X86_64_TABLE (X86_64_62
) },
2422 { X86_64_TABLE (X86_64_63
) },
2423 { Bad_Opcode
}, /* seg fs */
2424 { Bad_Opcode
}, /* seg gs */
2425 { Bad_Opcode
}, /* op size prefix */
2426 { Bad_Opcode
}, /* adr size prefix */
2428 { "pushT", { sIv
}, 0 },
2429 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2430 { "pushT", { sIbT
}, 0 },
2431 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2432 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2433 { X86_64_TABLE (X86_64_6D
) },
2434 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2435 { X86_64_TABLE (X86_64_6F
) },
2437 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2438 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2439 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2440 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2441 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2442 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2443 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2444 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2446 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2447 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2448 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2449 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2450 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2451 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2452 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2453 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2455 { REG_TABLE (REG_80
) },
2456 { REG_TABLE (REG_81
) },
2457 { X86_64_TABLE (X86_64_82
) },
2458 { REG_TABLE (REG_83
) },
2459 { "testB", { Eb
, Gb
}, 0 },
2460 { "testS", { Ev
, Gv
}, 0 },
2461 { "xchgB", { Ebh2
, Gb
}, 0 },
2462 { "xchgS", { Evh2
, Gv
}, 0 },
2464 { "movB", { Ebh3
, Gb
}, 0 },
2465 { "movS", { Evh3
, Gv
}, 0 },
2466 { "movB", { Gb
, EbS
}, 0 },
2467 { "movS", { Gv
, EvS
}, 0 },
2468 { "movD", { Sv
, Sw
}, 0 },
2469 { MOD_TABLE (MOD_8D
) },
2470 { "movD", { Sw
, Sv
}, 0 },
2471 { REG_TABLE (REG_8F
) },
2473 { PREFIX_TABLE (PREFIX_90
) },
2474 { "xchgS", { RMeCX
, eAX
}, 0 },
2475 { "xchgS", { RMeDX
, eAX
}, 0 },
2476 { "xchgS", { RMeBX
, eAX
}, 0 },
2477 { "xchgS", { RMeSP
, eAX
}, 0 },
2478 { "xchgS", { RMeBP
, eAX
}, 0 },
2479 { "xchgS", { RMeSI
, eAX
}, 0 },
2480 { "xchgS", { RMeDI
, eAX
}, 0 },
2482 { "cW{t|}R", { XX
}, 0 },
2483 { "cR{t|}O", { XX
}, 0 },
2484 { X86_64_TABLE (X86_64_9A
) },
2485 { Bad_Opcode
}, /* fwait */
2486 { "pushfT", { XX
}, 0 },
2487 { "popfT", { XX
}, 0 },
2488 { "sahf", { XX
}, 0 },
2489 { "lahf", { XX
}, 0 },
2491 { "mov%LB", { AL
, Ob
}, 0 },
2492 { "mov%LS", { eAX
, Ov
}, 0 },
2493 { "mov%LB", { Ob
, AL
}, 0 },
2494 { "mov%LS", { Ov
, eAX
}, 0 },
2495 { "movs{b|}", { Ybr
, Xb
}, 0 },
2496 { "movs{R|}", { Yvr
, Xv
}, 0 },
2497 { "cmps{b|}", { Xb
, Yb
}, 0 },
2498 { "cmps{R|}", { Xv
, Yv
}, 0 },
2500 { "testB", { AL
, Ib
}, 0 },
2501 { "testS", { eAX
, Iv
}, 0 },
2502 { "stosB", { Ybr
, AL
}, 0 },
2503 { "stosS", { Yvr
, eAX
}, 0 },
2504 { "lodsB", { ALr
, Xb
}, 0 },
2505 { "lodsS", { eAXr
, Xv
}, 0 },
2506 { "scasB", { AL
, Yb
}, 0 },
2507 { "scasS", { eAX
, Yv
}, 0 },
2509 { "movB", { RMAL
, Ib
}, 0 },
2510 { "movB", { RMCL
, Ib
}, 0 },
2511 { "movB", { RMDL
, Ib
}, 0 },
2512 { "movB", { RMBL
, Ib
}, 0 },
2513 { "movB", { RMAH
, Ib
}, 0 },
2514 { "movB", { RMCH
, Ib
}, 0 },
2515 { "movB", { RMDH
, Ib
}, 0 },
2516 { "movB", { RMBH
, Ib
}, 0 },
2518 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2519 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2520 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2521 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2522 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2523 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2524 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2525 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2527 { REG_TABLE (REG_C0
) },
2528 { REG_TABLE (REG_C1
) },
2529 { X86_64_TABLE (X86_64_C2
) },
2530 { X86_64_TABLE (X86_64_C3
) },
2531 { X86_64_TABLE (X86_64_C4
) },
2532 { X86_64_TABLE (X86_64_C5
) },
2533 { REG_TABLE (REG_C6
) },
2534 { REG_TABLE (REG_C7
) },
2536 { "enterT", { Iw
, Ib
}, 0 },
2537 { "leaveT", { XX
}, 0 },
2538 { "{l|}ret{|f}P", { Iw
}, 0 },
2539 { "{l|}ret{|f}P", { XX
}, 0 },
2540 { "int3", { XX
}, 0 },
2541 { "int", { Ib
}, 0 },
2542 { X86_64_TABLE (X86_64_CE
) },
2543 { "iret%LP", { XX
}, 0 },
2545 { REG_TABLE (REG_D0
) },
2546 { REG_TABLE (REG_D1
) },
2547 { REG_TABLE (REG_D2
) },
2548 { REG_TABLE (REG_D3
) },
2549 { X86_64_TABLE (X86_64_D4
) },
2550 { X86_64_TABLE (X86_64_D5
) },
2552 { "xlat", { DSBX
}, 0 },
2563 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2564 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2565 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2566 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2567 { "inB", { AL
, Ib
}, 0 },
2568 { "inG", { zAX
, Ib
}, 0 },
2569 { "outB", { Ib
, AL
}, 0 },
2570 { "outG", { Ib
, zAX
}, 0 },
2572 { X86_64_TABLE (X86_64_E8
) },
2573 { X86_64_TABLE (X86_64_E9
) },
2574 { X86_64_TABLE (X86_64_EA
) },
2575 { "jmp", { Jb
, BND
}, 0 },
2576 { "inB", { AL
, indirDX
}, 0 },
2577 { "inG", { zAX
, indirDX
}, 0 },
2578 { "outB", { indirDX
, AL
}, 0 },
2579 { "outG", { indirDX
, zAX
}, 0 },
2581 { Bad_Opcode
}, /* lock prefix */
2582 { "icebp", { XX
}, 0 },
2583 { Bad_Opcode
}, /* repne */
2584 { Bad_Opcode
}, /* repz */
2585 { "hlt", { XX
}, 0 },
2586 { "cmc", { XX
}, 0 },
2587 { REG_TABLE (REG_F6
) },
2588 { REG_TABLE (REG_F7
) },
2590 { "clc", { XX
}, 0 },
2591 { "stc", { XX
}, 0 },
2592 { "cli", { XX
}, 0 },
2593 { "sti", { XX
}, 0 },
2594 { "cld", { XX
}, 0 },
2595 { "std", { XX
}, 0 },
2596 { REG_TABLE (REG_FE
) },
2597 { REG_TABLE (REG_FF
) },
2600 static const struct dis386 dis386_twobyte
[] = {
2602 { REG_TABLE (REG_0F00
) },
2603 { REG_TABLE (REG_0F01
) },
2604 { "larS", { Gv
, Ew
}, 0 },
2605 { "lslS", { Gv
, Ew
}, 0 },
2607 { "syscall", { XX
}, 0 },
2608 { "clts", { XX
}, 0 },
2609 { "sysret%LQ", { XX
}, 0 },
2611 { "invd", { XX
}, 0 },
2612 { PREFIX_TABLE (PREFIX_0F09
) },
2614 { "ud2", { XX
}, 0 },
2616 { REG_TABLE (REG_0F0D
) },
2617 { "femms", { XX
}, 0 },
2618 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2620 { PREFIX_TABLE (PREFIX_0F10
) },
2621 { PREFIX_TABLE (PREFIX_0F11
) },
2622 { PREFIX_TABLE (PREFIX_0F12
) },
2623 { MOD_TABLE (MOD_0F13
) },
2624 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2625 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2626 { PREFIX_TABLE (PREFIX_0F16
) },
2627 { MOD_TABLE (MOD_0F17
) },
2629 { REG_TABLE (REG_0F18
) },
2630 { "nopQ", { Ev
}, 0 },
2631 { PREFIX_TABLE (PREFIX_0F1A
) },
2632 { PREFIX_TABLE (PREFIX_0F1B
) },
2633 { PREFIX_TABLE (PREFIX_0F1C
) },
2634 { "nopQ", { Ev
}, 0 },
2635 { PREFIX_TABLE (PREFIX_0F1E
) },
2636 { "nopQ", { Ev
}, 0 },
2638 { "movZ", { Rm
, Cm
}, 0 },
2639 { "movZ", { Rm
, Dm
}, 0 },
2640 { "movZ", { Cm
, Rm
}, 0 },
2641 { "movZ", { Dm
, Rm
}, 0 },
2642 { MOD_TABLE (MOD_0F24
) },
2644 { MOD_TABLE (MOD_0F26
) },
2647 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2648 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2649 { PREFIX_TABLE (PREFIX_0F2A
) },
2650 { PREFIX_TABLE (PREFIX_0F2B
) },
2651 { PREFIX_TABLE (PREFIX_0F2C
) },
2652 { PREFIX_TABLE (PREFIX_0F2D
) },
2653 { PREFIX_TABLE (PREFIX_0F2E
) },
2654 { PREFIX_TABLE (PREFIX_0F2F
) },
2656 { "wrmsr", { XX
}, 0 },
2657 { "rdtsc", { XX
}, 0 },
2658 { "rdmsr", { XX
}, 0 },
2659 { "rdpmc", { XX
}, 0 },
2660 { "sysenter", { SEP
}, 0 },
2661 { "sysexit", { SEP
}, 0 },
2663 { "getsec", { XX
}, 0 },
2665 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2667 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2674 { "cmovoS", { Gv
, Ev
}, 0 },
2675 { "cmovnoS", { Gv
, Ev
}, 0 },
2676 { "cmovbS", { Gv
, Ev
}, 0 },
2677 { "cmovaeS", { Gv
, Ev
}, 0 },
2678 { "cmoveS", { Gv
, Ev
}, 0 },
2679 { "cmovneS", { Gv
, Ev
}, 0 },
2680 { "cmovbeS", { Gv
, Ev
}, 0 },
2681 { "cmovaS", { Gv
, Ev
}, 0 },
2683 { "cmovsS", { Gv
, Ev
}, 0 },
2684 { "cmovnsS", { Gv
, Ev
}, 0 },
2685 { "cmovpS", { Gv
, Ev
}, 0 },
2686 { "cmovnpS", { Gv
, Ev
}, 0 },
2687 { "cmovlS", { Gv
, Ev
}, 0 },
2688 { "cmovgeS", { Gv
, Ev
}, 0 },
2689 { "cmovleS", { Gv
, Ev
}, 0 },
2690 { "cmovgS", { Gv
, Ev
}, 0 },
2692 { MOD_TABLE (MOD_0F50
) },
2693 { PREFIX_TABLE (PREFIX_0F51
) },
2694 { PREFIX_TABLE (PREFIX_0F52
) },
2695 { PREFIX_TABLE (PREFIX_0F53
) },
2696 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2697 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2698 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2699 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2701 { PREFIX_TABLE (PREFIX_0F58
) },
2702 { PREFIX_TABLE (PREFIX_0F59
) },
2703 { PREFIX_TABLE (PREFIX_0F5A
) },
2704 { PREFIX_TABLE (PREFIX_0F5B
) },
2705 { PREFIX_TABLE (PREFIX_0F5C
) },
2706 { PREFIX_TABLE (PREFIX_0F5D
) },
2707 { PREFIX_TABLE (PREFIX_0F5E
) },
2708 { PREFIX_TABLE (PREFIX_0F5F
) },
2710 { PREFIX_TABLE (PREFIX_0F60
) },
2711 { PREFIX_TABLE (PREFIX_0F61
) },
2712 { PREFIX_TABLE (PREFIX_0F62
) },
2713 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2714 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2715 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2716 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2717 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2719 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2720 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2721 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2722 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2723 { PREFIX_TABLE (PREFIX_0F6C
) },
2724 { PREFIX_TABLE (PREFIX_0F6D
) },
2725 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2726 { PREFIX_TABLE (PREFIX_0F6F
) },
2728 { PREFIX_TABLE (PREFIX_0F70
) },
2729 { REG_TABLE (REG_0F71
) },
2730 { REG_TABLE (REG_0F72
) },
2731 { REG_TABLE (REG_0F73
) },
2732 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2733 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2734 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2735 { "emms", { XX
}, PREFIX_OPCODE
},
2737 { PREFIX_TABLE (PREFIX_0F78
) },
2738 { PREFIX_TABLE (PREFIX_0F79
) },
2741 { PREFIX_TABLE (PREFIX_0F7C
) },
2742 { PREFIX_TABLE (PREFIX_0F7D
) },
2743 { PREFIX_TABLE (PREFIX_0F7E
) },
2744 { PREFIX_TABLE (PREFIX_0F7F
) },
2746 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2747 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2748 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2749 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2750 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2751 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2752 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2753 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2755 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2756 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2757 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2758 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2759 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2760 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2761 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2762 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2764 { "seto", { Eb
}, 0 },
2765 { "setno", { Eb
}, 0 },
2766 { "setb", { Eb
}, 0 },
2767 { "setae", { Eb
}, 0 },
2768 { "sete", { Eb
}, 0 },
2769 { "setne", { Eb
}, 0 },
2770 { "setbe", { Eb
}, 0 },
2771 { "seta", { Eb
}, 0 },
2773 { "sets", { Eb
}, 0 },
2774 { "setns", { Eb
}, 0 },
2775 { "setp", { Eb
}, 0 },
2776 { "setnp", { Eb
}, 0 },
2777 { "setl", { Eb
}, 0 },
2778 { "setge", { Eb
}, 0 },
2779 { "setle", { Eb
}, 0 },
2780 { "setg", { Eb
}, 0 },
2782 { "pushT", { fs
}, 0 },
2783 { "popT", { fs
}, 0 },
2784 { "cpuid", { XX
}, 0 },
2785 { "btS", { Ev
, Gv
}, 0 },
2786 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2787 { "shldS", { Ev
, Gv
, CL
}, 0 },
2788 { REG_TABLE (REG_0FA6
) },
2789 { REG_TABLE (REG_0FA7
) },
2791 { "pushT", { gs
}, 0 },
2792 { "popT", { gs
}, 0 },
2793 { "rsm", { XX
}, 0 },
2794 { "btsS", { Evh1
, Gv
}, 0 },
2795 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2796 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2797 { REG_TABLE (REG_0FAE
) },
2798 { "imulS", { Gv
, Ev
}, 0 },
2800 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2801 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2802 { MOD_TABLE (MOD_0FB2
) },
2803 { "btrS", { Evh1
, Gv
}, 0 },
2804 { MOD_TABLE (MOD_0FB4
) },
2805 { MOD_TABLE (MOD_0FB5
) },
2806 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2807 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2809 { PREFIX_TABLE (PREFIX_0FB8
) },
2810 { "ud1S", { Gv
, Ev
}, 0 },
2811 { REG_TABLE (REG_0FBA
) },
2812 { "btcS", { Evh1
, Gv
}, 0 },
2813 { PREFIX_TABLE (PREFIX_0FBC
) },
2814 { PREFIX_TABLE (PREFIX_0FBD
) },
2815 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2816 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2818 { "xaddB", { Ebh1
, Gb
}, 0 },
2819 { "xaddS", { Evh1
, Gv
}, 0 },
2820 { PREFIX_TABLE (PREFIX_0FC2
) },
2821 { MOD_TABLE (MOD_0FC3
) },
2822 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2823 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2824 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2825 { REG_TABLE (REG_0FC7
) },
2827 { "bswap", { RMeAX
}, 0 },
2828 { "bswap", { RMeCX
}, 0 },
2829 { "bswap", { RMeDX
}, 0 },
2830 { "bswap", { RMeBX
}, 0 },
2831 { "bswap", { RMeSP
}, 0 },
2832 { "bswap", { RMeBP
}, 0 },
2833 { "bswap", { RMeSI
}, 0 },
2834 { "bswap", { RMeDI
}, 0 },
2836 { PREFIX_TABLE (PREFIX_0FD0
) },
2837 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2838 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2839 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2840 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2841 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2842 { PREFIX_TABLE (PREFIX_0FD6
) },
2843 { MOD_TABLE (MOD_0FD7
) },
2845 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2846 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2847 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2848 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2849 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2850 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2851 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2852 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2854 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2855 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2856 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2857 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2858 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2859 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2860 { PREFIX_TABLE (PREFIX_0FE6
) },
2861 { PREFIX_TABLE (PREFIX_0FE7
) },
2863 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2864 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2865 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2866 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2867 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2868 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2869 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2870 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2872 { PREFIX_TABLE (PREFIX_0FF0
) },
2873 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2874 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2875 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2876 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2877 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2878 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2879 { PREFIX_TABLE (PREFIX_0FF7
) },
2881 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2882 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2883 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2884 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2885 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2886 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2887 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2888 { "ud0S", { Gv
, Ev
}, 0 },
2891 static const unsigned char onebyte_has_modrm
[256] = {
2892 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2893 /* ------------------------------- */
2894 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2895 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2896 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2897 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2898 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2899 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2900 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2901 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2902 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2903 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2904 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2905 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2906 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2907 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2908 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2909 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2910 /* ------------------------------- */
2911 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2914 static const unsigned char twobyte_has_modrm
[256] = {
2915 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2916 /* ------------------------------- */
2917 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2918 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2919 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2920 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2921 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2922 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2923 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2924 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2925 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2926 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2927 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2928 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2929 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2930 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2931 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2932 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2933 /* ------------------------------- */
2934 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2937 static char obuf
[100];
2939 static char *mnemonicendp
;
2940 static char scratchbuf
[100];
2941 static unsigned char *start_codep
;
2942 static unsigned char *insn_codep
;
2943 static unsigned char *codep
;
2944 static unsigned char *end_codep
;
2945 static int last_lock_prefix
;
2946 static int last_repz_prefix
;
2947 static int last_repnz_prefix
;
2948 static int last_data_prefix
;
2949 static int last_addr_prefix
;
2950 static int last_rex_prefix
;
2951 static int last_seg_prefix
;
2952 static int fwait_prefix
;
2953 /* The active segment register prefix. */
2954 static int active_seg_prefix
;
2955 #define MAX_CODE_LENGTH 15
2956 /* We can up to 14 prefixes since the maximum instruction length is
2958 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2959 static disassemble_info
*the_info
;
2967 static unsigned char need_modrm
;
2977 int register_specifier
;
2984 int mask_register_specifier
;
2990 static unsigned char need_vex
;
2991 static unsigned char need_vex_reg
;
2992 static unsigned char vex_w_done
;
3000 /* If we are accessing mod/rm/reg without need_modrm set, then the
3001 values are stale. Hitting this abort likely indicates that you
3002 need to update onebyte_has_modrm or twobyte_has_modrm. */
3003 #define MODRM_CHECK if (!need_modrm) abort ()
3005 static const char **names64
;
3006 static const char **names32
;
3007 static const char **names16
;
3008 static const char **names8
;
3009 static const char **names8rex
;
3010 static const char **names_seg
;
3011 static const char *index64
;
3012 static const char *index32
;
3013 static const char **index16
;
3014 static const char **names_bnd
;
3016 static const char *intel_names64
[] = {
3017 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3018 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3020 static const char *intel_names32
[] = {
3021 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3022 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3024 static const char *intel_names16
[] = {
3025 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3026 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3028 static const char *intel_names8
[] = {
3029 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3031 static const char *intel_names8rex
[] = {
3032 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3033 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3035 static const char *intel_names_seg
[] = {
3036 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3038 static const char *intel_index64
= "riz";
3039 static const char *intel_index32
= "eiz";
3040 static const char *intel_index16
[] = {
3041 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3044 static const char *att_names64
[] = {
3045 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3046 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3048 static const char *att_names32
[] = {
3049 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3050 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3052 static const char *att_names16
[] = {
3053 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3054 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3056 static const char *att_names8
[] = {
3057 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3059 static const char *att_names8rex
[] = {
3060 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3061 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3063 static const char *att_names_seg
[] = {
3064 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3066 static const char *att_index64
= "%riz";
3067 static const char *att_index32
= "%eiz";
3068 static const char *att_index16
[] = {
3069 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3072 static const char **names_mm
;
3073 static const char *intel_names_mm
[] = {
3074 "mm0", "mm1", "mm2", "mm3",
3075 "mm4", "mm5", "mm6", "mm7"
3077 static const char *att_names_mm
[] = {
3078 "%mm0", "%mm1", "%mm2", "%mm3",
3079 "%mm4", "%mm5", "%mm6", "%mm7"
3082 static const char *intel_names_bnd
[] = {
3083 "bnd0", "bnd1", "bnd2", "bnd3"
3086 static const char *att_names_bnd
[] = {
3087 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3090 static const char **names_xmm
;
3091 static const char *intel_names_xmm
[] = {
3092 "xmm0", "xmm1", "xmm2", "xmm3",
3093 "xmm4", "xmm5", "xmm6", "xmm7",
3094 "xmm8", "xmm9", "xmm10", "xmm11",
3095 "xmm12", "xmm13", "xmm14", "xmm15",
3096 "xmm16", "xmm17", "xmm18", "xmm19",
3097 "xmm20", "xmm21", "xmm22", "xmm23",
3098 "xmm24", "xmm25", "xmm26", "xmm27",
3099 "xmm28", "xmm29", "xmm30", "xmm31"
3101 static const char *att_names_xmm
[] = {
3102 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3103 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3104 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3105 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3106 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3107 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3108 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3109 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3112 static const char **names_ymm
;
3113 static const char *intel_names_ymm
[] = {
3114 "ymm0", "ymm1", "ymm2", "ymm3",
3115 "ymm4", "ymm5", "ymm6", "ymm7",
3116 "ymm8", "ymm9", "ymm10", "ymm11",
3117 "ymm12", "ymm13", "ymm14", "ymm15",
3118 "ymm16", "ymm17", "ymm18", "ymm19",
3119 "ymm20", "ymm21", "ymm22", "ymm23",
3120 "ymm24", "ymm25", "ymm26", "ymm27",
3121 "ymm28", "ymm29", "ymm30", "ymm31"
3123 static const char *att_names_ymm
[] = {
3124 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3125 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3126 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3127 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3128 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3129 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3130 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3131 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3134 static const char **names_zmm
;
3135 static const char *intel_names_zmm
[] = {
3136 "zmm0", "zmm1", "zmm2", "zmm3",
3137 "zmm4", "zmm5", "zmm6", "zmm7",
3138 "zmm8", "zmm9", "zmm10", "zmm11",
3139 "zmm12", "zmm13", "zmm14", "zmm15",
3140 "zmm16", "zmm17", "zmm18", "zmm19",
3141 "zmm20", "zmm21", "zmm22", "zmm23",
3142 "zmm24", "zmm25", "zmm26", "zmm27",
3143 "zmm28", "zmm29", "zmm30", "zmm31"
3145 static const char *att_names_zmm
[] = {
3146 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3147 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3148 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3149 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3150 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3151 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3152 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3153 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3156 static const char **names_mask
;
3157 static const char *intel_names_mask
[] = {
3158 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3160 static const char *att_names_mask
[] = {
3161 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3164 static const char *names_rounding
[] =
3172 static const struct dis386 reg_table
[][8] = {
3175 { "addA", { Ebh1
, Ib
}, 0 },
3176 { "orA", { Ebh1
, Ib
}, 0 },
3177 { "adcA", { Ebh1
, Ib
}, 0 },
3178 { "sbbA", { Ebh1
, Ib
}, 0 },
3179 { "andA", { Ebh1
, Ib
}, 0 },
3180 { "subA", { Ebh1
, Ib
}, 0 },
3181 { "xorA", { Ebh1
, Ib
}, 0 },
3182 { "cmpA", { Eb
, Ib
}, 0 },
3186 { "addQ", { Evh1
, Iv
}, 0 },
3187 { "orQ", { Evh1
, Iv
}, 0 },
3188 { "adcQ", { Evh1
, Iv
}, 0 },
3189 { "sbbQ", { Evh1
, Iv
}, 0 },
3190 { "andQ", { Evh1
, Iv
}, 0 },
3191 { "subQ", { Evh1
, Iv
}, 0 },
3192 { "xorQ", { Evh1
, Iv
}, 0 },
3193 { "cmpQ", { Ev
, Iv
}, 0 },
3197 { "addQ", { Evh1
, sIb
}, 0 },
3198 { "orQ", { Evh1
, sIb
}, 0 },
3199 { "adcQ", { Evh1
, sIb
}, 0 },
3200 { "sbbQ", { Evh1
, sIb
}, 0 },
3201 { "andQ", { Evh1
, sIb
}, 0 },
3202 { "subQ", { Evh1
, sIb
}, 0 },
3203 { "xorQ", { Evh1
, sIb
}, 0 },
3204 { "cmpQ", { Ev
, sIb
}, 0 },
3208 { "popU", { stackEv
}, 0 },
3209 { XOP_8F_TABLE (XOP_09
) },
3213 { XOP_8F_TABLE (XOP_09
) },
3217 { "rolA", { Eb
, Ib
}, 0 },
3218 { "rorA", { Eb
, Ib
}, 0 },
3219 { "rclA", { Eb
, Ib
}, 0 },
3220 { "rcrA", { Eb
, Ib
}, 0 },
3221 { "shlA", { Eb
, Ib
}, 0 },
3222 { "shrA", { Eb
, Ib
}, 0 },
3223 { "shlA", { Eb
, Ib
}, 0 },
3224 { "sarA", { Eb
, Ib
}, 0 },
3228 { "rolQ", { Ev
, Ib
}, 0 },
3229 { "rorQ", { Ev
, Ib
}, 0 },
3230 { "rclQ", { Ev
, Ib
}, 0 },
3231 { "rcrQ", { Ev
, Ib
}, 0 },
3232 { "shlQ", { Ev
, Ib
}, 0 },
3233 { "shrQ", { Ev
, Ib
}, 0 },
3234 { "shlQ", { Ev
, Ib
}, 0 },
3235 { "sarQ", { Ev
, Ib
}, 0 },
3239 { "movA", { Ebh3
, Ib
}, 0 },
3246 { MOD_TABLE (MOD_C6_REG_7
) },
3250 { "movQ", { Evh3
, Iv
}, 0 },
3257 { MOD_TABLE (MOD_C7_REG_7
) },
3261 { "rolA", { Eb
, I1
}, 0 },
3262 { "rorA", { Eb
, I1
}, 0 },
3263 { "rclA", { Eb
, I1
}, 0 },
3264 { "rcrA", { Eb
, I1
}, 0 },
3265 { "shlA", { Eb
, I1
}, 0 },
3266 { "shrA", { Eb
, I1
}, 0 },
3267 { "shlA", { Eb
, I1
}, 0 },
3268 { "sarA", { Eb
, I1
}, 0 },
3272 { "rolQ", { Ev
, I1
}, 0 },
3273 { "rorQ", { Ev
, I1
}, 0 },
3274 { "rclQ", { Ev
, I1
}, 0 },
3275 { "rcrQ", { Ev
, I1
}, 0 },
3276 { "shlQ", { Ev
, I1
}, 0 },
3277 { "shrQ", { Ev
, I1
}, 0 },
3278 { "shlQ", { Ev
, I1
}, 0 },
3279 { "sarQ", { Ev
, I1
}, 0 },
3283 { "rolA", { Eb
, CL
}, 0 },
3284 { "rorA", { Eb
, CL
}, 0 },
3285 { "rclA", { Eb
, CL
}, 0 },
3286 { "rcrA", { Eb
, CL
}, 0 },
3287 { "shlA", { Eb
, CL
}, 0 },
3288 { "shrA", { Eb
, CL
}, 0 },
3289 { "shlA", { Eb
, CL
}, 0 },
3290 { "sarA", { Eb
, CL
}, 0 },
3294 { "rolQ", { Ev
, CL
}, 0 },
3295 { "rorQ", { Ev
, CL
}, 0 },
3296 { "rclQ", { Ev
, CL
}, 0 },
3297 { "rcrQ", { Ev
, CL
}, 0 },
3298 { "shlQ", { Ev
, CL
}, 0 },
3299 { "shrQ", { Ev
, CL
}, 0 },
3300 { "shlQ", { Ev
, CL
}, 0 },
3301 { "sarQ", { Ev
, CL
}, 0 },
3305 { "testA", { Eb
, Ib
}, 0 },
3306 { "testA", { Eb
, Ib
}, 0 },
3307 { "notA", { Ebh1
}, 0 },
3308 { "negA", { Ebh1
}, 0 },
3309 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3310 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3311 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3312 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3316 { "testQ", { Ev
, Iv
}, 0 },
3317 { "testQ", { Ev
, Iv
}, 0 },
3318 { "notQ", { Evh1
}, 0 },
3319 { "negQ", { Evh1
}, 0 },
3320 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3321 { "imulQ", { Ev
}, 0 },
3322 { "divQ", { Ev
}, 0 },
3323 { "idivQ", { Ev
}, 0 },
3327 { "incA", { Ebh1
}, 0 },
3328 { "decA", { Ebh1
}, 0 },
3332 { "incQ", { Evh1
}, 0 },
3333 { "decQ", { Evh1
}, 0 },
3334 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3335 { MOD_TABLE (MOD_FF_REG_3
) },
3336 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3337 { MOD_TABLE (MOD_FF_REG_5
) },
3338 { "pushU", { stackEv
}, 0 },
3343 { "sldtD", { Sv
}, 0 },
3344 { "strD", { Sv
}, 0 },
3345 { "lldt", { Ew
}, 0 },
3346 { "ltr", { Ew
}, 0 },
3347 { "verr", { Ew
}, 0 },
3348 { "verw", { Ew
}, 0 },
3354 { MOD_TABLE (MOD_0F01_REG_0
) },
3355 { MOD_TABLE (MOD_0F01_REG_1
) },
3356 { MOD_TABLE (MOD_0F01_REG_2
) },
3357 { MOD_TABLE (MOD_0F01_REG_3
) },
3358 { "smswD", { Sv
}, 0 },
3359 { MOD_TABLE (MOD_0F01_REG_5
) },
3360 { "lmsw", { Ew
}, 0 },
3361 { MOD_TABLE (MOD_0F01_REG_7
) },
3365 { "prefetch", { Mb
}, 0 },
3366 { "prefetchw", { Mb
}, 0 },
3367 { "prefetchwt1", { Mb
}, 0 },
3368 { "prefetch", { Mb
}, 0 },
3369 { "prefetch", { Mb
}, 0 },
3370 { "prefetch", { Mb
}, 0 },
3371 { "prefetch", { Mb
}, 0 },
3372 { "prefetch", { Mb
}, 0 },
3376 { MOD_TABLE (MOD_0F18_REG_0
) },
3377 { MOD_TABLE (MOD_0F18_REG_1
) },
3378 { MOD_TABLE (MOD_0F18_REG_2
) },
3379 { MOD_TABLE (MOD_0F18_REG_3
) },
3380 { MOD_TABLE (MOD_0F18_REG_4
) },
3381 { MOD_TABLE (MOD_0F18_REG_5
) },
3382 { MOD_TABLE (MOD_0F18_REG_6
) },
3383 { MOD_TABLE (MOD_0F18_REG_7
) },
3385 /* REG_0F1C_P_0_MOD_0 */
3387 { "cldemote", { Mb
}, 0 },
3388 { "nopQ", { Ev
}, 0 },
3389 { "nopQ", { Ev
}, 0 },
3390 { "nopQ", { Ev
}, 0 },
3391 { "nopQ", { Ev
}, 0 },
3392 { "nopQ", { Ev
}, 0 },
3393 { "nopQ", { Ev
}, 0 },
3394 { "nopQ", { Ev
}, 0 },
3396 /* REG_0F1E_P_1_MOD_3 */
3398 { "nopQ", { Ev
}, 0 },
3399 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3400 { "nopQ", { Ev
}, 0 },
3401 { "nopQ", { Ev
}, 0 },
3402 { "nopQ", { Ev
}, 0 },
3403 { "nopQ", { Ev
}, 0 },
3404 { "nopQ", { Ev
}, 0 },
3405 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3411 { MOD_TABLE (MOD_0F71_REG_2
) },
3413 { MOD_TABLE (MOD_0F71_REG_4
) },
3415 { MOD_TABLE (MOD_0F71_REG_6
) },
3421 { MOD_TABLE (MOD_0F72_REG_2
) },
3423 { MOD_TABLE (MOD_0F72_REG_4
) },
3425 { MOD_TABLE (MOD_0F72_REG_6
) },
3431 { MOD_TABLE (MOD_0F73_REG_2
) },
3432 { MOD_TABLE (MOD_0F73_REG_3
) },
3435 { MOD_TABLE (MOD_0F73_REG_6
) },
3436 { MOD_TABLE (MOD_0F73_REG_7
) },
3440 { "montmul", { { OP_0f07
, 0 } }, 0 },
3441 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3442 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3446 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3447 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3448 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3449 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3450 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3451 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3455 { MOD_TABLE (MOD_0FAE_REG_0
) },
3456 { MOD_TABLE (MOD_0FAE_REG_1
) },
3457 { MOD_TABLE (MOD_0FAE_REG_2
) },
3458 { MOD_TABLE (MOD_0FAE_REG_3
) },
3459 { MOD_TABLE (MOD_0FAE_REG_4
) },
3460 { MOD_TABLE (MOD_0FAE_REG_5
) },
3461 { MOD_TABLE (MOD_0FAE_REG_6
) },
3462 { MOD_TABLE (MOD_0FAE_REG_7
) },
3470 { "btQ", { Ev
, Ib
}, 0 },
3471 { "btsQ", { Evh1
, Ib
}, 0 },
3472 { "btrQ", { Evh1
, Ib
}, 0 },
3473 { "btcQ", { Evh1
, Ib
}, 0 },
3478 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3480 { MOD_TABLE (MOD_0FC7_REG_3
) },
3481 { MOD_TABLE (MOD_0FC7_REG_4
) },
3482 { MOD_TABLE (MOD_0FC7_REG_5
) },
3483 { MOD_TABLE (MOD_0FC7_REG_6
) },
3484 { MOD_TABLE (MOD_0FC7_REG_7
) },
3490 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3492 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3494 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3500 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3502 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3504 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3510 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3511 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3514 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3515 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3521 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3522 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3524 /* REG_VEX_0F38F3 */
3527 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3528 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3529 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3533 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3534 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3538 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3539 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3541 /* REG_XOP_TBM_01 */
3544 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3545 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3546 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3547 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3548 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3549 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3550 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3552 /* REG_XOP_TBM_02 */
3555 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3560 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3563 #include "i386-dis-evex-reg.h"
3566 static const struct dis386 prefix_table
[][4] = {
3569 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3570 { "pause", { XX
}, 0 },
3571 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3572 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3575 /* PREFIX_0F01_REG_3_RM_1 */
3577 { "vmmcall", { Skip_MODRM
}, 0 },
3578 { "vmgexit", { Skip_MODRM
}, 0 },
3580 { "vmgexit", { Skip_MODRM
}, 0 },
3583 /* PREFIX_0F01_REG_5_MOD_0 */
3586 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3589 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3591 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3592 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3594 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3597 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3602 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3605 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3608 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3611 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3613 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3614 { "mcommit", { Skip_MODRM
}, 0 },
3617 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3619 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3624 { "wbinvd", { XX
}, 0 },
3625 { "wbnoinvd", { XX
}, 0 },
3630 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3631 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3632 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3633 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3638 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3639 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3640 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3641 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3646 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3647 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3648 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3649 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3654 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3655 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3656 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3661 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3662 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3663 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3664 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3669 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3670 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3671 { "bndmov", { EbndS
, Gbnd
}, 0 },
3672 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3677 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3678 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3679 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3680 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3685 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3686 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3687 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3688 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3693 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3694 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3695 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3696 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3701 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3702 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3703 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3704 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3709 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3710 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3711 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3712 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3717 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3718 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3719 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3720 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3725 { "ucomiss",{ XM
, EXd
}, 0 },
3727 { "ucomisd",{ XM
, EXq
}, 0 },
3732 { "comiss", { XM
, EXd
}, 0 },
3734 { "comisd", { XM
, EXq
}, 0 },
3739 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3740 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3741 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3742 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3747 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3748 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3753 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3754 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3759 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3760 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3761 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3762 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3767 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3768 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3769 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3770 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3775 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3776 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3777 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3778 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3783 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3784 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3785 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3790 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3791 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3792 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3793 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3798 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3799 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3800 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3801 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3806 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3807 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3808 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3809 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3814 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3815 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3816 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3817 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3822 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3824 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3829 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3831 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3836 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3838 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3845 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3852 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3857 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3858 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3859 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3864 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3865 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3866 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3867 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3870 /* PREFIX_0F73_REG_3 */
3874 { "psrldq", { XS
, Ib
}, 0 },
3877 /* PREFIX_0F73_REG_7 */
3881 { "pslldq", { XS
, Ib
}, 0 },
3886 {"vmread", { Em
, Gm
}, 0 },
3888 {"extrq", { XS
, Ib
, Ib
}, 0 },
3889 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3894 {"vmwrite", { Gm
, Em
}, 0 },
3896 {"extrq", { XM
, XS
}, 0 },
3897 {"insertq", { XM
, XS
}, 0 },
3904 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3905 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3912 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3913 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3918 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3919 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3920 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3925 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3926 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3927 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3930 /* PREFIX_0FAE_REG_0_MOD_3 */
3933 { "rdfsbase", { Ev
}, 0 },
3936 /* PREFIX_0FAE_REG_1_MOD_3 */
3939 { "rdgsbase", { Ev
}, 0 },
3942 /* PREFIX_0FAE_REG_2_MOD_3 */
3945 { "wrfsbase", { Ev
}, 0 },
3948 /* PREFIX_0FAE_REG_3_MOD_3 */
3951 { "wrgsbase", { Ev
}, 0 },
3954 /* PREFIX_0FAE_REG_4_MOD_0 */
3956 { "xsave", { FXSAVE
}, 0 },
3957 { "ptwrite%LQ", { Edq
}, 0 },
3960 /* PREFIX_0FAE_REG_4_MOD_3 */
3963 { "ptwrite%LQ", { Edq
}, 0 },
3966 /* PREFIX_0FAE_REG_5_MOD_0 */
3968 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
3971 /* PREFIX_0FAE_REG_5_MOD_3 */
3973 { "lfence", { Skip_MODRM
}, 0 },
3974 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
3977 /* PREFIX_0FAE_REG_6_MOD_0 */
3979 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3980 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3981 { "clwb", { Mb
}, PREFIX_OPCODE
},
3984 /* PREFIX_0FAE_REG_6_MOD_3 */
3986 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3987 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3988 { "tpause", { Edq
}, PREFIX_OPCODE
},
3989 { "umwait", { Edq
}, PREFIX_OPCODE
},
3992 /* PREFIX_0FAE_REG_7_MOD_0 */
3994 { "clflush", { Mb
}, 0 },
3996 { "clflushopt", { Mb
}, 0 },
4002 { "popcntS", { Gv
, Ev
}, 0 },
4007 { "bsfS", { Gv
, Ev
}, 0 },
4008 { "tzcntS", { Gv
, Ev
}, 0 },
4009 { "bsfS", { Gv
, Ev
}, 0 },
4014 { "bsrS", { Gv
, Ev
}, 0 },
4015 { "lzcntS", { Gv
, Ev
}, 0 },
4016 { "bsrS", { Gv
, Ev
}, 0 },
4021 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4022 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4023 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4024 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4027 /* PREFIX_0FC3_MOD_0 */
4029 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4032 /* PREFIX_0FC7_REG_6_MOD_0 */
4034 { "vmptrld",{ Mq
}, 0 },
4035 { "vmxon", { Mq
}, 0 },
4036 { "vmclear",{ Mq
}, 0 },
4039 /* PREFIX_0FC7_REG_6_MOD_3 */
4041 { "rdrand", { Ev
}, 0 },
4043 { "rdrand", { Ev
}, 0 }
4046 /* PREFIX_0FC7_REG_7_MOD_3 */
4048 { "rdseed", { Ev
}, 0 },
4049 { "rdpid", { Em
}, 0 },
4050 { "rdseed", { Ev
}, 0 },
4057 { "addsubpd", { XM
, EXx
}, 0 },
4058 { "addsubps", { XM
, EXx
}, 0 },
4064 { "movq2dq",{ XM
, MS
}, 0 },
4065 { "movq", { EXqS
, XM
}, 0 },
4066 { "movdq2q",{ MX
, XS
}, 0 },
4072 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4073 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4074 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4079 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4081 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4089 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4094 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4096 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4103 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4110 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4117 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4124 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4131 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4138 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4145 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4152 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4159 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4166 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4173 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4180 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4187 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4194 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4201 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4208 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4215 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4222 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4229 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4236 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4243 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4250 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4257 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4264 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4271 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4278 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4285 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4292 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4299 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4306 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4313 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4320 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4327 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4334 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4339 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4344 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4349 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4354 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4359 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4364 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4371 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4378 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4385 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4392 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4399 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4406 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4411 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4413 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4414 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4419 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4421 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4422 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4429 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4434 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4435 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4436 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4443 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4444 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4445 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4450 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4457 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4464 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4471 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4478 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4485 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4492 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4499 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4506 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4513 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4520 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4527 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4534 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4541 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4548 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4555 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4562 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4569 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4576 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4583 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4590 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4597 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4604 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4609 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4616 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4623 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4630 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4633 /* PREFIX_VEX_0F10 */
4635 { "vmovups", { XM
, EXx
}, 0 },
4636 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4637 { "vmovupd", { XM
, EXx
}, 0 },
4638 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4641 /* PREFIX_VEX_0F11 */
4643 { "vmovups", { EXxS
, XM
}, 0 },
4644 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4645 { "vmovupd", { EXxS
, XM
}, 0 },
4646 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4649 /* PREFIX_VEX_0F12 */
4651 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4652 { "vmovsldup", { XM
, EXx
}, 0 },
4653 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
4654 { "vmovddup", { XM
, EXymmq
}, 0 },
4657 /* PREFIX_VEX_0F16 */
4659 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4660 { "vmovshdup", { XM
, EXx
}, 0 },
4661 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
4664 /* PREFIX_VEX_0F2A */
4667 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4669 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4672 /* PREFIX_VEX_0F2C */
4675 { "vcvttss2si", { Gdq
, EXdScalar
}, 0 },
4677 { "vcvttsd2si", { Gdq
, EXqScalar
}, 0 },
4680 /* PREFIX_VEX_0F2D */
4683 { "vcvtss2si", { Gdq
, EXdScalar
}, 0 },
4685 { "vcvtsd2si", { Gdq
, EXqScalar
}, 0 },
4688 /* PREFIX_VEX_0F2E */
4690 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4692 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4695 /* PREFIX_VEX_0F2F */
4697 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4699 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4702 /* PREFIX_VEX_0F41 */
4704 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4706 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4709 /* PREFIX_VEX_0F42 */
4711 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4713 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4716 /* PREFIX_VEX_0F44 */
4718 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4720 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4723 /* PREFIX_VEX_0F45 */
4725 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4727 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4730 /* PREFIX_VEX_0F46 */
4732 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4734 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4737 /* PREFIX_VEX_0F47 */
4739 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4741 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4744 /* PREFIX_VEX_0F4A */
4746 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4748 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4751 /* PREFIX_VEX_0F4B */
4753 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4755 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4758 /* PREFIX_VEX_0F51 */
4760 { "vsqrtps", { XM
, EXx
}, 0 },
4761 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4762 { "vsqrtpd", { XM
, EXx
}, 0 },
4763 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4766 /* PREFIX_VEX_0F52 */
4768 { "vrsqrtps", { XM
, EXx
}, 0 },
4769 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4772 /* PREFIX_VEX_0F53 */
4774 { "vrcpps", { XM
, EXx
}, 0 },
4775 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4778 /* PREFIX_VEX_0F58 */
4780 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4781 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4782 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4783 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4786 /* PREFIX_VEX_0F59 */
4788 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4789 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4790 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4791 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4794 /* PREFIX_VEX_0F5A */
4796 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4797 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4798 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4799 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4802 /* PREFIX_VEX_0F5B */
4804 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4805 { "vcvttps2dq", { XM
, EXx
}, 0 },
4806 { "vcvtps2dq", { XM
, EXx
}, 0 },
4809 /* PREFIX_VEX_0F5C */
4811 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4812 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4813 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4814 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4817 /* PREFIX_VEX_0F5D */
4819 { "vminps", { XM
, Vex
, EXx
}, 0 },
4820 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4821 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4822 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4825 /* PREFIX_VEX_0F5E */
4827 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4828 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4829 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4830 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4833 /* PREFIX_VEX_0F5F */
4835 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4836 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4837 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4838 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4841 /* PREFIX_VEX_0F60 */
4845 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4848 /* PREFIX_VEX_0F61 */
4852 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4855 /* PREFIX_VEX_0F62 */
4859 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4862 /* PREFIX_VEX_0F63 */
4866 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4869 /* PREFIX_VEX_0F64 */
4873 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4876 /* PREFIX_VEX_0F65 */
4880 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4883 /* PREFIX_VEX_0F66 */
4887 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4890 /* PREFIX_VEX_0F67 */
4894 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4897 /* PREFIX_VEX_0F68 */
4901 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4904 /* PREFIX_VEX_0F69 */
4908 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4911 /* PREFIX_VEX_0F6A */
4915 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4918 /* PREFIX_VEX_0F6B */
4922 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4925 /* PREFIX_VEX_0F6C */
4929 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4932 /* PREFIX_VEX_0F6D */
4936 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4939 /* PREFIX_VEX_0F6E */
4943 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4946 /* PREFIX_VEX_0F6F */
4949 { "vmovdqu", { XM
, EXx
}, 0 },
4950 { "vmovdqa", { XM
, EXx
}, 0 },
4953 /* PREFIX_VEX_0F70 */
4956 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4957 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4958 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4961 /* PREFIX_VEX_0F71_REG_2 */
4965 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
4968 /* PREFIX_VEX_0F71_REG_4 */
4972 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
4975 /* PREFIX_VEX_0F71_REG_6 */
4979 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
4982 /* PREFIX_VEX_0F72_REG_2 */
4986 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
4989 /* PREFIX_VEX_0F72_REG_4 */
4993 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
4996 /* PREFIX_VEX_0F72_REG_6 */
5000 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5003 /* PREFIX_VEX_0F73_REG_2 */
5007 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5010 /* PREFIX_VEX_0F73_REG_3 */
5014 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5017 /* PREFIX_VEX_0F73_REG_6 */
5021 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5024 /* PREFIX_VEX_0F73_REG_7 */
5028 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5031 /* PREFIX_VEX_0F74 */
5035 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5038 /* PREFIX_VEX_0F75 */
5042 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5045 /* PREFIX_VEX_0F76 */
5049 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5052 /* PREFIX_VEX_0F77 */
5054 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5057 /* PREFIX_VEX_0F7C */
5061 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5062 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5065 /* PREFIX_VEX_0F7D */
5069 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5070 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5073 /* PREFIX_VEX_0F7E */
5076 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5077 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5080 /* PREFIX_VEX_0F7F */
5083 { "vmovdqu", { EXxS
, XM
}, 0 },
5084 { "vmovdqa", { EXxS
, XM
}, 0 },
5087 /* PREFIX_VEX_0F90 */
5089 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5091 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5094 /* PREFIX_VEX_0F91 */
5096 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5098 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5101 /* PREFIX_VEX_0F92 */
5103 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5105 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5106 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5109 /* PREFIX_VEX_0F93 */
5111 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5113 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5114 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5117 /* PREFIX_VEX_0F98 */
5119 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5121 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5124 /* PREFIX_VEX_0F99 */
5126 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5128 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5131 /* PREFIX_VEX_0FC2 */
5133 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5134 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5135 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5136 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5139 /* PREFIX_VEX_0FC4 */
5143 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5146 /* PREFIX_VEX_0FC5 */
5150 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5153 /* PREFIX_VEX_0FD0 */
5157 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5158 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5161 /* PREFIX_VEX_0FD1 */
5165 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5168 /* PREFIX_VEX_0FD2 */
5172 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5175 /* PREFIX_VEX_0FD3 */
5179 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5182 /* PREFIX_VEX_0FD4 */
5186 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5189 /* PREFIX_VEX_0FD5 */
5193 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5196 /* PREFIX_VEX_0FD6 */
5200 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5203 /* PREFIX_VEX_0FD7 */
5207 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5210 /* PREFIX_VEX_0FD8 */
5214 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5217 /* PREFIX_VEX_0FD9 */
5221 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5224 /* PREFIX_VEX_0FDA */
5228 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5231 /* PREFIX_VEX_0FDB */
5235 { "vpand", { XM
, Vex
, EXx
}, 0 },
5238 /* PREFIX_VEX_0FDC */
5242 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5245 /* PREFIX_VEX_0FDD */
5249 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5252 /* PREFIX_VEX_0FDE */
5256 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5259 /* PREFIX_VEX_0FDF */
5263 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5266 /* PREFIX_VEX_0FE0 */
5270 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5273 /* PREFIX_VEX_0FE1 */
5277 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5280 /* PREFIX_VEX_0FE2 */
5284 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5287 /* PREFIX_VEX_0FE3 */
5291 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5294 /* PREFIX_VEX_0FE4 */
5298 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5301 /* PREFIX_VEX_0FE5 */
5305 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5308 /* PREFIX_VEX_0FE6 */
5311 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5312 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5313 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5316 /* PREFIX_VEX_0FE7 */
5320 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5323 /* PREFIX_VEX_0FE8 */
5327 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5330 /* PREFIX_VEX_0FE9 */
5334 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5337 /* PREFIX_VEX_0FEA */
5341 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5344 /* PREFIX_VEX_0FEB */
5348 { "vpor", { XM
, Vex
, EXx
}, 0 },
5351 /* PREFIX_VEX_0FEC */
5355 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5358 /* PREFIX_VEX_0FED */
5362 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5365 /* PREFIX_VEX_0FEE */
5369 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5372 /* PREFIX_VEX_0FEF */
5376 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5379 /* PREFIX_VEX_0FF0 */
5384 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5387 /* PREFIX_VEX_0FF1 */
5391 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5394 /* PREFIX_VEX_0FF2 */
5398 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5401 /* PREFIX_VEX_0FF3 */
5405 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5408 /* PREFIX_VEX_0FF4 */
5412 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5415 /* PREFIX_VEX_0FF5 */
5419 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5422 /* PREFIX_VEX_0FF6 */
5426 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5429 /* PREFIX_VEX_0FF7 */
5433 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5436 /* PREFIX_VEX_0FF8 */
5440 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5443 /* PREFIX_VEX_0FF9 */
5447 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5450 /* PREFIX_VEX_0FFA */
5454 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5457 /* PREFIX_VEX_0FFB */
5461 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5464 /* PREFIX_VEX_0FFC */
5468 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5471 /* PREFIX_VEX_0FFD */
5475 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5478 /* PREFIX_VEX_0FFE */
5482 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5485 /* PREFIX_VEX_0F3800 */
5489 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5492 /* PREFIX_VEX_0F3801 */
5496 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5499 /* PREFIX_VEX_0F3802 */
5503 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5506 /* PREFIX_VEX_0F3803 */
5510 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5513 /* PREFIX_VEX_0F3804 */
5517 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5520 /* PREFIX_VEX_0F3805 */
5524 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5527 /* PREFIX_VEX_0F3806 */
5531 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5534 /* PREFIX_VEX_0F3807 */
5538 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5541 /* PREFIX_VEX_0F3808 */
5545 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5548 /* PREFIX_VEX_0F3809 */
5552 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5555 /* PREFIX_VEX_0F380A */
5559 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5562 /* PREFIX_VEX_0F380B */
5566 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5569 /* PREFIX_VEX_0F380C */
5573 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5576 /* PREFIX_VEX_0F380D */
5580 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5583 /* PREFIX_VEX_0F380E */
5587 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5590 /* PREFIX_VEX_0F380F */
5594 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5597 /* PREFIX_VEX_0F3813 */
5601 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5604 /* PREFIX_VEX_0F3816 */
5608 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5611 /* PREFIX_VEX_0F3817 */
5615 { "vptest", { XM
, EXx
}, 0 },
5618 /* PREFIX_VEX_0F3818 */
5622 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5625 /* PREFIX_VEX_0F3819 */
5629 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5632 /* PREFIX_VEX_0F381A */
5636 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5639 /* PREFIX_VEX_0F381C */
5643 { "vpabsb", { XM
, EXx
}, 0 },
5646 /* PREFIX_VEX_0F381D */
5650 { "vpabsw", { XM
, EXx
}, 0 },
5653 /* PREFIX_VEX_0F381E */
5657 { "vpabsd", { XM
, EXx
}, 0 },
5660 /* PREFIX_VEX_0F3820 */
5664 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5667 /* PREFIX_VEX_0F3821 */
5671 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5674 /* PREFIX_VEX_0F3822 */
5678 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5681 /* PREFIX_VEX_0F3823 */
5685 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5688 /* PREFIX_VEX_0F3824 */
5692 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5695 /* PREFIX_VEX_0F3825 */
5699 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5702 /* PREFIX_VEX_0F3828 */
5706 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5709 /* PREFIX_VEX_0F3829 */
5713 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5716 /* PREFIX_VEX_0F382A */
5720 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5723 /* PREFIX_VEX_0F382B */
5727 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5730 /* PREFIX_VEX_0F382C */
5734 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5737 /* PREFIX_VEX_0F382D */
5741 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5744 /* PREFIX_VEX_0F382E */
5748 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5751 /* PREFIX_VEX_0F382F */
5755 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5758 /* PREFIX_VEX_0F3830 */
5762 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5765 /* PREFIX_VEX_0F3831 */
5769 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5772 /* PREFIX_VEX_0F3832 */
5776 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5779 /* PREFIX_VEX_0F3833 */
5783 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5786 /* PREFIX_VEX_0F3834 */
5790 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5793 /* PREFIX_VEX_0F3835 */
5797 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5800 /* PREFIX_VEX_0F3836 */
5804 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5807 /* PREFIX_VEX_0F3837 */
5811 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5814 /* PREFIX_VEX_0F3838 */
5818 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5821 /* PREFIX_VEX_0F3839 */
5825 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5828 /* PREFIX_VEX_0F383A */
5832 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5835 /* PREFIX_VEX_0F383B */
5839 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5842 /* PREFIX_VEX_0F383C */
5846 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5849 /* PREFIX_VEX_0F383D */
5853 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5856 /* PREFIX_VEX_0F383E */
5860 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5863 /* PREFIX_VEX_0F383F */
5867 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5870 /* PREFIX_VEX_0F3840 */
5874 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5877 /* PREFIX_VEX_0F3841 */
5881 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5884 /* PREFIX_VEX_0F3845 */
5888 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5891 /* PREFIX_VEX_0F3846 */
5895 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5898 /* PREFIX_VEX_0F3847 */
5902 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5905 /* PREFIX_VEX_0F3858 */
5909 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5912 /* PREFIX_VEX_0F3859 */
5916 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5919 /* PREFIX_VEX_0F385A */
5923 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5926 /* PREFIX_VEX_0F3878 */
5930 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5933 /* PREFIX_VEX_0F3879 */
5937 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5940 /* PREFIX_VEX_0F388C */
5944 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5947 /* PREFIX_VEX_0F388E */
5951 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5954 /* PREFIX_VEX_0F3890 */
5958 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5961 /* PREFIX_VEX_0F3891 */
5965 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5968 /* PREFIX_VEX_0F3892 */
5972 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5975 /* PREFIX_VEX_0F3893 */
5979 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5982 /* PREFIX_VEX_0F3896 */
5986 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
5989 /* PREFIX_VEX_0F3897 */
5993 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
5996 /* PREFIX_VEX_0F3898 */
6000 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6003 /* PREFIX_VEX_0F3899 */
6007 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6010 /* PREFIX_VEX_0F389A */
6014 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6017 /* PREFIX_VEX_0F389B */
6021 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6024 /* PREFIX_VEX_0F389C */
6028 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6031 /* PREFIX_VEX_0F389D */
6035 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6038 /* PREFIX_VEX_0F389E */
6042 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6045 /* PREFIX_VEX_0F389F */
6049 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6052 /* PREFIX_VEX_0F38A6 */
6056 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6060 /* PREFIX_VEX_0F38A7 */
6064 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6067 /* PREFIX_VEX_0F38A8 */
6071 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6074 /* PREFIX_VEX_0F38A9 */
6078 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6081 /* PREFIX_VEX_0F38AA */
6085 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6088 /* PREFIX_VEX_0F38AB */
6092 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6095 /* PREFIX_VEX_0F38AC */
6099 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6102 /* PREFIX_VEX_0F38AD */
6106 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6109 /* PREFIX_VEX_0F38AE */
6113 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6116 /* PREFIX_VEX_0F38AF */
6120 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6123 /* PREFIX_VEX_0F38B6 */
6127 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6130 /* PREFIX_VEX_0F38B7 */
6134 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6137 /* PREFIX_VEX_0F38B8 */
6141 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6144 /* PREFIX_VEX_0F38B9 */
6148 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6151 /* PREFIX_VEX_0F38BA */
6155 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6158 /* PREFIX_VEX_0F38BB */
6162 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6165 /* PREFIX_VEX_0F38BC */
6169 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6172 /* PREFIX_VEX_0F38BD */
6176 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6179 /* PREFIX_VEX_0F38BE */
6183 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6186 /* PREFIX_VEX_0F38BF */
6190 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6193 /* PREFIX_VEX_0F38CF */
6197 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6200 /* PREFIX_VEX_0F38DB */
6204 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6207 /* PREFIX_VEX_0F38DC */
6211 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6214 /* PREFIX_VEX_0F38DD */
6218 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6221 /* PREFIX_VEX_0F38DE */
6225 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6228 /* PREFIX_VEX_0F38DF */
6232 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6235 /* PREFIX_VEX_0F38F2 */
6237 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6240 /* PREFIX_VEX_0F38F3_REG_1 */
6242 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6245 /* PREFIX_VEX_0F38F3_REG_2 */
6247 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6250 /* PREFIX_VEX_0F38F3_REG_3 */
6252 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6255 /* PREFIX_VEX_0F38F5 */
6257 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6258 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6260 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6263 /* PREFIX_VEX_0F38F6 */
6268 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6271 /* PREFIX_VEX_0F38F7 */
6273 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6274 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6275 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6276 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6279 /* PREFIX_VEX_0F3A00 */
6283 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6286 /* PREFIX_VEX_0F3A01 */
6290 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6293 /* PREFIX_VEX_0F3A02 */
6297 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6300 /* PREFIX_VEX_0F3A04 */
6304 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6307 /* PREFIX_VEX_0F3A05 */
6311 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6314 /* PREFIX_VEX_0F3A06 */
6318 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6321 /* PREFIX_VEX_0F3A08 */
6325 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6328 /* PREFIX_VEX_0F3A09 */
6332 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6335 /* PREFIX_VEX_0F3A0A */
6339 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6342 /* PREFIX_VEX_0F3A0B */
6346 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6349 /* PREFIX_VEX_0F3A0C */
6353 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6356 /* PREFIX_VEX_0F3A0D */
6360 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6363 /* PREFIX_VEX_0F3A0E */
6367 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6370 /* PREFIX_VEX_0F3A0F */
6374 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6377 /* PREFIX_VEX_0F3A14 */
6381 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6384 /* PREFIX_VEX_0F3A15 */
6388 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6391 /* PREFIX_VEX_0F3A16 */
6395 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6398 /* PREFIX_VEX_0F3A17 */
6402 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6405 /* PREFIX_VEX_0F3A18 */
6409 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6412 /* PREFIX_VEX_0F3A19 */
6416 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6419 /* PREFIX_VEX_0F3A1D */
6423 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6426 /* PREFIX_VEX_0F3A20 */
6430 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6433 /* PREFIX_VEX_0F3A21 */
6437 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6440 /* PREFIX_VEX_0F3A22 */
6444 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6447 /* PREFIX_VEX_0F3A30 */
6451 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6454 /* PREFIX_VEX_0F3A31 */
6458 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6461 /* PREFIX_VEX_0F3A32 */
6465 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6468 /* PREFIX_VEX_0F3A33 */
6472 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6475 /* PREFIX_VEX_0F3A38 */
6479 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6482 /* PREFIX_VEX_0F3A39 */
6486 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6489 /* PREFIX_VEX_0F3A40 */
6493 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6496 /* PREFIX_VEX_0F3A41 */
6500 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6503 /* PREFIX_VEX_0F3A42 */
6507 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6510 /* PREFIX_VEX_0F3A44 */
6514 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6517 /* PREFIX_VEX_0F3A46 */
6521 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6524 /* PREFIX_VEX_0F3A48 */
6528 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6531 /* PREFIX_VEX_0F3A49 */
6535 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6538 /* PREFIX_VEX_0F3A4A */
6542 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6545 /* PREFIX_VEX_0F3A4B */
6549 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6552 /* PREFIX_VEX_0F3A4C */
6556 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6559 /* PREFIX_VEX_0F3A5C */
6563 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6566 /* PREFIX_VEX_0F3A5D */
6570 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6573 /* PREFIX_VEX_0F3A5E */
6577 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6580 /* PREFIX_VEX_0F3A5F */
6584 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6587 /* PREFIX_VEX_0F3A60 */
6591 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6595 /* PREFIX_VEX_0F3A61 */
6599 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6602 /* PREFIX_VEX_0F3A62 */
6606 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6609 /* PREFIX_VEX_0F3A63 */
6613 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6616 /* PREFIX_VEX_0F3A68 */
6620 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6623 /* PREFIX_VEX_0F3A69 */
6627 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6630 /* PREFIX_VEX_0F3A6A */
6634 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6637 /* PREFIX_VEX_0F3A6B */
6641 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6644 /* PREFIX_VEX_0F3A6C */
6648 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6651 /* PREFIX_VEX_0F3A6D */
6655 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6658 /* PREFIX_VEX_0F3A6E */
6662 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6665 /* PREFIX_VEX_0F3A6F */
6669 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6672 /* PREFIX_VEX_0F3A78 */
6676 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6679 /* PREFIX_VEX_0F3A79 */
6683 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6686 /* PREFIX_VEX_0F3A7A */
6690 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6693 /* PREFIX_VEX_0F3A7B */
6697 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6700 /* PREFIX_VEX_0F3A7C */
6704 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6708 /* PREFIX_VEX_0F3A7D */
6712 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6715 /* PREFIX_VEX_0F3A7E */
6719 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6722 /* PREFIX_VEX_0F3A7F */
6726 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6729 /* PREFIX_VEX_0F3ACE */
6733 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6736 /* PREFIX_VEX_0F3ACF */
6740 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6743 /* PREFIX_VEX_0F3ADF */
6747 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6750 /* PREFIX_VEX_0F3AF0 */
6755 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6758 #include "i386-dis-evex-prefix.h"
6761 static const struct dis386 x86_64_table
[][2] = {
6764 { "pushP", { es
}, 0 },
6769 { "popP", { es
}, 0 },
6774 { "pushP", { cs
}, 0 },
6779 { "pushP", { ss
}, 0 },
6784 { "popP", { ss
}, 0 },
6789 { "pushP", { ds
}, 0 },
6794 { "popP", { ds
}, 0 },
6799 { "daa", { XX
}, 0 },
6804 { "das", { XX
}, 0 },
6809 { "aaa", { XX
}, 0 },
6814 { "aas", { XX
}, 0 },
6819 { "pushaP", { XX
}, 0 },
6824 { "popaP", { XX
}, 0 },
6829 { MOD_TABLE (MOD_62_32BIT
) },
6830 { EVEX_TABLE (EVEX_0F
) },
6835 { "arpl", { Ew
, Gw
}, 0 },
6836 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
6841 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6842 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6847 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6848 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6853 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6854 { REG_TABLE (REG_80
) },
6859 { "{l|}call{T|}", { Ap
}, 0 },
6864 { "retP", { Iw
, BND
}, 0 },
6865 { "ret@", { Iw
, BND
}, 0 },
6870 { "retP", { BND
}, 0 },
6871 { "ret@", { BND
}, 0 },
6876 { MOD_TABLE (MOD_C4_32BIT
) },
6877 { VEX_C4_TABLE (VEX_0F
) },
6882 { MOD_TABLE (MOD_C5_32BIT
) },
6883 { VEX_C5_TABLE (VEX_0F
) },
6888 { "into", { XX
}, 0 },
6893 { "aam", { Ib
}, 0 },
6898 { "aad", { Ib
}, 0 },
6903 { "callP", { Jv
, BND
}, 0 },
6904 { "call@", { Jv
, BND
}, 0 }
6909 { "jmpP", { Jv
, BND
}, 0 },
6910 { "jmp@", { Jv
, BND
}, 0 }
6915 { "{l|}jmp{T|}", { Ap
}, 0 },
6918 /* X86_64_0F01_REG_0 */
6920 { "sgdt{Q|Q}", { M
}, 0 },
6921 { "sgdt", { M
}, 0 },
6924 /* X86_64_0F01_REG_1 */
6926 { "sidt{Q|Q}", { M
}, 0 },
6927 { "sidt", { M
}, 0 },
6930 /* X86_64_0F01_REG_2 */
6932 { "lgdt{Q|Q}", { M
}, 0 },
6933 { "lgdt", { M
}, 0 },
6936 /* X86_64_0F01_REG_3 */
6938 { "lidt{Q|Q}", { M
}, 0 },
6939 { "lidt", { M
}, 0 },
6943 static const struct dis386 three_byte_table
[][256] = {
6945 /* THREE_BYTE_0F38 */
6948 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6949 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6950 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6951 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6952 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6953 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6954 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6955 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6957 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6958 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6959 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6960 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6966 { PREFIX_TABLE (PREFIX_0F3810
) },
6970 { PREFIX_TABLE (PREFIX_0F3814
) },
6971 { PREFIX_TABLE (PREFIX_0F3815
) },
6973 { PREFIX_TABLE (PREFIX_0F3817
) },
6979 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6980 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6981 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6984 { PREFIX_TABLE (PREFIX_0F3820
) },
6985 { PREFIX_TABLE (PREFIX_0F3821
) },
6986 { PREFIX_TABLE (PREFIX_0F3822
) },
6987 { PREFIX_TABLE (PREFIX_0F3823
) },
6988 { PREFIX_TABLE (PREFIX_0F3824
) },
6989 { PREFIX_TABLE (PREFIX_0F3825
) },
6993 { PREFIX_TABLE (PREFIX_0F3828
) },
6994 { PREFIX_TABLE (PREFIX_0F3829
) },
6995 { PREFIX_TABLE (PREFIX_0F382A
) },
6996 { PREFIX_TABLE (PREFIX_0F382B
) },
7002 { PREFIX_TABLE (PREFIX_0F3830
) },
7003 { PREFIX_TABLE (PREFIX_0F3831
) },
7004 { PREFIX_TABLE (PREFIX_0F3832
) },
7005 { PREFIX_TABLE (PREFIX_0F3833
) },
7006 { PREFIX_TABLE (PREFIX_0F3834
) },
7007 { PREFIX_TABLE (PREFIX_0F3835
) },
7009 { PREFIX_TABLE (PREFIX_0F3837
) },
7011 { PREFIX_TABLE (PREFIX_0F3838
) },
7012 { PREFIX_TABLE (PREFIX_0F3839
) },
7013 { PREFIX_TABLE (PREFIX_0F383A
) },
7014 { PREFIX_TABLE (PREFIX_0F383B
) },
7015 { PREFIX_TABLE (PREFIX_0F383C
) },
7016 { PREFIX_TABLE (PREFIX_0F383D
) },
7017 { PREFIX_TABLE (PREFIX_0F383E
) },
7018 { PREFIX_TABLE (PREFIX_0F383F
) },
7020 { PREFIX_TABLE (PREFIX_0F3840
) },
7021 { PREFIX_TABLE (PREFIX_0F3841
) },
7092 { PREFIX_TABLE (PREFIX_0F3880
) },
7093 { PREFIX_TABLE (PREFIX_0F3881
) },
7094 { PREFIX_TABLE (PREFIX_0F3882
) },
7173 { PREFIX_TABLE (PREFIX_0F38C8
) },
7174 { PREFIX_TABLE (PREFIX_0F38C9
) },
7175 { PREFIX_TABLE (PREFIX_0F38CA
) },
7176 { PREFIX_TABLE (PREFIX_0F38CB
) },
7177 { PREFIX_TABLE (PREFIX_0F38CC
) },
7178 { PREFIX_TABLE (PREFIX_0F38CD
) },
7180 { PREFIX_TABLE (PREFIX_0F38CF
) },
7194 { PREFIX_TABLE (PREFIX_0F38DB
) },
7195 { PREFIX_TABLE (PREFIX_0F38DC
) },
7196 { PREFIX_TABLE (PREFIX_0F38DD
) },
7197 { PREFIX_TABLE (PREFIX_0F38DE
) },
7198 { PREFIX_TABLE (PREFIX_0F38DF
) },
7218 { PREFIX_TABLE (PREFIX_0F38F0
) },
7219 { PREFIX_TABLE (PREFIX_0F38F1
) },
7223 { PREFIX_TABLE (PREFIX_0F38F5
) },
7224 { PREFIX_TABLE (PREFIX_0F38F6
) },
7227 { PREFIX_TABLE (PREFIX_0F38F8
) },
7228 { PREFIX_TABLE (PREFIX_0F38F9
) },
7236 /* THREE_BYTE_0F3A */
7248 { PREFIX_TABLE (PREFIX_0F3A08
) },
7249 { PREFIX_TABLE (PREFIX_0F3A09
) },
7250 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7251 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7252 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7253 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7254 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7255 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7261 { PREFIX_TABLE (PREFIX_0F3A14
) },
7262 { PREFIX_TABLE (PREFIX_0F3A15
) },
7263 { PREFIX_TABLE (PREFIX_0F3A16
) },
7264 { PREFIX_TABLE (PREFIX_0F3A17
) },
7275 { PREFIX_TABLE (PREFIX_0F3A20
) },
7276 { PREFIX_TABLE (PREFIX_0F3A21
) },
7277 { PREFIX_TABLE (PREFIX_0F3A22
) },
7311 { PREFIX_TABLE (PREFIX_0F3A40
) },
7312 { PREFIX_TABLE (PREFIX_0F3A41
) },
7313 { PREFIX_TABLE (PREFIX_0F3A42
) },
7315 { PREFIX_TABLE (PREFIX_0F3A44
) },
7347 { PREFIX_TABLE (PREFIX_0F3A60
) },
7348 { PREFIX_TABLE (PREFIX_0F3A61
) },
7349 { PREFIX_TABLE (PREFIX_0F3A62
) },
7350 { PREFIX_TABLE (PREFIX_0F3A63
) },
7468 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7470 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7471 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7489 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7529 static const struct dis386 xop_table
[][256] = {
7682 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7683 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7684 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7692 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7693 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7700 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7701 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7702 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7710 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7711 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7715 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7716 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7719 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7737 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7749 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7750 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7751 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7752 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7762 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7763 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7764 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7765 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7798 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7799 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7800 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7801 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7825 { REG_TABLE (REG_XOP_TBM_01
) },
7826 { REG_TABLE (REG_XOP_TBM_02
) },
7844 { REG_TABLE (REG_XOP_LWPCB
) },
7968 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7969 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7970 { "vfrczss", { XM
, EXd
}, 0 },
7971 { "vfrczsd", { XM
, EXq
}, 0 },
7986 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7987 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7988 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7989 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7990 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7991 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7992 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7993 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7995 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7996 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7997 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7998 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8041 { "vphaddbw", { XM
, EXxmm
}, 0 },
8042 { "vphaddbd", { XM
, EXxmm
}, 0 },
8043 { "vphaddbq", { XM
, EXxmm
}, 0 },
8046 { "vphaddwd", { XM
, EXxmm
}, 0 },
8047 { "vphaddwq", { XM
, EXxmm
}, 0 },
8052 { "vphadddq", { XM
, EXxmm
}, 0 },
8059 { "vphaddubw", { XM
, EXxmm
}, 0 },
8060 { "vphaddubd", { XM
, EXxmm
}, 0 },
8061 { "vphaddubq", { XM
, EXxmm
}, 0 },
8064 { "vphadduwd", { XM
, EXxmm
}, 0 },
8065 { "vphadduwq", { XM
, EXxmm
}, 0 },
8070 { "vphaddudq", { XM
, EXxmm
}, 0 },
8077 { "vphsubbw", { XM
, EXxmm
}, 0 },
8078 { "vphsubwd", { XM
, EXxmm
}, 0 },
8079 { "vphsubdq", { XM
, EXxmm
}, 0 },
8133 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8135 { REG_TABLE (REG_XOP_LWP
) },
8405 static const struct dis386 vex_table
[][256] = {
8427 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8428 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8429 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8430 { MOD_TABLE (MOD_VEX_0F13
) },
8431 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8432 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8433 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8434 { MOD_TABLE (MOD_VEX_0F17
) },
8454 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
8455 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
8456 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8457 { MOD_TABLE (MOD_VEX_0F2B
) },
8458 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8459 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8460 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8461 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8482 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8483 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8485 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8486 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8487 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8488 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8492 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8493 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8499 { MOD_TABLE (MOD_VEX_0F50
) },
8500 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8501 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8502 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8503 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8504 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8505 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8506 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8508 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8509 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8510 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8511 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8512 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8514 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8515 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8517 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8518 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8519 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8520 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8521 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8522 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8524 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8526 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8527 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8528 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8529 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8530 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8531 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8532 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8533 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8536 { REG_TABLE (REG_VEX_0F71
) },
8537 { REG_TABLE (REG_VEX_0F72
) },
8538 { REG_TABLE (REG_VEX_0F73
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8541 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8542 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8550 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8551 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8573 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8580 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8581 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8604 { REG_TABLE (REG_VEX_0FAE
) },
8627 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8629 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8630 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8631 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
8643 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8644 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8645 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8646 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8647 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8648 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8649 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8650 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8652 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8654 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8657 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8662 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8663 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8835 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8836 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8863 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8865 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8872 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8873 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8874 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8875 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8876 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8877 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8878 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8973 { REG_TABLE (REG_VEX_0F38F3
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9222 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9223 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9241 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9261 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9281 #include "i386-dis-evex.h"
9283 static const struct dis386 vex_len_table
[][2] = {
9284 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9286 { "vmovlpX", { XM
, Vex128
, EXq
}, 0 },
9289 /* VEX_LEN_0F12_P_0_M_1 */
9291 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9294 /* VEX_LEN_0F13_M_0 */
9296 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
9299 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9301 { "vmovhpX", { XM
, Vex128
, EXq
}, 0 },
9304 /* VEX_LEN_0F16_P_0_M_1 */
9306 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9309 /* VEX_LEN_0F17_M_0 */
9311 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
9314 /* VEX_LEN_0F41_P_0 */
9317 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9319 /* VEX_LEN_0F41_P_2 */
9322 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9324 /* VEX_LEN_0F42_P_0 */
9327 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9329 /* VEX_LEN_0F42_P_2 */
9332 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9334 /* VEX_LEN_0F44_P_0 */
9336 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9338 /* VEX_LEN_0F44_P_2 */
9340 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9342 /* VEX_LEN_0F45_P_0 */
9345 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9347 /* VEX_LEN_0F45_P_2 */
9350 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9352 /* VEX_LEN_0F46_P_0 */
9355 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9357 /* VEX_LEN_0F46_P_2 */
9360 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9362 /* VEX_LEN_0F47_P_0 */
9365 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9367 /* VEX_LEN_0F47_P_2 */
9370 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9372 /* VEX_LEN_0F4A_P_0 */
9375 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9377 /* VEX_LEN_0F4A_P_2 */
9380 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9382 /* VEX_LEN_0F4B_P_0 */
9385 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9387 /* VEX_LEN_0F4B_P_2 */
9390 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9393 /* VEX_LEN_0F6E_P_2 */
9395 { "vmovK", { XMScalar
, Edq
}, 0 },
9398 /* VEX_LEN_0F77_P_1 */
9400 { "vzeroupper", { XX
}, 0 },
9401 { "vzeroall", { XX
}, 0 },
9404 /* VEX_LEN_0F7E_P_1 */
9406 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9409 /* VEX_LEN_0F7E_P_2 */
9411 { "vmovK", { Edq
, XMScalar
}, 0 },
9414 /* VEX_LEN_0F90_P_0 */
9416 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9419 /* VEX_LEN_0F90_P_2 */
9421 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9424 /* VEX_LEN_0F91_P_0 */
9426 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9429 /* VEX_LEN_0F91_P_2 */
9431 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9434 /* VEX_LEN_0F92_P_0 */
9436 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9439 /* VEX_LEN_0F92_P_2 */
9441 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9444 /* VEX_LEN_0F92_P_3 */
9446 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9449 /* VEX_LEN_0F93_P_0 */
9451 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9454 /* VEX_LEN_0F93_P_2 */
9456 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9459 /* VEX_LEN_0F93_P_3 */
9461 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9464 /* VEX_LEN_0F98_P_0 */
9466 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9469 /* VEX_LEN_0F98_P_2 */
9471 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9474 /* VEX_LEN_0F99_P_0 */
9476 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9479 /* VEX_LEN_0F99_P_2 */
9481 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9484 /* VEX_LEN_0FAE_R_2_M_0 */
9486 { "vldmxcsr", { Md
}, 0 },
9489 /* VEX_LEN_0FAE_R_3_M_0 */
9491 { "vstmxcsr", { Md
}, 0 },
9494 /* VEX_LEN_0FC4_P_2 */
9496 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9499 /* VEX_LEN_0FC5_P_2 */
9501 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9504 /* VEX_LEN_0FD6_P_2 */
9506 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9509 /* VEX_LEN_0FF7_P_2 */
9511 { "vmaskmovdqu", { XM
, XS
}, 0 },
9514 /* VEX_LEN_0F3816_P_2 */
9517 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9520 /* VEX_LEN_0F3819_P_2 */
9523 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9526 /* VEX_LEN_0F381A_P_2_M_0 */
9529 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9532 /* VEX_LEN_0F3836_P_2 */
9535 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9538 /* VEX_LEN_0F3841_P_2 */
9540 { "vphminposuw", { XM
, EXx
}, 0 },
9543 /* VEX_LEN_0F385A_P_2_M_0 */
9546 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9549 /* VEX_LEN_0F38DB_P_2 */
9551 { "vaesimc", { XM
, EXx
}, 0 },
9554 /* VEX_LEN_0F38F2_P_0 */
9556 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9559 /* VEX_LEN_0F38F3_R_1_P_0 */
9561 { "blsrS", { VexGdq
, Edq
}, 0 },
9564 /* VEX_LEN_0F38F3_R_2_P_0 */
9566 { "blsmskS", { VexGdq
, Edq
}, 0 },
9569 /* VEX_LEN_0F38F3_R_3_P_0 */
9571 { "blsiS", { VexGdq
, Edq
}, 0 },
9574 /* VEX_LEN_0F38F5_P_0 */
9576 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9579 /* VEX_LEN_0F38F5_P_1 */
9581 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9584 /* VEX_LEN_0F38F5_P_3 */
9586 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9589 /* VEX_LEN_0F38F6_P_3 */
9591 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9594 /* VEX_LEN_0F38F7_P_0 */
9596 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9599 /* VEX_LEN_0F38F7_P_1 */
9601 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9604 /* VEX_LEN_0F38F7_P_2 */
9606 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9609 /* VEX_LEN_0F38F7_P_3 */
9611 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9614 /* VEX_LEN_0F3A00_P_2 */
9617 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9620 /* VEX_LEN_0F3A01_P_2 */
9623 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9626 /* VEX_LEN_0F3A06_P_2 */
9629 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9632 /* VEX_LEN_0F3A14_P_2 */
9634 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9637 /* VEX_LEN_0F3A15_P_2 */
9639 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9642 /* VEX_LEN_0F3A16_P_2 */
9644 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9647 /* VEX_LEN_0F3A17_P_2 */
9649 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9652 /* VEX_LEN_0F3A18_P_2 */
9655 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9658 /* VEX_LEN_0F3A19_P_2 */
9661 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9664 /* VEX_LEN_0F3A20_P_2 */
9666 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9669 /* VEX_LEN_0F3A21_P_2 */
9671 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9674 /* VEX_LEN_0F3A22_P_2 */
9676 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9679 /* VEX_LEN_0F3A30_P_2 */
9681 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9684 /* VEX_LEN_0F3A31_P_2 */
9686 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9689 /* VEX_LEN_0F3A32_P_2 */
9691 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9694 /* VEX_LEN_0F3A33_P_2 */
9696 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9699 /* VEX_LEN_0F3A38_P_2 */
9702 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9705 /* VEX_LEN_0F3A39_P_2 */
9708 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9711 /* VEX_LEN_0F3A41_P_2 */
9713 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9716 /* VEX_LEN_0F3A46_P_2 */
9719 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9722 /* VEX_LEN_0F3A60_P_2 */
9724 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9727 /* VEX_LEN_0F3A61_P_2 */
9729 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9732 /* VEX_LEN_0F3A62_P_2 */
9734 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9737 /* VEX_LEN_0F3A63_P_2 */
9739 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9742 /* VEX_LEN_0F3A6A_P_2 */
9744 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9747 /* VEX_LEN_0F3A6B_P_2 */
9749 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9752 /* VEX_LEN_0F3A6E_P_2 */
9754 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9757 /* VEX_LEN_0F3A6F_P_2 */
9759 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9762 /* VEX_LEN_0F3A7A_P_2 */
9764 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9767 /* VEX_LEN_0F3A7B_P_2 */
9769 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9772 /* VEX_LEN_0F3A7E_P_2 */
9774 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9777 /* VEX_LEN_0F3A7F_P_2 */
9779 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9782 /* VEX_LEN_0F3ADF_P_2 */
9784 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9787 /* VEX_LEN_0F3AF0_P_3 */
9789 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9792 /* VEX_LEN_0FXOP_08_CC */
9794 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9797 /* VEX_LEN_0FXOP_08_CD */
9799 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9802 /* VEX_LEN_0FXOP_08_CE */
9804 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9807 /* VEX_LEN_0FXOP_08_CF */
9809 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9812 /* VEX_LEN_0FXOP_08_EC */
9814 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9817 /* VEX_LEN_0FXOP_08_ED */
9819 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9822 /* VEX_LEN_0FXOP_08_EE */
9824 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9827 /* VEX_LEN_0FXOP_08_EF */
9829 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9832 /* VEX_LEN_0FXOP_09_80 */
9834 { "vfrczps", { XM
, EXxmm
}, 0 },
9835 { "vfrczps", { XM
, EXymmq
}, 0 },
9838 /* VEX_LEN_0FXOP_09_81 */
9840 { "vfrczpd", { XM
, EXxmm
}, 0 },
9841 { "vfrczpd", { XM
, EXymmq
}, 0 },
9845 #include "i386-dis-evex-len.h"
9847 static const struct dis386 vex_w_table
[][2] = {
9849 /* VEX_W_0F41_P_0_LEN_1 */
9850 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9851 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9854 /* VEX_W_0F41_P_2_LEN_1 */
9855 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9856 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9859 /* VEX_W_0F42_P_0_LEN_1 */
9860 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9861 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9864 /* VEX_W_0F42_P_2_LEN_1 */
9865 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9866 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9869 /* VEX_W_0F44_P_0_LEN_0 */
9870 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9871 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9874 /* VEX_W_0F44_P_2_LEN_0 */
9875 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9876 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9879 /* VEX_W_0F45_P_0_LEN_1 */
9880 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9881 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9884 /* VEX_W_0F45_P_2_LEN_1 */
9885 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9886 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9889 /* VEX_W_0F46_P_0_LEN_1 */
9890 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9891 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9894 /* VEX_W_0F46_P_2_LEN_1 */
9895 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9896 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9899 /* VEX_W_0F47_P_0_LEN_1 */
9900 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9901 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9904 /* VEX_W_0F47_P_2_LEN_1 */
9905 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9906 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9909 /* VEX_W_0F4A_P_0_LEN_1 */
9910 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9911 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9914 /* VEX_W_0F4A_P_2_LEN_1 */
9915 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9916 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9919 /* VEX_W_0F4B_P_0_LEN_1 */
9920 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9921 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9924 /* VEX_W_0F4B_P_2_LEN_1 */
9925 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9928 /* VEX_W_0F90_P_0_LEN_0 */
9929 { "kmovw", { MaskG
, MaskE
}, 0 },
9930 { "kmovq", { MaskG
, MaskE
}, 0 },
9933 /* VEX_W_0F90_P_2_LEN_0 */
9934 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9935 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9938 /* VEX_W_0F91_P_0_LEN_0 */
9939 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9940 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9943 /* VEX_W_0F91_P_2_LEN_0 */
9944 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9945 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9948 /* VEX_W_0F92_P_0_LEN_0 */
9949 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9952 /* VEX_W_0F92_P_2_LEN_0 */
9953 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
9956 /* VEX_W_0F93_P_0_LEN_0 */
9957 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
9960 /* VEX_W_0F93_P_2_LEN_0 */
9961 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
9964 /* VEX_W_0F98_P_0_LEN_0 */
9965 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
9966 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
9969 /* VEX_W_0F98_P_2_LEN_0 */
9970 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
9971 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
9974 /* VEX_W_0F99_P_0_LEN_0 */
9975 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
9976 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
9979 /* VEX_W_0F99_P_2_LEN_0 */
9980 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
9981 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
9984 /* VEX_W_0F380C_P_2 */
9985 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
9988 /* VEX_W_0F380D_P_2 */
9989 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
9992 /* VEX_W_0F380E_P_2 */
9993 { "vtestps", { XM
, EXx
}, 0 },
9996 /* VEX_W_0F380F_P_2 */
9997 { "vtestpd", { XM
, EXx
}, 0 },
10000 /* VEX_W_0F3816_P_2 */
10001 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10004 /* VEX_W_0F3818_P_2 */
10005 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10008 /* VEX_W_0F3819_P_2 */
10009 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10012 /* VEX_W_0F381A_P_2_M_0 */
10013 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10016 /* VEX_W_0F382C_P_2_M_0 */
10017 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10020 /* VEX_W_0F382D_P_2_M_0 */
10021 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10024 /* VEX_W_0F382E_P_2_M_0 */
10025 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10028 /* VEX_W_0F382F_P_2_M_0 */
10029 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10032 /* VEX_W_0F3836_P_2 */
10033 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10036 /* VEX_W_0F3846_P_2 */
10037 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10040 /* VEX_W_0F3858_P_2 */
10041 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10044 /* VEX_W_0F3859_P_2 */
10045 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10048 /* VEX_W_0F385A_P_2_M_0 */
10049 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10052 /* VEX_W_0F3878_P_2 */
10053 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10056 /* VEX_W_0F3879_P_2 */
10057 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10060 /* VEX_W_0F38CF_P_2 */
10061 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10064 /* VEX_W_0F3A00_P_2 */
10066 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10069 /* VEX_W_0F3A01_P_2 */
10071 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10074 /* VEX_W_0F3A02_P_2 */
10075 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10078 /* VEX_W_0F3A04_P_2 */
10079 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10082 /* VEX_W_0F3A05_P_2 */
10083 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10086 /* VEX_W_0F3A06_P_2 */
10087 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10090 /* VEX_W_0F3A18_P_2 */
10091 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10094 /* VEX_W_0F3A19_P_2 */
10095 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10098 /* VEX_W_0F3A30_P_2_LEN_0 */
10099 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10100 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10103 /* VEX_W_0F3A31_P_2_LEN_0 */
10104 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10105 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10108 /* VEX_W_0F3A32_P_2_LEN_0 */
10109 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10110 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10113 /* VEX_W_0F3A33_P_2_LEN_0 */
10114 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10115 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10118 /* VEX_W_0F3A38_P_2 */
10119 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10122 /* VEX_W_0F3A39_P_2 */
10123 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10126 /* VEX_W_0F3A46_P_2 */
10127 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10130 /* VEX_W_0F3A48_P_2 */
10131 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10132 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10135 /* VEX_W_0F3A49_P_2 */
10136 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10137 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10140 /* VEX_W_0F3A4A_P_2 */
10141 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10144 /* VEX_W_0F3A4B_P_2 */
10145 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10148 /* VEX_W_0F3A4C_P_2 */
10149 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10152 /* VEX_W_0F3ACE_P_2 */
10154 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10157 /* VEX_W_0F3ACF_P_2 */
10159 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10162 #include "i386-dis-evex-w.h"
10165 static const struct dis386 mod_table
[][2] = {
10168 { "leaS", { Gv
, M
}, 0 },
10173 { RM_TABLE (RM_C6_REG_7
) },
10178 { RM_TABLE (RM_C7_REG_7
) },
10182 { "{l|}call^", { indirEp
}, 0 },
10186 { "{l|}jmp^", { indirEp
}, 0 },
10189 /* MOD_0F01_REG_0 */
10190 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10191 { RM_TABLE (RM_0F01_REG_0
) },
10194 /* MOD_0F01_REG_1 */
10195 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10196 { RM_TABLE (RM_0F01_REG_1
) },
10199 /* MOD_0F01_REG_2 */
10200 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10201 { RM_TABLE (RM_0F01_REG_2
) },
10204 /* MOD_0F01_REG_3 */
10205 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10206 { RM_TABLE (RM_0F01_REG_3
) },
10209 /* MOD_0F01_REG_5 */
10210 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10211 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10214 /* MOD_0F01_REG_7 */
10215 { "invlpg", { Mb
}, 0 },
10216 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10219 /* MOD_0F12_PREFIX_0 */
10220 { "movlpX", { XM
, EXq
}, 0 },
10221 { "movhlps", { XM
, EXq
}, 0 },
10224 /* MOD_0F12_PREFIX_2 */
10225 { "movlpX", { XM
, EXq
}, 0 },
10229 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10232 /* MOD_0F16_PREFIX_0 */
10233 { "movhpX", { XM
, EXq
}, 0 },
10234 { "movlhps", { XM
, EXq
}, 0 },
10237 /* MOD_0F16_PREFIX_2 */
10238 { "movhpX", { XM
, EXq
}, 0 },
10242 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10245 /* MOD_0F18_REG_0 */
10246 { "prefetchnta", { Mb
}, 0 },
10249 /* MOD_0F18_REG_1 */
10250 { "prefetcht0", { Mb
}, 0 },
10253 /* MOD_0F18_REG_2 */
10254 { "prefetcht1", { Mb
}, 0 },
10257 /* MOD_0F18_REG_3 */
10258 { "prefetcht2", { Mb
}, 0 },
10261 /* MOD_0F18_REG_4 */
10262 { "nop/reserved", { Mb
}, 0 },
10265 /* MOD_0F18_REG_5 */
10266 { "nop/reserved", { Mb
}, 0 },
10269 /* MOD_0F18_REG_6 */
10270 { "nop/reserved", { Mb
}, 0 },
10273 /* MOD_0F18_REG_7 */
10274 { "nop/reserved", { Mb
}, 0 },
10277 /* MOD_0F1A_PREFIX_0 */
10278 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10279 { "nopQ", { Ev
}, 0 },
10282 /* MOD_0F1B_PREFIX_0 */
10283 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10284 { "nopQ", { Ev
}, 0 },
10287 /* MOD_0F1B_PREFIX_1 */
10288 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10289 { "nopQ", { Ev
}, 0 },
10292 /* MOD_0F1C_PREFIX_0 */
10293 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10294 { "nopQ", { Ev
}, 0 },
10297 /* MOD_0F1E_PREFIX_1 */
10298 { "nopQ", { Ev
}, 0 },
10299 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10304 { "movL", { Rd
, Td
}, 0 },
10309 { "movL", { Td
, Rd
}, 0 },
10312 /* MOD_0F2B_PREFIX_0 */
10313 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10316 /* MOD_0F2B_PREFIX_1 */
10317 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10320 /* MOD_0F2B_PREFIX_2 */
10321 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10324 /* MOD_0F2B_PREFIX_3 */
10325 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10330 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10333 /* MOD_0F71_REG_2 */
10335 { "psrlw", { MS
, Ib
}, 0 },
10338 /* MOD_0F71_REG_4 */
10340 { "psraw", { MS
, Ib
}, 0 },
10343 /* MOD_0F71_REG_6 */
10345 { "psllw", { MS
, Ib
}, 0 },
10348 /* MOD_0F72_REG_2 */
10350 { "psrld", { MS
, Ib
}, 0 },
10353 /* MOD_0F72_REG_4 */
10355 { "psrad", { MS
, Ib
}, 0 },
10358 /* MOD_0F72_REG_6 */
10360 { "pslld", { MS
, Ib
}, 0 },
10363 /* MOD_0F73_REG_2 */
10365 { "psrlq", { MS
, Ib
}, 0 },
10368 /* MOD_0F73_REG_3 */
10370 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10373 /* MOD_0F73_REG_6 */
10375 { "psllq", { MS
, Ib
}, 0 },
10378 /* MOD_0F73_REG_7 */
10380 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10383 /* MOD_0FAE_REG_0 */
10384 { "fxsave", { FXSAVE
}, 0 },
10385 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10388 /* MOD_0FAE_REG_1 */
10389 { "fxrstor", { FXSAVE
}, 0 },
10390 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10393 /* MOD_0FAE_REG_2 */
10394 { "ldmxcsr", { Md
}, 0 },
10395 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10398 /* MOD_0FAE_REG_3 */
10399 { "stmxcsr", { Md
}, 0 },
10400 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10403 /* MOD_0FAE_REG_4 */
10404 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10405 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10408 /* MOD_0FAE_REG_5 */
10409 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10410 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10413 /* MOD_0FAE_REG_6 */
10414 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10415 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10418 /* MOD_0FAE_REG_7 */
10419 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10420 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10424 { "lssS", { Gv
, Mp
}, 0 },
10428 { "lfsS", { Gv
, Mp
}, 0 },
10432 { "lgsS", { Gv
, Mp
}, 0 },
10436 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10439 /* MOD_0FC7_REG_3 */
10440 { "xrstors", { FXSAVE
}, 0 },
10443 /* MOD_0FC7_REG_4 */
10444 { "xsavec", { FXSAVE
}, 0 },
10447 /* MOD_0FC7_REG_5 */
10448 { "xsaves", { FXSAVE
}, 0 },
10451 /* MOD_0FC7_REG_6 */
10452 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10453 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10456 /* MOD_0FC7_REG_7 */
10457 { "vmptrst", { Mq
}, 0 },
10458 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10463 { "pmovmskb", { Gdq
, MS
}, 0 },
10466 /* MOD_0FE7_PREFIX_2 */
10467 { "movntdq", { Mx
, XM
}, 0 },
10470 /* MOD_0FF0_PREFIX_3 */
10471 { "lddqu", { XM
, M
}, 0 },
10474 /* MOD_0F382A_PREFIX_2 */
10475 { "movntdqa", { XM
, Mx
}, 0 },
10478 /* MOD_0F38F5_PREFIX_2 */
10479 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10482 /* MOD_0F38F6_PREFIX_0 */
10483 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10486 /* MOD_0F38F8_PREFIX_1 */
10487 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10490 /* MOD_0F38F8_PREFIX_2 */
10491 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10494 /* MOD_0F38F8_PREFIX_3 */
10495 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10498 /* MOD_0F38F9_PREFIX_0 */
10499 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
10503 { "bound{S|}", { Gv
, Ma
}, 0 },
10504 { EVEX_TABLE (EVEX_0F
) },
10508 { "lesS", { Gv
, Mp
}, 0 },
10509 { VEX_C4_TABLE (VEX_0F
) },
10513 { "ldsS", { Gv
, Mp
}, 0 },
10514 { VEX_C5_TABLE (VEX_0F
) },
10517 /* MOD_VEX_0F12_PREFIX_0 */
10518 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10519 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10522 /* MOD_VEX_0F12_PREFIX_2 */
10523 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
10527 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10530 /* MOD_VEX_0F16_PREFIX_0 */
10531 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10532 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10535 /* MOD_VEX_0F16_PREFIX_2 */
10536 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
10540 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10544 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
10547 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10549 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10552 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10554 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10557 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10559 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10562 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10564 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10567 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10569 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10572 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10574 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10577 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10579 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10582 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10584 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10587 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10589 { "knotw", { MaskG
, MaskR
}, 0 },
10592 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10594 { "knotq", { MaskG
, MaskR
}, 0 },
10597 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10599 { "knotb", { MaskG
, MaskR
}, 0 },
10602 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10604 { "knotd", { MaskG
, MaskR
}, 0 },
10607 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10609 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10612 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10614 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10617 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10619 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10622 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10624 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10627 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10629 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10632 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10634 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10637 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10639 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10642 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10644 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10647 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10649 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10652 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10654 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10657 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10659 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10662 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10664 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10667 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10669 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10672 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10674 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10677 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10679 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10682 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10684 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10687 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10689 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10692 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10694 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10697 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10699 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10704 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10707 /* MOD_VEX_0F71_REG_2 */
10709 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10712 /* MOD_VEX_0F71_REG_4 */
10714 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10717 /* MOD_VEX_0F71_REG_6 */
10719 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10722 /* MOD_VEX_0F72_REG_2 */
10724 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10727 /* MOD_VEX_0F72_REG_4 */
10729 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10732 /* MOD_VEX_0F72_REG_6 */
10734 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10737 /* MOD_VEX_0F73_REG_2 */
10739 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10742 /* MOD_VEX_0F73_REG_3 */
10744 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10747 /* MOD_VEX_0F73_REG_6 */
10749 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10752 /* MOD_VEX_0F73_REG_7 */
10754 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10757 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10758 { "kmovw", { Ew
, MaskG
}, 0 },
10762 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10763 { "kmovq", { Eq
, MaskG
}, 0 },
10767 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10768 { "kmovb", { Eb
, MaskG
}, 0 },
10772 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10773 { "kmovd", { Ed
, MaskG
}, 0 },
10777 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10779 { "kmovw", { MaskG
, Rdq
}, 0 },
10782 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10784 { "kmovb", { MaskG
, Rdq
}, 0 },
10787 /* MOD_VEX_0F92_P_3_LEN_0 */
10789 { "kmovK", { MaskG
, Rdq
}, 0 },
10792 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10794 { "kmovw", { Gdq
, MaskR
}, 0 },
10797 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10799 { "kmovb", { Gdq
, MaskR
}, 0 },
10802 /* MOD_VEX_0F93_P_3_LEN_0 */
10804 { "kmovK", { Gdq
, MaskR
}, 0 },
10807 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10809 { "kortestw", { MaskG
, MaskR
}, 0 },
10812 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10814 { "kortestq", { MaskG
, MaskR
}, 0 },
10817 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10819 { "kortestb", { MaskG
, MaskR
}, 0 },
10822 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10824 { "kortestd", { MaskG
, MaskR
}, 0 },
10827 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10829 { "ktestw", { MaskG
, MaskR
}, 0 },
10832 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10834 { "ktestq", { MaskG
, MaskR
}, 0 },
10837 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10839 { "ktestb", { MaskG
, MaskR
}, 0 },
10842 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10844 { "ktestd", { MaskG
, MaskR
}, 0 },
10847 /* MOD_VEX_0FAE_REG_2 */
10848 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10851 /* MOD_VEX_0FAE_REG_3 */
10852 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10855 /* MOD_VEX_0FD7_PREFIX_2 */
10857 { "vpmovmskb", { Gdq
, XS
}, 0 },
10860 /* MOD_VEX_0FE7_PREFIX_2 */
10861 { "vmovntdq", { Mx
, XM
}, 0 },
10864 /* MOD_VEX_0FF0_PREFIX_3 */
10865 { "vlddqu", { XM
, M
}, 0 },
10868 /* MOD_VEX_0F381A_PREFIX_2 */
10869 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10872 /* MOD_VEX_0F382A_PREFIX_2 */
10873 { "vmovntdqa", { XM
, Mx
}, 0 },
10876 /* MOD_VEX_0F382C_PREFIX_2 */
10877 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10880 /* MOD_VEX_0F382D_PREFIX_2 */
10881 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10884 /* MOD_VEX_0F382E_PREFIX_2 */
10885 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10888 /* MOD_VEX_0F382F_PREFIX_2 */
10889 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10892 /* MOD_VEX_0F385A_PREFIX_2 */
10893 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10896 /* MOD_VEX_0F388C_PREFIX_2 */
10897 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10900 /* MOD_VEX_0F388E_PREFIX_2 */
10901 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10904 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10906 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10909 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10911 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10914 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10916 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10919 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10921 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10924 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10926 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10929 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10931 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10934 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10936 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10939 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10941 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10944 #include "i386-dis-evex-mod.h"
10947 static const struct dis386 rm_table
[][8] = {
10950 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10954 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
10957 /* RM_0F01_REG_0 */
10958 { "enclv", { Skip_MODRM
}, 0 },
10959 { "vmcall", { Skip_MODRM
}, 0 },
10960 { "vmlaunch", { Skip_MODRM
}, 0 },
10961 { "vmresume", { Skip_MODRM
}, 0 },
10962 { "vmxoff", { Skip_MODRM
}, 0 },
10963 { "pconfig", { Skip_MODRM
}, 0 },
10966 /* RM_0F01_REG_1 */
10967 { "monitor", { { OP_Monitor
, 0 } }, 0 },
10968 { "mwait", { { OP_Mwait
, 0 } }, 0 },
10969 { "clac", { Skip_MODRM
}, 0 },
10970 { "stac", { Skip_MODRM
}, 0 },
10974 { "encls", { Skip_MODRM
}, 0 },
10977 /* RM_0F01_REG_2 */
10978 { "xgetbv", { Skip_MODRM
}, 0 },
10979 { "xsetbv", { Skip_MODRM
}, 0 },
10982 { "vmfunc", { Skip_MODRM
}, 0 },
10983 { "xend", { Skip_MODRM
}, 0 },
10984 { "xtest", { Skip_MODRM
}, 0 },
10985 { "enclu", { Skip_MODRM
}, 0 },
10988 /* RM_0F01_REG_3 */
10989 { "vmrun", { Skip_MODRM
}, 0 },
10990 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
10991 { "vmload", { Skip_MODRM
}, 0 },
10992 { "vmsave", { Skip_MODRM
}, 0 },
10993 { "stgi", { Skip_MODRM
}, 0 },
10994 { "clgi", { Skip_MODRM
}, 0 },
10995 { "skinit", { Skip_MODRM
}, 0 },
10996 { "invlpga", { Skip_MODRM
}, 0 },
10999 /* RM_0F01_REG_5_MOD_3 */
11000 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
11001 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
11002 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
11006 { "rdpkru", { Skip_MODRM
}, 0 },
11007 { "wrpkru", { Skip_MODRM
}, 0 },
11010 /* RM_0F01_REG_7_MOD_3 */
11011 { "swapgs", { Skip_MODRM
}, 0 },
11012 { "rdtscp", { Skip_MODRM
}, 0 },
11013 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
11014 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
11015 { "clzero", { Skip_MODRM
}, 0 },
11016 { "rdpru", { Skip_MODRM
}, 0 },
11019 /* RM_0F1E_P_1_MOD_3_REG_7 */
11020 { "nopQ", { Ev
}, 0 },
11021 { "nopQ", { Ev
}, 0 },
11022 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11023 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11024 { "nopQ", { Ev
}, 0 },
11025 { "nopQ", { Ev
}, 0 },
11026 { "nopQ", { Ev
}, 0 },
11027 { "nopQ", { Ev
}, 0 },
11030 /* RM_0FAE_REG_6_MOD_3 */
11031 { "mfence", { Skip_MODRM
}, 0 },
11034 /* RM_0FAE_REG_7_MOD_3 */
11035 { "sfence", { Skip_MODRM
}, 0 },
11040 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11042 /* We use the high bit to indicate different name for the same
11044 #define REP_PREFIX (0xf3 | 0x100)
11045 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11046 #define XRELEASE_PREFIX (0xf3 | 0x400)
11047 #define BND_PREFIX (0xf2 | 0x400)
11048 #define NOTRACK_PREFIX (0x3e | 0x100)
11050 /* Remember if the current op is a jump instruction. */
11051 static bfd_boolean op_is_jump
= FALSE
;
11056 int newrex
, i
, length
;
11061 last_lock_prefix
= -1;
11062 last_repz_prefix
= -1;
11063 last_repnz_prefix
= -1;
11064 last_data_prefix
= -1;
11065 last_addr_prefix
= -1;
11066 last_rex_prefix
= -1;
11067 last_seg_prefix
= -1;
11069 active_seg_prefix
= 0;
11070 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11071 all_prefixes
[i
] = 0;
11074 /* The maximum instruction length is 15bytes. */
11075 while (length
< MAX_CODE_LENGTH
- 1)
11077 FETCH_DATA (the_info
, codep
+ 1);
11081 /* REX prefixes family. */
11098 if (address_mode
== mode_64bit
)
11102 last_rex_prefix
= i
;
11105 prefixes
|= PREFIX_REPZ
;
11106 last_repz_prefix
= i
;
11109 prefixes
|= PREFIX_REPNZ
;
11110 last_repnz_prefix
= i
;
11113 prefixes
|= PREFIX_LOCK
;
11114 last_lock_prefix
= i
;
11117 prefixes
|= PREFIX_CS
;
11118 last_seg_prefix
= i
;
11119 active_seg_prefix
= PREFIX_CS
;
11122 prefixes
|= PREFIX_SS
;
11123 last_seg_prefix
= i
;
11124 active_seg_prefix
= PREFIX_SS
;
11127 prefixes
|= PREFIX_DS
;
11128 last_seg_prefix
= i
;
11129 active_seg_prefix
= PREFIX_DS
;
11132 prefixes
|= PREFIX_ES
;
11133 last_seg_prefix
= i
;
11134 active_seg_prefix
= PREFIX_ES
;
11137 prefixes
|= PREFIX_FS
;
11138 last_seg_prefix
= i
;
11139 active_seg_prefix
= PREFIX_FS
;
11142 prefixes
|= PREFIX_GS
;
11143 last_seg_prefix
= i
;
11144 active_seg_prefix
= PREFIX_GS
;
11147 prefixes
|= PREFIX_DATA
;
11148 last_data_prefix
= i
;
11151 prefixes
|= PREFIX_ADDR
;
11152 last_addr_prefix
= i
;
11155 /* fwait is really an instruction. If there are prefixes
11156 before the fwait, they belong to the fwait, *not* to the
11157 following instruction. */
11159 if (prefixes
|| rex
)
11161 prefixes
|= PREFIX_FWAIT
;
11163 /* This ensures that the previous REX prefixes are noticed
11164 as unused prefixes, as in the return case below. */
11168 prefixes
= PREFIX_FWAIT
;
11173 /* Rex is ignored when followed by another prefix. */
11179 if (*codep
!= FWAIT_OPCODE
)
11180 all_prefixes
[i
++] = *codep
;
11188 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11191 static const char *
11192 prefix_name (int pref
, int sizeflag
)
11194 static const char *rexes
[16] =
11197 "rex.B", /* 0x41 */
11198 "rex.X", /* 0x42 */
11199 "rex.XB", /* 0x43 */
11200 "rex.R", /* 0x44 */
11201 "rex.RB", /* 0x45 */
11202 "rex.RX", /* 0x46 */
11203 "rex.RXB", /* 0x47 */
11204 "rex.W", /* 0x48 */
11205 "rex.WB", /* 0x49 */
11206 "rex.WX", /* 0x4a */
11207 "rex.WXB", /* 0x4b */
11208 "rex.WR", /* 0x4c */
11209 "rex.WRB", /* 0x4d */
11210 "rex.WRX", /* 0x4e */
11211 "rex.WRXB", /* 0x4f */
11216 /* REX prefixes family. */
11233 return rexes
[pref
- 0x40];
11253 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11255 if (address_mode
== mode_64bit
)
11256 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11258 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11263 case XACQUIRE_PREFIX
:
11265 case XRELEASE_PREFIX
:
11269 case NOTRACK_PREFIX
:
11276 static char op_out
[MAX_OPERANDS
][100];
11277 static int op_ad
, op_index
[MAX_OPERANDS
];
11278 static int two_source_ops
;
11279 static bfd_vma op_address
[MAX_OPERANDS
];
11280 static bfd_vma op_riprel
[MAX_OPERANDS
];
11281 static bfd_vma start_pc
;
11284 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11285 * (see topic "Redundant prefixes" in the "Differences from 8086"
11286 * section of the "Virtual 8086 Mode" chapter.)
11287 * 'pc' should be the address of this instruction, it will
11288 * be used to print the target address if this is a relative jump or call
11289 * The function returns the length of this instruction in bytes.
11292 static char intel_syntax
;
11293 static char intel_mnemonic
= !SYSV386_COMPAT
;
11294 static char open_char
;
11295 static char close_char
;
11296 static char separator_char
;
11297 static char scale_char
;
11305 static enum x86_64_isa isa64
;
11307 /* Here for backwards compatibility. When gdb stops using
11308 print_insn_i386_att and print_insn_i386_intel these functions can
11309 disappear, and print_insn_i386 be merged into print_insn. */
11311 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11315 return print_insn (pc
, info
);
11319 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11323 return print_insn (pc
, info
);
11327 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11331 return print_insn (pc
, info
);
11335 print_i386_disassembler_options (FILE *stream
)
11337 fprintf (stream
, _("\n\
11338 The following i386/x86-64 specific disassembler options are supported for use\n\
11339 with the -M switch (multiple options should be separated by commas):\n"));
11341 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11342 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11343 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11344 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11345 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11346 fprintf (stream
, _(" att-mnemonic\n"
11347 " Display instruction in AT&T mnemonic\n"));
11348 fprintf (stream
, _(" intel-mnemonic\n"
11349 " Display instruction in Intel mnemonic\n"));
11350 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11351 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11352 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11353 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11354 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11355 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11356 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11357 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11361 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11363 /* Get a pointer to struct dis386 with a valid name. */
11365 static const struct dis386
*
11366 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11368 int vindex
, vex_table_index
;
11370 if (dp
->name
!= NULL
)
11373 switch (dp
->op
[0].bytemode
)
11375 case USE_REG_TABLE
:
11376 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11379 case USE_MOD_TABLE
:
11380 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11381 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11385 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11388 case USE_PREFIX_TABLE
:
11391 /* The prefix in VEX is implicit. */
11392 switch (vex
.prefix
)
11397 case REPE_PREFIX_OPCODE
:
11400 case DATA_PREFIX_OPCODE
:
11403 case REPNE_PREFIX_OPCODE
:
11413 int last_prefix
= -1;
11416 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11417 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11419 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11421 if (last_repz_prefix
> last_repnz_prefix
)
11424 prefix
= PREFIX_REPZ
;
11425 last_prefix
= last_repz_prefix
;
11430 prefix
= PREFIX_REPNZ
;
11431 last_prefix
= last_repnz_prefix
;
11434 /* Check if prefix should be ignored. */
11435 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11436 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11441 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11444 prefix
= PREFIX_DATA
;
11445 last_prefix
= last_data_prefix
;
11450 used_prefixes
|= prefix
;
11451 all_prefixes
[last_prefix
] = 0;
11454 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11457 case USE_X86_64_TABLE
:
11458 vindex
= address_mode
== mode_64bit
? 1 : 0;
11459 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11462 case USE_3BYTE_TABLE
:
11463 FETCH_DATA (info
, codep
+ 2);
11465 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11467 modrm
.mod
= (*codep
>> 6) & 3;
11468 modrm
.reg
= (*codep
>> 3) & 7;
11469 modrm
.rm
= *codep
& 7;
11472 case USE_VEX_LEN_TABLE
:
11476 switch (vex
.length
)
11489 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11492 case USE_EVEX_LEN_TABLE
:
11496 switch (vex
.length
)
11512 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11515 case USE_XOP_8F_TABLE
:
11516 FETCH_DATA (info
, codep
+ 3);
11517 rex
= ~(*codep
>> 5) & 0x7;
11519 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11520 switch ((*codep
& 0x1f))
11526 vex_table_index
= XOP_08
;
11529 vex_table_index
= XOP_09
;
11532 vex_table_index
= XOP_0A
;
11536 vex
.w
= *codep
& 0x80;
11537 if (vex
.w
&& address_mode
== mode_64bit
)
11540 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11541 if (address_mode
!= mode_64bit
)
11543 /* In 16/32-bit mode REX_B is silently ignored. */
11547 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11548 switch ((*codep
& 0x3))
11553 vex
.prefix
= DATA_PREFIX_OPCODE
;
11556 vex
.prefix
= REPE_PREFIX_OPCODE
;
11559 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11566 dp
= &xop_table
[vex_table_index
][vindex
];
11569 FETCH_DATA (info
, codep
+ 1);
11570 modrm
.mod
= (*codep
>> 6) & 3;
11571 modrm
.reg
= (*codep
>> 3) & 7;
11572 modrm
.rm
= *codep
& 7;
11575 case USE_VEX_C4_TABLE
:
11577 FETCH_DATA (info
, codep
+ 3);
11578 rex
= ~(*codep
>> 5) & 0x7;
11579 switch ((*codep
& 0x1f))
11585 vex_table_index
= VEX_0F
;
11588 vex_table_index
= VEX_0F38
;
11591 vex_table_index
= VEX_0F3A
;
11595 vex
.w
= *codep
& 0x80;
11596 if (address_mode
== mode_64bit
)
11603 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11604 is ignored, other REX bits are 0 and the highest bit in
11605 VEX.vvvv is also ignored (but we mustn't clear it here). */
11608 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11609 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11610 switch ((*codep
& 0x3))
11615 vex
.prefix
= DATA_PREFIX_OPCODE
;
11618 vex
.prefix
= REPE_PREFIX_OPCODE
;
11621 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11628 dp
= &vex_table
[vex_table_index
][vindex
];
11630 /* There is no MODRM byte for VEX0F 77. */
11631 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11633 FETCH_DATA (info
, codep
+ 1);
11634 modrm
.mod
= (*codep
>> 6) & 3;
11635 modrm
.reg
= (*codep
>> 3) & 7;
11636 modrm
.rm
= *codep
& 7;
11640 case USE_VEX_C5_TABLE
:
11642 FETCH_DATA (info
, codep
+ 2);
11643 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11645 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11647 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11648 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11649 switch ((*codep
& 0x3))
11654 vex
.prefix
= DATA_PREFIX_OPCODE
;
11657 vex
.prefix
= REPE_PREFIX_OPCODE
;
11660 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11667 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11669 /* There is no MODRM byte for VEX 77. */
11670 if (vindex
!= 0x77)
11672 FETCH_DATA (info
, codep
+ 1);
11673 modrm
.mod
= (*codep
>> 6) & 3;
11674 modrm
.reg
= (*codep
>> 3) & 7;
11675 modrm
.rm
= *codep
& 7;
11679 case USE_VEX_W_TABLE
:
11683 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11686 case USE_EVEX_TABLE
:
11687 two_source_ops
= 0;
11690 FETCH_DATA (info
, codep
+ 4);
11691 /* The first byte after 0x62. */
11692 rex
= ~(*codep
>> 5) & 0x7;
11693 vex
.r
= *codep
& 0x10;
11694 switch ((*codep
& 0xf))
11697 return &bad_opcode
;
11699 vex_table_index
= EVEX_0F
;
11702 vex_table_index
= EVEX_0F38
;
11705 vex_table_index
= EVEX_0F3A
;
11709 /* The second byte after 0x62. */
11711 vex
.w
= *codep
& 0x80;
11712 if (vex
.w
&& address_mode
== mode_64bit
)
11715 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11718 if (!(*codep
& 0x4))
11719 return &bad_opcode
;
11721 switch ((*codep
& 0x3))
11726 vex
.prefix
= DATA_PREFIX_OPCODE
;
11729 vex
.prefix
= REPE_PREFIX_OPCODE
;
11732 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11736 /* The third byte after 0x62. */
11739 /* Remember the static rounding bits. */
11740 vex
.ll
= (*codep
>> 5) & 3;
11741 vex
.b
= (*codep
& 0x10) != 0;
11743 vex
.v
= *codep
& 0x8;
11744 vex
.mask_register_specifier
= *codep
& 0x7;
11745 vex
.zeroing
= *codep
& 0x80;
11747 if (address_mode
!= mode_64bit
)
11749 /* In 16/32-bit mode silently ignore following bits. */
11759 dp
= &evex_table
[vex_table_index
][vindex
];
11761 FETCH_DATA (info
, codep
+ 1);
11762 modrm
.mod
= (*codep
>> 6) & 3;
11763 modrm
.reg
= (*codep
>> 3) & 7;
11764 modrm
.rm
= *codep
& 7;
11766 /* Set vector length. */
11767 if (modrm
.mod
== 3 && vex
.b
)
11783 return &bad_opcode
;
11796 if (dp
->name
!= NULL
)
11799 return get_valid_dis386 (dp
, info
);
11803 get_sib (disassemble_info
*info
, int sizeflag
)
11805 /* If modrm.mod == 3, operand must be register. */
11807 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11811 FETCH_DATA (info
, codep
+ 2);
11812 sib
.index
= (codep
[1] >> 3) & 7;
11813 sib
.scale
= (codep
[1] >> 6) & 3;
11814 sib
.base
= codep
[1] & 7;
11819 print_insn (bfd_vma pc
, disassemble_info
*info
)
11821 const struct dis386
*dp
;
11823 char *op_txt
[MAX_OPERANDS
];
11825 int sizeflag
, orig_sizeflag
;
11827 struct dis_private priv
;
11830 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11831 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11832 address_mode
= mode_32bit
;
11833 else if (info
->mach
== bfd_mach_i386_i8086
)
11835 address_mode
= mode_16bit
;
11836 priv
.orig_sizeflag
= 0;
11839 address_mode
= mode_64bit
;
11841 if (intel_syntax
== (char) -1)
11842 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11844 for (p
= info
->disassembler_options
; p
!= NULL
; )
11846 if (CONST_STRNEQ (p
, "amd64"))
11848 else if (CONST_STRNEQ (p
, "intel64"))
11850 else if (CONST_STRNEQ (p
, "x86-64"))
11852 address_mode
= mode_64bit
;
11853 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
11855 else if (CONST_STRNEQ (p
, "i386"))
11857 address_mode
= mode_32bit
;
11858 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
11860 else if (CONST_STRNEQ (p
, "i8086"))
11862 address_mode
= mode_16bit
;
11863 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
11865 else if (CONST_STRNEQ (p
, "intel"))
11868 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11869 intel_mnemonic
= 1;
11871 else if (CONST_STRNEQ (p
, "att"))
11874 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11875 intel_mnemonic
= 0;
11877 else if (CONST_STRNEQ (p
, "addr"))
11879 if (address_mode
== mode_64bit
)
11881 if (p
[4] == '3' && p
[5] == '2')
11882 priv
.orig_sizeflag
&= ~AFLAG
;
11883 else if (p
[4] == '6' && p
[5] == '4')
11884 priv
.orig_sizeflag
|= AFLAG
;
11888 if (p
[4] == '1' && p
[5] == '6')
11889 priv
.orig_sizeflag
&= ~AFLAG
;
11890 else if (p
[4] == '3' && p
[5] == '2')
11891 priv
.orig_sizeflag
|= AFLAG
;
11894 else if (CONST_STRNEQ (p
, "data"))
11896 if (p
[4] == '1' && p
[5] == '6')
11897 priv
.orig_sizeflag
&= ~DFLAG
;
11898 else if (p
[4] == '3' && p
[5] == '2')
11899 priv
.orig_sizeflag
|= DFLAG
;
11901 else if (CONST_STRNEQ (p
, "suffix"))
11902 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11904 p
= strchr (p
, ',');
11909 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11911 (*info
->fprintf_func
) (info
->stream
,
11912 _("64-bit address is disabled"));
11918 names64
= intel_names64
;
11919 names32
= intel_names32
;
11920 names16
= intel_names16
;
11921 names8
= intel_names8
;
11922 names8rex
= intel_names8rex
;
11923 names_seg
= intel_names_seg
;
11924 names_mm
= intel_names_mm
;
11925 names_bnd
= intel_names_bnd
;
11926 names_xmm
= intel_names_xmm
;
11927 names_ymm
= intel_names_ymm
;
11928 names_zmm
= intel_names_zmm
;
11929 index64
= intel_index64
;
11930 index32
= intel_index32
;
11931 names_mask
= intel_names_mask
;
11932 index16
= intel_index16
;
11935 separator_char
= '+';
11940 names64
= att_names64
;
11941 names32
= att_names32
;
11942 names16
= att_names16
;
11943 names8
= att_names8
;
11944 names8rex
= att_names8rex
;
11945 names_seg
= att_names_seg
;
11946 names_mm
= att_names_mm
;
11947 names_bnd
= att_names_bnd
;
11948 names_xmm
= att_names_xmm
;
11949 names_ymm
= att_names_ymm
;
11950 names_zmm
= att_names_zmm
;
11951 index64
= att_index64
;
11952 index32
= att_index32
;
11953 names_mask
= att_names_mask
;
11954 index16
= att_index16
;
11957 separator_char
= ',';
11961 /* The output looks better if we put 7 bytes on a line, since that
11962 puts most long word instructions on a single line. Use 8 bytes
11964 if ((info
->mach
& bfd_mach_l1om
) != 0)
11965 info
->bytes_per_line
= 8;
11967 info
->bytes_per_line
= 7;
11969 info
->private_data
= &priv
;
11970 priv
.max_fetched
= priv
.the_buffer
;
11971 priv
.insn_start
= pc
;
11974 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11982 start_codep
= priv
.the_buffer
;
11983 codep
= priv
.the_buffer
;
11985 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
11989 /* Getting here means we tried for data but didn't get it. That
11990 means we have an incomplete instruction of some sort. Just
11991 print the first byte as a prefix or a .byte pseudo-op. */
11992 if (codep
> priv
.the_buffer
)
11994 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
11996 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11999 /* Just print the first byte as a .byte instruction. */
12000 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12001 (unsigned int) priv
.the_buffer
[0]);
12011 sizeflag
= priv
.orig_sizeflag
;
12013 if (!ckprefix () || rex_used
)
12015 /* Too many prefixes or unused REX prefixes. */
12017 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12019 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12021 prefix_name (all_prefixes
[i
], sizeflag
));
12025 insn_codep
= codep
;
12027 FETCH_DATA (info
, codep
+ 1);
12028 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12030 if (((prefixes
& PREFIX_FWAIT
)
12031 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12033 /* Handle prefixes before fwait. */
12034 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12036 (*info
->fprintf_func
) (info
->stream
, "%s ",
12037 prefix_name (all_prefixes
[i
], sizeflag
));
12038 (*info
->fprintf_func
) (info
->stream
, "fwait");
12042 if (*codep
== 0x0f)
12044 unsigned char threebyte
;
12047 FETCH_DATA (info
, codep
+ 1);
12048 threebyte
= *codep
;
12049 dp
= &dis386_twobyte
[threebyte
];
12050 need_modrm
= twobyte_has_modrm
[*codep
];
12055 dp
= &dis386
[*codep
];
12056 need_modrm
= onebyte_has_modrm
[*codep
];
12060 /* Save sizeflag for printing the extra prefixes later before updating
12061 it for mnemonic and operand processing. The prefix names depend
12062 only on the address mode. */
12063 orig_sizeflag
= sizeflag
;
12064 if (prefixes
& PREFIX_ADDR
)
12066 if ((prefixes
& PREFIX_DATA
))
12072 FETCH_DATA (info
, codep
+ 1);
12073 modrm
.mod
= (*codep
>> 6) & 3;
12074 modrm
.reg
= (*codep
>> 3) & 7;
12075 modrm
.rm
= *codep
& 7;
12081 memset (&vex
, 0, sizeof (vex
));
12083 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12085 get_sib (info
, sizeflag
);
12086 dofloat (sizeflag
);
12090 dp
= get_valid_dis386 (dp
, info
);
12091 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12093 get_sib (info
, sizeflag
);
12094 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12097 op_ad
= MAX_OPERANDS
- 1 - i
;
12099 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12100 /* For EVEX instruction after the last operand masking
12101 should be printed. */
12102 if (i
== 0 && vex
.evex
)
12104 /* Don't print {%k0}. */
12105 if (vex
.mask_register_specifier
)
12108 oappend (names_mask
[vex
.mask_register_specifier
]);
12118 /* Clear instruction information. */
12121 the_info
->insn_info_valid
= 0;
12122 the_info
->branch_delay_insns
= 0;
12123 the_info
->data_size
= 0;
12124 the_info
->insn_type
= dis_noninsn
;
12125 the_info
->target
= 0;
12126 the_info
->target2
= 0;
12129 /* Reset jump operation indicator. */
12130 op_is_jump
= FALSE
;
12133 int jump_detection
= 0;
12135 /* Extract flags. */
12136 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12138 if ((dp
->op
[i
].rtn
== OP_J
)
12139 || (dp
->op
[i
].rtn
== OP_indirE
))
12140 jump_detection
|= 1;
12141 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
12142 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
12143 jump_detection
|= 2;
12144 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
12145 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
12146 jump_detection
|= 4;
12149 /* Determine if this is a jump or branch. */
12150 if ((jump_detection
& 0x3) == 0x3)
12153 if (jump_detection
& 0x4)
12154 the_info
->insn_type
= dis_condbranch
;
12156 the_info
->insn_type
=
12157 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
12158 ? dis_jsr
: dis_branch
;
12162 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12163 are all 0s in inverted form. */
12164 if (need_vex
&& vex
.register_specifier
!= 0)
12166 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12167 return end_codep
- priv
.the_buffer
;
12170 /* Check if the REX prefix is used. */
12171 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
12172 all_prefixes
[last_rex_prefix
] = 0;
12174 /* Check if the SEG prefix is used. */
12175 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12176 | PREFIX_FS
| PREFIX_GS
)) != 0
12177 && (used_prefixes
& active_seg_prefix
) != 0)
12178 all_prefixes
[last_seg_prefix
] = 0;
12180 /* Check if the ADDR prefix is used. */
12181 if ((prefixes
& PREFIX_ADDR
) != 0
12182 && (used_prefixes
& PREFIX_ADDR
) != 0)
12183 all_prefixes
[last_addr_prefix
] = 0;
12185 /* Check if the DATA prefix is used. */
12186 if ((prefixes
& PREFIX_DATA
) != 0
12187 && (used_prefixes
& PREFIX_DATA
) != 0
12189 all_prefixes
[last_data_prefix
] = 0;
12191 /* Print the extra prefixes. */
12193 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12194 if (all_prefixes
[i
])
12197 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12200 prefix_length
+= strlen (name
) + 1;
12201 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12204 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12205 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12206 used by putop and MMX/SSE operand and may be overriden by the
12207 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12209 if (dp
->prefix_requirement
== PREFIX_OPCODE
12211 ? vex
.prefix
== REPE_PREFIX_OPCODE
12212 || vex
.prefix
== REPNE_PREFIX_OPCODE
12214 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12216 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12218 ? vex
.prefix
== DATA_PREFIX_OPCODE
12220 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12222 && (used_prefixes
& PREFIX_DATA
) == 0))
12223 || (vex
.evex
&& !vex
.w
!= !(used_prefixes
& PREFIX_DATA
))))
12225 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12226 return end_codep
- priv
.the_buffer
;
12229 /* Check maximum code length. */
12230 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12232 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12233 return MAX_CODE_LENGTH
;
12236 obufp
= mnemonicendp
;
12237 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12240 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12242 /* The enter and bound instructions are printed with operands in the same
12243 order as the intel book; everything else is printed in reverse order. */
12244 if (intel_syntax
|| two_source_ops
)
12248 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12249 op_txt
[i
] = op_out
[i
];
12251 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12252 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12254 op_txt
[2] = op_out
[3];
12255 op_txt
[3] = op_out
[2];
12258 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12260 op_ad
= op_index
[i
];
12261 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12262 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12263 riprel
= op_riprel
[i
];
12264 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12265 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12270 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12271 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12275 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12279 (*info
->fprintf_func
) (info
->stream
, ",");
12280 if (op_index
[i
] != -1 && !op_riprel
[i
])
12282 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
12284 if (the_info
&& op_is_jump
)
12286 the_info
->insn_info_valid
= 1;
12287 the_info
->branch_delay_insns
= 0;
12288 the_info
->data_size
= 0;
12289 the_info
->target
= target
;
12290 the_info
->target2
= 0;
12292 (*info
->print_address_func
) (target
, info
);
12295 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12299 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12300 if (op_index
[i
] != -1 && op_riprel
[i
])
12302 (*info
->fprintf_func
) (info
->stream
, " # ");
12303 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12304 + op_address
[op_index
[i
]]), info
);
12307 return codep
- priv
.the_buffer
;
12310 static const char *float_mem
[] = {
12385 static const unsigned char float_mem_mode
[] = {
12460 #define ST { OP_ST, 0 }
12461 #define STi { OP_STi, 0 }
12463 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12464 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12465 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12466 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12467 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12468 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12469 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12470 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12471 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12473 static const struct dis386 float_reg
[][8] = {
12476 { "fadd", { ST
, STi
}, 0 },
12477 { "fmul", { ST
, STi
}, 0 },
12478 { "fcom", { STi
}, 0 },
12479 { "fcomp", { STi
}, 0 },
12480 { "fsub", { ST
, STi
}, 0 },
12481 { "fsubr", { ST
, STi
}, 0 },
12482 { "fdiv", { ST
, STi
}, 0 },
12483 { "fdivr", { ST
, STi
}, 0 },
12487 { "fld", { STi
}, 0 },
12488 { "fxch", { STi
}, 0 },
12498 { "fcmovb", { ST
, STi
}, 0 },
12499 { "fcmove", { ST
, STi
}, 0 },
12500 { "fcmovbe",{ ST
, STi
}, 0 },
12501 { "fcmovu", { ST
, STi
}, 0 },
12509 { "fcmovnb",{ ST
, STi
}, 0 },
12510 { "fcmovne",{ ST
, STi
}, 0 },
12511 { "fcmovnbe",{ ST
, STi
}, 0 },
12512 { "fcmovnu",{ ST
, STi
}, 0 },
12514 { "fucomi", { ST
, STi
}, 0 },
12515 { "fcomi", { ST
, STi
}, 0 },
12520 { "fadd", { STi
, ST
}, 0 },
12521 { "fmul", { STi
, ST
}, 0 },
12524 { "fsub{!M|r}", { STi
, ST
}, 0 },
12525 { "fsub{M|}", { STi
, ST
}, 0 },
12526 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12527 { "fdiv{M|}", { STi
, ST
}, 0 },
12531 { "ffree", { STi
}, 0 },
12533 { "fst", { STi
}, 0 },
12534 { "fstp", { STi
}, 0 },
12535 { "fucom", { STi
}, 0 },
12536 { "fucomp", { STi
}, 0 },
12542 { "faddp", { STi
, ST
}, 0 },
12543 { "fmulp", { STi
, ST
}, 0 },
12546 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12547 { "fsub{M|}p", { STi
, ST
}, 0 },
12548 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12549 { "fdiv{M|}p", { STi
, ST
}, 0 },
12553 { "ffreep", { STi
}, 0 },
12558 { "fucomip", { ST
, STi
}, 0 },
12559 { "fcomip", { ST
, STi
}, 0 },
12564 static char *fgrps
[][8] = {
12567 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12572 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12577 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12582 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12587 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12592 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12597 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12602 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12603 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12608 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12613 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12618 swap_operand (void)
12620 mnemonicendp
[0] = '.';
12621 mnemonicendp
[1] = 's';
12626 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12627 int sizeflag ATTRIBUTE_UNUSED
)
12629 /* Skip mod/rm byte. */
12635 dofloat (int sizeflag
)
12637 const struct dis386
*dp
;
12638 unsigned char floatop
;
12640 floatop
= codep
[-1];
12642 if (modrm
.mod
!= 3)
12644 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12646 putop (float_mem
[fp_indx
], sizeflag
);
12649 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12652 /* Skip mod/rm byte. */
12656 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12657 if (dp
->name
== NULL
)
12659 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12661 /* Instruction fnstsw is only one with strange arg. */
12662 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12663 strcpy (op_out
[0], names16
[0]);
12667 putop (dp
->name
, sizeflag
);
12672 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12677 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12681 /* Like oappend (below), but S is a string starting with '%'.
12682 In Intel syntax, the '%' is elided. */
12684 oappend_maybe_intel (const char *s
)
12686 oappend (s
+ intel_syntax
);
12690 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12692 oappend_maybe_intel ("%st");
12696 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12698 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12699 oappend_maybe_intel (scratchbuf
);
12702 /* Capital letters in template are macros. */
12704 putop (const char *in_template
, int sizeflag
)
12709 unsigned int l
= 0, len
= 1;
12712 #define SAVE_LAST(c) \
12713 if (l < len && l < sizeof (last)) \
12718 for (p
= in_template
; *p
; p
++)
12734 while (*++p
!= '|')
12735 if (*p
== '}' || *p
== '\0')
12741 while (*++p
!= '}')
12753 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12757 if (l
== 0 && len
== 1)
12762 if (sizeflag
& SUFFIX_ALWAYS
)
12775 if (address_mode
== mode_64bit
12776 && !(prefixes
& PREFIX_ADDR
))
12787 if (intel_syntax
&& !alt
)
12789 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12791 if (sizeflag
& DFLAG
)
12792 *obufp
++ = intel_syntax
? 'd' : 'l';
12794 *obufp
++ = intel_syntax
? 'w' : 's';
12795 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12799 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12802 if (modrm
.mod
== 3)
12808 if (sizeflag
& DFLAG
)
12809 *obufp
++ = intel_syntax
? 'd' : 'l';
12812 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12818 case 'E': /* For jcxz/jecxz */
12819 if (address_mode
== mode_64bit
)
12821 if (sizeflag
& AFLAG
)
12827 if (sizeflag
& AFLAG
)
12829 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12834 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12836 if (sizeflag
& AFLAG
)
12837 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12839 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12840 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12844 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12846 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12850 if (!(rex
& REX_W
))
12851 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12856 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12857 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12859 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12862 if (prefixes
& PREFIX_DS
)
12876 if (l
!= 0 || len
!= 1)
12878 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12883 if (!need_vex
|| !vex
.evex
)
12886 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12888 switch (vex
.length
)
12906 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12911 /* Fall through. */
12914 if (l
!= 0 || len
!= 1)
12922 if (sizeflag
& SUFFIX_ALWAYS
)
12926 if (intel_mnemonic
!= cond
)
12930 if ((prefixes
& PREFIX_FWAIT
) == 0)
12933 used_prefixes
|= PREFIX_FWAIT
;
12939 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12943 if (!(rex
& REX_W
))
12944 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12948 && address_mode
== mode_64bit
12949 && isa64
== intel64
)
12954 /* Fall through. */
12957 && address_mode
== mode_64bit
12958 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12963 /* Fall through. */
12966 if (l
== 0 && len
== 1)
12971 if ((rex
& REX_W
) == 0
12972 && (prefixes
& PREFIX_DATA
))
12974 if ((sizeflag
& DFLAG
) == 0)
12976 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12980 if ((prefixes
& PREFIX_DATA
)
12982 || (sizeflag
& SUFFIX_ALWAYS
))
12989 if (sizeflag
& DFLAG
)
12993 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12999 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13005 if ((prefixes
& PREFIX_DATA
)
13007 || (sizeflag
& SUFFIX_ALWAYS
))
13014 if (sizeflag
& DFLAG
)
13015 *obufp
++ = intel_syntax
? 'd' : 'l';
13018 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13026 if (address_mode
== mode_64bit
13027 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13029 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13033 /* Fall through. */
13036 if (l
== 0 && len
== 1)
13039 if (intel_syntax
&& !alt
)
13042 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13048 if (sizeflag
& DFLAG
)
13049 *obufp
++ = intel_syntax
? 'd' : 'l';
13052 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13058 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13063 if ((intel_syntax
&& need_modrm
)
13064 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13071 else if((address_mode
== mode_64bit
&& need_modrm
)
13072 || (sizeflag
& SUFFIX_ALWAYS
))
13073 *obufp
++ = intel_syntax
? 'd' : 'l';
13080 else if (sizeflag
& DFLAG
)
13089 if (intel_syntax
&& !p
[1]
13090 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13092 if (!(rex
& REX_W
))
13093 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13096 if (l
== 0 && len
== 1)
13100 if (address_mode
== mode_64bit
13101 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13103 if (sizeflag
& SUFFIX_ALWAYS
)
13125 /* Fall through. */
13128 if (l
== 0 && len
== 1)
13133 if (sizeflag
& SUFFIX_ALWAYS
)
13139 if (sizeflag
& DFLAG
)
13143 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13157 if (address_mode
== mode_64bit
13158 && !(prefixes
& PREFIX_ADDR
))
13169 if (l
!= 0 || len
!= 1)
13175 ? vex
.prefix
== DATA_PREFIX_OPCODE
13176 : prefixes
& PREFIX_DATA
)
13179 used_prefixes
|= PREFIX_DATA
;
13185 if (l
== 0 && len
== 1)
13189 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13197 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13199 switch (vex
.length
)
13215 if (l
== 0 && len
== 1)
13217 /* operand size flag for cwtl, cbtw */
13226 else if (sizeflag
& DFLAG
)
13230 if (!(rex
& REX_W
))
13231 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13238 && last
[0] != 'L'))
13245 if (last
[0] == 'X')
13246 *obufp
++ = vex
.w
? 'd': 's';
13248 *obufp
++ = vex
.w
? 'q': 'd';
13254 if (isa64
== intel64
&& (rex
& REX_W
))
13260 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13262 if (sizeflag
& DFLAG
)
13266 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13272 if (address_mode
== mode_64bit
13273 && (isa64
== intel64
13274 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13276 else if ((prefixes
& PREFIX_DATA
))
13278 if (!(sizeflag
& DFLAG
))
13280 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13286 mnemonicendp
= obufp
;
13291 oappend (const char *s
)
13293 obufp
= stpcpy (obufp
, s
);
13299 /* Only print the active segment register. */
13300 if (!active_seg_prefix
)
13303 used_prefixes
|= active_seg_prefix
;
13304 switch (active_seg_prefix
)
13307 oappend_maybe_intel ("%cs:");
13310 oappend_maybe_intel ("%ds:");
13313 oappend_maybe_intel ("%ss:");
13316 oappend_maybe_intel ("%es:");
13319 oappend_maybe_intel ("%fs:");
13322 oappend_maybe_intel ("%gs:");
13330 OP_indirE (int bytemode
, int sizeflag
)
13334 OP_E (bytemode
, sizeflag
);
13338 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13340 if (address_mode
== mode_64bit
)
13348 sprintf_vma (tmp
, disp
);
13349 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13350 strcpy (buf
+ 2, tmp
+ i
);
13354 bfd_signed_vma v
= disp
;
13361 /* Check for possible overflow on 0x8000000000000000. */
13364 strcpy (buf
, "9223372036854775808");
13378 tmp
[28 - i
] = (v
% 10) + '0';
13382 strcpy (buf
, tmp
+ 29 - i
);
13388 sprintf (buf
, "0x%x", (unsigned int) disp
);
13390 sprintf (buf
, "%d", (int) disp
);
13394 /* Put DISP in BUF as signed hex number. */
13397 print_displacement (char *buf
, bfd_vma disp
)
13399 bfd_signed_vma val
= disp
;
13408 /* Check for possible overflow. */
13411 switch (address_mode
)
13414 strcpy (buf
+ j
, "0x8000000000000000");
13417 strcpy (buf
+ j
, "0x80000000");
13420 strcpy (buf
+ j
, "0x8000");
13430 sprintf_vma (tmp
, (bfd_vma
) val
);
13431 for (i
= 0; tmp
[i
] == '0'; i
++)
13433 if (tmp
[i
] == '\0')
13435 strcpy (buf
+ j
, tmp
+ i
);
13439 intel_operand_size (int bytemode
, int sizeflag
)
13443 && (bytemode
== x_mode
13444 || bytemode
== evex_half_bcst_xmmq_mode
))
13447 oappend ("QWORD PTR ");
13449 oappend ("DWORD PTR ");
13458 oappend ("BYTE PTR ");
13463 oappend ("WORD PTR ");
13466 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13468 oappend ("QWORD PTR ");
13471 /* Fall through. */
13473 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13475 oappend ("QWORD PTR ");
13478 /* Fall through. */
13484 oappend ("QWORD PTR ");
13487 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13488 oappend ("DWORD PTR ");
13490 oappend ("WORD PTR ");
13491 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13495 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13497 oappend ("WORD PTR ");
13498 if (!(rex
& REX_W
))
13499 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13502 if (sizeflag
& DFLAG
)
13503 oappend ("QWORD PTR ");
13505 oappend ("DWORD PTR ");
13506 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13509 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13510 oappend ("WORD PTR ");
13512 oappend ("DWORD PTR ");
13513 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13516 case d_scalar_mode
:
13517 case d_scalar_swap_mode
:
13520 oappend ("DWORD PTR ");
13523 case q_scalar_mode
:
13524 case q_scalar_swap_mode
:
13526 oappend ("QWORD PTR ");
13529 if (address_mode
== mode_64bit
)
13530 oappend ("QWORD PTR ");
13532 oappend ("DWORD PTR ");
13535 if (sizeflag
& DFLAG
)
13536 oappend ("FWORD PTR ");
13538 oappend ("DWORD PTR ");
13539 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13542 oappend ("TBYTE PTR ");
13546 case evex_x_gscat_mode
:
13547 case evex_x_nobcst_mode
:
13548 case b_scalar_mode
:
13549 case w_scalar_mode
:
13552 switch (vex
.length
)
13555 oappend ("XMMWORD PTR ");
13558 oappend ("YMMWORD PTR ");
13561 oappend ("ZMMWORD PTR ");
13568 oappend ("XMMWORD PTR ");
13571 oappend ("XMMWORD PTR ");
13574 oappend ("YMMWORD PTR ");
13577 case evex_half_bcst_xmmq_mode
:
13581 switch (vex
.length
)
13584 oappend ("QWORD PTR ");
13587 oappend ("XMMWORD PTR ");
13590 oappend ("YMMWORD PTR ");
13600 switch (vex
.length
)
13605 oappend ("BYTE PTR ");
13615 switch (vex
.length
)
13620 oappend ("WORD PTR ");
13630 switch (vex
.length
)
13635 oappend ("DWORD PTR ");
13645 switch (vex
.length
)
13650 oappend ("QWORD PTR ");
13660 switch (vex
.length
)
13663 oappend ("WORD PTR ");
13666 oappend ("DWORD PTR ");
13669 oappend ("QWORD PTR ");
13679 switch (vex
.length
)
13682 oappend ("DWORD PTR ");
13685 oappend ("QWORD PTR ");
13688 oappend ("XMMWORD PTR ");
13698 switch (vex
.length
)
13701 oappend ("QWORD PTR ");
13704 oappend ("YMMWORD PTR ");
13707 oappend ("ZMMWORD PTR ");
13717 switch (vex
.length
)
13721 oappend ("XMMWORD PTR ");
13728 oappend ("OWORD PTR ");
13730 case vex_scalar_w_dq_mode
:
13735 oappend ("QWORD PTR ");
13737 oappend ("DWORD PTR ");
13739 case vex_vsib_d_w_dq_mode
:
13740 case vex_vsib_q_w_dq_mode
:
13747 oappend ("QWORD PTR ");
13749 oappend ("DWORD PTR ");
13753 switch (vex
.length
)
13756 oappend ("XMMWORD PTR ");
13759 oappend ("YMMWORD PTR ");
13762 oappend ("ZMMWORD PTR ");
13769 case vex_vsib_q_w_d_mode
:
13770 case vex_vsib_d_w_d_mode
:
13771 if (!need_vex
|| !vex
.evex
)
13774 switch (vex
.length
)
13777 oappend ("QWORD PTR ");
13780 oappend ("XMMWORD PTR ");
13783 oappend ("YMMWORD PTR ");
13791 if (!need_vex
|| vex
.length
!= 128)
13794 oappend ("DWORD PTR ");
13796 oappend ("BYTE PTR ");
13802 oappend ("QWORD PTR ");
13804 oappend ("WORD PTR ");
13814 OP_E_register (int bytemode
, int sizeflag
)
13816 int reg
= modrm
.rm
;
13817 const char **names
;
13823 if ((sizeflag
& SUFFIX_ALWAYS
)
13824 && (bytemode
== b_swap_mode
13825 || bytemode
== bnd_swap_mode
13826 || bytemode
== v_swap_mode
))
13852 names
= address_mode
== mode_64bit
? names64
: names32
;
13855 case bnd_swap_mode
:
13864 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13869 /* Fall through. */
13871 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13877 /* Fall through. */
13889 if ((sizeflag
& DFLAG
)
13890 || (bytemode
!= v_mode
13891 && bytemode
!= v_swap_mode
))
13895 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13899 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13903 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13906 names
= (address_mode
== mode_64bit
13907 ? names64
: names32
);
13908 if (!(prefixes
& PREFIX_ADDR
))
13909 names
= (address_mode
== mode_16bit
13910 ? names16
: names
);
13913 /* Remove "addr16/addr32". */
13914 all_prefixes
[last_addr_prefix
] = 0;
13915 names
= (address_mode
!= mode_32bit
13916 ? names32
: names16
);
13917 used_prefixes
|= PREFIX_ADDR
;
13927 names
= names_mask
;
13932 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13935 oappend (names
[reg
]);
13939 OP_E_memory (int bytemode
, int sizeflag
)
13942 int add
= (rex
& REX_B
) ? 8 : 0;
13948 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13950 && bytemode
!= x_mode
13951 && bytemode
!= xmmq_mode
13952 && bytemode
!= evex_half_bcst_xmmq_mode
)
13968 if (address_mode
!= mode_64bit
)
13974 case vex_scalar_w_dq_mode
:
13975 case vex_vsib_d_w_dq_mode
:
13976 case vex_vsib_d_w_d_mode
:
13977 case vex_vsib_q_w_dq_mode
:
13978 case vex_vsib_q_w_d_mode
:
13979 case evex_x_gscat_mode
:
13980 shift
= vex
.w
? 3 : 2;
13983 case evex_half_bcst_xmmq_mode
:
13987 shift
= vex
.w
? 3 : 2;
13990 /* Fall through. */
13994 case evex_x_nobcst_mode
:
13996 switch (vex
.length
)
14019 case q_scalar_mode
:
14021 case q_scalar_swap_mode
:
14027 case d_scalar_mode
:
14029 case d_scalar_swap_mode
:
14032 case w_scalar_mode
:
14036 case b_scalar_mode
:
14043 /* Make necessary corrections to shift for modes that need it.
14044 For these modes we currently have shift 4, 5 or 6 depending on
14045 vex.length (it corresponds to xmmword, ymmword or zmmword
14046 operand). We might want to make it 3, 4 or 5 (e.g. for
14047 xmmq_mode). In case of broadcast enabled the corrections
14048 aren't needed, as element size is always 32 or 64 bits. */
14050 && (bytemode
== xmmq_mode
14051 || bytemode
== evex_half_bcst_xmmq_mode
))
14053 else if (bytemode
== xmmqd_mode
)
14055 else if (bytemode
== xmmdw_mode
)
14057 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14065 intel_operand_size (bytemode
, sizeflag
);
14068 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14070 /* 32/64 bit address mode */
14080 int addr32flag
= !((sizeflag
& AFLAG
)
14081 || bytemode
== v_bnd_mode
14082 || bytemode
== v_bndmk_mode
14083 || bytemode
== bnd_mode
14084 || bytemode
== bnd_swap_mode
);
14085 const char **indexes64
= names64
;
14086 const char **indexes32
= names32
;
14096 vindex
= sib
.index
;
14102 case vex_vsib_d_w_dq_mode
:
14103 case vex_vsib_d_w_d_mode
:
14104 case vex_vsib_q_w_dq_mode
:
14105 case vex_vsib_q_w_d_mode
:
14115 switch (vex
.length
)
14118 indexes64
= indexes32
= names_xmm
;
14122 || bytemode
== vex_vsib_q_w_dq_mode
14123 || bytemode
== vex_vsib_q_w_d_mode
)
14124 indexes64
= indexes32
= names_ymm
;
14126 indexes64
= indexes32
= names_xmm
;
14130 || bytemode
== vex_vsib_q_w_dq_mode
14131 || bytemode
== vex_vsib_q_w_d_mode
)
14132 indexes64
= indexes32
= names_zmm
;
14134 indexes64
= indexes32
= names_ymm
;
14141 haveindex
= vindex
!= 4;
14148 rbase
= base
+ add
;
14156 if (address_mode
== mode_64bit
&& !havesib
)
14159 if (riprel
&& bytemode
== v_bndmk_mode
)
14167 FETCH_DATA (the_info
, codep
+ 1);
14169 if ((disp
& 0x80) != 0)
14171 if (vex
.evex
&& shift
> 0)
14184 && address_mode
!= mode_16bit
)
14186 if (address_mode
== mode_64bit
)
14188 /* Display eiz instead of addr32. */
14189 needindex
= addr32flag
;
14194 /* In 32-bit mode, we need index register to tell [offset]
14195 from [eiz*1 + offset]. */
14200 havedisp
= (havebase
14202 || (havesib
&& (haveindex
|| scale
!= 0)));
14205 if (modrm
.mod
!= 0 || base
== 5)
14207 if (havedisp
|| riprel
)
14208 print_displacement (scratchbuf
, disp
);
14210 print_operand_value (scratchbuf
, 1, disp
);
14211 oappend (scratchbuf
);
14215 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14219 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14220 && (address_mode
!= mode_64bit
14221 || ((bytemode
!= v_bnd_mode
)
14222 && (bytemode
!= v_bndmk_mode
)
14223 && (bytemode
!= bnd_mode
)
14224 && (bytemode
!= bnd_swap_mode
))))
14225 used_prefixes
|= PREFIX_ADDR
;
14227 if (havedisp
|| (intel_syntax
&& riprel
))
14229 *obufp
++ = open_char
;
14230 if (intel_syntax
&& riprel
)
14233 oappend (!addr32flag
? "rip" : "eip");
14237 oappend (address_mode
== mode_64bit
&& !addr32flag
14238 ? names64
[rbase
] : names32
[rbase
]);
14241 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14242 print index to tell base + index from base. */
14246 || (havebase
&& base
!= ESP_REG_NUM
))
14248 if (!intel_syntax
|| havebase
)
14250 *obufp
++ = separator_char
;
14254 oappend (address_mode
== mode_64bit
&& !addr32flag
14255 ? indexes64
[vindex
] : indexes32
[vindex
]);
14257 oappend (address_mode
== mode_64bit
&& !addr32flag
14258 ? index64
: index32
);
14260 *obufp
++ = scale_char
;
14262 sprintf (scratchbuf
, "%d", 1 << scale
);
14263 oappend (scratchbuf
);
14267 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14269 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14274 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14278 disp
= - (bfd_signed_vma
) disp
;
14282 print_displacement (scratchbuf
, disp
);
14284 print_operand_value (scratchbuf
, 1, disp
);
14285 oappend (scratchbuf
);
14288 *obufp
++ = close_char
;
14291 else if (intel_syntax
)
14293 if (modrm
.mod
!= 0 || base
== 5)
14295 if (!active_seg_prefix
)
14297 oappend (names_seg
[ds_reg
- es_reg
]);
14300 print_operand_value (scratchbuf
, 1, disp
);
14301 oappend (scratchbuf
);
14305 else if (bytemode
== v_bnd_mode
14306 || bytemode
== v_bndmk_mode
14307 || bytemode
== bnd_mode
14308 || bytemode
== bnd_swap_mode
)
14315 /* 16 bit address mode */
14316 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14323 if ((disp
& 0x8000) != 0)
14328 FETCH_DATA (the_info
, codep
+ 1);
14330 if ((disp
& 0x80) != 0)
14332 if (vex
.evex
&& shift
> 0)
14337 if ((disp
& 0x8000) != 0)
14343 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14345 print_displacement (scratchbuf
, disp
);
14346 oappend (scratchbuf
);
14349 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14351 *obufp
++ = open_char
;
14353 oappend (index16
[modrm
.rm
]);
14355 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14357 if ((bfd_signed_vma
) disp
>= 0)
14362 else if (modrm
.mod
!= 1)
14366 disp
= - (bfd_signed_vma
) disp
;
14369 print_displacement (scratchbuf
, disp
);
14370 oappend (scratchbuf
);
14373 *obufp
++ = close_char
;
14376 else if (intel_syntax
)
14378 if (!active_seg_prefix
)
14380 oappend (names_seg
[ds_reg
- es_reg
]);
14383 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14384 oappend (scratchbuf
);
14387 if (vex
.evex
&& vex
.b
14388 && (bytemode
== x_mode
14389 || bytemode
== xmmq_mode
14390 || bytemode
== evex_half_bcst_xmmq_mode
))
14393 || bytemode
== xmmq_mode
14394 || bytemode
== evex_half_bcst_xmmq_mode
)
14396 switch (vex
.length
)
14399 oappend ("{1to2}");
14402 oappend ("{1to4}");
14405 oappend ("{1to8}");
14413 switch (vex
.length
)
14416 oappend ("{1to4}");
14419 oappend ("{1to8}");
14422 oappend ("{1to16}");
14432 OP_E (int bytemode
, int sizeflag
)
14434 /* Skip mod/rm byte. */
14438 if (modrm
.mod
== 3)
14439 OP_E_register (bytemode
, sizeflag
);
14441 OP_E_memory (bytemode
, sizeflag
);
14445 OP_G (int bytemode
, int sizeflag
)
14448 const char **names
;
14457 oappend (names8rex
[modrm
.reg
+ add
]);
14459 oappend (names8
[modrm
.reg
+ add
]);
14462 oappend (names16
[modrm
.reg
+ add
]);
14467 oappend (names32
[modrm
.reg
+ add
]);
14470 oappend (names64
[modrm
.reg
+ add
]);
14473 if (modrm
.reg
> 0x3)
14478 oappend (names_bnd
[modrm
.reg
]);
14488 oappend (names64
[modrm
.reg
+ add
]);
14491 if ((sizeflag
& DFLAG
)
14492 || (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
))
14493 oappend (names32
[modrm
.reg
+ add
]);
14495 oappend (names16
[modrm
.reg
+ add
]);
14496 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14500 names
= (address_mode
== mode_64bit
14501 ? names64
: names32
);
14502 if (!(prefixes
& PREFIX_ADDR
))
14504 if (address_mode
== mode_16bit
)
14509 /* Remove "addr16/addr32". */
14510 all_prefixes
[last_addr_prefix
] = 0;
14511 names
= (address_mode
!= mode_32bit
14512 ? names32
: names16
);
14513 used_prefixes
|= PREFIX_ADDR
;
14515 oappend (names
[modrm
.reg
+ add
]);
14518 if (address_mode
== mode_64bit
)
14519 oappend (names64
[modrm
.reg
+ add
]);
14521 oappend (names32
[modrm
.reg
+ add
]);
14525 if ((modrm
.reg
+ add
) > 0x7)
14530 oappend (names_mask
[modrm
.reg
+ add
]);
14533 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14546 FETCH_DATA (the_info
, codep
+ 8);
14547 a
= *codep
++ & 0xff;
14548 a
|= (*codep
++ & 0xff) << 8;
14549 a
|= (*codep
++ & 0xff) << 16;
14550 a
|= (*codep
++ & 0xffu
) << 24;
14551 b
= *codep
++ & 0xff;
14552 b
|= (*codep
++ & 0xff) << 8;
14553 b
|= (*codep
++ & 0xff) << 16;
14554 b
|= (*codep
++ & 0xffu
) << 24;
14555 x
= a
+ ((bfd_vma
) b
<< 32);
14563 static bfd_signed_vma
14566 bfd_signed_vma x
= 0;
14568 FETCH_DATA (the_info
, codep
+ 4);
14569 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14570 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14571 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14572 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14576 static bfd_signed_vma
14579 bfd_signed_vma x
= 0;
14581 FETCH_DATA (the_info
, codep
+ 4);
14582 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14583 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14584 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14585 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14587 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14597 FETCH_DATA (the_info
, codep
+ 2);
14598 x
= *codep
++ & 0xff;
14599 x
|= (*codep
++ & 0xff) << 8;
14604 set_op (bfd_vma op
, int riprel
)
14606 op_index
[op_ad
] = op_ad
;
14607 if (address_mode
== mode_64bit
)
14609 op_address
[op_ad
] = op
;
14610 op_riprel
[op_ad
] = riprel
;
14614 /* Mask to get a 32-bit address. */
14615 op_address
[op_ad
] = op
& 0xffffffff;
14616 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14621 OP_REG (int code
, int sizeflag
)
14628 case es_reg
: case ss_reg
: case cs_reg
:
14629 case ds_reg
: case fs_reg
: case gs_reg
:
14630 oappend (names_seg
[code
- es_reg
]);
14642 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14643 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14644 s
= names16
[code
- ax_reg
+ add
];
14646 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14647 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14650 s
= names8rex
[code
- al_reg
+ add
];
14652 s
= names8
[code
- al_reg
];
14654 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14655 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14656 if (address_mode
== mode_64bit
14657 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14659 s
= names64
[code
- rAX_reg
+ add
];
14662 code
+= eAX_reg
- rAX_reg
;
14663 /* Fall through. */
14664 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14665 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14668 s
= names64
[code
- eAX_reg
+ add
];
14671 if (sizeflag
& DFLAG
)
14672 s
= names32
[code
- eAX_reg
+ add
];
14674 s
= names16
[code
- eAX_reg
+ add
];
14675 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14679 s
= INTERNAL_DISASSEMBLER_ERROR
;
14686 OP_IMREG (int code
, int sizeflag
)
14698 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14699 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14700 s
= names16
[code
- ax_reg
];
14702 case es_reg
: case ss_reg
: case cs_reg
:
14703 case ds_reg
: case fs_reg
: case gs_reg
:
14704 s
= names_seg
[code
- es_reg
];
14706 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14707 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14710 s
= names8rex
[code
- al_reg
];
14712 s
= names8
[code
- al_reg
];
14714 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14715 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14718 s
= names64
[code
- eAX_reg
];
14721 if (sizeflag
& DFLAG
)
14722 s
= names32
[code
- eAX_reg
];
14724 s
= names16
[code
- eAX_reg
];
14725 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14728 case z_mode_ax_reg
:
14729 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14733 if (!(rex
& REX_W
))
14734 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14737 s
= INTERNAL_DISASSEMBLER_ERROR
;
14744 OP_I (int bytemode
, int sizeflag
)
14747 bfd_signed_vma mask
= -1;
14752 FETCH_DATA (the_info
, codep
+ 1);
14762 if (sizeflag
& DFLAG
)
14772 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14788 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14793 scratchbuf
[0] = '$';
14794 print_operand_value (scratchbuf
+ 1, 1, op
);
14795 oappend_maybe_intel (scratchbuf
);
14796 scratchbuf
[0] = '\0';
14800 OP_I64 (int bytemode
, int sizeflag
)
14802 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14804 OP_I (bytemode
, sizeflag
);
14810 scratchbuf
[0] = '$';
14811 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14812 oappend_maybe_intel (scratchbuf
);
14813 scratchbuf
[0] = '\0';
14817 OP_sI (int bytemode
, int sizeflag
)
14825 FETCH_DATA (the_info
, codep
+ 1);
14827 if ((op
& 0x80) != 0)
14829 if (bytemode
== b_T_mode
)
14831 if (address_mode
!= mode_64bit
14832 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14834 /* The operand-size prefix is overridden by a REX prefix. */
14835 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14843 if (!(rex
& REX_W
))
14845 if (sizeflag
& DFLAG
)
14853 /* The operand-size prefix is overridden by a REX prefix. */
14854 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14860 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14864 scratchbuf
[0] = '$';
14865 print_operand_value (scratchbuf
+ 1, 1, op
);
14866 oappend_maybe_intel (scratchbuf
);
14870 OP_J (int bytemode
, int sizeflag
)
14874 bfd_vma segment
= 0;
14879 FETCH_DATA (the_info
, codep
+ 1);
14881 if ((disp
& 0x80) != 0)
14885 if (isa64
!= intel64
)
14888 if ((sizeflag
& DFLAG
)
14889 || (address_mode
== mode_64bit
14890 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
14891 || (rex
& REX_W
))))
14896 if ((disp
& 0x8000) != 0)
14898 /* In 16bit mode, address is wrapped around at 64k within
14899 the same segment. Otherwise, a data16 prefix on a jump
14900 instruction means that the pc is masked to 16 bits after
14901 the displacement is added! */
14903 if ((prefixes
& PREFIX_DATA
) == 0)
14904 segment
= ((start_pc
+ (codep
- start_codep
))
14905 & ~((bfd_vma
) 0xffff));
14907 if (address_mode
!= mode_64bit
14908 || (isa64
!= intel64
&& !(rex
& REX_W
)))
14909 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14912 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14915 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14917 print_operand_value (scratchbuf
, 1, disp
);
14918 oappend (scratchbuf
);
14922 OP_SEG (int bytemode
, int sizeflag
)
14924 if (bytemode
== w_mode
)
14925 oappend (names_seg
[modrm
.reg
]);
14927 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14931 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14935 if (sizeflag
& DFLAG
)
14945 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14947 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14949 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14950 oappend (scratchbuf
);
14954 OP_OFF (int bytemode
, int sizeflag
)
14958 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14959 intel_operand_size (bytemode
, sizeflag
);
14962 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14969 if (!active_seg_prefix
)
14971 oappend (names_seg
[ds_reg
- es_reg
]);
14975 print_operand_value (scratchbuf
, 1, off
);
14976 oappend (scratchbuf
);
14980 OP_OFF64 (int bytemode
, int sizeflag
)
14984 if (address_mode
!= mode_64bit
14985 || (prefixes
& PREFIX_ADDR
))
14987 OP_OFF (bytemode
, sizeflag
);
14991 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14992 intel_operand_size (bytemode
, sizeflag
);
14999 if (!active_seg_prefix
)
15001 oappend (names_seg
[ds_reg
- es_reg
]);
15005 print_operand_value (scratchbuf
, 1, off
);
15006 oappend (scratchbuf
);
15010 ptr_reg (int code
, int sizeflag
)
15014 *obufp
++ = open_char
;
15015 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15016 if (address_mode
== mode_64bit
)
15018 if (!(sizeflag
& AFLAG
))
15019 s
= names32
[code
- eAX_reg
];
15021 s
= names64
[code
- eAX_reg
];
15023 else if (sizeflag
& AFLAG
)
15024 s
= names32
[code
- eAX_reg
];
15026 s
= names16
[code
- eAX_reg
];
15028 *obufp
++ = close_char
;
15033 OP_ESreg (int code
, int sizeflag
)
15039 case 0x6d: /* insw/insl */
15040 intel_operand_size (z_mode
, sizeflag
);
15042 case 0xa5: /* movsw/movsl/movsq */
15043 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15044 case 0xab: /* stosw/stosl */
15045 case 0xaf: /* scasw/scasl */
15046 intel_operand_size (v_mode
, sizeflag
);
15049 intel_operand_size (b_mode
, sizeflag
);
15052 oappend_maybe_intel ("%es:");
15053 ptr_reg (code
, sizeflag
);
15057 OP_DSreg (int code
, int sizeflag
)
15063 case 0x6f: /* outsw/outsl */
15064 intel_operand_size (z_mode
, sizeflag
);
15066 case 0xa5: /* movsw/movsl/movsq */
15067 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15068 case 0xad: /* lodsw/lodsl/lodsq */
15069 intel_operand_size (v_mode
, sizeflag
);
15072 intel_operand_size (b_mode
, sizeflag
);
15075 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15076 default segment register DS is printed. */
15077 if (!active_seg_prefix
)
15078 active_seg_prefix
= PREFIX_DS
;
15080 ptr_reg (code
, sizeflag
);
15084 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15092 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15094 all_prefixes
[last_lock_prefix
] = 0;
15095 used_prefixes
|= PREFIX_LOCK
;
15100 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15101 oappend_maybe_intel (scratchbuf
);
15105 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15114 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15116 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15117 oappend (scratchbuf
);
15121 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15123 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15124 oappend_maybe_intel (scratchbuf
);
15128 OP_R (int bytemode
, int sizeflag
)
15130 /* Skip mod/rm byte. */
15133 OP_E_register (bytemode
, sizeflag
);
15137 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15139 int reg
= modrm
.reg
;
15140 const char **names
;
15142 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15143 if (prefixes
& PREFIX_DATA
)
15152 oappend (names
[reg
]);
15156 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15158 int reg
= modrm
.reg
;
15159 const char **names
;
15171 && bytemode
!= xmm_mode
15172 && bytemode
!= xmmq_mode
15173 && bytemode
!= evex_half_bcst_xmmq_mode
15174 && bytemode
!= ymm_mode
15175 && bytemode
!= scalar_mode
)
15177 switch (vex
.length
)
15184 || (bytemode
!= vex_vsib_q_w_dq_mode
15185 && bytemode
!= vex_vsib_q_w_d_mode
))
15197 else if (bytemode
== xmmq_mode
15198 || bytemode
== evex_half_bcst_xmmq_mode
)
15200 switch (vex
.length
)
15213 else if (bytemode
== ymm_mode
)
15217 oappend (names
[reg
]);
15221 OP_EM (int bytemode
, int sizeflag
)
15224 const char **names
;
15226 if (modrm
.mod
!= 3)
15229 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15231 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15232 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15234 OP_E (bytemode
, sizeflag
);
15238 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15241 /* Skip mod/rm byte. */
15244 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15246 if (prefixes
& PREFIX_DATA
)
15255 oappend (names
[reg
]);
15258 /* cvt* are the only instructions in sse2 which have
15259 both SSE and MMX operands and also have 0x66 prefix
15260 in their opcode. 0x66 was originally used to differentiate
15261 between SSE and MMX instruction(operands). So we have to handle the
15262 cvt* separately using OP_EMC and OP_MXC */
15264 OP_EMC (int bytemode
, int sizeflag
)
15266 if (modrm
.mod
!= 3)
15268 if (intel_syntax
&& bytemode
== v_mode
)
15270 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15271 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15273 OP_E (bytemode
, sizeflag
);
15277 /* Skip mod/rm byte. */
15280 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15281 oappend (names_mm
[modrm
.rm
]);
15285 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15287 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15288 oappend (names_mm
[modrm
.reg
]);
15292 OP_EX (int bytemode
, int sizeflag
)
15295 const char **names
;
15297 /* Skip mod/rm byte. */
15301 if (modrm
.mod
!= 3)
15303 OP_E_memory (bytemode
, sizeflag
);
15318 if ((sizeflag
& SUFFIX_ALWAYS
)
15319 && (bytemode
== x_swap_mode
15320 || bytemode
== d_swap_mode
15321 || bytemode
== d_scalar_swap_mode
15322 || bytemode
== q_swap_mode
15323 || bytemode
== q_scalar_swap_mode
))
15327 && bytemode
!= xmm_mode
15328 && bytemode
!= xmmdw_mode
15329 && bytemode
!= xmmqd_mode
15330 && bytemode
!= xmm_mb_mode
15331 && bytemode
!= xmm_mw_mode
15332 && bytemode
!= xmm_md_mode
15333 && bytemode
!= xmm_mq_mode
15334 && bytemode
!= xmmq_mode
15335 && bytemode
!= evex_half_bcst_xmmq_mode
15336 && bytemode
!= ymm_mode
15337 && bytemode
!= d_scalar_mode
15338 && bytemode
!= d_scalar_swap_mode
15339 && bytemode
!= q_scalar_mode
15340 && bytemode
!= q_scalar_swap_mode
15341 && bytemode
!= vex_scalar_w_dq_mode
)
15343 switch (vex
.length
)
15358 else if (bytemode
== xmmq_mode
15359 || bytemode
== evex_half_bcst_xmmq_mode
)
15361 switch (vex
.length
)
15374 else if (bytemode
== ymm_mode
)
15378 oappend (names
[reg
]);
15382 OP_MS (int bytemode
, int sizeflag
)
15384 if (modrm
.mod
== 3)
15385 OP_EM (bytemode
, sizeflag
);
15391 OP_XS (int bytemode
, int sizeflag
)
15393 if (modrm
.mod
== 3)
15394 OP_EX (bytemode
, sizeflag
);
15400 OP_M (int bytemode
, int sizeflag
)
15402 if (modrm
.mod
== 3)
15403 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15406 OP_E (bytemode
, sizeflag
);
15410 OP_0f07 (int bytemode
, int sizeflag
)
15412 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15415 OP_E (bytemode
, sizeflag
);
15418 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15419 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15422 NOP_Fixup1 (int bytemode
, int sizeflag
)
15424 if ((prefixes
& PREFIX_DATA
) != 0
15427 && address_mode
== mode_64bit
))
15428 OP_REG (bytemode
, sizeflag
);
15430 strcpy (obuf
, "nop");
15434 NOP_Fixup2 (int bytemode
, int sizeflag
)
15436 if ((prefixes
& PREFIX_DATA
) != 0
15439 && address_mode
== mode_64bit
))
15440 OP_IMREG (bytemode
, sizeflag
);
15443 static const char *const Suffix3DNow
[] = {
15444 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15445 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15446 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15447 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15448 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15449 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15450 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15451 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15452 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15453 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15454 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15455 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15456 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15457 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15458 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15459 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15460 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15461 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15462 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15463 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15464 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15465 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15466 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15467 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15468 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15469 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15470 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15471 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15472 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15473 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15474 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15475 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15476 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15477 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15478 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15479 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15480 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15481 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15482 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15483 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15484 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15485 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15486 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15487 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15488 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15489 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15490 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15491 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15492 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15493 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15494 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15495 /* CC */ NULL
, NULL
, NULL
, NULL
,
15496 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15497 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15498 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15499 /* DC */ NULL
, NULL
, NULL
, NULL
,
15500 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15501 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15502 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15503 /* EC */ NULL
, NULL
, NULL
, NULL
,
15504 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15505 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15506 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15507 /* FC */ NULL
, NULL
, NULL
, NULL
,
15511 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15513 const char *mnemonic
;
15515 FETCH_DATA (the_info
, codep
+ 1);
15516 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15517 place where an 8-bit immediate would normally go. ie. the last
15518 byte of the instruction. */
15519 obufp
= mnemonicendp
;
15520 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15522 oappend (mnemonic
);
15525 /* Since a variable sized modrm/sib chunk is between the start
15526 of the opcode (0x0f0f) and the opcode suffix, we need to do
15527 all the modrm processing first, and don't know until now that
15528 we have a bad opcode. This necessitates some cleaning up. */
15529 op_out
[0][0] = '\0';
15530 op_out
[1][0] = '\0';
15533 mnemonicendp
= obufp
;
15536 static struct op simd_cmp_op
[] =
15538 { STRING_COMMA_LEN ("eq") },
15539 { STRING_COMMA_LEN ("lt") },
15540 { STRING_COMMA_LEN ("le") },
15541 { STRING_COMMA_LEN ("unord") },
15542 { STRING_COMMA_LEN ("neq") },
15543 { STRING_COMMA_LEN ("nlt") },
15544 { STRING_COMMA_LEN ("nle") },
15545 { STRING_COMMA_LEN ("ord") }
15549 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15551 unsigned int cmp_type
;
15553 FETCH_DATA (the_info
, codep
+ 1);
15554 cmp_type
= *codep
++ & 0xff;
15555 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15558 char *p
= mnemonicendp
- 2;
15562 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15563 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15567 /* We have a reserved extension byte. Output it directly. */
15568 scratchbuf
[0] = '$';
15569 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15570 oappend_maybe_intel (scratchbuf
);
15571 scratchbuf
[0] = '\0';
15576 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15578 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
15581 strcpy (op_out
[0], names32
[0]);
15582 strcpy (op_out
[1], names32
[1]);
15583 if (bytemode
== eBX_reg
)
15584 strcpy (op_out
[2], names32
[3]);
15585 two_source_ops
= 1;
15587 /* Skip mod/rm byte. */
15593 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15594 int sizeflag ATTRIBUTE_UNUSED
)
15596 /* monitor %{e,r,}ax,%ecx,%edx" */
15599 const char **names
= (address_mode
== mode_64bit
15600 ? names64
: names32
);
15602 if (prefixes
& PREFIX_ADDR
)
15604 /* Remove "addr16/addr32". */
15605 all_prefixes
[last_addr_prefix
] = 0;
15606 names
= (address_mode
!= mode_32bit
15607 ? names32
: names16
);
15608 used_prefixes
|= PREFIX_ADDR
;
15610 else if (address_mode
== mode_16bit
)
15612 strcpy (op_out
[0], names
[0]);
15613 strcpy (op_out
[1], names32
[1]);
15614 strcpy (op_out
[2], names32
[2]);
15615 two_source_ops
= 1;
15617 /* Skip mod/rm byte. */
15625 /* Throw away prefixes and 1st. opcode byte. */
15626 codep
= insn_codep
+ 1;
15631 REP_Fixup (int bytemode
, int sizeflag
)
15633 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15635 if (prefixes
& PREFIX_REPZ
)
15636 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15643 OP_IMREG (bytemode
, sizeflag
);
15646 OP_ESreg (bytemode
, sizeflag
);
15649 OP_DSreg (bytemode
, sizeflag
);
15658 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15660 if ( isa64
!= amd64
)
15665 mnemonicendp
= obufp
;
15669 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15673 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15675 if (prefixes
& PREFIX_REPNZ
)
15676 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15679 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15683 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15684 int sizeflag ATTRIBUTE_UNUSED
)
15686 if (active_seg_prefix
== PREFIX_DS
15687 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15689 /* NOTRACK prefix is only valid on indirect branch instructions.
15690 NB: DATA prefix is unsupported for Intel64. */
15691 active_seg_prefix
= 0;
15692 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15696 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15697 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15701 HLE_Fixup1 (int bytemode
, int sizeflag
)
15704 && (prefixes
& PREFIX_LOCK
) != 0)
15706 if (prefixes
& PREFIX_REPZ
)
15707 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15708 if (prefixes
& PREFIX_REPNZ
)
15709 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15712 OP_E (bytemode
, sizeflag
);
15715 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15716 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15720 HLE_Fixup2 (int bytemode
, int sizeflag
)
15722 if (modrm
.mod
!= 3)
15724 if (prefixes
& PREFIX_REPZ
)
15725 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15726 if (prefixes
& PREFIX_REPNZ
)
15727 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15730 OP_E (bytemode
, sizeflag
);
15733 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15734 "xrelease" for memory operand. No check for LOCK prefix. */
15737 HLE_Fixup3 (int bytemode
, int sizeflag
)
15740 && last_repz_prefix
> last_repnz_prefix
15741 && (prefixes
& PREFIX_REPZ
) != 0)
15742 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15744 OP_E (bytemode
, sizeflag
);
15748 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15753 /* Change cmpxchg8b to cmpxchg16b. */
15754 char *p
= mnemonicendp
- 2;
15755 mnemonicendp
= stpcpy (p
, "16b");
15758 else if ((prefixes
& PREFIX_LOCK
) != 0)
15760 if (prefixes
& PREFIX_REPZ
)
15761 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15762 if (prefixes
& PREFIX_REPNZ
)
15763 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15766 OP_M (bytemode
, sizeflag
);
15770 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15772 const char **names
;
15776 switch (vex
.length
)
15790 oappend (names
[reg
]);
15794 CRC32_Fixup (int bytemode
, int sizeflag
)
15796 /* Add proper suffix to "crc32". */
15797 char *p
= mnemonicendp
;
15816 if (sizeflag
& DFLAG
)
15820 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15824 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15831 if (modrm
.mod
== 3)
15835 /* Skip mod/rm byte. */
15840 add
= (rex
& REX_B
) ? 8 : 0;
15841 if (bytemode
== b_mode
)
15845 oappend (names8rex
[modrm
.rm
+ add
]);
15847 oappend (names8
[modrm
.rm
+ add
]);
15853 oappend (names64
[modrm
.rm
+ add
]);
15854 else if ((prefixes
& PREFIX_DATA
))
15855 oappend (names16
[modrm
.rm
+ add
]);
15857 oappend (names32
[modrm
.rm
+ add
]);
15861 OP_E (bytemode
, sizeflag
);
15865 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15867 /* Add proper suffix to "fxsave" and "fxrstor". */
15871 char *p
= mnemonicendp
;
15877 OP_M (bytemode
, sizeflag
);
15881 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15883 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15886 char *p
= mnemonicendp
;
15891 else if (sizeflag
& SUFFIX_ALWAYS
)
15898 OP_EX (bytemode
, sizeflag
);
15901 /* Display the destination register operand for instructions with
15905 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15908 const char **names
;
15916 reg
= vex
.register_specifier
;
15917 vex
.register_specifier
= 0;
15918 if (address_mode
!= mode_64bit
)
15920 else if (vex
.evex
&& !vex
.v
)
15923 if (bytemode
== vex_scalar_mode
)
15925 oappend (names_xmm
[reg
]);
15929 switch (vex
.length
)
15936 case vex_vsib_q_w_dq_mode
:
15937 case vex_vsib_q_w_d_mode
:
15953 names
= names_mask
;
15967 case vex_vsib_q_w_dq_mode
:
15968 case vex_vsib_q_w_d_mode
:
15969 names
= vex
.w
? names_ymm
: names_xmm
;
15978 names
= names_mask
;
15981 /* See PR binutils/20893 for a reproducer. */
15993 oappend (names
[reg
]);
15996 /* Get the VEX immediate byte without moving codep. */
15998 static unsigned char
15999 get_vex_imm8 (int sizeflag
, int opnum
)
16001 int bytes_before_imm
= 0;
16003 if (modrm
.mod
!= 3)
16005 /* There are SIB/displacement bytes. */
16006 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16008 /* 32/64 bit address mode */
16009 int base
= modrm
.rm
;
16011 /* Check SIB byte. */
16014 FETCH_DATA (the_info
, codep
+ 1);
16016 /* When decoding the third source, don't increase
16017 bytes_before_imm as this has already been incremented
16018 by one in OP_E_memory while decoding the second
16021 bytes_before_imm
++;
16024 /* Don't increase bytes_before_imm when decoding the third source,
16025 it has already been incremented by OP_E_memory while decoding
16026 the second source operand. */
16032 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16033 SIB == 5, there is a 4 byte displacement. */
16035 /* No displacement. */
16037 /* Fall through. */
16039 /* 4 byte displacement. */
16040 bytes_before_imm
+= 4;
16043 /* 1 byte displacement. */
16044 bytes_before_imm
++;
16051 /* 16 bit address mode */
16052 /* Don't increase bytes_before_imm when decoding the third source,
16053 it has already been incremented by OP_E_memory while decoding
16054 the second source operand. */
16060 /* When modrm.rm == 6, there is a 2 byte displacement. */
16062 /* No displacement. */
16064 /* Fall through. */
16066 /* 2 byte displacement. */
16067 bytes_before_imm
+= 2;
16070 /* 1 byte displacement: when decoding the third source,
16071 don't increase bytes_before_imm as this has already
16072 been incremented by one in OP_E_memory while decoding
16073 the second source operand. */
16075 bytes_before_imm
++;
16083 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16084 return codep
[bytes_before_imm
];
16088 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16090 const char **names
;
16092 if (reg
== -1 && modrm
.mod
!= 3)
16094 OP_E_memory (bytemode
, sizeflag
);
16106 if (address_mode
!= mode_64bit
)
16110 switch (vex
.length
)
16121 oappend (names
[reg
]);
16125 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16128 static unsigned char vex_imm8
;
16130 if (vex_w_done
== 0)
16134 /* Skip mod/rm byte. */
16138 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16141 reg
= vex_imm8
>> 4;
16143 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16145 else if (vex_w_done
== 1)
16150 reg
= vex_imm8
>> 4;
16152 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16156 /* Output the imm8 directly. */
16157 scratchbuf
[0] = '$';
16158 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16159 oappend_maybe_intel (scratchbuf
);
16160 scratchbuf
[0] = '\0';
16166 OP_Vex_2src (int bytemode
, int sizeflag
)
16168 if (modrm
.mod
== 3)
16170 int reg
= modrm
.rm
;
16174 oappend (names_xmm
[reg
]);
16179 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16181 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16182 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16184 OP_E (bytemode
, sizeflag
);
16189 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16191 if (modrm
.mod
== 3)
16193 /* Skip mod/rm byte. */
16200 unsigned int reg
= vex
.register_specifier
;
16201 vex
.register_specifier
= 0;
16203 if (address_mode
!= mode_64bit
)
16205 oappend (names_xmm
[reg
]);
16208 OP_Vex_2src (bytemode
, sizeflag
);
16212 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16215 OP_Vex_2src (bytemode
, sizeflag
);
16218 unsigned int reg
= vex
.register_specifier
;
16219 vex
.register_specifier
= 0;
16221 if (address_mode
!= mode_64bit
)
16223 oappend (names_xmm
[reg
]);
16228 OP_EX_VexW (int bytemode
, int sizeflag
)
16234 /* Skip mod/rm byte. */
16239 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16244 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16247 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16255 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16258 const char **names
;
16260 FETCH_DATA (the_info
, codep
+ 1);
16263 if (bytemode
!= x_mode
)
16267 if (address_mode
!= mode_64bit
)
16270 switch (vex
.length
)
16281 oappend (names
[reg
]);
16285 OP_XMM_VexW (int bytemode
, int sizeflag
)
16287 /* Turn off the REX.W bit since it is used for swapping operands
16290 OP_XMM (bytemode
, sizeflag
);
16294 OP_EX_Vex (int bytemode
, int sizeflag
)
16296 if (modrm
.mod
!= 3)
16298 OP_EX (bytemode
, sizeflag
);
16302 OP_XMM_Vex (int bytemode
, int sizeflag
)
16304 if (modrm
.mod
!= 3)
16306 OP_XMM (bytemode
, sizeflag
);
16309 static struct op vex_cmp_op
[] =
16311 { STRING_COMMA_LEN ("eq") },
16312 { STRING_COMMA_LEN ("lt") },
16313 { STRING_COMMA_LEN ("le") },
16314 { STRING_COMMA_LEN ("unord") },
16315 { STRING_COMMA_LEN ("neq") },
16316 { STRING_COMMA_LEN ("nlt") },
16317 { STRING_COMMA_LEN ("nle") },
16318 { STRING_COMMA_LEN ("ord") },
16319 { STRING_COMMA_LEN ("eq_uq") },
16320 { STRING_COMMA_LEN ("nge") },
16321 { STRING_COMMA_LEN ("ngt") },
16322 { STRING_COMMA_LEN ("false") },
16323 { STRING_COMMA_LEN ("neq_oq") },
16324 { STRING_COMMA_LEN ("ge") },
16325 { STRING_COMMA_LEN ("gt") },
16326 { STRING_COMMA_LEN ("true") },
16327 { STRING_COMMA_LEN ("eq_os") },
16328 { STRING_COMMA_LEN ("lt_oq") },
16329 { STRING_COMMA_LEN ("le_oq") },
16330 { STRING_COMMA_LEN ("unord_s") },
16331 { STRING_COMMA_LEN ("neq_us") },
16332 { STRING_COMMA_LEN ("nlt_uq") },
16333 { STRING_COMMA_LEN ("nle_uq") },
16334 { STRING_COMMA_LEN ("ord_s") },
16335 { STRING_COMMA_LEN ("eq_us") },
16336 { STRING_COMMA_LEN ("nge_uq") },
16337 { STRING_COMMA_LEN ("ngt_uq") },
16338 { STRING_COMMA_LEN ("false_os") },
16339 { STRING_COMMA_LEN ("neq_os") },
16340 { STRING_COMMA_LEN ("ge_oq") },
16341 { STRING_COMMA_LEN ("gt_oq") },
16342 { STRING_COMMA_LEN ("true_us") },
16346 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16348 unsigned int cmp_type
;
16350 FETCH_DATA (the_info
, codep
+ 1);
16351 cmp_type
= *codep
++ & 0xff;
16352 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16355 char *p
= mnemonicendp
- 2;
16359 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16360 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16364 /* We have a reserved extension byte. Output it directly. */
16365 scratchbuf
[0] = '$';
16366 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16367 oappend_maybe_intel (scratchbuf
);
16368 scratchbuf
[0] = '\0';
16373 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16374 int sizeflag ATTRIBUTE_UNUSED
)
16376 unsigned int cmp_type
;
16381 FETCH_DATA (the_info
, codep
+ 1);
16382 cmp_type
= *codep
++ & 0xff;
16383 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16384 If it's the case, print suffix, otherwise - print the immediate. */
16385 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16390 char *p
= mnemonicendp
- 2;
16392 /* vpcmp* can have both one- and two-lettered suffix. */
16406 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16407 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16411 /* We have a reserved extension byte. Output it directly. */
16412 scratchbuf
[0] = '$';
16413 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16414 oappend_maybe_intel (scratchbuf
);
16415 scratchbuf
[0] = '\0';
16419 static const struct op xop_cmp_op
[] =
16421 { STRING_COMMA_LEN ("lt") },
16422 { STRING_COMMA_LEN ("le") },
16423 { STRING_COMMA_LEN ("gt") },
16424 { STRING_COMMA_LEN ("ge") },
16425 { STRING_COMMA_LEN ("eq") },
16426 { STRING_COMMA_LEN ("neq") },
16427 { STRING_COMMA_LEN ("false") },
16428 { STRING_COMMA_LEN ("true") }
16432 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16433 int sizeflag ATTRIBUTE_UNUSED
)
16435 unsigned int cmp_type
;
16437 FETCH_DATA (the_info
, codep
+ 1);
16438 cmp_type
= *codep
++ & 0xff;
16439 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16442 char *p
= mnemonicendp
- 2;
16444 /* vpcom* can have both one- and two-lettered suffix. */
16458 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16459 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16463 /* We have a reserved extension byte. Output it directly. */
16464 scratchbuf
[0] = '$';
16465 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16466 oappend_maybe_intel (scratchbuf
);
16467 scratchbuf
[0] = '\0';
16471 static const struct op pclmul_op
[] =
16473 { STRING_COMMA_LEN ("lql") },
16474 { STRING_COMMA_LEN ("hql") },
16475 { STRING_COMMA_LEN ("lqh") },
16476 { STRING_COMMA_LEN ("hqh") }
16480 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16481 int sizeflag ATTRIBUTE_UNUSED
)
16483 unsigned int pclmul_type
;
16485 FETCH_DATA (the_info
, codep
+ 1);
16486 pclmul_type
= *codep
++ & 0xff;
16487 switch (pclmul_type
)
16498 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16501 char *p
= mnemonicendp
- 3;
16506 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16507 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16511 /* We have a reserved extension byte. Output it directly. */
16512 scratchbuf
[0] = '$';
16513 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16514 oappend_maybe_intel (scratchbuf
);
16515 scratchbuf
[0] = '\0';
16520 MOVBE_Fixup (int bytemode
, int sizeflag
)
16522 /* Add proper suffix to "movbe". */
16523 char *p
= mnemonicendp
;
16532 if (sizeflag
& SUFFIX_ALWAYS
)
16538 if (sizeflag
& DFLAG
)
16542 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16547 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16554 OP_M (bytemode
, sizeflag
);
16558 MOVSXD_Fixup (int bytemode
, int sizeflag
)
16560 /* Add proper suffix to "movsxd". */
16561 char *p
= mnemonicendp
;
16586 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16593 OP_E (bytemode
, sizeflag
);
16597 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16600 const char **names
;
16602 /* Skip mod/rm byte. */
16616 oappend (names
[reg
]);
16620 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16622 const char **names
;
16623 unsigned int reg
= vex
.register_specifier
;
16624 vex
.register_specifier
= 0;
16631 if (address_mode
!= mode_64bit
)
16633 oappend (names
[reg
]);
16637 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16640 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16644 if ((rex
& REX_R
) != 0 || !vex
.r
)
16650 oappend (names_mask
[modrm
.reg
]);
16654 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16657 || (bytemode
!= evex_rounding_mode
16658 && bytemode
!= evex_rounding_64_mode
16659 && bytemode
!= evex_sae_mode
))
16661 if (modrm
.mod
== 3 && vex
.b
)
16664 case evex_rounding_64_mode
:
16665 if (address_mode
!= mode_64bit
)
16670 /* Fall through. */
16671 case evex_rounding_mode
:
16672 oappend (names_rounding
[vex
.ll
]);
16674 case evex_sae_mode
: