opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2019 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void OP_Mwaitx (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Edqa { OP_E, dqa_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iq { OP_I, q_mode }
 296 #define Iv64 { OP_I64, v_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdScalar { OP_EX, d_scalar_mode }
 388 #define EXdS { OP_EX, d_swap_mode }
 389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 405 #define EXxmmdw { OP_EX, xmmdw_mode }
 406 #define EXxmmqd { OP_EX, xmmqd_mode }
 407 #define EXymmq { OP_EX, ymmq_mode }
 408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 412 #define MS { OP_MS, v_mode }
 413 #define XS { OP_XS, v_mode }
 414 #define EMCq { OP_EMC, q_mode }
 415 #define MXC { OP_MXC, 0 }
 416 #define OPSUF { OP_3DNowSuffix, 0 }
 417 #define CMP { CMP_Fixup, 0 }
 418 #define XMM0 { XMM_Fixup, 0 }
 419 #define FXSAVE { FXSAVE_Fixup, 0 }
 420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 422
 423 #define Vex { OP_VEX, vex_mode }
 424 #define VexScalar { OP_VEX, vex_scalar_mode }
 425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 426 #define Vex128 { OP_VEX, vex128_mode }
 427 #define Vex256 { OP_VEX, vex256_mode }
 428 #define VexGdq { OP_VEX, dq_mode }
 429 #define EXdVex { OP_EX_Vex, d_mode }
 430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 432 #define EXqVex { OP_EX_Vex, q_mode }
 433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 435 #define EXVexW { OP_EX_VexW, x_mode }
 436 #define EXdVexW { OP_EX_VexW, d_mode }
 437 #define EXqVexW { OP_EX_VexW, q_mode }
 438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 439 #define XMVex { OP_XMM_Vex, 0 }
 440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 441 #define XMVexW { OP_XMM_VexW, 0 }
 442 #define XMVexI4 { OP_REG_VexI4, x_mode }
 443 #define PCLMUL { PCLMUL_Fixup, 0 }
 444 #define VCMP { VCMP_Fixup, 0 }
 445 #define VPCMP { VPCMP_Fixup, 0 }
 446 #define VPCOM { VPCOM_Fixup, 0 }
 447
 448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 451
 452 #define XMask { OP_Mask, mask_mode }
 453 #define MaskG { OP_G, mask_mode }
 454 #define MaskE { OP_E, mask_mode }
 455 #define MaskBDE { OP_E, mask_bd_mode }
 456 #define MaskR { OP_R, mask_mode }
 457 #define MaskVex { OP_VEX, mask_mode }
 458
 459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 463
 464 /* Used handle "rep" prefix for string instructions.  */
 465 #define Xbr { REP_Fixup, eSI_reg }
 466 #define Xvr { REP_Fixup, eSI_reg }
 467 #define Ybr { REP_Fixup, eDI_reg }
 468 #define Yvr { REP_Fixup, eDI_reg }
 469 #define Yzr { REP_Fixup, eDI_reg }
 470 #define indirDXr { REP_Fixup, indir_dx_reg }
 471 #define ALr { REP_Fixup, al_reg }
 472 #define eAXr { REP_Fixup, eAX_reg }
 473
 474 /* Used handle HLE prefix for lockable instructions.  */
 475 #define Ebh1 { HLE_Fixup1, b_mode }
 476 #define Evh1 { HLE_Fixup1, v_mode }
 477 #define Ebh2 { HLE_Fixup2, b_mode }
 478 #define Evh2 { HLE_Fixup2, v_mode }
 479 #define Ebh3 { HLE_Fixup3, b_mode }
 480 #define Evh3 { HLE_Fixup3, v_mode }
 481
 482 #define BND { BND_Fixup, 0 }
 483 #define NOTRACK { NOTRACK_Fixup, 0 }
 484
 485 #define cond_jump_flag { NULL, cond_jump_mode }
 486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 487
 488 /* bits in sizeflag */
 489 #define SUFFIX_ALWAYS 4
 490 #define AFLAG 2
 491 #define DFLAG 1
 492
 493 enum
 494 {
 495   /* byte operand */
 496   b_mode = 1,
 497   /* byte operand with operand swapped */
 498   b_swap_mode,
 499   /* byte operand, sign extend like 'T' suffix */
 500   b_T_mode,
 501   /* operand size depends on prefixes */
 502   v_mode,
 503   /* operand size depends on prefixes with operand swapped */
 504   v_swap_mode,
 505   /* operand size depends on address prefix */
 506   va_mode,
 507   /* word operand */
 508   w_mode,
 509   /* double word operand  */
 510   d_mode,
 511   /* double word operand with operand swapped */
 512   d_swap_mode,
 513   /* quad word operand */
 514   q_mode,
 515   /* quad word operand with operand swapped */
 516   q_swap_mode,
 517   /* ten-byte operand */
 518   t_mode,
 519   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 520      broadcast enabled.  */
 521   x_mode,
 522   /* Similar to x_mode, but with different EVEX mem shifts.  */
 523   evex_x_gscat_mode,
 524   /* Similar to x_mode, but with disabled broadcast.  */
 525   evex_x_nobcst_mode,
 526   /* Similar to x_mode, but with operands swapped and disabled broadcast
 527      in EVEX.  */
 528   x_swap_mode,
 529   /* 16-byte XMM operand */
 530   xmm_mode,
 531   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 532      memory operand (depending on vector length).  Broadcast isn't
 533      allowed.  */
 534   xmmq_mode,
 535   /* Same as xmmq_mode, but broadcast is allowed.  */
 536   evex_half_bcst_xmmq_mode,
 537   /* XMM register or byte memory operand */
 538   xmm_mb_mode,
 539   /* XMM register or word memory operand */
 540   xmm_mw_mode,
 541   /* XMM register or double word memory operand */
 542   xmm_md_mode,
 543   /* XMM register or quad word memory operand */
 544   xmm_mq_mode,
 545   /* XMM register or double/quad word memory operand, depending on
 546      VEX.W.  */
 547   xmm_mdq_mode,
 548   /* 16-byte XMM, word, double word or quad word operand.  */
 549   xmmdw_mode,
 550   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 551   xmmqd_mode,
 552   /* 32-byte YMM operand */
 553   ymm_mode,
 554   /* quad word, ymmword or zmmword memory operand.  */
 555   ymmq_mode,
 556   /* 32-byte YMM or 16-byte word operand */
 557   ymmxmm_mode,
 558   /* d_mode in 32bit, q_mode in 64bit mode.  */
 559   m_mode,
 560   /* pair of v_mode operands */
 561   a_mode,
 562   cond_jump_mode,
 563   loop_jcxz_mode,
 564   v_bnd_mode,
 565   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 566   v_bndmk_mode,
 567   /* operand size depends on REX prefixes.  */
 568   dq_mode,
 569   /* registers like dq_mode, memory like w_mode.  */
 570   dqw_mode,
 571   /* bounds operand */
 572   bnd_mode,
 573   /* bounds operand with operand swapped */
 574   bnd_swap_mode,
 575   /* 4- or 6-byte pointer operand */
 576   f_mode,
 577   const_1_mode,
 578   /* v_mode for indirect branch opcodes.  */
 579   indir_v_mode,
 580   /* v_mode for stack-related opcodes.  */
 581   stack_v_mode,
 582   /* non-quad operand size depends on prefixes */
 583   z_mode,
 584   /* 16-byte operand */
 585   o_mode,
 586   /* registers like dq_mode, memory like b_mode.  */
 587   dqb_mode,
 588   /* registers like d_mode, memory like b_mode.  */
 589   db_mode,
 590   /* registers like d_mode, memory like w_mode.  */
 591   dw_mode,
 592   /* registers like dq_mode, memory like d_mode.  */
 593   dqd_mode,
 594   /* operand size depends on the W bit as well as address mode.  */
 595   dqa_mode,
 596   /* normal vex mode */
 597   vex_mode,
 598   /* 128bit vex mode */
 599   vex128_mode,
 600   /* 256bit vex mode */
 601   vex256_mode,
 602   /* operand size depends on the VEX.W bit.  */
 603   vex_w_dq_mode,
 604
 605   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 606   vex_vsib_d_w_dq_mode,
 607   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 608   vex_vsib_d_w_d_mode,
 609   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 610   vex_vsib_q_w_dq_mode,
 611   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 612   vex_vsib_q_w_d_mode,
 613
 614   /* scalar, ignore vector length.  */
 615   scalar_mode,
 616   /* like b_mode, ignore vector length.  */
 617   b_scalar_mode,
 618   /* like w_mode, ignore vector length.  */
 619   w_scalar_mode,
 620   /* like d_mode, ignore vector length.  */
 621   d_scalar_mode,
 622   /* like d_swap_mode, ignore vector length.  */
 623   d_scalar_swap_mode,
 624   /* like q_mode, ignore vector length.  */
 625   q_scalar_mode,
 626   /* like q_swap_mode, ignore vector length.  */
 627   q_scalar_swap_mode,
 628   /* like vex_mode, ignore vector length.  */
 629   vex_scalar_mode,
 630   /* like vex_w_dq_mode, ignore vector length.  */
 631   vex_scalar_w_dq_mode,
 632
 633   /* Static rounding.  */
 634   evex_rounding_mode,
 635   /* Static rounding, 64-bit mode only.  */
 636   evex_rounding_64_mode,
 637   /* Supress all exceptions.  */
 638   evex_sae_mode,
 639
 640   /* Mask register operand.  */
 641   mask_mode,
 642   /* Mask register operand.  */
 643   mask_bd_mode,
 644
 645   es_reg,
 646   cs_reg,
 647   ss_reg,
 648   ds_reg,
 649   fs_reg,
 650   gs_reg,
 651
 652   eAX_reg,
 653   eCX_reg,
 654   eDX_reg,
 655   eBX_reg,
 656   eSP_reg,
 657   eBP_reg,
 658   eSI_reg,
 659   eDI_reg,
 660
 661   al_reg,
 662   cl_reg,
 663   dl_reg,
 664   bl_reg,
 665   ah_reg,
 666   ch_reg,
 667   dh_reg,
 668   bh_reg,
 669
 670   ax_reg,
 671   cx_reg,
 672   dx_reg,
 673   bx_reg,
 674   sp_reg,
 675   bp_reg,
 676   si_reg,
 677   di_reg,
 678
 679   rAX_reg,
 680   rCX_reg,
 681   rDX_reg,
 682   rBX_reg,
 683   rSP_reg,
 684   rBP_reg,
 685   rSI_reg,
 686   rDI_reg,
 687
 688   z_mode_ax_reg,
 689   indir_dx_reg
 690 };
 691
 692 enum
 693 {
 694   FLOATCODE = 1,
 695   USE_REG_TABLE,
 696   USE_MOD_TABLE,
 697   USE_RM_TABLE,
 698   USE_PREFIX_TABLE,
 699   USE_X86_64_TABLE,
 700   USE_3BYTE_TABLE,
 701   USE_XOP_8F_TABLE,
 702   USE_VEX_C4_TABLE,
 703   USE_VEX_C5_TABLE,
 704   USE_VEX_LEN_TABLE,
 705   USE_VEX_W_TABLE,
 706   USE_EVEX_TABLE,
 707   USE_EVEX_LEN_TABLE
 708 };
 709
 710 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 711
 712 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 713 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 714 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 715 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 716 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 717 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 718 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 719 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 720 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 721 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 722 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 723 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 724 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 725 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 726 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 727 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 728
 729 enum
 730 {
 731   REG_80 = 0,
 732   REG_81,
 733   REG_83,
 734   REG_8F,
 735   REG_C0,
 736   REG_C1,
 737   REG_C6,
 738   REG_C7,
 739   REG_D0,
 740   REG_D1,
 741   REG_D2,
 742   REG_D3,
 743   REG_F6,
 744   REG_F7,
 745   REG_FE,
 746   REG_FF,
 747   REG_0F00,
 748   REG_0F01,
 749   REG_0F0D,
 750   REG_0F18,
 751   REG_0F1C_MOD_0,
 752   REG_0F1E_MOD_3,
 753   REG_0F71,
 754   REG_0F72,
 755   REG_0F73,
 756   REG_0FA6,
 757   REG_0FA7,
 758   REG_0FAE,
 759   REG_0FBA,
 760   REG_0FC7,
 761   REG_VEX_0F71,
 762   REG_VEX_0F72,
 763   REG_VEX_0F73,
 764   REG_VEX_0FAE,
 765   REG_VEX_0F38F3,
 766   REG_XOP_LWPCB,
 767   REG_XOP_LWP,
 768   REG_XOP_TBM_01,
 769   REG_XOP_TBM_02,
 770
 771   REG_EVEX_0F71,
 772   REG_EVEX_0F72,
 773   REG_EVEX_0F73,
 774   REG_EVEX_0F38C6,
 775   REG_EVEX_0F38C7
 776 };
 777
 778 enum
 779 {
 780   MOD_8D = 0,
 781   MOD_C6_REG_7,
 782   MOD_C7_REG_7,
 783   MOD_FF_REG_3,
 784   MOD_FF_REG_5,
 785   MOD_0F01_REG_0,
 786   MOD_0F01_REG_1,
 787   MOD_0F01_REG_2,
 788   MOD_0F01_REG_3,
 789   MOD_0F01_REG_5,
 790   MOD_0F01_REG_7,
 791   MOD_0F12_PREFIX_0,
 792   MOD_0F13,
 793   MOD_0F16_PREFIX_0,
 794   MOD_0F17,
 795   MOD_0F18_REG_0,
 796   MOD_0F18_REG_1,
 797   MOD_0F18_REG_2,
 798   MOD_0F18_REG_3,
 799   MOD_0F18_REG_4,
 800   MOD_0F18_REG_5,
 801   MOD_0F18_REG_6,
 802   MOD_0F18_REG_7,
 803   MOD_0F1A_PREFIX_0,
 804   MOD_0F1B_PREFIX_0,
 805   MOD_0F1B_PREFIX_1,
 806   MOD_0F1C_PREFIX_0,
 807   MOD_0F1E_PREFIX_1,
 808   MOD_0F24,
 809   MOD_0F26,
 810   MOD_0F2B_PREFIX_0,
 811   MOD_0F2B_PREFIX_1,
 812   MOD_0F2B_PREFIX_2,
 813   MOD_0F2B_PREFIX_3,
 814   MOD_0F51,
 815   MOD_0F71_REG_2,
 816   MOD_0F71_REG_4,
 817   MOD_0F71_REG_6,
 818   MOD_0F72_REG_2,
 819   MOD_0F72_REG_4,
 820   MOD_0F72_REG_6,
 821   MOD_0F73_REG_2,
 822   MOD_0F73_REG_3,
 823   MOD_0F73_REG_6,
 824   MOD_0F73_REG_7,
 825   MOD_0FAE_REG_0,
 826   MOD_0FAE_REG_1,
 827   MOD_0FAE_REG_2,
 828   MOD_0FAE_REG_3,
 829   MOD_0FAE_REG_4,
 830   MOD_0FAE_REG_5,
 831   MOD_0FAE_REG_6,
 832   MOD_0FAE_REG_7,
 833   MOD_0FB2,
 834   MOD_0FB4,
 835   MOD_0FB5,
 836   MOD_0FC3,
 837   MOD_0FC7_REG_3,
 838   MOD_0FC7_REG_4,
 839   MOD_0FC7_REG_5,
 840   MOD_0FC7_REG_6,
 841   MOD_0FC7_REG_7,
 842   MOD_0FD7,
 843   MOD_0FE7_PREFIX_2,
 844   MOD_0FF0_PREFIX_3,
 845   MOD_0F382A_PREFIX_2,
 846   MOD_0F38F5_PREFIX_2,
 847   MOD_0F38F6_PREFIX_0,
 848   MOD_0F38F8_PREFIX_1,
 849   MOD_0F38F8_PREFIX_2,
 850   MOD_0F38F8_PREFIX_3,
 851   MOD_0F38F9_PREFIX_0,
 852   MOD_62_32BIT,
 853   MOD_C4_32BIT,
 854   MOD_C5_32BIT,
 855   MOD_VEX_0F12_PREFIX_0,
 856   MOD_VEX_0F13,
 857   MOD_VEX_0F16_PREFIX_0,
 858   MOD_VEX_0F17,
 859   MOD_VEX_0F2B,
 860   MOD_VEX_W_0_0F41_P_0_LEN_1,
 861   MOD_VEX_W_1_0F41_P_0_LEN_1,
 862   MOD_VEX_W_0_0F41_P_2_LEN_1,
 863   MOD_VEX_W_1_0F41_P_2_LEN_1,
 864   MOD_VEX_W_0_0F42_P_0_LEN_1,
 865   MOD_VEX_W_1_0F42_P_0_LEN_1,
 866   MOD_VEX_W_0_0F42_P_2_LEN_1,
 867   MOD_VEX_W_1_0F42_P_2_LEN_1,
 868   MOD_VEX_W_0_0F44_P_0_LEN_1,
 869   MOD_VEX_W_1_0F44_P_0_LEN_1,
 870   MOD_VEX_W_0_0F44_P_2_LEN_1,
 871   MOD_VEX_W_1_0F44_P_2_LEN_1,
 872   MOD_VEX_W_0_0F45_P_0_LEN_1,
 873   MOD_VEX_W_1_0F45_P_0_LEN_1,
 874   MOD_VEX_W_0_0F45_P_2_LEN_1,
 875   MOD_VEX_W_1_0F45_P_2_LEN_1,
 876   MOD_VEX_W_0_0F46_P_0_LEN_1,
 877   MOD_VEX_W_1_0F46_P_0_LEN_1,
 878   MOD_VEX_W_0_0F46_P_2_LEN_1,
 879   MOD_VEX_W_1_0F46_P_2_LEN_1,
 880   MOD_VEX_W_0_0F47_P_0_LEN_1,
 881   MOD_VEX_W_1_0F47_P_0_LEN_1,
 882   MOD_VEX_W_0_0F47_P_2_LEN_1,
 883   MOD_VEX_W_1_0F47_P_2_LEN_1,
 884   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 885   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 886   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 887   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 888   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 889   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 890   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 891   MOD_VEX_0F50,
 892   MOD_VEX_0F71_REG_2,
 893   MOD_VEX_0F71_REG_4,
 894   MOD_VEX_0F71_REG_6,
 895   MOD_VEX_0F72_REG_2,
 896   MOD_VEX_0F72_REG_4,
 897   MOD_VEX_0F72_REG_6,
 898   MOD_VEX_0F73_REG_2,
 899   MOD_VEX_0F73_REG_3,
 900   MOD_VEX_0F73_REG_6,
 901   MOD_VEX_0F73_REG_7,
 902   MOD_VEX_W_0_0F91_P_0_LEN_0,
 903   MOD_VEX_W_1_0F91_P_0_LEN_0,
 904   MOD_VEX_W_0_0F91_P_2_LEN_0,
 905   MOD_VEX_W_1_0F91_P_2_LEN_0,
 906   MOD_VEX_W_0_0F92_P_0_LEN_0,
 907   MOD_VEX_W_0_0F92_P_2_LEN_0,
 908   MOD_VEX_0F92_P_3_LEN_0,
 909   MOD_VEX_W_0_0F93_P_0_LEN_0,
 910   MOD_VEX_W_0_0F93_P_2_LEN_0,
 911   MOD_VEX_0F93_P_3_LEN_0,
 912   MOD_VEX_W_0_0F98_P_0_LEN_0,
 913   MOD_VEX_W_1_0F98_P_0_LEN_0,
 914   MOD_VEX_W_0_0F98_P_2_LEN_0,
 915   MOD_VEX_W_1_0F98_P_2_LEN_0,
 916   MOD_VEX_W_0_0F99_P_0_LEN_0,
 917   MOD_VEX_W_1_0F99_P_0_LEN_0,
 918   MOD_VEX_W_0_0F99_P_2_LEN_0,
 919   MOD_VEX_W_1_0F99_P_2_LEN_0,
 920   MOD_VEX_0FAE_REG_2,
 921   MOD_VEX_0FAE_REG_3,
 922   MOD_VEX_0FD7_PREFIX_2,
 923   MOD_VEX_0FE7_PREFIX_2,
 924   MOD_VEX_0FF0_PREFIX_3,
 925   MOD_VEX_0F381A_PREFIX_2,
 926   MOD_VEX_0F382A_PREFIX_2,
 927   MOD_VEX_0F382C_PREFIX_2,
 928   MOD_VEX_0F382D_PREFIX_2,
 929   MOD_VEX_0F382E_PREFIX_2,
 930   MOD_VEX_0F382F_PREFIX_2,
 931   MOD_VEX_0F385A_PREFIX_2,
 932   MOD_VEX_0F388C_PREFIX_2,
 933   MOD_VEX_0F388E_PREFIX_2,
 934   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 935   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 936   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 937   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 938   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 939   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 940   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 941   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 942
 943   MOD_EVEX_0F10_PREFIX_1,
 944   MOD_EVEX_0F10_PREFIX_3,
 945   MOD_EVEX_0F11_PREFIX_1,
 946   MOD_EVEX_0F11_PREFIX_3,
 947   MOD_EVEX_0F12_PREFIX_0,
 948   MOD_EVEX_0F16_PREFIX_0,
 949   MOD_EVEX_0F38C6_REG_1,
 950   MOD_EVEX_0F38C6_REG_2,
 951   MOD_EVEX_0F38C6_REG_5,
 952   MOD_EVEX_0F38C6_REG_6,
 953   MOD_EVEX_0F38C7_REG_1,
 954   MOD_EVEX_0F38C7_REG_2,
 955   MOD_EVEX_0F38C7_REG_5,
 956   MOD_EVEX_0F38C7_REG_6
 957 };
 958
 959 enum
 960 {
 961   RM_C6_REG_7 = 0,
 962   RM_C7_REG_7,
 963   RM_0F01_REG_0,
 964   RM_0F01_REG_1,
 965   RM_0F01_REG_2,
 966   RM_0F01_REG_3,
 967   RM_0F01_REG_5,
 968   RM_0F01_REG_7,
 969   RM_0F1E_MOD_3_REG_7,
 970   RM_0FAE_REG_6,
 971   RM_0FAE_REG_7
 972 };
 973
 974 enum
 975 {
 976   PREFIX_90 = 0,
 977   PREFIX_MOD_0_0F01_REG_5,
 978   PREFIX_MOD_3_0F01_REG_5_RM_0,
 979   PREFIX_MOD_3_0F01_REG_5_RM_2,
 980   PREFIX_0F09,
 981   PREFIX_0F10,
 982   PREFIX_0F11,
 983   PREFIX_0F12,
 984   PREFIX_0F16,
 985   PREFIX_0F1A,
 986   PREFIX_0F1B,
 987   PREFIX_0F1C,
 988   PREFIX_0F1E,
 989   PREFIX_0F2A,
 990   PREFIX_0F2B,
 991   PREFIX_0F2C,
 992   PREFIX_0F2D,
 993   PREFIX_0F2E,
 994   PREFIX_0F2F,
 995   PREFIX_0F51,
 996   PREFIX_0F52,
 997   PREFIX_0F53,
 998   PREFIX_0F58,
 999   PREFIX_0F59,
1000   PREFIX_0F5A,
1001   PREFIX_0F5B,
1002   PREFIX_0F5C,
1003   PREFIX_0F5D,
1004   PREFIX_0F5E,
1005   PREFIX_0F5F,
1006   PREFIX_0F60,
1007   PREFIX_0F61,
1008   PREFIX_0F62,
1009   PREFIX_0F6C,
1010   PREFIX_0F6D,
1011   PREFIX_0F6F,
1012   PREFIX_0F70,
1013   PREFIX_0F73_REG_3,
1014   PREFIX_0F73_REG_7,
1015   PREFIX_0F78,
1016   PREFIX_0F79,
1017   PREFIX_0F7C,
1018   PREFIX_0F7D,
1019   PREFIX_0F7E,
1020   PREFIX_0F7F,
1021   PREFIX_0FAE_REG_0,
1022   PREFIX_0FAE_REG_1,
1023   PREFIX_0FAE_REG_2,
1024   PREFIX_0FAE_REG_3,
1025   PREFIX_MOD_0_0FAE_REG_4,
1026   PREFIX_MOD_3_0FAE_REG_4,
1027   PREFIX_MOD_0_0FAE_REG_5,
1028   PREFIX_MOD_3_0FAE_REG_5,
1029   PREFIX_MOD_0_0FAE_REG_6,
1030   PREFIX_MOD_1_0FAE_REG_6,
1031   PREFIX_0FAE_REG_7,
1032   PREFIX_0FB8,
1033   PREFIX_0FBC,
1034   PREFIX_0FBD,
1035   PREFIX_0FC2,
1036   PREFIX_MOD_0_0FC3,
1037   PREFIX_MOD_0_0FC7_REG_6,
1038   PREFIX_MOD_3_0FC7_REG_6,
1039   PREFIX_MOD_3_0FC7_REG_7,
1040   PREFIX_0FD0,
1041   PREFIX_0FD6,
1042   PREFIX_0FE6,
1043   PREFIX_0FE7,
1044   PREFIX_0FF0,
1045   PREFIX_0FF7,
1046   PREFIX_0F3810,
1047   PREFIX_0F3814,
1048   PREFIX_0F3815,
1049   PREFIX_0F3817,
1050   PREFIX_0F3820,
1051   PREFIX_0F3821,
1052   PREFIX_0F3822,
1053   PREFIX_0F3823,
1054   PREFIX_0F3824,
1055   PREFIX_0F3825,
1056   PREFIX_0F3828,
1057   PREFIX_0F3829,
1058   PREFIX_0F382A,
1059   PREFIX_0F382B,
1060   PREFIX_0F3830,
1061   PREFIX_0F3831,
1062   PREFIX_0F3832,
1063   PREFIX_0F3833,
1064   PREFIX_0F3834,
1065   PREFIX_0F3835,
1066   PREFIX_0F3837,
1067   PREFIX_0F3838,
1068   PREFIX_0F3839,
1069   PREFIX_0F383A,
1070   PREFIX_0F383B,
1071   PREFIX_0F383C,
1072   PREFIX_0F383D,
1073   PREFIX_0F383E,
1074   PREFIX_0F383F,
1075   PREFIX_0F3840,
1076   PREFIX_0F3841,
1077   PREFIX_0F3880,
1078   PREFIX_0F3881,
1079   PREFIX_0F3882,
1080   PREFIX_0F38C8,
1081   PREFIX_0F38C9,
1082   PREFIX_0F38CA,
1083   PREFIX_0F38CB,
1084   PREFIX_0F38CC,
1085   PREFIX_0F38CD,
1086   PREFIX_0F38CF,
1087   PREFIX_0F38DB,
1088   PREFIX_0F38DC,
1089   PREFIX_0F38DD,
1090   PREFIX_0F38DE,
1091   PREFIX_0F38DF,
1092   PREFIX_0F38F0,
1093   PREFIX_0F38F1,
1094   PREFIX_0F38F5,
1095   PREFIX_0F38F6,
1096   PREFIX_0F38F8,
1097   PREFIX_0F38F9,
1098   PREFIX_0F3A08,
1099   PREFIX_0F3A09,
1100   PREFIX_0F3A0A,
1101   PREFIX_0F3A0B,
1102   PREFIX_0F3A0C,
1103   PREFIX_0F3A0D,
1104   PREFIX_0F3A0E,
1105   PREFIX_0F3A14,
1106   PREFIX_0F3A15,
1107   PREFIX_0F3A16,
1108   PREFIX_0F3A17,
1109   PREFIX_0F3A20,
1110   PREFIX_0F3A21,
1111   PREFIX_0F3A22,
1112   PREFIX_0F3A40,
1113   PREFIX_0F3A41,
1114   PREFIX_0F3A42,
1115   PREFIX_0F3A44,
1116   PREFIX_0F3A60,
1117   PREFIX_0F3A61,
1118   PREFIX_0F3A62,
1119   PREFIX_0F3A63,
1120   PREFIX_0F3ACC,
1121   PREFIX_0F3ACE,
1122   PREFIX_0F3ACF,
1123   PREFIX_0F3ADF,
1124   PREFIX_VEX_0F10,
1125   PREFIX_VEX_0F11,
1126   PREFIX_VEX_0F12,
1127   PREFIX_VEX_0F16,
1128   PREFIX_VEX_0F2A,
1129   PREFIX_VEX_0F2C,
1130   PREFIX_VEX_0F2D,
1131   PREFIX_VEX_0F2E,
1132   PREFIX_VEX_0F2F,
1133   PREFIX_VEX_0F41,
1134   PREFIX_VEX_0F42,
1135   PREFIX_VEX_0F44,
1136   PREFIX_VEX_0F45,
1137   PREFIX_VEX_0F46,
1138   PREFIX_VEX_0F47,
1139   PREFIX_VEX_0F4A,
1140   PREFIX_VEX_0F4B,
1141   PREFIX_VEX_0F51,
1142   PREFIX_VEX_0F52,
1143   PREFIX_VEX_0F53,
1144   PREFIX_VEX_0F58,
1145   PREFIX_VEX_0F59,
1146   PREFIX_VEX_0F5A,
1147   PREFIX_VEX_0F5B,
1148   PREFIX_VEX_0F5C,
1149   PREFIX_VEX_0F5D,
1150   PREFIX_VEX_0F5E,
1151   PREFIX_VEX_0F5F,
1152   PREFIX_VEX_0F60,
1153   PREFIX_VEX_0F61,
1154   PREFIX_VEX_0F62,
1155   PREFIX_VEX_0F63,
1156   PREFIX_VEX_0F64,
1157   PREFIX_VEX_0F65,
1158   PREFIX_VEX_0F66,
1159   PREFIX_VEX_0F67,
1160   PREFIX_VEX_0F68,
1161   PREFIX_VEX_0F69,
1162   PREFIX_VEX_0F6A,
1163   PREFIX_VEX_0F6B,
1164   PREFIX_VEX_0F6C,
1165   PREFIX_VEX_0F6D,
1166   PREFIX_VEX_0F6E,
1167   PREFIX_VEX_0F6F,
1168   PREFIX_VEX_0F70,
1169   PREFIX_VEX_0F71_REG_2,
1170   PREFIX_VEX_0F71_REG_4,
1171   PREFIX_VEX_0F71_REG_6,
1172   PREFIX_VEX_0F72_REG_2,
1173   PREFIX_VEX_0F72_REG_4,
1174   PREFIX_VEX_0F72_REG_6,
1175   PREFIX_VEX_0F73_REG_2,
1176   PREFIX_VEX_0F73_REG_3,
1177   PREFIX_VEX_0F73_REG_6,
1178   PREFIX_VEX_0F73_REG_7,
1179   PREFIX_VEX_0F74,
1180   PREFIX_VEX_0F75,
1181   PREFIX_VEX_0F76,
1182   PREFIX_VEX_0F77,
1183   PREFIX_VEX_0F7C,
1184   PREFIX_VEX_0F7D,
1185   PREFIX_VEX_0F7E,
1186   PREFIX_VEX_0F7F,
1187   PREFIX_VEX_0F90,
1188   PREFIX_VEX_0F91,
1189   PREFIX_VEX_0F92,
1190   PREFIX_VEX_0F93,
1191   PREFIX_VEX_0F98,
1192   PREFIX_VEX_0F99,
1193   PREFIX_VEX_0FC2,
1194   PREFIX_VEX_0FC4,
1195   PREFIX_VEX_0FC5,
1196   PREFIX_VEX_0FD0,
1197   PREFIX_VEX_0FD1,
1198   PREFIX_VEX_0FD2,
1199   PREFIX_VEX_0FD3,
1200   PREFIX_VEX_0FD4,
1201   PREFIX_VEX_0FD5,
1202   PREFIX_VEX_0FD6,
1203   PREFIX_VEX_0FD7,
1204   PREFIX_VEX_0FD8,
1205   PREFIX_VEX_0FD9,
1206   PREFIX_VEX_0FDA,
1207   PREFIX_VEX_0FDB,
1208   PREFIX_VEX_0FDC,
1209   PREFIX_VEX_0FDD,
1210   PREFIX_VEX_0FDE,
1211   PREFIX_VEX_0FDF,
1212   PREFIX_VEX_0FE0,
1213   PREFIX_VEX_0FE1,
1214   PREFIX_VEX_0FE2,
1215   PREFIX_VEX_0FE3,
1216   PREFIX_VEX_0FE4,
1217   PREFIX_VEX_0FE5,
1218   PREFIX_VEX_0FE6,
1219   PREFIX_VEX_0FE7,
1220   PREFIX_VEX_0FE8,
1221   PREFIX_VEX_0FE9,
1222   PREFIX_VEX_0FEA,
1223   PREFIX_VEX_0FEB,
1224   PREFIX_VEX_0FEC,
1225   PREFIX_VEX_0FED,
1226   PREFIX_VEX_0FEE,
1227   PREFIX_VEX_0FEF,
1228   PREFIX_VEX_0FF0,
1229   PREFIX_VEX_0FF1,
1230   PREFIX_VEX_0FF2,
1231   PREFIX_VEX_0FF3,
1232   PREFIX_VEX_0FF4,
1233   PREFIX_VEX_0FF5,
1234   PREFIX_VEX_0FF6,
1235   PREFIX_VEX_0FF7,
1236   PREFIX_VEX_0FF8,
1237   PREFIX_VEX_0FF9,
1238   PREFIX_VEX_0FFA,
1239   PREFIX_VEX_0FFB,
1240   PREFIX_VEX_0FFC,
1241   PREFIX_VEX_0FFD,
1242   PREFIX_VEX_0FFE,
1243   PREFIX_VEX_0F3800,
1244   PREFIX_VEX_0F3801,
1245   PREFIX_VEX_0F3802,
1246   PREFIX_VEX_0F3803,
1247   PREFIX_VEX_0F3804,
1248   PREFIX_VEX_0F3805,
1249   PREFIX_VEX_0F3806,
1250   PREFIX_VEX_0F3807,
1251   PREFIX_VEX_0F3808,
1252   PREFIX_VEX_0F3809,
1253   PREFIX_VEX_0F380A,
1254   PREFIX_VEX_0F380B,
1255   PREFIX_VEX_0F380C,
1256   PREFIX_VEX_0F380D,
1257   PREFIX_VEX_0F380E,
1258   PREFIX_VEX_0F380F,
1259   PREFIX_VEX_0F3813,
1260   PREFIX_VEX_0F3816,
1261   PREFIX_VEX_0F3817,
1262   PREFIX_VEX_0F3818,
1263   PREFIX_VEX_0F3819,
1264   PREFIX_VEX_0F381A,
1265   PREFIX_VEX_0F381C,
1266   PREFIX_VEX_0F381D,
1267   PREFIX_VEX_0F381E,
1268   PREFIX_VEX_0F3820,
1269   PREFIX_VEX_0F3821,
1270   PREFIX_VEX_0F3822,
1271   PREFIX_VEX_0F3823,
1272   PREFIX_VEX_0F3824,
1273   PREFIX_VEX_0F3825,
1274   PREFIX_VEX_0F3828,
1275   PREFIX_VEX_0F3829,
1276   PREFIX_VEX_0F382A,
1277   PREFIX_VEX_0F382B,
1278   PREFIX_VEX_0F382C,
1279   PREFIX_VEX_0F382D,
1280   PREFIX_VEX_0F382E,
1281   PREFIX_VEX_0F382F,
1282   PREFIX_VEX_0F3830,
1283   PREFIX_VEX_0F3831,
1284   PREFIX_VEX_0F3832,
1285   PREFIX_VEX_0F3833,
1286   PREFIX_VEX_0F3834,
1287   PREFIX_VEX_0F3835,
1288   PREFIX_VEX_0F3836,
1289   PREFIX_VEX_0F3837,
1290   PREFIX_VEX_0F3838,
1291   PREFIX_VEX_0F3839,
1292   PREFIX_VEX_0F383A,
1293   PREFIX_VEX_0F383B,
1294   PREFIX_VEX_0F383C,
1295   PREFIX_VEX_0F383D,
1296   PREFIX_VEX_0F383E,
1297   PREFIX_VEX_0F383F,
1298   PREFIX_VEX_0F3840,
1299   PREFIX_VEX_0F3841,
1300   PREFIX_VEX_0F3845,
1301   PREFIX_VEX_0F3846,
1302   PREFIX_VEX_0F3847,
1303   PREFIX_VEX_0F3858,
1304   PREFIX_VEX_0F3859,
1305   PREFIX_VEX_0F385A,
1306   PREFIX_VEX_0F3878,
1307   PREFIX_VEX_0F3879,
1308   PREFIX_VEX_0F388C,
1309   PREFIX_VEX_0F388E,
1310   PREFIX_VEX_0F3890,
1311   PREFIX_VEX_0F3891,
1312   PREFIX_VEX_0F3892,
1313   PREFIX_VEX_0F3893,
1314   PREFIX_VEX_0F3896,
1315   PREFIX_VEX_0F3897,
1316   PREFIX_VEX_0F3898,
1317   PREFIX_VEX_0F3899,
1318   PREFIX_VEX_0F389A,
1319   PREFIX_VEX_0F389B,
1320   PREFIX_VEX_0F389C,
1321   PREFIX_VEX_0F389D,
1322   PREFIX_VEX_0F389E,
1323   PREFIX_VEX_0F389F,
1324   PREFIX_VEX_0F38A6,
1325   PREFIX_VEX_0F38A7,
1326   PREFIX_VEX_0F38A8,
1327   PREFIX_VEX_0F38A9,
1328   PREFIX_VEX_0F38AA,
1329   PREFIX_VEX_0F38AB,
1330   PREFIX_VEX_0F38AC,
1331   PREFIX_VEX_0F38AD,
1332   PREFIX_VEX_0F38AE,
1333   PREFIX_VEX_0F38AF,
1334   PREFIX_VEX_0F38B6,
1335   PREFIX_VEX_0F38B7,
1336   PREFIX_VEX_0F38B8,
1337   PREFIX_VEX_0F38B9,
1338   PREFIX_VEX_0F38BA,
1339   PREFIX_VEX_0F38BB,
1340   PREFIX_VEX_0F38BC,
1341   PREFIX_VEX_0F38BD,
1342   PREFIX_VEX_0F38BE,
1343   PREFIX_VEX_0F38BF,
1344   PREFIX_VEX_0F38CF,
1345   PREFIX_VEX_0F38DB,
1346   PREFIX_VEX_0F38DC,
1347   PREFIX_VEX_0F38DD,
1348   PREFIX_VEX_0F38DE,
1349   PREFIX_VEX_0F38DF,
1350   PREFIX_VEX_0F38F2,
1351   PREFIX_VEX_0F38F3_REG_1,
1352   PREFIX_VEX_0F38F3_REG_2,
1353   PREFIX_VEX_0F38F3_REG_3,
1354   PREFIX_VEX_0F38F5,
1355   PREFIX_VEX_0F38F6,
1356   PREFIX_VEX_0F38F7,
1357   PREFIX_VEX_0F3A00,
1358   PREFIX_VEX_0F3A01,
1359   PREFIX_VEX_0F3A02,
1360   PREFIX_VEX_0F3A04,
1361   PREFIX_VEX_0F3A05,
1362   PREFIX_VEX_0F3A06,
1363   PREFIX_VEX_0F3A08,
1364   PREFIX_VEX_0F3A09,
1365   PREFIX_VEX_0F3A0A,
1366   PREFIX_VEX_0F3A0B,
1367   PREFIX_VEX_0F3A0C,
1368   PREFIX_VEX_0F3A0D,
1369   PREFIX_VEX_0F3A0E,
1370   PREFIX_VEX_0F3A0F,
1371   PREFIX_VEX_0F3A14,
1372   PREFIX_VEX_0F3A15,
1373   PREFIX_VEX_0F3A16,
1374   PREFIX_VEX_0F3A17,
1375   PREFIX_VEX_0F3A18,
1376   PREFIX_VEX_0F3A19,
1377   PREFIX_VEX_0F3A1D,
1378   PREFIX_VEX_0F3A20,
1379   PREFIX_VEX_0F3A21,
1380   PREFIX_VEX_0F3A22,
1381   PREFIX_VEX_0F3A30,
1382   PREFIX_VEX_0F3A31,
1383   PREFIX_VEX_0F3A32,
1384   PREFIX_VEX_0F3A33,
1385   PREFIX_VEX_0F3A38,
1386   PREFIX_VEX_0F3A39,
1387   PREFIX_VEX_0F3A40,
1388   PREFIX_VEX_0F3A41,
1389   PREFIX_VEX_0F3A42,
1390   PREFIX_VEX_0F3A44,
1391   PREFIX_VEX_0F3A46,
1392   PREFIX_VEX_0F3A48,
1393   PREFIX_VEX_0F3A49,
1394   PREFIX_VEX_0F3A4A,
1395   PREFIX_VEX_0F3A4B,
1396   PREFIX_VEX_0F3A4C,
1397   PREFIX_VEX_0F3A5C,
1398   PREFIX_VEX_0F3A5D,
1399   PREFIX_VEX_0F3A5E,
1400   PREFIX_VEX_0F3A5F,
1401   PREFIX_VEX_0F3A60,
1402   PREFIX_VEX_0F3A61,
1403   PREFIX_VEX_0F3A62,
1404   PREFIX_VEX_0F3A63,
1405   PREFIX_VEX_0F3A68,
1406   PREFIX_VEX_0F3A69,
1407   PREFIX_VEX_0F3A6A,
1408   PREFIX_VEX_0F3A6B,
1409   PREFIX_VEX_0F3A6C,
1410   PREFIX_VEX_0F3A6D,
1411   PREFIX_VEX_0F3A6E,
1412   PREFIX_VEX_0F3A6F,
1413   PREFIX_VEX_0F3A78,
1414   PREFIX_VEX_0F3A79,
1415   PREFIX_VEX_0F3A7A,
1416   PREFIX_VEX_0F3A7B,
1417   PREFIX_VEX_0F3A7C,
1418   PREFIX_VEX_0F3A7D,
1419   PREFIX_VEX_0F3A7E,
1420   PREFIX_VEX_0F3A7F,
1421   PREFIX_VEX_0F3ACE,
1422   PREFIX_VEX_0F3ACF,
1423   PREFIX_VEX_0F3ADF,
1424   PREFIX_VEX_0F3AF0,
1425
1426   PREFIX_EVEX_0F10,
1427   PREFIX_EVEX_0F11,
1428   PREFIX_EVEX_0F12,
1429   PREFIX_EVEX_0F13,
1430   PREFIX_EVEX_0F14,
1431   PREFIX_EVEX_0F15,
1432   PREFIX_EVEX_0F16,
1433   PREFIX_EVEX_0F17,
1434   PREFIX_EVEX_0F28,
1435   PREFIX_EVEX_0F29,
1436   PREFIX_EVEX_0F2A,
1437   PREFIX_EVEX_0F2B,
1438   PREFIX_EVEX_0F2C,
1439   PREFIX_EVEX_0F2D,
1440   PREFIX_EVEX_0F2E,
1441   PREFIX_EVEX_0F2F,
1442   PREFIX_EVEX_0F51,
1443   PREFIX_EVEX_0F54,
1444   PREFIX_EVEX_0F55,
1445   PREFIX_EVEX_0F56,
1446   PREFIX_EVEX_0F57,
1447   PREFIX_EVEX_0F58,
1448   PREFIX_EVEX_0F59,
1449   PREFIX_EVEX_0F5A,
1450   PREFIX_EVEX_0F5B,
1451   PREFIX_EVEX_0F5C,
1452   PREFIX_EVEX_0F5D,
1453   PREFIX_EVEX_0F5E,
1454   PREFIX_EVEX_0F5F,
1455   PREFIX_EVEX_0F60,
1456   PREFIX_EVEX_0F61,
1457   PREFIX_EVEX_0F62,
1458   PREFIX_EVEX_0F63,
1459   PREFIX_EVEX_0F64,
1460   PREFIX_EVEX_0F65,
1461   PREFIX_EVEX_0F66,
1462   PREFIX_EVEX_0F67,
1463   PREFIX_EVEX_0F68,
1464   PREFIX_EVEX_0F69,
1465   PREFIX_EVEX_0F6A,
1466   PREFIX_EVEX_0F6B,
1467   PREFIX_EVEX_0F6C,
1468   PREFIX_EVEX_0F6D,
1469   PREFIX_EVEX_0F6E,
1470   PREFIX_EVEX_0F6F,
1471   PREFIX_EVEX_0F70,
1472   PREFIX_EVEX_0F71_REG_2,
1473   PREFIX_EVEX_0F71_REG_4,
1474   PREFIX_EVEX_0F71_REG_6,
1475   PREFIX_EVEX_0F72_REG_0,
1476   PREFIX_EVEX_0F72_REG_1,
1477   PREFIX_EVEX_0F72_REG_2,
1478   PREFIX_EVEX_0F72_REG_4,
1479   PREFIX_EVEX_0F72_REG_6,
1480   PREFIX_EVEX_0F73_REG_2,
1481   PREFIX_EVEX_0F73_REG_3,
1482   PREFIX_EVEX_0F73_REG_6,
1483   PREFIX_EVEX_0F73_REG_7,
1484   PREFIX_EVEX_0F74,
1485   PREFIX_EVEX_0F75,
1486   PREFIX_EVEX_0F76,
1487   PREFIX_EVEX_0F78,
1488   PREFIX_EVEX_0F79,
1489   PREFIX_EVEX_0F7A,
1490   PREFIX_EVEX_0F7B,
1491   PREFIX_EVEX_0F7E,
1492   PREFIX_EVEX_0F7F,
1493   PREFIX_EVEX_0FC2,
1494   PREFIX_EVEX_0FC4,
1495   PREFIX_EVEX_0FC5,
1496   PREFIX_EVEX_0FC6,
1497   PREFIX_EVEX_0FD1,
1498   PREFIX_EVEX_0FD2,
1499   PREFIX_EVEX_0FD3,
1500   PREFIX_EVEX_0FD4,
1501   PREFIX_EVEX_0FD5,
1502   PREFIX_EVEX_0FD6,
1503   PREFIX_EVEX_0FD8,
1504   PREFIX_EVEX_0FD9,
1505   PREFIX_EVEX_0FDA,
1506   PREFIX_EVEX_0FDB,
1507   PREFIX_EVEX_0FDC,
1508   PREFIX_EVEX_0FDD,
1509   PREFIX_EVEX_0FDE,
1510   PREFIX_EVEX_0FDF,
1511   PREFIX_EVEX_0FE0,
1512   PREFIX_EVEX_0FE1,
1513   PREFIX_EVEX_0FE2,
1514   PREFIX_EVEX_0FE3,
1515   PREFIX_EVEX_0FE4,
1516   PREFIX_EVEX_0FE5,
1517   PREFIX_EVEX_0FE6,
1518   PREFIX_EVEX_0FE7,
1519   PREFIX_EVEX_0FE8,
1520   PREFIX_EVEX_0FE9,
1521   PREFIX_EVEX_0FEA,
1522   PREFIX_EVEX_0FEB,
1523   PREFIX_EVEX_0FEC,
1524   PREFIX_EVEX_0FED,
1525   PREFIX_EVEX_0FEE,
1526   PREFIX_EVEX_0FEF,
1527   PREFIX_EVEX_0FF1,
1528   PREFIX_EVEX_0FF2,
1529   PREFIX_EVEX_0FF3,
1530   PREFIX_EVEX_0FF4,
1531   PREFIX_EVEX_0FF5,
1532   PREFIX_EVEX_0FF6,
1533   PREFIX_EVEX_0FF8,
1534   PREFIX_EVEX_0FF9,
1535   PREFIX_EVEX_0FFA,
1536   PREFIX_EVEX_0FFB,
1537   PREFIX_EVEX_0FFC,
1538   PREFIX_EVEX_0FFD,
1539   PREFIX_EVEX_0FFE,
1540   PREFIX_EVEX_0F3800,
1541   PREFIX_EVEX_0F3804,
1542   PREFIX_EVEX_0F380B,
1543   PREFIX_EVEX_0F380C,
1544   PREFIX_EVEX_0F380D,
1545   PREFIX_EVEX_0F3810,
1546   PREFIX_EVEX_0F3811,
1547   PREFIX_EVEX_0F3812,
1548   PREFIX_EVEX_0F3813,
1549   PREFIX_EVEX_0F3814,
1550   PREFIX_EVEX_0F3815,
1551   PREFIX_EVEX_0F3816,
1552   PREFIX_EVEX_0F3818,
1553   PREFIX_EVEX_0F3819,
1554   PREFIX_EVEX_0F381A,
1555   PREFIX_EVEX_0F381B,
1556   PREFIX_EVEX_0F381C,
1557   PREFIX_EVEX_0F381D,
1558   PREFIX_EVEX_0F381E,
1559   PREFIX_EVEX_0F381F,
1560   PREFIX_EVEX_0F3820,
1561   PREFIX_EVEX_0F3821,
1562   PREFIX_EVEX_0F3822,
1563   PREFIX_EVEX_0F3823,
1564   PREFIX_EVEX_0F3824,
1565   PREFIX_EVEX_0F3825,
1566   PREFIX_EVEX_0F3826,
1567   PREFIX_EVEX_0F3827,
1568   PREFIX_EVEX_0F3828,
1569   PREFIX_EVEX_0F3829,
1570   PREFIX_EVEX_0F382A,
1571   PREFIX_EVEX_0F382B,
1572   PREFIX_EVEX_0F382C,
1573   PREFIX_EVEX_0F382D,
1574   PREFIX_EVEX_0F3830,
1575   PREFIX_EVEX_0F3831,
1576   PREFIX_EVEX_0F3832,
1577   PREFIX_EVEX_0F3833,
1578   PREFIX_EVEX_0F3834,
1579   PREFIX_EVEX_0F3835,
1580   PREFIX_EVEX_0F3836,
1581   PREFIX_EVEX_0F3837,
1582   PREFIX_EVEX_0F3838,
1583   PREFIX_EVEX_0F3839,
1584   PREFIX_EVEX_0F383A,
1585   PREFIX_EVEX_0F383B,
1586   PREFIX_EVEX_0F383C,
1587   PREFIX_EVEX_0F383D,
1588   PREFIX_EVEX_0F383E,
1589   PREFIX_EVEX_0F383F,
1590   PREFIX_EVEX_0F3840,
1591   PREFIX_EVEX_0F3842,
1592   PREFIX_EVEX_0F3843,
1593   PREFIX_EVEX_0F3844,
1594   PREFIX_EVEX_0F3845,
1595   PREFIX_EVEX_0F3846,
1596   PREFIX_EVEX_0F3847,
1597   PREFIX_EVEX_0F384C,
1598   PREFIX_EVEX_0F384D,
1599   PREFIX_EVEX_0F384E,
1600   PREFIX_EVEX_0F384F,
1601   PREFIX_EVEX_0F3850,
1602   PREFIX_EVEX_0F3851,
1603   PREFIX_EVEX_0F3852,
1604   PREFIX_EVEX_0F3853,
1605   PREFIX_EVEX_0F3854,
1606   PREFIX_EVEX_0F3855,
1607   PREFIX_EVEX_0F3858,
1608   PREFIX_EVEX_0F3859,
1609   PREFIX_EVEX_0F385A,
1610   PREFIX_EVEX_0F385B,
1611   PREFIX_EVEX_0F3862,
1612   PREFIX_EVEX_0F3863,
1613   PREFIX_EVEX_0F3864,
1614   PREFIX_EVEX_0F3865,
1615   PREFIX_EVEX_0F3866,
1616   PREFIX_EVEX_0F3868,
1617   PREFIX_EVEX_0F3870,
1618   PREFIX_EVEX_0F3871,
1619   PREFIX_EVEX_0F3872,
1620   PREFIX_EVEX_0F3873,
1621   PREFIX_EVEX_0F3875,
1622   PREFIX_EVEX_0F3876,
1623   PREFIX_EVEX_0F3877,
1624   PREFIX_EVEX_0F3878,
1625   PREFIX_EVEX_0F3879,
1626   PREFIX_EVEX_0F387A,
1627   PREFIX_EVEX_0F387B,
1628   PREFIX_EVEX_0F387C,
1629   PREFIX_EVEX_0F387D,
1630   PREFIX_EVEX_0F387E,
1631   PREFIX_EVEX_0F387F,
1632   PREFIX_EVEX_0F3883,
1633   PREFIX_EVEX_0F3888,
1634   PREFIX_EVEX_0F3889,
1635   PREFIX_EVEX_0F388A,
1636   PREFIX_EVEX_0F388B,
1637   PREFIX_EVEX_0F388D,
1638   PREFIX_EVEX_0F388F,
1639   PREFIX_EVEX_0F3890,
1640   PREFIX_EVEX_0F3891,
1641   PREFIX_EVEX_0F3892,
1642   PREFIX_EVEX_0F3893,
1643   PREFIX_EVEX_0F3896,
1644   PREFIX_EVEX_0F3897,
1645   PREFIX_EVEX_0F3898,
1646   PREFIX_EVEX_0F3899,
1647   PREFIX_EVEX_0F389A,
1648   PREFIX_EVEX_0F389B,
1649   PREFIX_EVEX_0F389C,
1650   PREFIX_EVEX_0F389D,
1651   PREFIX_EVEX_0F389E,
1652   PREFIX_EVEX_0F389F,
1653   PREFIX_EVEX_0F38A0,
1654   PREFIX_EVEX_0F38A1,
1655   PREFIX_EVEX_0F38A2,
1656   PREFIX_EVEX_0F38A3,
1657   PREFIX_EVEX_0F38A6,
1658   PREFIX_EVEX_0F38A7,
1659   PREFIX_EVEX_0F38A8,
1660   PREFIX_EVEX_0F38A9,
1661   PREFIX_EVEX_0F38AA,
1662   PREFIX_EVEX_0F38AB,
1663   PREFIX_EVEX_0F38AC,
1664   PREFIX_EVEX_0F38AD,
1665   PREFIX_EVEX_0F38AE,
1666   PREFIX_EVEX_0F38AF,
1667   PREFIX_EVEX_0F38B4,
1668   PREFIX_EVEX_0F38B5,
1669   PREFIX_EVEX_0F38B6,
1670   PREFIX_EVEX_0F38B7,
1671   PREFIX_EVEX_0F38B8,
1672   PREFIX_EVEX_0F38B9,
1673   PREFIX_EVEX_0F38BA,
1674   PREFIX_EVEX_0F38BB,
1675   PREFIX_EVEX_0F38BC,
1676   PREFIX_EVEX_0F38BD,
1677   PREFIX_EVEX_0F38BE,
1678   PREFIX_EVEX_0F38BF,
1679   PREFIX_EVEX_0F38C4,
1680   PREFIX_EVEX_0F38C6_REG_1,
1681   PREFIX_EVEX_0F38C6_REG_2,
1682   PREFIX_EVEX_0F38C6_REG_5,
1683   PREFIX_EVEX_0F38C6_REG_6,
1684   PREFIX_EVEX_0F38C7_REG_1,
1685   PREFIX_EVEX_0F38C7_REG_2,
1686   PREFIX_EVEX_0F38C7_REG_5,
1687   PREFIX_EVEX_0F38C7_REG_6,
1688   PREFIX_EVEX_0F38C8,
1689   PREFIX_EVEX_0F38CA,
1690   PREFIX_EVEX_0F38CB,
1691   PREFIX_EVEX_0F38CC,
1692   PREFIX_EVEX_0F38CD,
1693   PREFIX_EVEX_0F38CF,
1694   PREFIX_EVEX_0F38DC,
1695   PREFIX_EVEX_0F38DD,
1696   PREFIX_EVEX_0F38DE,
1697   PREFIX_EVEX_0F38DF,
1698
1699   PREFIX_EVEX_0F3A00,
1700   PREFIX_EVEX_0F3A01,
1701   PREFIX_EVEX_0F3A03,
1702   PREFIX_EVEX_0F3A04,
1703   PREFIX_EVEX_0F3A05,
1704   PREFIX_EVEX_0F3A08,
1705   PREFIX_EVEX_0F3A09,
1706   PREFIX_EVEX_0F3A0A,
1707   PREFIX_EVEX_0F3A0B,
1708   PREFIX_EVEX_0F3A0F,
1709   PREFIX_EVEX_0F3A14,
1710   PREFIX_EVEX_0F3A15,
1711   PREFIX_EVEX_0F3A16,
1712   PREFIX_EVEX_0F3A17,
1713   PREFIX_EVEX_0F3A18,
1714   PREFIX_EVEX_0F3A19,
1715   PREFIX_EVEX_0F3A1A,
1716   PREFIX_EVEX_0F3A1B,
1717   PREFIX_EVEX_0F3A1D,
1718   PREFIX_EVEX_0F3A1E,
1719   PREFIX_EVEX_0F3A1F,
1720   PREFIX_EVEX_0F3A20,
1721   PREFIX_EVEX_0F3A21,
1722   PREFIX_EVEX_0F3A22,
1723   PREFIX_EVEX_0F3A23,
1724   PREFIX_EVEX_0F3A25,
1725   PREFIX_EVEX_0F3A26,
1726   PREFIX_EVEX_0F3A27,
1727   PREFIX_EVEX_0F3A38,
1728   PREFIX_EVEX_0F3A39,
1729   PREFIX_EVEX_0F3A3A,
1730   PREFIX_EVEX_0F3A3B,
1731   PREFIX_EVEX_0F3A3E,
1732   PREFIX_EVEX_0F3A3F,
1733   PREFIX_EVEX_0F3A42,
1734   PREFIX_EVEX_0F3A43,
1735   PREFIX_EVEX_0F3A44,
1736   PREFIX_EVEX_0F3A50,
1737   PREFIX_EVEX_0F3A51,
1738   PREFIX_EVEX_0F3A54,
1739   PREFIX_EVEX_0F3A55,
1740   PREFIX_EVEX_0F3A56,
1741   PREFIX_EVEX_0F3A57,
1742   PREFIX_EVEX_0F3A66,
1743   PREFIX_EVEX_0F3A67,
1744   PREFIX_EVEX_0F3A70,
1745   PREFIX_EVEX_0F3A71,
1746   PREFIX_EVEX_0F3A72,
1747   PREFIX_EVEX_0F3A73,
1748   PREFIX_EVEX_0F3ACE,
1749   PREFIX_EVEX_0F3ACF
1750 };
1751
1752 enum
1753 {
1754   X86_64_06 = 0,
1755   X86_64_07,
1756   X86_64_0D,
1757   X86_64_16,
1758   X86_64_17,
1759   X86_64_1E,
1760   X86_64_1F,
1761   X86_64_27,
1762   X86_64_2F,
1763   X86_64_37,
1764   X86_64_3F,
1765   X86_64_60,
1766   X86_64_61,
1767   X86_64_62,
1768   X86_64_63,
1769   X86_64_6D,
1770   X86_64_6F,
1771   X86_64_82,
1772   X86_64_9A,
1773   X86_64_C4,
1774   X86_64_C5,
1775   X86_64_CE,
1776   X86_64_D4,
1777   X86_64_D5,
1778   X86_64_E8,
1779   X86_64_E9,
1780   X86_64_EA,
1781   X86_64_0F01_REG_0,
1782   X86_64_0F01_REG_1,
1783   X86_64_0F01_REG_2,
1784   X86_64_0F01_REG_3
1785 };
1786
1787 enum
1788 {
1789   THREE_BYTE_0F38 = 0,
1790   THREE_BYTE_0F3A
1791 };
1792
1793 enum
1794 {
1795   XOP_08 = 0,
1796   XOP_09,
1797   XOP_0A
1798 };
1799
1800 enum
1801 {
1802   VEX_0F = 0,
1803   VEX_0F38,
1804   VEX_0F3A
1805 };
1806
1807 enum
1808 {
1809   EVEX_0F = 0,
1810   EVEX_0F38,
1811   EVEX_0F3A
1812 };
1813
1814 enum
1815 {
1816   VEX_LEN_0F12_P_0_M_0 = 0,
1817   VEX_LEN_0F12_P_0_M_1,
1818   VEX_LEN_0F12_P_2,
1819   VEX_LEN_0F13_M_0,
1820   VEX_LEN_0F16_P_0_M_0,
1821   VEX_LEN_0F16_P_0_M_1,
1822   VEX_LEN_0F16_P_2,
1823   VEX_LEN_0F17_M_0,
1824   VEX_LEN_0F2A_P_1,
1825   VEX_LEN_0F2A_P_3,
1826   VEX_LEN_0F2C_P_1,
1827   VEX_LEN_0F2C_P_3,
1828   VEX_LEN_0F2D_P_1,
1829   VEX_LEN_0F2D_P_3,
1830   VEX_LEN_0F41_P_0,
1831   VEX_LEN_0F41_P_2,
1832   VEX_LEN_0F42_P_0,
1833   VEX_LEN_0F42_P_2,
1834   VEX_LEN_0F44_P_0,
1835   VEX_LEN_0F44_P_2,
1836   VEX_LEN_0F45_P_0,
1837   VEX_LEN_0F45_P_2,
1838   VEX_LEN_0F46_P_0,
1839   VEX_LEN_0F46_P_2,
1840   VEX_LEN_0F47_P_0,
1841   VEX_LEN_0F47_P_2,
1842   VEX_LEN_0F4A_P_0,
1843   VEX_LEN_0F4A_P_2,
1844   VEX_LEN_0F4B_P_0,
1845   VEX_LEN_0F4B_P_2,
1846   VEX_LEN_0F6E_P_2,
1847   VEX_LEN_0F77_P_0,
1848   VEX_LEN_0F7E_P_1,
1849   VEX_LEN_0F7E_P_2,
1850   VEX_LEN_0F90_P_0,
1851   VEX_LEN_0F90_P_2,
1852   VEX_LEN_0F91_P_0,
1853   VEX_LEN_0F91_P_2,
1854   VEX_LEN_0F92_P_0,
1855   VEX_LEN_0F92_P_2,
1856   VEX_LEN_0F92_P_3,
1857   VEX_LEN_0F93_P_0,
1858   VEX_LEN_0F93_P_2,
1859   VEX_LEN_0F93_P_3,
1860   VEX_LEN_0F98_P_0,
1861   VEX_LEN_0F98_P_2,
1862   VEX_LEN_0F99_P_0,
1863   VEX_LEN_0F99_P_2,
1864   VEX_LEN_0FAE_R_2_M_0,
1865   VEX_LEN_0FAE_R_3_M_0,
1866   VEX_LEN_0FC4_P_2,
1867   VEX_LEN_0FC5_P_2,
1868   VEX_LEN_0FD6_P_2,
1869   VEX_LEN_0FF7_P_2,
1870   VEX_LEN_0F3816_P_2,
1871   VEX_LEN_0F3819_P_2,
1872   VEX_LEN_0F381A_P_2_M_0,
1873   VEX_LEN_0F3836_P_2,
1874   VEX_LEN_0F3841_P_2,
1875   VEX_LEN_0F385A_P_2_M_0,
1876   VEX_LEN_0F38DB_P_2,
1877   VEX_LEN_0F38F2_P_0,
1878   VEX_LEN_0F38F3_R_1_P_0,
1879   VEX_LEN_0F38F3_R_2_P_0,
1880   VEX_LEN_0F38F3_R_3_P_0,
1881   VEX_LEN_0F38F5_P_0,
1882   VEX_LEN_0F38F5_P_1,
1883   VEX_LEN_0F38F5_P_3,
1884   VEX_LEN_0F38F6_P_3,
1885   VEX_LEN_0F38F7_P_0,
1886   VEX_LEN_0F38F7_P_1,
1887   VEX_LEN_0F38F7_P_2,
1888   VEX_LEN_0F38F7_P_3,
1889   VEX_LEN_0F3A00_P_2,
1890   VEX_LEN_0F3A01_P_2,
1891   VEX_LEN_0F3A06_P_2,
1892   VEX_LEN_0F3A14_P_2,
1893   VEX_LEN_0F3A15_P_2,
1894   VEX_LEN_0F3A16_P_2,
1895   VEX_LEN_0F3A17_P_2,
1896   VEX_LEN_0F3A18_P_2,
1897   VEX_LEN_0F3A19_P_2,
1898   VEX_LEN_0F3A20_P_2,
1899   VEX_LEN_0F3A21_P_2,
1900   VEX_LEN_0F3A22_P_2,
1901   VEX_LEN_0F3A30_P_2,
1902   VEX_LEN_0F3A31_P_2,
1903   VEX_LEN_0F3A32_P_2,
1904   VEX_LEN_0F3A33_P_2,
1905   VEX_LEN_0F3A38_P_2,
1906   VEX_LEN_0F3A39_P_2,
1907   VEX_LEN_0F3A41_P_2,
1908   VEX_LEN_0F3A46_P_2,
1909   VEX_LEN_0F3A60_P_2,
1910   VEX_LEN_0F3A61_P_2,
1911   VEX_LEN_0F3A62_P_2,
1912   VEX_LEN_0F3A63_P_2,
1913   VEX_LEN_0F3A6A_P_2,
1914   VEX_LEN_0F3A6B_P_2,
1915   VEX_LEN_0F3A6E_P_2,
1916   VEX_LEN_0F3A6F_P_2,
1917   VEX_LEN_0F3A7A_P_2,
1918   VEX_LEN_0F3A7B_P_2,
1919   VEX_LEN_0F3A7E_P_2,
1920   VEX_LEN_0F3A7F_P_2,
1921   VEX_LEN_0F3ADF_P_2,
1922   VEX_LEN_0F3AF0_P_3,
1923   VEX_LEN_0FXOP_08_CC,
1924   VEX_LEN_0FXOP_08_CD,
1925   VEX_LEN_0FXOP_08_CE,
1926   VEX_LEN_0FXOP_08_CF,
1927   VEX_LEN_0FXOP_08_EC,
1928   VEX_LEN_0FXOP_08_ED,
1929   VEX_LEN_0FXOP_08_EE,
1930   VEX_LEN_0FXOP_08_EF,
1931   VEX_LEN_0FXOP_09_80,
1932   VEX_LEN_0FXOP_09_81
1933 };
1934
1935 enum
1936 {
1937   EVEX_LEN_0F6E_P_2 = 0,
1938   EVEX_LEN_0F7E_P_1,
1939   EVEX_LEN_0F7E_P_2,
1940   EVEX_LEN_0FD6_P_2
1941 };
1942
1943 enum
1944 {
1945   VEX_W_0F41_P_0_LEN_1 = 0,
1946   VEX_W_0F41_P_2_LEN_1,
1947   VEX_W_0F42_P_0_LEN_1,
1948   VEX_W_0F42_P_2_LEN_1,
1949   VEX_W_0F44_P_0_LEN_0,
1950   VEX_W_0F44_P_2_LEN_0,
1951   VEX_W_0F45_P_0_LEN_1,
1952   VEX_W_0F45_P_2_LEN_1,
1953   VEX_W_0F46_P_0_LEN_1,
1954   VEX_W_0F46_P_2_LEN_1,
1955   VEX_W_0F47_P_0_LEN_1,
1956   VEX_W_0F47_P_2_LEN_1,
1957   VEX_W_0F4A_P_0_LEN_1,
1958   VEX_W_0F4A_P_2_LEN_1,
1959   VEX_W_0F4B_P_0_LEN_1,
1960   VEX_W_0F4B_P_2_LEN_1,
1961   VEX_W_0F90_P_0_LEN_0,
1962   VEX_W_0F90_P_2_LEN_0,
1963   VEX_W_0F91_P_0_LEN_0,
1964   VEX_W_0F91_P_2_LEN_0,
1965   VEX_W_0F92_P_0_LEN_0,
1966   VEX_W_0F92_P_2_LEN_0,
1967   VEX_W_0F93_P_0_LEN_0,
1968   VEX_W_0F93_P_2_LEN_0,
1969   VEX_W_0F98_P_0_LEN_0,
1970   VEX_W_0F98_P_2_LEN_0,
1971   VEX_W_0F99_P_0_LEN_0,
1972   VEX_W_0F99_P_2_LEN_0,
1973   VEX_W_0F380C_P_2,
1974   VEX_W_0F380D_P_2,
1975   VEX_W_0F380E_P_2,
1976   VEX_W_0F380F_P_2,
1977   VEX_W_0F3816_P_2,
1978   VEX_W_0F3818_P_2,
1979   VEX_W_0F3819_P_2,
1980   VEX_W_0F381A_P_2_M_0,
1981   VEX_W_0F382C_P_2_M_0,
1982   VEX_W_0F382D_P_2_M_0,
1983   VEX_W_0F382E_P_2_M_0,
1984   VEX_W_0F382F_P_2_M_0,
1985   VEX_W_0F3836_P_2,
1986   VEX_W_0F3846_P_2,
1987   VEX_W_0F3858_P_2,
1988   VEX_W_0F3859_P_2,
1989   VEX_W_0F385A_P_2_M_0,
1990   VEX_W_0F3878_P_2,
1991   VEX_W_0F3879_P_2,
1992   VEX_W_0F38CF_P_2,
1993   VEX_W_0F3A00_P_2,
1994   VEX_W_0F3A01_P_2,
1995   VEX_W_0F3A02_P_2,
1996   VEX_W_0F3A04_P_2,
1997   VEX_W_0F3A05_P_2,
1998   VEX_W_0F3A06_P_2,
1999   VEX_W_0F3A18_P_2,
2000   VEX_W_0F3A19_P_2,
2001   VEX_W_0F3A30_P_2_LEN_0,
2002   VEX_W_0F3A31_P_2_LEN_0,
2003   VEX_W_0F3A32_P_2_LEN_0,
2004   VEX_W_0F3A33_P_2_LEN_0,
2005   VEX_W_0F3A38_P_2,
2006   VEX_W_0F3A39_P_2,
2007   VEX_W_0F3A46_P_2,
2008   VEX_W_0F3A48_P_2,
2009   VEX_W_0F3A49_P_2,
2010   VEX_W_0F3A4A_P_2,
2011   VEX_W_0F3A4B_P_2,
2012   VEX_W_0F3A4C_P_2,
2013   VEX_W_0F3ACE_P_2,
2014   VEX_W_0F3ACF_P_2,
2015
2016   EVEX_W_0F10_P_0,
2017   EVEX_W_0F10_P_1_M_0,
2018   EVEX_W_0F10_P_1_M_1,
2019   EVEX_W_0F10_P_2,
2020   EVEX_W_0F10_P_3_M_0,
2021   EVEX_W_0F10_P_3_M_1,
2022   EVEX_W_0F11_P_0,
2023   EVEX_W_0F11_P_1_M_0,
2024   EVEX_W_0F11_P_1_M_1,
2025   EVEX_W_0F11_P_2,
2026   EVEX_W_0F11_P_3_M_0,
2027   EVEX_W_0F11_P_3_M_1,
2028   EVEX_W_0F12_P_0_M_0,
2029   EVEX_W_0F12_P_0_M_1,
2030   EVEX_W_0F12_P_1,
2031   EVEX_W_0F12_P_2,
2032   EVEX_W_0F12_P_3,
2033   EVEX_W_0F13_P_0,
2034   EVEX_W_0F13_P_2,
2035   EVEX_W_0F14_P_0,
2036   EVEX_W_0F14_P_2,
2037   EVEX_W_0F15_P_0,
2038   EVEX_W_0F15_P_2,
2039   EVEX_W_0F16_P_0_M_0,
2040   EVEX_W_0F16_P_0_M_1,
2041   EVEX_W_0F16_P_1,
2042   EVEX_W_0F16_P_2,
2043   EVEX_W_0F17_P_0,
2044   EVEX_W_0F17_P_2,
2045   EVEX_W_0F28_P_0,
2046   EVEX_W_0F28_P_2,
2047   EVEX_W_0F29_P_0,
2048   EVEX_W_0F29_P_2,
2049   EVEX_W_0F2A_P_1,
2050   EVEX_W_0F2A_P_3,
2051   EVEX_W_0F2B_P_0,
2052   EVEX_W_0F2B_P_2,
2053   EVEX_W_0F2E_P_0,
2054   EVEX_W_0F2E_P_2,
2055   EVEX_W_0F2F_P_0,
2056   EVEX_W_0F2F_P_2,
2057   EVEX_W_0F51_P_0,
2058   EVEX_W_0F51_P_1,
2059   EVEX_W_0F51_P_2,
2060   EVEX_W_0F51_P_3,
2061   EVEX_W_0F54_P_0,
2062   EVEX_W_0F54_P_2,
2063   EVEX_W_0F55_P_0,
2064   EVEX_W_0F55_P_2,
2065   EVEX_W_0F56_P_0,
2066   EVEX_W_0F56_P_2,
2067   EVEX_W_0F57_P_0,
2068   EVEX_W_0F57_P_2,
2069   EVEX_W_0F58_P_0,
2070   EVEX_W_0F58_P_1,
2071   EVEX_W_0F58_P_2,
2072   EVEX_W_0F58_P_3,
2073   EVEX_W_0F59_P_0,
2074   EVEX_W_0F59_P_1,
2075   EVEX_W_0F59_P_2,
2076   EVEX_W_0F59_P_3,
2077   EVEX_W_0F5A_P_0,
2078   EVEX_W_0F5A_P_1,
2079   EVEX_W_0F5A_P_2,
2080   EVEX_W_0F5A_P_3,
2081   EVEX_W_0F5B_P_0,
2082   EVEX_W_0F5B_P_1,
2083   EVEX_W_0F5B_P_2,
2084   EVEX_W_0F5C_P_0,
2085   EVEX_W_0F5C_P_1,
2086   EVEX_W_0F5C_P_2,
2087   EVEX_W_0F5C_P_3,
2088   EVEX_W_0F5D_P_0,
2089   EVEX_W_0F5D_P_1,
2090   EVEX_W_0F5D_P_2,
2091   EVEX_W_0F5D_P_3,
2092   EVEX_W_0F5E_P_0,
2093   EVEX_W_0F5E_P_1,
2094   EVEX_W_0F5E_P_2,
2095   EVEX_W_0F5E_P_3,
2096   EVEX_W_0F5F_P_0,
2097   EVEX_W_0F5F_P_1,
2098   EVEX_W_0F5F_P_2,
2099   EVEX_W_0F5F_P_3,
2100   EVEX_W_0F62_P_2,
2101   EVEX_W_0F66_P_2,
2102   EVEX_W_0F6A_P_2,
2103   EVEX_W_0F6B_P_2,
2104   EVEX_W_0F6C_P_2,
2105   EVEX_W_0F6D_P_2,
2106   EVEX_W_0F6F_P_1,
2107   EVEX_W_0F6F_P_2,
2108   EVEX_W_0F6F_P_3,
2109   EVEX_W_0F70_P_2,
2110   EVEX_W_0F72_R_2_P_2,
2111   EVEX_W_0F72_R_6_P_2,
2112   EVEX_W_0F73_R_2_P_2,
2113   EVEX_W_0F73_R_6_P_2,
2114   EVEX_W_0F76_P_2,
2115   EVEX_W_0F78_P_0,
2116   EVEX_W_0F78_P_2,
2117   EVEX_W_0F79_P_0,
2118   EVEX_W_0F79_P_2,
2119   EVEX_W_0F7A_P_1,
2120   EVEX_W_0F7A_P_2,
2121   EVEX_W_0F7A_P_3,
2122   EVEX_W_0F7B_P_1,
2123   EVEX_W_0F7B_P_2,
2124   EVEX_W_0F7B_P_3,
2125   EVEX_W_0F7E_P_1,
2126   EVEX_W_0F7F_P_1,
2127   EVEX_W_0F7F_P_2,
2128   EVEX_W_0F7F_P_3,
2129   EVEX_W_0FC2_P_0,
2130   EVEX_W_0FC2_P_1,
2131   EVEX_W_0FC2_P_2,
2132   EVEX_W_0FC2_P_3,
2133   EVEX_W_0FC6_P_0,
2134   EVEX_W_0FC6_P_2,
2135   EVEX_W_0FD2_P_2,
2136   EVEX_W_0FD3_P_2,
2137   EVEX_W_0FD4_P_2,
2138   EVEX_W_0FD6_P_2,
2139   EVEX_W_0FE6_P_1,
2140   EVEX_W_0FE6_P_2,
2141   EVEX_W_0FE6_P_3,
2142   EVEX_W_0FE7_P_2,
2143   EVEX_W_0FF2_P_2,
2144   EVEX_W_0FF3_P_2,
2145   EVEX_W_0FF4_P_2,
2146   EVEX_W_0FFA_P_2,
2147   EVEX_W_0FFB_P_2,
2148   EVEX_W_0FFE_P_2,
2149   EVEX_W_0F380C_P_2,
2150   EVEX_W_0F380D_P_2,
2151   EVEX_W_0F3810_P_1,
2152   EVEX_W_0F3810_P_2,
2153   EVEX_W_0F3811_P_1,
2154   EVEX_W_0F3811_P_2,
2155   EVEX_W_0F3812_P_1,
2156   EVEX_W_0F3812_P_2,
2157   EVEX_W_0F3813_P_1,
2158   EVEX_W_0F3813_P_2,
2159   EVEX_W_0F3814_P_1,
2160   EVEX_W_0F3815_P_1,
2161   EVEX_W_0F3818_P_2,
2162   EVEX_W_0F3819_P_2,
2163   EVEX_W_0F381A_P_2,
2164   EVEX_W_0F381B_P_2,
2165   EVEX_W_0F381E_P_2,
2166   EVEX_W_0F381F_P_2,
2167   EVEX_W_0F3820_P_1,
2168   EVEX_W_0F3821_P_1,
2169   EVEX_W_0F3822_P_1,
2170   EVEX_W_0F3823_P_1,
2171   EVEX_W_0F3824_P_1,
2172   EVEX_W_0F3825_P_1,
2173   EVEX_W_0F3825_P_2,
2174   EVEX_W_0F3826_P_1,
2175   EVEX_W_0F3826_P_2,
2176   EVEX_W_0F3828_P_1,
2177   EVEX_W_0F3828_P_2,
2178   EVEX_W_0F3829_P_1,
2179   EVEX_W_0F3829_P_2,
2180   EVEX_W_0F382A_P_1,
2181   EVEX_W_0F382A_P_2,
2182   EVEX_W_0F382B_P_2,
2183   EVEX_W_0F3830_P_1,
2184   EVEX_W_0F3831_P_1,
2185   EVEX_W_0F3832_P_1,
2186   EVEX_W_0F3833_P_1,
2187   EVEX_W_0F3834_P_1,
2188   EVEX_W_0F3835_P_1,
2189   EVEX_W_0F3835_P_2,
2190   EVEX_W_0F3837_P_2,
2191   EVEX_W_0F3838_P_1,
2192   EVEX_W_0F3839_P_1,
2193   EVEX_W_0F383A_P_1,
2194   EVEX_W_0F3840_P_2,
2195   EVEX_W_0F3852_P_1,
2196   EVEX_W_0F3854_P_2,
2197   EVEX_W_0F3855_P_2,
2198   EVEX_W_0F3858_P_2,
2199   EVEX_W_0F3859_P_2,
2200   EVEX_W_0F385A_P_2,
2201   EVEX_W_0F385B_P_2,
2202   EVEX_W_0F3862_P_2,
2203   EVEX_W_0F3863_P_2,
2204   EVEX_W_0F3866_P_2,
2205   EVEX_W_0F3868_P_3,
2206   EVEX_W_0F3870_P_2,
2207   EVEX_W_0F3871_P_2,
2208   EVEX_W_0F3872_P_1,
2209   EVEX_W_0F3872_P_2,
2210   EVEX_W_0F3872_P_3,
2211   EVEX_W_0F3873_P_2,
2212   EVEX_W_0F3875_P_2,
2213   EVEX_W_0F3878_P_2,
2214   EVEX_W_0F3879_P_2,
2215   EVEX_W_0F387A_P_2,
2216   EVEX_W_0F387B_P_2,
2217   EVEX_W_0F387D_P_2,
2218   EVEX_W_0F3883_P_2,
2219   EVEX_W_0F388D_P_2,
2220   EVEX_W_0F3891_P_2,
2221   EVEX_W_0F3893_P_2,
2222   EVEX_W_0F38A1_P_2,
2223   EVEX_W_0F38A3_P_2,
2224   EVEX_W_0F38C7_R_1_P_2,
2225   EVEX_W_0F38C7_R_2_P_2,
2226   EVEX_W_0F38C7_R_5_P_2,
2227   EVEX_W_0F38C7_R_6_P_2,
2228
2229   EVEX_W_0F3A00_P_2,
2230   EVEX_W_0F3A01_P_2,
2231   EVEX_W_0F3A04_P_2,
2232   EVEX_W_0F3A05_P_2,
2233   EVEX_W_0F3A08_P_2,
2234   EVEX_W_0F3A09_P_2,
2235   EVEX_W_0F3A0A_P_2,
2236   EVEX_W_0F3A0B_P_2,
2237   EVEX_W_0F3A18_P_2,
2238   EVEX_W_0F3A19_P_2,
2239   EVEX_W_0F3A1A_P_2,
2240   EVEX_W_0F3A1B_P_2,
2241   EVEX_W_0F3A1D_P_2,
2242   EVEX_W_0F3A21_P_2,
2243   EVEX_W_0F3A23_P_2,
2244   EVEX_W_0F3A38_P_2,
2245   EVEX_W_0F3A39_P_2,
2246   EVEX_W_0F3A3A_P_2,
2247   EVEX_W_0F3A3B_P_2,
2248   EVEX_W_0F3A3E_P_2,
2249   EVEX_W_0F3A3F_P_2,
2250   EVEX_W_0F3A42_P_2,
2251   EVEX_W_0F3A43_P_2,
2252   EVEX_W_0F3A50_P_2,
2253   EVEX_W_0F3A51_P_2,
2254   EVEX_W_0F3A56_P_2,
2255   EVEX_W_0F3A57_P_2,
2256   EVEX_W_0F3A66_P_2,
2257   EVEX_W_0F3A67_P_2,
2258   EVEX_W_0F3A70_P_2,
2259   EVEX_W_0F3A71_P_2,
2260   EVEX_W_0F3A72_P_2,
2261   EVEX_W_0F3A73_P_2,
2262   EVEX_W_0F3ACE_P_2,
2263   EVEX_W_0F3ACF_P_2
2264 };
2265
2266 typedef void (*op_rtn) (int bytemode, int sizeflag);
2267
2268 struct dis386 {
2269   const char *name;
2270   struct
2271     {
2272       op_rtn rtn;
2273       int bytemode;
2274     } op[MAX_OPERANDS];
2275   unsigned int prefix_requirement;
2276 };
2277
2278 /* Upper case letters in the instruction names here are macros.
2279    'A' => print 'b' if no register operands or suffix_always is true
2280    'B' => print 'b' if suffix_always is true
2281    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2282           size prefix
2283    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2284           suffix_always is true
2285    'E' => print 'e' if 32-bit form of jcxz
2286    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2287    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2288    'H' => print ",pt" or ",pn" branch hint
2289    'I' => honor following macro letter even in Intel mode (implemented only
2290           for some of the macro letters)
2291    'J' => print 'l'
2292    'K' => print 'd' or 'q' if rex prefix is present.
2293    'L' => print 'l' if suffix_always is true
2294    'M' => print 'r' if intel_mnemonic is false.
2295    'N' => print 'n' if instruction has no wait "prefix"
2296    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2297    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2298           or suffix_always is true.  print 'q' if rex prefix is present.
2299    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2300           is true
2301    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2302    'S' => print 'w', 'l' or 'q' if suffix_always is true
2303    'T' => print 'q' in 64bit mode if instruction has no operand size
2304           prefix and behave as 'P' otherwise
2305    'U' => print 'q' in 64bit mode if instruction has no operand size
2306           prefix and behave as 'Q' otherwise
2307    'V' => print 'q' in 64bit mode if instruction has no operand size
2308           prefix and behave as 'S' otherwise
2309    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2310    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2311    'Y' unused.
2312    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2313    '!' => change condition from true to false or from false to true.
2314    '%' => add 1 upper case letter to the macro.
2315    '^' => print 'w' or 'l' depending on operand size prefix or
2316           suffix_always is true (lcall/ljmp).
2317    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2318           on operand size prefix.
2319    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2320           has no operand size prefix for AMD64 ISA, behave as 'P'
2321           otherwise
2322
2323    2 upper case letter macros:
2324    "XY" => print 'x' or 'y' if suffix_always is true or no register
2325            operands and no broadcast.
2326    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2327            register operands and no broadcast.
2328    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2329    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2330            or suffix_always is true
2331    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2332    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2333    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2334    "LW" => print 'd', 'q' depending on the VEX.W bit
2335    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2336            an operand size prefix, or suffix_always is true.  print
2337            'q' if rex prefix is present.
2338
2339    Many of the above letters print nothing in Intel mode.  See "putop"
2340    for the details.
2341
2342    Braces '{' and '}', and vertical bars '|', indicate alternative
2343    mnemonic strings for AT&T and Intel.  */
2344
2345 static const struct dis386 dis386[] = {
2346   /* 00 */
2347   { "addB",             { Ebh1, Gb }, 0 },
2348   { "addS",             { Evh1, Gv }, 0 },
2349   { "addB",             { Gb, EbS }, 0 },
2350   { "addS",             { Gv, EvS }, 0 },
2351   { "addB",             { AL, Ib }, 0 },
2352   { "addS",             { eAX, Iv }, 0 },
2353   { X86_64_TABLE (X86_64_06) },
2354   { X86_64_TABLE (X86_64_07) },
2355   /* 08 */
2356   { "orB",              { Ebh1, Gb }, 0 },
2357   { "orS",              { Evh1, Gv }, 0 },
2358   { "orB",              { Gb, EbS }, 0 },
2359   { "orS",              { Gv, EvS }, 0 },
2360   { "orB",              { AL, Ib }, 0 },
2361   { "orS",              { eAX, Iv }, 0 },
2362   { X86_64_TABLE (X86_64_0D) },
2363   { Bad_Opcode },       /* 0x0f extended opcode escape */
2364   /* 10 */
2365   { "adcB",             { Ebh1, Gb }, 0 },
2366   { "adcS",             { Evh1, Gv }, 0 },
2367   { "adcB",             { Gb, EbS }, 0 },
2368   { "adcS",             { Gv, EvS }, 0 },
2369   { "adcB",             { AL, Ib }, 0 },
2370   { "adcS",             { eAX, Iv }, 0 },
2371   { X86_64_TABLE (X86_64_16) },
2372   { X86_64_TABLE (X86_64_17) },
2373   /* 18 */
2374   { "sbbB",             { Ebh1, Gb }, 0 },
2375   { "sbbS",             { Evh1, Gv }, 0 },
2376   { "sbbB",             { Gb, EbS }, 0 },
2377   { "sbbS",             { Gv, EvS }, 0 },
2378   { "sbbB",             { AL, Ib }, 0 },
2379   { "sbbS",             { eAX, Iv }, 0 },
2380   { X86_64_TABLE (X86_64_1E) },
2381   { X86_64_TABLE (X86_64_1F) },
2382   /* 20 */
2383   { "andB",             { Ebh1, Gb }, 0 },
2384   { "andS",             { Evh1, Gv }, 0 },
2385   { "andB",             { Gb, EbS }, 0 },
2386   { "andS",             { Gv, EvS }, 0 },
2387   { "andB",             { AL, Ib }, 0 },
2388   { "andS",             { eAX, Iv }, 0 },
2389   { Bad_Opcode },       /* SEG ES prefix */
2390   { X86_64_TABLE (X86_64_27) },
2391   /* 28 */
2392   { "subB",             { Ebh1, Gb }, 0 },
2393   { "subS",             { Evh1, Gv }, 0 },
2394   { "subB",             { Gb, EbS }, 0 },
2395   { "subS",             { Gv, EvS }, 0 },
2396   { "subB",             { AL, Ib }, 0 },
2397   { "subS",             { eAX, Iv }, 0 },
2398   { Bad_Opcode },       /* SEG CS prefix */
2399   { X86_64_TABLE (X86_64_2F) },
2400   /* 30 */
2401   { "xorB",             { Ebh1, Gb }, 0 },
2402   { "xorS",             { Evh1, Gv }, 0 },
2403   { "xorB",             { Gb, EbS }, 0 },
2404   { "xorS",             { Gv, EvS }, 0 },
2405   { "xorB",             { AL, Ib }, 0 },
2406   { "xorS",             { eAX, Iv }, 0 },
2407   { Bad_Opcode },       /* SEG SS prefix */
2408   { X86_64_TABLE (X86_64_37) },
2409   /* 38 */
2410   { "cmpB",             { Eb, Gb }, 0 },
2411   { "cmpS",             { Ev, Gv }, 0 },
2412   { "cmpB",             { Gb, EbS }, 0 },
2413   { "cmpS",             { Gv, EvS }, 0 },
2414   { "cmpB",             { AL, Ib }, 0 },
2415   { "cmpS",             { eAX, Iv }, 0 },
2416   { Bad_Opcode },       /* SEG DS prefix */
2417   { X86_64_TABLE (X86_64_3F) },
2418   /* 40 */
2419   { "inc{S|}",          { RMeAX }, 0 },
2420   { "inc{S|}",          { RMeCX }, 0 },
2421   { "inc{S|}",          { RMeDX }, 0 },
2422   { "inc{S|}",          { RMeBX }, 0 },
2423   { "inc{S|}",          { RMeSP }, 0 },
2424   { "inc{S|}",          { RMeBP }, 0 },
2425   { "inc{S|}",          { RMeSI }, 0 },
2426   { "inc{S|}",          { RMeDI }, 0 },
2427   /* 48 */
2428   { "dec{S|}",          { RMeAX }, 0 },
2429   { "dec{S|}",          { RMeCX }, 0 },
2430   { "dec{S|}",          { RMeDX }, 0 },
2431   { "dec{S|}",          { RMeBX }, 0 },
2432   { "dec{S|}",          { RMeSP }, 0 },
2433   { "dec{S|}",          { RMeBP }, 0 },
2434   { "dec{S|}",          { RMeSI }, 0 },
2435   { "dec{S|}",          { RMeDI }, 0 },
2436   /* 50 */
2437   { "pushV",            { RMrAX }, 0 },
2438   { "pushV",            { RMrCX }, 0 },
2439   { "pushV",            { RMrDX }, 0 },
2440   { "pushV",            { RMrBX }, 0 },
2441   { "pushV",            { RMrSP }, 0 },
2442   { "pushV",            { RMrBP }, 0 },
2443   { "pushV",            { RMrSI }, 0 },
2444   { "pushV",            { RMrDI }, 0 },
2445   /* 58 */
2446   { "popV",             { RMrAX }, 0 },
2447   { "popV",             { RMrCX }, 0 },
2448   { "popV",             { RMrDX }, 0 },
2449   { "popV",             { RMrBX }, 0 },
2450   { "popV",             { RMrSP }, 0 },
2451   { "popV",             { RMrBP }, 0 },
2452   { "popV",             { RMrSI }, 0 },
2453   { "popV",             { RMrDI }, 0 },
2454   /* 60 */
2455   { X86_64_TABLE (X86_64_60) },
2456   { X86_64_TABLE (X86_64_61) },
2457   { X86_64_TABLE (X86_64_62) },
2458   { X86_64_TABLE (X86_64_63) },
2459   { Bad_Opcode },       /* seg fs */
2460   { Bad_Opcode },       /* seg gs */
2461   { Bad_Opcode },       /* op size prefix */
2462   { Bad_Opcode },       /* adr size prefix */
2463   /* 68 */
2464   { "pushT",            { sIv }, 0 },
2465   { "imulS",            { Gv, Ev, Iv }, 0 },
2466   { "pushT",            { sIbT }, 0 },
2467   { "imulS",            { Gv, Ev, sIb }, 0 },
2468   { "ins{b|}",          { Ybr, indirDX }, 0 },
2469   { X86_64_TABLE (X86_64_6D) },
2470   { "outs{b|}",         { indirDXr, Xb }, 0 },
2471   { X86_64_TABLE (X86_64_6F) },
2472   /* 70 */
2473   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2474   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2475   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2476   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2477   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2478   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2479   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2480   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2481   /* 78 */
2482   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2483   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2484   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2485   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2486   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2487   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2488   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2489   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2490   /* 80 */
2491   { REG_TABLE (REG_80) },
2492   { REG_TABLE (REG_81) },
2493   { X86_64_TABLE (X86_64_82) },
2494   { REG_TABLE (REG_83) },
2495   { "testB",            { Eb, Gb }, 0 },
2496   { "testS",            { Ev, Gv }, 0 },
2497   { "xchgB",            { Ebh2, Gb }, 0 },
2498   { "xchgS",            { Evh2, Gv }, 0 },
2499   /* 88 */
2500   { "movB",             { Ebh3, Gb }, 0 },
2501   { "movS",             { Evh3, Gv }, 0 },
2502   { "movB",             { Gb, EbS }, 0 },
2503   { "movS",             { Gv, EvS }, 0 },
2504   { "movD",             { Sv, Sw }, 0 },
2505   { MOD_TABLE (MOD_8D) },
2506   { "movD",             { Sw, Sv }, 0 },
2507   { REG_TABLE (REG_8F) },
2508   /* 90 */
2509   { PREFIX_TABLE (PREFIX_90) },
2510   { "xchgS",            { RMeCX, eAX }, 0 },
2511   { "xchgS",            { RMeDX, eAX }, 0 },
2512   { "xchgS",            { RMeBX, eAX }, 0 },
2513   { "xchgS",            { RMeSP, eAX }, 0 },
2514   { "xchgS",            { RMeBP, eAX }, 0 },
2515   { "xchgS",            { RMeSI, eAX }, 0 },
2516   { "xchgS",            { RMeDI, eAX }, 0 },
2517   /* 98 */
2518   { "cW{t|}R",          { XX }, 0 },
2519   { "cR{t|}O",          { XX }, 0 },
2520   { X86_64_TABLE (X86_64_9A) },
2521   { Bad_Opcode },       /* fwait */
2522   { "pushfT",           { XX }, 0 },
2523   { "popfT",            { XX }, 0 },
2524   { "sahf",             { XX }, 0 },
2525   { "lahf",             { XX }, 0 },
2526   /* a0 */
2527   { "mov%LB",           { AL, Ob }, 0 },
2528   { "mov%LS",           { eAX, Ov }, 0 },
2529   { "mov%LB",           { Ob, AL }, 0 },
2530   { "mov%LS",           { Ov, eAX }, 0 },
2531   { "movs{b|}",         { Ybr, Xb }, 0 },
2532   { "movs{R|}",         { Yvr, Xv }, 0 },
2533   { "cmps{b|}",         { Xb, Yb }, 0 },
2534   { "cmps{R|}",         { Xv, Yv }, 0 },
2535   /* a8 */
2536   { "testB",            { AL, Ib }, 0 },
2537   { "testS",            { eAX, Iv }, 0 },
2538   { "stosB",            { Ybr, AL }, 0 },
2539   { "stosS",            { Yvr, eAX }, 0 },
2540   { "lodsB",            { ALr, Xb }, 0 },
2541   { "lodsS",            { eAXr, Xv }, 0 },
2542   { "scasB",            { AL, Yb }, 0 },
2543   { "scasS",            { eAX, Yv }, 0 },
2544   /* b0 */
2545   { "movB",             { RMAL, Ib }, 0 },
2546   { "movB",             { RMCL, Ib }, 0 },
2547   { "movB",             { RMDL, Ib }, 0 },
2548   { "movB",             { RMBL, Ib }, 0 },
2549   { "movB",             { RMAH, Ib }, 0 },
2550   { "movB",             { RMCH, Ib }, 0 },
2551   { "movB",             { RMDH, Ib }, 0 },
2552   { "movB",             { RMBH, Ib }, 0 },
2553   /* b8 */
2554   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2555   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2556   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2557   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2558   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2559   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2560   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2561   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2562   /* c0 */
2563   { REG_TABLE (REG_C0) },
2564   { REG_TABLE (REG_C1) },
2565   { "retT",             { Iw, BND }, 0 },
2566   { "retT",             { BND }, 0 },
2567   { X86_64_TABLE (X86_64_C4) },
2568   { X86_64_TABLE (X86_64_C5) },
2569   { REG_TABLE (REG_C6) },
2570   { REG_TABLE (REG_C7) },
2571   /* c8 */
2572   { "enterT",           { Iw, Ib }, 0 },
2573   { "leaveT",           { XX }, 0 },
2574   { "Jret{|f}P",        { Iw }, 0 },
2575   { "Jret{|f}P",        { XX }, 0 },
2576   { "int3",             { XX }, 0 },
2577   { "int",              { Ib }, 0 },
2578   { X86_64_TABLE (X86_64_CE) },
2579   { "iret%LP",          { XX }, 0 },
2580   /* d0 */
2581   { REG_TABLE (REG_D0) },
2582   { REG_TABLE (REG_D1) },
2583   { REG_TABLE (REG_D2) },
2584   { REG_TABLE (REG_D3) },
2585   { X86_64_TABLE (X86_64_D4) },
2586   { X86_64_TABLE (X86_64_D5) },
2587   { Bad_Opcode },
2588   { "xlat",             { DSBX }, 0 },
2589   /* d8 */
2590   { FLOAT },
2591   { FLOAT },
2592   { FLOAT },
2593   { FLOAT },
2594   { FLOAT },
2595   { FLOAT },
2596   { FLOAT },
2597   { FLOAT },
2598   /* e0 */
2599   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2600   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2601   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2602   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2603   { "inB",              { AL, Ib }, 0 },
2604   { "inG",              { zAX, Ib }, 0 },
2605   { "outB",             { Ib, AL }, 0 },
2606   { "outG",             { Ib, zAX }, 0 },
2607   /* e8 */
2608   { X86_64_TABLE (X86_64_E8) },
2609   { X86_64_TABLE (X86_64_E9) },
2610   { X86_64_TABLE (X86_64_EA) },
2611   { "jmp",              { Jb, BND }, 0 },
2612   { "inB",              { AL, indirDX }, 0 },
2613   { "inG",              { zAX, indirDX }, 0 },
2614   { "outB",             { indirDX, AL }, 0 },
2615   { "outG",             { indirDX, zAX }, 0 },
2616   /* f0 */
2617   { Bad_Opcode },       /* lock prefix */
2618   { "icebp",            { XX }, 0 },
2619   { Bad_Opcode },       /* repne */
2620   { Bad_Opcode },       /* repz */
2621   { "hlt",              { XX }, 0 },
2622   { "cmc",              { XX }, 0 },
2623   { REG_TABLE (REG_F6) },
2624   { REG_TABLE (REG_F7) },
2625   /* f8 */
2626   { "clc",              { XX }, 0 },
2627   { "stc",              { XX }, 0 },
2628   { "cli",              { XX }, 0 },
2629   { "sti",              { XX }, 0 },
2630   { "cld",              { XX }, 0 },
2631   { "std",              { XX }, 0 },
2632   { REG_TABLE (REG_FE) },
2633   { REG_TABLE (REG_FF) },
2634 };
2635
2636 static const struct dis386 dis386_twobyte[] = {
2637   /* 00 */
2638   { REG_TABLE (REG_0F00 ) },
2639   { REG_TABLE (REG_0F01 ) },
2640   { "larS",             { Gv, Ew }, 0 },
2641   { "lslS",             { Gv, Ew }, 0 },
2642   { Bad_Opcode },
2643   { "syscall",          { XX }, 0 },
2644   { "clts",             { XX }, 0 },
2645   { "sysret%LP",                { XX }, 0 },
2646   /* 08 */
2647   { "invd",             { XX }, 0 },
2648   { PREFIX_TABLE (PREFIX_0F09) },
2649   { Bad_Opcode },
2650   { "ud2",              { XX }, 0 },
2651   { Bad_Opcode },
2652   { REG_TABLE (REG_0F0D) },
2653   { "femms",            { XX }, 0 },
2654   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2655   /* 10 */
2656   { PREFIX_TABLE (PREFIX_0F10) },
2657   { PREFIX_TABLE (PREFIX_0F11) },
2658   { PREFIX_TABLE (PREFIX_0F12) },
2659   { MOD_TABLE (MOD_0F13) },
2660   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2661   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2662   { PREFIX_TABLE (PREFIX_0F16) },
2663   { MOD_TABLE (MOD_0F17) },
2664   /* 18 */
2665   { REG_TABLE (REG_0F18) },
2666   { "nopQ",             { Ev }, 0 },
2667   { PREFIX_TABLE (PREFIX_0F1A) },
2668   { PREFIX_TABLE (PREFIX_0F1B) },
2669   { PREFIX_TABLE (PREFIX_0F1C) },
2670   { "nopQ",             { Ev }, 0 },
2671   { PREFIX_TABLE (PREFIX_0F1E) },
2672   { "nopQ",             { Ev }, 0 },
2673   /* 20 */
2674   { "movZ",             { Rm, Cm }, 0 },
2675   { "movZ",             { Rm, Dm }, 0 },
2676   { "movZ",             { Cm, Rm }, 0 },
2677   { "movZ",             { Dm, Rm }, 0 },
2678   { MOD_TABLE (MOD_0F24) },
2679   { Bad_Opcode },
2680   { MOD_TABLE (MOD_0F26) },
2681   { Bad_Opcode },
2682   /* 28 */
2683   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2684   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2685   { PREFIX_TABLE (PREFIX_0F2A) },
2686   { PREFIX_TABLE (PREFIX_0F2B) },
2687   { PREFIX_TABLE (PREFIX_0F2C) },
2688   { PREFIX_TABLE (PREFIX_0F2D) },
2689   { PREFIX_TABLE (PREFIX_0F2E) },
2690   { PREFIX_TABLE (PREFIX_0F2F) },
2691   /* 30 */
2692   { "wrmsr",            { XX }, 0 },
2693   { "rdtsc",            { XX }, 0 },
2694   { "rdmsr",            { XX }, 0 },
2695   { "rdpmc",            { XX }, 0 },
2696   { "sysenter",         { XX }, 0 },
2697   { "sysexit",          { XX }, 0 },
2698   { Bad_Opcode },
2699   { "getsec",           { XX }, 0 },
2700   /* 38 */
2701   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2702   { Bad_Opcode },
2703   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2704   { Bad_Opcode },
2705   { Bad_Opcode },
2706   { Bad_Opcode },
2707   { Bad_Opcode },
2708   { Bad_Opcode },
2709   /* 40 */
2710   { "cmovoS",           { Gv, Ev }, 0 },
2711   { "cmovnoS",          { Gv, Ev }, 0 },
2712   { "cmovbS",           { Gv, Ev }, 0 },
2713   { "cmovaeS",          { Gv, Ev }, 0 },
2714   { "cmoveS",           { Gv, Ev }, 0 },
2715   { "cmovneS",          { Gv, Ev }, 0 },
2716   { "cmovbeS",          { Gv, Ev }, 0 },
2717   { "cmovaS",           { Gv, Ev }, 0 },
2718   /* 48 */
2719   { "cmovsS",           { Gv, Ev }, 0 },
2720   { "cmovnsS",          { Gv, Ev }, 0 },
2721   { "cmovpS",           { Gv, Ev }, 0 },
2722   { "cmovnpS",          { Gv, Ev }, 0 },
2723   { "cmovlS",           { Gv, Ev }, 0 },
2724   { "cmovgeS",          { Gv, Ev }, 0 },
2725   { "cmovleS",          { Gv, Ev }, 0 },
2726   { "cmovgS",           { Gv, Ev }, 0 },
2727   /* 50 */
2728   { MOD_TABLE (MOD_0F51) },
2729   { PREFIX_TABLE (PREFIX_0F51) },
2730   { PREFIX_TABLE (PREFIX_0F52) },
2731   { PREFIX_TABLE (PREFIX_0F53) },
2732   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2733   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2734   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2735   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2736   /* 58 */
2737   { PREFIX_TABLE (PREFIX_0F58) },
2738   { PREFIX_TABLE (PREFIX_0F59) },
2739   { PREFIX_TABLE (PREFIX_0F5A) },
2740   { PREFIX_TABLE (PREFIX_0F5B) },
2741   { PREFIX_TABLE (PREFIX_0F5C) },
2742   { PREFIX_TABLE (PREFIX_0F5D) },
2743   { PREFIX_TABLE (PREFIX_0F5E) },
2744   { PREFIX_TABLE (PREFIX_0F5F) },
2745   /* 60 */
2746   { PREFIX_TABLE (PREFIX_0F60) },
2747   { PREFIX_TABLE (PREFIX_0F61) },
2748   { PREFIX_TABLE (PREFIX_0F62) },
2749   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2750   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2751   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2752   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2753   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2754   /* 68 */
2755   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2756   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2757   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2758   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2759   { PREFIX_TABLE (PREFIX_0F6C) },
2760   { PREFIX_TABLE (PREFIX_0F6D) },
2761   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2762   { PREFIX_TABLE (PREFIX_0F6F) },
2763   /* 70 */
2764   { PREFIX_TABLE (PREFIX_0F70) },
2765   { REG_TABLE (REG_0F71) },
2766   { REG_TABLE (REG_0F72) },
2767   { REG_TABLE (REG_0F73) },
2768   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2769   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2770   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2771   { "emms",             { XX }, PREFIX_OPCODE },
2772   /* 78 */
2773   { PREFIX_TABLE (PREFIX_0F78) },
2774   { PREFIX_TABLE (PREFIX_0F79) },
2775   { Bad_Opcode },
2776   { Bad_Opcode },
2777   { PREFIX_TABLE (PREFIX_0F7C) },
2778   { PREFIX_TABLE (PREFIX_0F7D) },
2779   { PREFIX_TABLE (PREFIX_0F7E) },
2780   { PREFIX_TABLE (PREFIX_0F7F) },
2781   /* 80 */
2782   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2783   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2784   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2785   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2786   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2787   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2788   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2789   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2790   /* 88 */
2791   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2792   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2793   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2794   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2795   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2796   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2797   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2798   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2799   /* 90 */
2800   { "seto",             { Eb }, 0 },
2801   { "setno",            { Eb }, 0 },
2802   { "setb",             { Eb }, 0 },
2803   { "setae",            { Eb }, 0 },
2804   { "sete",             { Eb }, 0 },
2805   { "setne",            { Eb }, 0 },
2806   { "setbe",            { Eb }, 0 },
2807   { "seta",             { Eb }, 0 },
2808   /* 98 */
2809   { "sets",             { Eb }, 0 },
2810   { "setns",            { Eb }, 0 },
2811   { "setp",             { Eb }, 0 },
2812   { "setnp",            { Eb }, 0 },
2813   { "setl",             { Eb }, 0 },
2814   { "setge",            { Eb }, 0 },
2815   { "setle",            { Eb }, 0 },
2816   { "setg",             { Eb }, 0 },
2817   /* a0 */
2818   { "pushT",            { fs }, 0 },
2819   { "popT",             { fs }, 0 },
2820   { "cpuid",            { XX }, 0 },
2821   { "btS",              { Ev, Gv }, 0 },
2822   { "shldS",            { Ev, Gv, Ib }, 0 },
2823   { "shldS",            { Ev, Gv, CL }, 0 },
2824   { REG_TABLE (REG_0FA6) },
2825   { REG_TABLE (REG_0FA7) },
2826   /* a8 */
2827   { "pushT",            { gs }, 0 },
2828   { "popT",             { gs }, 0 },
2829   { "rsm",              { XX }, 0 },
2830   { "btsS",             { Evh1, Gv }, 0 },
2831   { "shrdS",            { Ev, Gv, Ib }, 0 },
2832   { "shrdS",            { Ev, Gv, CL }, 0 },
2833   { REG_TABLE (REG_0FAE) },
2834   { "imulS",            { Gv, Ev }, 0 },
2835   /* b0 */
2836   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2837   { "cmpxchgS",         { Evh1, Gv }, 0 },
2838   { MOD_TABLE (MOD_0FB2) },
2839   { "btrS",             { Evh1, Gv }, 0 },
2840   { MOD_TABLE (MOD_0FB4) },
2841   { MOD_TABLE (MOD_0FB5) },
2842   { "movz{bR|x}",       { Gv, Eb }, 0 },
2843   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2844   /* b8 */
2845   { PREFIX_TABLE (PREFIX_0FB8) },
2846   { "ud1S",             { Gv, Ev }, 0 },
2847   { REG_TABLE (REG_0FBA) },
2848   { "btcS",             { Evh1, Gv }, 0 },
2849   { PREFIX_TABLE (PREFIX_0FBC) },
2850   { PREFIX_TABLE (PREFIX_0FBD) },
2851   { "movs{bR|x}",       { Gv, Eb }, 0 },
2852   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2853   /* c0 */
2854   { "xaddB",            { Ebh1, Gb }, 0 },
2855   { "xaddS",            { Evh1, Gv }, 0 },
2856   { PREFIX_TABLE (PREFIX_0FC2) },
2857   { MOD_TABLE (MOD_0FC3) },
2858   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2859   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2860   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2861   { REG_TABLE (REG_0FC7) },
2862   /* c8 */
2863   { "bswap",            { RMeAX }, 0 },
2864   { "bswap",            { RMeCX }, 0 },
2865   { "bswap",            { RMeDX }, 0 },
2866   { "bswap",            { RMeBX }, 0 },
2867   { "bswap",            { RMeSP }, 0 },
2868   { "bswap",            { RMeBP }, 0 },
2869   { "bswap",            { RMeSI }, 0 },
2870   { "bswap",            { RMeDI }, 0 },
2871   /* d0 */
2872   { PREFIX_TABLE (PREFIX_0FD0) },
2873   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2874   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2875   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2876   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2877   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2878   { PREFIX_TABLE (PREFIX_0FD6) },
2879   { MOD_TABLE (MOD_0FD7) },
2880   /* d8 */
2881   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2882   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2883   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2884   { "pand",             { MX, EM }, PREFIX_OPCODE },
2885   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2886   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2887   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2888   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2889   /* e0 */
2890   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2891   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2892   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2893   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2894   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2895   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2896   { PREFIX_TABLE (PREFIX_0FE6) },
2897   { PREFIX_TABLE (PREFIX_0FE7) },
2898   /* e8 */
2899   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2900   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2901   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2902   { "por",              { MX, EM }, PREFIX_OPCODE },
2903   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2904   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2905   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2906   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2907   /* f0 */
2908   { PREFIX_TABLE (PREFIX_0FF0) },
2909   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2910   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2911   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2912   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2913   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2914   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2915   { PREFIX_TABLE (PREFIX_0FF7) },
2916   /* f8 */
2917   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2918   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2919   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2920   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2921   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2922   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2923   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2924   { "ud0S",             { Gv, Ev }, 0 },
2925 };
2926
2927 static const unsigned char onebyte_has_modrm[256] = {
2928   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2929   /*       -------------------------------        */
2930   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2931   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2932   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2933   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2934   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2935   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2936   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2937   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2938   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2939   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2940   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2941   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2942   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2943   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2944   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2945   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2946   /*       -------------------------------        */
2947   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2948 };
2949
2950 static const unsigned char twobyte_has_modrm[256] = {
2951   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2952   /*       -------------------------------        */
2953   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2954   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2955   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2956   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2957   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2958   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2959   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2960   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2961   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2962   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2963   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2964   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2965   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2966   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2967   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2968   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2969   /*       -------------------------------        */
2970   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2971 };
2972
2973 static char obuf[100];
2974 static char *obufp;
2975 static char *mnemonicendp;
2976 static char scratchbuf[100];
2977 static unsigned char *start_codep;
2978 static unsigned char *insn_codep;
2979 static unsigned char *codep;
2980 static unsigned char *end_codep;
2981 static int last_lock_prefix;
2982 static int last_repz_prefix;
2983 static int last_repnz_prefix;
2984 static int last_data_prefix;
2985 static int last_addr_prefix;
2986 static int last_rex_prefix;
2987 static int last_seg_prefix;
2988 static int fwait_prefix;
2989 /* The active segment register prefix.  */
2990 static int active_seg_prefix;
2991 #define MAX_CODE_LENGTH 15
2992 /* We can up to 14 prefixes since the maximum instruction length is
2993    15bytes.  */
2994 static int all_prefixes[MAX_CODE_LENGTH - 1];
2995 static disassemble_info *the_info;
2996 static struct
2997   {
2998     int mod;
2999     int reg;
3000     int rm;
3001   }
3002 modrm;
3003 static unsigned char need_modrm;
3004 static struct
3005   {
3006     int scale;
3007     int index;
3008     int base;
3009   }
3010 sib;
3011 static struct
3012   {
3013     int register_specifier;
3014     int length;
3015     int prefix;
3016     int w;
3017     int evex;
3018     int r;
3019     int v;
3020     int mask_register_specifier;
3021     int zeroing;
3022     int ll;
3023     int b;
3024   }
3025 vex;
3026 static unsigned char need_vex;
3027 static unsigned char need_vex_reg;
3028 static unsigned char vex_w_done;
3029
3030 struct op
3031   {
3032     const char *name;
3033     unsigned int len;
3034   };
3035
3036 /* If we are accessing mod/rm/reg without need_modrm set, then the
3037    values are stale.  Hitting this abort likely indicates that you
3038    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3039 #define MODRM_CHECK  if (!need_modrm) abort ()
3040
3041 static const char **names64;
3042 static const char **names32;
3043 static const char **names16;
3044 static const char **names8;
3045 static const char **names8rex;
3046 static const char **names_seg;
3047 static const char *index64;
3048 static const char *index32;
3049 static const char **index16;
3050 static const char **names_bnd;
3051
3052 static const char *intel_names64[] = {
3053   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3054   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3055 };
3056 static const char *intel_names32[] = {
3057   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3058   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3059 };
3060 static const char *intel_names16[] = {
3061   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3062   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3063 };
3064 static const char *intel_names8[] = {
3065   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3066 };
3067 static const char *intel_names8rex[] = {
3068   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3069   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3070 };
3071 static const char *intel_names_seg[] = {
3072   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3073 };
3074 static const char *intel_index64 = "riz";
3075 static const char *intel_index32 = "eiz";
3076 static const char *intel_index16[] = {
3077   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3078 };
3079
3080 static const char *att_names64[] = {
3081   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3082   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3083 };
3084 static const char *att_names32[] = {
3085   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3086   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3087 };
3088 static const char *att_names16[] = {
3089   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3090   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3091 };
3092 static const char *att_names8[] = {
3093   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3094 };
3095 static const char *att_names8rex[] = {
3096   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3097   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3098 };
3099 static const char *att_names_seg[] = {
3100   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3101 };
3102 static const char *att_index64 = "%riz";
3103 static const char *att_index32 = "%eiz";
3104 static const char *att_index16[] = {
3105   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3106 };
3107
3108 static const char **names_mm;
3109 static const char *intel_names_mm[] = {
3110   "mm0", "mm1", "mm2", "mm3",
3111   "mm4", "mm5", "mm6", "mm7"
3112 };
3113 static const char *att_names_mm[] = {
3114   "%mm0", "%mm1", "%mm2", "%mm3",
3115   "%mm4", "%mm5", "%mm6", "%mm7"
3116 };
3117
3118 static const char *intel_names_bnd[] = {
3119   "bnd0", "bnd1", "bnd2", "bnd3"
3120 };
3121
3122 static const char *att_names_bnd[] = {
3123   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3124 };
3125
3126 static const char **names_xmm;
3127 static const char *intel_names_xmm[] = {
3128   "xmm0", "xmm1", "xmm2", "xmm3",
3129   "xmm4", "xmm5", "xmm6", "xmm7",
3130   "xmm8", "xmm9", "xmm10", "xmm11",
3131   "xmm12", "xmm13", "xmm14", "xmm15",
3132   "xmm16", "xmm17", "xmm18", "xmm19",
3133   "xmm20", "xmm21", "xmm22", "xmm23",
3134   "xmm24", "xmm25", "xmm26", "xmm27",
3135   "xmm28", "xmm29", "xmm30", "xmm31"
3136 };
3137 static const char *att_names_xmm[] = {
3138   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3139   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3140   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3141   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3142   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3143   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3144   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3145   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3146 };
3147
3148 static const char **names_ymm;
3149 static const char *intel_names_ymm[] = {
3150   "ymm0", "ymm1", "ymm2", "ymm3",
3151   "ymm4", "ymm5", "ymm6", "ymm7",
3152   "ymm8", "ymm9", "ymm10", "ymm11",
3153   "ymm12", "ymm13", "ymm14", "ymm15",
3154   "ymm16", "ymm17", "ymm18", "ymm19",
3155   "ymm20", "ymm21", "ymm22", "ymm23",
3156   "ymm24", "ymm25", "ymm26", "ymm27",
3157   "ymm28", "ymm29", "ymm30", "ymm31"
3158 };
3159 static const char *att_names_ymm[] = {
3160   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3161   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3162   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3163   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3164   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3165   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3166   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3167   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3168 };
3169
3170 static const char **names_zmm;
3171 static const char *intel_names_zmm[] = {
3172   "zmm0", "zmm1", "zmm2", "zmm3",
3173   "zmm4", "zmm5", "zmm6", "zmm7",
3174   "zmm8", "zmm9", "zmm10", "zmm11",
3175   "zmm12", "zmm13", "zmm14", "zmm15",
3176   "zmm16", "zmm17", "zmm18", "zmm19",
3177   "zmm20", "zmm21", "zmm22", "zmm23",
3178   "zmm24", "zmm25", "zmm26", "zmm27",
3179   "zmm28", "zmm29", "zmm30", "zmm31"
3180 };
3181 static const char *att_names_zmm[] = {
3182   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3183   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3184   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3185   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3186   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3187   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3188   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3189   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3190 };
3191
3192 static const char **names_mask;
3193 static const char *intel_names_mask[] = {
3194   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3195 };
3196 static const char *att_names_mask[] = {
3197   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3198 };
3199
3200 static const char *names_rounding[] =
3201 {
3202   "{rn-sae}",
3203   "{rd-sae}",
3204   "{ru-sae}",
3205   "{rz-sae}"
3206 };
3207
3208 static const struct dis386 reg_table[][8] = {
3209   /* REG_80 */
3210   {
3211     { "addA",   { Ebh1, Ib }, 0 },
3212     { "orA",    { Ebh1, Ib }, 0 },
3213     { "adcA",   { Ebh1, Ib }, 0 },
3214     { "sbbA",   { Ebh1, Ib }, 0 },
3215     { "andA",   { Ebh1, Ib }, 0 },
3216     { "subA",   { Ebh1, Ib }, 0 },
3217     { "xorA",   { Ebh1, Ib }, 0 },
3218     { "cmpA",   { Eb, Ib }, 0 },
3219   },
3220   /* REG_81 */
3221   {
3222     { "addQ",   { Evh1, Iv }, 0 },
3223     { "orQ",    { Evh1, Iv }, 0 },
3224     { "adcQ",   { Evh1, Iv }, 0 },
3225     { "sbbQ",   { Evh1, Iv }, 0 },
3226     { "andQ",   { Evh1, Iv }, 0 },
3227     { "subQ",   { Evh1, Iv }, 0 },
3228     { "xorQ",   { Evh1, Iv }, 0 },
3229     { "cmpQ",   { Ev, Iv }, 0 },
3230   },
3231   /* REG_83 */
3232   {
3233     { "addQ",   { Evh1, sIb }, 0 },
3234     { "orQ",    { Evh1, sIb }, 0 },
3235     { "adcQ",   { Evh1, sIb }, 0 },
3236     { "sbbQ",   { Evh1, sIb }, 0 },
3237     { "andQ",   { Evh1, sIb }, 0 },
3238     { "subQ",   { Evh1, sIb }, 0 },
3239     { "xorQ",   { Evh1, sIb }, 0 },
3240     { "cmpQ",   { Ev, sIb }, 0 },
3241   },
3242   /* REG_8F */
3243   {
3244     { "popU",   { stackEv }, 0 },
3245     { XOP_8F_TABLE (XOP_09) },
3246     { Bad_Opcode },
3247     { Bad_Opcode },
3248     { Bad_Opcode },
3249     { XOP_8F_TABLE (XOP_09) },
3250   },
3251   /* REG_C0 */
3252   {
3253     { "rolA",   { Eb, Ib }, 0 },
3254     { "rorA",   { Eb, Ib }, 0 },
3255     { "rclA",   { Eb, Ib }, 0 },
3256     { "rcrA",   { Eb, Ib }, 0 },
3257     { "shlA",   { Eb, Ib }, 0 },
3258     { "shrA",   { Eb, Ib }, 0 },
3259     { "shlA",   { Eb, Ib }, 0 },
3260     { "sarA",   { Eb, Ib }, 0 },
3261   },
3262   /* REG_C1 */
3263   {
3264     { "rolQ",   { Ev, Ib }, 0 },
3265     { "rorQ",   { Ev, Ib }, 0 },
3266     { "rclQ",   { Ev, Ib }, 0 },
3267     { "rcrQ",   { Ev, Ib }, 0 },
3268     { "shlQ",   { Ev, Ib }, 0 },
3269     { "shrQ",   { Ev, Ib }, 0 },
3270     { "shlQ",   { Ev, Ib }, 0 },
3271     { "sarQ",   { Ev, Ib }, 0 },
3272   },
3273   /* REG_C6 */
3274   {
3275     { "movA",   { Ebh3, Ib }, 0 },
3276     { Bad_Opcode },
3277     { Bad_Opcode },
3278     { Bad_Opcode },
3279     { Bad_Opcode },
3280     { Bad_Opcode },
3281     { Bad_Opcode },
3282     { MOD_TABLE (MOD_C6_REG_7) },
3283   },
3284   /* REG_C7 */
3285   {
3286     { "movQ",   { Evh3, Iv }, 0 },
3287     { Bad_Opcode },
3288     { Bad_Opcode },
3289     { Bad_Opcode },
3290     { Bad_Opcode },
3291     { Bad_Opcode },
3292     { Bad_Opcode },
3293     { MOD_TABLE (MOD_C7_REG_7) },
3294   },
3295   /* REG_D0 */
3296   {
3297     { "rolA",   { Eb, I1 }, 0 },
3298     { "rorA",   { Eb, I1 }, 0 },
3299     { "rclA",   { Eb, I1 }, 0 },
3300     { "rcrA",   { Eb, I1 }, 0 },
3301     { "shlA",   { Eb, I1 }, 0 },
3302     { "shrA",   { Eb, I1 }, 0 },
3303     { "shlA",   { Eb, I1 }, 0 },
3304     { "sarA",   { Eb, I1 }, 0 },
3305   },
3306   /* REG_D1 */
3307   {
3308     { "rolQ",   { Ev, I1 }, 0 },
3309     { "rorQ",   { Ev, I1 }, 0 },
3310     { "rclQ",   { Ev, I1 }, 0 },
3311     { "rcrQ",   { Ev, I1 }, 0 },
3312     { "shlQ",   { Ev, I1 }, 0 },
3313     { "shrQ",   { Ev, I1 }, 0 },
3314     { "shlQ",   { Ev, I1 }, 0 },
3315     { "sarQ",   { Ev, I1 }, 0 },
3316   },
3317   /* REG_D2 */
3318   {
3319     { "rolA",   { Eb, CL }, 0 },
3320     { "rorA",   { Eb, CL }, 0 },
3321     { "rclA",   { Eb, CL }, 0 },
3322     { "rcrA",   { Eb, CL }, 0 },
3323     { "shlA",   { Eb, CL }, 0 },
3324     { "shrA",   { Eb, CL }, 0 },
3325     { "shlA",   { Eb, CL }, 0 },
3326     { "sarA",   { Eb, CL }, 0 },
3327   },
3328   /* REG_D3 */
3329   {
3330     { "rolQ",   { Ev, CL }, 0 },
3331     { "rorQ",   { Ev, CL }, 0 },
3332     { "rclQ",   { Ev, CL }, 0 },
3333     { "rcrQ",   { Ev, CL }, 0 },
3334     { "shlQ",   { Ev, CL }, 0 },
3335     { "shrQ",   { Ev, CL }, 0 },
3336     { "shlQ",   { Ev, CL }, 0 },
3337     { "sarQ",   { Ev, CL }, 0 },
3338   },
3339   /* REG_F6 */
3340   {
3341     { "testA",  { Eb, Ib }, 0 },
3342     { "testA",  { Eb, Ib }, 0 },
3343     { "notA",   { Ebh1 }, 0 },
3344     { "negA",   { Ebh1 }, 0 },
3345     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3346     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3347     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3348     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3349   },
3350   /* REG_F7 */
3351   {
3352     { "testQ",  { Ev, Iv }, 0 },
3353     { "testQ",  { Ev, Iv }, 0 },
3354     { "notQ",   { Evh1 }, 0 },
3355     { "negQ",   { Evh1 }, 0 },
3356     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3357     { "imulQ",  { Ev }, 0 },
3358     { "divQ",   { Ev }, 0 },
3359     { "idivQ",  { Ev }, 0 },
3360   },
3361   /* REG_FE */
3362   {
3363     { "incA",   { Ebh1 }, 0 },
3364     { "decA",   { Ebh1 }, 0 },
3365   },
3366   /* REG_FF */
3367   {
3368     { "incQ",   { Evh1 }, 0 },
3369     { "decQ",   { Evh1 }, 0 },
3370     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3371     { MOD_TABLE (MOD_FF_REG_3) },
3372     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3373     { MOD_TABLE (MOD_FF_REG_5) },
3374     { "pushU",  { stackEv }, 0 },
3375     { Bad_Opcode },
3376   },
3377   /* REG_0F00 */
3378   {
3379     { "sldtD",  { Sv }, 0 },
3380     { "strD",   { Sv }, 0 },
3381     { "lldt",   { Ew }, 0 },
3382     { "ltr",    { Ew }, 0 },
3383     { "verr",   { Ew }, 0 },
3384     { "verw",   { Ew }, 0 },
3385     { Bad_Opcode },
3386     { Bad_Opcode },
3387   },
3388   /* REG_0F01 */
3389   {
3390     { MOD_TABLE (MOD_0F01_REG_0) },
3391     { MOD_TABLE (MOD_0F01_REG_1) },
3392     { MOD_TABLE (MOD_0F01_REG_2) },
3393     { MOD_TABLE (MOD_0F01_REG_3) },
3394     { "smswD",  { Sv }, 0 },
3395     { MOD_TABLE (MOD_0F01_REG_5) },
3396     { "lmsw",   { Ew }, 0 },
3397     { MOD_TABLE (MOD_0F01_REG_7) },
3398   },
3399   /* REG_0F0D */
3400   {
3401     { "prefetch",       { Mb }, 0 },
3402     { "prefetchw",      { Mb }, 0 },
3403     { "prefetchwt1",    { Mb }, 0 },
3404     { "prefetch",       { Mb }, 0 },
3405     { "prefetch",       { Mb }, 0 },
3406     { "prefetch",       { Mb }, 0 },
3407     { "prefetch",       { Mb }, 0 },
3408     { "prefetch",       { Mb }, 0 },
3409   },
3410   /* REG_0F18 */
3411   {
3412     { MOD_TABLE (MOD_0F18_REG_0) },
3413     { MOD_TABLE (MOD_0F18_REG_1) },
3414     { MOD_TABLE (MOD_0F18_REG_2) },
3415     { MOD_TABLE (MOD_0F18_REG_3) },
3416     { MOD_TABLE (MOD_0F18_REG_4) },
3417     { MOD_TABLE (MOD_0F18_REG_5) },
3418     { MOD_TABLE (MOD_0F18_REG_6) },
3419     { MOD_TABLE (MOD_0F18_REG_7) },
3420   },
3421   /* REG_0F1C_MOD_0 */
3422   {
3423     { "cldemote",       { Mb }, 0 },
3424     { "nopQ",           { Ev }, 0 },
3425     { "nopQ",           { Ev }, 0 },
3426     { "nopQ",           { Ev }, 0 },
3427     { "nopQ",           { Ev }, 0 },
3428     { "nopQ",           { Ev }, 0 },
3429     { "nopQ",           { Ev }, 0 },
3430     { "nopQ",           { Ev }, 0 },
3431   },
3432   /* REG_0F1E_MOD_3 */
3433   {
3434     { "nopQ",           { Ev }, 0 },
3435     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3436     { "nopQ",           { Ev }, 0 },
3437     { "nopQ",           { Ev }, 0 },
3438     { "nopQ",           { Ev }, 0 },
3439     { "nopQ",           { Ev }, 0 },
3440     { "nopQ",           { Ev }, 0 },
3441     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3442   },
3443   /* REG_0F71 */
3444   {
3445     { Bad_Opcode },
3446     { Bad_Opcode },
3447     { MOD_TABLE (MOD_0F71_REG_2) },
3448     { Bad_Opcode },
3449     { MOD_TABLE (MOD_0F71_REG_4) },
3450     { Bad_Opcode },
3451     { MOD_TABLE (MOD_0F71_REG_6) },
3452   },
3453   /* REG_0F72 */
3454   {
3455     { Bad_Opcode },
3456     { Bad_Opcode },
3457     { MOD_TABLE (MOD_0F72_REG_2) },
3458     { Bad_Opcode },
3459     { MOD_TABLE (MOD_0F72_REG_4) },
3460     { Bad_Opcode },
3461     { MOD_TABLE (MOD_0F72_REG_6) },
3462   },
3463   /* REG_0F73 */
3464   {
3465     { Bad_Opcode },
3466     { Bad_Opcode },
3467     { MOD_TABLE (MOD_0F73_REG_2) },
3468     { MOD_TABLE (MOD_0F73_REG_3) },
3469     { Bad_Opcode },
3470     { Bad_Opcode },
3471     { MOD_TABLE (MOD_0F73_REG_6) },
3472     { MOD_TABLE (MOD_0F73_REG_7) },
3473   },
3474   /* REG_0FA6 */
3475   {
3476     { "montmul",        { { OP_0f07, 0 } }, 0 },
3477     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3478     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3479   },
3480   /* REG_0FA7 */
3481   {
3482     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3483     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3484     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3485     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3486     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3487     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3488   },
3489   /* REG_0FAE */
3490   {
3491     { MOD_TABLE (MOD_0FAE_REG_0) },
3492     { MOD_TABLE (MOD_0FAE_REG_1) },
3493     { MOD_TABLE (MOD_0FAE_REG_2) },
3494     { MOD_TABLE (MOD_0FAE_REG_3) },
3495     { MOD_TABLE (MOD_0FAE_REG_4) },
3496     { MOD_TABLE (MOD_0FAE_REG_5) },
3497     { MOD_TABLE (MOD_0FAE_REG_6) },
3498     { MOD_TABLE (MOD_0FAE_REG_7) },
3499   },
3500   /* REG_0FBA */
3501   {
3502     { Bad_Opcode },
3503     { Bad_Opcode },
3504     { Bad_Opcode },
3505     { Bad_Opcode },
3506     { "btQ",    { Ev, Ib }, 0 },
3507     { "btsQ",   { Evh1, Ib }, 0 },
3508     { "btrQ",   { Evh1, Ib }, 0 },
3509     { "btcQ",   { Evh1, Ib }, 0 },
3510   },
3511   /* REG_0FC7 */
3512   {
3513     { Bad_Opcode },
3514     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3515     { Bad_Opcode },
3516     { MOD_TABLE (MOD_0FC7_REG_3) },
3517     { MOD_TABLE (MOD_0FC7_REG_4) },
3518     { MOD_TABLE (MOD_0FC7_REG_5) },
3519     { MOD_TABLE (MOD_0FC7_REG_6) },
3520     { MOD_TABLE (MOD_0FC7_REG_7) },
3521   },
3522   /* REG_VEX_0F71 */
3523   {
3524     { Bad_Opcode },
3525     { Bad_Opcode },
3526     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3527     { Bad_Opcode },
3528     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3529     { Bad_Opcode },
3530     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3531   },
3532   /* REG_VEX_0F72 */
3533   {
3534     { Bad_Opcode },
3535     { Bad_Opcode },
3536     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3537     { Bad_Opcode },
3538     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3539     { Bad_Opcode },
3540     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3541   },
3542   /* REG_VEX_0F73 */
3543   {
3544     { Bad_Opcode },
3545     { Bad_Opcode },
3546     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3547     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3548     { Bad_Opcode },
3549     { Bad_Opcode },
3550     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3551     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3552   },
3553   /* REG_VEX_0FAE */
3554   {
3555     { Bad_Opcode },
3556     { Bad_Opcode },
3557     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3558     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3559   },
3560   /* REG_VEX_0F38F3 */
3561   {
3562     { Bad_Opcode },
3563     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3564     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3565     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3566   },
3567   /* REG_XOP_LWPCB */
3568   {
3569     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3570     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3571   },
3572   /* REG_XOP_LWP */
3573   {
3574     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3575     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3576   },
3577   /* REG_XOP_TBM_01 */
3578   {
3579     { Bad_Opcode },
3580     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3581     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3582     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3583     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3584     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3585     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3586     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3587   },
3588   /* REG_XOP_TBM_02 */
3589   {
3590     { Bad_Opcode },
3591     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3592     { Bad_Opcode },
3593     { Bad_Opcode },
3594     { Bad_Opcode },
3595     { Bad_Opcode },
3596     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3597   },
3598 #define NEED_REG_TABLE
3599 #include "i386-dis-evex.h"
3600 #undef NEED_REG_TABLE
3601 };
3602
3603 static const struct dis386 prefix_table[][4] = {
3604   /* PREFIX_90 */
3605   {
3606     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3607     { "pause", { XX }, 0 },
3608     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3609     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3610   },
3611
3612   /* PREFIX_MOD_0_0F01_REG_5 */
3613   {
3614     { Bad_Opcode },
3615     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3616   },
3617
3618   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3619   {
3620     { Bad_Opcode },
3621     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3622   },
3623
3624   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3625   {
3626     { Bad_Opcode },
3627     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3628   },
3629
3630   /* PREFIX_0F09 */
3631   {
3632     { "wbinvd",   { XX }, 0 },
3633     { "wbnoinvd", { XX }, 0 },
3634   },
3635
3636   /* PREFIX_0F10 */
3637   {
3638     { "movups", { XM, EXx }, PREFIX_OPCODE },
3639     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3640     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3641     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3642   },
3643
3644   /* PREFIX_0F11 */
3645   {
3646     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3647     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3648     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3649     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3650   },
3651
3652   /* PREFIX_0F12 */
3653   {
3654     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3655     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3656     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3657     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3658   },
3659
3660   /* PREFIX_0F16 */
3661   {
3662     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3663     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3664     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3665   },
3666
3667   /* PREFIX_0F1A */
3668   {
3669     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3670     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3671     { "bndmov", { Gbnd, Ebnd }, 0 },
3672     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3673   },
3674
3675   /* PREFIX_0F1B */
3676   {
3677     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3678     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3679     { "bndmov", { EbndS, Gbnd }, 0 },
3680     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3681   },
3682
3683   /* PREFIX_0F1C */
3684   {
3685     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3686     { "nopQ",   { Ev }, PREFIX_OPCODE },
3687     { "nopQ",   { Ev }, PREFIX_OPCODE },
3688     { "nopQ",   { Ev }, PREFIX_OPCODE },
3689   },
3690
3691   /* PREFIX_0F1E */
3692   {
3693     { "nopQ",   { Ev }, PREFIX_OPCODE },
3694     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3695     { "nopQ",   { Ev }, PREFIX_OPCODE },
3696     { "nopQ",   { Ev }, PREFIX_OPCODE },
3697   },
3698
3699   /* PREFIX_0F2A */
3700   {
3701     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3702     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3703     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3704     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3705   },
3706
3707   /* PREFIX_0F2B */
3708   {
3709     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3710     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3711     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3712     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3713   },
3714
3715   /* PREFIX_0F2C */
3716   {
3717     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3718     { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3719     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3720     { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3721   },
3722
3723   /* PREFIX_0F2D */
3724   {
3725     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3726     { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3727     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3728     { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3729   },
3730
3731   /* PREFIX_0F2E */
3732   {
3733     { "ucomiss",{ XM, EXd }, 0 },
3734     { Bad_Opcode },
3735     { "ucomisd",{ XM, EXq }, 0 },
3736   },
3737
3738   /* PREFIX_0F2F */
3739   {
3740     { "comiss", { XM, EXd }, 0 },
3741     { Bad_Opcode },
3742     { "comisd", { XM, EXq }, 0 },
3743   },
3744
3745   /* PREFIX_0F51 */
3746   {
3747     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3748     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3749     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3750     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3751   },
3752
3753   /* PREFIX_0F52 */
3754   {
3755     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3756     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3757   },
3758
3759   /* PREFIX_0F53 */
3760   {
3761     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3762     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3763   },
3764
3765   /* PREFIX_0F58 */
3766   {
3767     { "addps", { XM, EXx }, PREFIX_OPCODE },
3768     { "addss", { XM, EXd }, PREFIX_OPCODE },
3769     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3770     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3771   },
3772
3773   /* PREFIX_0F59 */
3774   {
3775     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3776     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3777     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3778     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3779   },
3780
3781   /* PREFIX_0F5A */
3782   {
3783     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3784     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3785     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3786     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3787   },
3788
3789   /* PREFIX_0F5B */
3790   {
3791     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3792     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3793     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3794   },
3795
3796   /* PREFIX_0F5C */
3797   {
3798     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3799     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3800     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3801     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3802   },
3803
3804   /* PREFIX_0F5D */
3805   {
3806     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3807     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3808     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3809     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3810   },
3811
3812   /* PREFIX_0F5E */
3813   {
3814     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3815     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3816     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3817     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3818   },
3819
3820   /* PREFIX_0F5F */
3821   {
3822     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3823     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3824     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3825     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3826   },
3827
3828   /* PREFIX_0F60 */
3829   {
3830     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3831     { Bad_Opcode },
3832     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3833   },
3834
3835   /* PREFIX_0F61 */
3836   {
3837     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3838     { Bad_Opcode },
3839     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3840   },
3841
3842   /* PREFIX_0F62 */
3843   {
3844     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3845     { Bad_Opcode },
3846     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3847   },
3848
3849   /* PREFIX_0F6C */
3850   {
3851     { Bad_Opcode },
3852     { Bad_Opcode },
3853     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3854   },
3855
3856   /* PREFIX_0F6D */
3857   {
3858     { Bad_Opcode },
3859     { Bad_Opcode },
3860     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3861   },
3862
3863   /* PREFIX_0F6F */
3864   {
3865     { "movq",   { MX, EM }, PREFIX_OPCODE },
3866     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3867     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3868   },
3869
3870   /* PREFIX_0F70 */
3871   {
3872     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3873     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3874     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3875     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3876   },
3877
3878   /* PREFIX_0F73_REG_3 */
3879   {
3880     { Bad_Opcode },
3881     { Bad_Opcode },
3882     { "psrldq", { XS, Ib }, 0 },
3883   },
3884
3885   /* PREFIX_0F73_REG_7 */
3886   {
3887     { Bad_Opcode },
3888     { Bad_Opcode },
3889     { "pslldq", { XS, Ib }, 0 },
3890   },
3891
3892   /* PREFIX_0F78 */
3893   {
3894     {"vmread",  { Em, Gm }, 0 },
3895     { Bad_Opcode },
3896     {"extrq",   { XS, Ib, Ib }, 0 },
3897     {"insertq", { XM, XS, Ib, Ib }, 0 },
3898   },
3899
3900   /* PREFIX_0F79 */
3901   {
3902     {"vmwrite", { Gm, Em }, 0 },
3903     { Bad_Opcode },
3904     {"extrq",   { XM, XS }, 0 },
3905     {"insertq", { XM, XS }, 0 },
3906   },
3907
3908   /* PREFIX_0F7C */
3909   {
3910     { Bad_Opcode },
3911     { Bad_Opcode },
3912     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3913     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3914   },
3915
3916   /* PREFIX_0F7D */
3917   {
3918     { Bad_Opcode },
3919     { Bad_Opcode },
3920     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3921     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3922   },
3923
3924   /* PREFIX_0F7E */
3925   {
3926     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3927     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3928     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3929   },
3930
3931   /* PREFIX_0F7F */
3932   {
3933     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3934     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3935     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3936   },
3937
3938   /* PREFIX_0FAE_REG_0 */
3939   {
3940     { Bad_Opcode },
3941     { "rdfsbase", { Ev }, 0 },
3942   },
3943
3944   /* PREFIX_0FAE_REG_1 */
3945   {
3946     { Bad_Opcode },
3947     { "rdgsbase", { Ev }, 0 },
3948   },
3949
3950   /* PREFIX_0FAE_REG_2 */
3951   {
3952     { Bad_Opcode },
3953     { "wrfsbase", { Ev }, 0 },
3954   },
3955
3956   /* PREFIX_0FAE_REG_3 */
3957   {
3958     { Bad_Opcode },
3959     { "wrgsbase", { Ev }, 0 },
3960   },
3961
3962   /* PREFIX_MOD_0_0FAE_REG_4 */
3963   {
3964     { "xsave",  { FXSAVE }, 0 },
3965     { "ptwrite%LQ", { Edq }, 0 },
3966   },
3967
3968   /* PREFIX_MOD_3_0FAE_REG_4 */
3969   {
3970     { Bad_Opcode },
3971     { "ptwrite%LQ", { Edq }, 0 },
3972   },
3973
3974   /* PREFIX_MOD_0_0FAE_REG_5 */
3975   {
3976     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3977   },
3978
3979   /* PREFIX_MOD_3_0FAE_REG_5 */
3980   {
3981     { "lfence",         { Skip_MODRM }, 0 },
3982     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3983   },
3984
3985   /* PREFIX_MOD_0_0FAE_REG_6 */
3986   {
3987     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3988     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3989     { "clwb",   { Mb }, PREFIX_OPCODE },
3990   },
3991
3992   /* PREFIX_MOD_1_0FAE_REG_6 */
3993   {
3994     { RM_TABLE (RM_0FAE_REG_6) },
3995     { "umonitor",       { Eva }, PREFIX_OPCODE },
3996     { "tpause", { Edq }, PREFIX_OPCODE },
3997     { "umwait", { Edq }, PREFIX_OPCODE },
3998   },
3999
4000   /* PREFIX_0FAE_REG_7 */
4001   {
4002     { "clflush",        { Mb }, 0 },
4003     { Bad_Opcode },
4004     { "clflushopt",     { Mb }, 0 },
4005   },
4006
4007   /* PREFIX_0FB8 */
4008   {
4009     { Bad_Opcode },
4010     { "popcntS", { Gv, Ev }, 0 },
4011   },
4012
4013   /* PREFIX_0FBC */
4014   {
4015     { "bsfS",   { Gv, Ev }, 0 },
4016     { "tzcntS", { Gv, Ev }, 0 },
4017     { "bsfS",   { Gv, Ev }, 0 },
4018   },
4019
4020   /* PREFIX_0FBD */
4021   {
4022     { "bsrS",   { Gv, Ev }, 0 },
4023     { "lzcntS", { Gv, Ev }, 0 },
4024     { "bsrS",   { Gv, Ev }, 0 },
4025   },
4026
4027   /* PREFIX_0FC2 */
4028   {
4029     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4030     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4031     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4032     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4033   },
4034
4035   /* PREFIX_MOD_0_0FC3 */
4036   {
4037     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4038   },
4039
4040   /* PREFIX_MOD_0_0FC7_REG_6 */
4041   {
4042     { "vmptrld",{ Mq }, 0 },
4043     { "vmxon",  { Mq }, 0 },
4044     { "vmclear",{ Mq }, 0 },
4045   },
4046
4047   /* PREFIX_MOD_3_0FC7_REG_6 */
4048   {
4049     { "rdrand", { Ev }, 0 },
4050     { Bad_Opcode },
4051     { "rdrand", { Ev }, 0 }
4052   },
4053
4054   /* PREFIX_MOD_3_0FC7_REG_7 */
4055   {
4056     { "rdseed", { Ev }, 0 },
4057     { "rdpid",  { Em }, 0 },
4058     { "rdseed", { Ev }, 0 },
4059   },
4060
4061   /* PREFIX_0FD0 */
4062   {
4063     { Bad_Opcode },
4064     { Bad_Opcode },
4065     { "addsubpd", { XM, EXx }, 0 },
4066     { "addsubps", { XM, EXx }, 0 },
4067   },
4068
4069   /* PREFIX_0FD6 */
4070   {
4071     { Bad_Opcode },
4072     { "movq2dq",{ XM, MS }, 0 },
4073     { "movq",   { EXqS, XM }, 0 },
4074     { "movdq2q",{ MX, XS }, 0 },
4075   },
4076
4077   /* PREFIX_0FE6 */
4078   {
4079     { Bad_Opcode },
4080     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4081     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4082     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4083   },
4084
4085   /* PREFIX_0FE7 */
4086   {
4087     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4088     { Bad_Opcode },
4089     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4090   },
4091
4092   /* PREFIX_0FF0 */
4093   {
4094     { Bad_Opcode },
4095     { Bad_Opcode },
4096     { Bad_Opcode },
4097     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4098   },
4099
4100   /* PREFIX_0FF7 */
4101   {
4102     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4103     { Bad_Opcode },
4104     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4105   },
4106
4107   /* PREFIX_0F3810 */
4108   {
4109     { Bad_Opcode },
4110     { Bad_Opcode },
4111     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4112   },
4113
4114   /* PREFIX_0F3814 */
4115   {
4116     { Bad_Opcode },
4117     { Bad_Opcode },
4118     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4119   },
4120
4121   /* PREFIX_0F3815 */
4122   {
4123     { Bad_Opcode },
4124     { Bad_Opcode },
4125     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4126   },
4127
4128   /* PREFIX_0F3817 */
4129   {
4130     { Bad_Opcode },
4131     { Bad_Opcode },
4132     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4133   },
4134
4135   /* PREFIX_0F3820 */
4136   {
4137     { Bad_Opcode },
4138     { Bad_Opcode },
4139     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4140   },
4141
4142   /* PREFIX_0F3821 */
4143   {
4144     { Bad_Opcode },
4145     { Bad_Opcode },
4146     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4147   },
4148
4149   /* PREFIX_0F3822 */
4150   {
4151     { Bad_Opcode },
4152     { Bad_Opcode },
4153     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4154   },
4155
4156   /* PREFIX_0F3823 */
4157   {
4158     { Bad_Opcode },
4159     { Bad_Opcode },
4160     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4161   },
4162
4163   /* PREFIX_0F3824 */
4164   {
4165     { Bad_Opcode },
4166     { Bad_Opcode },
4167     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4168   },
4169
4170   /* PREFIX_0F3825 */
4171   {
4172     { Bad_Opcode },
4173     { Bad_Opcode },
4174     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4175   },
4176
4177   /* PREFIX_0F3828 */
4178   {
4179     { Bad_Opcode },
4180     { Bad_Opcode },
4181     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4182   },
4183
4184   /* PREFIX_0F3829 */
4185   {
4186     { Bad_Opcode },
4187     { Bad_Opcode },
4188     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4189   },
4190
4191   /* PREFIX_0F382A */
4192   {
4193     { Bad_Opcode },
4194     { Bad_Opcode },
4195     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4196   },
4197
4198   /* PREFIX_0F382B */
4199   {
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4203   },
4204
4205   /* PREFIX_0F3830 */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4210   },
4211
4212   /* PREFIX_0F3831 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4217   },
4218
4219   /* PREFIX_0F3832 */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4224   },
4225
4226   /* PREFIX_0F3833 */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4231   },
4232
4233   /* PREFIX_0F3834 */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4238   },
4239
4240   /* PREFIX_0F3835 */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4245   },
4246
4247   /* PREFIX_0F3837 */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4252   },
4253
4254   /* PREFIX_0F3838 */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4259   },
4260
4261   /* PREFIX_0F3839 */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4266   },
4267
4268   /* PREFIX_0F383A */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4273   },
4274
4275   /* PREFIX_0F383B */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4280   },
4281
4282   /* PREFIX_0F383C */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4287   },
4288
4289   /* PREFIX_0F383D */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4294   },
4295
4296   /* PREFIX_0F383E */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4301   },
4302
4303   /* PREFIX_0F383F */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4308   },
4309
4310   /* PREFIX_0F3840 */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4315   },
4316
4317   /* PREFIX_0F3841 */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4322   },
4323
4324   /* PREFIX_0F3880 */
4325   {
4326     { Bad_Opcode },
4327     { Bad_Opcode },
4328     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4329   },
4330
4331   /* PREFIX_0F3881 */
4332   {
4333     { Bad_Opcode },
4334     { Bad_Opcode },
4335     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4336   },
4337
4338   /* PREFIX_0F3882 */
4339   {
4340     { Bad_Opcode },
4341     { Bad_Opcode },
4342     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4343   },
4344
4345   /* PREFIX_0F38C8 */
4346   {
4347     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4348   },
4349
4350   /* PREFIX_0F38C9 */
4351   {
4352     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4353   },
4354
4355   /* PREFIX_0F38CA */
4356   {
4357     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4358   },
4359
4360   /* PREFIX_0F38CB */
4361   {
4362     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4363   },
4364
4365   /* PREFIX_0F38CC */
4366   {
4367     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4368   },
4369
4370   /* PREFIX_0F38CD */
4371   {
4372     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4373   },
4374
4375   /* PREFIX_0F38CF */
4376   {
4377     { Bad_Opcode },
4378     { Bad_Opcode },
4379     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4380   },
4381
4382   /* PREFIX_0F38DB */
4383   {
4384     { Bad_Opcode },
4385     { Bad_Opcode },
4386     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4387   },
4388
4389   /* PREFIX_0F38DC */
4390   {
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4394   },
4395
4396   /* PREFIX_0F38DD */
4397   {
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4401   },
4402
4403   /* PREFIX_0F38DE */
4404   {
4405     { Bad_Opcode },
4406     { Bad_Opcode },
4407     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4408   },
4409
4410   /* PREFIX_0F38DF */
4411   {
4412     { Bad_Opcode },
4413     { Bad_Opcode },
4414     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4415   },
4416
4417   /* PREFIX_0F38F0 */
4418   {
4419     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4420     { Bad_Opcode },
4421     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4422     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4423   },
4424
4425   /* PREFIX_0F38F1 */
4426   {
4427     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4428     { Bad_Opcode },
4429     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4430     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4431   },
4432
4433   /* PREFIX_0F38F5 */
4434   {
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4438   },
4439
4440   /* PREFIX_0F38F6 */
4441   {
4442     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4443     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4444     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4445     { Bad_Opcode },
4446   },
4447
4448   /* PREFIX_0F38F8 */
4449   {
4450     { Bad_Opcode },
4451     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4452     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4453     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4454   },
4455
4456   /* PREFIX_0F38F9 */
4457   {
4458     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4459   },
4460
4461   /* PREFIX_0F3A08 */
4462   {
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4466   },
4467
4468   /* PREFIX_0F3A09 */
4469   {
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4473   },
4474
4475   /* PREFIX_0F3A0A */
4476   {
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4480   },
4481
4482   /* PREFIX_0F3A0B */
4483   {
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4487   },
4488
4489   /* PREFIX_0F3A0C */
4490   {
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4494   },
4495
4496   /* PREFIX_0F3A0D */
4497   {
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4501   },
4502
4503   /* PREFIX_0F3A0E */
4504   {
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4508   },
4509
4510   /* PREFIX_0F3A14 */
4511   {
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F3A15 */
4518   {
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4522   },
4523
4524   /* PREFIX_0F3A16 */
4525   {
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4529   },
4530
4531   /* PREFIX_0F3A17 */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F3A20 */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4543   },
4544
4545   /* PREFIX_0F3A21 */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F3A22 */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F3A40 */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F3A41 */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F3A42 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F3A44 */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F3A60 */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F3A61 */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F3A62 */
4602   {
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4606   },
4607
4608   /* PREFIX_0F3A63 */
4609   {
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4613   },
4614
4615   /* PREFIX_0F3ACC */
4616   {
4617     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4618   },
4619
4620   /* PREFIX_0F3ACE */
4621   {
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4625   },
4626
4627   /* PREFIX_0F3ACF */
4628   {
4629     { Bad_Opcode },
4630     { Bad_Opcode },
4631     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4632   },
4633
4634   /* PREFIX_0F3ADF */
4635   {
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4639   },
4640
4641   /* PREFIX_VEX_0F10 */
4642   {
4643     { "vmovups",        { XM, EXx }, 0 },
4644     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4645     { "vmovupd",        { XM, EXx }, 0 },
4646     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4647   },
4648
4649   /* PREFIX_VEX_0F11 */
4650   {
4651     { "vmovups",        { EXxS, XM }, 0 },
4652     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4653     { "vmovupd",        { EXxS, XM }, 0 },
4654     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4655   },
4656
4657   /* PREFIX_VEX_0F12 */
4658   {
4659     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4660     { "vmovsldup",      { XM, EXx }, 0 },
4661     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4662     { "vmovddup",       { XM, EXymmq }, 0 },
4663   },
4664
4665   /* PREFIX_VEX_0F16 */
4666   {
4667     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4668     { "vmovshdup",      { XM, EXx }, 0 },
4669     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4670   },
4671
4672   /* PREFIX_VEX_0F2A */
4673   {
4674     { Bad_Opcode },
4675     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4676     { Bad_Opcode },
4677     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4678   },
4679
4680   /* PREFIX_VEX_0F2C */
4681   {
4682     { Bad_Opcode },
4683     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4684     { Bad_Opcode },
4685     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4686   },
4687
4688   /* PREFIX_VEX_0F2D */
4689   {
4690     { Bad_Opcode },
4691     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4692     { Bad_Opcode },
4693     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4694   },
4695
4696   /* PREFIX_VEX_0F2E */
4697   {
4698     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4699     { Bad_Opcode },
4700     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4701   },
4702
4703   /* PREFIX_VEX_0F2F */
4704   {
4705     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4706     { Bad_Opcode },
4707     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4708   },
4709
4710   /* PREFIX_VEX_0F41 */
4711   {
4712     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4713     { Bad_Opcode },
4714     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4715   },
4716
4717   /* PREFIX_VEX_0F42 */
4718   {
4719     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4720     { Bad_Opcode },
4721     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4722   },
4723
4724   /* PREFIX_VEX_0F44 */
4725   {
4726     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4727     { Bad_Opcode },
4728     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4729   },
4730
4731   /* PREFIX_VEX_0F45 */
4732   {
4733     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4734     { Bad_Opcode },
4735     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4736   },
4737
4738   /* PREFIX_VEX_0F46 */
4739   {
4740     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4741     { Bad_Opcode },
4742     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4743   },
4744
4745   /* PREFIX_VEX_0F47 */
4746   {
4747     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4748     { Bad_Opcode },
4749     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4750   },
4751
4752   /* PREFIX_VEX_0F4A */
4753   {
4754     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4755     { Bad_Opcode },
4756     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4757   },
4758
4759   /* PREFIX_VEX_0F4B */
4760   {
4761     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4762     { Bad_Opcode },
4763     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4764   },
4765
4766   /* PREFIX_VEX_0F51 */
4767   {
4768     { "vsqrtps",        { XM, EXx }, 0 },
4769     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4770     { "vsqrtpd",        { XM, EXx }, 0 },
4771     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4772   },
4773
4774   /* PREFIX_VEX_0F52 */
4775   {
4776     { "vrsqrtps",       { XM, EXx }, 0 },
4777     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4778   },
4779
4780   /* PREFIX_VEX_0F53 */
4781   {
4782     { "vrcpps",         { XM, EXx }, 0 },
4783     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4784   },
4785
4786   /* PREFIX_VEX_0F58 */
4787   {
4788     { "vaddps",         { XM, Vex, EXx }, 0 },
4789     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4790     { "vaddpd",         { XM, Vex, EXx }, 0 },
4791     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4792   },
4793
4794   /* PREFIX_VEX_0F59 */
4795   {
4796     { "vmulps",         { XM, Vex, EXx }, 0 },
4797     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4798     { "vmulpd",         { XM, Vex, EXx }, 0 },
4799     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4800   },
4801
4802   /* PREFIX_VEX_0F5A */
4803   {
4804     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4805     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4806     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4807     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4808   },
4809
4810   /* PREFIX_VEX_0F5B */
4811   {
4812     { "vcvtdq2ps",      { XM, EXx }, 0 },
4813     { "vcvttps2dq",     { XM, EXx }, 0 },
4814     { "vcvtps2dq",      { XM, EXx }, 0 },
4815   },
4816
4817   /* PREFIX_VEX_0F5C */
4818   {
4819     { "vsubps",         { XM, Vex, EXx }, 0 },
4820     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4821     { "vsubpd",         { XM, Vex, EXx }, 0 },
4822     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4823   },
4824
4825   /* PREFIX_VEX_0F5D */
4826   {
4827     { "vminps",         { XM, Vex, EXx }, 0 },
4828     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4829     { "vminpd",         { XM, Vex, EXx }, 0 },
4830     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4831   },
4832
4833   /* PREFIX_VEX_0F5E */
4834   {
4835     { "vdivps",         { XM, Vex, EXx }, 0 },
4836     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4837     { "vdivpd",         { XM, Vex, EXx }, 0 },
4838     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4839   },
4840
4841   /* PREFIX_VEX_0F5F */
4842   {
4843     { "vmaxps",         { XM, Vex, EXx }, 0 },
4844     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4845     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4846     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4847   },
4848
4849   /* PREFIX_VEX_0F60 */
4850   {
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4854   },
4855
4856   /* PREFIX_VEX_0F61 */
4857   {
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4861   },
4862
4863   /* PREFIX_VEX_0F62 */
4864   {
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4868   },
4869
4870   /* PREFIX_VEX_0F63 */
4871   {
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4875   },
4876
4877   /* PREFIX_VEX_0F64 */
4878   {
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4882   },
4883
4884   /* PREFIX_VEX_0F65 */
4885   {
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4889   },
4890
4891   /* PREFIX_VEX_0F66 */
4892   {
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4896   },
4897
4898   /* PREFIX_VEX_0F67 */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4903   },
4904
4905   /* PREFIX_VEX_0F68 */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4910   },
4911
4912   /* PREFIX_VEX_0F69 */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4917   },
4918
4919   /* PREFIX_VEX_0F6A */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4924   },
4925
4926   /* PREFIX_VEX_0F6B */
4927   {
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4931   },
4932
4933   /* PREFIX_VEX_0F6C */
4934   {
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4938   },
4939
4940   /* PREFIX_VEX_0F6D */
4941   {
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4945   },
4946
4947   /* PREFIX_VEX_0F6E */
4948   {
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4952   },
4953
4954   /* PREFIX_VEX_0F6F */
4955   {
4956     { Bad_Opcode },
4957     { "vmovdqu",        { XM, EXx }, 0 },
4958     { "vmovdqa",        { XM, EXx }, 0 },
4959   },
4960
4961   /* PREFIX_VEX_0F70 */
4962   {
4963     { Bad_Opcode },
4964     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4965     { "vpshufd",        { XM, EXx, Ib }, 0 },
4966     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4967   },
4968
4969   /* PREFIX_VEX_0F71_REG_2 */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4974   },
4975
4976   /* PREFIX_VEX_0F71_REG_4 */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { "vpsraw",         { Vex, XS, Ib }, 0 },
4981   },
4982
4983   /* PREFIX_VEX_0F71_REG_6 */
4984   {
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { "vpsllw",         { Vex, XS, Ib }, 0 },
4988   },
4989
4990   /* PREFIX_VEX_0F72_REG_2 */
4991   {
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { "vpsrld",         { Vex, XS, Ib }, 0 },
4995   },
4996
4997   /* PREFIX_VEX_0F72_REG_4 */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { "vpsrad",         { Vex, XS, Ib }, 0 },
5002   },
5003
5004   /* PREFIX_VEX_0F72_REG_6 */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { "vpslld",         { Vex, XS, Ib }, 0 },
5009   },
5010
5011   /* PREFIX_VEX_0F73_REG_2 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5016   },
5017
5018   /* PREFIX_VEX_0F73_REG_3 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5023   },
5024
5025   /* PREFIX_VEX_0F73_REG_6 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { "vpsllq",         { Vex, XS, Ib }, 0 },
5030   },
5031
5032   /* PREFIX_VEX_0F73_REG_7 */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { "vpslldq",        { Vex, XS, Ib }, 0 },
5037   },
5038
5039   /* PREFIX_VEX_0F74 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5044   },
5045
5046   /* PREFIX_VEX_0F75 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5051   },
5052
5053   /* PREFIX_VEX_0F76 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5058   },
5059
5060   /* PREFIX_VEX_0F77 */
5061   {
5062     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5063   },
5064
5065   /* PREFIX_VEX_0F7C */
5066   {
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5070     { "vhaddps",        { XM, Vex, EXx }, 0 },
5071   },
5072
5073   /* PREFIX_VEX_0F7D */
5074   {
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5078     { "vhsubps",        { XM, Vex, EXx }, 0 },
5079   },
5080
5081   /* PREFIX_VEX_0F7E */
5082   {
5083     { Bad_Opcode },
5084     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5085     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5086   },
5087
5088   /* PREFIX_VEX_0F7F */
5089   {
5090     { Bad_Opcode },
5091     { "vmovdqu",        { EXxS, XM }, 0 },
5092     { "vmovdqa",        { EXxS, XM }, 0 },
5093   },
5094
5095   /* PREFIX_VEX_0F90 */
5096   {
5097     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5098     { Bad_Opcode },
5099     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5100   },
5101
5102   /* PREFIX_VEX_0F91 */
5103   {
5104     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5105     { Bad_Opcode },
5106     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5107   },
5108
5109   /* PREFIX_VEX_0F92 */
5110   {
5111     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5112     { Bad_Opcode },
5113     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5114     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5115   },
5116
5117   /* PREFIX_VEX_0F93 */
5118   {
5119     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5120     { Bad_Opcode },
5121     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5122     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5123   },
5124
5125   /* PREFIX_VEX_0F98 */
5126   {
5127     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5128     { Bad_Opcode },
5129     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5130   },
5131
5132   /* PREFIX_VEX_0F99 */
5133   {
5134     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5135     { Bad_Opcode },
5136     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5137   },
5138
5139   /* PREFIX_VEX_0FC2 */
5140   {
5141     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5142     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5143     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5144     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5145   },
5146
5147   /* PREFIX_VEX_0FC4 */
5148   {
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5152   },
5153
5154   /* PREFIX_VEX_0FC5 */
5155   {
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5159   },
5160
5161   /* PREFIX_VEX_0FD0 */
5162   {
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5166     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5167   },
5168
5169   /* PREFIX_VEX_0FD1 */
5170   {
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5174   },
5175
5176   /* PREFIX_VEX_0FD2 */
5177   {
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5181   },
5182
5183   /* PREFIX_VEX_0FD3 */
5184   {
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5188   },
5189
5190   /* PREFIX_VEX_0FD4 */
5191   {
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { "vpaddq",         { XM, Vex, EXx }, 0 },
5195   },
5196
5197   /* PREFIX_VEX_0FD5 */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { "vpmullw",        { XM, Vex, EXx }, 0 },
5202   },
5203
5204   /* PREFIX_VEX_0FD6 */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5209   },
5210
5211   /* PREFIX_VEX_0FD7 */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5216   },
5217
5218   /* PREFIX_VEX_0FD8 */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5223   },
5224
5225   /* PREFIX_VEX_0FD9 */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5230   },
5231
5232   /* PREFIX_VEX_0FDA */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { "vpminub",        { XM, Vex, EXx }, 0 },
5237   },
5238
5239   /* PREFIX_VEX_0FDB */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { "vpand",          { XM, Vex, EXx }, 0 },
5244   },
5245
5246   /* PREFIX_VEX_0FDC */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5251   },
5252
5253   /* PREFIX_VEX_0FDD */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5258   },
5259
5260   /* PREFIX_VEX_0FDE */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5265   },
5266
5267   /* PREFIX_VEX_0FDF */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { "vpandn",         { XM, Vex, EXx }, 0 },
5272   },
5273
5274   /* PREFIX_VEX_0FE0 */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { "vpavgb",         { XM, Vex, EXx }, 0 },
5279   },
5280
5281   /* PREFIX_VEX_0FE1 */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5286   },
5287
5288   /* PREFIX_VEX_0FE2 */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5293   },
5294
5295   /* PREFIX_VEX_0FE3 */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { "vpavgw",         { XM, Vex, EXx }, 0 },
5300   },
5301
5302   /* PREFIX_VEX_0FE4 */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5307   },
5308
5309   /* PREFIX_VEX_0FE5 */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5314   },
5315
5316   /* PREFIX_VEX_0FE6 */
5317   {
5318     { Bad_Opcode },
5319     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5320     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5321     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5322   },
5323
5324   /* PREFIX_VEX_0FE7 */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5329   },
5330
5331   /* PREFIX_VEX_0FE8 */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5336   },
5337
5338   /* PREFIX_VEX_0FE9 */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5343   },
5344
5345   /* PREFIX_VEX_0FEA */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { "vpminsw",        { XM, Vex, EXx }, 0 },
5350   },
5351
5352   /* PREFIX_VEX_0FEB */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { "vpor",           { XM, Vex, EXx }, 0 },
5357   },
5358
5359   /* PREFIX_VEX_0FEC */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5364   },
5365
5366   /* PREFIX_VEX_0FED */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5371   },
5372
5373   /* PREFIX_VEX_0FEE */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5378   },
5379
5380   /* PREFIX_VEX_0FEF */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { "vpxor",          { XM, Vex, EXx }, 0 },
5385   },
5386
5387   /* PREFIX_VEX_0FF0 */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5393   },
5394
5395   /* PREFIX_VEX_0FF1 */
5396   {
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5400   },
5401
5402   /* PREFIX_VEX_0FF2 */
5403   {
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5407   },
5408
5409   /* PREFIX_VEX_0FF3 */
5410   {
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5414   },
5415
5416   /* PREFIX_VEX_0FF4 */
5417   {
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5421   },
5422
5423   /* PREFIX_VEX_0FF5 */
5424   {
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5428   },
5429
5430   /* PREFIX_VEX_0FF6 */
5431   {
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5435   },
5436
5437   /* PREFIX_VEX_0FF7 */
5438   {
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5442   },
5443
5444   /* PREFIX_VEX_0FF8 */
5445   {
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { "vpsubb",         { XM, Vex, EXx }, 0 },
5449   },
5450
5451   /* PREFIX_VEX_0FF9 */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { "vpsubw",         { XM, Vex, EXx }, 0 },
5456   },
5457
5458   /* PREFIX_VEX_0FFA */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { "vpsubd",         { XM, Vex, EXx }, 0 },
5463   },
5464
5465   /* PREFIX_VEX_0FFB */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { "vpsubq",         { XM, Vex, EXx }, 0 },
5470   },
5471
5472   /* PREFIX_VEX_0FFC */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { "vpaddb",         { XM, Vex, EXx }, 0 },
5477   },
5478
5479   /* PREFIX_VEX_0FFD */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { "vpaddw",         { XM, Vex, EXx }, 0 },
5484   },
5485
5486   /* PREFIX_VEX_0FFE */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { "vpaddd",         { XM, Vex, EXx }, 0 },
5491   },
5492
5493   /* PREFIX_VEX_0F3800 */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { "vpshufb",        { XM, Vex, EXx }, 0 },
5498   },
5499
5500   /* PREFIX_VEX_0F3801 */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { "vphaddw",        { XM, Vex, EXx }, 0 },
5505   },
5506
5507   /* PREFIX_VEX_0F3802 */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { "vphaddd",        { XM, Vex, EXx }, 0 },
5512   },
5513
5514   /* PREFIX_VEX_0F3803 */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5519   },
5520
5521   /* PREFIX_VEX_0F3804 */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5526   },
5527
5528   /* PREFIX_VEX_0F3805 */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { "vphsubw",        { XM, Vex, EXx }, 0 },
5533   },
5534
5535   /* PREFIX_VEX_0F3806 */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { "vphsubd",        { XM, Vex, EXx }, 0 },
5540   },
5541
5542   /* PREFIX_VEX_0F3807 */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5547   },
5548
5549   /* PREFIX_VEX_0F3808 */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { "vpsignb",        { XM, Vex, EXx }, 0 },
5554   },
5555
5556   /* PREFIX_VEX_0F3809 */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { "vpsignw",        { XM, Vex, EXx }, 0 },
5561   },
5562
5563   /* PREFIX_VEX_0F380A */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { "vpsignd",        { XM, Vex, EXx }, 0 },
5568   },
5569
5570   /* PREFIX_VEX_0F380B */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5575   },
5576
5577   /* PREFIX_VEX_0F380C */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5582   },
5583
5584   /* PREFIX_VEX_0F380D */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5589   },
5590
5591   /* PREFIX_VEX_0F380E */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5596   },
5597
5598   /* PREFIX_VEX_0F380F */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5603   },
5604
5605   /* PREFIX_VEX_0F3813 */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5610   },
5611
5612   /* PREFIX_VEX_0F3816 */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5617   },
5618
5619   /* PREFIX_VEX_0F3817 */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { "vptest",         { XM, EXx }, 0 },
5624   },
5625
5626   /* PREFIX_VEX_0F3818 */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5631   },
5632
5633   /* PREFIX_VEX_0F3819 */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5638   },
5639
5640   /* PREFIX_VEX_0F381A */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5645   },
5646
5647   /* PREFIX_VEX_0F381C */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { "vpabsb",         { XM, EXx }, 0 },
5652   },
5653
5654   /* PREFIX_VEX_0F381D */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { "vpabsw",         { XM, EXx }, 0 },
5659   },
5660
5661   /* PREFIX_VEX_0F381E */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { "vpabsd",         { XM, EXx }, 0 },
5666   },
5667
5668   /* PREFIX_VEX_0F3820 */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5673   },
5674
5675   /* PREFIX_VEX_0F3821 */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5680   },
5681
5682   /* PREFIX_VEX_0F3822 */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5687   },
5688
5689   /* PREFIX_VEX_0F3823 */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5694   },
5695
5696   /* PREFIX_VEX_0F3824 */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5701   },
5702
5703   /* PREFIX_VEX_0F3825 */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5708   },
5709
5710   /* PREFIX_VEX_0F3828 */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5715   },
5716
5717   /* PREFIX_VEX_0F3829 */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5722   },
5723
5724   /* PREFIX_VEX_0F382A */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5729   },
5730
5731   /* PREFIX_VEX_0F382B */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5736   },
5737
5738   /* PREFIX_VEX_0F382C */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5743   },
5744
5745   /* PREFIX_VEX_0F382D */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5750   },
5751
5752   /* PREFIX_VEX_0F382E */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5757   },
5758
5759   /* PREFIX_VEX_0F382F */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5764   },
5765
5766   /* PREFIX_VEX_0F3830 */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5771   },
5772
5773   /* PREFIX_VEX_0F3831 */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5778   },
5779
5780   /* PREFIX_VEX_0F3832 */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5785   },
5786
5787   /* PREFIX_VEX_0F3833 */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5792   },
5793
5794   /* PREFIX_VEX_0F3834 */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5799   },
5800
5801   /* PREFIX_VEX_0F3835 */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5806   },
5807
5808   /* PREFIX_VEX_0F3836 */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5813   },
5814
5815   /* PREFIX_VEX_0F3837 */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5820   },
5821
5822   /* PREFIX_VEX_0F3838 */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { "vpminsb",        { XM, Vex, EXx }, 0 },
5827   },
5828
5829   /* PREFIX_VEX_0F3839 */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { "vpminsd",        { XM, Vex, EXx }, 0 },
5834   },
5835
5836   /* PREFIX_VEX_0F383A */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { "vpminuw",        { XM, Vex, EXx }, 0 },
5841   },
5842
5843   /* PREFIX_VEX_0F383B */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { "vpminud",        { XM, Vex, EXx }, 0 },
5848   },
5849
5850   /* PREFIX_VEX_0F383C */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5855   },
5856
5857   /* PREFIX_VEX_0F383D */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5862   },
5863
5864   /* PREFIX_VEX_0F383E */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5869   },
5870
5871   /* PREFIX_VEX_0F383F */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5876   },
5877
5878   /* PREFIX_VEX_0F3840 */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { "vpmulld",        { XM, Vex, EXx }, 0 },
5883   },
5884
5885   /* PREFIX_VEX_0F3841 */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5890   },
5891
5892   /* PREFIX_VEX_0F3845 */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5897   },
5898
5899   /* PREFIX_VEX_0F3846 */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5904   },
5905
5906   /* PREFIX_VEX_0F3847 */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5911   },
5912
5913   /* PREFIX_VEX_0F3858 */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5918   },
5919
5920   /* PREFIX_VEX_0F3859 */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5925   },
5926
5927   /* PREFIX_VEX_0F385A */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5932   },
5933
5934   /* PREFIX_VEX_0F3878 */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5939   },
5940
5941   /* PREFIX_VEX_0F3879 */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5946   },
5947
5948   /* PREFIX_VEX_0F388C */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5953   },
5954
5955   /* PREFIX_VEX_0F388E */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5960   },
5961
5962   /* PREFIX_VEX_0F3890 */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5967   },
5968
5969   /* PREFIX_VEX_0F3891 */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5974   },
5975
5976   /* PREFIX_VEX_0F3892 */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5981   },
5982
5983   /* PREFIX_VEX_0F3893 */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5988   },
5989
5990   /* PREFIX_VEX_0F3896 */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5995   },
5996
5997   /* PREFIX_VEX_0F3897 */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6002   },
6003
6004   /* PREFIX_VEX_0F3898 */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6009   },
6010
6011   /* PREFIX_VEX_0F3899 */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6016   },
6017
6018   /* PREFIX_VEX_0F389A */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6023   },
6024
6025   /* PREFIX_VEX_0F389B */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6030   },
6031
6032   /* PREFIX_VEX_0F389C */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6037   },
6038
6039   /* PREFIX_VEX_0F389D */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6044   },
6045
6046   /* PREFIX_VEX_0F389E */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6051   },
6052
6053   /* PREFIX_VEX_0F389F */
6054   {
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6058   },
6059
6060   /* PREFIX_VEX_0F38A6 */
6061   {
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6065     { Bad_Opcode },
6066   },
6067
6068   /* PREFIX_VEX_0F38A7 */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6073   },
6074
6075   /* PREFIX_VEX_0F38A8 */
6076   {
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6080   },
6081
6082   /* PREFIX_VEX_0F38A9 */
6083   {
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6087   },
6088
6089   /* PREFIX_VEX_0F38AA */
6090   {
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6094   },
6095
6096   /* PREFIX_VEX_0F38AB */
6097   {
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6101   },
6102
6103   /* PREFIX_VEX_0F38AC */
6104   {
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6108   },
6109
6110   /* PREFIX_VEX_0F38AD */
6111   {
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6115   },
6116
6117   /* PREFIX_VEX_0F38AE */
6118   {
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6122   },
6123
6124   /* PREFIX_VEX_0F38AF */
6125   {
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6129   },
6130
6131   /* PREFIX_VEX_0F38B6 */
6132   {
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6136   },
6137
6138   /* PREFIX_VEX_0F38B7 */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6143   },
6144
6145   /* PREFIX_VEX_0F38B8 */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6150   },
6151
6152   /* PREFIX_VEX_0F38B9 */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6157   },
6158
6159   /* PREFIX_VEX_0F38BA */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6164   },
6165
6166   /* PREFIX_VEX_0F38BB */
6167   {
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6171   },
6172
6173   /* PREFIX_VEX_0F38BC */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6178   },
6179
6180   /* PREFIX_VEX_0F38BD */
6181   {
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6185   },
6186
6187   /* PREFIX_VEX_0F38BE */
6188   {
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6192   },
6193
6194   /* PREFIX_VEX_0F38BF */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6199   },
6200
6201   /* PREFIX_VEX_0F38CF */
6202   {
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6206   },
6207
6208   /* PREFIX_VEX_0F38DB */
6209   {
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6213   },
6214
6215   /* PREFIX_VEX_0F38DC */
6216   {
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { "vaesenc",        { XM, Vex, EXx }, 0 },
6220   },
6221
6222   /* PREFIX_VEX_0F38DD */
6223   {
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6227   },
6228
6229   /* PREFIX_VEX_0F38DE */
6230   {
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { "vaesdec",        { XM, Vex, EXx }, 0 },
6234   },
6235
6236   /* PREFIX_VEX_0F38DF */
6237   {
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6241   },
6242
6243   /* PREFIX_VEX_0F38F2 */
6244   {
6245     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6246   },
6247
6248   /* PREFIX_VEX_0F38F3_REG_1 */
6249   {
6250     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6251   },
6252
6253   /* PREFIX_VEX_0F38F3_REG_2 */
6254   {
6255     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6256   },
6257
6258   /* PREFIX_VEX_0F38F3_REG_3 */
6259   {
6260     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6261   },
6262
6263   /* PREFIX_VEX_0F38F5 */
6264   {
6265     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6266     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6267     { Bad_Opcode },
6268     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6269   },
6270
6271   /* PREFIX_VEX_0F38F6 */
6272   {
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6277   },
6278
6279   /* PREFIX_VEX_0F38F7 */
6280   {
6281     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6282     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6283     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6284     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6285   },
6286
6287   /* PREFIX_VEX_0F3A00 */
6288   {
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6292   },
6293
6294   /* PREFIX_VEX_0F3A01 */
6295   {
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6299   },
6300
6301   /* PREFIX_VEX_0F3A02 */
6302   {
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6306   },
6307
6308   /* PREFIX_VEX_0F3A04 */
6309   {
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6313   },
6314
6315   /* PREFIX_VEX_0F3A05 */
6316   {
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6320   },
6321
6322   /* PREFIX_VEX_0F3A06 */
6323   {
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6327   },
6328
6329   /* PREFIX_VEX_0F3A08 */
6330   {
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { "vroundps",       { XM, EXx, Ib }, 0 },
6334   },
6335
6336   /* PREFIX_VEX_0F3A09 */
6337   {
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { "vroundpd",       { XM, EXx, Ib }, 0 },
6341   },
6342
6343   /* PREFIX_VEX_0F3A0A */
6344   {
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6348   },
6349
6350   /* PREFIX_VEX_0F3A0B */
6351   {
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6355   },
6356
6357   /* PREFIX_VEX_0F3A0C */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6362   },
6363
6364   /* PREFIX_VEX_0F3A0D */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6369   },
6370
6371   /* PREFIX_VEX_0F3A0E */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6376   },
6377
6378   /* PREFIX_VEX_0F3A0F */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6383   },
6384
6385   /* PREFIX_VEX_0F3A14 */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6390   },
6391
6392   /* PREFIX_VEX_0F3A15 */
6393   {
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6397   },
6398
6399   /* PREFIX_VEX_0F3A16 */
6400   {
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6404   },
6405
6406   /* PREFIX_VEX_0F3A17 */
6407   {
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6411   },
6412
6413   /* PREFIX_VEX_0F3A18 */
6414   {
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6418   },
6419
6420   /* PREFIX_VEX_0F3A19 */
6421   {
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6425   },
6426
6427   /* PREFIX_VEX_0F3A1D */
6428   {
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6432   },
6433
6434   /* PREFIX_VEX_0F3A20 */
6435   {
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6439   },
6440
6441   /* PREFIX_VEX_0F3A21 */
6442   {
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6446   },
6447
6448   /* PREFIX_VEX_0F3A22 */
6449   {
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6453   },
6454
6455   /* PREFIX_VEX_0F3A30 */
6456   {
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6460   },
6461
6462   /* PREFIX_VEX_0F3A31 */
6463   {
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6467   },
6468
6469   /* PREFIX_VEX_0F3A32 */
6470   {
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6474   },
6475
6476   /* PREFIX_VEX_0F3A33 */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6481   },
6482
6483   /* PREFIX_VEX_0F3A38 */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6488   },
6489
6490   /* PREFIX_VEX_0F3A39 */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6495   },
6496
6497   /* PREFIX_VEX_0F3A40 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6502   },
6503
6504   /* PREFIX_VEX_0F3A41 */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6509   },
6510
6511   /* PREFIX_VEX_0F3A42 */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6516   },
6517
6518   /* PREFIX_VEX_0F3A44 */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6523   },
6524
6525   /* PREFIX_VEX_0F3A46 */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6530   },
6531
6532   /* PREFIX_VEX_0F3A48 */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6537   },
6538
6539   /* PREFIX_VEX_0F3A49 */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6544   },
6545
6546   /* PREFIX_VEX_0F3A4A */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6551   },
6552
6553   /* PREFIX_VEX_0F3A4B */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6558   },
6559
6560   /* PREFIX_VEX_0F3A4C */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6565   },
6566
6567   /* PREFIX_VEX_0F3A5C */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6572   },
6573
6574   /* PREFIX_VEX_0F3A5D */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6579   },
6580
6581   /* PREFIX_VEX_0F3A5E */
6582   {
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6586   },
6587
6588   /* PREFIX_VEX_0F3A5F */
6589   {
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6593   },
6594
6595   /* PREFIX_VEX_0F3A60 */
6596   {
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6600     { Bad_Opcode },
6601   },
6602
6603   /* PREFIX_VEX_0F3A61 */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6608   },
6609
6610   /* PREFIX_VEX_0F3A62 */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6615   },
6616
6617   /* PREFIX_VEX_0F3A63 */
6618   {
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6622   },
6623
6624   /* PREFIX_VEX_0F3A68 */
6625   {
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6629   },
6630
6631   /* PREFIX_VEX_0F3A69 */
6632   {
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6636   },
6637
6638   /* PREFIX_VEX_0F3A6A */
6639   {
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6643   },
6644
6645   /* PREFIX_VEX_0F3A6B */
6646   {
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6650   },
6651
6652   /* PREFIX_VEX_0F3A6C */
6653   {
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6657   },
6658
6659   /* PREFIX_VEX_0F3A6D */
6660   {
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6664   },
6665
6666   /* PREFIX_VEX_0F3A6E */
6667   {
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6671   },
6672
6673   /* PREFIX_VEX_0F3A6F */
6674   {
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6678   },
6679
6680   /* PREFIX_VEX_0F3A78 */
6681   {
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6685   },
6686
6687   /* PREFIX_VEX_0F3A79 */
6688   {
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6692   },
6693
6694   /* PREFIX_VEX_0F3A7A */
6695   {
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6699   },
6700
6701   /* PREFIX_VEX_0F3A7B */
6702   {
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6706   },
6707
6708   /* PREFIX_VEX_0F3A7C */
6709   {
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6713     { Bad_Opcode },
6714   },
6715
6716   /* PREFIX_VEX_0F3A7D */
6717   {
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6721   },
6722
6723   /* PREFIX_VEX_0F3A7E */
6724   {
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6728   },
6729
6730   /* PREFIX_VEX_0F3A7F */
6731   {
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6735   },
6736
6737   /* PREFIX_VEX_0F3ACE */
6738   {
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6742   },
6743
6744   /* PREFIX_VEX_0F3ACF */
6745   {
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6749   },
6750
6751   /* PREFIX_VEX_0F3ADF */
6752   {
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6756   },
6757
6758   /* PREFIX_VEX_0F3AF0 */
6759   {
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6764   },
6765
6766 #define NEED_PREFIX_TABLE
6767 #include "i386-dis-evex.h"
6768 #undef NEED_PREFIX_TABLE
6769 };
6770
6771 static const struct dis386 x86_64_table[][2] = {
6772   /* X86_64_06 */
6773   {
6774     { "pushP", { es }, 0 },
6775   },
6776
6777   /* X86_64_07 */
6778   {
6779     { "popP", { es }, 0 },
6780   },
6781
6782   /* X86_64_0D */
6783   {
6784     { "pushP", { cs }, 0 },
6785   },
6786
6787   /* X86_64_16 */
6788   {
6789     { "pushP", { ss }, 0 },
6790   },
6791
6792   /* X86_64_17 */
6793   {
6794     { "popP", { ss }, 0 },
6795   },
6796
6797   /* X86_64_1E */
6798   {
6799     { "pushP", { ds }, 0 },
6800   },
6801
6802   /* X86_64_1F */
6803   {
6804     { "popP", { ds }, 0 },
6805   },
6806
6807   /* X86_64_27 */
6808   {
6809     { "daa", { XX }, 0 },
6810   },
6811
6812   /* X86_64_2F */
6813   {
6814     { "das", { XX }, 0 },
6815   },
6816
6817   /* X86_64_37 */
6818   {
6819     { "aaa", { XX }, 0 },
6820   },
6821
6822   /* X86_64_3F */
6823   {
6824     { "aas", { XX }, 0 },
6825   },
6826
6827   /* X86_64_60 */
6828   {
6829     { "pushaP", { XX }, 0 },
6830   },
6831
6832   /* X86_64_61 */
6833   {
6834     { "popaP", { XX }, 0 },
6835   },
6836
6837   /* X86_64_62 */
6838   {
6839     { MOD_TABLE (MOD_62_32BIT) },
6840     { EVEX_TABLE (EVEX_0F) },
6841   },
6842
6843   /* X86_64_63 */
6844   {
6845     { "arpl", { Ew, Gw }, 0 },
6846     { "movs{lq|xd}", { Gv, Ed }, 0 },
6847   },
6848
6849   /* X86_64_6D */
6850   {
6851     { "ins{R|}", { Yzr, indirDX }, 0 },
6852     { "ins{G|}", { Yzr, indirDX }, 0 },
6853   },
6854
6855   /* X86_64_6F */
6856   {
6857     { "outs{R|}", { indirDXr, Xz }, 0 },
6858     { "outs{G|}", { indirDXr, Xz }, 0 },
6859   },
6860
6861   /* X86_64_82 */
6862   {
6863     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6864     { REG_TABLE (REG_80) },
6865   },
6866
6867   /* X86_64_9A */
6868   {
6869     { "Jcall{T|}", { Ap }, 0 },
6870   },
6871
6872   /* X86_64_C4 */
6873   {
6874     { MOD_TABLE (MOD_C4_32BIT) },
6875     { VEX_C4_TABLE (VEX_0F) },
6876   },
6877
6878   /* X86_64_C5 */
6879   {
6880     { MOD_TABLE (MOD_C5_32BIT) },
6881     { VEX_C5_TABLE (VEX_0F) },
6882   },
6883
6884   /* X86_64_CE */
6885   {
6886     { "into", { XX }, 0 },
6887   },
6888
6889   /* X86_64_D4 */
6890   {
6891     { "aam", { Ib }, 0 },
6892   },
6893
6894   /* X86_64_D5 */
6895   {
6896     { "aad", { Ib }, 0 },
6897   },
6898
6899   /* X86_64_E8 */
6900   {
6901     { "callP",          { Jv, BND }, 0 },
6902     { "call@",          { Jv, BND }, 0 }
6903   },
6904
6905   /* X86_64_E9 */
6906   {
6907     { "jmpP",           { Jv, BND }, 0 },
6908     { "jmp@",           { Jv, BND }, 0 }
6909   },
6910
6911   /* X86_64_EA */
6912   {
6913     { "Jjmp{T|}", { Ap }, 0 },
6914   },
6915
6916   /* X86_64_0F01_REG_0 */
6917   {
6918     { "sgdt{Q|IQ}", { M }, 0 },
6919     { "sgdt", { M }, 0 },
6920   },
6921
6922   /* X86_64_0F01_REG_1 */
6923   {
6924     { "sidt{Q|IQ}", { M }, 0 },
6925     { "sidt", { M }, 0 },
6926   },
6927
6928   /* X86_64_0F01_REG_2 */
6929   {
6930     { "lgdt{Q|Q}", { M }, 0 },
6931     { "lgdt", { M }, 0 },
6932   },
6933
6934   /* X86_64_0F01_REG_3 */
6935   {
6936     { "lidt{Q|Q}", { M }, 0 },
6937     { "lidt", { M }, 0 },
6938   },
6939 };
6940
6941 static const struct dis386 three_byte_table[][256] = {
6942
6943   /* THREE_BYTE_0F38 */
6944   {
6945     /* 00 */
6946     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6947     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6948     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6949     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6950     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6951     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6952     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6953     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6954     /* 08 */
6955     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6956     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6957     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6958     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     /* 10 */
6964     { PREFIX_TABLE (PREFIX_0F3810) },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { PREFIX_TABLE (PREFIX_0F3814) },
6969     { PREFIX_TABLE (PREFIX_0F3815) },
6970     { Bad_Opcode },
6971     { PREFIX_TABLE (PREFIX_0F3817) },
6972     /* 18 */
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6978     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6979     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6980     { Bad_Opcode },
6981     /* 20 */
6982     { PREFIX_TABLE (PREFIX_0F3820) },
6983     { PREFIX_TABLE (PREFIX_0F3821) },
6984     { PREFIX_TABLE (PREFIX_0F3822) },
6985     { PREFIX_TABLE (PREFIX_0F3823) },
6986     { PREFIX_TABLE (PREFIX_0F3824) },
6987     { PREFIX_TABLE (PREFIX_0F3825) },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     /* 28 */
6991     { PREFIX_TABLE (PREFIX_0F3828) },
6992     { PREFIX_TABLE (PREFIX_0F3829) },
6993     { PREFIX_TABLE (PREFIX_0F382A) },
6994     { PREFIX_TABLE (PREFIX_0F382B) },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     /* 30 */
7000     { PREFIX_TABLE (PREFIX_0F3830) },
7001     { PREFIX_TABLE (PREFIX_0F3831) },
7002     { PREFIX_TABLE (PREFIX_0F3832) },
7003     { PREFIX_TABLE (PREFIX_0F3833) },
7004     { PREFIX_TABLE (PREFIX_0F3834) },
7005     { PREFIX_TABLE (PREFIX_0F3835) },
7006     { Bad_Opcode },
7007     { PREFIX_TABLE (PREFIX_0F3837) },
7008     /* 38 */
7009     { PREFIX_TABLE (PREFIX_0F3838) },
7010     { PREFIX_TABLE (PREFIX_0F3839) },
7011     { PREFIX_TABLE (PREFIX_0F383A) },
7012     { PREFIX_TABLE (PREFIX_0F383B) },
7013     { PREFIX_TABLE (PREFIX_0F383C) },
7014     { PREFIX_TABLE (PREFIX_0F383D) },
7015     { PREFIX_TABLE (PREFIX_0F383E) },
7016     { PREFIX_TABLE (PREFIX_0F383F) },
7017     /* 40 */
7018     { PREFIX_TABLE (PREFIX_0F3840) },
7019     { PREFIX_TABLE (PREFIX_0F3841) },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     /* 48 */
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     /* 50 */
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     /* 58 */
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     /* 60 */
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     /* 68 */
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     /* 70 */
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     /* 78 */
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     /* 80 */
7090     { PREFIX_TABLE (PREFIX_0F3880) },
7091     { PREFIX_TABLE (PREFIX_0F3881) },
7092     { PREFIX_TABLE (PREFIX_0F3882) },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     /* 88 */
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     /* 90 */
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     /* 98 */
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     /* a0 */
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     /* a8 */
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     /* b0 */
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     /* b8 */
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     /* c0 */
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     /* c8 */
7171     { PREFIX_TABLE (PREFIX_0F38C8) },
7172     { PREFIX_TABLE (PREFIX_0F38C9) },
7173     { PREFIX_TABLE (PREFIX_0F38CA) },
7174     { PREFIX_TABLE (PREFIX_0F38CB) },
7175     { PREFIX_TABLE (PREFIX_0F38CC) },
7176     { PREFIX_TABLE (PREFIX_0F38CD) },
7177     { Bad_Opcode },
7178     { PREFIX_TABLE (PREFIX_0F38CF) },
7179     /* d0 */
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     /* d8 */
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { PREFIX_TABLE (PREFIX_0F38DB) },
7193     { PREFIX_TABLE (PREFIX_0F38DC) },
7194     { PREFIX_TABLE (PREFIX_0F38DD) },
7195     { PREFIX_TABLE (PREFIX_0F38DE) },
7196     { PREFIX_TABLE (PREFIX_0F38DF) },
7197     /* e0 */
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     /* e8 */
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     /* f0 */
7216     { PREFIX_TABLE (PREFIX_0F38F0) },
7217     { PREFIX_TABLE (PREFIX_0F38F1) },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { PREFIX_TABLE (PREFIX_0F38F5) },
7222     { PREFIX_TABLE (PREFIX_0F38F6) },
7223     { Bad_Opcode },
7224     /* f8 */
7225     { PREFIX_TABLE (PREFIX_0F38F8) },
7226     { PREFIX_TABLE (PREFIX_0F38F9) },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233   },
7234   /* THREE_BYTE_0F3A */
7235   {
7236     /* 00 */
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     /* 08 */
7246     { PREFIX_TABLE (PREFIX_0F3A08) },
7247     { PREFIX_TABLE (PREFIX_0F3A09) },
7248     { PREFIX_TABLE (PREFIX_0F3A0A) },
7249     { PREFIX_TABLE (PREFIX_0F3A0B) },
7250     { PREFIX_TABLE (PREFIX_0F3A0C) },
7251     { PREFIX_TABLE (PREFIX_0F3A0D) },
7252     { PREFIX_TABLE (PREFIX_0F3A0E) },
7253     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7254     /* 10 */
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { PREFIX_TABLE (PREFIX_0F3A14) },
7260     { PREFIX_TABLE (PREFIX_0F3A15) },
7261     { PREFIX_TABLE (PREFIX_0F3A16) },
7262     { PREFIX_TABLE (PREFIX_0F3A17) },
7263     /* 18 */
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     /* 20 */
7273     { PREFIX_TABLE (PREFIX_0F3A20) },
7274     { PREFIX_TABLE (PREFIX_0F3A21) },
7275     { PREFIX_TABLE (PREFIX_0F3A22) },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     /* 28 */
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     /* 30 */
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     /* 38 */
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     /* 40 */
7309     { PREFIX_TABLE (PREFIX_0F3A40) },
7310     { PREFIX_TABLE (PREFIX_0F3A41) },
7311     { PREFIX_TABLE (PREFIX_0F3A42) },
7312     { Bad_Opcode },
7313     { PREFIX_TABLE (PREFIX_0F3A44) },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     /* 48 */
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     /* 50 */
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     /* 58 */
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     /* 60 */
7345     { PREFIX_TABLE (PREFIX_0F3A60) },
7346     { PREFIX_TABLE (PREFIX_0F3A61) },
7347     { PREFIX_TABLE (PREFIX_0F3A62) },
7348     { PREFIX_TABLE (PREFIX_0F3A63) },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     /* 68 */
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     /* 70 */
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     /* 78 */
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     /* 80 */
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     /* 88 */
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     /* 90 */
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     /* 98 */
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     /* a0 */
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     /* a8 */
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     /* b0 */
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     /* b8 */
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     /* c0 */
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     /* c8 */
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { PREFIX_TABLE (PREFIX_0F3ACC) },
7467     { Bad_Opcode },
7468     { PREFIX_TABLE (PREFIX_0F3ACE) },
7469     { PREFIX_TABLE (PREFIX_0F3ACF) },
7470     /* d0 */
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     /* d8 */
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { PREFIX_TABLE (PREFIX_0F3ADF) },
7488     /* e0 */
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     /* e8 */
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     /* f0 */
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     /* f8 */
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524   },
7525 };
7526
7527 static const struct dis386 xop_table[][256] = {
7528   /* XOP_08 */
7529   {
7530     /* 00 */
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     /* 08 */
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     /* 10 */
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     /* 18 */
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     /* 20 */
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     /* 28 */
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     /* 30 */
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     /* 38 */
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     /* 40 */
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     /* 48 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     /* 50 */
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     /* 58 */
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     /* 60 */
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     /* 68 */
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     /* 70 */
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     /* 78 */
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     /* 80 */
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7681     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7682     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7683     /* 88 */
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7691     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7692     /* 90 */
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7699     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7700     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7701     /* 98 */
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7709     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7710     /* a0 */
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7714     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7718     { Bad_Opcode },
7719     /* a8 */
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     /* b0 */
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7736     { Bad_Opcode },
7737     /* b8 */
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     /* c0 */
7747     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7748     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7749     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7750     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     /* c8 */
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7761     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7762     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7763     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7764     /* d0 */
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     /* d8 */
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     /* e0 */
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     /* e8 */
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7797     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7798     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7799     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7800     /* f0 */
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     /* f8 */
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818   },
7819   /* XOP_09 */
7820   {
7821     /* 00 */
7822     { Bad_Opcode },
7823     { REG_TABLE (REG_XOP_TBM_01) },
7824     { REG_TABLE (REG_XOP_TBM_02) },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     /* 08 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     /* 10 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { REG_TABLE (REG_XOP_LWPCB) },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     /* 18 */
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     /* 20 */
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     /* 28 */
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     /* 30 */
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     /* 38 */
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     /* 40 */
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     /* 48 */
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     /* 50 */
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     /* 58 */
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     /* 60 */
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     /* 68 */
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     /* 70 */
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     /* 78 */
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     /* 80 */
7966     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7967     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7968     { "vfrczss",        { XM, EXd }, 0 },
7969     { "vfrczsd",        { XM, EXq }, 0 },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     /* 88 */
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     /* 90 */
7984     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7985     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7986     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7987     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7988     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7989     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7990     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7991     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7992     /* 98 */
7993     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7994     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7995     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7996     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     /* a0 */
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     /* a8 */
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     /* b0 */
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     /* b8 */
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     /* c0 */
8038     { Bad_Opcode },
8039     { "vphaddbw",       { XM, EXxmm }, 0 },
8040     { "vphaddbd",       { XM, EXxmm }, 0 },
8041     { "vphaddbq",       { XM, EXxmm }, 0 },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { "vphaddwd",       { XM, EXxmm }, 0 },
8045     { "vphaddwq",       { XM, EXxmm }, 0 },
8046     /* c8 */
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { "vphadddq",       { XM, EXxmm }, 0 },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     /* d0 */
8056     { Bad_Opcode },
8057     { "vphaddubw",      { XM, EXxmm }, 0 },
8058     { "vphaddubd",      { XM, EXxmm }, 0 },
8059     { "vphaddubq",      { XM, EXxmm }, 0 },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { "vphadduwd",      { XM, EXxmm }, 0 },
8063     { "vphadduwq",      { XM, EXxmm }, 0 },
8064     /* d8 */
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { "vphaddudq",      { XM, EXxmm }, 0 },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     /* e0 */
8074     { Bad_Opcode },
8075     { "vphsubbw",       { XM, EXxmm }, 0 },
8076     { "vphsubwd",       { XM, EXxmm }, 0 },
8077     { "vphsubdq",       { XM, EXxmm }, 0 },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     /* e8 */
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     /* f0 */
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     /* f8 */
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109   },
8110   /* XOP_0A */
8111   {
8112     /* 00 */
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     /* 08 */
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* 10 */
8131     { "bextr",  { Gv, Ev, Iq }, 0 },
8132     { Bad_Opcode },
8133     { REG_TABLE (REG_XOP_LWP) },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     /* 18 */
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     /* 20 */
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     /* 28 */
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     /* 30 */
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     /* 38 */
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     /* 40 */
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     /* 48 */
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     /* 50 */
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     /* 58 */
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     /* 60 */
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     /* 68 */
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     /* 70 */
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     /* 78 */
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     /* 80 */
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     /* 88 */
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     /* 90 */
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     /* 98 */
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     /* a0 */
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     /* a8 */
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     /* b0 */
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     /* b8 */
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     /* c0 */
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     /* c8 */
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     /* d0 */
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     /* d8 */
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     /* e0 */
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     /* e8 */
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     /* f0 */
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     /* f8 */
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400   },
8401 };
8402
8403 static const struct dis386 vex_table[][256] = {
8404   /* VEX_0F */
8405   {
8406     /* 00 */
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     /* 08 */
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     /* 10 */
8425     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8426     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8427     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8428     { MOD_TABLE (MOD_VEX_0F13) },
8429     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8430     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8431     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8432     { MOD_TABLE (MOD_VEX_0F17) },
8433     /* 18 */
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     /* 20 */
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     /* 28 */
8452     { "vmovapX",        { XM, EXx }, 0 },
8453     { "vmovapX",        { EXxS, XM }, 0 },
8454     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8455     { MOD_TABLE (MOD_VEX_0F2B) },
8456     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8457     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8458     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8459     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8460     /* 30 */
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     /* 38 */
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     /* 40 */
8479     { Bad_Opcode },
8480     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8481     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8482     { Bad_Opcode },
8483     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8485     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8486     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8487     /* 48 */
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8491     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     /* 50 */
8497     { MOD_TABLE (MOD_VEX_0F50) },
8498     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8499     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8500     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8501     { "vandpX",         { XM, Vex, EXx }, 0 },
8502     { "vandnpX",        { XM, Vex, EXx }, 0 },
8503     { "vorpX",          { XM, Vex, EXx }, 0 },
8504     { "vxorpX",         { XM, Vex, EXx }, 0 },
8505     /* 58 */
8506     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8507     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8508     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8509     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8510     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8511     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8514     /* 60 */
8515     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8517     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8518     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8519     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8520     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8521     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8522     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8523     /* 68 */
8524     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8531     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8532     /* 70 */
8533     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8534     { REG_TABLE (REG_VEX_0F71) },
8535     { REG_TABLE (REG_VEX_0F72) },
8536     { REG_TABLE (REG_VEX_0F73) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8541     /* 78 */
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8550     /* 80 */
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     /* 88 */
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     /* 90 */
8569     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8571     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8572     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     /* 98 */
8578     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8579     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     /* a0 */
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     /* a8 */
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { REG_TABLE (REG_VEX_0FAE) },
8603     { Bad_Opcode },
8604     /* b0 */
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     /* b8 */
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     /* c0 */
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8626     { Bad_Opcode },
8627     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8628     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8629     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8630     { Bad_Opcode },
8631     /* c8 */
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     /* d0 */
8641     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8642     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8643     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8644     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8645     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8646     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8647     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8648     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8649     /* d8 */
8650     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8651     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8652     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8653     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8654     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8655     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8656     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8657     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8658     /* e0 */
8659     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8660     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8661     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8662     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8663     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8664     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8665     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8666     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8667     /* e8 */
8668     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8676     /* f0 */
8677     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8685     /* f8 */
8686     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8693     { Bad_Opcode },
8694   },
8695   /* VEX_0F38 */
8696   {
8697     /* 00 */
8698     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8706     /* 08 */
8707     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8715     /* 10 */
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8724     /* 18 */
8725     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8728     { Bad_Opcode },
8729     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8732     { Bad_Opcode },
8733     /* 20 */
8734     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     /* 28 */
8743     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8751     /* 30 */
8752     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8760     /* 38 */
8761     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8769     /* 40 */
8770     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8778     /* 48 */
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     /* 50 */
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     /* 58 */
8797     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     /* 60 */
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     /* 68 */
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     /* 70 */
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     /* 78 */
8833     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8834     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     /* 80 */
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     /* 88 */
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8856     { Bad_Opcode },
8857     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8858     { Bad_Opcode },
8859     /* 90 */
8860     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8861     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8862     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8863     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8867     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8868     /* 98 */
8869     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8870     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8871     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8872     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8873     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8874     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8875     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8876     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8877     /* a0 */
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8886     /* a8 */
8887     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8895     /* b0 */
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8904     /* b8 */
8905     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8913     /* c0 */
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     /* c8 */
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8931     /* d0 */
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     /* d8 */
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8949     /* e0 */
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     /* e8 */
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     /* f0 */
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8971     { REG_TABLE (REG_VEX_0F38F3) },
8972     { Bad_Opcode },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8976     /* f8 */
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985   },
8986   /* VEX_0F3A */
8987   {
8988     /* 00 */
8989     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8992     { Bad_Opcode },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8996     { Bad_Opcode },
8997     /* 08 */
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9006     /* 10 */
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9015     /* 18 */
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     /* 20 */
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     /* 28 */
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     /* 30 */
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     /* 38 */
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     /* 40 */
9061     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9064     { Bad_Opcode },
9065     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9066     { Bad_Opcode },
9067     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9068     { Bad_Opcode },
9069     /* 48 */
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     /* 50 */
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     /* 58 */
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9096     /* 60 */
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     /* 68 */
9106     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9114     /* 70 */
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     /* 78 */
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9132     /* 80 */
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     /* 88 */
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     /* 90 */
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     /* 98 */
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     /* a0 */
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     /* a8 */
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     /* b0 */
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     /* b8 */
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     /* c0 */
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     /* c8 */
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9221     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9222     /* d0 */
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     /* d8 */
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9240     /* e0 */
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     /* e8 */
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     /* f0 */
9259     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     /* f8 */
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276   },
9277 };
9278
9279 #define NEED_OPCODE_TABLE
9280 #include "i386-dis-evex.h"
9281 #undef NEED_OPCODE_TABLE
9282 static const struct dis386 vex_len_table[][2] = {
9283   /* VEX_LEN_0F12_P_0_M_0 */
9284   {
9285     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9286   },
9287
9288   /* VEX_LEN_0F12_P_0_M_1 */
9289   {
9290     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9291   },
9292
9293   /* VEX_LEN_0F12_P_2 */
9294   {
9295     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9296   },
9297
9298   /* VEX_LEN_0F13_M_0 */
9299   {
9300     { "vmovlpX",        { EXq, XM }, 0 },
9301   },
9302
9303   /* VEX_LEN_0F16_P_0_M_0 */
9304   {
9305     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9306   },
9307
9308   /* VEX_LEN_0F16_P_0_M_1 */
9309   {
9310     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9311   },
9312
9313   /* VEX_LEN_0F16_P_2 */
9314   {
9315     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9316   },
9317
9318   /* VEX_LEN_0F17_M_0 */
9319   {
9320     { "vmovhpX",        { EXq, XM }, 0 },
9321   },
9322
9323   /* VEX_LEN_0F2A_P_1 */
9324   {
9325     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9326     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9327   },
9328
9329   /* VEX_LEN_0F2A_P_3 */
9330   {
9331     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9332     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9333   },
9334
9335   /* VEX_LEN_0F2C_P_1 */
9336   {
9337     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9338     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9339   },
9340
9341   /* VEX_LEN_0F2C_P_3 */
9342   {
9343     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9344     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9345   },
9346
9347   /* VEX_LEN_0F2D_P_1 */
9348   {
9349     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9350     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9351   },
9352
9353   /* VEX_LEN_0F2D_P_3 */
9354   {
9355     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9356     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9357   },
9358
9359   /* VEX_LEN_0F41_P_0 */
9360   {
9361     { Bad_Opcode },
9362     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9363   },
9364   /* VEX_LEN_0F41_P_2 */
9365   {
9366     { Bad_Opcode },
9367     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9368   },
9369   /* VEX_LEN_0F42_P_0 */
9370   {
9371     { Bad_Opcode },
9372     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9373   },
9374   /* VEX_LEN_0F42_P_2 */
9375   {
9376     { Bad_Opcode },
9377     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9378   },
9379   /* VEX_LEN_0F44_P_0 */
9380   {
9381     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9382   },
9383   /* VEX_LEN_0F44_P_2 */
9384   {
9385     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9386   },
9387   /* VEX_LEN_0F45_P_0 */
9388   {
9389     { Bad_Opcode },
9390     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9391   },
9392   /* VEX_LEN_0F45_P_2 */
9393   {
9394     { Bad_Opcode },
9395     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9396   },
9397   /* VEX_LEN_0F46_P_0 */
9398   {
9399     { Bad_Opcode },
9400     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9401   },
9402   /* VEX_LEN_0F46_P_2 */
9403   {
9404     { Bad_Opcode },
9405     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9406   },
9407   /* VEX_LEN_0F47_P_0 */
9408   {
9409     { Bad_Opcode },
9410     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9411   },
9412   /* VEX_LEN_0F47_P_2 */
9413   {
9414     { Bad_Opcode },
9415     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9416   },
9417   /* VEX_LEN_0F4A_P_0 */
9418   {
9419     { Bad_Opcode },
9420     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9421   },
9422   /* VEX_LEN_0F4A_P_2 */
9423   {
9424     { Bad_Opcode },
9425     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9426   },
9427   /* VEX_LEN_0F4B_P_0 */
9428   {
9429     { Bad_Opcode },
9430     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9431   },
9432   /* VEX_LEN_0F4B_P_2 */
9433   {
9434     { Bad_Opcode },
9435     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9436   },
9437
9438   /* VEX_LEN_0F6E_P_2 */
9439   {
9440     { "vmovK",          { XMScalar, Edq }, 0 },
9441   },
9442
9443   /* VEX_LEN_0F77_P_1 */
9444   {
9445     { "vzeroupper",     { XX }, 0 },
9446     { "vzeroall",       { XX }, 0 },
9447   },
9448
9449   /* VEX_LEN_0F7E_P_1 */
9450   {
9451     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9452   },
9453
9454   /* VEX_LEN_0F7E_P_2 */
9455   {
9456     { "vmovK",          { Edq, XMScalar }, 0 },
9457   },
9458
9459   /* VEX_LEN_0F90_P_0 */
9460   {
9461     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9462   },
9463
9464   /* VEX_LEN_0F90_P_2 */
9465   {
9466     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9467   },
9468
9469   /* VEX_LEN_0F91_P_0 */
9470   {
9471     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9472   },
9473
9474   /* VEX_LEN_0F91_P_2 */
9475   {
9476     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9477   },
9478
9479   /* VEX_LEN_0F92_P_0 */
9480   {
9481     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9482   },
9483
9484   /* VEX_LEN_0F92_P_2 */
9485   {
9486     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9487   },
9488
9489   /* VEX_LEN_0F92_P_3 */
9490   {
9491     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9492   },
9493
9494   /* VEX_LEN_0F93_P_0 */
9495   {
9496     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9497   },
9498
9499   /* VEX_LEN_0F93_P_2 */
9500   {
9501     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9502   },
9503
9504   /* VEX_LEN_0F93_P_3 */
9505   {
9506     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9507   },
9508
9509   /* VEX_LEN_0F98_P_0 */
9510   {
9511     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9512   },
9513
9514   /* VEX_LEN_0F98_P_2 */
9515   {
9516     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9517   },
9518
9519   /* VEX_LEN_0F99_P_0 */
9520   {
9521     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9522   },
9523
9524   /* VEX_LEN_0F99_P_2 */
9525   {
9526     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9527   },
9528
9529   /* VEX_LEN_0FAE_R_2_M_0 */
9530   {
9531     { "vldmxcsr",       { Md }, 0 },
9532   },
9533
9534   /* VEX_LEN_0FAE_R_3_M_0 */
9535   {
9536     { "vstmxcsr",       { Md }, 0 },
9537   },
9538
9539   /* VEX_LEN_0FC4_P_2 */
9540   {
9541     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9542   },
9543
9544   /* VEX_LEN_0FC5_P_2 */
9545   {
9546     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9547   },
9548
9549   /* VEX_LEN_0FD6_P_2 */
9550   {
9551     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9552   },
9553
9554   /* VEX_LEN_0FF7_P_2 */
9555   {
9556     { "vmaskmovdqu",    { XM, XS }, 0 },
9557   },
9558
9559   /* VEX_LEN_0F3816_P_2 */
9560   {
9561     { Bad_Opcode },
9562     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9563   },
9564
9565   /* VEX_LEN_0F3819_P_2 */
9566   {
9567     { Bad_Opcode },
9568     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9569   },
9570
9571   /* VEX_LEN_0F381A_P_2_M_0 */
9572   {
9573     { Bad_Opcode },
9574     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9575   },
9576
9577   /* VEX_LEN_0F3836_P_2 */
9578   {
9579     { Bad_Opcode },
9580     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9581   },
9582
9583   /* VEX_LEN_0F3841_P_2 */
9584   {
9585     { "vphminposuw",    { XM, EXx }, 0 },
9586   },
9587
9588   /* VEX_LEN_0F385A_P_2_M_0 */
9589   {
9590     { Bad_Opcode },
9591     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9592   },
9593
9594   /* VEX_LEN_0F38DB_P_2 */
9595   {
9596     { "vaesimc",        { XM, EXx }, 0 },
9597   },
9598
9599   /* VEX_LEN_0F38F2_P_0 */
9600   {
9601     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9602   },
9603
9604   /* VEX_LEN_0F38F3_R_1_P_0 */
9605   {
9606     { "blsrS",          { VexGdq, Edq }, 0 },
9607   },
9608
9609   /* VEX_LEN_0F38F3_R_2_P_0 */
9610   {
9611     { "blsmskS",        { VexGdq, Edq }, 0 },
9612   },
9613
9614   /* VEX_LEN_0F38F3_R_3_P_0 */
9615   {
9616     { "blsiS",          { VexGdq, Edq }, 0 },
9617   },
9618
9619   /* VEX_LEN_0F38F5_P_0 */
9620   {
9621     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9622   },
9623
9624   /* VEX_LEN_0F38F5_P_1 */
9625   {
9626     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9627   },
9628
9629   /* VEX_LEN_0F38F5_P_3 */
9630   {
9631     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9632   },
9633
9634   /* VEX_LEN_0F38F6_P_3 */
9635   {
9636     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9637   },
9638
9639   /* VEX_LEN_0F38F7_P_0 */
9640   {
9641     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9642   },
9643
9644   /* VEX_LEN_0F38F7_P_1 */
9645   {
9646     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9647   },
9648
9649   /* VEX_LEN_0F38F7_P_2 */
9650   {
9651     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9652   },
9653
9654   /* VEX_LEN_0F38F7_P_3 */
9655   {
9656     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9657   },
9658
9659   /* VEX_LEN_0F3A00_P_2 */
9660   {
9661     { Bad_Opcode },
9662     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9663   },
9664
9665   /* VEX_LEN_0F3A01_P_2 */
9666   {
9667     { Bad_Opcode },
9668     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9669   },
9670
9671   /* VEX_LEN_0F3A06_P_2 */
9672   {
9673     { Bad_Opcode },
9674     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9675   },
9676
9677   /* VEX_LEN_0F3A14_P_2 */
9678   {
9679     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9680   },
9681
9682   /* VEX_LEN_0F3A15_P_2 */
9683   {
9684     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9685   },
9686
9687   /* VEX_LEN_0F3A16_P_2  */
9688   {
9689     { "vpextrK",        { Edq, XM, Ib }, 0 },
9690   },
9691
9692   /* VEX_LEN_0F3A17_P_2 */
9693   {
9694     { "vextractps",     { Edqd, XM, Ib }, 0 },
9695   },
9696
9697   /* VEX_LEN_0F3A18_P_2 */
9698   {
9699     { Bad_Opcode },
9700     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9701   },
9702
9703   /* VEX_LEN_0F3A19_P_2 */
9704   {
9705     { Bad_Opcode },
9706     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9707   },
9708
9709   /* VEX_LEN_0F3A20_P_2 */
9710   {
9711     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9712   },
9713
9714   /* VEX_LEN_0F3A21_P_2 */
9715   {
9716     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9717   },
9718
9719   /* VEX_LEN_0F3A22_P_2 */
9720   {
9721     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9722   },
9723
9724   /* VEX_LEN_0F3A30_P_2 */
9725   {
9726     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9727   },
9728
9729   /* VEX_LEN_0F3A31_P_2 */
9730   {
9731     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9732   },
9733
9734   /* VEX_LEN_0F3A32_P_2 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9737   },
9738
9739   /* VEX_LEN_0F3A33_P_2 */
9740   {
9741     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9742   },
9743
9744   /* VEX_LEN_0F3A38_P_2 */
9745   {
9746     { Bad_Opcode },
9747     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9748   },
9749
9750   /* VEX_LEN_0F3A39_P_2 */
9751   {
9752     { Bad_Opcode },
9753     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9754   },
9755
9756   /* VEX_LEN_0F3A41_P_2 */
9757   {
9758     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9759   },
9760
9761   /* VEX_LEN_0F3A46_P_2 */
9762   {
9763     { Bad_Opcode },
9764     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9765   },
9766
9767   /* VEX_LEN_0F3A60_P_2 */
9768   {
9769     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9770   },
9771
9772   /* VEX_LEN_0F3A61_P_2 */
9773   {
9774     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9775   },
9776
9777   /* VEX_LEN_0F3A62_P_2 */
9778   {
9779     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9780   },
9781
9782   /* VEX_LEN_0F3A63_P_2 */
9783   {
9784     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9785   },
9786
9787   /* VEX_LEN_0F3A6A_P_2 */
9788   {
9789     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9790   },
9791
9792   /* VEX_LEN_0F3A6B_P_2 */
9793   {
9794     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9795   },
9796
9797   /* VEX_LEN_0F3A6E_P_2 */
9798   {
9799     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9800   },
9801
9802   /* VEX_LEN_0F3A6F_P_2 */
9803   {
9804     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9805   },
9806
9807   /* VEX_LEN_0F3A7A_P_2 */
9808   {
9809     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9810   },
9811
9812   /* VEX_LEN_0F3A7B_P_2 */
9813   {
9814     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9815   },
9816
9817   /* VEX_LEN_0F3A7E_P_2 */
9818   {
9819     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9820   },
9821
9822   /* VEX_LEN_0F3A7F_P_2 */
9823   {
9824     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9825   },
9826
9827   /* VEX_LEN_0F3ADF_P_2 */
9828   {
9829     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9830   },
9831
9832   /* VEX_LEN_0F3AF0_P_3 */
9833   {
9834     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9835   },
9836
9837   /* VEX_LEN_0FXOP_08_CC */
9838   {
9839      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9840   },
9841
9842   /* VEX_LEN_0FXOP_08_CD */
9843   {
9844      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9845   },
9846
9847   /* VEX_LEN_0FXOP_08_CE */
9848   {
9849      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9850   },
9851
9852   /* VEX_LEN_0FXOP_08_CF */
9853   {
9854      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9855   },
9856
9857   /* VEX_LEN_0FXOP_08_EC */
9858   {
9859      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9860   },
9861
9862   /* VEX_LEN_0FXOP_08_ED */
9863   {
9864      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9865   },
9866
9867   /* VEX_LEN_0FXOP_08_EE */
9868   {
9869      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9870   },
9871
9872   /* VEX_LEN_0FXOP_08_EF */
9873   {
9874      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9875   },
9876
9877   /* VEX_LEN_0FXOP_09_80 */
9878   {
9879     { "vfrczps",        { XM, EXxmm }, 0 },
9880     { "vfrczps",        { XM, EXymmq }, 0 },
9881   },
9882
9883   /* VEX_LEN_0FXOP_09_81 */
9884   {
9885     { "vfrczpd",        { XM, EXxmm }, 0 },
9886     { "vfrczpd",        { XM, EXymmq }, 0 },
9887   },
9888 };
9889
9890 static const struct dis386 evex_len_table[][3] = {
9891 #define NEED_EVEX_LEN_TABLE
9892 #include "i386-dis-evex.h"
9893 #undef NEED_EVEX_LEN_TABLE
9894 };
9895
9896 static const struct dis386 vex_w_table[][2] = {
9897   {
9898     /* VEX_W_0F41_P_0_LEN_1 */
9899     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9900     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9901   },
9902   {
9903     /* VEX_W_0F41_P_2_LEN_1 */
9904     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9905     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9906   },
9907   {
9908     /* VEX_W_0F42_P_0_LEN_1 */
9909     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9910     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9911   },
9912   {
9913     /* VEX_W_0F42_P_2_LEN_1 */
9914     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9915     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9916   },
9917   {
9918     /* VEX_W_0F44_P_0_LEN_0 */
9919     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9920     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9921   },
9922   {
9923     /* VEX_W_0F44_P_2_LEN_0 */
9924     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9925     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9926   },
9927   {
9928     /* VEX_W_0F45_P_0_LEN_1 */
9929     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9930     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9931   },
9932   {
9933     /* VEX_W_0F45_P_2_LEN_1 */
9934     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9935     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9936   },
9937   {
9938     /* VEX_W_0F46_P_0_LEN_1 */
9939     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9940     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9941   },
9942   {
9943     /* VEX_W_0F46_P_2_LEN_1 */
9944     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9945     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9946   },
9947   {
9948     /* VEX_W_0F47_P_0_LEN_1 */
9949     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9950     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9951   },
9952   {
9953     /* VEX_W_0F47_P_2_LEN_1 */
9954     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9955     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9956   },
9957   {
9958     /* VEX_W_0F4A_P_0_LEN_1 */
9959     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9960     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9961   },
9962   {
9963     /* VEX_W_0F4A_P_2_LEN_1 */
9964     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9965     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9966   },
9967   {
9968     /* VEX_W_0F4B_P_0_LEN_1 */
9969     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9970     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9971   },
9972   {
9973     /* VEX_W_0F4B_P_2_LEN_1 */
9974     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9975   },
9976   {
9977     /* VEX_W_0F90_P_0_LEN_0 */
9978     { "kmovw",          { MaskG, MaskE }, 0 },
9979     { "kmovq",          { MaskG, MaskE }, 0 },
9980   },
9981   {
9982     /* VEX_W_0F90_P_2_LEN_0 */
9983     { "kmovb",          { MaskG, MaskBDE }, 0 },
9984     { "kmovd",          { MaskG, MaskBDE }, 0 },
9985   },
9986   {
9987     /* VEX_W_0F91_P_0_LEN_0 */
9988     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9989     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9990   },
9991   {
9992     /* VEX_W_0F91_P_2_LEN_0 */
9993     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9994     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9995   },
9996   {
9997     /* VEX_W_0F92_P_0_LEN_0 */
9998     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9999   },
10000   {
10001     /* VEX_W_0F92_P_2_LEN_0 */
10002     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10003   },
10004   {
10005     /* VEX_W_0F93_P_0_LEN_0 */
10006     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10007   },
10008   {
10009     /* VEX_W_0F93_P_2_LEN_0 */
10010     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10011   },
10012   {
10013     /* VEX_W_0F98_P_0_LEN_0 */
10014     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10015     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10016   },
10017   {
10018     /* VEX_W_0F98_P_2_LEN_0 */
10019     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10020     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10021   },
10022   {
10023     /* VEX_W_0F99_P_0_LEN_0 */
10024     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10025     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10026   },
10027   {
10028     /* VEX_W_0F99_P_2_LEN_0 */
10029     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10030     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10031   },
10032   {
10033     /* VEX_W_0F380C_P_2  */
10034     { "vpermilps",      { XM, Vex, EXx }, 0 },
10035   },
10036   {
10037     /* VEX_W_0F380D_P_2  */
10038     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10039   },
10040   {
10041     /* VEX_W_0F380E_P_2  */
10042     { "vtestps",        { XM, EXx }, 0 },
10043   },
10044   {
10045     /* VEX_W_0F380F_P_2  */
10046     { "vtestpd",        { XM, EXx }, 0 },
10047   },
10048   {
10049     /* VEX_W_0F3816_P_2  */
10050     { "vpermps",        { XM, Vex, EXx }, 0 },
10051   },
10052   {
10053     /* VEX_W_0F3818_P_2 */
10054     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10055   },
10056   {
10057     /* VEX_W_0F3819_P_2 */
10058     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10059   },
10060   {
10061     /* VEX_W_0F381A_P_2_M_0 */
10062     { "vbroadcastf128", { XM, Mxmm }, 0 },
10063   },
10064   {
10065     /* VEX_W_0F382C_P_2_M_0 */
10066     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10067   },
10068   {
10069     /* VEX_W_0F382D_P_2_M_0 */
10070     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10071   },
10072   {
10073     /* VEX_W_0F382E_P_2_M_0 */
10074     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10075   },
10076   {
10077     /* VEX_W_0F382F_P_2_M_0 */
10078     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10079   },
10080   {
10081     /* VEX_W_0F3836_P_2  */
10082     { "vpermd",         { XM, Vex, EXx }, 0 },
10083   },
10084   {
10085     /* VEX_W_0F3846_P_2 */
10086     { "vpsravd",        { XM, Vex, EXx }, 0 },
10087   },
10088   {
10089     /* VEX_W_0F3858_P_2 */
10090     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10091   },
10092   {
10093     /* VEX_W_0F3859_P_2 */
10094     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10095   },
10096   {
10097     /* VEX_W_0F385A_P_2_M_0 */
10098     { "vbroadcasti128", { XM, Mxmm }, 0 },
10099   },
10100   {
10101     /* VEX_W_0F3878_P_2 */
10102     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10103   },
10104   {
10105     /* VEX_W_0F3879_P_2 */
10106     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10107   },
10108   {
10109     /* VEX_W_0F38CF_P_2 */
10110     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10111   },
10112   {
10113     /* VEX_W_0F3A00_P_2 */
10114     { Bad_Opcode },
10115     { "vpermq",         { XM, EXx, Ib }, 0 },
10116   },
10117   {
10118     /* VEX_W_0F3A01_P_2 */
10119     { Bad_Opcode },
10120     { "vpermpd",        { XM, EXx, Ib }, 0 },
10121   },
10122   {
10123     /* VEX_W_0F3A02_P_2 */
10124     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10125   },
10126   {
10127     /* VEX_W_0F3A04_P_2 */
10128     { "vpermilps",      { XM, EXx, Ib }, 0 },
10129   },
10130   {
10131     /* VEX_W_0F3A05_P_2 */
10132     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10133   },
10134   {
10135     /* VEX_W_0F3A06_P_2 */
10136     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10137   },
10138   {
10139     /* VEX_W_0F3A18_P_2 */
10140     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10141   },
10142   {
10143     /* VEX_W_0F3A19_P_2 */
10144     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10145   },
10146   {
10147     /* VEX_W_0F3A30_P_2_LEN_0 */
10148     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10149     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10150   },
10151   {
10152     /* VEX_W_0F3A31_P_2_LEN_0 */
10153     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10154     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10155   },
10156   {
10157     /* VEX_W_0F3A32_P_2_LEN_0 */
10158     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10159     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10160   },
10161   {
10162     /* VEX_W_0F3A33_P_2_LEN_0 */
10163     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10164     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10165   },
10166   {
10167     /* VEX_W_0F3A38_P_2 */
10168     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10169   },
10170   {
10171     /* VEX_W_0F3A39_P_2 */
10172     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10173   },
10174   {
10175     /* VEX_W_0F3A46_P_2 */
10176     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10177   },
10178   {
10179     /* VEX_W_0F3A48_P_2 */
10180     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10181     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10182   },
10183   {
10184     /* VEX_W_0F3A49_P_2 */
10185     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10186     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10187   },
10188   {
10189     /* VEX_W_0F3A4A_P_2 */
10190     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10191   },
10192   {
10193     /* VEX_W_0F3A4B_P_2 */
10194     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10195   },
10196   {
10197     /* VEX_W_0F3A4C_P_2 */
10198     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10199   },
10200   {
10201     /* VEX_W_0F3ACE_P_2 */
10202     { Bad_Opcode },
10203     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10204   },
10205   {
10206     /* VEX_W_0F3ACF_P_2 */
10207     { Bad_Opcode },
10208     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10209   },
10210 #define NEED_VEX_W_TABLE
10211 #include "i386-dis-evex.h"
10212 #undef NEED_VEX_W_TABLE
10213 };
10214
10215 static const struct dis386 mod_table[][2] = {
10216   {
10217     /* MOD_8D */
10218     { "leaS",           { Gv, M }, 0 },
10219   },
10220   {
10221     /* MOD_C6_REG_7 */
10222     { Bad_Opcode },
10223     { RM_TABLE (RM_C6_REG_7) },
10224   },
10225   {
10226     /* MOD_C7_REG_7 */
10227     { Bad_Opcode },
10228     { RM_TABLE (RM_C7_REG_7) },
10229   },
10230   {
10231     /* MOD_FF_REG_3 */
10232     { "Jcall^", { indirEp }, 0 },
10233   },
10234   {
10235     /* MOD_FF_REG_5 */
10236     { "Jjmp^", { indirEp }, 0 },
10237   },
10238   {
10239     /* MOD_0F01_REG_0 */
10240     { X86_64_TABLE (X86_64_0F01_REG_0) },
10241     { RM_TABLE (RM_0F01_REG_0) },
10242   },
10243   {
10244     /* MOD_0F01_REG_1 */
10245     { X86_64_TABLE (X86_64_0F01_REG_1) },
10246     { RM_TABLE (RM_0F01_REG_1) },
10247   },
10248   {
10249     /* MOD_0F01_REG_2 */
10250     { X86_64_TABLE (X86_64_0F01_REG_2) },
10251     { RM_TABLE (RM_0F01_REG_2) },
10252   },
10253   {
10254     /* MOD_0F01_REG_3 */
10255     { X86_64_TABLE (X86_64_0F01_REG_3) },
10256     { RM_TABLE (RM_0F01_REG_3) },
10257   },
10258   {
10259     /* MOD_0F01_REG_5 */
10260     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10261     { RM_TABLE (RM_0F01_REG_5) },
10262   },
10263   {
10264     /* MOD_0F01_REG_7 */
10265     { "invlpg",         { Mb }, 0 },
10266     { RM_TABLE (RM_0F01_REG_7) },
10267   },
10268   {
10269     /* MOD_0F12_PREFIX_0 */
10270     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10271     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10272   },
10273   {
10274     /* MOD_0F13 */
10275     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10276   },
10277   {
10278     /* MOD_0F16_PREFIX_0 */
10279     { "movhps",         { XM, EXq }, 0 },
10280     { "movlhps",        { XM, EXq }, 0 },
10281   },
10282   {
10283     /* MOD_0F17 */
10284     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10285   },
10286   {
10287     /* MOD_0F18_REG_0 */
10288     { "prefetchnta",    { Mb }, 0 },
10289   },
10290   {
10291     /* MOD_0F18_REG_1 */
10292     { "prefetcht0",     { Mb }, 0 },
10293   },
10294   {
10295     /* MOD_0F18_REG_2 */
10296     { "prefetcht1",     { Mb }, 0 },
10297   },
10298   {
10299     /* MOD_0F18_REG_3 */
10300     { "prefetcht2",     { Mb }, 0 },
10301   },
10302   {
10303     /* MOD_0F18_REG_4 */
10304     { "nop/reserved",   { Mb }, 0 },
10305   },
10306   {
10307     /* MOD_0F18_REG_5 */
10308     { "nop/reserved",   { Mb }, 0 },
10309   },
10310   {
10311     /* MOD_0F18_REG_6 */
10312     { "nop/reserved",   { Mb }, 0 },
10313   },
10314   {
10315     /* MOD_0F18_REG_7 */
10316     { "nop/reserved",   { Mb }, 0 },
10317   },
10318   {
10319     /* MOD_0F1A_PREFIX_0 */
10320     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10321     { "nopQ",           { Ev }, 0 },
10322   },
10323   {
10324     /* MOD_0F1B_PREFIX_0 */
10325     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10326     { "nopQ",           { Ev }, 0 },
10327   },
10328   {
10329     /* MOD_0F1B_PREFIX_1 */
10330     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10331     { "nopQ",           { Ev }, 0 },
10332   },
10333   {
10334     /* MOD_0F1C_PREFIX_0 */
10335     { REG_TABLE (REG_0F1C_MOD_0) },
10336     { "nopQ",           { Ev }, 0 },
10337   },
10338   {
10339     /* MOD_0F1E_PREFIX_1 */
10340     { "nopQ",           { Ev }, 0 },
10341     { REG_TABLE (REG_0F1E_MOD_3) },
10342   },
10343   {
10344     /* MOD_0F24 */
10345     { Bad_Opcode },
10346     { "movL",           { Rd, Td }, 0 },
10347   },
10348   {
10349     /* MOD_0F26 */
10350     { Bad_Opcode },
10351     { "movL",           { Td, Rd }, 0 },
10352   },
10353   {
10354     /* MOD_0F2B_PREFIX_0 */
10355     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10356   },
10357   {
10358     /* MOD_0F2B_PREFIX_1 */
10359     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10360   },
10361   {
10362     /* MOD_0F2B_PREFIX_2 */
10363     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10364   },
10365   {
10366     /* MOD_0F2B_PREFIX_3 */
10367     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10368   },
10369   {
10370     /* MOD_0F51 */
10371     { Bad_Opcode },
10372     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10373   },
10374   {
10375     /* MOD_0F71_REG_2 */
10376     { Bad_Opcode },
10377     { "psrlw",          { MS, Ib }, 0 },
10378   },
10379   {
10380     /* MOD_0F71_REG_4 */
10381     { Bad_Opcode },
10382     { "psraw",          { MS, Ib }, 0 },
10383   },
10384   {
10385     /* MOD_0F71_REG_6 */
10386     { Bad_Opcode },
10387     { "psllw",          { MS, Ib }, 0 },
10388   },
10389   {
10390     /* MOD_0F72_REG_2 */
10391     { Bad_Opcode },
10392     { "psrld",          { MS, Ib }, 0 },
10393   },
10394   {
10395     /* MOD_0F72_REG_4 */
10396     { Bad_Opcode },
10397     { "psrad",          { MS, Ib }, 0 },
10398   },
10399   {
10400     /* MOD_0F72_REG_6 */
10401     { Bad_Opcode },
10402     { "pslld",          { MS, Ib }, 0 },
10403   },
10404   {
10405     /* MOD_0F73_REG_2 */
10406     { Bad_Opcode },
10407     { "psrlq",          { MS, Ib }, 0 },
10408   },
10409   {
10410     /* MOD_0F73_REG_3 */
10411     { Bad_Opcode },
10412     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10413   },
10414   {
10415     /* MOD_0F73_REG_6 */
10416     { Bad_Opcode },
10417     { "psllq",          { MS, Ib }, 0 },
10418   },
10419   {
10420     /* MOD_0F73_REG_7 */
10421     { Bad_Opcode },
10422     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10423   },
10424   {
10425     /* MOD_0FAE_REG_0 */
10426     { "fxsave",         { FXSAVE }, 0 },
10427     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10428   },
10429   {
10430     /* MOD_0FAE_REG_1 */
10431     { "fxrstor",        { FXSAVE }, 0 },
10432     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10433   },
10434   {
10435     /* MOD_0FAE_REG_2 */
10436     { "ldmxcsr",        { Md }, 0 },
10437     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10438   },
10439   {
10440     /* MOD_0FAE_REG_3 */
10441     { "stmxcsr",        { Md }, 0 },
10442     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10443   },
10444   {
10445     /* MOD_0FAE_REG_4 */
10446     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10447     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10448   },
10449   {
10450     /* MOD_0FAE_REG_5 */
10451     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10452     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10453   },
10454   {
10455     /* MOD_0FAE_REG_6 */
10456     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10457     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10458   },
10459   {
10460     /* MOD_0FAE_REG_7 */
10461     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10462     { RM_TABLE (RM_0FAE_REG_7) },
10463   },
10464   {
10465     /* MOD_0FB2 */
10466     { "lssS",           { Gv, Mp }, 0 },
10467   },
10468   {
10469     /* MOD_0FB4 */
10470     { "lfsS",           { Gv, Mp }, 0 },
10471   },
10472   {
10473     /* MOD_0FB5 */
10474     { "lgsS",           { Gv, Mp }, 0 },
10475   },
10476   {
10477     /* MOD_0FC3 */
10478     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10479   },
10480   {
10481     /* MOD_0FC7_REG_3 */
10482     { "xrstors",        { FXSAVE }, 0 },
10483   },
10484   {
10485     /* MOD_0FC7_REG_4 */
10486     { "xsavec",         { FXSAVE }, 0 },
10487   },
10488   {
10489     /* MOD_0FC7_REG_5 */
10490     { "xsaves",         { FXSAVE }, 0 },
10491   },
10492   {
10493     /* MOD_0FC7_REG_6 */
10494     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10495     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10496   },
10497   {
10498     /* MOD_0FC7_REG_7 */
10499     { "vmptrst",        { Mq }, 0 },
10500     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10501   },
10502   {
10503     /* MOD_0FD7 */
10504     { Bad_Opcode },
10505     { "pmovmskb",       { Gdq, MS }, 0 },
10506   },
10507   {
10508     /* MOD_0FE7_PREFIX_2 */
10509     { "movntdq",        { Mx, XM }, 0 },
10510   },
10511   {
10512     /* MOD_0FF0_PREFIX_3 */
10513     { "lddqu",          { XM, M }, 0 },
10514   },
10515   {
10516     /* MOD_0F382A_PREFIX_2 */
10517     { "movntdqa",       { XM, Mx }, 0 },
10518   },
10519   {
10520     /* MOD_0F38F5_PREFIX_2 */
10521     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10522   },
10523   {
10524     /* MOD_0F38F6_PREFIX_0 */
10525     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10526   },
10527   {
10528     /* MOD_0F38F8_PREFIX_1 */
10529     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10530   },
10531   {
10532     /* MOD_0F38F8_PREFIX_2 */
10533     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10534   },
10535   {
10536     /* MOD_0F38F8_PREFIX_3 */
10537     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10538   },
10539   {
10540     /* MOD_0F38F9_PREFIX_0 */
10541     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10542   },
10543   {
10544     /* MOD_62_32BIT */
10545     { "bound{S|}",      { Gv, Ma }, 0 },
10546     { EVEX_TABLE (EVEX_0F) },
10547   },
10548   {
10549     /* MOD_C4_32BIT */
10550     { "lesS",           { Gv, Mp }, 0 },
10551     { VEX_C4_TABLE (VEX_0F) },
10552   },
10553   {
10554     /* MOD_C5_32BIT */
10555     { "ldsS",           { Gv, Mp }, 0 },
10556     { VEX_C5_TABLE (VEX_0F) },
10557   },
10558   {
10559     /* MOD_VEX_0F12_PREFIX_0 */
10560     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10561     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10562   },
10563   {
10564     /* MOD_VEX_0F13 */
10565     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10566   },
10567   {
10568     /* MOD_VEX_0F16_PREFIX_0 */
10569     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10570     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10571   },
10572   {
10573     /* MOD_VEX_0F17 */
10574     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10575   },
10576   {
10577     /* MOD_VEX_0F2B */
10578     { "vmovntpX",       { Mx, XM }, 0 },
10579   },
10580   {
10581     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10582     { Bad_Opcode },
10583     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10584   },
10585   {
10586     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10587     { Bad_Opcode },
10588     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10589   },
10590   {
10591     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10592     { Bad_Opcode },
10593     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10594   },
10595   {
10596     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10597     { Bad_Opcode },
10598     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10599   },
10600   {
10601     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10602     { Bad_Opcode },
10603     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10604   },
10605   {
10606     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10607     { Bad_Opcode },
10608     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10609   },
10610   {
10611     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10612     { Bad_Opcode },
10613     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10614   },
10615   {
10616     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10617     { Bad_Opcode },
10618     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10619   },
10620   {
10621     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10622     { Bad_Opcode },
10623     { "knotw",          { MaskG, MaskR }, 0 },
10624   },
10625   {
10626     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10627     { Bad_Opcode },
10628     { "knotq",          { MaskG, MaskR }, 0 },
10629   },
10630   {
10631     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10632     { Bad_Opcode },
10633     { "knotb",          { MaskG, MaskR }, 0 },
10634   },
10635   {
10636     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10637     { Bad_Opcode },
10638     { "knotd",          { MaskG, MaskR }, 0 },
10639   },
10640   {
10641     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10642     { Bad_Opcode },
10643     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10644   },
10645   {
10646     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10647     { Bad_Opcode },
10648     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10649   },
10650   {
10651     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10652     { Bad_Opcode },
10653     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10654   },
10655   {
10656     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10657     { Bad_Opcode },
10658     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10659   },
10660  {
10661     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10662     { Bad_Opcode },
10663     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10664   },
10665   {
10666     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10667     { Bad_Opcode },
10668     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10669   },
10670   {
10671     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10672     { Bad_Opcode },
10673     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10674   },
10675   {
10676     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10677     { Bad_Opcode },
10678     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10679   },
10680   {
10681     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10682     { Bad_Opcode },
10683     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10684   },
10685   {
10686     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10687     { Bad_Opcode },
10688     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10689   },
10690   {
10691     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10692     { Bad_Opcode },
10693     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10694   },
10695   {
10696     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10697     { Bad_Opcode },
10698     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10699   },
10700   {
10701     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10702     { Bad_Opcode },
10703     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10704   },
10705   {
10706     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10707     { Bad_Opcode },
10708     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10709   },
10710   {
10711     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10712     { Bad_Opcode },
10713     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10714   },
10715   {
10716     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10717     { Bad_Opcode },
10718     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10719   },
10720   {
10721     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10722     { Bad_Opcode },
10723     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10724   },
10725   {
10726     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10727     { Bad_Opcode },
10728     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10729   },
10730   {
10731     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10732     { Bad_Opcode },
10733     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10734   },
10735   {
10736     /* MOD_VEX_0F50 */
10737     { Bad_Opcode },
10738     { "vmovmskpX",      { Gdq, XS }, 0 },
10739   },
10740   {
10741     /* MOD_VEX_0F71_REG_2 */
10742     { Bad_Opcode },
10743     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10744   },
10745   {
10746     /* MOD_VEX_0F71_REG_4 */
10747     { Bad_Opcode },
10748     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10749   },
10750   {
10751     /* MOD_VEX_0F71_REG_6 */
10752     { Bad_Opcode },
10753     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10754   },
10755   {
10756     /* MOD_VEX_0F72_REG_2 */
10757     { Bad_Opcode },
10758     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10759   },
10760   {
10761     /* MOD_VEX_0F72_REG_4 */
10762     { Bad_Opcode },
10763     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10764   },
10765   {
10766     /* MOD_VEX_0F72_REG_6 */
10767     { Bad_Opcode },
10768     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10769   },
10770   {
10771     /* MOD_VEX_0F73_REG_2 */
10772     { Bad_Opcode },
10773     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10774   },
10775   {
10776     /* MOD_VEX_0F73_REG_3 */
10777     { Bad_Opcode },
10778     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10779   },
10780   {
10781     /* MOD_VEX_0F73_REG_6 */
10782     { Bad_Opcode },
10783     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10784   },
10785   {
10786     /* MOD_VEX_0F73_REG_7 */
10787     { Bad_Opcode },
10788     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10789   },
10790   {
10791     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10792     { "kmovw",          { Ew, MaskG }, 0 },
10793     { Bad_Opcode },
10794   },
10795   {
10796     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10797     { "kmovq",          { Eq, MaskG }, 0 },
10798     { Bad_Opcode },
10799   },
10800   {
10801     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10802     { "kmovb",          { Eb, MaskG }, 0 },
10803     { Bad_Opcode },
10804   },
10805   {
10806     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10807     { "kmovd",          { Ed, MaskG }, 0 },
10808     { Bad_Opcode },
10809   },
10810   {
10811     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10812     { Bad_Opcode },
10813     { "kmovw",          { MaskG, Rdq }, 0 },
10814   },
10815   {
10816     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10817     { Bad_Opcode },
10818     { "kmovb",          { MaskG, Rdq }, 0 },
10819   },
10820   {
10821     /* MOD_VEX_0F92_P_3_LEN_0 */
10822     { Bad_Opcode },
10823     { "kmovK",          { MaskG, Rdq }, 0 },
10824   },
10825   {
10826     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10827     { Bad_Opcode },
10828     { "kmovw",          { Gdq, MaskR }, 0 },
10829   },
10830   {
10831     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10832     { Bad_Opcode },
10833     { "kmovb",          { Gdq, MaskR }, 0 },
10834   },
10835   {
10836     /* MOD_VEX_0F93_P_3_LEN_0 */
10837     { Bad_Opcode },
10838     { "kmovK",          { Gdq, MaskR }, 0 },
10839   },
10840   {
10841     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10842     { Bad_Opcode },
10843     { "kortestw", { MaskG, MaskR }, 0 },
10844   },
10845   {
10846     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10847     { Bad_Opcode },
10848     { "kortestq", { MaskG, MaskR }, 0 },
10849   },
10850   {
10851     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10852     { Bad_Opcode },
10853     { "kortestb", { MaskG, MaskR }, 0 },
10854   },
10855   {
10856     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10857     { Bad_Opcode },
10858     { "kortestd", { MaskG, MaskR }, 0 },
10859   },
10860   {
10861     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10862     { Bad_Opcode },
10863     { "ktestw", { MaskG, MaskR }, 0 },
10864   },
10865   {
10866     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10867     { Bad_Opcode },
10868     { "ktestq", { MaskG, MaskR }, 0 },
10869   },
10870   {
10871     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10872     { Bad_Opcode },
10873     { "ktestb", { MaskG, MaskR }, 0 },
10874   },
10875   {
10876     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10877     { Bad_Opcode },
10878     { "ktestd", { MaskG, MaskR }, 0 },
10879   },
10880   {
10881     /* MOD_VEX_0FAE_REG_2 */
10882     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10883   },
10884   {
10885     /* MOD_VEX_0FAE_REG_3 */
10886     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10887   },
10888   {
10889     /* MOD_VEX_0FD7_PREFIX_2 */
10890     { Bad_Opcode },
10891     { "vpmovmskb",      { Gdq, XS }, 0 },
10892   },
10893   {
10894     /* MOD_VEX_0FE7_PREFIX_2 */
10895     { "vmovntdq",       { Mx, XM }, 0 },
10896   },
10897   {
10898     /* MOD_VEX_0FF0_PREFIX_3 */
10899     { "vlddqu",         { XM, M }, 0 },
10900   },
10901   {
10902     /* MOD_VEX_0F381A_PREFIX_2 */
10903     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10904   },
10905   {
10906     /* MOD_VEX_0F382A_PREFIX_2 */
10907     { "vmovntdqa",      { XM, Mx }, 0 },
10908   },
10909   {
10910     /* MOD_VEX_0F382C_PREFIX_2 */
10911     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10912   },
10913   {
10914     /* MOD_VEX_0F382D_PREFIX_2 */
10915     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10916   },
10917   {
10918     /* MOD_VEX_0F382E_PREFIX_2 */
10919     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10920   },
10921   {
10922     /* MOD_VEX_0F382F_PREFIX_2 */
10923     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10924   },
10925   {
10926     /* MOD_VEX_0F385A_PREFIX_2 */
10927     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10928   },
10929   {
10930     /* MOD_VEX_0F388C_PREFIX_2 */
10931     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10932   },
10933   {
10934     /* MOD_VEX_0F388E_PREFIX_2 */
10935     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10936   },
10937   {
10938     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10939     { Bad_Opcode },
10940     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10941   },
10942   {
10943     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10944     { Bad_Opcode },
10945     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10946   },
10947   {
10948     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10949     { Bad_Opcode },
10950     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10951   },
10952   {
10953     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10954     { Bad_Opcode },
10955     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10956   },
10957   {
10958     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10959     { Bad_Opcode },
10960     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10961   },
10962   {
10963     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10964     { Bad_Opcode },
10965     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10966   },
10967   {
10968     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10969     { Bad_Opcode },
10970     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10971   },
10972   {
10973     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10974     { Bad_Opcode },
10975     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10976   },
10977 #define NEED_MOD_TABLE
10978 #include "i386-dis-evex.h"
10979 #undef NEED_MOD_TABLE
10980 };
10981
10982 static const struct dis386 rm_table[][8] = {
10983   {
10984     /* RM_C6_REG_7 */
10985     { "xabort",         { Skip_MODRM, Ib }, 0 },
10986   },
10987   {
10988     /* RM_C7_REG_7 */
10989     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
10990   },
10991   {
10992     /* RM_0F01_REG_0 */
10993     { "enclv",          { Skip_MODRM }, 0 },
10994     { "vmcall",         { Skip_MODRM }, 0 },
10995     { "vmlaunch",       { Skip_MODRM }, 0 },
10996     { "vmresume",       { Skip_MODRM }, 0 },
10997     { "vmxoff",         { Skip_MODRM }, 0 },
10998     { "pconfig",        { Skip_MODRM }, 0 },
10999   },
11000   {
11001     /* RM_0F01_REG_1 */
11002     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11003     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11004     { "clac",           { Skip_MODRM }, 0 },
11005     { "stac",           { Skip_MODRM }, 0 },
11006     { Bad_Opcode },
11007     { Bad_Opcode },
11008     { Bad_Opcode },
11009     { "encls",          { Skip_MODRM }, 0 },
11010   },
11011   {
11012     /* RM_0F01_REG_2 */
11013     { "xgetbv",         { Skip_MODRM }, 0 },
11014     { "xsetbv",         { Skip_MODRM }, 0 },
11015     { Bad_Opcode },
11016     { Bad_Opcode },
11017     { "vmfunc",         { Skip_MODRM }, 0 },
11018     { "xend",           { Skip_MODRM }, 0 },
11019     { "xtest",          { Skip_MODRM }, 0 },
11020     { "enclu",          { Skip_MODRM }, 0 },
11021   },
11022   {
11023     /* RM_0F01_REG_3 */
11024     { "vmrun",          { Skip_MODRM }, 0 },
11025     { "vmmcall",        { Skip_MODRM }, 0 },
11026     { "vmload",         { Skip_MODRM }, 0 },
11027     { "vmsave",         { Skip_MODRM }, 0 },
11028     { "stgi",           { Skip_MODRM }, 0 },
11029     { "clgi",           { Skip_MODRM }, 0 },
11030     { "skinit",         { Skip_MODRM }, 0 },
11031     { "invlpga",        { Skip_MODRM }, 0 },
11032   },
11033   {
11034     /* RM_0F01_REG_5 */
11035     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11036     { Bad_Opcode },
11037     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11038     { Bad_Opcode },
11039     { Bad_Opcode },
11040     { Bad_Opcode },
11041     { "rdpkru",         { Skip_MODRM }, 0 },
11042     { "wrpkru",         { Skip_MODRM }, 0 },
11043   },
11044   {
11045     /* RM_0F01_REG_7 */
11046     { "swapgs",         { Skip_MODRM }, 0  },
11047     { "rdtscp",         { Skip_MODRM }, 0  },
11048     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
11049     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
11050     { "clzero",         { Skip_MODRM }, 0  },
11051   },
11052   {
11053     /* RM_0F1E_MOD_3_REG_7 */
11054     { "nopQ",           { Ev }, 0 },
11055     { "nopQ",           { Ev }, 0 },
11056     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11057     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11058     { "nopQ",           { Ev }, 0 },
11059     { "nopQ",           { Ev }, 0 },
11060     { "nopQ",           { Ev }, 0 },
11061     { "nopQ",           { Ev }, 0 },
11062   },
11063   {
11064     /* RM_0FAE_REG_6 */
11065     { "mfence",         { Skip_MODRM }, 0 },
11066   },
11067   {
11068     /* RM_0FAE_REG_7 */
11069     { "sfence",         { Skip_MODRM }, 0 },
11070
11071   },
11072 };
11073
11074 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11075
11076 /* We use the high bit to indicate different name for the same
11077    prefix.  */
11078 #define REP_PREFIX      (0xf3 | 0x100)
11079 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11080 #define XRELEASE_PREFIX (0xf3 | 0x400)
11081 #define BND_PREFIX      (0xf2 | 0x400)
11082 #define NOTRACK_PREFIX  (0x3e | 0x100)
11083
11084 static int
11085 ckprefix (void)
11086 {
11087   int newrex, i, length;
11088   rex = 0;
11089   rex_ignored = 0;
11090   prefixes = 0;
11091   used_prefixes = 0;
11092   rex_used = 0;
11093   last_lock_prefix = -1;
11094   last_repz_prefix = -1;
11095   last_repnz_prefix = -1;
11096   last_data_prefix = -1;
11097   last_addr_prefix = -1;
11098   last_rex_prefix = -1;
11099   last_seg_prefix = -1;
11100   fwait_prefix = -1;
11101   active_seg_prefix = 0;
11102   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11103     all_prefixes[i] = 0;
11104   i = 0;
11105   length = 0;
11106   /* The maximum instruction length is 15bytes.  */
11107   while (length < MAX_CODE_LENGTH - 1)
11108     {
11109       FETCH_DATA (the_info, codep + 1);
11110       newrex = 0;
11111       switch (*codep)
11112         {
11113         /* REX prefixes family.  */
11114         case 0x40:
11115         case 0x41:
11116         case 0x42:
11117         case 0x43:
11118         case 0x44:
11119         case 0x45:
11120         case 0x46:
11121         case 0x47:
11122         case 0x48:
11123         case 0x49:
11124         case 0x4a:
11125         case 0x4b:
11126         case 0x4c:
11127         case 0x4d:
11128         case 0x4e:
11129         case 0x4f:
11130           if (address_mode == mode_64bit)
11131             newrex = *codep;
11132           else
11133             return 1;
11134           last_rex_prefix = i;
11135           break;
11136         case 0xf3:
11137           prefixes |= PREFIX_REPZ;
11138           last_repz_prefix = i;
11139           break;
11140         case 0xf2:
11141           prefixes |= PREFIX_REPNZ;
11142           last_repnz_prefix = i;
11143           break;
11144         case 0xf0:
11145           prefixes |= PREFIX_LOCK;
11146           last_lock_prefix = i;
11147           break;
11148         case 0x2e:
11149           prefixes |= PREFIX_CS;
11150           last_seg_prefix = i;
11151           active_seg_prefix = PREFIX_CS;
11152           break;
11153         case 0x36:
11154           prefixes |= PREFIX_SS;
11155           last_seg_prefix = i;
11156           active_seg_prefix = PREFIX_SS;
11157           break;
11158         case 0x3e:
11159           prefixes |= PREFIX_DS;
11160           last_seg_prefix = i;
11161           active_seg_prefix = PREFIX_DS;
11162           break;
11163         case 0x26:
11164           prefixes |= PREFIX_ES;
11165           last_seg_prefix = i;
11166           active_seg_prefix = PREFIX_ES;
11167           break;
11168         case 0x64:
11169           prefixes |= PREFIX_FS;
11170           last_seg_prefix = i;
11171           active_seg_prefix = PREFIX_FS;
11172           break;
11173         case 0x65:
11174           prefixes |= PREFIX_GS;
11175           last_seg_prefix = i;
11176           active_seg_prefix = PREFIX_GS;
11177           break;
11178         case 0x66:
11179           prefixes |= PREFIX_DATA;
11180           last_data_prefix = i;
11181           break;
11182         case 0x67:
11183           prefixes |= PREFIX_ADDR;
11184           last_addr_prefix = i;
11185           break;
11186         case FWAIT_OPCODE:
11187           /* fwait is really an instruction.  If there are prefixes
11188              before the fwait, they belong to the fwait, *not* to the
11189              following instruction.  */
11190           fwait_prefix = i;
11191           if (prefixes || rex)
11192             {
11193               prefixes |= PREFIX_FWAIT;
11194               codep++;
11195               /* This ensures that the previous REX prefixes are noticed
11196                  as unused prefixes, as in the return case below.  */
11197               rex_used = rex;
11198               return 1;
11199             }
11200           prefixes = PREFIX_FWAIT;
11201           break;
11202         default:
11203           return 1;
11204         }
11205       /* Rex is ignored when followed by another prefix.  */
11206       if (rex)
11207         {
11208           rex_used = rex;
11209           return 1;
11210         }
11211       if (*codep != FWAIT_OPCODE)
11212         all_prefixes[i++] = *codep;
11213       rex = newrex;
11214       codep++;
11215       length++;
11216     }
11217   return 0;
11218 }
11219
11220 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11221    prefix byte.  */
11222
11223 static const char *
11224 prefix_name (int pref, int sizeflag)
11225 {
11226   static const char *rexes [16] =
11227     {
11228       "rex",            /* 0x40 */
11229       "rex.B",          /* 0x41 */
11230       "rex.X",          /* 0x42 */
11231       "rex.XB",         /* 0x43 */
11232       "rex.R",          /* 0x44 */
11233       "rex.RB",         /* 0x45 */
11234       "rex.RX",         /* 0x46 */
11235       "rex.RXB",        /* 0x47 */
11236       "rex.W",          /* 0x48 */
11237       "rex.WB",         /* 0x49 */
11238       "rex.WX",         /* 0x4a */
11239       "rex.WXB",        /* 0x4b */
11240       "rex.WR",         /* 0x4c */
11241       "rex.WRB",        /* 0x4d */
11242       "rex.WRX",        /* 0x4e */
11243       "rex.WRXB",       /* 0x4f */
11244     };
11245
11246   switch (pref)
11247     {
11248     /* REX prefixes family.  */
11249     case 0x40:
11250     case 0x41:
11251     case 0x42:
11252     case 0x43:
11253     case 0x44:
11254     case 0x45:
11255     case 0x46:
11256     case 0x47:
11257     case 0x48:
11258     case 0x49:
11259     case 0x4a:
11260     case 0x4b:
11261     case 0x4c:
11262     case 0x4d:
11263     case 0x4e:
11264     case 0x4f:
11265       return rexes [pref - 0x40];
11266     case 0xf3:
11267       return "repz";
11268     case 0xf2:
11269       return "repnz";
11270     case 0xf0:
11271       return "lock";
11272     case 0x2e:
11273       return "cs";
11274     case 0x36:
11275       return "ss";
11276     case 0x3e:
11277       return "ds";
11278     case 0x26:
11279       return "es";
11280     case 0x64:
11281       return "fs";
11282     case 0x65:
11283       return "gs";
11284     case 0x66:
11285       return (sizeflag & DFLAG) ? "data16" : "data32";
11286     case 0x67:
11287       if (address_mode == mode_64bit)
11288         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11289       else
11290         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11291     case FWAIT_OPCODE:
11292       return "fwait";
11293     case REP_PREFIX:
11294       return "rep";
11295     case XACQUIRE_PREFIX:
11296       return "xacquire";
11297     case XRELEASE_PREFIX:
11298       return "xrelease";
11299     case BND_PREFIX:
11300       return "bnd";
11301     case NOTRACK_PREFIX:
11302       return "notrack";
11303     default:
11304       return NULL;
11305     }
11306 }
11307
11308 static char op_out[MAX_OPERANDS][100];
11309 static int op_ad, op_index[MAX_OPERANDS];
11310 static int two_source_ops;
11311 static bfd_vma op_address[MAX_OPERANDS];
11312 static bfd_vma op_riprel[MAX_OPERANDS];
11313 static bfd_vma start_pc;
11314
11315 /*
11316  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11317  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11318  *   section of the "Virtual 8086 Mode" chapter.)
11319  * 'pc' should be the address of this instruction, it will
11320  *   be used to print the target address if this is a relative jump or call
11321  * The function returns the length of this instruction in bytes.
11322  */
11323
11324 static char intel_syntax;
11325 static char intel_mnemonic = !SYSV386_COMPAT;
11326 static char open_char;
11327 static char close_char;
11328 static char separator_char;
11329 static char scale_char;
11330
11331 enum x86_64_isa
11332 {
11333   amd64 = 0,
11334   intel64
11335 };
11336
11337 static enum x86_64_isa isa64;
11338
11339 /* Here for backwards compatibility.  When gdb stops using
11340    print_insn_i386_att and print_insn_i386_intel these functions can
11341    disappear, and print_insn_i386 be merged into print_insn.  */
11342 int
11343 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11344 {
11345   intel_syntax = 0;
11346
11347   return print_insn (pc, info);
11348 }
11349
11350 int
11351 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11352 {
11353   intel_syntax = 1;
11354
11355   return print_insn (pc, info);
11356 }
11357
11358 int
11359 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11360 {
11361   intel_syntax = -1;
11362
11363   return print_insn (pc, info);
11364 }
11365
11366 void
11367 print_i386_disassembler_options (FILE *stream)
11368 {
11369   fprintf (stream, _("\n\
11370 The following i386/x86-64 specific disassembler options are supported for use\n\
11371 with the -M switch (multiple options should be separated by commas):\n"));
11372
11373   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11374   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11375   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11376   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11377   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11378   fprintf (stream, _("  att-mnemonic\n"
11379                      "              Display instruction in AT&T mnemonic\n"));
11380   fprintf (stream, _("  intel-mnemonic\n"
11381                      "              Display instruction in Intel mnemonic\n"));
11382   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11383   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11384   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11385   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11386   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11387   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11388   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11389   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11390 }
11391
11392 /* Bad opcode.  */
11393 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11394
11395 /* Get a pointer to struct dis386 with a valid name.  */
11396
11397 static const struct dis386 *
11398 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11399 {
11400   int vindex, vex_table_index;
11401
11402   if (dp->name != NULL)
11403     return dp;
11404
11405   switch (dp->op[0].bytemode)
11406     {
11407     case USE_REG_TABLE:
11408       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11409       break;
11410
11411     case USE_MOD_TABLE:
11412       vindex = modrm.mod == 0x3 ? 1 : 0;
11413       dp = &mod_table[dp->op[1].bytemode][vindex];
11414       break;
11415
11416     case USE_RM_TABLE:
11417       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11418       break;
11419
11420     case USE_PREFIX_TABLE:
11421       if (need_vex)
11422         {
11423           /* The prefix in VEX is implicit.  */
11424           switch (vex.prefix)
11425             {
11426             case 0:
11427               vindex = 0;
11428               break;
11429             case REPE_PREFIX_OPCODE:
11430               vindex = 1;
11431               break;
11432             case DATA_PREFIX_OPCODE:
11433               vindex = 2;
11434               break;
11435             case REPNE_PREFIX_OPCODE:
11436               vindex = 3;
11437               break;
11438             default:
11439               abort ();
11440               break;
11441             }
11442         }
11443       else
11444         {
11445           int last_prefix = -1;
11446           int prefix = 0;
11447           vindex = 0;
11448           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11449              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11450              last one wins.  */
11451           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11452             {
11453               if (last_repz_prefix > last_repnz_prefix)
11454                 {
11455                   vindex = 1;
11456                   prefix = PREFIX_REPZ;
11457                   last_prefix = last_repz_prefix;
11458                 }
11459               else
11460                 {
11461                   vindex = 3;
11462                   prefix = PREFIX_REPNZ;
11463                   last_prefix = last_repnz_prefix;
11464                 }
11465
11466               /* Check if prefix should be ignored.  */
11467               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11468                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11469                    & prefix) != 0)
11470                 vindex = 0;
11471             }
11472
11473           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11474             {
11475               vindex = 2;
11476               prefix = PREFIX_DATA;
11477               last_prefix = last_data_prefix;
11478             }
11479
11480           if (vindex != 0)
11481             {
11482               used_prefixes |= prefix;
11483               all_prefixes[last_prefix] = 0;
11484             }
11485         }
11486       dp = &prefix_table[dp->op[1].bytemode][vindex];
11487       break;
11488
11489     case USE_X86_64_TABLE:
11490       vindex = address_mode == mode_64bit ? 1 : 0;
11491       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11492       break;
11493
11494     case USE_3BYTE_TABLE:
11495       FETCH_DATA (info, codep + 2);
11496       vindex = *codep++;
11497       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11498       end_codep = codep;
11499       modrm.mod = (*codep >> 6) & 3;
11500       modrm.reg = (*codep >> 3) & 7;
11501       modrm.rm = *codep & 7;
11502       break;
11503
11504     case USE_VEX_LEN_TABLE:
11505       if (!need_vex)
11506         abort ();
11507
11508       switch (vex.length)
11509         {
11510         case 128:
11511           vindex = 0;
11512           break;
11513         case 256:
11514           vindex = 1;
11515           break;
11516         default:
11517           abort ();
11518           break;
11519         }
11520
11521       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11522       break;
11523
11524     case USE_EVEX_LEN_TABLE:
11525       if (!vex.evex)
11526         abort ();
11527
11528       switch (vex.length)
11529         {
11530         case 128:
11531           vindex = 0;
11532           break;
11533         case 256:
11534           vindex = 1;
11535           break;
11536         case 512:
11537           vindex = 2;
11538           break;
11539         default:
11540           abort ();
11541           break;
11542         }
11543
11544       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11545       break;
11546
11547     case USE_XOP_8F_TABLE:
11548       FETCH_DATA (info, codep + 3);
11549       /* All bits in the REX prefix are ignored.  */
11550       rex_ignored = rex;
11551       rex = ~(*codep >> 5) & 0x7;
11552
11553       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11554       switch ((*codep & 0x1f))
11555         {
11556         default:
11557           dp = &bad_opcode;
11558           return dp;
11559         case 0x8:
11560           vex_table_index = XOP_08;
11561           break;
11562         case 0x9:
11563           vex_table_index = XOP_09;
11564           break;
11565         case 0xa:
11566           vex_table_index = XOP_0A;
11567           break;
11568         }
11569       codep++;
11570       vex.w = *codep & 0x80;
11571       if (vex.w && address_mode == mode_64bit)
11572         rex |= REX_W;
11573
11574       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11575       if (address_mode != mode_64bit)
11576         {
11577           /* In 16/32-bit mode REX_B is silently ignored.  */
11578           rex &= ~REX_B;
11579         }
11580
11581       vex.length = (*codep & 0x4) ? 256 : 128;
11582       switch ((*codep & 0x3))
11583         {
11584         case 0:
11585           break;
11586         case 1:
11587           vex.prefix = DATA_PREFIX_OPCODE;
11588           break;
11589         case 2:
11590           vex.prefix = REPE_PREFIX_OPCODE;
11591           break;
11592         case 3:
11593           vex.prefix = REPNE_PREFIX_OPCODE;
11594           break;
11595         }
11596       need_vex = 1;
11597       need_vex_reg = 1;
11598       codep++;
11599       vindex = *codep++;
11600       dp = &xop_table[vex_table_index][vindex];
11601
11602       end_codep = codep;
11603       FETCH_DATA (info, codep + 1);
11604       modrm.mod = (*codep >> 6) & 3;
11605       modrm.reg = (*codep >> 3) & 7;
11606       modrm.rm = *codep & 7;
11607       break;
11608
11609     case USE_VEX_C4_TABLE:
11610       /* VEX prefix.  */
11611       FETCH_DATA (info, codep + 3);
11612       /* All bits in the REX prefix are ignored.  */
11613       rex_ignored = rex;
11614       rex = ~(*codep >> 5) & 0x7;
11615       switch ((*codep & 0x1f))
11616         {
11617         default:
11618           dp = &bad_opcode;
11619           return dp;
11620         case 0x1:
11621           vex_table_index = VEX_0F;
11622           break;
11623         case 0x2:
11624           vex_table_index = VEX_0F38;
11625           break;
11626         case 0x3:
11627           vex_table_index = VEX_0F3A;
11628           break;
11629         }
11630       codep++;
11631       vex.w = *codep & 0x80;
11632       if (address_mode == mode_64bit)
11633         {
11634           if (vex.w)
11635             rex |= REX_W;
11636         }
11637       else
11638         {
11639           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11640              is ignored, other REX bits are 0 and the highest bit in
11641              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11642           rex = 0;
11643         }
11644       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11645       vex.length = (*codep & 0x4) ? 256 : 128;
11646       switch ((*codep & 0x3))
11647         {
11648         case 0:
11649           break;
11650         case 1:
11651           vex.prefix = DATA_PREFIX_OPCODE;
11652           break;
11653         case 2:
11654           vex.prefix = REPE_PREFIX_OPCODE;
11655           break;
11656         case 3:
11657           vex.prefix = REPNE_PREFIX_OPCODE;
11658           break;
11659         }
11660       need_vex = 1;
11661       need_vex_reg = 1;
11662       codep++;
11663       vindex = *codep++;
11664       dp = &vex_table[vex_table_index][vindex];
11665       end_codep = codep;
11666       /* There is no MODRM byte for VEX0F 77.  */
11667       if (vex_table_index != VEX_0F || vindex != 0x77)
11668         {
11669           FETCH_DATA (info, codep + 1);
11670           modrm.mod = (*codep >> 6) & 3;
11671           modrm.reg = (*codep >> 3) & 7;
11672           modrm.rm = *codep & 7;
11673         }
11674       break;
11675
11676     case USE_VEX_C5_TABLE:
11677       /* VEX prefix.  */
11678       FETCH_DATA (info, codep + 2);
11679       /* All bits in the REX prefix are ignored.  */
11680       rex_ignored = rex;
11681       rex = (*codep & 0x80) ? 0 : REX_R;
11682
11683       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11684          VEX.vvvv is 1.  */
11685       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11686       vex.length = (*codep & 0x4) ? 256 : 128;
11687       switch ((*codep & 0x3))
11688         {
11689         case 0:
11690           break;
11691         case 1:
11692           vex.prefix = DATA_PREFIX_OPCODE;
11693           break;
11694         case 2:
11695           vex.prefix = REPE_PREFIX_OPCODE;
11696           break;
11697         case 3:
11698           vex.prefix = REPNE_PREFIX_OPCODE;
11699           break;
11700         }
11701       need_vex = 1;
11702       need_vex_reg = 1;
11703       codep++;
11704       vindex = *codep++;
11705       dp = &vex_table[dp->op[1].bytemode][vindex];
11706       end_codep = codep;
11707       /* There is no MODRM byte for VEX 77.  */
11708       if (vindex != 0x77)
11709         {
11710           FETCH_DATA (info, codep + 1);
11711           modrm.mod = (*codep >> 6) & 3;
11712           modrm.reg = (*codep >> 3) & 7;
11713           modrm.rm = *codep & 7;
11714         }
11715       break;
11716
11717     case USE_VEX_W_TABLE:
11718       if (!need_vex)
11719         abort ();
11720
11721       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11722       break;
11723
11724     case USE_EVEX_TABLE:
11725       two_source_ops = 0;
11726       /* EVEX prefix.  */
11727       vex.evex = 1;
11728       FETCH_DATA (info, codep + 4);
11729       /* All bits in the REX prefix are ignored.  */
11730       rex_ignored = rex;
11731       /* The first byte after 0x62.  */
11732       rex = ~(*codep >> 5) & 0x7;
11733       vex.r = *codep & 0x10;
11734       switch ((*codep & 0xf))
11735         {
11736         default:
11737           return &bad_opcode;
11738         case 0x1:
11739           vex_table_index = EVEX_0F;
11740           break;
11741         case 0x2:
11742           vex_table_index = EVEX_0F38;
11743           break;
11744         case 0x3:
11745           vex_table_index = EVEX_0F3A;
11746           break;
11747         }
11748
11749       /* The second byte after 0x62.  */
11750       codep++;
11751       vex.w = *codep & 0x80;
11752       if (vex.w && address_mode == mode_64bit)
11753         rex |= REX_W;
11754
11755       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11756
11757       /* The U bit.  */
11758       if (!(*codep & 0x4))
11759         return &bad_opcode;
11760
11761       switch ((*codep & 0x3))
11762         {
11763         case 0:
11764           break;
11765         case 1:
11766           vex.prefix = DATA_PREFIX_OPCODE;
11767           break;
11768         case 2:
11769           vex.prefix = REPE_PREFIX_OPCODE;
11770           break;
11771         case 3:
11772           vex.prefix = REPNE_PREFIX_OPCODE;
11773           break;
11774         }
11775
11776       /* The third byte after 0x62.  */
11777       codep++;
11778
11779       /* Remember the static rounding bits.  */
11780       vex.ll = (*codep >> 5) & 3;
11781       vex.b = (*codep & 0x10) != 0;
11782
11783       vex.v = *codep & 0x8;
11784       vex.mask_register_specifier = *codep & 0x7;
11785       vex.zeroing = *codep & 0x80;
11786
11787       if (address_mode != mode_64bit)
11788         {
11789           /* In 16/32-bit mode silently ignore following bits.  */
11790           rex &= ~REX_B;
11791           vex.r = 1;
11792           vex.v = 1;
11793         }
11794
11795       need_vex = 1;
11796       need_vex_reg = 1;
11797       codep++;
11798       vindex = *codep++;
11799       dp = &evex_table[vex_table_index][vindex];
11800       end_codep = codep;
11801       FETCH_DATA (info, codep + 1);
11802       modrm.mod = (*codep >> 6) & 3;
11803       modrm.reg = (*codep >> 3) & 7;
11804       modrm.rm = *codep & 7;
11805
11806       /* Set vector length.  */
11807       if (modrm.mod == 3 && vex.b)
11808         vex.length = 512;
11809       else
11810         {
11811           switch (vex.ll)
11812             {
11813             case 0x0:
11814               vex.length = 128;
11815               break;
11816             case 0x1:
11817               vex.length = 256;
11818               break;
11819             case 0x2:
11820               vex.length = 512;
11821               break;
11822             default:
11823               return &bad_opcode;
11824             }
11825         }
11826       break;
11827
11828     case 0:
11829       dp = &bad_opcode;
11830       break;
11831
11832     default:
11833       abort ();
11834     }
11835
11836   if (dp->name != NULL)
11837     return dp;
11838   else
11839     return get_valid_dis386 (dp, info);
11840 }
11841
11842 static void
11843 get_sib (disassemble_info *info, int sizeflag)
11844 {
11845   /* If modrm.mod == 3, operand must be register.  */
11846   if (need_modrm
11847       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11848       && modrm.mod != 3
11849       && modrm.rm == 4)
11850     {
11851       FETCH_DATA (info, codep + 2);
11852       sib.index = (codep [1] >> 3) & 7;
11853       sib.scale = (codep [1] >> 6) & 3;
11854       sib.base = codep [1] & 7;
11855     }
11856 }
11857
11858 static int
11859 print_insn (bfd_vma pc, disassemble_info *info)
11860 {
11861   const struct dis386 *dp;
11862   int i;
11863   char *op_txt[MAX_OPERANDS];
11864   int needcomma;
11865   int sizeflag, orig_sizeflag;
11866   const char *p;
11867   struct dis_private priv;
11868   int prefix_length;
11869
11870   priv.orig_sizeflag = AFLAG | DFLAG;
11871   if ((info->mach & bfd_mach_i386_i386) != 0)
11872     address_mode = mode_32bit;
11873   else if (info->mach == bfd_mach_i386_i8086)
11874     {
11875       address_mode = mode_16bit;
11876       priv.orig_sizeflag = 0;
11877     }
11878   else
11879     address_mode = mode_64bit;
11880
11881   if (intel_syntax == (char) -1)
11882     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11883
11884   for (p = info->disassembler_options; p != NULL; )
11885     {
11886       if (CONST_STRNEQ (p, "amd64"))
11887         isa64 = amd64;
11888       else if (CONST_STRNEQ (p, "intel64"))
11889         isa64 = intel64;
11890       else if (CONST_STRNEQ (p, "x86-64"))
11891         {
11892           address_mode = mode_64bit;
11893           priv.orig_sizeflag = AFLAG | DFLAG;
11894         }
11895       else if (CONST_STRNEQ (p, "i386"))
11896         {
11897           address_mode = mode_32bit;
11898           priv.orig_sizeflag = AFLAG | DFLAG;
11899         }
11900       else if (CONST_STRNEQ (p, "i8086"))
11901         {
11902           address_mode = mode_16bit;
11903           priv.orig_sizeflag = 0;
11904         }
11905       else if (CONST_STRNEQ (p, "intel"))
11906         {
11907           intel_syntax = 1;
11908           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11909             intel_mnemonic = 1;
11910         }
11911       else if (CONST_STRNEQ (p, "att"))
11912         {
11913           intel_syntax = 0;
11914           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11915             intel_mnemonic = 0;
11916         }
11917       else if (CONST_STRNEQ (p, "addr"))
11918         {
11919           if (address_mode == mode_64bit)
11920             {
11921               if (p[4] == '3' && p[5] == '2')
11922                 priv.orig_sizeflag &= ~AFLAG;
11923               else if (p[4] == '6' && p[5] == '4')
11924                 priv.orig_sizeflag |= AFLAG;
11925             }
11926           else
11927             {
11928               if (p[4] == '1' && p[5] == '6')
11929                 priv.orig_sizeflag &= ~AFLAG;
11930               else if (p[4] == '3' && p[5] == '2')
11931                 priv.orig_sizeflag |= AFLAG;
11932             }
11933         }
11934       else if (CONST_STRNEQ (p, "data"))
11935         {
11936           if (p[4] == '1' && p[5] == '6')
11937             priv.orig_sizeflag &= ~DFLAG;
11938           else if (p[4] == '3' && p[5] == '2')
11939             priv.orig_sizeflag |= DFLAG;
11940         }
11941       else if (CONST_STRNEQ (p, "suffix"))
11942         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11943
11944       p = strchr (p, ',');
11945       if (p != NULL)
11946         p++;
11947     }
11948
11949   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11950     {
11951       (*info->fprintf_func) (info->stream,
11952                              _("64-bit address is disabled"));
11953       return -1;
11954     }
11955
11956   if (intel_syntax)
11957     {
11958       names64 = intel_names64;
11959       names32 = intel_names32;
11960       names16 = intel_names16;
11961       names8 = intel_names8;
11962       names8rex = intel_names8rex;
11963       names_seg = intel_names_seg;
11964       names_mm = intel_names_mm;
11965       names_bnd = intel_names_bnd;
11966       names_xmm = intel_names_xmm;
11967       names_ymm = intel_names_ymm;
11968       names_zmm = intel_names_zmm;
11969       index64 = intel_index64;
11970       index32 = intel_index32;
11971       names_mask = intel_names_mask;
11972       index16 = intel_index16;
11973       open_char = '[';
11974       close_char = ']';
11975       separator_char = '+';
11976       scale_char = '*';
11977     }
11978   else
11979     {
11980       names64 = att_names64;
11981       names32 = att_names32;
11982       names16 = att_names16;
11983       names8 = att_names8;
11984       names8rex = att_names8rex;
11985       names_seg = att_names_seg;
11986       names_mm = att_names_mm;
11987       names_bnd = att_names_bnd;
11988       names_xmm = att_names_xmm;
11989       names_ymm = att_names_ymm;
11990       names_zmm = att_names_zmm;
11991       index64 = att_index64;
11992       index32 = att_index32;
11993       names_mask = att_names_mask;
11994       index16 = att_index16;
11995       open_char = '(';
11996       close_char =  ')';
11997       separator_char = ',';
11998       scale_char = ',';
11999     }
12000
12001   /* The output looks better if we put 7 bytes on a line, since that
12002      puts most long word instructions on a single line.  Use 8 bytes
12003      for Intel L1OM.  */
12004   if ((info->mach & bfd_mach_l1om) != 0)
12005     info->bytes_per_line = 8;
12006   else
12007     info->bytes_per_line = 7;
12008
12009   info->private_data = &priv;
12010   priv.max_fetched = priv.the_buffer;
12011   priv.insn_start = pc;
12012
12013   obuf[0] = 0;
12014   for (i = 0; i < MAX_OPERANDS; ++i)
12015     {
12016       op_out[i][0] = 0;
12017       op_index[i] = -1;
12018     }
12019
12020   the_info = info;
12021   start_pc = pc;
12022   start_codep = priv.the_buffer;
12023   codep = priv.the_buffer;
12024
12025   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12026     {
12027       const char *name;
12028
12029       /* Getting here means we tried for data but didn't get it.  That
12030          means we have an incomplete instruction of some sort.  Just
12031          print the first byte as a prefix or a .byte pseudo-op.  */
12032       if (codep > priv.the_buffer)
12033         {
12034           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12035           if (name != NULL)
12036             (*info->fprintf_func) (info->stream, "%s", name);
12037           else
12038             {
12039               /* Just print the first byte as a .byte instruction.  */
12040               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12041                                      (unsigned int) priv.the_buffer[0]);
12042             }
12043
12044           return 1;
12045         }
12046
12047       return -1;
12048     }
12049
12050   obufp = obuf;
12051   sizeflag = priv.orig_sizeflag;
12052
12053   if (!ckprefix () || rex_used)
12054     {
12055       /* Too many prefixes or unused REX prefixes.  */
12056       for (i = 0;
12057            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12058            i++)
12059         (*info->fprintf_func) (info->stream, "%s%s",
12060                                i == 0 ? "" : " ",
12061                                prefix_name (all_prefixes[i], sizeflag));
12062       return i;
12063     }
12064
12065   insn_codep = codep;
12066
12067   FETCH_DATA (info, codep + 1);
12068   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12069
12070   if (((prefixes & PREFIX_FWAIT)
12071        && ((*codep < 0xd8) || (*codep > 0xdf))))
12072     {
12073       /* Handle prefixes before fwait.  */
12074       for (i = 0; i < fwait_prefix && all_prefixes[i];
12075            i++)
12076         (*info->fprintf_func) (info->stream, "%s ",
12077                                prefix_name (all_prefixes[i], sizeflag));
12078       (*info->fprintf_func) (info->stream, "fwait");
12079       return i + 1;
12080     }
12081
12082   if (*codep == 0x0f)
12083     {
12084       unsigned char threebyte;
12085
12086       codep++;
12087       FETCH_DATA (info, codep + 1);
12088       threebyte = *codep;
12089       dp = &dis386_twobyte[threebyte];
12090       need_modrm = twobyte_has_modrm[*codep];
12091       codep++;
12092     }
12093   else
12094     {
12095       dp = &dis386[*codep];
12096       need_modrm = onebyte_has_modrm[*codep];
12097       codep++;
12098     }
12099
12100   /* Save sizeflag for printing the extra prefixes later before updating
12101      it for mnemonic and operand processing.  The prefix names depend
12102      only on the address mode.  */
12103   orig_sizeflag = sizeflag;
12104   if (prefixes & PREFIX_ADDR)
12105     sizeflag ^= AFLAG;
12106   if ((prefixes & PREFIX_DATA))
12107     sizeflag ^= DFLAG;
12108
12109   end_codep = codep;
12110   if (need_modrm)
12111     {
12112       FETCH_DATA (info, codep + 1);
12113       modrm.mod = (*codep >> 6) & 3;
12114       modrm.reg = (*codep >> 3) & 7;
12115       modrm.rm = *codep & 7;
12116     }
12117
12118   need_vex = 0;
12119   need_vex_reg = 0;
12120   vex_w_done = 0;
12121   memset (&vex, 0, sizeof (vex));
12122
12123   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12124     {
12125       get_sib (info, sizeflag);
12126       dofloat (sizeflag);
12127     }
12128   else
12129     {
12130       dp = get_valid_dis386 (dp, info);
12131       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12132         {
12133           get_sib (info, sizeflag);
12134           for (i = 0; i < MAX_OPERANDS; ++i)
12135             {
12136               obufp = op_out[i];
12137               op_ad = MAX_OPERANDS - 1 - i;
12138               if (dp->op[i].rtn)
12139                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12140               /* For EVEX instruction after the last operand masking
12141                  should be printed.  */
12142               if (i == 0 && vex.evex)
12143                 {
12144                   /* Don't print {%k0}.  */
12145                   if (vex.mask_register_specifier)
12146                     {
12147                       oappend ("{");
12148                       oappend (names_mask[vex.mask_register_specifier]);
12149                       oappend ("}");
12150                     }
12151                   if (vex.zeroing)
12152                     oappend ("{z}");
12153                 }
12154             }
12155         }
12156     }
12157
12158   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12159      are all 0s in inverted form.  */
12160   if (need_vex && vex.register_specifier != 0)
12161     {
12162       (*info->fprintf_func) (info->stream, "(bad)");
12163       return end_codep - priv.the_buffer;
12164     }
12165
12166   /* Check if the REX prefix is used.  */
12167   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12168     all_prefixes[last_rex_prefix] = 0;
12169
12170   /* Check if the SEG prefix is used.  */
12171   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12172                    | PREFIX_FS | PREFIX_GS)) != 0
12173       && (used_prefixes & active_seg_prefix) != 0)
12174     all_prefixes[last_seg_prefix] = 0;
12175
12176   /* Check if the ADDR prefix is used.  */
12177   if ((prefixes & PREFIX_ADDR) != 0
12178       && (used_prefixes & PREFIX_ADDR) != 0)
12179     all_prefixes[last_addr_prefix] = 0;
12180
12181   /* Check if the DATA prefix is used.  */
12182   if ((prefixes & PREFIX_DATA) != 0
12183       && (used_prefixes & PREFIX_DATA) != 0)
12184     all_prefixes[last_data_prefix] = 0;
12185
12186   /* Print the extra prefixes.  */
12187   prefix_length = 0;
12188   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12189     if (all_prefixes[i])
12190       {
12191         const char *name;
12192         name = prefix_name (all_prefixes[i], orig_sizeflag);
12193         if (name == NULL)
12194           abort ();
12195         prefix_length += strlen (name) + 1;
12196         (*info->fprintf_func) (info->stream, "%s ", name);
12197       }
12198
12199   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12200      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12201      used by putop and MMX/SSE operand and may be overriden by the
12202      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12203      separately.  */
12204   if (dp->prefix_requirement == PREFIX_OPCODE
12205       && dp != &bad_opcode
12206       && (((prefixes
12207             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12208            && (used_prefixes
12209                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12210           || ((((prefixes
12211                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12212                 == PREFIX_DATA)
12213                && (used_prefixes & PREFIX_DATA) == 0))))
12214     {
12215       (*info->fprintf_func) (info->stream, "(bad)");
12216       return end_codep - priv.the_buffer;
12217     }
12218
12219   /* Check maximum code length.  */
12220   if ((codep - start_codep) > MAX_CODE_LENGTH)
12221     {
12222       (*info->fprintf_func) (info->stream, "(bad)");
12223       return MAX_CODE_LENGTH;
12224     }
12225
12226   obufp = mnemonicendp;
12227   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12228     oappend (" ");
12229   oappend (" ");
12230   (*info->fprintf_func) (info->stream, "%s", obuf);
12231
12232   /* The enter and bound instructions are printed with operands in the same
12233      order as the intel book; everything else is printed in reverse order.  */
12234   if (intel_syntax || two_source_ops)
12235     {
12236       bfd_vma riprel;
12237
12238       for (i = 0; i < MAX_OPERANDS; ++i)
12239         op_txt[i] = op_out[i];
12240
12241       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12242           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12243         {
12244           op_txt[2] = op_out[3];
12245           op_txt[3] = op_out[2];
12246         }
12247
12248       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12249         {
12250           op_ad = op_index[i];
12251           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12252           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12253           riprel = op_riprel[i];
12254           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12255           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12256         }
12257     }
12258   else
12259     {
12260       for (i = 0; i < MAX_OPERANDS; ++i)
12261         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12262     }
12263
12264   needcomma = 0;
12265   for (i = 0; i < MAX_OPERANDS; ++i)
12266     if (*op_txt[i])
12267       {
12268         if (needcomma)
12269           (*info->fprintf_func) (info->stream, ",");
12270         if (op_index[i] != -1 && !op_riprel[i])
12271           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12272         else
12273           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12274         needcomma = 1;
12275       }
12276
12277   for (i = 0; i < MAX_OPERANDS; i++)
12278     if (op_index[i] != -1 && op_riprel[i])
12279       {
12280         (*info->fprintf_func) (info->stream, "        # ");
12281         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12282                                                 + op_address[op_index[i]]), info);
12283         break;
12284       }
12285   return codep - priv.the_buffer;
12286 }
12287
12288 static const char *float_mem[] = {
12289   /* d8 */
12290   "fadd{s|}",
12291   "fmul{s|}",
12292   "fcom{s|}",
12293   "fcomp{s|}",
12294   "fsub{s|}",
12295   "fsubr{s|}",
12296   "fdiv{s|}",
12297   "fdivr{s|}",
12298   /* d9 */
12299   "fld{s|}",
12300   "(bad)",
12301   "fst{s|}",
12302   "fstp{s|}",
12303   "fldenvIC",
12304   "fldcw",
12305   "fNstenvIC",
12306   "fNstcw",
12307   /* da */
12308   "fiadd{l|}",
12309   "fimul{l|}",
12310   "ficom{l|}",
12311   "ficomp{l|}",
12312   "fisub{l|}",
12313   "fisubr{l|}",
12314   "fidiv{l|}",
12315   "fidivr{l|}",
12316   /* db */
12317   "fild{l|}",
12318   "fisttp{l|}",
12319   "fist{l|}",
12320   "fistp{l|}",
12321   "(bad)",
12322   "fld{t||t|}",
12323   "(bad)",
12324   "fstp{t||t|}",
12325   /* dc */
12326   "fadd{l|}",
12327   "fmul{l|}",
12328   "fcom{l|}",
12329   "fcomp{l|}",
12330   "fsub{l|}",
12331   "fsubr{l|}",
12332   "fdiv{l|}",
12333   "fdivr{l|}",
12334   /* dd */
12335   "fld{l|}",
12336   "fisttp{ll|}",
12337   "fst{l||}",
12338   "fstp{l|}",
12339   "frstorIC",
12340   "(bad)",
12341   "fNsaveIC",
12342   "fNstsw",
12343   /* de */
12344   "fiadd{s|}",
12345   "fimul{s|}",
12346   "ficom{s|}",
12347   "ficomp{s|}",
12348   "fisub{s|}",
12349   "fisubr{s|}",
12350   "fidiv{s|}",
12351   "fidivr{s|}",
12352   /* df */
12353   "fild{s|}",
12354   "fisttp{s|}",
12355   "fist{s|}",
12356   "fistp{s|}",
12357   "fbld",
12358   "fild{ll|}",
12359   "fbstp",
12360   "fistp{ll|}",
12361 };
12362
12363 static const unsigned char float_mem_mode[] = {
12364   /* d8 */
12365   d_mode,
12366   d_mode,
12367   d_mode,
12368   d_mode,
12369   d_mode,
12370   d_mode,
12371   d_mode,
12372   d_mode,
12373   /* d9 */
12374   d_mode,
12375   0,
12376   d_mode,
12377   d_mode,
12378   0,
12379   w_mode,
12380   0,
12381   w_mode,
12382   /* da */
12383   d_mode,
12384   d_mode,
12385   d_mode,
12386   d_mode,
12387   d_mode,
12388   d_mode,
12389   d_mode,
12390   d_mode,
12391   /* db */
12392   d_mode,
12393   d_mode,
12394   d_mode,
12395   d_mode,
12396   0,
12397   t_mode,
12398   0,
12399   t_mode,
12400   /* dc */
12401   q_mode,
12402   q_mode,
12403   q_mode,
12404   q_mode,
12405   q_mode,
12406   q_mode,
12407   q_mode,
12408   q_mode,
12409   /* dd */
12410   q_mode,
12411   q_mode,
12412   q_mode,
12413   q_mode,
12414   0,
12415   0,
12416   0,
12417   w_mode,
12418   /* de */
12419   w_mode,
12420   w_mode,
12421   w_mode,
12422   w_mode,
12423   w_mode,
12424   w_mode,
12425   w_mode,
12426   w_mode,
12427   /* df */
12428   w_mode,
12429   w_mode,
12430   w_mode,
12431   w_mode,
12432   t_mode,
12433   q_mode,
12434   t_mode,
12435   q_mode
12436 };
12437
12438 #define ST { OP_ST, 0 }
12439 #define STi { OP_STi, 0 }
12440
12441 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12442 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12443 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12444 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12445 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12446 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12447 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12448 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12449 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12450
12451 static const struct dis386 float_reg[][8] = {
12452   /* d8 */
12453   {
12454     { "fadd",   { ST, STi }, 0 },
12455     { "fmul",   { ST, STi }, 0 },
12456     { "fcom",   { STi }, 0 },
12457     { "fcomp",  { STi }, 0 },
12458     { "fsub",   { ST, STi }, 0 },
12459     { "fsubr",  { ST, STi }, 0 },
12460     { "fdiv",   { ST, STi }, 0 },
12461     { "fdivr",  { ST, STi }, 0 },
12462   },
12463   /* d9 */
12464   {
12465     { "fld",    { STi }, 0 },
12466     { "fxch",   { STi }, 0 },
12467     { FGRPd9_2 },
12468     { Bad_Opcode },
12469     { FGRPd9_4 },
12470     { FGRPd9_5 },
12471     { FGRPd9_6 },
12472     { FGRPd9_7 },
12473   },
12474   /* da */
12475   {
12476     { "fcmovb", { ST, STi }, 0 },
12477     { "fcmove", { ST, STi }, 0 },
12478     { "fcmovbe",{ ST, STi }, 0 },
12479     { "fcmovu", { ST, STi }, 0 },
12480     { Bad_Opcode },
12481     { FGRPda_5 },
12482     { Bad_Opcode },
12483     { Bad_Opcode },
12484   },
12485   /* db */
12486   {
12487     { "fcmovnb",{ ST, STi }, 0 },
12488     { "fcmovne",{ ST, STi }, 0 },
12489     { "fcmovnbe",{ ST, STi }, 0 },
12490     { "fcmovnu",{ ST, STi }, 0 },
12491     { FGRPdb_4 },
12492     { "fucomi", { ST, STi }, 0 },
12493     { "fcomi",  { ST, STi }, 0 },
12494     { Bad_Opcode },
12495   },
12496   /* dc */
12497   {
12498     { "fadd",   { STi, ST }, 0 },
12499     { "fmul",   { STi, ST }, 0 },
12500     { Bad_Opcode },
12501     { Bad_Opcode },
12502     { "fsub{!M|r}",     { STi, ST }, 0 },
12503     { "fsub{M|}",       { STi, ST }, 0 },
12504     { "fdiv{!M|r}",     { STi, ST }, 0 },
12505     { "fdiv{M|}",       { STi, ST }, 0 },
12506   },
12507   /* dd */
12508   {
12509     { "ffree",  { STi }, 0 },
12510     { Bad_Opcode },
12511     { "fst",    { STi }, 0 },
12512     { "fstp",   { STi }, 0 },
12513     { "fucom",  { STi }, 0 },
12514     { "fucomp", { STi }, 0 },
12515     { Bad_Opcode },
12516     { Bad_Opcode },
12517   },
12518   /* de */
12519   {
12520     { "faddp",  { STi, ST }, 0 },
12521     { "fmulp",  { STi, ST }, 0 },
12522     { Bad_Opcode },
12523     { FGRPde_3 },
12524     { "fsub{!M|r}p",    { STi, ST }, 0 },
12525     { "fsub{M|}p",      { STi, ST }, 0 },
12526     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12527     { "fdiv{M|}p",      { STi, ST }, 0 },
12528   },
12529   /* df */
12530   {
12531     { "ffreep", { STi }, 0 },
12532     { Bad_Opcode },
12533     { Bad_Opcode },
12534     { Bad_Opcode },
12535     { FGRPdf_4 },
12536     { "fucomip", { ST, STi }, 0 },
12537     { "fcomip", { ST, STi }, 0 },
12538     { Bad_Opcode },
12539   },
12540 };
12541
12542 static char *fgrps[][8] = {
12543   /* Bad opcode 0 */
12544   {
12545     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12546   },
12547
12548   /* d9_2  1 */
12549   {
12550     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12551   },
12552
12553   /* d9_4  2 */
12554   {
12555     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12556   },
12557
12558   /* d9_5  3 */
12559   {
12560     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12561   },
12562
12563   /* d9_6  4 */
12564   {
12565     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12566   },
12567
12568   /* d9_7  5 */
12569   {
12570     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12571   },
12572
12573   /* da_5  6 */
12574   {
12575     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12576   },
12577
12578   /* db_4  7 */
12579   {
12580     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12581     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12582   },
12583
12584   /* de_3  8 */
12585   {
12586     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12587   },
12588
12589   /* df_4  9 */
12590   {
12591     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12592   },
12593 };
12594
12595 static void
12596 swap_operand (void)
12597 {
12598   mnemonicendp[0] = '.';
12599   mnemonicendp[1] = 's';
12600   mnemonicendp += 2;
12601 }
12602
12603 static void
12604 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12605                int sizeflag ATTRIBUTE_UNUSED)
12606 {
12607   /* Skip mod/rm byte.  */
12608   MODRM_CHECK;
12609   codep++;
12610 }
12611
12612 static void
12613 dofloat (int sizeflag)
12614 {
12615   const struct dis386 *dp;
12616   unsigned char floatop;
12617
12618   floatop = codep[-1];
12619
12620   if (modrm.mod != 3)
12621     {
12622       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12623
12624       putop (float_mem[fp_indx], sizeflag);
12625       obufp = op_out[0];
12626       op_ad = 2;
12627       OP_E (float_mem_mode[fp_indx], sizeflag);
12628       return;
12629     }
12630   /* Skip mod/rm byte.  */
12631   MODRM_CHECK;
12632   codep++;
12633
12634   dp = &float_reg[floatop - 0xd8][modrm.reg];
12635   if (dp->name == NULL)
12636     {
12637       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12638
12639       /* Instruction fnstsw is only one with strange arg.  */
12640       if (floatop == 0xdf && codep[-1] == 0xe0)
12641         strcpy (op_out[0], names16[0]);
12642     }
12643   else
12644     {
12645       putop (dp->name, sizeflag);
12646
12647       obufp = op_out[0];
12648       op_ad = 2;
12649       if (dp->op[0].rtn)
12650         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12651
12652       obufp = op_out[1];
12653       op_ad = 1;
12654       if (dp->op[1].rtn)
12655         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12656     }
12657 }
12658
12659 /* Like oappend (below), but S is a string starting with '%'.
12660    In Intel syntax, the '%' is elided.  */
12661 static void
12662 oappend_maybe_intel (const char *s)
12663 {
12664   oappend (s + intel_syntax);
12665 }
12666
12667 static void
12668 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12669 {
12670   oappend_maybe_intel ("%st");
12671 }
12672
12673 static void
12674 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12675 {
12676   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12677   oappend_maybe_intel (scratchbuf);
12678 }
12679
12680 /* Capital letters in template are macros.  */
12681 static int
12682 putop (const char *in_template, int sizeflag)
12683 {
12684   const char *p;
12685   int alt = 0;
12686   int cond = 1;
12687   unsigned int l = 0, len = 1;
12688   char last[4];
12689
12690 #define SAVE_LAST(c)                    \
12691   if (l < len && l < sizeof (last))     \
12692     last[l++] = c;                      \
12693   else                                  \
12694     abort ();
12695
12696   for (p = in_template; *p; p++)
12697     {
12698       switch (*p)
12699         {
12700         default:
12701           *obufp++ = *p;
12702           break;
12703         case '%':
12704           len++;
12705           break;
12706         case '!':
12707           cond = 0;
12708           break;
12709         case '{':
12710           if (intel_syntax)
12711             {
12712               while (*++p != '|')
12713                 if (*p == '}' || *p == '\0')
12714                   abort ();
12715             }
12716           /* Fall through.  */
12717         case 'I':
12718           alt = 1;
12719           continue;
12720         case '|':
12721           while (*++p != '}')
12722             {
12723               if (*p == '\0')
12724                 abort ();
12725             }
12726           break;
12727         case '}':
12728           break;
12729         case 'A':
12730           if (intel_syntax)
12731             break;
12732           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12733             *obufp++ = 'b';
12734           break;
12735         case 'B':
12736           if (l == 0 && len == 1)
12737             {
12738 case_B:
12739               if (intel_syntax)
12740                 break;
12741               if (sizeflag & SUFFIX_ALWAYS)
12742                 *obufp++ = 'b';
12743             }
12744           else
12745             {
12746               if (l != 1
12747                   || len != 2
12748                   || last[0] != 'L')
12749                 {
12750                   SAVE_LAST (*p);
12751                   break;
12752                 }
12753
12754               if (address_mode == mode_64bit
12755                   && !(prefixes & PREFIX_ADDR))
12756                 {
12757                   *obufp++ = 'a';
12758                   *obufp++ = 'b';
12759                   *obufp++ = 's';
12760                 }
12761
12762               goto case_B;
12763             }
12764           break;
12765         case 'C':
12766           if (intel_syntax && !alt)
12767             break;
12768           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12769             {
12770               if (sizeflag & DFLAG)
12771                 *obufp++ = intel_syntax ? 'd' : 'l';
12772               else
12773                 *obufp++ = intel_syntax ? 'w' : 's';
12774               used_prefixes |= (prefixes & PREFIX_DATA);
12775             }
12776           break;
12777         case 'D':
12778           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12779             break;
12780           USED_REX (REX_W);
12781           if (modrm.mod == 3)
12782             {
12783               if (rex & REX_W)
12784                 *obufp++ = 'q';
12785               else
12786                 {
12787                   if (sizeflag & DFLAG)
12788                     *obufp++ = intel_syntax ? 'd' : 'l';
12789                   else
12790                     *obufp++ = 'w';
12791                   used_prefixes |= (prefixes & PREFIX_DATA);
12792                 }
12793             }
12794           else
12795             *obufp++ = 'w';
12796           break;
12797         case 'E':               /* For jcxz/jecxz */
12798           if (address_mode == mode_64bit)
12799             {
12800               if (sizeflag & AFLAG)
12801                 *obufp++ = 'r';
12802               else
12803                 *obufp++ = 'e';
12804             }
12805           else
12806             if (sizeflag & AFLAG)
12807               *obufp++ = 'e';
12808           used_prefixes |= (prefixes & PREFIX_ADDR);
12809           break;
12810         case 'F':
12811           if (intel_syntax)
12812             break;
12813           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12814             {
12815               if (sizeflag & AFLAG)
12816                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12817               else
12818                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12819               used_prefixes |= (prefixes & PREFIX_ADDR);
12820             }
12821           break;
12822         case 'G':
12823           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12824             break;
12825           if ((rex & REX_W) || (sizeflag & DFLAG))
12826             *obufp++ = 'l';
12827           else
12828             *obufp++ = 'w';
12829           if (!(rex & REX_W))
12830             used_prefixes |= (prefixes & PREFIX_DATA);
12831           break;
12832         case 'H':
12833           if (intel_syntax)
12834             break;
12835           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12836               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12837             {
12838               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12839               *obufp++ = ',';
12840               *obufp++ = 'p';
12841               if (prefixes & PREFIX_DS)
12842                 *obufp++ = 't';
12843               else
12844                 *obufp++ = 'n';
12845             }
12846           break;
12847         case 'J':
12848           if (intel_syntax)
12849             break;
12850           *obufp++ = 'l';
12851           break;
12852         case 'K':
12853           USED_REX (REX_W);
12854           if (rex & REX_W)
12855             *obufp++ = 'q';
12856           else
12857             *obufp++ = 'd';
12858           break;
12859         case 'Z':
12860           if (l != 0 || len != 1)
12861             {
12862               if (l != 1 || len != 2 || last[0] != 'X')
12863                 {
12864                   SAVE_LAST (*p);
12865                   break;
12866                 }
12867               if (!need_vex || !vex.evex)
12868                 abort ();
12869               if (intel_syntax
12870                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12871                 break;
12872               switch (vex.length)
12873                 {
12874                 case 128:
12875                   *obufp++ = 'x';
12876                   break;
12877                 case 256:
12878                   *obufp++ = 'y';
12879                   break;
12880                 case 512:
12881                   *obufp++ = 'z';
12882                   break;
12883                 default:
12884                   abort ();
12885                 }
12886               break;
12887             }
12888           if (intel_syntax)
12889             break;
12890           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12891             {
12892               *obufp++ = 'q';
12893               break;
12894             }
12895           /* Fall through.  */
12896           goto case_L;
12897         case 'L':
12898           if (l != 0 || len != 1)
12899             {
12900               SAVE_LAST (*p);
12901               break;
12902             }
12903 case_L:
12904           if (intel_syntax)
12905             break;
12906           if (sizeflag & SUFFIX_ALWAYS)
12907             *obufp++ = 'l';
12908           break;
12909         case 'M':
12910           if (intel_mnemonic != cond)
12911             *obufp++ = 'r';
12912           break;
12913         case 'N':
12914           if ((prefixes & PREFIX_FWAIT) == 0)
12915             *obufp++ = 'n';
12916           else
12917             used_prefixes |= PREFIX_FWAIT;
12918           break;
12919         case 'O':
12920           USED_REX (REX_W);
12921           if (rex & REX_W)
12922             *obufp++ = 'o';
12923           else if (intel_syntax && (sizeflag & DFLAG))
12924             *obufp++ = 'q';
12925           else
12926             *obufp++ = 'd';
12927           if (!(rex & REX_W))
12928             used_prefixes |= (prefixes & PREFIX_DATA);
12929           break;
12930         case '&':
12931           if (!intel_syntax
12932               && address_mode == mode_64bit
12933               && isa64 == intel64)
12934             {
12935               *obufp++ = 'q';
12936               break;
12937             }
12938           /* Fall through.  */
12939         case 'T':
12940           if (!intel_syntax
12941               && address_mode == mode_64bit
12942               && ((sizeflag & DFLAG) || (rex & REX_W)))
12943             {
12944               *obufp++ = 'q';
12945               break;
12946             }
12947           /* Fall through.  */
12948           goto case_P;
12949         case 'P':
12950           if (l == 0 && len == 1)
12951             {
12952 case_P:
12953               if (intel_syntax)
12954                 {
12955                   if ((rex & REX_W) == 0
12956                       && (prefixes & PREFIX_DATA))
12957                     {
12958                       if ((sizeflag & DFLAG) == 0)
12959                         *obufp++ = 'w';
12960                       used_prefixes |= (prefixes & PREFIX_DATA);
12961                     }
12962                   break;
12963                 }
12964               if ((prefixes & PREFIX_DATA)
12965                   || (rex & REX_W)
12966                   || (sizeflag & SUFFIX_ALWAYS))
12967                 {
12968                   USED_REX (REX_W);
12969                   if (rex & REX_W)
12970                     *obufp++ = 'q';
12971                   else
12972                     {
12973                       if (sizeflag & DFLAG)
12974                         *obufp++ = 'l';
12975                       else
12976                         *obufp++ = 'w';
12977                       used_prefixes |= (prefixes & PREFIX_DATA);
12978                     }
12979                 }
12980             }
12981           else
12982             {
12983               if (l != 1 || len != 2 || last[0] != 'L')
12984                 {
12985                   SAVE_LAST (*p);
12986                   break;
12987                 }
12988
12989               if ((prefixes & PREFIX_DATA)
12990                   || (rex & REX_W)
12991                   || (sizeflag & SUFFIX_ALWAYS))
12992                 {
12993                   USED_REX (REX_W);
12994                   if (rex & REX_W)
12995                     *obufp++ = 'q';
12996                   else
12997                     {
12998                       if (sizeflag & DFLAG)
12999                         *obufp++ = intel_syntax ? 'd' : 'l';
13000                       else
13001                         *obufp++ = 'w';
13002                       used_prefixes |= (prefixes & PREFIX_DATA);
13003                     }
13004                 }
13005             }
13006           break;
13007         case 'U':
13008           if (intel_syntax)
13009             break;
13010           if (address_mode == mode_64bit
13011               && ((sizeflag & DFLAG) || (rex & REX_W)))
13012             {
13013               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13014                 *obufp++ = 'q';
13015               break;
13016             }
13017           /* Fall through.  */
13018           goto case_Q;
13019         case 'Q':
13020           if (l == 0 && len == 1)
13021             {
13022 case_Q:
13023               if (intel_syntax && !alt)
13024                 break;
13025               USED_REX (REX_W);
13026               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13027                 {
13028                   if (rex & REX_W)
13029                     *obufp++ = 'q';
13030                   else
13031                     {
13032                       if (sizeflag & DFLAG)
13033                         *obufp++ = intel_syntax ? 'd' : 'l';
13034                       else
13035                         *obufp++ = 'w';
13036                       used_prefixes |= (prefixes & PREFIX_DATA);
13037                     }
13038                 }
13039             }
13040           else
13041             {
13042               if (l != 1 || len != 2 || last[0] != 'L')
13043                 {
13044                   SAVE_LAST (*p);
13045                   break;
13046                 }
13047               if (intel_syntax
13048                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13049                 break;
13050               if ((rex & REX_W))
13051                 {
13052                   USED_REX (REX_W);
13053                   *obufp++ = 'q';
13054                 }
13055               else
13056                 *obufp++ = 'l';
13057             }
13058           break;
13059         case 'R':
13060           USED_REX (REX_W);
13061           if (rex & REX_W)
13062             *obufp++ = 'q';
13063           else if (sizeflag & DFLAG)
13064             {
13065               if (intel_syntax)
13066                   *obufp++ = 'd';
13067               else
13068                   *obufp++ = 'l';
13069             }
13070           else
13071             *obufp++ = 'w';
13072           if (intel_syntax && !p[1]
13073               && ((rex & REX_W) || (sizeflag & DFLAG)))
13074             *obufp++ = 'e';
13075           if (!(rex & REX_W))
13076             used_prefixes |= (prefixes & PREFIX_DATA);
13077           break;
13078         case 'V':
13079           if (l == 0 && len == 1)
13080             {
13081               if (intel_syntax)
13082                 break;
13083               if (address_mode == mode_64bit
13084                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13085                 {
13086                   if (sizeflag & SUFFIX_ALWAYS)
13087                     *obufp++ = 'q';
13088                   break;
13089                 }
13090             }
13091           else
13092             {
13093               if (l != 1
13094                   || len != 2
13095                   || last[0] != 'L')
13096                 {
13097                   SAVE_LAST (*p);
13098                   break;
13099                 }
13100
13101               if (rex & REX_W)
13102                 {
13103                   *obufp++ = 'a';
13104                   *obufp++ = 'b';
13105                   *obufp++ = 's';
13106                 }
13107             }
13108           /* Fall through.  */
13109           goto case_S;
13110         case 'S':
13111           if (l == 0 && len == 1)
13112             {
13113 case_S:
13114               if (intel_syntax)
13115                 break;
13116               if (sizeflag & SUFFIX_ALWAYS)
13117                 {
13118                   if (rex & REX_W)
13119                     *obufp++ = 'q';
13120                   else
13121                     {
13122                       if (sizeflag & DFLAG)
13123                         *obufp++ = 'l';
13124                       else
13125                         *obufp++ = 'w';
13126                       used_prefixes |= (prefixes & PREFIX_DATA);
13127                     }
13128                 }
13129             }
13130           else
13131             {
13132               if (l != 1
13133                   || len != 2
13134                   || last[0] != 'L')
13135                 {
13136                   SAVE_LAST (*p);
13137                   break;
13138                 }
13139
13140               if (address_mode == mode_64bit
13141                   && !(prefixes & PREFIX_ADDR))
13142                 {
13143                   *obufp++ = 'a';
13144                   *obufp++ = 'b';
13145                   *obufp++ = 's';
13146                 }
13147
13148               goto case_S;
13149             }
13150           break;
13151         case 'X':
13152           if (l != 0 || len != 1)
13153             {
13154               SAVE_LAST (*p);
13155               break;
13156             }
13157           if (need_vex && vex.prefix)
13158             {
13159               if (vex.prefix == DATA_PREFIX_OPCODE)
13160                 *obufp++ = 'd';
13161               else
13162                 *obufp++ = 's';
13163             }
13164           else
13165             {
13166               if (prefixes & PREFIX_DATA)
13167                 *obufp++ = 'd';
13168               else
13169                 *obufp++ = 's';
13170               used_prefixes |= (prefixes & PREFIX_DATA);
13171             }
13172           break;
13173         case 'Y':
13174           if (l == 0 && len == 1)
13175             abort ();
13176           else
13177             {
13178               if (l != 1 || len != 2 || last[0] != 'X')
13179                 {
13180                   SAVE_LAST (*p);
13181                   break;
13182                 }
13183               if (!need_vex)
13184                 abort ();
13185               if (intel_syntax
13186                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13187                 break;
13188               switch (vex.length)
13189                 {
13190                 case 128:
13191                   *obufp++ = 'x';
13192                   break;
13193                 case 256:
13194                   *obufp++ = 'y';
13195                   break;
13196                 case 512:
13197                   if (!vex.evex)
13198                 default:
13199                     abort ();
13200                 }
13201             }
13202           break;
13203         case 'W':
13204           if (l == 0 && len == 1)
13205             {
13206               /* operand size flag for cwtl, cbtw */
13207               USED_REX (REX_W);
13208               if (rex & REX_W)
13209                 {
13210                   if (intel_syntax)
13211                     *obufp++ = 'd';
13212                   else
13213                     *obufp++ = 'l';
13214                 }
13215               else if (sizeflag & DFLAG)
13216                 *obufp++ = 'w';
13217               else
13218                 *obufp++ = 'b';
13219               if (!(rex & REX_W))
13220                 used_prefixes |= (prefixes & PREFIX_DATA);
13221             }
13222           else
13223             {
13224               if (l != 1
13225                   || len != 2
13226                   || (last[0] != 'X'
13227                       && last[0] != 'L'))
13228                 {
13229                   SAVE_LAST (*p);
13230                   break;
13231                 }
13232               if (!need_vex)
13233                 abort ();
13234               if (last[0] == 'X')
13235                 *obufp++ = vex.w ? 'd': 's';
13236               else
13237                 *obufp++ = vex.w ? 'q': 'd';
13238             }
13239           break;
13240         case '^':
13241           if (intel_syntax)
13242             break;
13243           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13244             {
13245               if (sizeflag & DFLAG)
13246                 *obufp++ = 'l';
13247               else
13248                 *obufp++ = 'w';
13249               used_prefixes |= (prefixes & PREFIX_DATA);
13250             }
13251           break;
13252         case '@':
13253           if (intel_syntax)
13254             break;
13255           if (address_mode == mode_64bit
13256               && (isa64 == intel64
13257                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13258               *obufp++ = 'q';
13259           else if ((prefixes & PREFIX_DATA))
13260             {
13261               if (!(sizeflag & DFLAG))
13262                 *obufp++ = 'w';
13263               used_prefixes |= (prefixes & PREFIX_DATA);
13264             }
13265           break;
13266         }
13267       alt = 0;
13268     }
13269   *obufp = 0;
13270   mnemonicendp = obufp;
13271   return 0;
13272 }
13273
13274 static void
13275 oappend (const char *s)
13276 {
13277   obufp = stpcpy (obufp, s);
13278 }
13279
13280 static void
13281 append_seg (void)
13282 {
13283   /* Only print the active segment register.  */
13284   if (!active_seg_prefix)
13285     return;
13286
13287   used_prefixes |= active_seg_prefix;
13288   switch (active_seg_prefix)
13289     {
13290     case PREFIX_CS:
13291       oappend_maybe_intel ("%cs:");
13292       break;
13293     case PREFIX_DS:
13294       oappend_maybe_intel ("%ds:");
13295       break;
13296     case PREFIX_SS:
13297       oappend_maybe_intel ("%ss:");
13298       break;
13299     case PREFIX_ES:
13300       oappend_maybe_intel ("%es:");
13301       break;
13302     case PREFIX_FS:
13303       oappend_maybe_intel ("%fs:");
13304       break;
13305     case PREFIX_GS:
13306       oappend_maybe_intel ("%gs:");
13307       break;
13308     default:
13309       break;
13310     }
13311 }
13312
13313 static void
13314 OP_indirE (int bytemode, int sizeflag)
13315 {
13316   if (!intel_syntax)
13317     oappend ("*");
13318   OP_E (bytemode, sizeflag);
13319 }
13320
13321 static void
13322 print_operand_value (char *buf, int hex, bfd_vma disp)
13323 {
13324   if (address_mode == mode_64bit)
13325     {
13326       if (hex)
13327         {
13328           char tmp[30];
13329           int i;
13330           buf[0] = '0';
13331           buf[1] = 'x';
13332           sprintf_vma (tmp, disp);
13333           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13334           strcpy (buf + 2, tmp + i);
13335         }
13336       else
13337         {
13338           bfd_signed_vma v = disp;
13339           char tmp[30];
13340           int i;
13341           if (v < 0)
13342             {
13343               *(buf++) = '-';
13344               v = -disp;
13345               /* Check for possible overflow on 0x8000000000000000.  */
13346               if (v < 0)
13347                 {
13348                   strcpy (buf, "9223372036854775808");
13349                   return;
13350                 }
13351             }
13352           if (!v)
13353             {
13354               strcpy (buf, "0");
13355               return;
13356             }
13357
13358           i = 0;
13359           tmp[29] = 0;
13360           while (v)
13361             {
13362               tmp[28 - i] = (v % 10) + '0';
13363               v /= 10;
13364               i++;
13365             }
13366           strcpy (buf, tmp + 29 - i);
13367         }
13368     }
13369   else
13370     {
13371       if (hex)
13372         sprintf (buf, "0x%x", (unsigned int) disp);
13373       else
13374         sprintf (buf, "%d", (int) disp);
13375     }
13376 }
13377
13378 /* Put DISP in BUF as signed hex number.  */
13379
13380 static void
13381 print_displacement (char *buf, bfd_vma disp)
13382 {
13383   bfd_signed_vma val = disp;
13384   char tmp[30];
13385   int i, j = 0;
13386
13387   if (val < 0)
13388     {
13389       buf[j++] = '-';
13390       val = -disp;
13391
13392       /* Check for possible overflow.  */
13393       if (val < 0)
13394         {
13395           switch (address_mode)
13396             {
13397             case mode_64bit:
13398               strcpy (buf + j, "0x8000000000000000");
13399               break;
13400             case mode_32bit:
13401               strcpy (buf + j, "0x80000000");
13402               break;
13403             case mode_16bit:
13404               strcpy (buf + j, "0x8000");
13405               break;
13406             }
13407           return;
13408         }
13409     }
13410
13411   buf[j++] = '0';
13412   buf[j++] = 'x';
13413
13414   sprintf_vma (tmp, (bfd_vma) val);
13415   for (i = 0; tmp[i] == '0'; i++)
13416     continue;
13417   if (tmp[i] == '\0')
13418     i--;
13419   strcpy (buf + j, tmp + i);
13420 }
13421
13422 static void
13423 intel_operand_size (int bytemode, int sizeflag)
13424 {
13425   if (vex.evex
13426       && vex.b
13427       && (bytemode == x_mode
13428           || bytemode == evex_half_bcst_xmmq_mode))
13429     {
13430       if (vex.w)
13431         oappend ("QWORD PTR ");
13432       else
13433         oappend ("DWORD PTR ");
13434       return;
13435     }
13436   switch (bytemode)
13437     {
13438     case b_mode:
13439     case b_swap_mode:
13440     case dqb_mode:
13441     case db_mode:
13442       oappend ("BYTE PTR ");
13443       break;
13444     case w_mode:
13445     case dw_mode:
13446     case dqw_mode:
13447       oappend ("WORD PTR ");
13448       break;
13449     case indir_v_mode:
13450       if (address_mode == mode_64bit && isa64 == intel64)
13451         {
13452           oappend ("QWORD PTR ");
13453           break;
13454         }
13455       /* Fall through.  */
13456     case stack_v_mode:
13457       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13458         {
13459           oappend ("QWORD PTR ");
13460           break;
13461         }
13462       /* Fall through.  */
13463     case v_mode:
13464     case v_swap_mode:
13465     case dq_mode:
13466       USED_REX (REX_W);
13467       if (rex & REX_W)
13468         oappend ("QWORD PTR ");
13469       else
13470         {
13471           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13472             oappend ("DWORD PTR ");
13473           else
13474             oappend ("WORD PTR ");
13475           used_prefixes |= (prefixes & PREFIX_DATA);
13476         }
13477       break;
13478     case z_mode:
13479       if ((rex & REX_W) || (sizeflag & DFLAG))
13480         *obufp++ = 'D';
13481       oappend ("WORD PTR ");
13482       if (!(rex & REX_W))
13483         used_prefixes |= (prefixes & PREFIX_DATA);
13484       break;
13485     case a_mode:
13486       if (sizeflag & DFLAG)
13487         oappend ("QWORD PTR ");
13488       else
13489         oappend ("DWORD PTR ");
13490       used_prefixes |= (prefixes & PREFIX_DATA);
13491       break;
13492     case d_mode:
13493     case d_scalar_mode:
13494     case d_scalar_swap_mode:
13495     case d_swap_mode:
13496     case dqd_mode:
13497       oappend ("DWORD PTR ");
13498       break;
13499     case q_mode:
13500     case q_scalar_mode:
13501     case q_scalar_swap_mode:
13502     case q_swap_mode:
13503       oappend ("QWORD PTR ");
13504       break;
13505     case dqa_mode:
13506     case m_mode:
13507       if (address_mode == mode_64bit)
13508         oappend ("QWORD PTR ");
13509       else
13510         oappend ("DWORD PTR ");
13511       break;
13512     case f_mode:
13513       if (sizeflag & DFLAG)
13514         oappend ("FWORD PTR ");
13515       else
13516         oappend ("DWORD PTR ");
13517       used_prefixes |= (prefixes & PREFIX_DATA);
13518       break;
13519     case t_mode:
13520       oappend ("TBYTE PTR ");
13521       break;
13522     case x_mode:
13523     case x_swap_mode:
13524     case evex_x_gscat_mode:
13525     case evex_x_nobcst_mode:
13526     case b_scalar_mode:
13527     case w_scalar_mode:
13528       if (need_vex)
13529         {
13530           switch (vex.length)
13531             {
13532             case 128:
13533               oappend ("XMMWORD PTR ");
13534               break;
13535             case 256:
13536               oappend ("YMMWORD PTR ");
13537               break;
13538             case 512:
13539               oappend ("ZMMWORD PTR ");
13540               break;
13541             default:
13542               abort ();
13543             }
13544         }
13545       else
13546         oappend ("XMMWORD PTR ");
13547       break;
13548     case xmm_mode:
13549       oappend ("XMMWORD PTR ");
13550       break;
13551     case ymm_mode:
13552       oappend ("YMMWORD PTR ");
13553       break;
13554     case xmmq_mode:
13555     case evex_half_bcst_xmmq_mode:
13556       if (!need_vex)
13557         abort ();
13558
13559       switch (vex.length)
13560         {
13561         case 128:
13562           oappend ("QWORD PTR ");
13563           break;
13564         case 256:
13565           oappend ("XMMWORD PTR ");
13566           break;
13567         case 512:
13568           oappend ("YMMWORD PTR ");
13569           break;
13570         default:
13571           abort ();
13572         }
13573       break;
13574     case xmm_mb_mode:
13575       if (!need_vex)
13576         abort ();
13577
13578       switch (vex.length)
13579         {
13580         case 128:
13581         case 256:
13582         case 512:
13583           oappend ("BYTE PTR ");
13584           break;
13585         default:
13586           abort ();
13587         }
13588       break;
13589     case xmm_mw_mode:
13590       if (!need_vex)
13591         abort ();
13592
13593       switch (vex.length)
13594         {
13595         case 128:
13596         case 256:
13597         case 512:
13598           oappend ("WORD PTR ");
13599           break;
13600         default:
13601           abort ();
13602         }
13603       break;
13604     case xmm_md_mode:
13605       if (!need_vex)
13606         abort ();
13607
13608       switch (vex.length)
13609         {
13610         case 128:
13611         case 256:
13612         case 512:
13613           oappend ("DWORD PTR ");
13614           break;
13615         default:
13616           abort ();
13617         }
13618       break;
13619     case xmm_mq_mode:
13620       if (!need_vex)
13621         abort ();
13622
13623       switch (vex.length)
13624         {
13625         case 128:
13626         case 256:
13627         case 512:
13628           oappend ("QWORD PTR ");
13629           break;
13630         default:
13631           abort ();
13632         }
13633       break;
13634     case xmmdw_mode:
13635       if (!need_vex)
13636         abort ();
13637
13638       switch (vex.length)
13639         {
13640         case 128:
13641           oappend ("WORD PTR ");
13642           break;
13643         case 256:
13644           oappend ("DWORD PTR ");
13645           break;
13646         case 512:
13647           oappend ("QWORD PTR ");
13648           break;
13649         default:
13650           abort ();
13651         }
13652       break;
13653     case xmmqd_mode:
13654       if (!need_vex)
13655         abort ();
13656
13657       switch (vex.length)
13658         {
13659         case 128:
13660           oappend ("DWORD PTR ");
13661           break;
13662         case 256:
13663           oappend ("QWORD PTR ");
13664           break;
13665         case 512:
13666           oappend ("XMMWORD PTR ");
13667           break;
13668         default:
13669           abort ();
13670         }
13671       break;
13672     case ymmq_mode:
13673       if (!need_vex)
13674         abort ();
13675
13676       switch (vex.length)
13677         {
13678         case 128:
13679           oappend ("QWORD PTR ");
13680           break;
13681         case 256:
13682           oappend ("YMMWORD PTR ");
13683           break;
13684         case 512:
13685           oappend ("ZMMWORD PTR ");
13686           break;
13687         default:
13688           abort ();
13689         }
13690       break;
13691     case ymmxmm_mode:
13692       if (!need_vex)
13693         abort ();
13694
13695       switch (vex.length)
13696         {
13697         case 128:
13698         case 256:
13699           oappend ("XMMWORD PTR ");
13700           break;
13701         default:
13702           abort ();
13703         }
13704       break;
13705     case o_mode:
13706       oappend ("OWORD PTR ");
13707       break;
13708     case xmm_mdq_mode:
13709     case vex_w_dq_mode:
13710     case vex_scalar_w_dq_mode:
13711       if (!need_vex)
13712         abort ();
13713
13714       if (vex.w)
13715         oappend ("QWORD PTR ");
13716       else
13717         oappend ("DWORD PTR ");
13718       break;
13719     case vex_vsib_d_w_dq_mode:
13720     case vex_vsib_q_w_dq_mode:
13721       if (!need_vex)
13722         abort ();
13723
13724       if (!vex.evex)
13725         {
13726           if (vex.w)
13727             oappend ("QWORD PTR ");
13728           else
13729             oappend ("DWORD PTR ");
13730         }
13731       else
13732         {
13733           switch (vex.length)
13734             {
13735             case 128:
13736               oappend ("XMMWORD PTR ");
13737               break;
13738             case 256:
13739               oappend ("YMMWORD PTR ");
13740               break;
13741             case 512:
13742               oappend ("ZMMWORD PTR ");
13743               break;
13744             default:
13745               abort ();
13746             }
13747         }
13748       break;
13749     case vex_vsib_q_w_d_mode:
13750     case vex_vsib_d_w_d_mode:
13751       if (!need_vex || !vex.evex)
13752         abort ();
13753
13754       switch (vex.length)
13755         {
13756         case 128:
13757           oappend ("QWORD PTR ");
13758           break;
13759         case 256:
13760           oappend ("XMMWORD PTR ");
13761           break;
13762         case 512:
13763           oappend ("YMMWORD PTR ");
13764           break;
13765         default:
13766           abort ();
13767         }
13768
13769       break;
13770     case mask_bd_mode:
13771       if (!need_vex || vex.length != 128)
13772         abort ();
13773       if (vex.w)
13774         oappend ("DWORD PTR ");
13775       else
13776         oappend ("BYTE PTR ");
13777       break;
13778     case mask_mode:
13779       if (!need_vex)
13780         abort ();
13781       if (vex.w)
13782         oappend ("QWORD PTR ");
13783       else
13784         oappend ("WORD PTR ");
13785       break;
13786     case v_bnd_mode:
13787     case v_bndmk_mode:
13788     default:
13789       break;
13790     }
13791 }
13792
13793 static void
13794 OP_E_register (int bytemode, int sizeflag)
13795 {
13796   int reg = modrm.rm;
13797   const char **names;
13798
13799   USED_REX (REX_B);
13800   if ((rex & REX_B))
13801     reg += 8;
13802
13803   if ((sizeflag & SUFFIX_ALWAYS)
13804       && (bytemode == b_swap_mode
13805           || bytemode == bnd_swap_mode
13806           || bytemode == v_swap_mode))
13807     swap_operand ();
13808
13809   switch (bytemode)
13810     {
13811     case b_mode:
13812     case b_swap_mode:
13813       USED_REX (0);
13814       if (rex)
13815         names = names8rex;
13816       else
13817         names = names8;
13818       break;
13819     case w_mode:
13820       names = names16;
13821       break;
13822     case d_mode:
13823     case dw_mode:
13824     case db_mode:
13825       names = names32;
13826       break;
13827     case q_mode:
13828       names = names64;
13829       break;
13830     case m_mode:
13831     case v_bnd_mode:
13832       names = address_mode == mode_64bit ? names64 : names32;
13833       break;
13834     case bnd_mode:
13835     case bnd_swap_mode:
13836       if (reg > 0x3)
13837         {
13838           oappend ("(bad)");
13839           return;
13840         }
13841       names = names_bnd;
13842       break;
13843     case indir_v_mode:
13844       if (address_mode == mode_64bit && isa64 == intel64)
13845         {
13846           names = names64;
13847           break;
13848         }
13849       /* Fall through.  */
13850     case stack_v_mode:
13851       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13852         {
13853           names = names64;
13854           break;
13855         }
13856       bytemode = v_mode;
13857       /* Fall through.  */
13858     case v_mode:
13859     case v_swap_mode:
13860     case dq_mode:
13861     case dqb_mode:
13862     case dqd_mode:
13863     case dqw_mode:
13864     case dqa_mode:
13865       USED_REX (REX_W);
13866       if (rex & REX_W)
13867         names = names64;
13868       else
13869         {
13870           if ((sizeflag & DFLAG)
13871               || (bytemode != v_mode
13872                   && bytemode != v_swap_mode))
13873             names = names32;
13874           else
13875             names = names16;
13876           used_prefixes |= (prefixes & PREFIX_DATA);
13877         }
13878       break;
13879     case va_mode:
13880       names = (address_mode == mode_64bit
13881                ? names64 : names32);
13882       if (!(prefixes & PREFIX_ADDR))
13883         names = (address_mode == mode_16bit
13884                      ? names16 : names);
13885       else
13886         {
13887           /* Remove "addr16/addr32".  */
13888           all_prefixes[last_addr_prefix] = 0;
13889           names = (address_mode != mode_32bit
13890                        ? names32 : names16);
13891           used_prefixes |= PREFIX_ADDR;
13892         }
13893       break;
13894     case mask_bd_mode:
13895     case mask_mode:
13896       if (reg > 0x7)
13897         {
13898           oappend ("(bad)");
13899           return;
13900         }
13901       names = names_mask;
13902       break;
13903     case 0:
13904       return;
13905     default:
13906       oappend (INTERNAL_DISASSEMBLER_ERROR);
13907       return;
13908     }
13909   oappend (names[reg]);
13910 }
13911
13912 static void
13913 OP_E_memory (int bytemode, int sizeflag)
13914 {
13915   bfd_vma disp = 0;
13916   int add = (rex & REX_B) ? 8 : 0;
13917   int riprel = 0;
13918   int shift;
13919
13920   if (vex.evex)
13921     {
13922       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13923       if (vex.b
13924           && bytemode != x_mode
13925           && bytemode != xmmq_mode
13926           && bytemode != evex_half_bcst_xmmq_mode)
13927         {
13928           BadOp ();
13929           return;
13930         }
13931       switch (bytemode)
13932         {
13933         case dqw_mode:
13934         case dw_mode:
13935           shift = 1;
13936           break;
13937         case dqb_mode:
13938         case db_mode:
13939           shift = 0;
13940           break;
13941         case dq_mode:
13942           if (address_mode != mode_64bit)
13943             {
13944               shift = 2;
13945               break;
13946             }
13947             /* fall through */
13948         case vex_vsib_d_w_dq_mode:
13949         case vex_vsib_d_w_d_mode:
13950         case vex_vsib_q_w_dq_mode:
13951         case vex_vsib_q_w_d_mode:
13952         case evex_x_gscat_mode:
13953         case xmm_mdq_mode:
13954           shift = vex.w ? 3 : 2;
13955           break;
13956         case x_mode:
13957         case evex_half_bcst_xmmq_mode:
13958         case xmmq_mode:
13959           if (vex.b)
13960             {
13961               shift = vex.w ? 3 : 2;
13962               break;
13963             }
13964           /* Fall through.  */
13965         case xmmqd_mode:
13966         case xmmdw_mode:
13967         case ymmq_mode:
13968         case evex_x_nobcst_mode:
13969         case x_swap_mode:
13970           switch (vex.length)
13971             {
13972             case 128:
13973               shift = 4;
13974               break;
13975             case 256:
13976               shift = 5;
13977               break;
13978             case 512:
13979               shift = 6;
13980               break;
13981             default:
13982               abort ();
13983             }
13984           break;
13985         case ymm_mode:
13986           shift = 5;
13987           break;
13988         case xmm_mode:
13989           shift = 4;
13990           break;
13991         case xmm_mq_mode:
13992         case q_mode:
13993         case q_scalar_mode:
13994         case q_swap_mode:
13995         case q_scalar_swap_mode:
13996           shift = 3;
13997           break;
13998         case dqd_mode:
13999         case xmm_md_mode:
14000         case d_mode:
14001         case d_scalar_mode:
14002         case d_swap_mode:
14003         case d_scalar_swap_mode:
14004           shift = 2;
14005           break;
14006         case w_scalar_mode:
14007         case xmm_mw_mode:
14008           shift = 1;
14009           break;
14010         case b_scalar_mode:
14011         case xmm_mb_mode:
14012           shift = 0;
14013           break;
14014         case dqa_mode:
14015           shift = address_mode == mode_64bit ? 3 : 2;
14016           break;
14017         default:
14018           abort ();
14019         }
14020       /* Make necessary corrections to shift for modes that need it.
14021          For these modes we currently have shift 4, 5 or 6 depending on
14022          vex.length (it corresponds to xmmword, ymmword or zmmword
14023          operand).  We might want to make it 3, 4 or 5 (e.g. for
14024          xmmq_mode).  In case of broadcast enabled the corrections
14025          aren't needed, as element size is always 32 or 64 bits.  */
14026       if (!vex.b
14027           && (bytemode == xmmq_mode
14028               || bytemode == evex_half_bcst_xmmq_mode))
14029         shift -= 1;
14030       else if (bytemode == xmmqd_mode)
14031         shift -= 2;
14032       else if (bytemode == xmmdw_mode)
14033         shift -= 3;
14034       else if (bytemode == ymmq_mode && vex.length == 128)
14035         shift -= 1;
14036     }
14037   else
14038     shift = 0;
14039
14040   USED_REX (REX_B);
14041   if (intel_syntax)
14042     intel_operand_size (bytemode, sizeflag);
14043   append_seg ();
14044
14045   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14046     {
14047       /* 32/64 bit address mode */
14048       int havedisp;
14049       int havesib;
14050       int havebase;
14051       int haveindex;
14052       int needindex;
14053       int needaddr32;
14054       int base, rbase;
14055       int vindex = 0;
14056       int scale = 0;
14057       int addr32flag = !((sizeflag & AFLAG)
14058                          || bytemode == v_bnd_mode
14059                          || bytemode == v_bndmk_mode
14060                          || bytemode == bnd_mode
14061                          || bytemode == bnd_swap_mode);
14062       const char **indexes64 = names64;
14063       const char **indexes32 = names32;
14064
14065       havesib = 0;
14066       havebase = 1;
14067       haveindex = 0;
14068       base = modrm.rm;
14069
14070       if (base == 4)
14071         {
14072           havesib = 1;
14073           vindex = sib.index;
14074           USED_REX (REX_X);
14075           if (rex & REX_X)
14076             vindex += 8;
14077           switch (bytemode)
14078             {
14079             case vex_vsib_d_w_dq_mode:
14080             case vex_vsib_d_w_d_mode:
14081             case vex_vsib_q_w_dq_mode:
14082             case vex_vsib_q_w_d_mode:
14083               if (!need_vex)
14084                 abort ();
14085               if (vex.evex)
14086                 {
14087                   if (!vex.v)
14088                     vindex += 16;
14089                 }
14090
14091               haveindex = 1;
14092               switch (vex.length)
14093                 {
14094                 case 128:
14095                   indexes64 = indexes32 = names_xmm;
14096                   break;
14097                 case 256:
14098                   if (!vex.w
14099                       || bytemode == vex_vsib_q_w_dq_mode
14100                       || bytemode == vex_vsib_q_w_d_mode)
14101                     indexes64 = indexes32 = names_ymm;
14102                   else
14103                     indexes64 = indexes32 = names_xmm;
14104                   break;
14105                 case 512:
14106                   if (!vex.w
14107                       || bytemode == vex_vsib_q_w_dq_mode
14108                       || bytemode == vex_vsib_q_w_d_mode)
14109                     indexes64 = indexes32 = names_zmm;
14110                   else
14111                     indexes64 = indexes32 = names_ymm;
14112                   break;
14113                 default:
14114                   abort ();
14115                 }
14116               break;
14117             default:
14118               haveindex = vindex != 4;
14119               break;
14120             }
14121           scale = sib.scale;
14122           base = sib.base;
14123           codep++;
14124         }
14125       rbase = base + add;
14126
14127       switch (modrm.mod)
14128         {
14129         case 0:
14130           if (base == 5)
14131             {
14132               havebase = 0;
14133               if (address_mode == mode_64bit && !havesib)
14134                 riprel = 1;
14135               disp = get32s ();
14136               if (riprel && bytemode == v_bndmk_mode)
14137                 {
14138                   oappend ("(bad)");
14139                   return;
14140                 }
14141             }
14142           break;
14143         case 1:
14144           FETCH_DATA (the_info, codep + 1);
14145           disp = *codep++;
14146           if ((disp & 0x80) != 0)
14147             disp -= 0x100;
14148           if (vex.evex && shift > 0)
14149             disp <<= shift;
14150           break;
14151         case 2:
14152           disp = get32s ();
14153           break;
14154         }
14155
14156       needindex = 0;
14157       needaddr32 = 0;
14158       if (havesib
14159           && !havebase
14160           && !haveindex
14161           && address_mode != mode_16bit)
14162         {
14163           if (address_mode == mode_64bit)
14164             {
14165               /* Display eiz instead of addr32.  */
14166               needindex = addr32flag;
14167               needaddr32 = 1;
14168             }
14169           else
14170             {
14171               /* In 32-bit mode, we need index register to tell [offset]
14172                  from [eiz*1 + offset].  */
14173               needindex = 1;
14174             }
14175         }
14176
14177       havedisp = (havebase
14178                   || needindex
14179                   || (havesib && (haveindex || scale != 0)));
14180
14181       if (!intel_syntax)
14182         if (modrm.mod != 0 || base == 5)
14183           {
14184             if (havedisp || riprel)
14185               print_displacement (scratchbuf, disp);
14186             else
14187               print_operand_value (scratchbuf, 1, disp);
14188             oappend (scratchbuf);
14189             if (riprel)
14190               {
14191                 set_op (disp, 1);
14192                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14193               }
14194           }
14195
14196       if ((havebase || haveindex || needaddr32 || riprel)
14197           && (bytemode != v_bnd_mode)
14198           && (bytemode != v_bndmk_mode)
14199           && (bytemode != bnd_mode)
14200           && (bytemode != bnd_swap_mode))
14201         used_prefixes |= PREFIX_ADDR;
14202
14203       if (havedisp || (intel_syntax && riprel))
14204         {
14205           *obufp++ = open_char;
14206           if (intel_syntax && riprel)
14207             {
14208               set_op (disp, 1);
14209               oappend (!addr32flag ? "rip" : "eip");
14210             }
14211           *obufp = '\0';
14212           if (havebase)
14213             oappend (address_mode == mode_64bit && !addr32flag
14214                      ? names64[rbase] : names32[rbase]);
14215           if (havesib)
14216             {
14217               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14218                  print index to tell base + index from base.  */
14219               if (scale != 0
14220                   || needindex
14221                   || haveindex
14222                   || (havebase && base != ESP_REG_NUM))
14223                 {
14224                   if (!intel_syntax || havebase)
14225                     {
14226                       *obufp++ = separator_char;
14227                       *obufp = '\0';
14228                     }
14229                   if (haveindex)
14230                     oappend (address_mode == mode_64bit && !addr32flag
14231                              ? indexes64[vindex] : indexes32[vindex]);
14232                   else
14233                     oappend (address_mode == mode_64bit && !addr32flag
14234                              ? index64 : index32);
14235
14236                   *obufp++ = scale_char;
14237                   *obufp = '\0';
14238                   sprintf (scratchbuf, "%d", 1 << scale);
14239                   oappend (scratchbuf);
14240                 }
14241             }
14242           if (intel_syntax
14243               && (disp || modrm.mod != 0 || base == 5))
14244             {
14245               if (!havedisp || (bfd_signed_vma) disp >= 0)
14246                 {
14247                   *obufp++ = '+';
14248                   *obufp = '\0';
14249                 }
14250               else if (modrm.mod != 1 && disp != -disp)
14251                 {
14252                   *obufp++ = '-';
14253                   *obufp = '\0';
14254                   disp = - (bfd_signed_vma) disp;
14255                 }
14256
14257               if (havedisp)
14258                 print_displacement (scratchbuf, disp);
14259               else
14260                 print_operand_value (scratchbuf, 1, disp);
14261               oappend (scratchbuf);
14262             }
14263
14264           *obufp++ = close_char;
14265           *obufp = '\0';
14266         }
14267       else if (intel_syntax)
14268         {
14269           if (modrm.mod != 0 || base == 5)
14270             {
14271               if (!active_seg_prefix)
14272                 {
14273                   oappend (names_seg[ds_reg - es_reg]);
14274                   oappend (":");
14275                 }
14276               print_operand_value (scratchbuf, 1, disp);
14277               oappend (scratchbuf);
14278             }
14279         }
14280     }
14281   else
14282     {
14283       /* 16 bit address mode */
14284       used_prefixes |= prefixes & PREFIX_ADDR;
14285       switch (modrm.mod)
14286         {
14287         case 0:
14288           if (modrm.rm == 6)
14289             {
14290               disp = get16 ();
14291               if ((disp & 0x8000) != 0)
14292                 disp -= 0x10000;
14293             }
14294           break;
14295         case 1:
14296           FETCH_DATA (the_info, codep + 1);
14297           disp = *codep++;
14298           if ((disp & 0x80) != 0)
14299             disp -= 0x100;
14300           if (vex.evex && shift > 0)
14301             disp <<= shift;
14302           break;
14303         case 2:
14304           disp = get16 ();
14305           if ((disp & 0x8000) != 0)
14306             disp -= 0x10000;
14307           break;
14308         }
14309
14310       if (!intel_syntax)
14311         if (modrm.mod != 0 || modrm.rm == 6)
14312           {
14313             print_displacement (scratchbuf, disp);
14314             oappend (scratchbuf);
14315           }
14316
14317       if (modrm.mod != 0 || modrm.rm != 6)
14318         {
14319           *obufp++ = open_char;
14320           *obufp = '\0';
14321           oappend (index16[modrm.rm]);
14322           if (intel_syntax
14323               && (disp || modrm.mod != 0 || modrm.rm == 6))
14324             {
14325               if ((bfd_signed_vma) disp >= 0)
14326                 {
14327                   *obufp++ = '+';
14328                   *obufp = '\0';
14329                 }
14330               else if (modrm.mod != 1)
14331                 {
14332                   *obufp++ = '-';
14333                   *obufp = '\0';
14334                   disp = - (bfd_signed_vma) disp;
14335                 }
14336
14337               print_displacement (scratchbuf, disp);
14338               oappend (scratchbuf);
14339             }
14340
14341           *obufp++ = close_char;
14342           *obufp = '\0';
14343         }
14344       else if (intel_syntax)
14345         {
14346           if (!active_seg_prefix)
14347             {
14348               oappend (names_seg[ds_reg - es_reg]);
14349               oappend (":");
14350             }
14351           print_operand_value (scratchbuf, 1, disp & 0xffff);
14352           oappend (scratchbuf);
14353         }
14354     }
14355   if (vex.evex && vex.b
14356       && (bytemode == x_mode
14357           || bytemode == xmmq_mode
14358           || bytemode == evex_half_bcst_xmmq_mode))
14359     {
14360       if (vex.w
14361           || bytemode == xmmq_mode
14362           || bytemode == evex_half_bcst_xmmq_mode)
14363         {
14364           switch (vex.length)
14365             {
14366             case 128:
14367               oappend ("{1to2}");
14368               break;
14369             case 256:
14370               oappend ("{1to4}");
14371               break;
14372             case 512:
14373               oappend ("{1to8}");
14374               break;
14375             default:
14376               abort ();
14377             }
14378         }
14379       else
14380         {
14381           switch (vex.length)
14382             {
14383             case 128:
14384               oappend ("{1to4}");
14385               break;
14386             case 256:
14387               oappend ("{1to8}");
14388               break;
14389             case 512:
14390               oappend ("{1to16}");
14391               break;
14392             default:
14393               abort ();
14394             }
14395         }
14396     }
14397 }
14398
14399 static void
14400 OP_E (int bytemode, int sizeflag)
14401 {
14402   /* Skip mod/rm byte.  */
14403   MODRM_CHECK;
14404   codep++;
14405
14406   if (modrm.mod == 3)
14407     OP_E_register (bytemode, sizeflag);
14408   else
14409     OP_E_memory (bytemode, sizeflag);
14410 }
14411
14412 static void
14413 OP_G (int bytemode, int sizeflag)
14414 {
14415   int add = 0;
14416   const char **names;
14417   USED_REX (REX_R);
14418   if (rex & REX_R)
14419     add += 8;
14420   switch (bytemode)
14421     {
14422     case b_mode:
14423       USED_REX (0);
14424       if (rex)
14425         oappend (names8rex[modrm.reg + add]);
14426       else
14427         oappend (names8[modrm.reg + add]);
14428       break;
14429     case w_mode:
14430       oappend (names16[modrm.reg + add]);
14431       break;
14432     case d_mode:
14433     case db_mode:
14434     case dw_mode:
14435       oappend (names32[modrm.reg + add]);
14436       break;
14437     case q_mode:
14438       oappend (names64[modrm.reg + add]);
14439       break;
14440     case bnd_mode:
14441       if (modrm.reg > 0x3)
14442         {
14443           oappend ("(bad)");
14444           return;
14445         }
14446       oappend (names_bnd[modrm.reg]);
14447       break;
14448     case v_mode:
14449     case dq_mode:
14450     case dqb_mode:
14451     case dqd_mode:
14452     case dqw_mode:
14453       USED_REX (REX_W);
14454       if (rex & REX_W)
14455         oappend (names64[modrm.reg + add]);
14456       else
14457         {
14458           if ((sizeflag & DFLAG) || bytemode != v_mode)
14459             oappend (names32[modrm.reg + add]);
14460           else
14461             oappend (names16[modrm.reg + add]);
14462           used_prefixes |= (prefixes & PREFIX_DATA);
14463         }
14464       break;
14465     case va_mode:
14466       names = (address_mode == mode_64bit
14467                ? names64 : names32);
14468       if (!(prefixes & PREFIX_ADDR))
14469         {
14470           if (address_mode == mode_16bit)
14471             names = names16;
14472         }
14473       else
14474         {
14475           /* Remove "addr16/addr32".  */
14476           all_prefixes[last_addr_prefix] = 0;
14477           names = (address_mode != mode_32bit
14478                        ? names32 : names16);
14479           used_prefixes |= PREFIX_ADDR;
14480         }
14481       oappend (names[modrm.reg + add]);
14482       break;
14483     case m_mode:
14484       if (address_mode == mode_64bit)
14485         oappend (names64[modrm.reg + add]);
14486       else
14487         oappend (names32[modrm.reg + add]);
14488       break;
14489     case mask_bd_mode:
14490     case mask_mode:
14491       if ((modrm.reg + add) > 0x7)
14492         {
14493           oappend ("(bad)");
14494           return;
14495         }
14496       oappend (names_mask[modrm.reg + add]);
14497       break;
14498     default:
14499       oappend (INTERNAL_DISASSEMBLER_ERROR);
14500       break;
14501     }
14502 }
14503
14504 static bfd_vma
14505 get64 (void)
14506 {
14507   bfd_vma x;
14508 #ifdef BFD64
14509   unsigned int a;
14510   unsigned int b;
14511
14512   FETCH_DATA (the_info, codep + 8);
14513   a = *codep++ & 0xff;
14514   a |= (*codep++ & 0xff) << 8;
14515   a |= (*codep++ & 0xff) << 16;
14516   a |= (*codep++ & 0xffu) << 24;
14517   b = *codep++ & 0xff;
14518   b |= (*codep++ & 0xff) << 8;
14519   b |= (*codep++ & 0xff) << 16;
14520   b |= (*codep++ & 0xffu) << 24;
14521   x = a + ((bfd_vma) b << 32);
14522 #else
14523   abort ();
14524   x = 0;
14525 #endif
14526   return x;
14527 }
14528
14529 static bfd_signed_vma
14530 get32 (void)
14531 {
14532   bfd_signed_vma x = 0;
14533
14534   FETCH_DATA (the_info, codep + 4);
14535   x = *codep++ & (bfd_signed_vma) 0xff;
14536   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14537   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14538   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14539   return x;
14540 }
14541
14542 static bfd_signed_vma
14543 get32s (void)
14544 {
14545   bfd_signed_vma x = 0;
14546
14547   FETCH_DATA (the_info, codep + 4);
14548   x = *codep++ & (bfd_signed_vma) 0xff;
14549   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14550   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14551   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14552
14553   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14554
14555   return x;
14556 }
14557
14558 static int
14559 get16 (void)
14560 {
14561   int x = 0;
14562
14563   FETCH_DATA (the_info, codep + 2);
14564   x = *codep++ & 0xff;
14565   x |= (*codep++ & 0xff) << 8;
14566   return x;
14567 }
14568
14569 static void
14570 set_op (bfd_vma op, int riprel)
14571 {
14572   op_index[op_ad] = op_ad;
14573   if (address_mode == mode_64bit)
14574     {
14575       op_address[op_ad] = op;
14576       op_riprel[op_ad] = riprel;
14577     }
14578   else
14579     {
14580       /* Mask to get a 32-bit address.  */
14581       op_address[op_ad] = op & 0xffffffff;
14582       op_riprel[op_ad] = riprel & 0xffffffff;
14583     }
14584 }
14585
14586 static void
14587 OP_REG (int code, int sizeflag)
14588 {
14589   const char *s;
14590   int add;
14591
14592   switch (code)
14593     {
14594     case es_reg: case ss_reg: case cs_reg:
14595     case ds_reg: case fs_reg: case gs_reg:
14596       oappend (names_seg[code - es_reg]);
14597       return;
14598     }
14599
14600   USED_REX (REX_B);
14601   if (rex & REX_B)
14602     add = 8;
14603   else
14604     add = 0;
14605
14606   switch (code)
14607     {
14608     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14609     case sp_reg: case bp_reg: case si_reg: case di_reg:
14610       s = names16[code - ax_reg + add];
14611       break;
14612     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14613     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14614       USED_REX (0);
14615       if (rex)
14616         s = names8rex[code - al_reg + add];
14617       else
14618         s = names8[code - al_reg];
14619       break;
14620     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14621     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14622       if (address_mode == mode_64bit
14623           && ((sizeflag & DFLAG) || (rex & REX_W)))
14624         {
14625           s = names64[code - rAX_reg + add];
14626           break;
14627         }
14628       code += eAX_reg - rAX_reg;
14629       /* Fall through.  */
14630     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14631     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14632       USED_REX (REX_W);
14633       if (rex & REX_W)
14634         s = names64[code - eAX_reg + add];
14635       else
14636         {
14637           if (sizeflag & DFLAG)
14638             s = names32[code - eAX_reg + add];
14639           else
14640             s = names16[code - eAX_reg + add];
14641           used_prefixes |= (prefixes & PREFIX_DATA);
14642         }
14643       break;
14644     default:
14645       s = INTERNAL_DISASSEMBLER_ERROR;
14646       break;
14647     }
14648   oappend (s);
14649 }
14650
14651 static void
14652 OP_IMREG (int code, int sizeflag)
14653 {
14654   const char *s;
14655
14656   switch (code)
14657     {
14658     case indir_dx_reg:
14659       if (intel_syntax)
14660         s = "dx";
14661       else
14662         s = "(%dx)";
14663       break;
14664     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14665     case sp_reg: case bp_reg: case si_reg: case di_reg:
14666       s = names16[code - ax_reg];
14667       break;
14668     case es_reg: case ss_reg: case cs_reg:
14669     case ds_reg: case fs_reg: case gs_reg:
14670       s = names_seg[code - es_reg];
14671       break;
14672     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14673     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14674       USED_REX (0);
14675       if (rex)
14676         s = names8rex[code - al_reg];
14677       else
14678         s = names8[code - al_reg];
14679       break;
14680     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14681     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14682       USED_REX (REX_W);
14683       if (rex & REX_W)
14684         s = names64[code - eAX_reg];
14685       else
14686         {
14687           if (sizeflag & DFLAG)
14688             s = names32[code - eAX_reg];
14689           else
14690             s = names16[code - eAX_reg];
14691           used_prefixes |= (prefixes & PREFIX_DATA);
14692         }
14693       break;
14694     case z_mode_ax_reg:
14695       if ((rex & REX_W) || (sizeflag & DFLAG))
14696         s = *names32;
14697       else
14698         s = *names16;
14699       if (!(rex & REX_W))
14700         used_prefixes |= (prefixes & PREFIX_DATA);
14701       break;
14702     default:
14703       s = INTERNAL_DISASSEMBLER_ERROR;
14704       break;
14705     }
14706   oappend (s);
14707 }
14708
14709 static void
14710 OP_I (int bytemode, int sizeflag)
14711 {
14712   bfd_signed_vma op;
14713   bfd_signed_vma mask = -1;
14714
14715   switch (bytemode)
14716     {
14717     case b_mode:
14718       FETCH_DATA (the_info, codep + 1);
14719       op = *codep++;
14720       mask = 0xff;
14721       break;
14722     case q_mode:
14723       if (address_mode == mode_64bit)
14724         {
14725           op = get32s ();
14726           break;
14727         }
14728       /* Fall through.  */
14729     case v_mode:
14730       USED_REX (REX_W);
14731       if (rex & REX_W)
14732         op = get32s ();
14733       else
14734         {
14735           if (sizeflag & DFLAG)
14736             {
14737               op = get32 ();
14738               mask = 0xffffffff;
14739             }
14740           else
14741             {
14742               op = get16 ();
14743               mask = 0xfffff;
14744             }
14745           used_prefixes |= (prefixes & PREFIX_DATA);
14746         }
14747       break;
14748     case w_mode:
14749       mask = 0xfffff;
14750       op = get16 ();
14751       break;
14752     case const_1_mode:
14753       if (intel_syntax)
14754         oappend ("1");
14755       return;
14756     default:
14757       oappend (INTERNAL_DISASSEMBLER_ERROR);
14758       return;
14759     }
14760
14761   op &= mask;
14762   scratchbuf[0] = '$';
14763   print_operand_value (scratchbuf + 1, 1, op);
14764   oappend_maybe_intel (scratchbuf);
14765   scratchbuf[0] = '\0';
14766 }
14767
14768 static void
14769 OP_I64 (int bytemode, int sizeflag)
14770 {
14771   bfd_signed_vma op;
14772   bfd_signed_vma mask = -1;
14773
14774   if (address_mode != mode_64bit)
14775     {
14776       OP_I (bytemode, sizeflag);
14777       return;
14778     }
14779
14780   switch (bytemode)
14781     {
14782     case b_mode:
14783       FETCH_DATA (the_info, codep + 1);
14784       op = *codep++;
14785       mask = 0xff;
14786       break;
14787     case v_mode:
14788       USED_REX (REX_W);
14789       if (rex & REX_W)
14790         op = get64 ();
14791       else
14792         {
14793           if (sizeflag & DFLAG)
14794             {
14795               op = get32 ();
14796               mask = 0xffffffff;
14797             }
14798           else
14799             {
14800               op = get16 ();
14801               mask = 0xfffff;
14802             }
14803           used_prefixes |= (prefixes & PREFIX_DATA);
14804         }
14805       break;
14806     case w_mode:
14807       mask = 0xfffff;
14808       op = get16 ();
14809       break;
14810     default:
14811       oappend (INTERNAL_DISASSEMBLER_ERROR);
14812       return;
14813     }
14814
14815   op &= mask;
14816   scratchbuf[0] = '$';
14817   print_operand_value (scratchbuf + 1, 1, op);
14818   oappend_maybe_intel (scratchbuf);
14819   scratchbuf[0] = '\0';
14820 }
14821
14822 static void
14823 OP_sI (int bytemode, int sizeflag)
14824 {
14825   bfd_signed_vma op;
14826
14827   switch (bytemode)
14828     {
14829     case b_mode:
14830     case b_T_mode:
14831       FETCH_DATA (the_info, codep + 1);
14832       op = *codep++;
14833       if ((op & 0x80) != 0)
14834         op -= 0x100;
14835       if (bytemode == b_T_mode)
14836         {
14837           if (address_mode != mode_64bit
14838               || !((sizeflag & DFLAG) || (rex & REX_W)))
14839             {
14840               /* The operand-size prefix is overridden by a REX prefix.  */
14841               if ((sizeflag & DFLAG) || (rex & REX_W))
14842                 op &= 0xffffffff;
14843               else
14844                 op &= 0xffff;
14845           }
14846         }
14847       else
14848         {
14849           if (!(rex & REX_W))
14850             {
14851               if (sizeflag & DFLAG)
14852                 op &= 0xffffffff;
14853               else
14854                 op &= 0xffff;
14855             }
14856         }
14857       break;
14858     case v_mode:
14859       /* The operand-size prefix is overridden by a REX prefix.  */
14860       if ((sizeflag & DFLAG) || (rex & REX_W))
14861         op = get32s ();
14862       else
14863         op = get16 ();
14864       break;
14865     default:
14866       oappend (INTERNAL_DISASSEMBLER_ERROR);
14867       return;
14868     }
14869
14870   scratchbuf[0] = '$';
14871   print_operand_value (scratchbuf + 1, 1, op);
14872   oappend_maybe_intel (scratchbuf);
14873 }
14874
14875 static void
14876 OP_J (int bytemode, int sizeflag)
14877 {
14878   bfd_vma disp;
14879   bfd_vma mask = -1;
14880   bfd_vma segment = 0;
14881
14882   switch (bytemode)
14883     {
14884     case b_mode:
14885       FETCH_DATA (the_info, codep + 1);
14886       disp = *codep++;
14887       if ((disp & 0x80) != 0)
14888         disp -= 0x100;
14889       break;
14890     case v_mode:
14891       if (isa64 == amd64)
14892         USED_REX (REX_W);
14893       if ((sizeflag & DFLAG)
14894           || (address_mode == mode_64bit
14895               && (isa64 != amd64 || (rex & REX_W))))
14896         disp = get32s ();
14897       else
14898         {
14899           disp = get16 ();
14900           if ((disp & 0x8000) != 0)
14901             disp -= 0x10000;
14902           /* In 16bit mode, address is wrapped around at 64k within
14903              the same segment.  Otherwise, a data16 prefix on a jump
14904              instruction means that the pc is masked to 16 bits after
14905              the displacement is added!  */
14906           mask = 0xffff;
14907           if ((prefixes & PREFIX_DATA) == 0)
14908             segment = ((start_pc + (codep - start_codep))
14909                        & ~((bfd_vma) 0xffff));
14910         }
14911       if (address_mode != mode_64bit
14912           || (isa64 == amd64 && !(rex & REX_W)))
14913         used_prefixes |= (prefixes & PREFIX_DATA);
14914       break;
14915     default:
14916       oappend (INTERNAL_DISASSEMBLER_ERROR);
14917       return;
14918     }
14919   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14920   set_op (disp, 0);
14921   print_operand_value (scratchbuf, 1, disp);
14922   oappend (scratchbuf);
14923 }
14924
14925 static void
14926 OP_SEG (int bytemode, int sizeflag)
14927 {
14928   if (bytemode == w_mode)
14929     oappend (names_seg[modrm.reg]);
14930   else
14931     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14932 }
14933
14934 static void
14935 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14936 {
14937   int seg, offset;
14938
14939   if (sizeflag & DFLAG)
14940     {
14941       offset = get32 ();
14942       seg = get16 ();
14943     }
14944   else
14945     {
14946       offset = get16 ();
14947       seg = get16 ();
14948     }
14949   used_prefixes |= (prefixes & PREFIX_DATA);
14950   if (intel_syntax)
14951     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14952   else
14953     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14954   oappend (scratchbuf);
14955 }
14956
14957 static void
14958 OP_OFF (int bytemode, int sizeflag)
14959 {
14960   bfd_vma off;
14961
14962   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14963     intel_operand_size (bytemode, sizeflag);
14964   append_seg ();
14965
14966   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14967     off = get32 ();
14968   else
14969     off = get16 ();
14970
14971   if (intel_syntax)
14972     {
14973       if (!active_seg_prefix)
14974         {
14975           oappend (names_seg[ds_reg - es_reg]);
14976           oappend (":");
14977         }
14978     }
14979   print_operand_value (scratchbuf, 1, off);
14980   oappend (scratchbuf);
14981 }
14982
14983 static void
14984 OP_OFF64 (int bytemode, int sizeflag)
14985 {
14986   bfd_vma off;
14987
14988   if (address_mode != mode_64bit
14989       || (prefixes & PREFIX_ADDR))
14990     {
14991       OP_OFF (bytemode, sizeflag);
14992       return;
14993     }
14994
14995   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14996     intel_operand_size (bytemode, sizeflag);
14997   append_seg ();
14998
14999   off = get64 ();
15000
15001   if (intel_syntax)
15002     {
15003       if (!active_seg_prefix)
15004         {
15005           oappend (names_seg[ds_reg - es_reg]);
15006           oappend (":");
15007         }
15008     }
15009   print_operand_value (scratchbuf, 1, off);
15010   oappend (scratchbuf);
15011 }
15012
15013 static void
15014 ptr_reg (int code, int sizeflag)
15015 {
15016   const char *s;
15017
15018   *obufp++ = open_char;
15019   used_prefixes |= (prefixes & PREFIX_ADDR);
15020   if (address_mode == mode_64bit)
15021     {
15022       if (!(sizeflag & AFLAG))
15023         s = names32[code - eAX_reg];
15024       else
15025         s = names64[code - eAX_reg];
15026     }
15027   else if (sizeflag & AFLAG)
15028     s = names32[code - eAX_reg];
15029   else
15030     s = names16[code - eAX_reg];
15031   oappend (s);
15032   *obufp++ = close_char;
15033   *obufp = 0;
15034 }
15035
15036 static void
15037 OP_ESreg (int code, int sizeflag)
15038 {
15039   if (intel_syntax)
15040     {
15041       switch (codep[-1])
15042         {
15043         case 0x6d:      /* insw/insl */
15044           intel_operand_size (z_mode, sizeflag);
15045           break;
15046         case 0xa5:      /* movsw/movsl/movsq */
15047         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15048         case 0xab:      /* stosw/stosl */
15049         case 0xaf:      /* scasw/scasl */
15050           intel_operand_size (v_mode, sizeflag);
15051           break;
15052         default:
15053           intel_operand_size (b_mode, sizeflag);
15054         }
15055     }
15056   oappend_maybe_intel ("%es:");
15057   ptr_reg (code, sizeflag);
15058 }
15059
15060 static void
15061 OP_DSreg (int code, int sizeflag)
15062 {
15063   if (intel_syntax)
15064     {
15065       switch (codep[-1])
15066         {
15067         case 0x6f:      /* outsw/outsl */
15068           intel_operand_size (z_mode, sizeflag);
15069           break;
15070         case 0xa5:      /* movsw/movsl/movsq */
15071         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15072         case 0xad:      /* lodsw/lodsl/lodsq */
15073           intel_operand_size (v_mode, sizeflag);
15074           break;
15075         default:
15076           intel_operand_size (b_mode, sizeflag);
15077         }
15078     }
15079   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15080      default segment register DS is printed.  */
15081   if (!active_seg_prefix)
15082     active_seg_prefix = PREFIX_DS;
15083   append_seg ();
15084   ptr_reg (code, sizeflag);
15085 }
15086
15087 static void
15088 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15089 {
15090   int add;
15091   if (rex & REX_R)
15092     {
15093       USED_REX (REX_R);
15094       add = 8;
15095     }
15096   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15097     {
15098       all_prefixes[last_lock_prefix] = 0;
15099       used_prefixes |= PREFIX_LOCK;
15100       add = 8;
15101     }
15102   else
15103     add = 0;
15104   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15105   oappend_maybe_intel (scratchbuf);
15106 }
15107
15108 static void
15109 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15110 {
15111   int add;
15112   USED_REX (REX_R);
15113   if (rex & REX_R)
15114     add = 8;
15115   else
15116     add = 0;
15117   if (intel_syntax)
15118     sprintf (scratchbuf, "db%d", modrm.reg + add);
15119   else
15120     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15121   oappend (scratchbuf);
15122 }
15123
15124 static void
15125 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15126 {
15127   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15128   oappend_maybe_intel (scratchbuf);
15129 }
15130
15131 static void
15132 OP_R (int bytemode, int sizeflag)
15133 {
15134   /* Skip mod/rm byte.  */
15135   MODRM_CHECK;
15136   codep++;
15137   OP_E_register (bytemode, sizeflag);
15138 }
15139
15140 static void
15141 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15142 {
15143   int reg = modrm.reg;
15144   const char **names;
15145
15146   used_prefixes |= (prefixes & PREFIX_DATA);
15147   if (prefixes & PREFIX_DATA)
15148     {
15149       names = names_xmm;
15150       USED_REX (REX_R);
15151       if (rex & REX_R)
15152         reg += 8;
15153     }
15154   else
15155     names = names_mm;
15156   oappend (names[reg]);
15157 }
15158
15159 static void
15160 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15161 {
15162   int reg = modrm.reg;
15163   const char **names;
15164
15165   USED_REX (REX_R);
15166   if (rex & REX_R)
15167     reg += 8;
15168   if (vex.evex)
15169     {
15170       if (!vex.r)
15171         reg += 16;
15172     }
15173
15174   if (need_vex
15175       && bytemode != xmm_mode
15176       && bytemode != xmmq_mode
15177       && bytemode != evex_half_bcst_xmmq_mode
15178       && bytemode != ymm_mode
15179       && bytemode != scalar_mode)
15180     {
15181       switch (vex.length)
15182         {
15183         case 128:
15184           names = names_xmm;
15185           break;
15186         case 256:
15187           if (vex.w
15188               || (bytemode != vex_vsib_q_w_dq_mode
15189                   && bytemode != vex_vsib_q_w_d_mode))
15190             names = names_ymm;
15191           else
15192             names = names_xmm;
15193           break;
15194         case 512:
15195           names = names_zmm;
15196           break;
15197         default:
15198           abort ();
15199         }
15200     }
15201   else if (bytemode == xmmq_mode
15202            || bytemode == evex_half_bcst_xmmq_mode)
15203     {
15204       switch (vex.length)
15205         {
15206         case 128:
15207         case 256:
15208           names = names_xmm;
15209           break;
15210         case 512:
15211           names = names_ymm;
15212           break;
15213         default:
15214           abort ();
15215         }
15216     }
15217   else if (bytemode == ymm_mode)
15218     names = names_ymm;
15219   else
15220     names = names_xmm;
15221   oappend (names[reg]);
15222 }
15223
15224 static void
15225 OP_EM (int bytemode, int sizeflag)
15226 {
15227   int reg;
15228   const char **names;
15229
15230   if (modrm.mod != 3)
15231     {
15232       if (intel_syntax
15233           && (bytemode == v_mode || bytemode == v_swap_mode))
15234         {
15235           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15236           used_prefixes |= (prefixes & PREFIX_DATA);
15237         }
15238       OP_E (bytemode, sizeflag);
15239       return;
15240     }
15241
15242   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15243     swap_operand ();
15244
15245   /* Skip mod/rm byte.  */
15246   MODRM_CHECK;
15247   codep++;
15248   used_prefixes |= (prefixes & PREFIX_DATA);
15249   reg = modrm.rm;
15250   if (prefixes & PREFIX_DATA)
15251     {
15252       names = names_xmm;
15253       USED_REX (REX_B);
15254       if (rex & REX_B)
15255         reg += 8;
15256     }
15257   else
15258     names = names_mm;
15259   oappend (names[reg]);
15260 }
15261
15262 /* cvt* are the only instructions in sse2 which have
15263    both SSE and MMX operands and also have 0x66 prefix
15264    in their opcode. 0x66 was originally used to differentiate
15265    between SSE and MMX instruction(operands). So we have to handle the
15266    cvt* separately using OP_EMC and OP_MXC */
15267 static void
15268 OP_EMC (int bytemode, int sizeflag)
15269 {
15270   if (modrm.mod != 3)
15271     {
15272       if (intel_syntax && bytemode == v_mode)
15273         {
15274           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15275           used_prefixes |= (prefixes & PREFIX_DATA);
15276         }
15277       OP_E (bytemode, sizeflag);
15278       return;
15279     }
15280
15281   /* Skip mod/rm byte.  */
15282   MODRM_CHECK;
15283   codep++;
15284   used_prefixes |= (prefixes & PREFIX_DATA);
15285   oappend (names_mm[modrm.rm]);
15286 }
15287
15288 static void
15289 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15290 {
15291   used_prefixes |= (prefixes & PREFIX_DATA);
15292   oappend (names_mm[modrm.reg]);
15293 }
15294
15295 static void
15296 OP_EX (int bytemode, int sizeflag)
15297 {
15298   int reg;
15299   const char **names;
15300
15301   /* Skip mod/rm byte.  */
15302   MODRM_CHECK;
15303   codep++;
15304
15305   if (modrm.mod != 3)
15306     {
15307       OP_E_memory (bytemode, sizeflag);
15308       return;
15309     }
15310
15311   reg = modrm.rm;
15312   USED_REX (REX_B);
15313   if (rex & REX_B)
15314     reg += 8;
15315   if (vex.evex)
15316     {
15317       USED_REX (REX_X);
15318       if ((rex & REX_X))
15319         reg += 16;
15320     }
15321
15322   if ((sizeflag & SUFFIX_ALWAYS)
15323       && (bytemode == x_swap_mode
15324           || bytemode == d_swap_mode
15325           || bytemode == d_scalar_swap_mode
15326           || bytemode == q_swap_mode
15327           || bytemode == q_scalar_swap_mode))
15328     swap_operand ();
15329
15330   if (need_vex
15331       && bytemode != xmm_mode
15332       && bytemode != xmmdw_mode
15333       && bytemode != xmmqd_mode
15334       && bytemode != xmm_mb_mode
15335       && bytemode != xmm_mw_mode
15336       && bytemode != xmm_md_mode
15337       && bytemode != xmm_mq_mode
15338       && bytemode != xmm_mdq_mode
15339       && bytemode != xmmq_mode
15340       && bytemode != evex_half_bcst_xmmq_mode
15341       && bytemode != ymm_mode
15342       && bytemode != d_scalar_mode
15343       && bytemode != d_scalar_swap_mode
15344       && bytemode != q_scalar_mode
15345       && bytemode != q_scalar_swap_mode
15346       && bytemode != vex_scalar_w_dq_mode)
15347     {
15348       switch (vex.length)
15349         {
15350         case 128:
15351           names = names_xmm;
15352           break;
15353         case 256:
15354           names = names_ymm;
15355           break;
15356         case 512:
15357           names = names_zmm;
15358           break;
15359         default:
15360           abort ();
15361         }
15362     }
15363   else if (bytemode == xmmq_mode
15364            || bytemode == evex_half_bcst_xmmq_mode)
15365     {
15366       switch (vex.length)
15367         {
15368         case 128:
15369         case 256:
15370           names = names_xmm;
15371           break;
15372         case 512:
15373           names = names_ymm;
15374           break;
15375         default:
15376           abort ();
15377         }
15378     }
15379   else if (bytemode == ymm_mode)
15380     names = names_ymm;
15381   else
15382     names = names_xmm;
15383   oappend (names[reg]);
15384 }
15385
15386 static void
15387 OP_MS (int bytemode, int sizeflag)
15388 {
15389   if (modrm.mod == 3)
15390     OP_EM (bytemode, sizeflag);
15391   else
15392     BadOp ();
15393 }
15394
15395 static void
15396 OP_XS (int bytemode, int sizeflag)
15397 {
15398   if (modrm.mod == 3)
15399     OP_EX (bytemode, sizeflag);
15400   else
15401     BadOp ();
15402 }
15403
15404 static void
15405 OP_M (int bytemode, int sizeflag)
15406 {
15407   if (modrm.mod == 3)
15408     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15409     BadOp ();
15410   else
15411     OP_E (bytemode, sizeflag);
15412 }
15413
15414 static void
15415 OP_0f07 (int bytemode, int sizeflag)
15416 {
15417   if (modrm.mod != 3 || modrm.rm != 0)
15418     BadOp ();
15419   else
15420     OP_E (bytemode, sizeflag);
15421 }
15422
15423 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15424    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15425
15426 static void
15427 NOP_Fixup1 (int bytemode, int sizeflag)
15428 {
15429   if ((prefixes & PREFIX_DATA) != 0
15430       || (rex != 0
15431           && rex != 0x48
15432           && address_mode == mode_64bit))
15433     OP_REG (bytemode, sizeflag);
15434   else
15435     strcpy (obuf, "nop");
15436 }
15437
15438 static void
15439 NOP_Fixup2 (int bytemode, int sizeflag)
15440 {
15441   if ((prefixes & PREFIX_DATA) != 0
15442       || (rex != 0
15443           && rex != 0x48
15444           && address_mode == mode_64bit))
15445     OP_IMREG (bytemode, sizeflag);
15446 }
15447
15448 static const char *const Suffix3DNow[] = {
15449 /* 00 */        NULL,           NULL,           NULL,           NULL,
15450 /* 04 */        NULL,           NULL,           NULL,           NULL,
15451 /* 08 */        NULL,           NULL,           NULL,           NULL,
15452 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15453 /* 10 */        NULL,           NULL,           NULL,           NULL,
15454 /* 14 */        NULL,           NULL,           NULL,           NULL,
15455 /* 18 */        NULL,           NULL,           NULL,           NULL,
15456 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15457 /* 20 */        NULL,           NULL,           NULL,           NULL,
15458 /* 24 */        NULL,           NULL,           NULL,           NULL,
15459 /* 28 */        NULL,           NULL,           NULL,           NULL,
15460 /* 2C */        NULL,           NULL,           NULL,           NULL,
15461 /* 30 */        NULL,           NULL,           NULL,           NULL,
15462 /* 34 */        NULL,           NULL,           NULL,           NULL,
15463 /* 38 */        NULL,           NULL,           NULL,           NULL,
15464 /* 3C */        NULL,           NULL,           NULL,           NULL,
15465 /* 40 */        NULL,           NULL,           NULL,           NULL,
15466 /* 44 */        NULL,           NULL,           NULL,           NULL,
15467 /* 48 */        NULL,           NULL,           NULL,           NULL,
15468 /* 4C */        NULL,           NULL,           NULL,           NULL,
15469 /* 50 */        NULL,           NULL,           NULL,           NULL,
15470 /* 54 */        NULL,           NULL,           NULL,           NULL,
15471 /* 58 */        NULL,           NULL,           NULL,           NULL,
15472 /* 5C */        NULL,           NULL,           NULL,           NULL,
15473 /* 60 */        NULL,           NULL,           NULL,           NULL,
15474 /* 64 */        NULL,           NULL,           NULL,           NULL,
15475 /* 68 */        NULL,           NULL,           NULL,           NULL,
15476 /* 6C */        NULL,           NULL,           NULL,           NULL,
15477 /* 70 */        NULL,           NULL,           NULL,           NULL,
15478 /* 74 */        NULL,           NULL,           NULL,           NULL,
15479 /* 78 */        NULL,           NULL,           NULL,           NULL,
15480 /* 7C */        NULL,           NULL,           NULL,           NULL,
15481 /* 80 */        NULL,           NULL,           NULL,           NULL,
15482 /* 84 */        NULL,           NULL,           NULL,           NULL,
15483 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15484 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15485 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15486 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15487 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15488 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15489 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15490 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15491 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15492 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15493 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15494 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15495 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15496 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15497 /* C0 */        NULL,           NULL,           NULL,           NULL,
15498 /* C4 */        NULL,           NULL,           NULL,           NULL,
15499 /* C8 */        NULL,           NULL,           NULL,           NULL,
15500 /* CC */        NULL,           NULL,           NULL,           NULL,
15501 /* D0 */        NULL,           NULL,           NULL,           NULL,
15502 /* D4 */        NULL,           NULL,           NULL,           NULL,
15503 /* D8 */        NULL,           NULL,           NULL,           NULL,
15504 /* DC */        NULL,           NULL,           NULL,           NULL,
15505 /* E0 */        NULL,           NULL,           NULL,           NULL,
15506 /* E4 */        NULL,           NULL,           NULL,           NULL,
15507 /* E8 */        NULL,           NULL,           NULL,           NULL,
15508 /* EC */        NULL,           NULL,           NULL,           NULL,
15509 /* F0 */        NULL,           NULL,           NULL,           NULL,
15510 /* F4 */        NULL,           NULL,           NULL,           NULL,
15511 /* F8 */        NULL,           NULL,           NULL,           NULL,
15512 /* FC */        NULL,           NULL,           NULL,           NULL,
15513 };
15514
15515 static void
15516 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15517 {
15518   const char *mnemonic;
15519
15520   FETCH_DATA (the_info, codep + 1);
15521   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15522      place where an 8-bit immediate would normally go.  ie. the last
15523      byte of the instruction.  */
15524   obufp = mnemonicendp;
15525   mnemonic = Suffix3DNow[*codep++ & 0xff];
15526   if (mnemonic)
15527     oappend (mnemonic);
15528   else
15529     {
15530       /* Since a variable sized modrm/sib chunk is between the start
15531          of the opcode (0x0f0f) and the opcode suffix, we need to do
15532          all the modrm processing first, and don't know until now that
15533          we have a bad opcode.  This necessitates some cleaning up.  */
15534       op_out[0][0] = '\0';
15535       op_out[1][0] = '\0';
15536       BadOp ();
15537     }
15538   mnemonicendp = obufp;
15539 }
15540
15541 static struct op simd_cmp_op[] =
15542 {
15543   { STRING_COMMA_LEN ("eq") },
15544   { STRING_COMMA_LEN ("lt") },
15545   { STRING_COMMA_LEN ("le") },
15546   { STRING_COMMA_LEN ("unord") },
15547   { STRING_COMMA_LEN ("neq") },
15548   { STRING_COMMA_LEN ("nlt") },
15549   { STRING_COMMA_LEN ("nle") },
15550   { STRING_COMMA_LEN ("ord") }
15551 };
15552
15553 static void
15554 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15555 {
15556   unsigned int cmp_type;
15557
15558   FETCH_DATA (the_info, codep + 1);
15559   cmp_type = *codep++ & 0xff;
15560   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15561     {
15562       char suffix [3];
15563       char *p = mnemonicendp - 2;
15564       suffix[0] = p[0];
15565       suffix[1] = p[1];
15566       suffix[2] = '\0';
15567       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15568       mnemonicendp += simd_cmp_op[cmp_type].len;
15569     }
15570   else
15571     {
15572       /* We have a reserved extension byte.  Output it directly.  */
15573       scratchbuf[0] = '$';
15574       print_operand_value (scratchbuf + 1, 1, cmp_type);
15575       oappend_maybe_intel (scratchbuf);
15576       scratchbuf[0] = '\0';
15577     }
15578 }
15579
15580 static void
15581 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15582           int sizeflag ATTRIBUTE_UNUSED)
15583 {
15584   /* mwaitx %eax,%ecx,%ebx */
15585   if (!intel_syntax)
15586     {
15587       const char **names = (address_mode == mode_64bit
15588                             ? names64 : names32);
15589       strcpy (op_out[0], names[0]);
15590       strcpy (op_out[1], names[1]);
15591       strcpy (op_out[2], names[3]);
15592       two_source_ops = 1;
15593     }
15594   /* Skip mod/rm byte.  */
15595   MODRM_CHECK;
15596   codep++;
15597 }
15598
15599 static void
15600 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15601           int sizeflag ATTRIBUTE_UNUSED)
15602 {
15603   /* mwait %eax,%ecx  */
15604   if (!intel_syntax)
15605     {
15606       const char **names = (address_mode == mode_64bit
15607                             ? names64 : names32);
15608       strcpy (op_out[0], names[0]);
15609       strcpy (op_out[1], names[1]);
15610       two_source_ops = 1;
15611     }
15612   /* Skip mod/rm byte.  */
15613   MODRM_CHECK;
15614   codep++;
15615 }
15616
15617 static void
15618 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15619             int sizeflag ATTRIBUTE_UNUSED)
15620 {
15621   /* monitor %eax,%ecx,%edx"  */
15622   if (!intel_syntax)
15623     {
15624       const char **op1_names;
15625       const char **names = (address_mode == mode_64bit
15626                             ? names64 : names32);
15627
15628       if (!(prefixes & PREFIX_ADDR))
15629         op1_names = (address_mode == mode_16bit
15630                      ? names16 : names);
15631       else
15632         {
15633           /* Remove "addr16/addr32".  */
15634           all_prefixes[last_addr_prefix] = 0;
15635           op1_names = (address_mode != mode_32bit
15636                        ? names32 : names16);
15637           used_prefixes |= PREFIX_ADDR;
15638         }
15639       strcpy (op_out[0], op1_names[0]);
15640       strcpy (op_out[1], names[1]);
15641       strcpy (op_out[2], names[2]);
15642       two_source_ops = 1;
15643     }
15644   /* Skip mod/rm byte.  */
15645   MODRM_CHECK;
15646   codep++;
15647 }
15648
15649 static void
15650 BadOp (void)
15651 {
15652   /* Throw away prefixes and 1st. opcode byte.  */
15653   codep = insn_codep + 1;
15654   oappend ("(bad)");
15655 }
15656
15657 static void
15658 REP_Fixup (int bytemode, int sizeflag)
15659 {
15660   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15661      lods and stos.  */
15662   if (prefixes & PREFIX_REPZ)
15663     all_prefixes[last_repz_prefix] = REP_PREFIX;
15664
15665   switch (bytemode)
15666     {
15667     case al_reg:
15668     case eAX_reg:
15669     case indir_dx_reg:
15670       OP_IMREG (bytemode, sizeflag);
15671       break;
15672     case eDI_reg:
15673       OP_ESreg (bytemode, sizeflag);
15674       break;
15675     case eSI_reg:
15676       OP_DSreg (bytemode, sizeflag);
15677       break;
15678     default:
15679       abort ();
15680       break;
15681     }
15682 }
15683
15684 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15685    "bnd".  */
15686
15687 static void
15688 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15689 {
15690   if (prefixes & PREFIX_REPNZ)
15691     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15692 }
15693
15694 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15695    "notrack".  */
15696
15697 static void
15698 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15699                int sizeflag ATTRIBUTE_UNUSED)
15700 {
15701   if (active_seg_prefix == PREFIX_DS
15702       && (address_mode != mode_64bit || last_data_prefix < 0))
15703     {
15704       /* NOTRACK prefix is only valid on indirect branch instructions.
15705          NB: DATA prefix is unsupported for Intel64.  */
15706       active_seg_prefix = 0;
15707       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15708     }
15709 }
15710
15711 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15712    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15713  */
15714
15715 static void
15716 HLE_Fixup1 (int bytemode, int sizeflag)
15717 {
15718   if (modrm.mod != 3
15719       && (prefixes & PREFIX_LOCK) != 0)
15720     {
15721       if (prefixes & PREFIX_REPZ)
15722         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15723       if (prefixes & PREFIX_REPNZ)
15724         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15725     }
15726
15727   OP_E (bytemode, sizeflag);
15728 }
15729
15730 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15731    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15732  */
15733
15734 static void
15735 HLE_Fixup2 (int bytemode, int sizeflag)
15736 {
15737   if (modrm.mod != 3)
15738     {
15739       if (prefixes & PREFIX_REPZ)
15740         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15741       if (prefixes & PREFIX_REPNZ)
15742         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15743     }
15744
15745   OP_E (bytemode, sizeflag);
15746 }
15747
15748 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15749    "xrelease" for memory operand.  No check for LOCK prefix.   */
15750
15751 static void
15752 HLE_Fixup3 (int bytemode, int sizeflag)
15753 {
15754   if (modrm.mod != 3
15755       && last_repz_prefix > last_repnz_prefix
15756       && (prefixes & PREFIX_REPZ) != 0)
15757     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15758
15759   OP_E (bytemode, sizeflag);
15760 }
15761
15762 static void
15763 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15764 {
15765   USED_REX (REX_W);
15766   if (rex & REX_W)
15767     {
15768       /* Change cmpxchg8b to cmpxchg16b.  */
15769       char *p = mnemonicendp - 2;
15770       mnemonicendp = stpcpy (p, "16b");
15771       bytemode = o_mode;
15772     }
15773   else if ((prefixes & PREFIX_LOCK) != 0)
15774     {
15775       if (prefixes & PREFIX_REPZ)
15776         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15777       if (prefixes & PREFIX_REPNZ)
15778         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15779     }
15780
15781   OP_M (bytemode, sizeflag);
15782 }
15783
15784 static void
15785 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15786 {
15787   const char **names;
15788
15789   if (need_vex)
15790     {
15791       switch (vex.length)
15792         {
15793         case 128:
15794           names = names_xmm;
15795           break;
15796         case 256:
15797           names = names_ymm;
15798           break;
15799         default:
15800           abort ();
15801         }
15802     }
15803   else
15804     names = names_xmm;
15805   oappend (names[reg]);
15806 }
15807
15808 static void
15809 CRC32_Fixup (int bytemode, int sizeflag)
15810 {
15811   /* Add proper suffix to "crc32".  */
15812   char *p = mnemonicendp;
15813
15814   switch (bytemode)
15815     {
15816     case b_mode:
15817       if (intel_syntax)
15818         goto skip;
15819
15820       *p++ = 'b';
15821       break;
15822     case v_mode:
15823       if (intel_syntax)
15824         goto skip;
15825
15826       USED_REX (REX_W);
15827       if (rex & REX_W)
15828         *p++ = 'q';
15829       else
15830         {
15831           if (sizeflag & DFLAG)
15832             *p++ = 'l';
15833           else
15834             *p++ = 'w';
15835           used_prefixes |= (prefixes & PREFIX_DATA);
15836         }
15837       break;
15838     default:
15839       oappend (INTERNAL_DISASSEMBLER_ERROR);
15840       break;
15841     }
15842   mnemonicendp = p;
15843   *p = '\0';
15844
15845 skip:
15846   if (modrm.mod == 3)
15847     {
15848       int add;
15849
15850       /* Skip mod/rm byte.  */
15851       MODRM_CHECK;
15852       codep++;
15853
15854       USED_REX (REX_B);
15855       add = (rex & REX_B) ? 8 : 0;
15856       if (bytemode == b_mode)
15857         {
15858           USED_REX (0);
15859           if (rex)
15860             oappend (names8rex[modrm.rm + add]);
15861           else
15862             oappend (names8[modrm.rm + add]);
15863         }
15864       else
15865         {
15866           USED_REX (REX_W);
15867           if (rex & REX_W)
15868             oappend (names64[modrm.rm + add]);
15869           else if ((prefixes & PREFIX_DATA))
15870             oappend (names16[modrm.rm + add]);
15871           else
15872             oappend (names32[modrm.rm + add]);
15873         }
15874     }
15875   else
15876     OP_E (bytemode, sizeflag);
15877 }
15878
15879 static void
15880 FXSAVE_Fixup (int bytemode, int sizeflag)
15881 {
15882   /* Add proper suffix to "fxsave" and "fxrstor".  */
15883   USED_REX (REX_W);
15884   if (rex & REX_W)
15885     {
15886       char *p = mnemonicendp;
15887       *p++ = '6';
15888       *p++ = '4';
15889       *p = '\0';
15890       mnemonicendp = p;
15891     }
15892   OP_M (bytemode, sizeflag);
15893 }
15894
15895 static void
15896 PCMPESTR_Fixup (int bytemode, int sizeflag)
15897 {
15898   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15899   if (!intel_syntax)
15900     {
15901       char *p = mnemonicendp;
15902
15903       USED_REX (REX_W);
15904       if (rex & REX_W)
15905         *p++ = 'q';
15906       else if (sizeflag & SUFFIX_ALWAYS)
15907         *p++ = 'l';
15908
15909       *p = '\0';
15910       mnemonicendp = p;
15911     }
15912
15913   OP_EX (bytemode, sizeflag);
15914 }
15915
15916 /* Display the destination register operand for instructions with
15917    VEX. */
15918
15919 static void
15920 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15921 {
15922   int reg;
15923   const char **names;
15924
15925   if (!need_vex)
15926     abort ();
15927
15928   if (!need_vex_reg)
15929     return;
15930
15931   reg = vex.register_specifier;
15932   vex.register_specifier = 0;
15933   if (address_mode != mode_64bit)
15934     reg &= 7;
15935   else if (vex.evex && !vex.v)
15936     reg += 16;
15937
15938   if (bytemode == vex_scalar_mode)
15939     {
15940       oappend (names_xmm[reg]);
15941       return;
15942     }
15943
15944   switch (vex.length)
15945     {
15946     case 128:
15947       switch (bytemode)
15948         {
15949         case vex_mode:
15950         case vex128_mode:
15951         case vex_vsib_q_w_dq_mode:
15952         case vex_vsib_q_w_d_mode:
15953           names = names_xmm;
15954           break;
15955         case dq_mode:
15956           if (rex & REX_W)
15957             names = names64;
15958           else
15959             names = names32;
15960           break;
15961         case mask_bd_mode:
15962         case mask_mode:
15963           if (reg > 0x7)
15964             {
15965               oappend ("(bad)");
15966               return;
15967             }
15968           names = names_mask;
15969           break;
15970         default:
15971           abort ();
15972           return;
15973         }
15974       break;
15975     case 256:
15976       switch (bytemode)
15977         {
15978         case vex_mode:
15979         case vex256_mode:
15980           names = names_ymm;
15981           break;
15982         case vex_vsib_q_w_dq_mode:
15983         case vex_vsib_q_w_d_mode:
15984           names = vex.w ? names_ymm : names_xmm;
15985           break;
15986         case mask_bd_mode:
15987         case mask_mode:
15988           if (reg > 0x7)
15989             {
15990               oappend ("(bad)");
15991               return;
15992             }
15993           names = names_mask;
15994           break;
15995         default:
15996           /* See PR binutils/20893 for a reproducer.  */
15997           oappend ("(bad)");
15998           return;
15999         }
16000       break;
16001     case 512:
16002       names = names_zmm;
16003       break;
16004     default:
16005       abort ();
16006       break;
16007     }
16008   oappend (names[reg]);
16009 }
16010
16011 /* Get the VEX immediate byte without moving codep.  */
16012
16013 static unsigned char
16014 get_vex_imm8 (int sizeflag, int opnum)
16015 {
16016   int bytes_before_imm = 0;
16017
16018   if (modrm.mod != 3)
16019     {
16020       /* There are SIB/displacement bytes.  */
16021       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16022         {
16023           /* 32/64 bit address mode */
16024           int base = modrm.rm;
16025
16026           /* Check SIB byte.  */
16027           if (base == 4)
16028             {
16029               FETCH_DATA (the_info, codep + 1);
16030               base = *codep & 7;
16031               /* When decoding the third source, don't increase
16032                  bytes_before_imm as this has already been incremented
16033                  by one in OP_E_memory while decoding the second
16034                  source operand.  */
16035               if (opnum == 0)
16036                 bytes_before_imm++;
16037             }
16038
16039           /* Don't increase bytes_before_imm when decoding the third source,
16040              it has already been incremented by OP_E_memory while decoding
16041              the second source operand.  */
16042           if (opnum == 0)
16043             {
16044               switch (modrm.mod)
16045                 {
16046                   case 0:
16047                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16048                        SIB == 5, there is a 4 byte displacement.  */
16049                     if (base != 5)
16050                       /* No displacement. */
16051                       break;
16052                     /* Fall through.  */
16053                   case 2:
16054                     /* 4 byte displacement.  */
16055                     bytes_before_imm += 4;
16056                     break;
16057                   case 1:
16058                     /* 1 byte displacement.  */
16059                     bytes_before_imm++;
16060                     break;
16061                 }
16062             }
16063         }
16064       else
16065         {
16066           /* 16 bit address mode */
16067           /* Don't increase bytes_before_imm when decoding the third source,
16068              it has already been incremented by OP_E_memory while decoding
16069              the second source operand.  */
16070           if (opnum == 0)
16071             {
16072               switch (modrm.mod)
16073                 {
16074                 case 0:
16075                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16076                   if (modrm.rm != 6)
16077                     /* No displacement. */
16078                     break;
16079                   /* Fall through.  */
16080                 case 2:
16081                   /* 2 byte displacement.  */
16082                   bytes_before_imm += 2;
16083                   break;
16084                 case 1:
16085                   /* 1 byte displacement: when decoding the third source,
16086                      don't increase bytes_before_imm as this has already
16087                      been incremented by one in OP_E_memory while decoding
16088                      the second source operand.  */
16089                   if (opnum == 0)
16090                     bytes_before_imm++;
16091
16092                   break;
16093                 }
16094             }
16095         }
16096     }
16097
16098   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16099   return codep [bytes_before_imm];
16100 }
16101
16102 static void
16103 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16104 {
16105   const char **names;
16106
16107   if (reg == -1 && modrm.mod != 3)
16108     {
16109       OP_E_memory (bytemode, sizeflag);
16110       return;
16111     }
16112   else
16113     {
16114       if (reg == -1)
16115         {
16116           reg = modrm.rm;
16117           USED_REX (REX_B);
16118           if (rex & REX_B)
16119             reg += 8;
16120         }
16121       if (address_mode != mode_64bit)
16122         reg &= 7;
16123     }
16124
16125   switch (vex.length)
16126     {
16127     case 128:
16128       names = names_xmm;
16129       break;
16130     case 256:
16131       names = names_ymm;
16132       break;
16133     default:
16134       abort ();
16135     }
16136   oappend (names[reg]);
16137 }
16138
16139 static void
16140 OP_EX_VexImmW (int bytemode, int sizeflag)
16141 {
16142   int reg = -1;
16143   static unsigned char vex_imm8;
16144
16145   if (vex_w_done == 0)
16146     {
16147       vex_w_done = 1;
16148
16149       /* Skip mod/rm byte.  */
16150       MODRM_CHECK;
16151       codep++;
16152
16153       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16154
16155       if (vex.w)
16156           reg = vex_imm8 >> 4;
16157
16158       OP_EX_VexReg (bytemode, sizeflag, reg);
16159     }
16160   else if (vex_w_done == 1)
16161     {
16162       vex_w_done = 2;
16163
16164       if (!vex.w)
16165           reg = vex_imm8 >> 4;
16166
16167       OP_EX_VexReg (bytemode, sizeflag, reg);
16168     }
16169   else
16170     {
16171       /* Output the imm8 directly.  */
16172       scratchbuf[0] = '$';
16173       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16174       oappend_maybe_intel (scratchbuf);
16175       scratchbuf[0] = '\0';
16176       codep++;
16177     }
16178 }
16179
16180 static void
16181 OP_Vex_2src (int bytemode, int sizeflag)
16182 {
16183   if (modrm.mod == 3)
16184     {
16185       int reg = modrm.rm;
16186       USED_REX (REX_B);
16187       if (rex & REX_B)
16188         reg += 8;
16189       oappend (names_xmm[reg]);
16190     }
16191   else
16192     {
16193       if (intel_syntax
16194           && (bytemode == v_mode || bytemode == v_swap_mode))
16195         {
16196           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16197           used_prefixes |= (prefixes & PREFIX_DATA);
16198         }
16199       OP_E (bytemode, sizeflag);
16200     }
16201 }
16202
16203 static void
16204 OP_Vex_2src_1 (int bytemode, int sizeflag)
16205 {
16206   if (modrm.mod == 3)
16207     {
16208       /* Skip mod/rm byte.   */
16209       MODRM_CHECK;
16210       codep++;
16211     }
16212
16213   if (vex.w)
16214     {
16215       unsigned int reg = vex.register_specifier;
16216       vex.register_specifier = 0;
16217
16218       if (address_mode != mode_64bit)
16219         reg &= 7;
16220       oappend (names_xmm[reg]);
16221     }
16222   else
16223     OP_Vex_2src (bytemode, sizeflag);
16224 }
16225
16226 static void
16227 OP_Vex_2src_2 (int bytemode, int sizeflag)
16228 {
16229   if (vex.w)
16230     OP_Vex_2src (bytemode, sizeflag);
16231   else
16232     {
16233       unsigned int reg = vex.register_specifier;
16234       vex.register_specifier = 0;
16235
16236       if (address_mode != mode_64bit)
16237         reg &= 7;
16238       oappend (names_xmm[reg]);
16239     }
16240 }
16241
16242 static void
16243 OP_EX_VexW (int bytemode, int sizeflag)
16244 {
16245   int reg = -1;
16246
16247   if (!vex_w_done)
16248     {
16249       /* Skip mod/rm byte.  */
16250       MODRM_CHECK;
16251       codep++;
16252
16253       if (vex.w)
16254         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16255     }
16256   else
16257     {
16258       if (!vex.w)
16259         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16260     }
16261
16262   OP_EX_VexReg (bytemode, sizeflag, reg);
16263
16264   if (vex_w_done)
16265     codep++;
16266   vex_w_done = 1;
16267 }
16268
16269 static void
16270 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16271 {
16272   int reg;
16273   const char **names;
16274
16275   FETCH_DATA (the_info, codep + 1);
16276   reg = *codep++;
16277
16278   if (bytemode != x_mode)
16279     abort ();
16280
16281   reg >>= 4;
16282   if (address_mode != mode_64bit)
16283     reg &= 7;
16284
16285   switch (vex.length)
16286     {
16287     case 128:
16288       names = names_xmm;
16289       break;
16290     case 256:
16291       names = names_ymm;
16292       break;
16293     default:
16294       abort ();
16295     }
16296   oappend (names[reg]);
16297 }
16298
16299 static void
16300 OP_XMM_VexW (int bytemode, int sizeflag)
16301 {
16302   /* Turn off the REX.W bit since it is used for swapping operands
16303      now.  */
16304   rex &= ~REX_W;
16305   OP_XMM (bytemode, sizeflag);
16306 }
16307
16308 static void
16309 OP_EX_Vex (int bytemode, int sizeflag)
16310 {
16311   if (modrm.mod != 3)
16312     need_vex_reg = 0;
16313   OP_EX (bytemode, sizeflag);
16314 }
16315
16316 static void
16317 OP_XMM_Vex (int bytemode, int sizeflag)
16318 {
16319   if (modrm.mod != 3)
16320     need_vex_reg = 0;
16321   OP_XMM (bytemode, sizeflag);
16322 }
16323
16324 static struct op vex_cmp_op[] =
16325 {
16326   { STRING_COMMA_LEN ("eq") },
16327   { STRING_COMMA_LEN ("lt") },
16328   { STRING_COMMA_LEN ("le") },
16329   { STRING_COMMA_LEN ("unord") },
16330   { STRING_COMMA_LEN ("neq") },
16331   { STRING_COMMA_LEN ("nlt") },
16332   { STRING_COMMA_LEN ("nle") },
16333   { STRING_COMMA_LEN ("ord") },
16334   { STRING_COMMA_LEN ("eq_uq") },
16335   { STRING_COMMA_LEN ("nge") },
16336   { STRING_COMMA_LEN ("ngt") },
16337   { STRING_COMMA_LEN ("false") },
16338   { STRING_COMMA_LEN ("neq_oq") },
16339   { STRING_COMMA_LEN ("ge") },
16340   { STRING_COMMA_LEN ("gt") },
16341   { STRING_COMMA_LEN ("true") },
16342   { STRING_COMMA_LEN ("eq_os") },
16343   { STRING_COMMA_LEN ("lt_oq") },
16344   { STRING_COMMA_LEN ("le_oq") },
16345   { STRING_COMMA_LEN ("unord_s") },
16346   { STRING_COMMA_LEN ("neq_us") },
16347   { STRING_COMMA_LEN ("nlt_uq") },
16348   { STRING_COMMA_LEN ("nle_uq") },
16349   { STRING_COMMA_LEN ("ord_s") },
16350   { STRING_COMMA_LEN ("eq_us") },
16351   { STRING_COMMA_LEN ("nge_uq") },
16352   { STRING_COMMA_LEN ("ngt_uq") },
16353   { STRING_COMMA_LEN ("false_os") },
16354   { STRING_COMMA_LEN ("neq_os") },
16355   { STRING_COMMA_LEN ("ge_oq") },
16356   { STRING_COMMA_LEN ("gt_oq") },
16357   { STRING_COMMA_LEN ("true_us") },
16358 };
16359
16360 static void
16361 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16362 {
16363   unsigned int cmp_type;
16364
16365   FETCH_DATA (the_info, codep + 1);
16366   cmp_type = *codep++ & 0xff;
16367   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16368     {
16369       char suffix [3];
16370       char *p = mnemonicendp - 2;
16371       suffix[0] = p[0];
16372       suffix[1] = p[1];
16373       suffix[2] = '\0';
16374       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16375       mnemonicendp += vex_cmp_op[cmp_type].len;
16376     }
16377   else
16378     {
16379       /* We have a reserved extension byte.  Output it directly.  */
16380       scratchbuf[0] = '$';
16381       print_operand_value (scratchbuf + 1, 1, cmp_type);
16382       oappend_maybe_intel (scratchbuf);
16383       scratchbuf[0] = '\0';
16384     }
16385 }
16386
16387 static void
16388 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16389              int sizeflag ATTRIBUTE_UNUSED)
16390 {
16391   unsigned int cmp_type;
16392
16393   if (!vex.evex)
16394     abort ();
16395
16396   FETCH_DATA (the_info, codep + 1);
16397   cmp_type = *codep++ & 0xff;
16398   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16399      If it's the case, print suffix, otherwise - print the immediate.  */
16400   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16401       && cmp_type != 3
16402       && cmp_type != 7)
16403     {
16404       char suffix [3];
16405       char *p = mnemonicendp - 2;
16406
16407       /* vpcmp* can have both one- and two-lettered suffix.  */
16408       if (p[0] == 'p')
16409         {
16410           p++;
16411           suffix[0] = p[0];
16412           suffix[1] = '\0';
16413         }
16414       else
16415         {
16416           suffix[0] = p[0];
16417           suffix[1] = p[1];
16418           suffix[2] = '\0';
16419         }
16420
16421       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16422       mnemonicendp += simd_cmp_op[cmp_type].len;
16423     }
16424   else
16425     {
16426       /* We have a reserved extension byte.  Output it directly.  */
16427       scratchbuf[0] = '$';
16428       print_operand_value (scratchbuf + 1, 1, cmp_type);
16429       oappend_maybe_intel (scratchbuf);
16430       scratchbuf[0] = '\0';
16431     }
16432 }
16433
16434 static const struct op xop_cmp_op[] =
16435 {
16436   { STRING_COMMA_LEN ("lt") },
16437   { STRING_COMMA_LEN ("le") },
16438   { STRING_COMMA_LEN ("gt") },
16439   { STRING_COMMA_LEN ("ge") },
16440   { STRING_COMMA_LEN ("eq") },
16441   { STRING_COMMA_LEN ("neq") },
16442   { STRING_COMMA_LEN ("false") },
16443   { STRING_COMMA_LEN ("true") }
16444 };
16445
16446 static void
16447 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16448              int sizeflag ATTRIBUTE_UNUSED)
16449 {
16450   unsigned int cmp_type;
16451
16452   FETCH_DATA (the_info, codep + 1);
16453   cmp_type = *codep++ & 0xff;
16454   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16455     {
16456       char suffix[3];
16457       char *p = mnemonicendp - 2;
16458
16459       /* vpcom* can have both one- and two-lettered suffix.  */
16460       if (p[0] == 'm')
16461         {
16462           p++;
16463           suffix[0] = p[0];
16464           suffix[1] = '\0';
16465         }
16466       else
16467         {
16468           suffix[0] = p[0];
16469           suffix[1] = p[1];
16470           suffix[2] = '\0';
16471         }
16472
16473       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16474       mnemonicendp += xop_cmp_op[cmp_type].len;
16475     }
16476   else
16477     {
16478       /* We have a reserved extension byte.  Output it directly.  */
16479       scratchbuf[0] = '$';
16480       print_operand_value (scratchbuf + 1, 1, cmp_type);
16481       oappend_maybe_intel (scratchbuf);
16482       scratchbuf[0] = '\0';
16483     }
16484 }
16485
16486 static const struct op pclmul_op[] =
16487 {
16488   { STRING_COMMA_LEN ("lql") },
16489   { STRING_COMMA_LEN ("hql") },
16490   { STRING_COMMA_LEN ("lqh") },
16491   { STRING_COMMA_LEN ("hqh") }
16492 };
16493
16494 static void
16495 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16496               int sizeflag ATTRIBUTE_UNUSED)
16497 {
16498   unsigned int pclmul_type;
16499
16500   FETCH_DATA (the_info, codep + 1);
16501   pclmul_type = *codep++ & 0xff;
16502   switch (pclmul_type)
16503     {
16504     case 0x10:
16505       pclmul_type = 2;
16506       break;
16507     case 0x11:
16508       pclmul_type = 3;
16509       break;
16510     default:
16511       break;
16512     }
16513   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16514     {
16515       char suffix [4];
16516       char *p = mnemonicendp - 3;
16517       suffix[0] = p[0];
16518       suffix[1] = p[1];
16519       suffix[2] = p[2];
16520       suffix[3] = '\0';
16521       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16522       mnemonicendp += pclmul_op[pclmul_type].len;
16523     }
16524   else
16525     {
16526       /* We have a reserved extension byte.  Output it directly.  */
16527       scratchbuf[0] = '$';
16528       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16529       oappend_maybe_intel (scratchbuf);
16530       scratchbuf[0] = '\0';
16531     }
16532 }
16533
16534 static void
16535 MOVBE_Fixup (int bytemode, int sizeflag)
16536 {
16537   /* Add proper suffix to "movbe".  */
16538   char *p = mnemonicendp;
16539
16540   switch (bytemode)
16541     {
16542     case v_mode:
16543       if (intel_syntax)
16544         goto skip;
16545
16546       USED_REX (REX_W);
16547       if (sizeflag & SUFFIX_ALWAYS)
16548         {
16549           if (rex & REX_W)
16550             *p++ = 'q';
16551           else
16552             {
16553               if (sizeflag & DFLAG)
16554                 *p++ = 'l';
16555               else
16556                 *p++ = 'w';
16557               used_prefixes |= (prefixes & PREFIX_DATA);
16558             }
16559         }
16560       break;
16561     default:
16562       oappend (INTERNAL_DISASSEMBLER_ERROR);
16563       break;
16564     }
16565   mnemonicendp = p;
16566   *p = '\0';
16567
16568 skip:
16569   OP_M (bytemode, sizeflag);
16570 }
16571
16572 static void
16573 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16574 {
16575   int reg;
16576   const char **names;
16577
16578   /* Skip mod/rm byte.  */
16579   MODRM_CHECK;
16580   codep++;
16581
16582   if (rex & REX_W)
16583     names = names64;
16584   else
16585     names = names32;
16586
16587   reg = modrm.rm;
16588   USED_REX (REX_B);
16589   if (rex & REX_B)
16590     reg += 8;
16591
16592   oappend (names[reg]);
16593 }
16594
16595 static void
16596 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16597 {
16598   const char **names;
16599   unsigned int reg = vex.register_specifier;
16600   vex.register_specifier = 0;
16601
16602   if (rex & REX_W)
16603     names = names64;
16604   else
16605     names = names32;
16606
16607   if (address_mode != mode_64bit)
16608     reg &= 7;
16609   oappend (names[reg]);
16610 }
16611
16612 static void
16613 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16614 {
16615   if (!vex.evex
16616       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16617     abort ();
16618
16619   USED_REX (REX_R);
16620   if ((rex & REX_R) != 0 || !vex.r)
16621     {
16622       BadOp ();
16623       return;
16624     }
16625
16626   oappend (names_mask [modrm.reg]);
16627 }
16628
16629 static void
16630 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16631 {
16632   if (!vex.evex
16633       || (bytemode != evex_rounding_mode
16634           && bytemode != evex_rounding_64_mode
16635           && bytemode != evex_sae_mode))
16636     abort ();
16637   if (modrm.mod == 3 && vex.b)
16638     switch (bytemode)
16639       {
16640       case evex_rounding_64_mode:
16641         if (address_mode != mode_64bit)
16642           {
16643             oappend ("(bad)");
16644             break;
16645           }
16646         /* Fall through.  */
16647       case evex_rounding_mode:
16648         oappend (names_rounding[vex.ll]);
16649         break;
16650       case evex_sae_mode:
16651         oappend ("{sae}");
16652         break;
16653       default:
16654         break;
16655       }
16656 }