opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2019 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void OP_Mwaitx (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Edqa { OP_E, dqa_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iq { OP_I, q_mode }
 296 #define Iv64 { OP_I64, v_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdScalar { OP_EX, d_scalar_mode }
 388 #define EXdS { OP_EX, d_swap_mode }
 389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 405 #define EXxmmdw { OP_EX, xmmdw_mode }
 406 #define EXxmmqd { OP_EX, xmmqd_mode }
 407 #define EXymmq { OP_EX, ymmq_mode }
 408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 412 #define MS { OP_MS, v_mode }
 413 #define XS { OP_XS, v_mode }
 414 #define EMCq { OP_EMC, q_mode }
 415 #define MXC { OP_MXC, 0 }
 416 #define OPSUF { OP_3DNowSuffix, 0 }
 417 #define CMP { CMP_Fixup, 0 }
 418 #define XMM0 { XMM_Fixup, 0 }
 419 #define FXSAVE { FXSAVE_Fixup, 0 }
 420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 422
 423 #define Vex { OP_VEX, vex_mode }
 424 #define VexScalar { OP_VEX, vex_scalar_mode }
 425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 426 #define Vex128 { OP_VEX, vex128_mode }
 427 #define Vex256 { OP_VEX, vex256_mode }
 428 #define VexGdq { OP_VEX, dq_mode }
 429 #define EXdVex { OP_EX_Vex, d_mode }
 430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 432 #define EXqVex { OP_EX_Vex, q_mode }
 433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 435 #define EXVexW { OP_EX_VexW, x_mode }
 436 #define EXdVexW { OP_EX_VexW, d_mode }
 437 #define EXqVexW { OP_EX_VexW, q_mode }
 438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 439 #define XMVex { OP_XMM_Vex, 0 }
 440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 441 #define XMVexW { OP_XMM_VexW, 0 }
 442 #define XMVexI4 { OP_REG_VexI4, x_mode }
 443 #define PCLMUL { PCLMUL_Fixup, 0 }
 444 #define VCMP { VCMP_Fixup, 0 }
 445 #define VPCMP { VPCMP_Fixup, 0 }
 446 #define VPCOM { VPCOM_Fixup, 0 }
 447
 448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 451
 452 #define XMask { OP_Mask, mask_mode }
 453 #define MaskG { OP_G, mask_mode }
 454 #define MaskE { OP_E, mask_mode }
 455 #define MaskBDE { OP_E, mask_bd_mode }
 456 #define MaskR { OP_R, mask_mode }
 457 #define MaskVex { OP_VEX, mask_mode }
 458
 459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 463
 464 /* Used handle "rep" prefix for string instructions.  */
 465 #define Xbr { REP_Fixup, eSI_reg }
 466 #define Xvr { REP_Fixup, eSI_reg }
 467 #define Ybr { REP_Fixup, eDI_reg }
 468 #define Yvr { REP_Fixup, eDI_reg }
 469 #define Yzr { REP_Fixup, eDI_reg }
 470 #define indirDXr { REP_Fixup, indir_dx_reg }
 471 #define ALr { REP_Fixup, al_reg }
 472 #define eAXr { REP_Fixup, eAX_reg }
 473
 474 /* Used handle HLE prefix for lockable instructions.  */
 475 #define Ebh1 { HLE_Fixup1, b_mode }
 476 #define Evh1 { HLE_Fixup1, v_mode }
 477 #define Ebh2 { HLE_Fixup2, b_mode }
 478 #define Evh2 { HLE_Fixup2, v_mode }
 479 #define Ebh3 { HLE_Fixup3, b_mode }
 480 #define Evh3 { HLE_Fixup3, v_mode }
 481
 482 #define BND { BND_Fixup, 0 }
 483 #define NOTRACK { NOTRACK_Fixup, 0 }
 484
 485 #define cond_jump_flag { NULL, cond_jump_mode }
 486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 487
 488 /* bits in sizeflag */
 489 #define SUFFIX_ALWAYS 4
 490 #define AFLAG 2
 491 #define DFLAG 1
 492
 493 enum
 494 {
 495   /* byte operand */
 496   b_mode = 1,
 497   /* byte operand with operand swapped */
 498   b_swap_mode,
 499   /* byte operand, sign extend like 'T' suffix */
 500   b_T_mode,
 501   /* operand size depends on prefixes */
 502   v_mode,
 503   /* operand size depends on prefixes with operand swapped */
 504   v_swap_mode,
 505   /* operand size depends on address prefix */
 506   va_mode,
 507   /* word operand */
 508   w_mode,
 509   /* double word operand  */
 510   d_mode,
 511   /* double word operand with operand swapped */
 512   d_swap_mode,
 513   /* quad word operand */
 514   q_mode,
 515   /* quad word operand with operand swapped */
 516   q_swap_mode,
 517   /* ten-byte operand */
 518   t_mode,
 519   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 520      broadcast enabled.  */
 521   x_mode,
 522   /* Similar to x_mode, but with different EVEX mem shifts.  */
 523   evex_x_gscat_mode,
 524   /* Similar to x_mode, but with disabled broadcast.  */
 525   evex_x_nobcst_mode,
 526   /* Similar to x_mode, but with operands swapped and disabled broadcast
 527      in EVEX.  */
 528   x_swap_mode,
 529   /* 16-byte XMM operand */
 530   xmm_mode,
 531   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 532      memory operand (depending on vector length).  Broadcast isn't
 533      allowed.  */
 534   xmmq_mode,
 535   /* Same as xmmq_mode, but broadcast is allowed.  */
 536   evex_half_bcst_xmmq_mode,
 537   /* XMM register or byte memory operand */
 538   xmm_mb_mode,
 539   /* XMM register or word memory operand */
 540   xmm_mw_mode,
 541   /* XMM register or double word memory operand */
 542   xmm_md_mode,
 543   /* XMM register or quad word memory operand */
 544   xmm_mq_mode,
 545   /* XMM register or double/quad word memory operand, depending on
 546      VEX.W.  */
 547   xmm_mdq_mode,
 548   /* 16-byte XMM, word, double word or quad word operand.  */
 549   xmmdw_mode,
 550   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 551   xmmqd_mode,
 552   /* 32-byte YMM operand */
 553   ymm_mode,
 554   /* quad word, ymmword or zmmword memory operand.  */
 555   ymmq_mode,
 556   /* 32-byte YMM or 16-byte word operand */
 557   ymmxmm_mode,
 558   /* d_mode in 32bit, q_mode in 64bit mode.  */
 559   m_mode,
 560   /* pair of v_mode operands */
 561   a_mode,
 562   cond_jump_mode,
 563   loop_jcxz_mode,
 564   v_bnd_mode,
 565   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 566   v_bndmk_mode,
 567   /* operand size depends on REX prefixes.  */
 568   dq_mode,
 569   /* registers like dq_mode, memory like w_mode.  */
 570   dqw_mode,
 571   /* bounds operand */
 572   bnd_mode,
 573   /* bounds operand with operand swapped */
 574   bnd_swap_mode,
 575   /* 4- or 6-byte pointer operand */
 576   f_mode,
 577   const_1_mode,
 578   /* v_mode for indirect branch opcodes.  */
 579   indir_v_mode,
 580   /* v_mode for stack-related opcodes.  */
 581   stack_v_mode,
 582   /* non-quad operand size depends on prefixes */
 583   z_mode,
 584   /* 16-byte operand */
 585   o_mode,
 586   /* registers like dq_mode, memory like b_mode.  */
 587   dqb_mode,
 588   /* registers like d_mode, memory like b_mode.  */
 589   db_mode,
 590   /* registers like d_mode, memory like w_mode.  */
 591   dw_mode,
 592   /* registers like dq_mode, memory like d_mode.  */
 593   dqd_mode,
 594   /* operand size depends on the W bit as well as address mode.  */
 595   dqa_mode,
 596   /* normal vex mode */
 597   vex_mode,
 598   /* 128bit vex mode */
 599   vex128_mode,
 600   /* 256bit vex mode */
 601   vex256_mode,
 602   /* operand size depends on the VEX.W bit.  */
 603   vex_w_dq_mode,
 604
 605   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 606   vex_vsib_d_w_dq_mode,
 607   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 608   vex_vsib_d_w_d_mode,
 609   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 610   vex_vsib_q_w_dq_mode,
 611   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 612   vex_vsib_q_w_d_mode,
 613
 614   /* scalar, ignore vector length.  */
 615   scalar_mode,
 616   /* like b_mode, ignore vector length.  */
 617   b_scalar_mode,
 618   /* like w_mode, ignore vector length.  */
 619   w_scalar_mode,
 620   /* like d_mode, ignore vector length.  */
 621   d_scalar_mode,
 622   /* like d_swap_mode, ignore vector length.  */
 623   d_scalar_swap_mode,
 624   /* like q_mode, ignore vector length.  */
 625   q_scalar_mode,
 626   /* like q_swap_mode, ignore vector length.  */
 627   q_scalar_swap_mode,
 628   /* like vex_mode, ignore vector length.  */
 629   vex_scalar_mode,
 630   /* like vex_w_dq_mode, ignore vector length.  */
 631   vex_scalar_w_dq_mode,
 632
 633   /* Static rounding.  */
 634   evex_rounding_mode,
 635   /* Static rounding, 64-bit mode only.  */
 636   evex_rounding_64_mode,
 637   /* Supress all exceptions.  */
 638   evex_sae_mode,
 639
 640   /* Mask register operand.  */
 641   mask_mode,
 642   /* Mask register operand.  */
 643   mask_bd_mode,
 644
 645   es_reg,
 646   cs_reg,
 647   ss_reg,
 648   ds_reg,
 649   fs_reg,
 650   gs_reg,
 651
 652   eAX_reg,
 653   eCX_reg,
 654   eDX_reg,
 655   eBX_reg,
 656   eSP_reg,
 657   eBP_reg,
 658   eSI_reg,
 659   eDI_reg,
 660
 661   al_reg,
 662   cl_reg,
 663   dl_reg,
 664   bl_reg,
 665   ah_reg,
 666   ch_reg,
 667   dh_reg,
 668   bh_reg,
 669
 670   ax_reg,
 671   cx_reg,
 672   dx_reg,
 673   bx_reg,
 674   sp_reg,
 675   bp_reg,
 676   si_reg,
 677   di_reg,
 678
 679   rAX_reg,
 680   rCX_reg,
 681   rDX_reg,
 682   rBX_reg,
 683   rSP_reg,
 684   rBP_reg,
 685   rSI_reg,
 686   rDI_reg,
 687
 688   z_mode_ax_reg,
 689   indir_dx_reg
 690 };
 691
 692 enum
 693 {
 694   FLOATCODE = 1,
 695   USE_REG_TABLE,
 696   USE_MOD_TABLE,
 697   USE_RM_TABLE,
 698   USE_PREFIX_TABLE,
 699   USE_X86_64_TABLE,
 700   USE_3BYTE_TABLE,
 701   USE_XOP_8F_TABLE,
 702   USE_VEX_C4_TABLE,
 703   USE_VEX_C5_TABLE,
 704   USE_VEX_LEN_TABLE,
 705   USE_VEX_W_TABLE,
 706   USE_EVEX_TABLE,
 707   USE_EVEX_LEN_TABLE
 708 };
 709
 710 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 711
 712 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 713 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 714 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 715 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 716 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 717 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 718 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 719 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 720 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 721 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 722 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 723 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 724 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 725 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 726 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 727 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 728
 729 enum
 730 {
 731   REG_80 = 0,
 732   REG_81,
 733   REG_83,
 734   REG_8F,
 735   REG_C0,
 736   REG_C1,
 737   REG_C6,
 738   REG_C7,
 739   REG_D0,
 740   REG_D1,
 741   REG_D2,
 742   REG_D3,
 743   REG_F6,
 744   REG_F7,
 745   REG_FE,
 746   REG_FF,
 747   REG_0F00,
 748   REG_0F01,
 749   REG_0F0D,
 750   REG_0F18,
 751   REG_0F1C_MOD_0,
 752   REG_0F1E_MOD_3,
 753   REG_0F71,
 754   REG_0F72,
 755   REG_0F73,
 756   REG_0FA6,
 757   REG_0FA7,
 758   REG_0FAE,
 759   REG_0FBA,
 760   REG_0FC7,
 761   REG_VEX_0F71,
 762   REG_VEX_0F72,
 763   REG_VEX_0F73,
 764   REG_VEX_0FAE,
 765   REG_VEX_0F38F3,
 766   REG_XOP_LWPCB,
 767   REG_XOP_LWP,
 768   REG_XOP_TBM_01,
 769   REG_XOP_TBM_02,
 770
 771   REG_EVEX_0F71,
 772   REG_EVEX_0F72,
 773   REG_EVEX_0F73,
 774   REG_EVEX_0F38C6,
 775   REG_EVEX_0F38C7
 776 };
 777
 778 enum
 779 {
 780   MOD_8D = 0,
 781   MOD_C6_REG_7,
 782   MOD_C7_REG_7,
 783   MOD_FF_REG_3,
 784   MOD_FF_REG_5,
 785   MOD_0F01_REG_0,
 786   MOD_0F01_REG_1,
 787   MOD_0F01_REG_2,
 788   MOD_0F01_REG_3,
 789   MOD_0F01_REG_5,
 790   MOD_0F01_REG_7,
 791   MOD_0F12_PREFIX_0,
 792   MOD_0F13,
 793   MOD_0F16_PREFIX_0,
 794   MOD_0F17,
 795   MOD_0F18_REG_0,
 796   MOD_0F18_REG_1,
 797   MOD_0F18_REG_2,
 798   MOD_0F18_REG_3,
 799   MOD_0F18_REG_4,
 800   MOD_0F18_REG_5,
 801   MOD_0F18_REG_6,
 802   MOD_0F18_REG_7,
 803   MOD_0F1A_PREFIX_0,
 804   MOD_0F1B_PREFIX_0,
 805   MOD_0F1B_PREFIX_1,
 806   MOD_0F1C_PREFIX_0,
 807   MOD_0F1E_PREFIX_1,
 808   MOD_0F24,
 809   MOD_0F26,
 810   MOD_0F2B_PREFIX_0,
 811   MOD_0F2B_PREFIX_1,
 812   MOD_0F2B_PREFIX_2,
 813   MOD_0F2B_PREFIX_3,
 814   MOD_0F51,
 815   MOD_0F71_REG_2,
 816   MOD_0F71_REG_4,
 817   MOD_0F71_REG_6,
 818   MOD_0F72_REG_2,
 819   MOD_0F72_REG_4,
 820   MOD_0F72_REG_6,
 821   MOD_0F73_REG_2,
 822   MOD_0F73_REG_3,
 823   MOD_0F73_REG_6,
 824   MOD_0F73_REG_7,
 825   MOD_0FAE_REG_0,
 826   MOD_0FAE_REG_1,
 827   MOD_0FAE_REG_2,
 828   MOD_0FAE_REG_3,
 829   MOD_0FAE_REG_4,
 830   MOD_0FAE_REG_5,
 831   MOD_0FAE_REG_6,
 832   MOD_0FAE_REG_7,
 833   MOD_0FB2,
 834   MOD_0FB4,
 835   MOD_0FB5,
 836   MOD_0FC3,
 837   MOD_0FC7_REG_3,
 838   MOD_0FC7_REG_4,
 839   MOD_0FC7_REG_5,
 840   MOD_0FC7_REG_6,
 841   MOD_0FC7_REG_7,
 842   MOD_0FD7,
 843   MOD_0FE7_PREFIX_2,
 844   MOD_0FF0_PREFIX_3,
 845   MOD_0F382A_PREFIX_2,
 846   MOD_0F38F5_PREFIX_2,
 847   MOD_0F38F6_PREFIX_0,
 848   MOD_0F38F8_PREFIX_1,
 849   MOD_0F38F8_PREFIX_2,
 850   MOD_0F38F8_PREFIX_3,
 851   MOD_0F38F9_PREFIX_0,
 852   MOD_62_32BIT,
 853   MOD_C4_32BIT,
 854   MOD_C5_32BIT,
 855   MOD_VEX_0F12_PREFIX_0,
 856   MOD_VEX_0F13,
 857   MOD_VEX_0F16_PREFIX_0,
 858   MOD_VEX_0F17,
 859   MOD_VEX_0F2B,
 860   MOD_VEX_W_0_0F41_P_0_LEN_1,
 861   MOD_VEX_W_1_0F41_P_0_LEN_1,
 862   MOD_VEX_W_0_0F41_P_2_LEN_1,
 863   MOD_VEX_W_1_0F41_P_2_LEN_1,
 864   MOD_VEX_W_0_0F42_P_0_LEN_1,
 865   MOD_VEX_W_1_0F42_P_0_LEN_1,
 866   MOD_VEX_W_0_0F42_P_2_LEN_1,
 867   MOD_VEX_W_1_0F42_P_2_LEN_1,
 868   MOD_VEX_W_0_0F44_P_0_LEN_1,
 869   MOD_VEX_W_1_0F44_P_0_LEN_1,
 870   MOD_VEX_W_0_0F44_P_2_LEN_1,
 871   MOD_VEX_W_1_0F44_P_2_LEN_1,
 872   MOD_VEX_W_0_0F45_P_0_LEN_1,
 873   MOD_VEX_W_1_0F45_P_0_LEN_1,
 874   MOD_VEX_W_0_0F45_P_2_LEN_1,
 875   MOD_VEX_W_1_0F45_P_2_LEN_1,
 876   MOD_VEX_W_0_0F46_P_0_LEN_1,
 877   MOD_VEX_W_1_0F46_P_0_LEN_1,
 878   MOD_VEX_W_0_0F46_P_2_LEN_1,
 879   MOD_VEX_W_1_0F46_P_2_LEN_1,
 880   MOD_VEX_W_0_0F47_P_0_LEN_1,
 881   MOD_VEX_W_1_0F47_P_0_LEN_1,
 882   MOD_VEX_W_0_0F47_P_2_LEN_1,
 883   MOD_VEX_W_1_0F47_P_2_LEN_1,
 884   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 885   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 886   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 887   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 888   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 889   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 890   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 891   MOD_VEX_0F50,
 892   MOD_VEX_0F71_REG_2,
 893   MOD_VEX_0F71_REG_4,
 894   MOD_VEX_0F71_REG_6,
 895   MOD_VEX_0F72_REG_2,
 896   MOD_VEX_0F72_REG_4,
 897   MOD_VEX_0F72_REG_6,
 898   MOD_VEX_0F73_REG_2,
 899   MOD_VEX_0F73_REG_3,
 900   MOD_VEX_0F73_REG_6,
 901   MOD_VEX_0F73_REG_7,
 902   MOD_VEX_W_0_0F91_P_0_LEN_0,
 903   MOD_VEX_W_1_0F91_P_0_LEN_0,
 904   MOD_VEX_W_0_0F91_P_2_LEN_0,
 905   MOD_VEX_W_1_0F91_P_2_LEN_0,
 906   MOD_VEX_W_0_0F92_P_0_LEN_0,
 907   MOD_VEX_W_0_0F92_P_2_LEN_0,
 908   MOD_VEX_0F92_P_3_LEN_0,
 909   MOD_VEX_W_0_0F93_P_0_LEN_0,
 910   MOD_VEX_W_0_0F93_P_2_LEN_0,
 911   MOD_VEX_0F93_P_3_LEN_0,
 912   MOD_VEX_W_0_0F98_P_0_LEN_0,
 913   MOD_VEX_W_1_0F98_P_0_LEN_0,
 914   MOD_VEX_W_0_0F98_P_2_LEN_0,
 915   MOD_VEX_W_1_0F98_P_2_LEN_0,
 916   MOD_VEX_W_0_0F99_P_0_LEN_0,
 917   MOD_VEX_W_1_0F99_P_0_LEN_0,
 918   MOD_VEX_W_0_0F99_P_2_LEN_0,
 919   MOD_VEX_W_1_0F99_P_2_LEN_0,
 920   MOD_VEX_0FAE_REG_2,
 921   MOD_VEX_0FAE_REG_3,
 922   MOD_VEX_0FD7_PREFIX_2,
 923   MOD_VEX_0FE7_PREFIX_2,
 924   MOD_VEX_0FF0_PREFIX_3,
 925   MOD_VEX_0F381A_PREFIX_2,
 926   MOD_VEX_0F382A_PREFIX_2,
 927   MOD_VEX_0F382C_PREFIX_2,
 928   MOD_VEX_0F382D_PREFIX_2,
 929   MOD_VEX_0F382E_PREFIX_2,
 930   MOD_VEX_0F382F_PREFIX_2,
 931   MOD_VEX_0F385A_PREFIX_2,
 932   MOD_VEX_0F388C_PREFIX_2,
 933   MOD_VEX_0F388E_PREFIX_2,
 934   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 935   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 936   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 937   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 938   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 939   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 940   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 941   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 942
 943   MOD_EVEX_0F10_PREFIX_1,
 944   MOD_EVEX_0F10_PREFIX_3,
 945   MOD_EVEX_0F11_PREFIX_1,
 946   MOD_EVEX_0F11_PREFIX_3,
 947   MOD_EVEX_0F12_PREFIX_0,
 948   MOD_EVEX_0F16_PREFIX_0,
 949   MOD_EVEX_0F38C6_REG_1,
 950   MOD_EVEX_0F38C6_REG_2,
 951   MOD_EVEX_0F38C6_REG_5,
 952   MOD_EVEX_0F38C6_REG_6,
 953   MOD_EVEX_0F38C7_REG_1,
 954   MOD_EVEX_0F38C7_REG_2,
 955   MOD_EVEX_0F38C7_REG_5,
 956   MOD_EVEX_0F38C7_REG_6
 957 };
 958
 959 enum
 960 {
 961   RM_C6_REG_7 = 0,
 962   RM_C7_REG_7,
 963   RM_0F01_REG_0,
 964   RM_0F01_REG_1,
 965   RM_0F01_REG_2,
 966   RM_0F01_REG_3,
 967   RM_0F01_REG_5,
 968   RM_0F01_REG_7,
 969   RM_0F1E_MOD_3_REG_7,
 970   RM_0FAE_REG_6,
 971   RM_0FAE_REG_7
 972 };
 973
 974 enum
 975 {
 976   PREFIX_90 = 0,
 977   PREFIX_MOD_0_0F01_REG_5,
 978   PREFIX_MOD_3_0F01_REG_5_RM_0,
 979   PREFIX_MOD_3_0F01_REG_5_RM_2,
 980   PREFIX_0F09,
 981   PREFIX_0F10,
 982   PREFIX_0F11,
 983   PREFIX_0F12,
 984   PREFIX_0F16,
 985   PREFIX_0F1A,
 986   PREFIX_0F1B,
 987   PREFIX_0F1C,
 988   PREFIX_0F1E,
 989   PREFIX_0F2A,
 990   PREFIX_0F2B,
 991   PREFIX_0F2C,
 992   PREFIX_0F2D,
 993   PREFIX_0F2E,
 994   PREFIX_0F2F,
 995   PREFIX_0F51,
 996   PREFIX_0F52,
 997   PREFIX_0F53,
 998   PREFIX_0F58,
 999   PREFIX_0F59,
1000   PREFIX_0F5A,
1001   PREFIX_0F5B,
1002   PREFIX_0F5C,
1003   PREFIX_0F5D,
1004   PREFIX_0F5E,
1005   PREFIX_0F5F,
1006   PREFIX_0F60,
1007   PREFIX_0F61,
1008   PREFIX_0F62,
1009   PREFIX_0F6C,
1010   PREFIX_0F6D,
1011   PREFIX_0F6F,
1012   PREFIX_0F70,
1013   PREFIX_0F73_REG_3,
1014   PREFIX_0F73_REG_7,
1015   PREFIX_0F78,
1016   PREFIX_0F79,
1017   PREFIX_0F7C,
1018   PREFIX_0F7D,
1019   PREFIX_0F7E,
1020   PREFIX_0F7F,
1021   PREFIX_0FAE_REG_0,
1022   PREFIX_0FAE_REG_1,
1023   PREFIX_0FAE_REG_2,
1024   PREFIX_0FAE_REG_3,
1025   PREFIX_MOD_0_0FAE_REG_4,
1026   PREFIX_MOD_3_0FAE_REG_4,
1027   PREFIX_MOD_0_0FAE_REG_5,
1028   PREFIX_MOD_3_0FAE_REG_5,
1029   PREFIX_MOD_0_0FAE_REG_6,
1030   PREFIX_MOD_1_0FAE_REG_6,
1031   PREFIX_0FAE_REG_7,
1032   PREFIX_0FB8,
1033   PREFIX_0FBC,
1034   PREFIX_0FBD,
1035   PREFIX_0FC2,
1036   PREFIX_MOD_0_0FC3,
1037   PREFIX_MOD_0_0FC7_REG_6,
1038   PREFIX_MOD_3_0FC7_REG_6,
1039   PREFIX_MOD_3_0FC7_REG_7,
1040   PREFIX_0FD0,
1041   PREFIX_0FD6,
1042   PREFIX_0FE6,
1043   PREFIX_0FE7,
1044   PREFIX_0FF0,
1045   PREFIX_0FF7,
1046   PREFIX_0F3810,
1047   PREFIX_0F3814,
1048   PREFIX_0F3815,
1049   PREFIX_0F3817,
1050   PREFIX_0F3820,
1051   PREFIX_0F3821,
1052   PREFIX_0F3822,
1053   PREFIX_0F3823,
1054   PREFIX_0F3824,
1055   PREFIX_0F3825,
1056   PREFIX_0F3828,
1057   PREFIX_0F3829,
1058   PREFIX_0F382A,
1059   PREFIX_0F382B,
1060   PREFIX_0F3830,
1061   PREFIX_0F3831,
1062   PREFIX_0F3832,
1063   PREFIX_0F3833,
1064   PREFIX_0F3834,
1065   PREFIX_0F3835,
1066   PREFIX_0F3837,
1067   PREFIX_0F3838,
1068   PREFIX_0F3839,
1069   PREFIX_0F383A,
1070   PREFIX_0F383B,
1071   PREFIX_0F383C,
1072   PREFIX_0F383D,
1073   PREFIX_0F383E,
1074   PREFIX_0F383F,
1075   PREFIX_0F3840,
1076   PREFIX_0F3841,
1077   PREFIX_0F3880,
1078   PREFIX_0F3881,
1079   PREFIX_0F3882,
1080   PREFIX_0F38C8,
1081   PREFIX_0F38C9,
1082   PREFIX_0F38CA,
1083   PREFIX_0F38CB,
1084   PREFIX_0F38CC,
1085   PREFIX_0F38CD,
1086   PREFIX_0F38CF,
1087   PREFIX_0F38DB,
1088   PREFIX_0F38DC,
1089   PREFIX_0F38DD,
1090   PREFIX_0F38DE,
1091   PREFIX_0F38DF,
1092   PREFIX_0F38F0,
1093   PREFIX_0F38F1,
1094   PREFIX_0F38F5,
1095   PREFIX_0F38F6,
1096   PREFIX_0F38F8,
1097   PREFIX_0F38F9,
1098   PREFIX_0F3A08,
1099   PREFIX_0F3A09,
1100   PREFIX_0F3A0A,
1101   PREFIX_0F3A0B,
1102   PREFIX_0F3A0C,
1103   PREFIX_0F3A0D,
1104   PREFIX_0F3A0E,
1105   PREFIX_0F3A14,
1106   PREFIX_0F3A15,
1107   PREFIX_0F3A16,
1108   PREFIX_0F3A17,
1109   PREFIX_0F3A20,
1110   PREFIX_0F3A21,
1111   PREFIX_0F3A22,
1112   PREFIX_0F3A40,
1113   PREFIX_0F3A41,
1114   PREFIX_0F3A42,
1115   PREFIX_0F3A44,
1116   PREFIX_0F3A60,
1117   PREFIX_0F3A61,
1118   PREFIX_0F3A62,
1119   PREFIX_0F3A63,
1120   PREFIX_0F3ACC,
1121   PREFIX_0F3ACE,
1122   PREFIX_0F3ACF,
1123   PREFIX_0F3ADF,
1124   PREFIX_VEX_0F10,
1125   PREFIX_VEX_0F11,
1126   PREFIX_VEX_0F12,
1127   PREFIX_VEX_0F16,
1128   PREFIX_VEX_0F2A,
1129   PREFIX_VEX_0F2C,
1130   PREFIX_VEX_0F2D,
1131   PREFIX_VEX_0F2E,
1132   PREFIX_VEX_0F2F,
1133   PREFIX_VEX_0F41,
1134   PREFIX_VEX_0F42,
1135   PREFIX_VEX_0F44,
1136   PREFIX_VEX_0F45,
1137   PREFIX_VEX_0F46,
1138   PREFIX_VEX_0F47,
1139   PREFIX_VEX_0F4A,
1140   PREFIX_VEX_0F4B,
1141   PREFIX_VEX_0F51,
1142   PREFIX_VEX_0F52,
1143   PREFIX_VEX_0F53,
1144   PREFIX_VEX_0F58,
1145   PREFIX_VEX_0F59,
1146   PREFIX_VEX_0F5A,
1147   PREFIX_VEX_0F5B,
1148   PREFIX_VEX_0F5C,
1149   PREFIX_VEX_0F5D,
1150   PREFIX_VEX_0F5E,
1151   PREFIX_VEX_0F5F,
1152   PREFIX_VEX_0F60,
1153   PREFIX_VEX_0F61,
1154   PREFIX_VEX_0F62,
1155   PREFIX_VEX_0F63,
1156   PREFIX_VEX_0F64,
1157   PREFIX_VEX_0F65,
1158   PREFIX_VEX_0F66,
1159   PREFIX_VEX_0F67,
1160   PREFIX_VEX_0F68,
1161   PREFIX_VEX_0F69,
1162   PREFIX_VEX_0F6A,
1163   PREFIX_VEX_0F6B,
1164   PREFIX_VEX_0F6C,
1165   PREFIX_VEX_0F6D,
1166   PREFIX_VEX_0F6E,
1167   PREFIX_VEX_0F6F,
1168   PREFIX_VEX_0F70,
1169   PREFIX_VEX_0F71_REG_2,
1170   PREFIX_VEX_0F71_REG_4,
1171   PREFIX_VEX_0F71_REG_6,
1172   PREFIX_VEX_0F72_REG_2,
1173   PREFIX_VEX_0F72_REG_4,
1174   PREFIX_VEX_0F72_REG_6,
1175   PREFIX_VEX_0F73_REG_2,
1176   PREFIX_VEX_0F73_REG_3,
1177   PREFIX_VEX_0F73_REG_6,
1178   PREFIX_VEX_0F73_REG_7,
1179   PREFIX_VEX_0F74,
1180   PREFIX_VEX_0F75,
1181   PREFIX_VEX_0F76,
1182   PREFIX_VEX_0F77,
1183   PREFIX_VEX_0F7C,
1184   PREFIX_VEX_0F7D,
1185   PREFIX_VEX_0F7E,
1186   PREFIX_VEX_0F7F,
1187   PREFIX_VEX_0F90,
1188   PREFIX_VEX_0F91,
1189   PREFIX_VEX_0F92,
1190   PREFIX_VEX_0F93,
1191   PREFIX_VEX_0F98,
1192   PREFIX_VEX_0F99,
1193   PREFIX_VEX_0FC2,
1194   PREFIX_VEX_0FC4,
1195   PREFIX_VEX_0FC5,
1196   PREFIX_VEX_0FD0,
1197   PREFIX_VEX_0FD1,
1198   PREFIX_VEX_0FD2,
1199   PREFIX_VEX_0FD3,
1200   PREFIX_VEX_0FD4,
1201   PREFIX_VEX_0FD5,
1202   PREFIX_VEX_0FD6,
1203   PREFIX_VEX_0FD7,
1204   PREFIX_VEX_0FD8,
1205   PREFIX_VEX_0FD9,
1206   PREFIX_VEX_0FDA,
1207   PREFIX_VEX_0FDB,
1208   PREFIX_VEX_0FDC,
1209   PREFIX_VEX_0FDD,
1210   PREFIX_VEX_0FDE,
1211   PREFIX_VEX_0FDF,
1212   PREFIX_VEX_0FE0,
1213   PREFIX_VEX_0FE1,
1214   PREFIX_VEX_0FE2,
1215   PREFIX_VEX_0FE3,
1216   PREFIX_VEX_0FE4,
1217   PREFIX_VEX_0FE5,
1218   PREFIX_VEX_0FE6,
1219   PREFIX_VEX_0FE7,
1220   PREFIX_VEX_0FE8,
1221   PREFIX_VEX_0FE9,
1222   PREFIX_VEX_0FEA,
1223   PREFIX_VEX_0FEB,
1224   PREFIX_VEX_0FEC,
1225   PREFIX_VEX_0FED,
1226   PREFIX_VEX_0FEE,
1227   PREFIX_VEX_0FEF,
1228   PREFIX_VEX_0FF0,
1229   PREFIX_VEX_0FF1,
1230   PREFIX_VEX_0FF2,
1231   PREFIX_VEX_0FF3,
1232   PREFIX_VEX_0FF4,
1233   PREFIX_VEX_0FF5,
1234   PREFIX_VEX_0FF6,
1235   PREFIX_VEX_0FF7,
1236   PREFIX_VEX_0FF8,
1237   PREFIX_VEX_0FF9,
1238   PREFIX_VEX_0FFA,
1239   PREFIX_VEX_0FFB,
1240   PREFIX_VEX_0FFC,
1241   PREFIX_VEX_0FFD,
1242   PREFIX_VEX_0FFE,
1243   PREFIX_VEX_0F3800,
1244   PREFIX_VEX_0F3801,
1245   PREFIX_VEX_0F3802,
1246   PREFIX_VEX_0F3803,
1247   PREFIX_VEX_0F3804,
1248   PREFIX_VEX_0F3805,
1249   PREFIX_VEX_0F3806,
1250   PREFIX_VEX_0F3807,
1251   PREFIX_VEX_0F3808,
1252   PREFIX_VEX_0F3809,
1253   PREFIX_VEX_0F380A,
1254   PREFIX_VEX_0F380B,
1255   PREFIX_VEX_0F380C,
1256   PREFIX_VEX_0F380D,
1257   PREFIX_VEX_0F380E,
1258   PREFIX_VEX_0F380F,
1259   PREFIX_VEX_0F3813,
1260   PREFIX_VEX_0F3816,
1261   PREFIX_VEX_0F3817,
1262   PREFIX_VEX_0F3818,
1263   PREFIX_VEX_0F3819,
1264   PREFIX_VEX_0F381A,
1265   PREFIX_VEX_0F381C,
1266   PREFIX_VEX_0F381D,
1267   PREFIX_VEX_0F381E,
1268   PREFIX_VEX_0F3820,
1269   PREFIX_VEX_0F3821,
1270   PREFIX_VEX_0F3822,
1271   PREFIX_VEX_0F3823,
1272   PREFIX_VEX_0F3824,
1273   PREFIX_VEX_0F3825,
1274   PREFIX_VEX_0F3828,
1275   PREFIX_VEX_0F3829,
1276   PREFIX_VEX_0F382A,
1277   PREFIX_VEX_0F382B,
1278   PREFIX_VEX_0F382C,
1279   PREFIX_VEX_0F382D,
1280   PREFIX_VEX_0F382E,
1281   PREFIX_VEX_0F382F,
1282   PREFIX_VEX_0F3830,
1283   PREFIX_VEX_0F3831,
1284   PREFIX_VEX_0F3832,
1285   PREFIX_VEX_0F3833,
1286   PREFIX_VEX_0F3834,
1287   PREFIX_VEX_0F3835,
1288   PREFIX_VEX_0F3836,
1289   PREFIX_VEX_0F3837,
1290   PREFIX_VEX_0F3838,
1291   PREFIX_VEX_0F3839,
1292   PREFIX_VEX_0F383A,
1293   PREFIX_VEX_0F383B,
1294   PREFIX_VEX_0F383C,
1295   PREFIX_VEX_0F383D,
1296   PREFIX_VEX_0F383E,
1297   PREFIX_VEX_0F383F,
1298   PREFIX_VEX_0F3840,
1299   PREFIX_VEX_0F3841,
1300   PREFIX_VEX_0F3845,
1301   PREFIX_VEX_0F3846,
1302   PREFIX_VEX_0F3847,
1303   PREFIX_VEX_0F3858,
1304   PREFIX_VEX_0F3859,
1305   PREFIX_VEX_0F385A,
1306   PREFIX_VEX_0F3878,
1307   PREFIX_VEX_0F3879,
1308   PREFIX_VEX_0F388C,
1309   PREFIX_VEX_0F388E,
1310   PREFIX_VEX_0F3890,
1311   PREFIX_VEX_0F3891,
1312   PREFIX_VEX_0F3892,
1313   PREFIX_VEX_0F3893,
1314   PREFIX_VEX_0F3896,
1315   PREFIX_VEX_0F3897,
1316   PREFIX_VEX_0F3898,
1317   PREFIX_VEX_0F3899,
1318   PREFIX_VEX_0F389A,
1319   PREFIX_VEX_0F389B,
1320   PREFIX_VEX_0F389C,
1321   PREFIX_VEX_0F389D,
1322   PREFIX_VEX_0F389E,
1323   PREFIX_VEX_0F389F,
1324   PREFIX_VEX_0F38A6,
1325   PREFIX_VEX_0F38A7,
1326   PREFIX_VEX_0F38A8,
1327   PREFIX_VEX_0F38A9,
1328   PREFIX_VEX_0F38AA,
1329   PREFIX_VEX_0F38AB,
1330   PREFIX_VEX_0F38AC,
1331   PREFIX_VEX_0F38AD,
1332   PREFIX_VEX_0F38AE,
1333   PREFIX_VEX_0F38AF,
1334   PREFIX_VEX_0F38B6,
1335   PREFIX_VEX_0F38B7,
1336   PREFIX_VEX_0F38B8,
1337   PREFIX_VEX_0F38B9,
1338   PREFIX_VEX_0F38BA,
1339   PREFIX_VEX_0F38BB,
1340   PREFIX_VEX_0F38BC,
1341   PREFIX_VEX_0F38BD,
1342   PREFIX_VEX_0F38BE,
1343   PREFIX_VEX_0F38BF,
1344   PREFIX_VEX_0F38CF,
1345   PREFIX_VEX_0F38DB,
1346   PREFIX_VEX_0F38DC,
1347   PREFIX_VEX_0F38DD,
1348   PREFIX_VEX_0F38DE,
1349   PREFIX_VEX_0F38DF,
1350   PREFIX_VEX_0F38F2,
1351   PREFIX_VEX_0F38F3_REG_1,
1352   PREFIX_VEX_0F38F3_REG_2,
1353   PREFIX_VEX_0F38F3_REG_3,
1354   PREFIX_VEX_0F38F5,
1355   PREFIX_VEX_0F38F6,
1356   PREFIX_VEX_0F38F7,
1357   PREFIX_VEX_0F3A00,
1358   PREFIX_VEX_0F3A01,
1359   PREFIX_VEX_0F3A02,
1360   PREFIX_VEX_0F3A04,
1361   PREFIX_VEX_0F3A05,
1362   PREFIX_VEX_0F3A06,
1363   PREFIX_VEX_0F3A08,
1364   PREFIX_VEX_0F3A09,
1365   PREFIX_VEX_0F3A0A,
1366   PREFIX_VEX_0F3A0B,
1367   PREFIX_VEX_0F3A0C,
1368   PREFIX_VEX_0F3A0D,
1369   PREFIX_VEX_0F3A0E,
1370   PREFIX_VEX_0F3A0F,
1371   PREFIX_VEX_0F3A14,
1372   PREFIX_VEX_0F3A15,
1373   PREFIX_VEX_0F3A16,
1374   PREFIX_VEX_0F3A17,
1375   PREFIX_VEX_0F3A18,
1376   PREFIX_VEX_0F3A19,
1377   PREFIX_VEX_0F3A1D,
1378   PREFIX_VEX_0F3A20,
1379   PREFIX_VEX_0F3A21,
1380   PREFIX_VEX_0F3A22,
1381   PREFIX_VEX_0F3A30,
1382   PREFIX_VEX_0F3A31,
1383   PREFIX_VEX_0F3A32,
1384   PREFIX_VEX_0F3A33,
1385   PREFIX_VEX_0F3A38,
1386   PREFIX_VEX_0F3A39,
1387   PREFIX_VEX_0F3A40,
1388   PREFIX_VEX_0F3A41,
1389   PREFIX_VEX_0F3A42,
1390   PREFIX_VEX_0F3A44,
1391   PREFIX_VEX_0F3A46,
1392   PREFIX_VEX_0F3A48,
1393   PREFIX_VEX_0F3A49,
1394   PREFIX_VEX_0F3A4A,
1395   PREFIX_VEX_0F3A4B,
1396   PREFIX_VEX_0F3A4C,
1397   PREFIX_VEX_0F3A5C,
1398   PREFIX_VEX_0F3A5D,
1399   PREFIX_VEX_0F3A5E,
1400   PREFIX_VEX_0F3A5F,
1401   PREFIX_VEX_0F3A60,
1402   PREFIX_VEX_0F3A61,
1403   PREFIX_VEX_0F3A62,
1404   PREFIX_VEX_0F3A63,
1405   PREFIX_VEX_0F3A68,
1406   PREFIX_VEX_0F3A69,
1407   PREFIX_VEX_0F3A6A,
1408   PREFIX_VEX_0F3A6B,
1409   PREFIX_VEX_0F3A6C,
1410   PREFIX_VEX_0F3A6D,
1411   PREFIX_VEX_0F3A6E,
1412   PREFIX_VEX_0F3A6F,
1413   PREFIX_VEX_0F3A78,
1414   PREFIX_VEX_0F3A79,
1415   PREFIX_VEX_0F3A7A,
1416   PREFIX_VEX_0F3A7B,
1417   PREFIX_VEX_0F3A7C,
1418   PREFIX_VEX_0F3A7D,
1419   PREFIX_VEX_0F3A7E,
1420   PREFIX_VEX_0F3A7F,
1421   PREFIX_VEX_0F3ACE,
1422   PREFIX_VEX_0F3ACF,
1423   PREFIX_VEX_0F3ADF,
1424   PREFIX_VEX_0F3AF0,
1425
1426   PREFIX_EVEX_0F10,
1427   PREFIX_EVEX_0F11,
1428   PREFIX_EVEX_0F12,
1429   PREFIX_EVEX_0F13,
1430   PREFIX_EVEX_0F14,
1431   PREFIX_EVEX_0F15,
1432   PREFIX_EVEX_0F16,
1433   PREFIX_EVEX_0F17,
1434   PREFIX_EVEX_0F28,
1435   PREFIX_EVEX_0F29,
1436   PREFIX_EVEX_0F2A,
1437   PREFIX_EVEX_0F2B,
1438   PREFIX_EVEX_0F2C,
1439   PREFIX_EVEX_0F2D,
1440   PREFIX_EVEX_0F2E,
1441   PREFIX_EVEX_0F2F,
1442   PREFIX_EVEX_0F51,
1443   PREFIX_EVEX_0F54,
1444   PREFIX_EVEX_0F55,
1445   PREFIX_EVEX_0F56,
1446   PREFIX_EVEX_0F57,
1447   PREFIX_EVEX_0F58,
1448   PREFIX_EVEX_0F59,
1449   PREFIX_EVEX_0F5A,
1450   PREFIX_EVEX_0F5B,
1451   PREFIX_EVEX_0F5C,
1452   PREFIX_EVEX_0F5D,
1453   PREFIX_EVEX_0F5E,
1454   PREFIX_EVEX_0F5F,
1455   PREFIX_EVEX_0F60,
1456   PREFIX_EVEX_0F61,
1457   PREFIX_EVEX_0F62,
1458   PREFIX_EVEX_0F63,
1459   PREFIX_EVEX_0F64,
1460   PREFIX_EVEX_0F65,
1461   PREFIX_EVEX_0F66,
1462   PREFIX_EVEX_0F67,
1463   PREFIX_EVEX_0F68,
1464   PREFIX_EVEX_0F69,
1465   PREFIX_EVEX_0F6A,
1466   PREFIX_EVEX_0F6B,
1467   PREFIX_EVEX_0F6C,
1468   PREFIX_EVEX_0F6D,
1469   PREFIX_EVEX_0F6E,
1470   PREFIX_EVEX_0F6F,
1471   PREFIX_EVEX_0F70,
1472   PREFIX_EVEX_0F71_REG_2,
1473   PREFIX_EVEX_0F71_REG_4,
1474   PREFIX_EVEX_0F71_REG_6,
1475   PREFIX_EVEX_0F72_REG_0,
1476   PREFIX_EVEX_0F72_REG_1,
1477   PREFIX_EVEX_0F72_REG_2,
1478   PREFIX_EVEX_0F72_REG_4,
1479   PREFIX_EVEX_0F72_REG_6,
1480   PREFIX_EVEX_0F73_REG_2,
1481   PREFIX_EVEX_0F73_REG_3,
1482   PREFIX_EVEX_0F73_REG_6,
1483   PREFIX_EVEX_0F73_REG_7,
1484   PREFIX_EVEX_0F74,
1485   PREFIX_EVEX_0F75,
1486   PREFIX_EVEX_0F76,
1487   PREFIX_EVEX_0F78,
1488   PREFIX_EVEX_0F79,
1489   PREFIX_EVEX_0F7A,
1490   PREFIX_EVEX_0F7B,
1491   PREFIX_EVEX_0F7E,
1492   PREFIX_EVEX_0F7F,
1493   PREFIX_EVEX_0FC2,
1494   PREFIX_EVEX_0FC4,
1495   PREFIX_EVEX_0FC5,
1496   PREFIX_EVEX_0FC6,
1497   PREFIX_EVEX_0FD1,
1498   PREFIX_EVEX_0FD2,
1499   PREFIX_EVEX_0FD3,
1500   PREFIX_EVEX_0FD4,
1501   PREFIX_EVEX_0FD5,
1502   PREFIX_EVEX_0FD6,
1503   PREFIX_EVEX_0FD8,
1504   PREFIX_EVEX_0FD9,
1505   PREFIX_EVEX_0FDA,
1506   PREFIX_EVEX_0FDB,
1507   PREFIX_EVEX_0FDC,
1508   PREFIX_EVEX_0FDD,
1509   PREFIX_EVEX_0FDE,
1510   PREFIX_EVEX_0FDF,
1511   PREFIX_EVEX_0FE0,
1512   PREFIX_EVEX_0FE1,
1513   PREFIX_EVEX_0FE2,
1514   PREFIX_EVEX_0FE3,
1515   PREFIX_EVEX_0FE4,
1516   PREFIX_EVEX_0FE5,
1517   PREFIX_EVEX_0FE6,
1518   PREFIX_EVEX_0FE7,
1519   PREFIX_EVEX_0FE8,
1520   PREFIX_EVEX_0FE9,
1521   PREFIX_EVEX_0FEA,
1522   PREFIX_EVEX_0FEB,
1523   PREFIX_EVEX_0FEC,
1524   PREFIX_EVEX_0FED,
1525   PREFIX_EVEX_0FEE,
1526   PREFIX_EVEX_0FEF,
1527   PREFIX_EVEX_0FF1,
1528   PREFIX_EVEX_0FF2,
1529   PREFIX_EVEX_0FF3,
1530   PREFIX_EVEX_0FF4,
1531   PREFIX_EVEX_0FF5,
1532   PREFIX_EVEX_0FF6,
1533   PREFIX_EVEX_0FF8,
1534   PREFIX_EVEX_0FF9,
1535   PREFIX_EVEX_0FFA,
1536   PREFIX_EVEX_0FFB,
1537   PREFIX_EVEX_0FFC,
1538   PREFIX_EVEX_0FFD,
1539   PREFIX_EVEX_0FFE,
1540   PREFIX_EVEX_0F3800,
1541   PREFIX_EVEX_0F3804,
1542   PREFIX_EVEX_0F380B,
1543   PREFIX_EVEX_0F380C,
1544   PREFIX_EVEX_0F380D,
1545   PREFIX_EVEX_0F3810,
1546   PREFIX_EVEX_0F3811,
1547   PREFIX_EVEX_0F3812,
1548   PREFIX_EVEX_0F3813,
1549   PREFIX_EVEX_0F3814,
1550   PREFIX_EVEX_0F3815,
1551   PREFIX_EVEX_0F3816,
1552   PREFIX_EVEX_0F3818,
1553   PREFIX_EVEX_0F3819,
1554   PREFIX_EVEX_0F381A,
1555   PREFIX_EVEX_0F381B,
1556   PREFIX_EVEX_0F381C,
1557   PREFIX_EVEX_0F381D,
1558   PREFIX_EVEX_0F381E,
1559   PREFIX_EVEX_0F381F,
1560   PREFIX_EVEX_0F3820,
1561   PREFIX_EVEX_0F3821,
1562   PREFIX_EVEX_0F3822,
1563   PREFIX_EVEX_0F3823,
1564   PREFIX_EVEX_0F3824,
1565   PREFIX_EVEX_0F3825,
1566   PREFIX_EVEX_0F3826,
1567   PREFIX_EVEX_0F3827,
1568   PREFIX_EVEX_0F3828,
1569   PREFIX_EVEX_0F3829,
1570   PREFIX_EVEX_0F382A,
1571   PREFIX_EVEX_0F382B,
1572   PREFIX_EVEX_0F382C,
1573   PREFIX_EVEX_0F382D,
1574   PREFIX_EVEX_0F3830,
1575   PREFIX_EVEX_0F3831,
1576   PREFIX_EVEX_0F3832,
1577   PREFIX_EVEX_0F3833,
1578   PREFIX_EVEX_0F3834,
1579   PREFIX_EVEX_0F3835,
1580   PREFIX_EVEX_0F3836,
1581   PREFIX_EVEX_0F3837,
1582   PREFIX_EVEX_0F3838,
1583   PREFIX_EVEX_0F3839,
1584   PREFIX_EVEX_0F383A,
1585   PREFIX_EVEX_0F383B,
1586   PREFIX_EVEX_0F383C,
1587   PREFIX_EVEX_0F383D,
1588   PREFIX_EVEX_0F383E,
1589   PREFIX_EVEX_0F383F,
1590   PREFIX_EVEX_0F3840,
1591   PREFIX_EVEX_0F3842,
1592   PREFIX_EVEX_0F3843,
1593   PREFIX_EVEX_0F3844,
1594   PREFIX_EVEX_0F3845,
1595   PREFIX_EVEX_0F3846,
1596   PREFIX_EVEX_0F3847,
1597   PREFIX_EVEX_0F384C,
1598   PREFIX_EVEX_0F384D,
1599   PREFIX_EVEX_0F384E,
1600   PREFIX_EVEX_0F384F,
1601   PREFIX_EVEX_0F3850,
1602   PREFIX_EVEX_0F3851,
1603   PREFIX_EVEX_0F3852,
1604   PREFIX_EVEX_0F3853,
1605   PREFIX_EVEX_0F3854,
1606   PREFIX_EVEX_0F3855,
1607   PREFIX_EVEX_0F3858,
1608   PREFIX_EVEX_0F3859,
1609   PREFIX_EVEX_0F385A,
1610   PREFIX_EVEX_0F385B,
1611   PREFIX_EVEX_0F3862,
1612   PREFIX_EVEX_0F3863,
1613   PREFIX_EVEX_0F3864,
1614   PREFIX_EVEX_0F3865,
1615   PREFIX_EVEX_0F3866,
1616   PREFIX_EVEX_0F3868,
1617   PREFIX_EVEX_0F3870,
1618   PREFIX_EVEX_0F3871,
1619   PREFIX_EVEX_0F3872,
1620   PREFIX_EVEX_0F3873,
1621   PREFIX_EVEX_0F3875,
1622   PREFIX_EVEX_0F3876,
1623   PREFIX_EVEX_0F3877,
1624   PREFIX_EVEX_0F3878,
1625   PREFIX_EVEX_0F3879,
1626   PREFIX_EVEX_0F387A,
1627   PREFIX_EVEX_0F387B,
1628   PREFIX_EVEX_0F387C,
1629   PREFIX_EVEX_0F387D,
1630   PREFIX_EVEX_0F387E,
1631   PREFIX_EVEX_0F387F,
1632   PREFIX_EVEX_0F3883,
1633   PREFIX_EVEX_0F3888,
1634   PREFIX_EVEX_0F3889,
1635   PREFIX_EVEX_0F388A,
1636   PREFIX_EVEX_0F388B,
1637   PREFIX_EVEX_0F388D,
1638   PREFIX_EVEX_0F388F,
1639   PREFIX_EVEX_0F3890,
1640   PREFIX_EVEX_0F3891,
1641   PREFIX_EVEX_0F3892,
1642   PREFIX_EVEX_0F3893,
1643   PREFIX_EVEX_0F3896,
1644   PREFIX_EVEX_0F3897,
1645   PREFIX_EVEX_0F3898,
1646   PREFIX_EVEX_0F3899,
1647   PREFIX_EVEX_0F389A,
1648   PREFIX_EVEX_0F389B,
1649   PREFIX_EVEX_0F389C,
1650   PREFIX_EVEX_0F389D,
1651   PREFIX_EVEX_0F389E,
1652   PREFIX_EVEX_0F389F,
1653   PREFIX_EVEX_0F38A0,
1654   PREFIX_EVEX_0F38A1,
1655   PREFIX_EVEX_0F38A2,
1656   PREFIX_EVEX_0F38A3,
1657   PREFIX_EVEX_0F38A6,
1658   PREFIX_EVEX_0F38A7,
1659   PREFIX_EVEX_0F38A8,
1660   PREFIX_EVEX_0F38A9,
1661   PREFIX_EVEX_0F38AA,
1662   PREFIX_EVEX_0F38AB,
1663   PREFIX_EVEX_0F38AC,
1664   PREFIX_EVEX_0F38AD,
1665   PREFIX_EVEX_0F38AE,
1666   PREFIX_EVEX_0F38AF,
1667   PREFIX_EVEX_0F38B4,
1668   PREFIX_EVEX_0F38B5,
1669   PREFIX_EVEX_0F38B6,
1670   PREFIX_EVEX_0F38B7,
1671   PREFIX_EVEX_0F38B8,
1672   PREFIX_EVEX_0F38B9,
1673   PREFIX_EVEX_0F38BA,
1674   PREFIX_EVEX_0F38BB,
1675   PREFIX_EVEX_0F38BC,
1676   PREFIX_EVEX_0F38BD,
1677   PREFIX_EVEX_0F38BE,
1678   PREFIX_EVEX_0F38BF,
1679   PREFIX_EVEX_0F38C4,
1680   PREFIX_EVEX_0F38C6_REG_1,
1681   PREFIX_EVEX_0F38C6_REG_2,
1682   PREFIX_EVEX_0F38C6_REG_5,
1683   PREFIX_EVEX_0F38C6_REG_6,
1684   PREFIX_EVEX_0F38C7_REG_1,
1685   PREFIX_EVEX_0F38C7_REG_2,
1686   PREFIX_EVEX_0F38C7_REG_5,
1687   PREFIX_EVEX_0F38C7_REG_6,
1688   PREFIX_EVEX_0F38C8,
1689   PREFIX_EVEX_0F38CA,
1690   PREFIX_EVEX_0F38CB,
1691   PREFIX_EVEX_0F38CC,
1692   PREFIX_EVEX_0F38CD,
1693   PREFIX_EVEX_0F38CF,
1694   PREFIX_EVEX_0F38DC,
1695   PREFIX_EVEX_0F38DD,
1696   PREFIX_EVEX_0F38DE,
1697   PREFIX_EVEX_0F38DF,
1698
1699   PREFIX_EVEX_0F3A00,
1700   PREFIX_EVEX_0F3A01,
1701   PREFIX_EVEX_0F3A03,
1702   PREFIX_EVEX_0F3A04,
1703   PREFIX_EVEX_0F3A05,
1704   PREFIX_EVEX_0F3A08,
1705   PREFIX_EVEX_0F3A09,
1706   PREFIX_EVEX_0F3A0A,
1707   PREFIX_EVEX_0F3A0B,
1708   PREFIX_EVEX_0F3A0F,
1709   PREFIX_EVEX_0F3A14,
1710   PREFIX_EVEX_0F3A15,
1711   PREFIX_EVEX_0F3A16,
1712   PREFIX_EVEX_0F3A17,
1713   PREFIX_EVEX_0F3A18,
1714   PREFIX_EVEX_0F3A19,
1715   PREFIX_EVEX_0F3A1A,
1716   PREFIX_EVEX_0F3A1B,
1717   PREFIX_EVEX_0F3A1D,
1718   PREFIX_EVEX_0F3A1E,
1719   PREFIX_EVEX_0F3A1F,
1720   PREFIX_EVEX_0F3A20,
1721   PREFIX_EVEX_0F3A21,
1722   PREFIX_EVEX_0F3A22,
1723   PREFIX_EVEX_0F3A23,
1724   PREFIX_EVEX_0F3A25,
1725   PREFIX_EVEX_0F3A26,
1726   PREFIX_EVEX_0F3A27,
1727   PREFIX_EVEX_0F3A38,
1728   PREFIX_EVEX_0F3A39,
1729   PREFIX_EVEX_0F3A3A,
1730   PREFIX_EVEX_0F3A3B,
1731   PREFIX_EVEX_0F3A3E,
1732   PREFIX_EVEX_0F3A3F,
1733   PREFIX_EVEX_0F3A42,
1734   PREFIX_EVEX_0F3A43,
1735   PREFIX_EVEX_0F3A44,
1736   PREFIX_EVEX_0F3A50,
1737   PREFIX_EVEX_0F3A51,
1738   PREFIX_EVEX_0F3A54,
1739   PREFIX_EVEX_0F3A55,
1740   PREFIX_EVEX_0F3A56,
1741   PREFIX_EVEX_0F3A57,
1742   PREFIX_EVEX_0F3A66,
1743   PREFIX_EVEX_0F3A67,
1744   PREFIX_EVEX_0F3A70,
1745   PREFIX_EVEX_0F3A71,
1746   PREFIX_EVEX_0F3A72,
1747   PREFIX_EVEX_0F3A73,
1748   PREFIX_EVEX_0F3ACE,
1749   PREFIX_EVEX_0F3ACF
1750 };
1751
1752 enum
1753 {
1754   X86_64_06 = 0,
1755   X86_64_07,
1756   X86_64_0D,
1757   X86_64_16,
1758   X86_64_17,
1759   X86_64_1E,
1760   X86_64_1F,
1761   X86_64_27,
1762   X86_64_2F,
1763   X86_64_37,
1764   X86_64_3F,
1765   X86_64_60,
1766   X86_64_61,
1767   X86_64_62,
1768   X86_64_63,
1769   X86_64_6D,
1770   X86_64_6F,
1771   X86_64_82,
1772   X86_64_9A,
1773   X86_64_C4,
1774   X86_64_C5,
1775   X86_64_CE,
1776   X86_64_D4,
1777   X86_64_D5,
1778   X86_64_E8,
1779   X86_64_E9,
1780   X86_64_EA,
1781   X86_64_0F01_REG_0,
1782   X86_64_0F01_REG_1,
1783   X86_64_0F01_REG_2,
1784   X86_64_0F01_REG_3
1785 };
1786
1787 enum
1788 {
1789   THREE_BYTE_0F38 = 0,
1790   THREE_BYTE_0F3A
1791 };
1792
1793 enum
1794 {
1795   XOP_08 = 0,
1796   XOP_09,
1797   XOP_0A
1798 };
1799
1800 enum
1801 {
1802   VEX_0F = 0,
1803   VEX_0F38,
1804   VEX_0F3A
1805 };
1806
1807 enum
1808 {
1809   EVEX_0F = 0,
1810   EVEX_0F38,
1811   EVEX_0F3A
1812 };
1813
1814 enum
1815 {
1816   VEX_LEN_0F12_P_0_M_0 = 0,
1817   VEX_LEN_0F12_P_0_M_1,
1818   VEX_LEN_0F12_P_2,
1819   VEX_LEN_0F13_M_0,
1820   VEX_LEN_0F16_P_0_M_0,
1821   VEX_LEN_0F16_P_0_M_1,
1822   VEX_LEN_0F16_P_2,
1823   VEX_LEN_0F17_M_0,
1824   VEX_LEN_0F2A_P_1,
1825   VEX_LEN_0F2A_P_3,
1826   VEX_LEN_0F2C_P_1,
1827   VEX_LEN_0F2C_P_3,
1828   VEX_LEN_0F2D_P_1,
1829   VEX_LEN_0F2D_P_3,
1830   VEX_LEN_0F41_P_0,
1831   VEX_LEN_0F41_P_2,
1832   VEX_LEN_0F42_P_0,
1833   VEX_LEN_0F42_P_2,
1834   VEX_LEN_0F44_P_0,
1835   VEX_LEN_0F44_P_2,
1836   VEX_LEN_0F45_P_0,
1837   VEX_LEN_0F45_P_2,
1838   VEX_LEN_0F46_P_0,
1839   VEX_LEN_0F46_P_2,
1840   VEX_LEN_0F47_P_0,
1841   VEX_LEN_0F47_P_2,
1842   VEX_LEN_0F4A_P_0,
1843   VEX_LEN_0F4A_P_2,
1844   VEX_LEN_0F4B_P_0,
1845   VEX_LEN_0F4B_P_2,
1846   VEX_LEN_0F6E_P_2,
1847   VEX_LEN_0F77_P_0,
1848   VEX_LEN_0F7E_P_1,
1849   VEX_LEN_0F7E_P_2,
1850   VEX_LEN_0F90_P_0,
1851   VEX_LEN_0F90_P_2,
1852   VEX_LEN_0F91_P_0,
1853   VEX_LEN_0F91_P_2,
1854   VEX_LEN_0F92_P_0,
1855   VEX_LEN_0F92_P_2,
1856   VEX_LEN_0F92_P_3,
1857   VEX_LEN_0F93_P_0,
1858   VEX_LEN_0F93_P_2,
1859   VEX_LEN_0F93_P_3,
1860   VEX_LEN_0F98_P_0,
1861   VEX_LEN_0F98_P_2,
1862   VEX_LEN_0F99_P_0,
1863   VEX_LEN_0F99_P_2,
1864   VEX_LEN_0FAE_R_2_M_0,
1865   VEX_LEN_0FAE_R_3_M_0,
1866   VEX_LEN_0FC4_P_2,
1867   VEX_LEN_0FC5_P_2,
1868   VEX_LEN_0FD6_P_2,
1869   VEX_LEN_0FF7_P_2,
1870   VEX_LEN_0F3816_P_2,
1871   VEX_LEN_0F3819_P_2,
1872   VEX_LEN_0F381A_P_2_M_0,
1873   VEX_LEN_0F3836_P_2,
1874   VEX_LEN_0F3841_P_2,
1875   VEX_LEN_0F385A_P_2_M_0,
1876   VEX_LEN_0F38DB_P_2,
1877   VEX_LEN_0F38F2_P_0,
1878   VEX_LEN_0F38F3_R_1_P_0,
1879   VEX_LEN_0F38F3_R_2_P_0,
1880   VEX_LEN_0F38F3_R_3_P_0,
1881   VEX_LEN_0F38F5_P_0,
1882   VEX_LEN_0F38F5_P_1,
1883   VEX_LEN_0F38F5_P_3,
1884   VEX_LEN_0F38F6_P_3,
1885   VEX_LEN_0F38F7_P_0,
1886   VEX_LEN_0F38F7_P_1,
1887   VEX_LEN_0F38F7_P_2,
1888   VEX_LEN_0F38F7_P_3,
1889   VEX_LEN_0F3A00_P_2,
1890   VEX_LEN_0F3A01_P_2,
1891   VEX_LEN_0F3A06_P_2,
1892   VEX_LEN_0F3A14_P_2,
1893   VEX_LEN_0F3A15_P_2,
1894   VEX_LEN_0F3A16_P_2,
1895   VEX_LEN_0F3A17_P_2,
1896   VEX_LEN_0F3A18_P_2,
1897   VEX_LEN_0F3A19_P_2,
1898   VEX_LEN_0F3A20_P_2,
1899   VEX_LEN_0F3A21_P_2,
1900   VEX_LEN_0F3A22_P_2,
1901   VEX_LEN_0F3A30_P_2,
1902   VEX_LEN_0F3A31_P_2,
1903   VEX_LEN_0F3A32_P_2,
1904   VEX_LEN_0F3A33_P_2,
1905   VEX_LEN_0F3A38_P_2,
1906   VEX_LEN_0F3A39_P_2,
1907   VEX_LEN_0F3A41_P_2,
1908   VEX_LEN_0F3A46_P_2,
1909   VEX_LEN_0F3A60_P_2,
1910   VEX_LEN_0F3A61_P_2,
1911   VEX_LEN_0F3A62_P_2,
1912   VEX_LEN_0F3A63_P_2,
1913   VEX_LEN_0F3A6A_P_2,
1914   VEX_LEN_0F3A6B_P_2,
1915   VEX_LEN_0F3A6E_P_2,
1916   VEX_LEN_0F3A6F_P_2,
1917   VEX_LEN_0F3A7A_P_2,
1918   VEX_LEN_0F3A7B_P_2,
1919   VEX_LEN_0F3A7E_P_2,
1920   VEX_LEN_0F3A7F_P_2,
1921   VEX_LEN_0F3ADF_P_2,
1922   VEX_LEN_0F3AF0_P_3,
1923   VEX_LEN_0FXOP_08_CC,
1924   VEX_LEN_0FXOP_08_CD,
1925   VEX_LEN_0FXOP_08_CE,
1926   VEX_LEN_0FXOP_08_CF,
1927   VEX_LEN_0FXOP_08_EC,
1928   VEX_LEN_0FXOP_08_ED,
1929   VEX_LEN_0FXOP_08_EE,
1930   VEX_LEN_0FXOP_08_EF,
1931   VEX_LEN_0FXOP_09_80,
1932   VEX_LEN_0FXOP_09_81
1933 };
1934
1935 enum
1936 {
1937   EVEX_LEN_0F6E_P_2 = 0,
1938   EVEX_LEN_0F7E_P_1,
1939   EVEX_LEN_0F7E_P_2,
1940   EVEX_LEN_0FD6_P_2,
1941   EVEX_LEN_0F3819_P_2_W_0,
1942   EVEX_LEN_0F3819_P_2_W_1,
1943   EVEX_LEN_0F381A_P_2_W_0,
1944   EVEX_LEN_0F381A_P_2_W_1,
1945   EVEX_LEN_0F381B_P_2_W_0,
1946   EVEX_LEN_0F381B_P_2_W_1,
1947   EVEX_LEN_0F385A_P_2_W_0,
1948   EVEX_LEN_0F385A_P_2_W_1,
1949   EVEX_LEN_0F385B_P_2_W_0,
1950   EVEX_LEN_0F385B_P_2_W_1,
1951   EVEX_LEN_0F3A18_P_2_W_0,
1952   EVEX_LEN_0F3A18_P_2_W_1,
1953   EVEX_LEN_0F3A19_P_2_W_0,
1954   EVEX_LEN_0F3A19_P_2_W_1,
1955   EVEX_LEN_0F3A1A_P_2_W_0,
1956   EVEX_LEN_0F3A1A_P_2_W_1,
1957   EVEX_LEN_0F3A1B_P_2_W_0,
1958   EVEX_LEN_0F3A1B_P_2_W_1,
1959   EVEX_LEN_0F3A23_P_2_W_0,
1960   EVEX_LEN_0F3A23_P_2_W_1,
1961   EVEX_LEN_0F3A38_P_2_W_0,
1962   EVEX_LEN_0F3A38_P_2_W_1,
1963   EVEX_LEN_0F3A39_P_2_W_0,
1964   EVEX_LEN_0F3A39_P_2_W_1,
1965   EVEX_LEN_0F3A3A_P_2_W_0,
1966   EVEX_LEN_0F3A3A_P_2_W_1,
1967   EVEX_LEN_0F3A3B_P_2_W_0,
1968   EVEX_LEN_0F3A3B_P_2_W_1,
1969   EVEX_LEN_0F3A43_P_2_W_0,
1970   EVEX_LEN_0F3A43_P_2_W_1
1971 };
1972
1973 enum
1974 {
1975   VEX_W_0F41_P_0_LEN_1 = 0,
1976   VEX_W_0F41_P_2_LEN_1,
1977   VEX_W_0F42_P_0_LEN_1,
1978   VEX_W_0F42_P_2_LEN_1,
1979   VEX_W_0F44_P_0_LEN_0,
1980   VEX_W_0F44_P_2_LEN_0,
1981   VEX_W_0F45_P_0_LEN_1,
1982   VEX_W_0F45_P_2_LEN_1,
1983   VEX_W_0F46_P_0_LEN_1,
1984   VEX_W_0F46_P_2_LEN_1,
1985   VEX_W_0F47_P_0_LEN_1,
1986   VEX_W_0F47_P_2_LEN_1,
1987   VEX_W_0F4A_P_0_LEN_1,
1988   VEX_W_0F4A_P_2_LEN_1,
1989   VEX_W_0F4B_P_0_LEN_1,
1990   VEX_W_0F4B_P_2_LEN_1,
1991   VEX_W_0F90_P_0_LEN_0,
1992   VEX_W_0F90_P_2_LEN_0,
1993   VEX_W_0F91_P_0_LEN_0,
1994   VEX_W_0F91_P_2_LEN_0,
1995   VEX_W_0F92_P_0_LEN_0,
1996   VEX_W_0F92_P_2_LEN_0,
1997   VEX_W_0F93_P_0_LEN_0,
1998   VEX_W_0F93_P_2_LEN_0,
1999   VEX_W_0F98_P_0_LEN_0,
2000   VEX_W_0F98_P_2_LEN_0,
2001   VEX_W_0F99_P_0_LEN_0,
2002   VEX_W_0F99_P_2_LEN_0,
2003   VEX_W_0F380C_P_2,
2004   VEX_W_0F380D_P_2,
2005   VEX_W_0F380E_P_2,
2006   VEX_W_0F380F_P_2,
2007   VEX_W_0F3816_P_2,
2008   VEX_W_0F3818_P_2,
2009   VEX_W_0F3819_P_2,
2010   VEX_W_0F381A_P_2_M_0,
2011   VEX_W_0F382C_P_2_M_0,
2012   VEX_W_0F382D_P_2_M_0,
2013   VEX_W_0F382E_P_2_M_0,
2014   VEX_W_0F382F_P_2_M_0,
2015   VEX_W_0F3836_P_2,
2016   VEX_W_0F3846_P_2,
2017   VEX_W_0F3858_P_2,
2018   VEX_W_0F3859_P_2,
2019   VEX_W_0F385A_P_2_M_0,
2020   VEX_W_0F3878_P_2,
2021   VEX_W_0F3879_P_2,
2022   VEX_W_0F38CF_P_2,
2023   VEX_W_0F3A00_P_2,
2024   VEX_W_0F3A01_P_2,
2025   VEX_W_0F3A02_P_2,
2026   VEX_W_0F3A04_P_2,
2027   VEX_W_0F3A05_P_2,
2028   VEX_W_0F3A06_P_2,
2029   VEX_W_0F3A18_P_2,
2030   VEX_W_0F3A19_P_2,
2031   VEX_W_0F3A30_P_2_LEN_0,
2032   VEX_W_0F3A31_P_2_LEN_0,
2033   VEX_W_0F3A32_P_2_LEN_0,
2034   VEX_W_0F3A33_P_2_LEN_0,
2035   VEX_W_0F3A38_P_2,
2036   VEX_W_0F3A39_P_2,
2037   VEX_W_0F3A46_P_2,
2038   VEX_W_0F3A48_P_2,
2039   VEX_W_0F3A49_P_2,
2040   VEX_W_0F3A4A_P_2,
2041   VEX_W_0F3A4B_P_2,
2042   VEX_W_0F3A4C_P_2,
2043   VEX_W_0F3ACE_P_2,
2044   VEX_W_0F3ACF_P_2,
2045
2046   EVEX_W_0F10_P_0,
2047   EVEX_W_0F10_P_1_M_0,
2048   EVEX_W_0F10_P_1_M_1,
2049   EVEX_W_0F10_P_2,
2050   EVEX_W_0F10_P_3_M_0,
2051   EVEX_W_0F10_P_3_M_1,
2052   EVEX_W_0F11_P_0,
2053   EVEX_W_0F11_P_1_M_0,
2054   EVEX_W_0F11_P_1_M_1,
2055   EVEX_W_0F11_P_2,
2056   EVEX_W_0F11_P_3_M_0,
2057   EVEX_W_0F11_P_3_M_1,
2058   EVEX_W_0F12_P_0_M_0,
2059   EVEX_W_0F12_P_0_M_1,
2060   EVEX_W_0F12_P_1,
2061   EVEX_W_0F12_P_2,
2062   EVEX_W_0F12_P_3,
2063   EVEX_W_0F13_P_0,
2064   EVEX_W_0F13_P_2,
2065   EVEX_W_0F14_P_0,
2066   EVEX_W_0F14_P_2,
2067   EVEX_W_0F15_P_0,
2068   EVEX_W_0F15_P_2,
2069   EVEX_W_0F16_P_0_M_0,
2070   EVEX_W_0F16_P_0_M_1,
2071   EVEX_W_0F16_P_1,
2072   EVEX_W_0F16_P_2,
2073   EVEX_W_0F17_P_0,
2074   EVEX_W_0F17_P_2,
2075   EVEX_W_0F28_P_0,
2076   EVEX_W_0F28_P_2,
2077   EVEX_W_0F29_P_0,
2078   EVEX_W_0F29_P_2,
2079   EVEX_W_0F2A_P_1,
2080   EVEX_W_0F2A_P_3,
2081   EVEX_W_0F2B_P_0,
2082   EVEX_W_0F2B_P_2,
2083   EVEX_W_0F2E_P_0,
2084   EVEX_W_0F2E_P_2,
2085   EVEX_W_0F2F_P_0,
2086   EVEX_W_0F2F_P_2,
2087   EVEX_W_0F51_P_0,
2088   EVEX_W_0F51_P_1,
2089   EVEX_W_0F51_P_2,
2090   EVEX_W_0F51_P_3,
2091   EVEX_W_0F54_P_0,
2092   EVEX_W_0F54_P_2,
2093   EVEX_W_0F55_P_0,
2094   EVEX_W_0F55_P_2,
2095   EVEX_W_0F56_P_0,
2096   EVEX_W_0F56_P_2,
2097   EVEX_W_0F57_P_0,
2098   EVEX_W_0F57_P_2,
2099   EVEX_W_0F58_P_0,
2100   EVEX_W_0F58_P_1,
2101   EVEX_W_0F58_P_2,
2102   EVEX_W_0F58_P_3,
2103   EVEX_W_0F59_P_0,
2104   EVEX_W_0F59_P_1,
2105   EVEX_W_0F59_P_2,
2106   EVEX_W_0F59_P_3,
2107   EVEX_W_0F5A_P_0,
2108   EVEX_W_0F5A_P_1,
2109   EVEX_W_0F5A_P_2,
2110   EVEX_W_0F5A_P_3,
2111   EVEX_W_0F5B_P_0,
2112   EVEX_W_0F5B_P_1,
2113   EVEX_W_0F5B_P_2,
2114   EVEX_W_0F5C_P_0,
2115   EVEX_W_0F5C_P_1,
2116   EVEX_W_0F5C_P_2,
2117   EVEX_W_0F5C_P_3,
2118   EVEX_W_0F5D_P_0,
2119   EVEX_W_0F5D_P_1,
2120   EVEX_W_0F5D_P_2,
2121   EVEX_W_0F5D_P_3,
2122   EVEX_W_0F5E_P_0,
2123   EVEX_W_0F5E_P_1,
2124   EVEX_W_0F5E_P_2,
2125   EVEX_W_0F5E_P_3,
2126   EVEX_W_0F5F_P_0,
2127   EVEX_W_0F5F_P_1,
2128   EVEX_W_0F5F_P_2,
2129   EVEX_W_0F5F_P_3,
2130   EVEX_W_0F62_P_2,
2131   EVEX_W_0F66_P_2,
2132   EVEX_W_0F6A_P_2,
2133   EVEX_W_0F6B_P_2,
2134   EVEX_W_0F6C_P_2,
2135   EVEX_W_0F6D_P_2,
2136   EVEX_W_0F6F_P_1,
2137   EVEX_W_0F6F_P_2,
2138   EVEX_W_0F6F_P_3,
2139   EVEX_W_0F70_P_2,
2140   EVEX_W_0F72_R_2_P_2,
2141   EVEX_W_0F72_R_6_P_2,
2142   EVEX_W_0F73_R_2_P_2,
2143   EVEX_W_0F73_R_6_P_2,
2144   EVEX_W_0F76_P_2,
2145   EVEX_W_0F78_P_0,
2146   EVEX_W_0F78_P_2,
2147   EVEX_W_0F79_P_0,
2148   EVEX_W_0F79_P_2,
2149   EVEX_W_0F7A_P_1,
2150   EVEX_W_0F7A_P_2,
2151   EVEX_W_0F7A_P_3,
2152   EVEX_W_0F7B_P_1,
2153   EVEX_W_0F7B_P_2,
2154   EVEX_W_0F7B_P_3,
2155   EVEX_W_0F7E_P_1,
2156   EVEX_W_0F7F_P_1,
2157   EVEX_W_0F7F_P_2,
2158   EVEX_W_0F7F_P_3,
2159   EVEX_W_0FC2_P_0,
2160   EVEX_W_0FC2_P_1,
2161   EVEX_W_0FC2_P_2,
2162   EVEX_W_0FC2_P_3,
2163   EVEX_W_0FC6_P_0,
2164   EVEX_W_0FC6_P_2,
2165   EVEX_W_0FD2_P_2,
2166   EVEX_W_0FD3_P_2,
2167   EVEX_W_0FD4_P_2,
2168   EVEX_W_0FD6_P_2,
2169   EVEX_W_0FE6_P_1,
2170   EVEX_W_0FE6_P_2,
2171   EVEX_W_0FE6_P_3,
2172   EVEX_W_0FE7_P_2,
2173   EVEX_W_0FF2_P_2,
2174   EVEX_W_0FF3_P_2,
2175   EVEX_W_0FF4_P_2,
2176   EVEX_W_0FFA_P_2,
2177   EVEX_W_0FFB_P_2,
2178   EVEX_W_0FFE_P_2,
2179   EVEX_W_0F380C_P_2,
2180   EVEX_W_0F380D_P_2,
2181   EVEX_W_0F3810_P_1,
2182   EVEX_W_0F3810_P_2,
2183   EVEX_W_0F3811_P_1,
2184   EVEX_W_0F3811_P_2,
2185   EVEX_W_0F3812_P_1,
2186   EVEX_W_0F3812_P_2,
2187   EVEX_W_0F3813_P_1,
2188   EVEX_W_0F3813_P_2,
2189   EVEX_W_0F3814_P_1,
2190   EVEX_W_0F3815_P_1,
2191   EVEX_W_0F3818_P_2,
2192   EVEX_W_0F3819_P_2,
2193   EVEX_W_0F381A_P_2,
2194   EVEX_W_0F381B_P_2,
2195   EVEX_W_0F381E_P_2,
2196   EVEX_W_0F381F_P_2,
2197   EVEX_W_0F3820_P_1,
2198   EVEX_W_0F3821_P_1,
2199   EVEX_W_0F3822_P_1,
2200   EVEX_W_0F3823_P_1,
2201   EVEX_W_0F3824_P_1,
2202   EVEX_W_0F3825_P_1,
2203   EVEX_W_0F3825_P_2,
2204   EVEX_W_0F3826_P_1,
2205   EVEX_W_0F3826_P_2,
2206   EVEX_W_0F3828_P_1,
2207   EVEX_W_0F3828_P_2,
2208   EVEX_W_0F3829_P_1,
2209   EVEX_W_0F3829_P_2,
2210   EVEX_W_0F382A_P_1,
2211   EVEX_W_0F382A_P_2,
2212   EVEX_W_0F382B_P_2,
2213   EVEX_W_0F3830_P_1,
2214   EVEX_W_0F3831_P_1,
2215   EVEX_W_0F3832_P_1,
2216   EVEX_W_0F3833_P_1,
2217   EVEX_W_0F3834_P_1,
2218   EVEX_W_0F3835_P_1,
2219   EVEX_W_0F3835_P_2,
2220   EVEX_W_0F3837_P_2,
2221   EVEX_W_0F3838_P_1,
2222   EVEX_W_0F3839_P_1,
2223   EVEX_W_0F383A_P_1,
2224   EVEX_W_0F3840_P_2,
2225   EVEX_W_0F3852_P_1,
2226   EVEX_W_0F3854_P_2,
2227   EVEX_W_0F3855_P_2,
2228   EVEX_W_0F3858_P_2,
2229   EVEX_W_0F3859_P_2,
2230   EVEX_W_0F385A_P_2,
2231   EVEX_W_0F385B_P_2,
2232   EVEX_W_0F3862_P_2,
2233   EVEX_W_0F3863_P_2,
2234   EVEX_W_0F3866_P_2,
2235   EVEX_W_0F3868_P_3,
2236   EVEX_W_0F3870_P_2,
2237   EVEX_W_0F3871_P_2,
2238   EVEX_W_0F3872_P_1,
2239   EVEX_W_0F3872_P_2,
2240   EVEX_W_0F3872_P_3,
2241   EVEX_W_0F3873_P_2,
2242   EVEX_W_0F3875_P_2,
2243   EVEX_W_0F3878_P_2,
2244   EVEX_W_0F3879_P_2,
2245   EVEX_W_0F387A_P_2,
2246   EVEX_W_0F387B_P_2,
2247   EVEX_W_0F387D_P_2,
2248   EVEX_W_0F3883_P_2,
2249   EVEX_W_0F388D_P_2,
2250   EVEX_W_0F3891_P_2,
2251   EVEX_W_0F3893_P_2,
2252   EVEX_W_0F38A1_P_2,
2253   EVEX_W_0F38A3_P_2,
2254   EVEX_W_0F38C7_R_1_P_2,
2255   EVEX_W_0F38C7_R_2_P_2,
2256   EVEX_W_0F38C7_R_5_P_2,
2257   EVEX_W_0F38C7_R_6_P_2,
2258
2259   EVEX_W_0F3A00_P_2,
2260   EVEX_W_0F3A01_P_2,
2261   EVEX_W_0F3A04_P_2,
2262   EVEX_W_0F3A05_P_2,
2263   EVEX_W_0F3A08_P_2,
2264   EVEX_W_0F3A09_P_2,
2265   EVEX_W_0F3A0A_P_2,
2266   EVEX_W_0F3A0B_P_2,
2267   EVEX_W_0F3A18_P_2,
2268   EVEX_W_0F3A19_P_2,
2269   EVEX_W_0F3A1A_P_2,
2270   EVEX_W_0F3A1B_P_2,
2271   EVEX_W_0F3A1D_P_2,
2272   EVEX_W_0F3A21_P_2,
2273   EVEX_W_0F3A23_P_2,
2274   EVEX_W_0F3A38_P_2,
2275   EVEX_W_0F3A39_P_2,
2276   EVEX_W_0F3A3A_P_2,
2277   EVEX_W_0F3A3B_P_2,
2278   EVEX_W_0F3A3E_P_2,
2279   EVEX_W_0F3A3F_P_2,
2280   EVEX_W_0F3A42_P_2,
2281   EVEX_W_0F3A43_P_2,
2282   EVEX_W_0F3A50_P_2,
2283   EVEX_W_0F3A51_P_2,
2284   EVEX_W_0F3A56_P_2,
2285   EVEX_W_0F3A57_P_2,
2286   EVEX_W_0F3A66_P_2,
2287   EVEX_W_0F3A67_P_2,
2288   EVEX_W_0F3A70_P_2,
2289   EVEX_W_0F3A71_P_2,
2290   EVEX_W_0F3A72_P_2,
2291   EVEX_W_0F3A73_P_2,
2292   EVEX_W_0F3ACE_P_2,
2293   EVEX_W_0F3ACF_P_2
2294 };
2295
2296 typedef void (*op_rtn) (int bytemode, int sizeflag);
2297
2298 struct dis386 {
2299   const char *name;
2300   struct
2301     {
2302       op_rtn rtn;
2303       int bytemode;
2304     } op[MAX_OPERANDS];
2305   unsigned int prefix_requirement;
2306 };
2307
2308 /* Upper case letters in the instruction names here are macros.
2309    'A' => print 'b' if no register operands or suffix_always is true
2310    'B' => print 'b' if suffix_always is true
2311    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2312           size prefix
2313    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2314           suffix_always is true
2315    'E' => print 'e' if 32-bit form of jcxz
2316    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2317    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2318    'H' => print ",pt" or ",pn" branch hint
2319    'I' => honor following macro letter even in Intel mode (implemented only
2320           for some of the macro letters)
2321    'J' => print 'l'
2322    'K' => print 'd' or 'q' if rex prefix is present.
2323    'L' => print 'l' if suffix_always is true
2324    'M' => print 'r' if intel_mnemonic is false.
2325    'N' => print 'n' if instruction has no wait "prefix"
2326    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2327    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2328           or suffix_always is true.  print 'q' if rex prefix is present.
2329    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2330           is true
2331    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2332    'S' => print 'w', 'l' or 'q' if suffix_always is true
2333    'T' => print 'q' in 64bit mode if instruction has no operand size
2334           prefix and behave as 'P' otherwise
2335    'U' => print 'q' in 64bit mode if instruction has no operand size
2336           prefix and behave as 'Q' otherwise
2337    'V' => print 'q' in 64bit mode if instruction has no operand size
2338           prefix and behave as 'S' otherwise
2339    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2340    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2341    'Y' unused.
2342    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2343    '!' => change condition from true to false or from false to true.
2344    '%' => add 1 upper case letter to the macro.
2345    '^' => print 'w' or 'l' depending on operand size prefix or
2346           suffix_always is true (lcall/ljmp).
2347    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2348           on operand size prefix.
2349    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2350           has no operand size prefix for AMD64 ISA, behave as 'P'
2351           otherwise
2352
2353    2 upper case letter macros:
2354    "XY" => print 'x' or 'y' if suffix_always is true or no register
2355            operands and no broadcast.
2356    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2357            register operands and no broadcast.
2358    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2359    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2360            or suffix_always is true
2361    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2362    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2363    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2364    "LW" => print 'd', 'q' depending on the VEX.W bit
2365    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2366            an operand size prefix, or suffix_always is true.  print
2367            'q' if rex prefix is present.
2368
2369    Many of the above letters print nothing in Intel mode.  See "putop"
2370    for the details.
2371
2372    Braces '{' and '}', and vertical bars '|', indicate alternative
2373    mnemonic strings for AT&T and Intel.  */
2374
2375 static const struct dis386 dis386[] = {
2376   /* 00 */
2377   { "addB",             { Ebh1, Gb }, 0 },
2378   { "addS",             { Evh1, Gv }, 0 },
2379   { "addB",             { Gb, EbS }, 0 },
2380   { "addS",             { Gv, EvS }, 0 },
2381   { "addB",             { AL, Ib }, 0 },
2382   { "addS",             { eAX, Iv }, 0 },
2383   { X86_64_TABLE (X86_64_06) },
2384   { X86_64_TABLE (X86_64_07) },
2385   /* 08 */
2386   { "orB",              { Ebh1, Gb }, 0 },
2387   { "orS",              { Evh1, Gv }, 0 },
2388   { "orB",              { Gb, EbS }, 0 },
2389   { "orS",              { Gv, EvS }, 0 },
2390   { "orB",              { AL, Ib }, 0 },
2391   { "orS",              { eAX, Iv }, 0 },
2392   { X86_64_TABLE (X86_64_0D) },
2393   { Bad_Opcode },       /* 0x0f extended opcode escape */
2394   /* 10 */
2395   { "adcB",             { Ebh1, Gb }, 0 },
2396   { "adcS",             { Evh1, Gv }, 0 },
2397   { "adcB",             { Gb, EbS }, 0 },
2398   { "adcS",             { Gv, EvS }, 0 },
2399   { "adcB",             { AL, Ib }, 0 },
2400   { "adcS",             { eAX, Iv }, 0 },
2401   { X86_64_TABLE (X86_64_16) },
2402   { X86_64_TABLE (X86_64_17) },
2403   /* 18 */
2404   { "sbbB",             { Ebh1, Gb }, 0 },
2405   { "sbbS",             { Evh1, Gv }, 0 },
2406   { "sbbB",             { Gb, EbS }, 0 },
2407   { "sbbS",             { Gv, EvS }, 0 },
2408   { "sbbB",             { AL, Ib }, 0 },
2409   { "sbbS",             { eAX, Iv }, 0 },
2410   { X86_64_TABLE (X86_64_1E) },
2411   { X86_64_TABLE (X86_64_1F) },
2412   /* 20 */
2413   { "andB",             { Ebh1, Gb }, 0 },
2414   { "andS",             { Evh1, Gv }, 0 },
2415   { "andB",             { Gb, EbS }, 0 },
2416   { "andS",             { Gv, EvS }, 0 },
2417   { "andB",             { AL, Ib }, 0 },
2418   { "andS",             { eAX, Iv }, 0 },
2419   { Bad_Opcode },       /* SEG ES prefix */
2420   { X86_64_TABLE (X86_64_27) },
2421   /* 28 */
2422   { "subB",             { Ebh1, Gb }, 0 },
2423   { "subS",             { Evh1, Gv }, 0 },
2424   { "subB",             { Gb, EbS }, 0 },
2425   { "subS",             { Gv, EvS }, 0 },
2426   { "subB",             { AL, Ib }, 0 },
2427   { "subS",             { eAX, Iv }, 0 },
2428   { Bad_Opcode },       /* SEG CS prefix */
2429   { X86_64_TABLE (X86_64_2F) },
2430   /* 30 */
2431   { "xorB",             { Ebh1, Gb }, 0 },
2432   { "xorS",             { Evh1, Gv }, 0 },
2433   { "xorB",             { Gb, EbS }, 0 },
2434   { "xorS",             { Gv, EvS }, 0 },
2435   { "xorB",             { AL, Ib }, 0 },
2436   { "xorS",             { eAX, Iv }, 0 },
2437   { Bad_Opcode },       /* SEG SS prefix */
2438   { X86_64_TABLE (X86_64_37) },
2439   /* 38 */
2440   { "cmpB",             { Eb, Gb }, 0 },
2441   { "cmpS",             { Ev, Gv }, 0 },
2442   { "cmpB",             { Gb, EbS }, 0 },
2443   { "cmpS",             { Gv, EvS }, 0 },
2444   { "cmpB",             { AL, Ib }, 0 },
2445   { "cmpS",             { eAX, Iv }, 0 },
2446   { Bad_Opcode },       /* SEG DS prefix */
2447   { X86_64_TABLE (X86_64_3F) },
2448   /* 40 */
2449   { "inc{S|}",          { RMeAX }, 0 },
2450   { "inc{S|}",          { RMeCX }, 0 },
2451   { "inc{S|}",          { RMeDX }, 0 },
2452   { "inc{S|}",          { RMeBX }, 0 },
2453   { "inc{S|}",          { RMeSP }, 0 },
2454   { "inc{S|}",          { RMeBP }, 0 },
2455   { "inc{S|}",          { RMeSI }, 0 },
2456   { "inc{S|}",          { RMeDI }, 0 },
2457   /* 48 */
2458   { "dec{S|}",          { RMeAX }, 0 },
2459   { "dec{S|}",          { RMeCX }, 0 },
2460   { "dec{S|}",          { RMeDX }, 0 },
2461   { "dec{S|}",          { RMeBX }, 0 },
2462   { "dec{S|}",          { RMeSP }, 0 },
2463   { "dec{S|}",          { RMeBP }, 0 },
2464   { "dec{S|}",          { RMeSI }, 0 },
2465   { "dec{S|}",          { RMeDI }, 0 },
2466   /* 50 */
2467   { "pushV",            { RMrAX }, 0 },
2468   { "pushV",            { RMrCX }, 0 },
2469   { "pushV",            { RMrDX }, 0 },
2470   { "pushV",            { RMrBX }, 0 },
2471   { "pushV",            { RMrSP }, 0 },
2472   { "pushV",            { RMrBP }, 0 },
2473   { "pushV",            { RMrSI }, 0 },
2474   { "pushV",            { RMrDI }, 0 },
2475   /* 58 */
2476   { "popV",             { RMrAX }, 0 },
2477   { "popV",             { RMrCX }, 0 },
2478   { "popV",             { RMrDX }, 0 },
2479   { "popV",             { RMrBX }, 0 },
2480   { "popV",             { RMrSP }, 0 },
2481   { "popV",             { RMrBP }, 0 },
2482   { "popV",             { RMrSI }, 0 },
2483   { "popV",             { RMrDI }, 0 },
2484   /* 60 */
2485   { X86_64_TABLE (X86_64_60) },
2486   { X86_64_TABLE (X86_64_61) },
2487   { X86_64_TABLE (X86_64_62) },
2488   { X86_64_TABLE (X86_64_63) },
2489   { Bad_Opcode },       /* seg fs */
2490   { Bad_Opcode },       /* seg gs */
2491   { Bad_Opcode },       /* op size prefix */
2492   { Bad_Opcode },       /* adr size prefix */
2493   /* 68 */
2494   { "pushT",            { sIv }, 0 },
2495   { "imulS",            { Gv, Ev, Iv }, 0 },
2496   { "pushT",            { sIbT }, 0 },
2497   { "imulS",            { Gv, Ev, sIb }, 0 },
2498   { "ins{b|}",          { Ybr, indirDX }, 0 },
2499   { X86_64_TABLE (X86_64_6D) },
2500   { "outs{b|}",         { indirDXr, Xb }, 0 },
2501   { X86_64_TABLE (X86_64_6F) },
2502   /* 70 */
2503   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2504   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2505   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2506   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2507   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2508   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2509   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2510   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2511   /* 78 */
2512   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2513   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2514   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2515   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2516   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2517   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2518   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2519   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2520   /* 80 */
2521   { REG_TABLE (REG_80) },
2522   { REG_TABLE (REG_81) },
2523   { X86_64_TABLE (X86_64_82) },
2524   { REG_TABLE (REG_83) },
2525   { "testB",            { Eb, Gb }, 0 },
2526   { "testS",            { Ev, Gv }, 0 },
2527   { "xchgB",            { Ebh2, Gb }, 0 },
2528   { "xchgS",            { Evh2, Gv }, 0 },
2529   /* 88 */
2530   { "movB",             { Ebh3, Gb }, 0 },
2531   { "movS",             { Evh3, Gv }, 0 },
2532   { "movB",             { Gb, EbS }, 0 },
2533   { "movS",             { Gv, EvS }, 0 },
2534   { "movD",             { Sv, Sw }, 0 },
2535   { MOD_TABLE (MOD_8D) },
2536   { "movD",             { Sw, Sv }, 0 },
2537   { REG_TABLE (REG_8F) },
2538   /* 90 */
2539   { PREFIX_TABLE (PREFIX_90) },
2540   { "xchgS",            { RMeCX, eAX }, 0 },
2541   { "xchgS",            { RMeDX, eAX }, 0 },
2542   { "xchgS",            { RMeBX, eAX }, 0 },
2543   { "xchgS",            { RMeSP, eAX }, 0 },
2544   { "xchgS",            { RMeBP, eAX }, 0 },
2545   { "xchgS",            { RMeSI, eAX }, 0 },
2546   { "xchgS",            { RMeDI, eAX }, 0 },
2547   /* 98 */
2548   { "cW{t|}R",          { XX }, 0 },
2549   { "cR{t|}O",          { XX }, 0 },
2550   { X86_64_TABLE (X86_64_9A) },
2551   { Bad_Opcode },       /* fwait */
2552   { "pushfT",           { XX }, 0 },
2553   { "popfT",            { XX }, 0 },
2554   { "sahf",             { XX }, 0 },
2555   { "lahf",             { XX }, 0 },
2556   /* a0 */
2557   { "mov%LB",           { AL, Ob }, 0 },
2558   { "mov%LS",           { eAX, Ov }, 0 },
2559   { "mov%LB",           { Ob, AL }, 0 },
2560   { "mov%LS",           { Ov, eAX }, 0 },
2561   { "movs{b|}",         { Ybr, Xb }, 0 },
2562   { "movs{R|}",         { Yvr, Xv }, 0 },
2563   { "cmps{b|}",         { Xb, Yb }, 0 },
2564   { "cmps{R|}",         { Xv, Yv }, 0 },
2565   /* a8 */
2566   { "testB",            { AL, Ib }, 0 },
2567   { "testS",            { eAX, Iv }, 0 },
2568   { "stosB",            { Ybr, AL }, 0 },
2569   { "stosS",            { Yvr, eAX }, 0 },
2570   { "lodsB",            { ALr, Xb }, 0 },
2571   { "lodsS",            { eAXr, Xv }, 0 },
2572   { "scasB",            { AL, Yb }, 0 },
2573   { "scasS",            { eAX, Yv }, 0 },
2574   /* b0 */
2575   { "movB",             { RMAL, Ib }, 0 },
2576   { "movB",             { RMCL, Ib }, 0 },
2577   { "movB",             { RMDL, Ib }, 0 },
2578   { "movB",             { RMBL, Ib }, 0 },
2579   { "movB",             { RMAH, Ib }, 0 },
2580   { "movB",             { RMCH, Ib }, 0 },
2581   { "movB",             { RMDH, Ib }, 0 },
2582   { "movB",             { RMBH, Ib }, 0 },
2583   /* b8 */
2584   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2585   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2586   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2587   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2588   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2589   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2590   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2591   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2592   /* c0 */
2593   { REG_TABLE (REG_C0) },
2594   { REG_TABLE (REG_C1) },
2595   { "retT",             { Iw, BND }, 0 },
2596   { "retT",             { BND }, 0 },
2597   { X86_64_TABLE (X86_64_C4) },
2598   { X86_64_TABLE (X86_64_C5) },
2599   { REG_TABLE (REG_C6) },
2600   { REG_TABLE (REG_C7) },
2601   /* c8 */
2602   { "enterT",           { Iw, Ib }, 0 },
2603   { "leaveT",           { XX }, 0 },
2604   { "Jret{|f}P",        { Iw }, 0 },
2605   { "Jret{|f}P",        { XX }, 0 },
2606   { "int3",             { XX }, 0 },
2607   { "int",              { Ib }, 0 },
2608   { X86_64_TABLE (X86_64_CE) },
2609   { "iret%LP",          { XX }, 0 },
2610   /* d0 */
2611   { REG_TABLE (REG_D0) },
2612   { REG_TABLE (REG_D1) },
2613   { REG_TABLE (REG_D2) },
2614   { REG_TABLE (REG_D3) },
2615   { X86_64_TABLE (X86_64_D4) },
2616   { X86_64_TABLE (X86_64_D5) },
2617   { Bad_Opcode },
2618   { "xlat",             { DSBX }, 0 },
2619   /* d8 */
2620   { FLOAT },
2621   { FLOAT },
2622   { FLOAT },
2623   { FLOAT },
2624   { FLOAT },
2625   { FLOAT },
2626   { FLOAT },
2627   { FLOAT },
2628   /* e0 */
2629   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2630   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2631   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2632   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2633   { "inB",              { AL, Ib }, 0 },
2634   { "inG",              { zAX, Ib }, 0 },
2635   { "outB",             { Ib, AL }, 0 },
2636   { "outG",             { Ib, zAX }, 0 },
2637   /* e8 */
2638   { X86_64_TABLE (X86_64_E8) },
2639   { X86_64_TABLE (X86_64_E9) },
2640   { X86_64_TABLE (X86_64_EA) },
2641   { "jmp",              { Jb, BND }, 0 },
2642   { "inB",              { AL, indirDX }, 0 },
2643   { "inG",              { zAX, indirDX }, 0 },
2644   { "outB",             { indirDX, AL }, 0 },
2645   { "outG",             { indirDX, zAX }, 0 },
2646   /* f0 */
2647   { Bad_Opcode },       /* lock prefix */
2648   { "icebp",            { XX }, 0 },
2649   { Bad_Opcode },       /* repne */
2650   { Bad_Opcode },       /* repz */
2651   { "hlt",              { XX }, 0 },
2652   { "cmc",              { XX }, 0 },
2653   { REG_TABLE (REG_F6) },
2654   { REG_TABLE (REG_F7) },
2655   /* f8 */
2656   { "clc",              { XX }, 0 },
2657   { "stc",              { XX }, 0 },
2658   { "cli",              { XX }, 0 },
2659   { "sti",              { XX }, 0 },
2660   { "cld",              { XX }, 0 },
2661   { "std",              { XX }, 0 },
2662   { REG_TABLE (REG_FE) },
2663   { REG_TABLE (REG_FF) },
2664 };
2665
2666 static const struct dis386 dis386_twobyte[] = {
2667   /* 00 */
2668   { REG_TABLE (REG_0F00 ) },
2669   { REG_TABLE (REG_0F01 ) },
2670   { "larS",             { Gv, Ew }, 0 },
2671   { "lslS",             { Gv, Ew }, 0 },
2672   { Bad_Opcode },
2673   { "syscall",          { XX }, 0 },
2674   { "clts",             { XX }, 0 },
2675   { "sysret%LP",                { XX }, 0 },
2676   /* 08 */
2677   { "invd",             { XX }, 0 },
2678   { PREFIX_TABLE (PREFIX_0F09) },
2679   { Bad_Opcode },
2680   { "ud2",              { XX }, 0 },
2681   { Bad_Opcode },
2682   { REG_TABLE (REG_0F0D) },
2683   { "femms",            { XX }, 0 },
2684   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2685   /* 10 */
2686   { PREFIX_TABLE (PREFIX_0F10) },
2687   { PREFIX_TABLE (PREFIX_0F11) },
2688   { PREFIX_TABLE (PREFIX_0F12) },
2689   { MOD_TABLE (MOD_0F13) },
2690   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2691   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2692   { PREFIX_TABLE (PREFIX_0F16) },
2693   { MOD_TABLE (MOD_0F17) },
2694   /* 18 */
2695   { REG_TABLE (REG_0F18) },
2696   { "nopQ",             { Ev }, 0 },
2697   { PREFIX_TABLE (PREFIX_0F1A) },
2698   { PREFIX_TABLE (PREFIX_0F1B) },
2699   { PREFIX_TABLE (PREFIX_0F1C) },
2700   { "nopQ",             { Ev }, 0 },
2701   { PREFIX_TABLE (PREFIX_0F1E) },
2702   { "nopQ",             { Ev }, 0 },
2703   /* 20 */
2704   { "movZ",             { Rm, Cm }, 0 },
2705   { "movZ",             { Rm, Dm }, 0 },
2706   { "movZ",             { Cm, Rm }, 0 },
2707   { "movZ",             { Dm, Rm }, 0 },
2708   { MOD_TABLE (MOD_0F24) },
2709   { Bad_Opcode },
2710   { MOD_TABLE (MOD_0F26) },
2711   { Bad_Opcode },
2712   /* 28 */
2713   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2714   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2715   { PREFIX_TABLE (PREFIX_0F2A) },
2716   { PREFIX_TABLE (PREFIX_0F2B) },
2717   { PREFIX_TABLE (PREFIX_0F2C) },
2718   { PREFIX_TABLE (PREFIX_0F2D) },
2719   { PREFIX_TABLE (PREFIX_0F2E) },
2720   { PREFIX_TABLE (PREFIX_0F2F) },
2721   /* 30 */
2722   { "wrmsr",            { XX }, 0 },
2723   { "rdtsc",            { XX }, 0 },
2724   { "rdmsr",            { XX }, 0 },
2725   { "rdpmc",            { XX }, 0 },
2726   { "sysenter",         { XX }, 0 },
2727   { "sysexit",          { XX }, 0 },
2728   { Bad_Opcode },
2729   { "getsec",           { XX }, 0 },
2730   /* 38 */
2731   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2732   { Bad_Opcode },
2733   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2734   { Bad_Opcode },
2735   { Bad_Opcode },
2736   { Bad_Opcode },
2737   { Bad_Opcode },
2738   { Bad_Opcode },
2739   /* 40 */
2740   { "cmovoS",           { Gv, Ev }, 0 },
2741   { "cmovnoS",          { Gv, Ev }, 0 },
2742   { "cmovbS",           { Gv, Ev }, 0 },
2743   { "cmovaeS",          { Gv, Ev }, 0 },
2744   { "cmoveS",           { Gv, Ev }, 0 },
2745   { "cmovneS",          { Gv, Ev }, 0 },
2746   { "cmovbeS",          { Gv, Ev }, 0 },
2747   { "cmovaS",           { Gv, Ev }, 0 },
2748   /* 48 */
2749   { "cmovsS",           { Gv, Ev }, 0 },
2750   { "cmovnsS",          { Gv, Ev }, 0 },
2751   { "cmovpS",           { Gv, Ev }, 0 },
2752   { "cmovnpS",          { Gv, Ev }, 0 },
2753   { "cmovlS",           { Gv, Ev }, 0 },
2754   { "cmovgeS",          { Gv, Ev }, 0 },
2755   { "cmovleS",          { Gv, Ev }, 0 },
2756   { "cmovgS",           { Gv, Ev }, 0 },
2757   /* 50 */
2758   { MOD_TABLE (MOD_0F51) },
2759   { PREFIX_TABLE (PREFIX_0F51) },
2760   { PREFIX_TABLE (PREFIX_0F52) },
2761   { PREFIX_TABLE (PREFIX_0F53) },
2762   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2763   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2764   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2765   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2766   /* 58 */
2767   { PREFIX_TABLE (PREFIX_0F58) },
2768   { PREFIX_TABLE (PREFIX_0F59) },
2769   { PREFIX_TABLE (PREFIX_0F5A) },
2770   { PREFIX_TABLE (PREFIX_0F5B) },
2771   { PREFIX_TABLE (PREFIX_0F5C) },
2772   { PREFIX_TABLE (PREFIX_0F5D) },
2773   { PREFIX_TABLE (PREFIX_0F5E) },
2774   { PREFIX_TABLE (PREFIX_0F5F) },
2775   /* 60 */
2776   { PREFIX_TABLE (PREFIX_0F60) },
2777   { PREFIX_TABLE (PREFIX_0F61) },
2778   { PREFIX_TABLE (PREFIX_0F62) },
2779   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2780   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2781   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2782   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2783   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2784   /* 68 */
2785   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2786   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2787   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2788   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2789   { PREFIX_TABLE (PREFIX_0F6C) },
2790   { PREFIX_TABLE (PREFIX_0F6D) },
2791   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2792   { PREFIX_TABLE (PREFIX_0F6F) },
2793   /* 70 */
2794   { PREFIX_TABLE (PREFIX_0F70) },
2795   { REG_TABLE (REG_0F71) },
2796   { REG_TABLE (REG_0F72) },
2797   { REG_TABLE (REG_0F73) },
2798   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2799   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2800   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2801   { "emms",             { XX }, PREFIX_OPCODE },
2802   /* 78 */
2803   { PREFIX_TABLE (PREFIX_0F78) },
2804   { PREFIX_TABLE (PREFIX_0F79) },
2805   { Bad_Opcode },
2806   { Bad_Opcode },
2807   { PREFIX_TABLE (PREFIX_0F7C) },
2808   { PREFIX_TABLE (PREFIX_0F7D) },
2809   { PREFIX_TABLE (PREFIX_0F7E) },
2810   { PREFIX_TABLE (PREFIX_0F7F) },
2811   /* 80 */
2812   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2813   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2814   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2815   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2816   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2817   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2818   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2819   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2820   /* 88 */
2821   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2822   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2823   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2824   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2825   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2826   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2827   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2828   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2829   /* 90 */
2830   { "seto",             { Eb }, 0 },
2831   { "setno",            { Eb }, 0 },
2832   { "setb",             { Eb }, 0 },
2833   { "setae",            { Eb }, 0 },
2834   { "sete",             { Eb }, 0 },
2835   { "setne",            { Eb }, 0 },
2836   { "setbe",            { Eb }, 0 },
2837   { "seta",             { Eb }, 0 },
2838   /* 98 */
2839   { "sets",             { Eb }, 0 },
2840   { "setns",            { Eb }, 0 },
2841   { "setp",             { Eb }, 0 },
2842   { "setnp",            { Eb }, 0 },
2843   { "setl",             { Eb }, 0 },
2844   { "setge",            { Eb }, 0 },
2845   { "setle",            { Eb }, 0 },
2846   { "setg",             { Eb }, 0 },
2847   /* a0 */
2848   { "pushT",            { fs }, 0 },
2849   { "popT",             { fs }, 0 },
2850   { "cpuid",            { XX }, 0 },
2851   { "btS",              { Ev, Gv }, 0 },
2852   { "shldS",            { Ev, Gv, Ib }, 0 },
2853   { "shldS",            { Ev, Gv, CL }, 0 },
2854   { REG_TABLE (REG_0FA6) },
2855   { REG_TABLE (REG_0FA7) },
2856   /* a8 */
2857   { "pushT",            { gs }, 0 },
2858   { "popT",             { gs }, 0 },
2859   { "rsm",              { XX }, 0 },
2860   { "btsS",             { Evh1, Gv }, 0 },
2861   { "shrdS",            { Ev, Gv, Ib }, 0 },
2862   { "shrdS",            { Ev, Gv, CL }, 0 },
2863   { REG_TABLE (REG_0FAE) },
2864   { "imulS",            { Gv, Ev }, 0 },
2865   /* b0 */
2866   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2867   { "cmpxchgS",         { Evh1, Gv }, 0 },
2868   { MOD_TABLE (MOD_0FB2) },
2869   { "btrS",             { Evh1, Gv }, 0 },
2870   { MOD_TABLE (MOD_0FB4) },
2871   { MOD_TABLE (MOD_0FB5) },
2872   { "movz{bR|x}",       { Gv, Eb }, 0 },
2873   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2874   /* b8 */
2875   { PREFIX_TABLE (PREFIX_0FB8) },
2876   { "ud1S",             { Gv, Ev }, 0 },
2877   { REG_TABLE (REG_0FBA) },
2878   { "btcS",             { Evh1, Gv }, 0 },
2879   { PREFIX_TABLE (PREFIX_0FBC) },
2880   { PREFIX_TABLE (PREFIX_0FBD) },
2881   { "movs{bR|x}",       { Gv, Eb }, 0 },
2882   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2883   /* c0 */
2884   { "xaddB",            { Ebh1, Gb }, 0 },
2885   { "xaddS",            { Evh1, Gv }, 0 },
2886   { PREFIX_TABLE (PREFIX_0FC2) },
2887   { MOD_TABLE (MOD_0FC3) },
2888   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2889   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2890   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2891   { REG_TABLE (REG_0FC7) },
2892   /* c8 */
2893   { "bswap",            { RMeAX }, 0 },
2894   { "bswap",            { RMeCX }, 0 },
2895   { "bswap",            { RMeDX }, 0 },
2896   { "bswap",            { RMeBX }, 0 },
2897   { "bswap",            { RMeSP }, 0 },
2898   { "bswap",            { RMeBP }, 0 },
2899   { "bswap",            { RMeSI }, 0 },
2900   { "bswap",            { RMeDI }, 0 },
2901   /* d0 */
2902   { PREFIX_TABLE (PREFIX_0FD0) },
2903   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2904   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2905   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2906   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2907   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2908   { PREFIX_TABLE (PREFIX_0FD6) },
2909   { MOD_TABLE (MOD_0FD7) },
2910   /* d8 */
2911   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2912   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2913   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2914   { "pand",             { MX, EM }, PREFIX_OPCODE },
2915   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2916   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2917   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2918   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2919   /* e0 */
2920   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2921   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2922   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2923   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2924   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2925   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2926   { PREFIX_TABLE (PREFIX_0FE6) },
2927   { PREFIX_TABLE (PREFIX_0FE7) },
2928   /* e8 */
2929   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2930   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2931   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2932   { "por",              { MX, EM }, PREFIX_OPCODE },
2933   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2934   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2935   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2936   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2937   /* f0 */
2938   { PREFIX_TABLE (PREFIX_0FF0) },
2939   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2940   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2941   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2942   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2943   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2944   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2945   { PREFIX_TABLE (PREFIX_0FF7) },
2946   /* f8 */
2947   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2948   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2949   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2950   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2951   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2952   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2953   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2954   { "ud0S",             { Gv, Ev }, 0 },
2955 };
2956
2957 static const unsigned char onebyte_has_modrm[256] = {
2958   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2959   /*       -------------------------------        */
2960   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2961   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2962   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2963   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2964   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2965   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2966   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2967   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2968   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2969   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2970   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2971   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2972   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2973   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2974   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2975   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2976   /*       -------------------------------        */
2977   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2978 };
2979
2980 static const unsigned char twobyte_has_modrm[256] = {
2981   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2982   /*       -------------------------------        */
2983   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2984   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2985   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2986   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2987   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2988   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2989   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2990   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2991   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2992   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2993   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2994   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2995   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2996   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2997   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2998   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2999   /*       -------------------------------        */
3000   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3001 };
3002
3003 static char obuf[100];
3004 static char *obufp;
3005 static char *mnemonicendp;
3006 static char scratchbuf[100];
3007 static unsigned char *start_codep;
3008 static unsigned char *insn_codep;
3009 static unsigned char *codep;
3010 static unsigned char *end_codep;
3011 static int last_lock_prefix;
3012 static int last_repz_prefix;
3013 static int last_repnz_prefix;
3014 static int last_data_prefix;
3015 static int last_addr_prefix;
3016 static int last_rex_prefix;
3017 static int last_seg_prefix;
3018 static int fwait_prefix;
3019 /* The active segment register prefix.  */
3020 static int active_seg_prefix;
3021 #define MAX_CODE_LENGTH 15
3022 /* We can up to 14 prefixes since the maximum instruction length is
3023    15bytes.  */
3024 static int all_prefixes[MAX_CODE_LENGTH - 1];
3025 static disassemble_info *the_info;
3026 static struct
3027   {
3028     int mod;
3029     int reg;
3030     int rm;
3031   }
3032 modrm;
3033 static unsigned char need_modrm;
3034 static struct
3035   {
3036     int scale;
3037     int index;
3038     int base;
3039   }
3040 sib;
3041 static struct
3042   {
3043     int register_specifier;
3044     int length;
3045     int prefix;
3046     int w;
3047     int evex;
3048     int r;
3049     int v;
3050     int mask_register_specifier;
3051     int zeroing;
3052     int ll;
3053     int b;
3054   }
3055 vex;
3056 static unsigned char need_vex;
3057 static unsigned char need_vex_reg;
3058 static unsigned char vex_w_done;
3059
3060 struct op
3061   {
3062     const char *name;
3063     unsigned int len;
3064   };
3065
3066 /* If we are accessing mod/rm/reg without need_modrm set, then the
3067    values are stale.  Hitting this abort likely indicates that you
3068    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3069 #define MODRM_CHECK  if (!need_modrm) abort ()
3070
3071 static const char **names64;
3072 static const char **names32;
3073 static const char **names16;
3074 static const char **names8;
3075 static const char **names8rex;
3076 static const char **names_seg;
3077 static const char *index64;
3078 static const char *index32;
3079 static const char **index16;
3080 static const char **names_bnd;
3081
3082 static const char *intel_names64[] = {
3083   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3084   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3085 };
3086 static const char *intel_names32[] = {
3087   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3088   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3089 };
3090 static const char *intel_names16[] = {
3091   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3092   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3093 };
3094 static const char *intel_names8[] = {
3095   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3096 };
3097 static const char *intel_names8rex[] = {
3098   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3099   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3100 };
3101 static const char *intel_names_seg[] = {
3102   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3103 };
3104 static const char *intel_index64 = "riz";
3105 static const char *intel_index32 = "eiz";
3106 static const char *intel_index16[] = {
3107   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3108 };
3109
3110 static const char *att_names64[] = {
3111   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3112   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3113 };
3114 static const char *att_names32[] = {
3115   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3116   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3117 };
3118 static const char *att_names16[] = {
3119   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3120   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3121 };
3122 static const char *att_names8[] = {
3123   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3124 };
3125 static const char *att_names8rex[] = {
3126   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3127   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3128 };
3129 static const char *att_names_seg[] = {
3130   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3131 };
3132 static const char *att_index64 = "%riz";
3133 static const char *att_index32 = "%eiz";
3134 static const char *att_index16[] = {
3135   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3136 };
3137
3138 static const char **names_mm;
3139 static const char *intel_names_mm[] = {
3140   "mm0", "mm1", "mm2", "mm3",
3141   "mm4", "mm5", "mm6", "mm7"
3142 };
3143 static const char *att_names_mm[] = {
3144   "%mm0", "%mm1", "%mm2", "%mm3",
3145   "%mm4", "%mm5", "%mm6", "%mm7"
3146 };
3147
3148 static const char *intel_names_bnd[] = {
3149   "bnd0", "bnd1", "bnd2", "bnd3"
3150 };
3151
3152 static const char *att_names_bnd[] = {
3153   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3154 };
3155
3156 static const char **names_xmm;
3157 static const char *intel_names_xmm[] = {
3158   "xmm0", "xmm1", "xmm2", "xmm3",
3159   "xmm4", "xmm5", "xmm6", "xmm7",
3160   "xmm8", "xmm9", "xmm10", "xmm11",
3161   "xmm12", "xmm13", "xmm14", "xmm15",
3162   "xmm16", "xmm17", "xmm18", "xmm19",
3163   "xmm20", "xmm21", "xmm22", "xmm23",
3164   "xmm24", "xmm25", "xmm26", "xmm27",
3165   "xmm28", "xmm29", "xmm30", "xmm31"
3166 };
3167 static const char *att_names_xmm[] = {
3168   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3169   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3170   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3171   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3172   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3173   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3174   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3175   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3176 };
3177
3178 static const char **names_ymm;
3179 static const char *intel_names_ymm[] = {
3180   "ymm0", "ymm1", "ymm2", "ymm3",
3181   "ymm4", "ymm5", "ymm6", "ymm7",
3182   "ymm8", "ymm9", "ymm10", "ymm11",
3183   "ymm12", "ymm13", "ymm14", "ymm15",
3184   "ymm16", "ymm17", "ymm18", "ymm19",
3185   "ymm20", "ymm21", "ymm22", "ymm23",
3186   "ymm24", "ymm25", "ymm26", "ymm27",
3187   "ymm28", "ymm29", "ymm30", "ymm31"
3188 };
3189 static const char *att_names_ymm[] = {
3190   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3191   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3192   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3193   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3194   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3195   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3196   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3197   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3198 };
3199
3200 static const char **names_zmm;
3201 static const char *intel_names_zmm[] = {
3202   "zmm0", "zmm1", "zmm2", "zmm3",
3203   "zmm4", "zmm5", "zmm6", "zmm7",
3204   "zmm8", "zmm9", "zmm10", "zmm11",
3205   "zmm12", "zmm13", "zmm14", "zmm15",
3206   "zmm16", "zmm17", "zmm18", "zmm19",
3207   "zmm20", "zmm21", "zmm22", "zmm23",
3208   "zmm24", "zmm25", "zmm26", "zmm27",
3209   "zmm28", "zmm29", "zmm30", "zmm31"
3210 };
3211 static const char *att_names_zmm[] = {
3212   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3213   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3214   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3215   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3216   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3217   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3218   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3219   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3220 };
3221
3222 static const char **names_mask;
3223 static const char *intel_names_mask[] = {
3224   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3225 };
3226 static const char *att_names_mask[] = {
3227   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3228 };
3229
3230 static const char *names_rounding[] =
3231 {
3232   "{rn-sae}",
3233   "{rd-sae}",
3234   "{ru-sae}",
3235   "{rz-sae}"
3236 };
3237
3238 static const struct dis386 reg_table[][8] = {
3239   /* REG_80 */
3240   {
3241     { "addA",   { Ebh1, Ib }, 0 },
3242     { "orA",    { Ebh1, Ib }, 0 },
3243     { "adcA",   { Ebh1, Ib }, 0 },
3244     { "sbbA",   { Ebh1, Ib }, 0 },
3245     { "andA",   { Ebh1, Ib }, 0 },
3246     { "subA",   { Ebh1, Ib }, 0 },
3247     { "xorA",   { Ebh1, Ib }, 0 },
3248     { "cmpA",   { Eb, Ib }, 0 },
3249   },
3250   /* REG_81 */
3251   {
3252     { "addQ",   { Evh1, Iv }, 0 },
3253     { "orQ",    { Evh1, Iv }, 0 },
3254     { "adcQ",   { Evh1, Iv }, 0 },
3255     { "sbbQ",   { Evh1, Iv }, 0 },
3256     { "andQ",   { Evh1, Iv }, 0 },
3257     { "subQ",   { Evh1, Iv }, 0 },
3258     { "xorQ",   { Evh1, Iv }, 0 },
3259     { "cmpQ",   { Ev, Iv }, 0 },
3260   },
3261   /* REG_83 */
3262   {
3263     { "addQ",   { Evh1, sIb }, 0 },
3264     { "orQ",    { Evh1, sIb }, 0 },
3265     { "adcQ",   { Evh1, sIb }, 0 },
3266     { "sbbQ",   { Evh1, sIb }, 0 },
3267     { "andQ",   { Evh1, sIb }, 0 },
3268     { "subQ",   { Evh1, sIb }, 0 },
3269     { "xorQ",   { Evh1, sIb }, 0 },
3270     { "cmpQ",   { Ev, sIb }, 0 },
3271   },
3272   /* REG_8F */
3273   {
3274     { "popU",   { stackEv }, 0 },
3275     { XOP_8F_TABLE (XOP_09) },
3276     { Bad_Opcode },
3277     { Bad_Opcode },
3278     { Bad_Opcode },
3279     { XOP_8F_TABLE (XOP_09) },
3280   },
3281   /* REG_C0 */
3282   {
3283     { "rolA",   { Eb, Ib }, 0 },
3284     { "rorA",   { Eb, Ib }, 0 },
3285     { "rclA",   { Eb, Ib }, 0 },
3286     { "rcrA",   { Eb, Ib }, 0 },
3287     { "shlA",   { Eb, Ib }, 0 },
3288     { "shrA",   { Eb, Ib }, 0 },
3289     { "shlA",   { Eb, Ib }, 0 },
3290     { "sarA",   { Eb, Ib }, 0 },
3291   },
3292   /* REG_C1 */
3293   {
3294     { "rolQ",   { Ev, Ib }, 0 },
3295     { "rorQ",   { Ev, Ib }, 0 },
3296     { "rclQ",   { Ev, Ib }, 0 },
3297     { "rcrQ",   { Ev, Ib }, 0 },
3298     { "shlQ",   { Ev, Ib }, 0 },
3299     { "shrQ",   { Ev, Ib }, 0 },
3300     { "shlQ",   { Ev, Ib }, 0 },
3301     { "sarQ",   { Ev, Ib }, 0 },
3302   },
3303   /* REG_C6 */
3304   {
3305     { "movA",   { Ebh3, Ib }, 0 },
3306     { Bad_Opcode },
3307     { Bad_Opcode },
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { Bad_Opcode },
3311     { Bad_Opcode },
3312     { MOD_TABLE (MOD_C6_REG_7) },
3313   },
3314   /* REG_C7 */
3315   {
3316     { "movQ",   { Evh3, Iv }, 0 },
3317     { Bad_Opcode },
3318     { Bad_Opcode },
3319     { Bad_Opcode },
3320     { Bad_Opcode },
3321     { Bad_Opcode },
3322     { Bad_Opcode },
3323     { MOD_TABLE (MOD_C7_REG_7) },
3324   },
3325   /* REG_D0 */
3326   {
3327     { "rolA",   { Eb, I1 }, 0 },
3328     { "rorA",   { Eb, I1 }, 0 },
3329     { "rclA",   { Eb, I1 }, 0 },
3330     { "rcrA",   { Eb, I1 }, 0 },
3331     { "shlA",   { Eb, I1 }, 0 },
3332     { "shrA",   { Eb, I1 }, 0 },
3333     { "shlA",   { Eb, I1 }, 0 },
3334     { "sarA",   { Eb, I1 }, 0 },
3335   },
3336   /* REG_D1 */
3337   {
3338     { "rolQ",   { Ev, I1 }, 0 },
3339     { "rorQ",   { Ev, I1 }, 0 },
3340     { "rclQ",   { Ev, I1 }, 0 },
3341     { "rcrQ",   { Ev, I1 }, 0 },
3342     { "shlQ",   { Ev, I1 }, 0 },
3343     { "shrQ",   { Ev, I1 }, 0 },
3344     { "shlQ",   { Ev, I1 }, 0 },
3345     { "sarQ",   { Ev, I1 }, 0 },
3346   },
3347   /* REG_D2 */
3348   {
3349     { "rolA",   { Eb, CL }, 0 },
3350     { "rorA",   { Eb, CL }, 0 },
3351     { "rclA",   { Eb, CL }, 0 },
3352     { "rcrA",   { Eb, CL }, 0 },
3353     { "shlA",   { Eb, CL }, 0 },
3354     { "shrA",   { Eb, CL }, 0 },
3355     { "shlA",   { Eb, CL }, 0 },
3356     { "sarA",   { Eb, CL }, 0 },
3357   },
3358   /* REG_D3 */
3359   {
3360     { "rolQ",   { Ev, CL }, 0 },
3361     { "rorQ",   { Ev, CL }, 0 },
3362     { "rclQ",   { Ev, CL }, 0 },
3363     { "rcrQ",   { Ev, CL }, 0 },
3364     { "shlQ",   { Ev, CL }, 0 },
3365     { "shrQ",   { Ev, CL }, 0 },
3366     { "shlQ",   { Ev, CL }, 0 },
3367     { "sarQ",   { Ev, CL }, 0 },
3368   },
3369   /* REG_F6 */
3370   {
3371     { "testA",  { Eb, Ib }, 0 },
3372     { "testA",  { Eb, Ib }, 0 },
3373     { "notA",   { Ebh1 }, 0 },
3374     { "negA",   { Ebh1 }, 0 },
3375     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3376     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3377     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3378     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3379   },
3380   /* REG_F7 */
3381   {
3382     { "testQ",  { Ev, Iv }, 0 },
3383     { "testQ",  { Ev, Iv }, 0 },
3384     { "notQ",   { Evh1 }, 0 },
3385     { "negQ",   { Evh1 }, 0 },
3386     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3387     { "imulQ",  { Ev }, 0 },
3388     { "divQ",   { Ev }, 0 },
3389     { "idivQ",  { Ev }, 0 },
3390   },
3391   /* REG_FE */
3392   {
3393     { "incA",   { Ebh1 }, 0 },
3394     { "decA",   { Ebh1 }, 0 },
3395   },
3396   /* REG_FF */
3397   {
3398     { "incQ",   { Evh1 }, 0 },
3399     { "decQ",   { Evh1 }, 0 },
3400     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3401     { MOD_TABLE (MOD_FF_REG_3) },
3402     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3403     { MOD_TABLE (MOD_FF_REG_5) },
3404     { "pushU",  { stackEv }, 0 },
3405     { Bad_Opcode },
3406   },
3407   /* REG_0F00 */
3408   {
3409     { "sldtD",  { Sv }, 0 },
3410     { "strD",   { Sv }, 0 },
3411     { "lldt",   { Ew }, 0 },
3412     { "ltr",    { Ew }, 0 },
3413     { "verr",   { Ew }, 0 },
3414     { "verw",   { Ew }, 0 },
3415     { Bad_Opcode },
3416     { Bad_Opcode },
3417   },
3418   /* REG_0F01 */
3419   {
3420     { MOD_TABLE (MOD_0F01_REG_0) },
3421     { MOD_TABLE (MOD_0F01_REG_1) },
3422     { MOD_TABLE (MOD_0F01_REG_2) },
3423     { MOD_TABLE (MOD_0F01_REG_3) },
3424     { "smswD",  { Sv }, 0 },
3425     { MOD_TABLE (MOD_0F01_REG_5) },
3426     { "lmsw",   { Ew }, 0 },
3427     { MOD_TABLE (MOD_0F01_REG_7) },
3428   },
3429   /* REG_0F0D */
3430   {
3431     { "prefetch",       { Mb }, 0 },
3432     { "prefetchw",      { Mb }, 0 },
3433     { "prefetchwt1",    { Mb }, 0 },
3434     { "prefetch",       { Mb }, 0 },
3435     { "prefetch",       { Mb }, 0 },
3436     { "prefetch",       { Mb }, 0 },
3437     { "prefetch",       { Mb }, 0 },
3438     { "prefetch",       { Mb }, 0 },
3439   },
3440   /* REG_0F18 */
3441   {
3442     { MOD_TABLE (MOD_0F18_REG_0) },
3443     { MOD_TABLE (MOD_0F18_REG_1) },
3444     { MOD_TABLE (MOD_0F18_REG_2) },
3445     { MOD_TABLE (MOD_0F18_REG_3) },
3446     { MOD_TABLE (MOD_0F18_REG_4) },
3447     { MOD_TABLE (MOD_0F18_REG_5) },
3448     { MOD_TABLE (MOD_0F18_REG_6) },
3449     { MOD_TABLE (MOD_0F18_REG_7) },
3450   },
3451   /* REG_0F1C_MOD_0 */
3452   {
3453     { "cldemote",       { Mb }, 0 },
3454     { "nopQ",           { Ev }, 0 },
3455     { "nopQ",           { Ev }, 0 },
3456     { "nopQ",           { Ev }, 0 },
3457     { "nopQ",           { Ev }, 0 },
3458     { "nopQ",           { Ev }, 0 },
3459     { "nopQ",           { Ev }, 0 },
3460     { "nopQ",           { Ev }, 0 },
3461   },
3462   /* REG_0F1E_MOD_3 */
3463   {
3464     { "nopQ",           { Ev }, 0 },
3465     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3466     { "nopQ",           { Ev }, 0 },
3467     { "nopQ",           { Ev }, 0 },
3468     { "nopQ",           { Ev }, 0 },
3469     { "nopQ",           { Ev }, 0 },
3470     { "nopQ",           { Ev }, 0 },
3471     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3472   },
3473   /* REG_0F71 */
3474   {
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { MOD_TABLE (MOD_0F71_REG_2) },
3478     { Bad_Opcode },
3479     { MOD_TABLE (MOD_0F71_REG_4) },
3480     { Bad_Opcode },
3481     { MOD_TABLE (MOD_0F71_REG_6) },
3482   },
3483   /* REG_0F72 */
3484   {
3485     { Bad_Opcode },
3486     { Bad_Opcode },
3487     { MOD_TABLE (MOD_0F72_REG_2) },
3488     { Bad_Opcode },
3489     { MOD_TABLE (MOD_0F72_REG_4) },
3490     { Bad_Opcode },
3491     { MOD_TABLE (MOD_0F72_REG_6) },
3492   },
3493   /* REG_0F73 */
3494   {
3495     { Bad_Opcode },
3496     { Bad_Opcode },
3497     { MOD_TABLE (MOD_0F73_REG_2) },
3498     { MOD_TABLE (MOD_0F73_REG_3) },
3499     { Bad_Opcode },
3500     { Bad_Opcode },
3501     { MOD_TABLE (MOD_0F73_REG_6) },
3502     { MOD_TABLE (MOD_0F73_REG_7) },
3503   },
3504   /* REG_0FA6 */
3505   {
3506     { "montmul",        { { OP_0f07, 0 } }, 0 },
3507     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3508     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3509   },
3510   /* REG_0FA7 */
3511   {
3512     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3513     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3514     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3515     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3516     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3517     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3518   },
3519   /* REG_0FAE */
3520   {
3521     { MOD_TABLE (MOD_0FAE_REG_0) },
3522     { MOD_TABLE (MOD_0FAE_REG_1) },
3523     { MOD_TABLE (MOD_0FAE_REG_2) },
3524     { MOD_TABLE (MOD_0FAE_REG_3) },
3525     { MOD_TABLE (MOD_0FAE_REG_4) },
3526     { MOD_TABLE (MOD_0FAE_REG_5) },
3527     { MOD_TABLE (MOD_0FAE_REG_6) },
3528     { MOD_TABLE (MOD_0FAE_REG_7) },
3529   },
3530   /* REG_0FBA */
3531   {
3532     { Bad_Opcode },
3533     { Bad_Opcode },
3534     { Bad_Opcode },
3535     { Bad_Opcode },
3536     { "btQ",    { Ev, Ib }, 0 },
3537     { "btsQ",   { Evh1, Ib }, 0 },
3538     { "btrQ",   { Evh1, Ib }, 0 },
3539     { "btcQ",   { Evh1, Ib }, 0 },
3540   },
3541   /* REG_0FC7 */
3542   {
3543     { Bad_Opcode },
3544     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3545     { Bad_Opcode },
3546     { MOD_TABLE (MOD_0FC7_REG_3) },
3547     { MOD_TABLE (MOD_0FC7_REG_4) },
3548     { MOD_TABLE (MOD_0FC7_REG_5) },
3549     { MOD_TABLE (MOD_0FC7_REG_6) },
3550     { MOD_TABLE (MOD_0FC7_REG_7) },
3551   },
3552   /* REG_VEX_0F71 */
3553   {
3554     { Bad_Opcode },
3555     { Bad_Opcode },
3556     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3557     { Bad_Opcode },
3558     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3559     { Bad_Opcode },
3560     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3561   },
3562   /* REG_VEX_0F72 */
3563   {
3564     { Bad_Opcode },
3565     { Bad_Opcode },
3566     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3567     { Bad_Opcode },
3568     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3569     { Bad_Opcode },
3570     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3571   },
3572   /* REG_VEX_0F73 */
3573   {
3574     { Bad_Opcode },
3575     { Bad_Opcode },
3576     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3577     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3578     { Bad_Opcode },
3579     { Bad_Opcode },
3580     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3581     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3582   },
3583   /* REG_VEX_0FAE */
3584   {
3585     { Bad_Opcode },
3586     { Bad_Opcode },
3587     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3588     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3589   },
3590   /* REG_VEX_0F38F3 */
3591   {
3592     { Bad_Opcode },
3593     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3594     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3595     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3596   },
3597   /* REG_XOP_LWPCB */
3598   {
3599     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3600     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3601   },
3602   /* REG_XOP_LWP */
3603   {
3604     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3605     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3606   },
3607   /* REG_XOP_TBM_01 */
3608   {
3609     { Bad_Opcode },
3610     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3611     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3612     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3613     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3614     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3615     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3616     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3617   },
3618   /* REG_XOP_TBM_02 */
3619   {
3620     { Bad_Opcode },
3621     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3622     { Bad_Opcode },
3623     { Bad_Opcode },
3624     { Bad_Opcode },
3625     { Bad_Opcode },
3626     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3627   },
3628
3629 #include "i386-dis-evex-reg.h"
3630 };
3631
3632 static const struct dis386 prefix_table[][4] = {
3633   /* PREFIX_90 */
3634   {
3635     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3636     { "pause", { XX }, 0 },
3637     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3638     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3639   },
3640
3641   /* PREFIX_MOD_0_0F01_REG_5 */
3642   {
3643     { Bad_Opcode },
3644     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3645   },
3646
3647   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3648   {
3649     { Bad_Opcode },
3650     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3651   },
3652
3653   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3654   {
3655     { Bad_Opcode },
3656     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3657   },
3658
3659   /* PREFIX_0F09 */
3660   {
3661     { "wbinvd",   { XX }, 0 },
3662     { "wbnoinvd", { XX }, 0 },
3663   },
3664
3665   /* PREFIX_0F10 */
3666   {
3667     { "movups", { XM, EXx }, PREFIX_OPCODE },
3668     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3669     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3670     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3671   },
3672
3673   /* PREFIX_0F11 */
3674   {
3675     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3676     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3677     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3678     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3679   },
3680
3681   /* PREFIX_0F12 */
3682   {
3683     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3684     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3685     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3686     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3687   },
3688
3689   /* PREFIX_0F16 */
3690   {
3691     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3692     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3693     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3694   },
3695
3696   /* PREFIX_0F1A */
3697   {
3698     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3699     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3700     { "bndmov", { Gbnd, Ebnd }, 0 },
3701     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3702   },
3703
3704   /* PREFIX_0F1B */
3705   {
3706     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3707     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3708     { "bndmov", { EbndS, Gbnd }, 0 },
3709     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3710   },
3711
3712   /* PREFIX_0F1C */
3713   {
3714     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3715     { "nopQ",   { Ev }, PREFIX_OPCODE },
3716     { "nopQ",   { Ev }, PREFIX_OPCODE },
3717     { "nopQ",   { Ev }, PREFIX_OPCODE },
3718   },
3719
3720   /* PREFIX_0F1E */
3721   {
3722     { "nopQ",   { Ev }, PREFIX_OPCODE },
3723     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3724     { "nopQ",   { Ev }, PREFIX_OPCODE },
3725     { "nopQ",   { Ev }, PREFIX_OPCODE },
3726   },
3727
3728   /* PREFIX_0F2A */
3729   {
3730     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3731     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3732     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3733     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3734   },
3735
3736   /* PREFIX_0F2B */
3737   {
3738     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3739     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3740     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3741     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3742   },
3743
3744   /* PREFIX_0F2C */
3745   {
3746     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3747     { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3748     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3749     { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3750   },
3751
3752   /* PREFIX_0F2D */
3753   {
3754     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3755     { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3756     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3757     { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3758   },
3759
3760   /* PREFIX_0F2E */
3761   {
3762     { "ucomiss",{ XM, EXd }, 0 },
3763     { Bad_Opcode },
3764     { "ucomisd",{ XM, EXq }, 0 },
3765   },
3766
3767   /* PREFIX_0F2F */
3768   {
3769     { "comiss", { XM, EXd }, 0 },
3770     { Bad_Opcode },
3771     { "comisd", { XM, EXq }, 0 },
3772   },
3773
3774   /* PREFIX_0F51 */
3775   {
3776     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3777     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3778     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3779     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3780   },
3781
3782   /* PREFIX_0F52 */
3783   {
3784     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3785     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3786   },
3787
3788   /* PREFIX_0F53 */
3789   {
3790     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3791     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3792   },
3793
3794   /* PREFIX_0F58 */
3795   {
3796     { "addps", { XM, EXx }, PREFIX_OPCODE },
3797     { "addss", { XM, EXd }, PREFIX_OPCODE },
3798     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3799     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3800   },
3801
3802   /* PREFIX_0F59 */
3803   {
3804     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3805     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3806     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3807     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3808   },
3809
3810   /* PREFIX_0F5A */
3811   {
3812     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3813     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3814     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3815     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3816   },
3817
3818   /* PREFIX_0F5B */
3819   {
3820     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3821     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3822     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3823   },
3824
3825   /* PREFIX_0F5C */
3826   {
3827     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3828     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3829     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3830     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3831   },
3832
3833   /* PREFIX_0F5D */
3834   {
3835     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3836     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3837     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3838     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3839   },
3840
3841   /* PREFIX_0F5E */
3842   {
3843     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3844     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3845     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3846     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3847   },
3848
3849   /* PREFIX_0F5F */
3850   {
3851     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3852     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3853     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3854     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3855   },
3856
3857   /* PREFIX_0F60 */
3858   {
3859     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3860     { Bad_Opcode },
3861     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3862   },
3863
3864   /* PREFIX_0F61 */
3865   {
3866     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3867     { Bad_Opcode },
3868     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3869   },
3870
3871   /* PREFIX_0F62 */
3872   {
3873     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3874     { Bad_Opcode },
3875     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3876   },
3877
3878   /* PREFIX_0F6C */
3879   {
3880     { Bad_Opcode },
3881     { Bad_Opcode },
3882     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3883   },
3884
3885   /* PREFIX_0F6D */
3886   {
3887     { Bad_Opcode },
3888     { Bad_Opcode },
3889     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3890   },
3891
3892   /* PREFIX_0F6F */
3893   {
3894     { "movq",   { MX, EM }, PREFIX_OPCODE },
3895     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3896     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3897   },
3898
3899   /* PREFIX_0F70 */
3900   {
3901     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3902     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3903     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3904     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3905   },
3906
3907   /* PREFIX_0F73_REG_3 */
3908   {
3909     { Bad_Opcode },
3910     { Bad_Opcode },
3911     { "psrldq", { XS, Ib }, 0 },
3912   },
3913
3914   /* PREFIX_0F73_REG_7 */
3915   {
3916     { Bad_Opcode },
3917     { Bad_Opcode },
3918     { "pslldq", { XS, Ib }, 0 },
3919   },
3920
3921   /* PREFIX_0F78 */
3922   {
3923     {"vmread",  { Em, Gm }, 0 },
3924     { Bad_Opcode },
3925     {"extrq",   { XS, Ib, Ib }, 0 },
3926     {"insertq", { XM, XS, Ib, Ib }, 0 },
3927   },
3928
3929   /* PREFIX_0F79 */
3930   {
3931     {"vmwrite", { Gm, Em }, 0 },
3932     { Bad_Opcode },
3933     {"extrq",   { XM, XS }, 0 },
3934     {"insertq", { XM, XS }, 0 },
3935   },
3936
3937   /* PREFIX_0F7C */
3938   {
3939     { Bad_Opcode },
3940     { Bad_Opcode },
3941     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3942     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3943   },
3944
3945   /* PREFIX_0F7D */
3946   {
3947     { Bad_Opcode },
3948     { Bad_Opcode },
3949     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3950     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3951   },
3952
3953   /* PREFIX_0F7E */
3954   {
3955     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3956     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3957     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3958   },
3959
3960   /* PREFIX_0F7F */
3961   {
3962     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3963     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3964     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3965   },
3966
3967   /* PREFIX_0FAE_REG_0 */
3968   {
3969     { Bad_Opcode },
3970     { "rdfsbase", { Ev }, 0 },
3971   },
3972
3973   /* PREFIX_0FAE_REG_1 */
3974   {
3975     { Bad_Opcode },
3976     { "rdgsbase", { Ev }, 0 },
3977   },
3978
3979   /* PREFIX_0FAE_REG_2 */
3980   {
3981     { Bad_Opcode },
3982     { "wrfsbase", { Ev }, 0 },
3983   },
3984
3985   /* PREFIX_0FAE_REG_3 */
3986   {
3987     { Bad_Opcode },
3988     { "wrgsbase", { Ev }, 0 },
3989   },
3990
3991   /* PREFIX_MOD_0_0FAE_REG_4 */
3992   {
3993     { "xsave",  { FXSAVE }, 0 },
3994     { "ptwrite%LQ", { Edq }, 0 },
3995   },
3996
3997   /* PREFIX_MOD_3_0FAE_REG_4 */
3998   {
3999     { Bad_Opcode },
4000     { "ptwrite%LQ", { Edq }, 0 },
4001   },
4002
4003   /* PREFIX_MOD_0_0FAE_REG_5 */
4004   {
4005     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4006   },
4007
4008   /* PREFIX_MOD_3_0FAE_REG_5 */
4009   {
4010     { "lfence",         { Skip_MODRM }, 0 },
4011     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4012   },
4013
4014   /* PREFIX_MOD_0_0FAE_REG_6 */
4015   {
4016     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4017     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4018     { "clwb",   { Mb }, PREFIX_OPCODE },
4019   },
4020
4021   /* PREFIX_MOD_1_0FAE_REG_6 */
4022   {
4023     { RM_TABLE (RM_0FAE_REG_6) },
4024     { "umonitor",       { Eva }, PREFIX_OPCODE },
4025     { "tpause", { Edq }, PREFIX_OPCODE },
4026     { "umwait", { Edq }, PREFIX_OPCODE },
4027   },
4028
4029   /* PREFIX_0FAE_REG_7 */
4030   {
4031     { "clflush",        { Mb }, 0 },
4032     { Bad_Opcode },
4033     { "clflushopt",     { Mb }, 0 },
4034   },
4035
4036   /* PREFIX_0FB8 */
4037   {
4038     { Bad_Opcode },
4039     { "popcntS", { Gv, Ev }, 0 },
4040   },
4041
4042   /* PREFIX_0FBC */
4043   {
4044     { "bsfS",   { Gv, Ev }, 0 },
4045     { "tzcntS", { Gv, Ev }, 0 },
4046     { "bsfS",   { Gv, Ev }, 0 },
4047   },
4048
4049   /* PREFIX_0FBD */
4050   {
4051     { "bsrS",   { Gv, Ev }, 0 },
4052     { "lzcntS", { Gv, Ev }, 0 },
4053     { "bsrS",   { Gv, Ev }, 0 },
4054   },
4055
4056   /* PREFIX_0FC2 */
4057   {
4058     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4059     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4060     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4061     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4062   },
4063
4064   /* PREFIX_MOD_0_0FC3 */
4065   {
4066     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4067   },
4068
4069   /* PREFIX_MOD_0_0FC7_REG_6 */
4070   {
4071     { "vmptrld",{ Mq }, 0 },
4072     { "vmxon",  { Mq }, 0 },
4073     { "vmclear",{ Mq }, 0 },
4074   },
4075
4076   /* PREFIX_MOD_3_0FC7_REG_6 */
4077   {
4078     { "rdrand", { Ev }, 0 },
4079     { Bad_Opcode },
4080     { "rdrand", { Ev }, 0 }
4081   },
4082
4083   /* PREFIX_MOD_3_0FC7_REG_7 */
4084   {
4085     { "rdseed", { Ev }, 0 },
4086     { "rdpid",  { Em }, 0 },
4087     { "rdseed", { Ev }, 0 },
4088   },
4089
4090   /* PREFIX_0FD0 */
4091   {
4092     { Bad_Opcode },
4093     { Bad_Opcode },
4094     { "addsubpd", { XM, EXx }, 0 },
4095     { "addsubps", { XM, EXx }, 0 },
4096   },
4097
4098   /* PREFIX_0FD6 */
4099   {
4100     { Bad_Opcode },
4101     { "movq2dq",{ XM, MS }, 0 },
4102     { "movq",   { EXqS, XM }, 0 },
4103     { "movdq2q",{ MX, XS }, 0 },
4104   },
4105
4106   /* PREFIX_0FE6 */
4107   {
4108     { Bad_Opcode },
4109     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4110     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4111     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4112   },
4113
4114   /* PREFIX_0FE7 */
4115   {
4116     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4117     { Bad_Opcode },
4118     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4119   },
4120
4121   /* PREFIX_0FF0 */
4122   {
4123     { Bad_Opcode },
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4127   },
4128
4129   /* PREFIX_0FF7 */
4130   {
4131     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4132     { Bad_Opcode },
4133     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4134   },
4135
4136   /* PREFIX_0F3810 */
4137   {
4138     { Bad_Opcode },
4139     { Bad_Opcode },
4140     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4141   },
4142
4143   /* PREFIX_0F3814 */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4148   },
4149
4150   /* PREFIX_0F3815 */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4155   },
4156
4157   /* PREFIX_0F3817 */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4162   },
4163
4164   /* PREFIX_0F3820 */
4165   {
4166     { Bad_Opcode },
4167     { Bad_Opcode },
4168     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4169   },
4170
4171   /* PREFIX_0F3821 */
4172   {
4173     { Bad_Opcode },
4174     { Bad_Opcode },
4175     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4176   },
4177
4178   /* PREFIX_0F3822 */
4179   {
4180     { Bad_Opcode },
4181     { Bad_Opcode },
4182     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4183   },
4184
4185   /* PREFIX_0F3823 */
4186   {
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4190   },
4191
4192   /* PREFIX_0F3824 */
4193   {
4194     { Bad_Opcode },
4195     { Bad_Opcode },
4196     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4197   },
4198
4199   /* PREFIX_0F3825 */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4204   },
4205
4206   /* PREFIX_0F3828 */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4211   },
4212
4213   /* PREFIX_0F3829 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4218   },
4219
4220   /* PREFIX_0F382A */
4221   {
4222     { Bad_Opcode },
4223     { Bad_Opcode },
4224     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4225   },
4226
4227   /* PREFIX_0F382B */
4228   {
4229     { Bad_Opcode },
4230     { Bad_Opcode },
4231     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4232   },
4233
4234   /* PREFIX_0F3830 */
4235   {
4236     { Bad_Opcode },
4237     { Bad_Opcode },
4238     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4239   },
4240
4241   /* PREFIX_0F3831 */
4242   {
4243     { Bad_Opcode },
4244     { Bad_Opcode },
4245     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4246   },
4247
4248   /* PREFIX_0F3832 */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4253   },
4254
4255   /* PREFIX_0F3833 */
4256   {
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4260   },
4261
4262   /* PREFIX_0F3834 */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4267   },
4268
4269   /* PREFIX_0F3835 */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4274   },
4275
4276   /* PREFIX_0F3837 */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_0F3838 */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4288   },
4289
4290   /* PREFIX_0F3839 */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4295   },
4296
4297   /* PREFIX_0F383A */
4298   {
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4302   },
4303
4304   /* PREFIX_0F383B */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4309   },
4310
4311   /* PREFIX_0F383C */
4312   {
4313     { Bad_Opcode },
4314     { Bad_Opcode },
4315     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4316   },
4317
4318   /* PREFIX_0F383D */
4319   {
4320     { Bad_Opcode },
4321     { Bad_Opcode },
4322     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4323   },
4324
4325   /* PREFIX_0F383E */
4326   {
4327     { Bad_Opcode },
4328     { Bad_Opcode },
4329     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4330   },
4331
4332   /* PREFIX_0F383F */
4333   {
4334     { Bad_Opcode },
4335     { Bad_Opcode },
4336     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4337   },
4338
4339   /* PREFIX_0F3840 */
4340   {
4341     { Bad_Opcode },
4342     { Bad_Opcode },
4343     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4344   },
4345
4346   /* PREFIX_0F3841 */
4347   {
4348     { Bad_Opcode },
4349     { Bad_Opcode },
4350     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4351   },
4352
4353   /* PREFIX_0F3880 */
4354   {
4355     { Bad_Opcode },
4356     { Bad_Opcode },
4357     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4358   },
4359
4360   /* PREFIX_0F3881 */
4361   {
4362     { Bad_Opcode },
4363     { Bad_Opcode },
4364     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4365   },
4366
4367   /* PREFIX_0F3882 */
4368   {
4369     { Bad_Opcode },
4370     { Bad_Opcode },
4371     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4372   },
4373
4374   /* PREFIX_0F38C8 */
4375   {
4376     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4377   },
4378
4379   /* PREFIX_0F38C9 */
4380   {
4381     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4382   },
4383
4384   /* PREFIX_0F38CA */
4385   {
4386     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4387   },
4388
4389   /* PREFIX_0F38CB */
4390   {
4391     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4392   },
4393
4394   /* PREFIX_0F38CC */
4395   {
4396     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4397   },
4398
4399   /* PREFIX_0F38CD */
4400   {
4401     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4402   },
4403
4404   /* PREFIX_0F38CF */
4405   {
4406     { Bad_Opcode },
4407     { Bad_Opcode },
4408     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4409   },
4410
4411   /* PREFIX_0F38DB */
4412   {
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4416   },
4417
4418   /* PREFIX_0F38DC */
4419   {
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4423   },
4424
4425   /* PREFIX_0F38DD */
4426   {
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4430   },
4431
4432   /* PREFIX_0F38DE */
4433   {
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4437   },
4438
4439   /* PREFIX_0F38DF */
4440   {
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4444   },
4445
4446   /* PREFIX_0F38F0 */
4447   {
4448     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4449     { Bad_Opcode },
4450     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4451     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4452   },
4453
4454   /* PREFIX_0F38F1 */
4455   {
4456     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4457     { Bad_Opcode },
4458     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4459     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4460   },
4461
4462   /* PREFIX_0F38F5 */
4463   {
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4467   },
4468
4469   /* PREFIX_0F38F6 */
4470   {
4471     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4472     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4473     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4474     { Bad_Opcode },
4475   },
4476
4477   /* PREFIX_0F38F8 */
4478   {
4479     { Bad_Opcode },
4480     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4481     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4482     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4483   },
4484
4485   /* PREFIX_0F38F9 */
4486   {
4487     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4488   },
4489
4490   /* PREFIX_0F3A08 */
4491   {
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4495   },
4496
4497   /* PREFIX_0F3A09 */
4498   {
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4502   },
4503
4504   /* PREFIX_0F3A0A */
4505   {
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4509   },
4510
4511   /* PREFIX_0F3A0B */
4512   {
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4516   },
4517
4518   /* PREFIX_0F3A0C */
4519   {
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4523   },
4524
4525   /* PREFIX_0F3A0D */
4526   {
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4530   },
4531
4532   /* PREFIX_0F3A0E */
4533   {
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4537   },
4538
4539   /* PREFIX_0F3A14 */
4540   {
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4544   },
4545
4546   /* PREFIX_0F3A15 */
4547   {
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4551   },
4552
4553   /* PREFIX_0F3A16 */
4554   {
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4558   },
4559
4560   /* PREFIX_0F3A17 */
4561   {
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4565   },
4566
4567   /* PREFIX_0F3A20 */
4568   {
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4572   },
4573
4574   /* PREFIX_0F3A21 */
4575   {
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4579   },
4580
4581   /* PREFIX_0F3A22 */
4582   {
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4586   },
4587
4588   /* PREFIX_0F3A40 */
4589   {
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4593   },
4594
4595   /* PREFIX_0F3A41 */
4596   {
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4600   },
4601
4602   /* PREFIX_0F3A42 */
4603   {
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4607   },
4608
4609   /* PREFIX_0F3A44 */
4610   {
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4614   },
4615
4616   /* PREFIX_0F3A60 */
4617   {
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4621   },
4622
4623   /* PREFIX_0F3A61 */
4624   {
4625     { Bad_Opcode },
4626     { Bad_Opcode },
4627     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4628   },
4629
4630   /* PREFIX_0F3A62 */
4631   {
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4635   },
4636
4637   /* PREFIX_0F3A63 */
4638   {
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4642   },
4643
4644   /* PREFIX_0F3ACC */
4645   {
4646     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4647   },
4648
4649   /* PREFIX_0F3ACE */
4650   {
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4654   },
4655
4656   /* PREFIX_0F3ACF */
4657   {
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4661   },
4662
4663   /* PREFIX_0F3ADF */
4664   {
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4668   },
4669
4670   /* PREFIX_VEX_0F10 */
4671   {
4672     { "vmovups",        { XM, EXx }, 0 },
4673     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4674     { "vmovupd",        { XM, EXx }, 0 },
4675     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4676   },
4677
4678   /* PREFIX_VEX_0F11 */
4679   {
4680     { "vmovups",        { EXxS, XM }, 0 },
4681     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4682     { "vmovupd",        { EXxS, XM }, 0 },
4683     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4684   },
4685
4686   /* PREFIX_VEX_0F12 */
4687   {
4688     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4689     { "vmovsldup",      { XM, EXx }, 0 },
4690     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4691     { "vmovddup",       { XM, EXymmq }, 0 },
4692   },
4693
4694   /* PREFIX_VEX_0F16 */
4695   {
4696     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4697     { "vmovshdup",      { XM, EXx }, 0 },
4698     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4699   },
4700
4701   /* PREFIX_VEX_0F2A */
4702   {
4703     { Bad_Opcode },
4704     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4705     { Bad_Opcode },
4706     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4707   },
4708
4709   /* PREFIX_VEX_0F2C */
4710   {
4711     { Bad_Opcode },
4712     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4713     { Bad_Opcode },
4714     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4715   },
4716
4717   /* PREFIX_VEX_0F2D */
4718   {
4719     { Bad_Opcode },
4720     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4721     { Bad_Opcode },
4722     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4723   },
4724
4725   /* PREFIX_VEX_0F2E */
4726   {
4727     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4728     { Bad_Opcode },
4729     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4730   },
4731
4732   /* PREFIX_VEX_0F2F */
4733   {
4734     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4735     { Bad_Opcode },
4736     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4737   },
4738
4739   /* PREFIX_VEX_0F41 */
4740   {
4741     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4742     { Bad_Opcode },
4743     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4744   },
4745
4746   /* PREFIX_VEX_0F42 */
4747   {
4748     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4749     { Bad_Opcode },
4750     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4751   },
4752
4753   /* PREFIX_VEX_0F44 */
4754   {
4755     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4756     { Bad_Opcode },
4757     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4758   },
4759
4760   /* PREFIX_VEX_0F45 */
4761   {
4762     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4763     { Bad_Opcode },
4764     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4765   },
4766
4767   /* PREFIX_VEX_0F46 */
4768   {
4769     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4770     { Bad_Opcode },
4771     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4772   },
4773
4774   /* PREFIX_VEX_0F47 */
4775   {
4776     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4777     { Bad_Opcode },
4778     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4779   },
4780
4781   /* PREFIX_VEX_0F4A */
4782   {
4783     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4784     { Bad_Opcode },
4785     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4786   },
4787
4788   /* PREFIX_VEX_0F4B */
4789   {
4790     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4791     { Bad_Opcode },
4792     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4793   },
4794
4795   /* PREFIX_VEX_0F51 */
4796   {
4797     { "vsqrtps",        { XM, EXx }, 0 },
4798     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4799     { "vsqrtpd",        { XM, EXx }, 0 },
4800     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4801   },
4802
4803   /* PREFIX_VEX_0F52 */
4804   {
4805     { "vrsqrtps",       { XM, EXx }, 0 },
4806     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4807   },
4808
4809   /* PREFIX_VEX_0F53 */
4810   {
4811     { "vrcpps",         { XM, EXx }, 0 },
4812     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4813   },
4814
4815   /* PREFIX_VEX_0F58 */
4816   {
4817     { "vaddps",         { XM, Vex, EXx }, 0 },
4818     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4819     { "vaddpd",         { XM, Vex, EXx }, 0 },
4820     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4821   },
4822
4823   /* PREFIX_VEX_0F59 */
4824   {
4825     { "vmulps",         { XM, Vex, EXx }, 0 },
4826     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4827     { "vmulpd",         { XM, Vex, EXx }, 0 },
4828     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4829   },
4830
4831   /* PREFIX_VEX_0F5A */
4832   {
4833     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4834     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4835     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4836     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4837   },
4838
4839   /* PREFIX_VEX_0F5B */
4840   {
4841     { "vcvtdq2ps",      { XM, EXx }, 0 },
4842     { "vcvttps2dq",     { XM, EXx }, 0 },
4843     { "vcvtps2dq",      { XM, EXx }, 0 },
4844   },
4845
4846   /* PREFIX_VEX_0F5C */
4847   {
4848     { "vsubps",         { XM, Vex, EXx }, 0 },
4849     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4850     { "vsubpd",         { XM, Vex, EXx }, 0 },
4851     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4852   },
4853
4854   /* PREFIX_VEX_0F5D */
4855   {
4856     { "vminps",         { XM, Vex, EXx }, 0 },
4857     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4858     { "vminpd",         { XM, Vex, EXx }, 0 },
4859     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4860   },
4861
4862   /* PREFIX_VEX_0F5E */
4863   {
4864     { "vdivps",         { XM, Vex, EXx }, 0 },
4865     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4866     { "vdivpd",         { XM, Vex, EXx }, 0 },
4867     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4868   },
4869
4870   /* PREFIX_VEX_0F5F */
4871   {
4872     { "vmaxps",         { XM, Vex, EXx }, 0 },
4873     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4874     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4875     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4876   },
4877
4878   /* PREFIX_VEX_0F60 */
4879   {
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4883   },
4884
4885   /* PREFIX_VEX_0F61 */
4886   {
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4890   },
4891
4892   /* PREFIX_VEX_0F62 */
4893   {
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4897   },
4898
4899   /* PREFIX_VEX_0F63 */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4904   },
4905
4906   /* PREFIX_VEX_0F64 */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4911   },
4912
4913   /* PREFIX_VEX_0F65 */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4918   },
4919
4920   /* PREFIX_VEX_0F66 */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4925   },
4926
4927   /* PREFIX_VEX_0F67 */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4932   },
4933
4934   /* PREFIX_VEX_0F68 */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4939   },
4940
4941   /* PREFIX_VEX_0F69 */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4946   },
4947
4948   /* PREFIX_VEX_0F6A */
4949   {
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4953   },
4954
4955   /* PREFIX_VEX_0F6B */
4956   {
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4960   },
4961
4962   /* PREFIX_VEX_0F6C */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4967   },
4968
4969   /* PREFIX_VEX_0F6D */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4974   },
4975
4976   /* PREFIX_VEX_0F6E */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4981   },
4982
4983   /* PREFIX_VEX_0F6F */
4984   {
4985     { Bad_Opcode },
4986     { "vmovdqu",        { XM, EXx }, 0 },
4987     { "vmovdqa",        { XM, EXx }, 0 },
4988   },
4989
4990   /* PREFIX_VEX_0F70 */
4991   {
4992     { Bad_Opcode },
4993     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4994     { "vpshufd",        { XM, EXx, Ib }, 0 },
4995     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4996   },
4997
4998   /* PREFIX_VEX_0F71_REG_2 */
4999   {
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { "vpsrlw",         { Vex, XS, Ib }, 0 },
5003   },
5004
5005   /* PREFIX_VEX_0F71_REG_4 */
5006   {
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { "vpsraw",         { Vex, XS, Ib }, 0 },
5010   },
5011
5012   /* PREFIX_VEX_0F71_REG_6 */
5013   {
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { "vpsllw",         { Vex, XS, Ib }, 0 },
5017   },
5018
5019   /* PREFIX_VEX_0F72_REG_2 */
5020   {
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { "vpsrld",         { Vex, XS, Ib }, 0 },
5024   },
5025
5026   /* PREFIX_VEX_0F72_REG_4 */
5027   {
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { "vpsrad",         { Vex, XS, Ib }, 0 },
5031   },
5032
5033   /* PREFIX_VEX_0F72_REG_6 */
5034   {
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { "vpslld",         { Vex, XS, Ib }, 0 },
5038   },
5039
5040   /* PREFIX_VEX_0F73_REG_2 */
5041   {
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5045   },
5046
5047   /* PREFIX_VEX_0F73_REG_3 */
5048   {
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5052   },
5053
5054   /* PREFIX_VEX_0F73_REG_6 */
5055   {
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { "vpsllq",         { Vex, XS, Ib }, 0 },
5059   },
5060
5061   /* PREFIX_VEX_0F73_REG_7 */
5062   {
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { "vpslldq",        { Vex, XS, Ib }, 0 },
5066   },
5067
5068   /* PREFIX_VEX_0F74 */
5069   {
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5073   },
5074
5075   /* PREFIX_VEX_0F75 */
5076   {
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5080   },
5081
5082   /* PREFIX_VEX_0F76 */
5083   {
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5087   },
5088
5089   /* PREFIX_VEX_0F77 */
5090   {
5091     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5092   },
5093
5094   /* PREFIX_VEX_0F7C */
5095   {
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5099     { "vhaddps",        { XM, Vex, EXx }, 0 },
5100   },
5101
5102   /* PREFIX_VEX_0F7D */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5107     { "vhsubps",        { XM, Vex, EXx }, 0 },
5108   },
5109
5110   /* PREFIX_VEX_0F7E */
5111   {
5112     { Bad_Opcode },
5113     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5114     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5115   },
5116
5117   /* PREFIX_VEX_0F7F */
5118   {
5119     { Bad_Opcode },
5120     { "vmovdqu",        { EXxS, XM }, 0 },
5121     { "vmovdqa",        { EXxS, XM }, 0 },
5122   },
5123
5124   /* PREFIX_VEX_0F90 */
5125   {
5126     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5127     { Bad_Opcode },
5128     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5129   },
5130
5131   /* PREFIX_VEX_0F91 */
5132   {
5133     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5134     { Bad_Opcode },
5135     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5136   },
5137
5138   /* PREFIX_VEX_0F92 */
5139   {
5140     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5141     { Bad_Opcode },
5142     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5143     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5144   },
5145
5146   /* PREFIX_VEX_0F93 */
5147   {
5148     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5149     { Bad_Opcode },
5150     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5151     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5152   },
5153
5154   /* PREFIX_VEX_0F98 */
5155   {
5156     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5157     { Bad_Opcode },
5158     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5159   },
5160
5161   /* PREFIX_VEX_0F99 */
5162   {
5163     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5164     { Bad_Opcode },
5165     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5166   },
5167
5168   /* PREFIX_VEX_0FC2 */
5169   {
5170     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5171     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5172     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5173     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5174   },
5175
5176   /* PREFIX_VEX_0FC4 */
5177   {
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5181   },
5182
5183   /* PREFIX_VEX_0FC5 */
5184   {
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5188   },
5189
5190   /* PREFIX_VEX_0FD0 */
5191   {
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5195     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5196   },
5197
5198   /* PREFIX_VEX_0FD1 */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5203   },
5204
5205   /* PREFIX_VEX_0FD2 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5210   },
5211
5212   /* PREFIX_VEX_0FD3 */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5217   },
5218
5219   /* PREFIX_VEX_0FD4 */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { "vpaddq",         { XM, Vex, EXx }, 0 },
5224   },
5225
5226   /* PREFIX_VEX_0FD5 */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { "vpmullw",        { XM, Vex, EXx }, 0 },
5231   },
5232
5233   /* PREFIX_VEX_0FD6 */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5238   },
5239
5240   /* PREFIX_VEX_0FD7 */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5245   },
5246
5247   /* PREFIX_VEX_0FD8 */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5252   },
5253
5254   /* PREFIX_VEX_0FD9 */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5259   },
5260
5261   /* PREFIX_VEX_0FDA */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { "vpminub",        { XM, Vex, EXx }, 0 },
5266   },
5267
5268   /* PREFIX_VEX_0FDB */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { "vpand",          { XM, Vex, EXx }, 0 },
5273   },
5274
5275   /* PREFIX_VEX_0FDC */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5280   },
5281
5282   /* PREFIX_VEX_0FDD */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5287   },
5288
5289   /* PREFIX_VEX_0FDE */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5294   },
5295
5296   /* PREFIX_VEX_0FDF */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { "vpandn",         { XM, Vex, EXx }, 0 },
5301   },
5302
5303   /* PREFIX_VEX_0FE0 */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { "vpavgb",         { XM, Vex, EXx }, 0 },
5308   },
5309
5310   /* PREFIX_VEX_0FE1 */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5315   },
5316
5317   /* PREFIX_VEX_0FE2 */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5322   },
5323
5324   /* PREFIX_VEX_0FE3 */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { "vpavgw",         { XM, Vex, EXx }, 0 },
5329   },
5330
5331   /* PREFIX_VEX_0FE4 */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5336   },
5337
5338   /* PREFIX_VEX_0FE5 */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5343   },
5344
5345   /* PREFIX_VEX_0FE6 */
5346   {
5347     { Bad_Opcode },
5348     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5349     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5350     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5351   },
5352
5353   /* PREFIX_VEX_0FE7 */
5354   {
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5358   },
5359
5360   /* PREFIX_VEX_0FE8 */
5361   {
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5365   },
5366
5367   /* PREFIX_VEX_0FE9 */
5368   {
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5372   },
5373
5374   /* PREFIX_VEX_0FEA */
5375   {
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { "vpminsw",        { XM, Vex, EXx }, 0 },
5379   },
5380
5381   /* PREFIX_VEX_0FEB */
5382   {
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { "vpor",           { XM, Vex, EXx }, 0 },
5386   },
5387
5388   /* PREFIX_VEX_0FEC */
5389   {
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5393   },
5394
5395   /* PREFIX_VEX_0FED */
5396   {
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5400   },
5401
5402   /* PREFIX_VEX_0FEE */
5403   {
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5407   },
5408
5409   /* PREFIX_VEX_0FEF */
5410   {
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { "vpxor",          { XM, Vex, EXx }, 0 },
5414   },
5415
5416   /* PREFIX_VEX_0FF0 */
5417   {
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5422   },
5423
5424   /* PREFIX_VEX_0FF1 */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5429   },
5430
5431   /* PREFIX_VEX_0FF2 */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5436   },
5437
5438   /* PREFIX_VEX_0FF3 */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5443   },
5444
5445   /* PREFIX_VEX_0FF4 */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5450   },
5451
5452   /* PREFIX_VEX_0FF5 */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5457   },
5458
5459   /* PREFIX_VEX_0FF6 */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5464   },
5465
5466   /* PREFIX_VEX_0FF7 */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5471   },
5472
5473   /* PREFIX_VEX_0FF8 */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { "vpsubb",         { XM, Vex, EXx }, 0 },
5478   },
5479
5480   /* PREFIX_VEX_0FF9 */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { "vpsubw",         { XM, Vex, EXx }, 0 },
5485   },
5486
5487   /* PREFIX_VEX_0FFA */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { "vpsubd",         { XM, Vex, EXx }, 0 },
5492   },
5493
5494   /* PREFIX_VEX_0FFB */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { "vpsubq",         { XM, Vex, EXx }, 0 },
5499   },
5500
5501   /* PREFIX_VEX_0FFC */
5502   {
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { "vpaddb",         { XM, Vex, EXx }, 0 },
5506   },
5507
5508   /* PREFIX_VEX_0FFD */
5509   {
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { "vpaddw",         { XM, Vex, EXx }, 0 },
5513   },
5514
5515   /* PREFIX_VEX_0FFE */
5516   {
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { "vpaddd",         { XM, Vex, EXx }, 0 },
5520   },
5521
5522   /* PREFIX_VEX_0F3800 */
5523   {
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { "vpshufb",        { XM, Vex, EXx }, 0 },
5527   },
5528
5529   /* PREFIX_VEX_0F3801 */
5530   {
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { "vphaddw",        { XM, Vex, EXx }, 0 },
5534   },
5535
5536   /* PREFIX_VEX_0F3802 */
5537   {
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { "vphaddd",        { XM, Vex, EXx }, 0 },
5541   },
5542
5543   /* PREFIX_VEX_0F3803 */
5544   {
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5548   },
5549
5550   /* PREFIX_VEX_0F3804 */
5551   {
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5555   },
5556
5557   /* PREFIX_VEX_0F3805 */
5558   {
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { "vphsubw",        { XM, Vex, EXx }, 0 },
5562   },
5563
5564   /* PREFIX_VEX_0F3806 */
5565   {
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { "vphsubd",        { XM, Vex, EXx }, 0 },
5569   },
5570
5571   /* PREFIX_VEX_0F3807 */
5572   {
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5576   },
5577
5578   /* PREFIX_VEX_0F3808 */
5579   {
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { "vpsignb",        { XM, Vex, EXx }, 0 },
5583   },
5584
5585   /* PREFIX_VEX_0F3809 */
5586   {
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { "vpsignw",        { XM, Vex, EXx }, 0 },
5590   },
5591
5592   /* PREFIX_VEX_0F380A */
5593   {
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { "vpsignd",        { XM, Vex, EXx }, 0 },
5597   },
5598
5599   /* PREFIX_VEX_0F380B */
5600   {
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5604   },
5605
5606   /* PREFIX_VEX_0F380C */
5607   {
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5611   },
5612
5613   /* PREFIX_VEX_0F380D */
5614   {
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5618   },
5619
5620   /* PREFIX_VEX_0F380E */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5625   },
5626
5627   /* PREFIX_VEX_0F380F */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5632   },
5633
5634   /* PREFIX_VEX_0F3813 */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5639   },
5640
5641   /* PREFIX_VEX_0F3816 */
5642   {
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5646   },
5647
5648   /* PREFIX_VEX_0F3817 */
5649   {
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { "vptest",         { XM, EXx }, 0 },
5653   },
5654
5655   /* PREFIX_VEX_0F3818 */
5656   {
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5660   },
5661
5662   /* PREFIX_VEX_0F3819 */
5663   {
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5667   },
5668
5669   /* PREFIX_VEX_0F381A */
5670   {
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5674   },
5675
5676   /* PREFIX_VEX_0F381C */
5677   {
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { "vpabsb",         { XM, EXx }, 0 },
5681   },
5682
5683   /* PREFIX_VEX_0F381D */
5684   {
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { "vpabsw",         { XM, EXx }, 0 },
5688   },
5689
5690   /* PREFIX_VEX_0F381E */
5691   {
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { "vpabsd",         { XM, EXx }, 0 },
5695   },
5696
5697   /* PREFIX_VEX_0F3820 */
5698   {
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5702   },
5703
5704   /* PREFIX_VEX_0F3821 */
5705   {
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5709   },
5710
5711   /* PREFIX_VEX_0F3822 */
5712   {
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5716   },
5717
5718   /* PREFIX_VEX_0F3823 */
5719   {
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5723   },
5724
5725   /* PREFIX_VEX_0F3824 */
5726   {
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5730   },
5731
5732   /* PREFIX_VEX_0F3825 */
5733   {
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5737   },
5738
5739   /* PREFIX_VEX_0F3828 */
5740   {
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5744   },
5745
5746   /* PREFIX_VEX_0F3829 */
5747   {
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5751   },
5752
5753   /* PREFIX_VEX_0F382A */
5754   {
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5758   },
5759
5760   /* PREFIX_VEX_0F382B */
5761   {
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5765   },
5766
5767   /* PREFIX_VEX_0F382C */
5768   {
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5772   },
5773
5774   /* PREFIX_VEX_0F382D */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5779   },
5780
5781   /* PREFIX_VEX_0F382E */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5786   },
5787
5788   /* PREFIX_VEX_0F382F */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5793   },
5794
5795   /* PREFIX_VEX_0F3830 */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5800   },
5801
5802   /* PREFIX_VEX_0F3831 */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5807   },
5808
5809   /* PREFIX_VEX_0F3832 */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5814   },
5815
5816   /* PREFIX_VEX_0F3833 */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5821   },
5822
5823   /* PREFIX_VEX_0F3834 */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5828   },
5829
5830   /* PREFIX_VEX_0F3835 */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5835   },
5836
5837   /* PREFIX_VEX_0F3836 */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5842   },
5843
5844   /* PREFIX_VEX_0F3837 */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5849   },
5850
5851   /* PREFIX_VEX_0F3838 */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { "vpminsb",        { XM, Vex, EXx }, 0 },
5856   },
5857
5858   /* PREFIX_VEX_0F3839 */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { "vpminsd",        { XM, Vex, EXx }, 0 },
5863   },
5864
5865   /* PREFIX_VEX_0F383A */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { "vpminuw",        { XM, Vex, EXx }, 0 },
5870   },
5871
5872   /* PREFIX_VEX_0F383B */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { "vpminud",        { XM, Vex, EXx }, 0 },
5877   },
5878
5879   /* PREFIX_VEX_0F383C */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5884   },
5885
5886   /* PREFIX_VEX_0F383D */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5891   },
5892
5893   /* PREFIX_VEX_0F383E */
5894   {
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5898   },
5899
5900   /* PREFIX_VEX_0F383F */
5901   {
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5905   },
5906
5907   /* PREFIX_VEX_0F3840 */
5908   {
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { "vpmulld",        { XM, Vex, EXx }, 0 },
5912   },
5913
5914   /* PREFIX_VEX_0F3841 */
5915   {
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5919   },
5920
5921   /* PREFIX_VEX_0F3845 */
5922   {
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5926   },
5927
5928   /* PREFIX_VEX_0F3846 */
5929   {
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5933   },
5934
5935   /* PREFIX_VEX_0F3847 */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5940   },
5941
5942   /* PREFIX_VEX_0F3858 */
5943   {
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5947   },
5948
5949   /* PREFIX_VEX_0F3859 */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5954   },
5955
5956   /* PREFIX_VEX_0F385A */
5957   {
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5961   },
5962
5963   /* PREFIX_VEX_0F3878 */
5964   {
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5968   },
5969
5970   /* PREFIX_VEX_0F3879 */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5975   },
5976
5977   /* PREFIX_VEX_0F388C */
5978   {
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5982   },
5983
5984   /* PREFIX_VEX_0F388E */
5985   {
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5989   },
5990
5991   /* PREFIX_VEX_0F3890 */
5992   {
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5996   },
5997
5998   /* PREFIX_VEX_0F3891 */
5999   {
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6003   },
6004
6005   /* PREFIX_VEX_0F3892 */
6006   {
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6010   },
6011
6012   /* PREFIX_VEX_0F3893 */
6013   {
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6017   },
6018
6019   /* PREFIX_VEX_0F3896 */
6020   {
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6024   },
6025
6026   /* PREFIX_VEX_0F3897 */
6027   {
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6031   },
6032
6033   /* PREFIX_VEX_0F3898 */
6034   {
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6038   },
6039
6040   /* PREFIX_VEX_0F3899 */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6045   },
6046
6047   /* PREFIX_VEX_0F389A */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6052   },
6053
6054   /* PREFIX_VEX_0F389B */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6059   },
6060
6061   /* PREFIX_VEX_0F389C */
6062   {
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6066   },
6067
6068   /* PREFIX_VEX_0F389D */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6073   },
6074
6075   /* PREFIX_VEX_0F389E */
6076   {
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6080   },
6081
6082   /* PREFIX_VEX_0F389F */
6083   {
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6087   },
6088
6089   /* PREFIX_VEX_0F38A6 */
6090   {
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6094     { Bad_Opcode },
6095   },
6096
6097   /* PREFIX_VEX_0F38A7 */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6102   },
6103
6104   /* PREFIX_VEX_0F38A8 */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6109   },
6110
6111   /* PREFIX_VEX_0F38A9 */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6116   },
6117
6118   /* PREFIX_VEX_0F38AA */
6119   {
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6123   },
6124
6125   /* PREFIX_VEX_0F38AB */
6126   {
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6130   },
6131
6132   /* PREFIX_VEX_0F38AC */
6133   {
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6137   },
6138
6139   /* PREFIX_VEX_0F38AD */
6140   {
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6144   },
6145
6146   /* PREFIX_VEX_0F38AE */
6147   {
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6151   },
6152
6153   /* PREFIX_VEX_0F38AF */
6154   {
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6158   },
6159
6160   /* PREFIX_VEX_0F38B6 */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6165   },
6166
6167   /* PREFIX_VEX_0F38B7 */
6168   {
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6172   },
6173
6174   /* PREFIX_VEX_0F38B8 */
6175   {
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6179   },
6180
6181   /* PREFIX_VEX_0F38B9 */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6186   },
6187
6188   /* PREFIX_VEX_0F38BA */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6193   },
6194
6195   /* PREFIX_VEX_0F38BB */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6200   },
6201
6202   /* PREFIX_VEX_0F38BC */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6207   },
6208
6209   /* PREFIX_VEX_0F38BD */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6214   },
6215
6216   /* PREFIX_VEX_0F38BE */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6221   },
6222
6223   /* PREFIX_VEX_0F38BF */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6228   },
6229
6230   /* PREFIX_VEX_0F38CF */
6231   {
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6235   },
6236
6237   /* PREFIX_VEX_0F38DB */
6238   {
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6242   },
6243
6244   /* PREFIX_VEX_0F38DC */
6245   {
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { "vaesenc",        { XM, Vex, EXx }, 0 },
6249   },
6250
6251   /* PREFIX_VEX_0F38DD */
6252   {
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6256   },
6257
6258   /* PREFIX_VEX_0F38DE */
6259   {
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { "vaesdec",        { XM, Vex, EXx }, 0 },
6263   },
6264
6265   /* PREFIX_VEX_0F38DF */
6266   {
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6270   },
6271
6272   /* PREFIX_VEX_0F38F2 */
6273   {
6274     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6275   },
6276
6277   /* PREFIX_VEX_0F38F3_REG_1 */
6278   {
6279     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6280   },
6281
6282   /* PREFIX_VEX_0F38F3_REG_2 */
6283   {
6284     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6285   },
6286
6287   /* PREFIX_VEX_0F38F3_REG_3 */
6288   {
6289     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6290   },
6291
6292   /* PREFIX_VEX_0F38F5 */
6293   {
6294     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6295     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6296     { Bad_Opcode },
6297     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6298   },
6299
6300   /* PREFIX_VEX_0F38F6 */
6301   {
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6306   },
6307
6308   /* PREFIX_VEX_0F38F7 */
6309   {
6310     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6311     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6312     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6313     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6314   },
6315
6316   /* PREFIX_VEX_0F3A00 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6321   },
6322
6323   /* PREFIX_VEX_0F3A01 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6328   },
6329
6330   /* PREFIX_VEX_0F3A02 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6335   },
6336
6337   /* PREFIX_VEX_0F3A04 */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6342   },
6343
6344   /* PREFIX_VEX_0F3A05 */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6349   },
6350
6351   /* PREFIX_VEX_0F3A06 */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6356   },
6357
6358   /* PREFIX_VEX_0F3A08 */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { "vroundps",       { XM, EXx, Ib }, 0 },
6363   },
6364
6365   /* PREFIX_VEX_0F3A09 */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { "vroundpd",       { XM, EXx, Ib }, 0 },
6370   },
6371
6372   /* PREFIX_VEX_0F3A0A */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6377   },
6378
6379   /* PREFIX_VEX_0F3A0B */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6384   },
6385
6386   /* PREFIX_VEX_0F3A0C */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6391   },
6392
6393   /* PREFIX_VEX_0F3A0D */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6398   },
6399
6400   /* PREFIX_VEX_0F3A0E */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6405   },
6406
6407   /* PREFIX_VEX_0F3A0F */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6412   },
6413
6414   /* PREFIX_VEX_0F3A14 */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6419   },
6420
6421   /* PREFIX_VEX_0F3A15 */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6426   },
6427
6428   /* PREFIX_VEX_0F3A16 */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6433   },
6434
6435   /* PREFIX_VEX_0F3A17 */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6440   },
6441
6442   /* PREFIX_VEX_0F3A18 */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6447   },
6448
6449   /* PREFIX_VEX_0F3A19 */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6454   },
6455
6456   /* PREFIX_VEX_0F3A1D */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6461   },
6462
6463   /* PREFIX_VEX_0F3A20 */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6468   },
6469
6470   /* PREFIX_VEX_0F3A21 */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6475   },
6476
6477   /* PREFIX_VEX_0F3A22 */
6478   {
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6482   },
6483
6484   /* PREFIX_VEX_0F3A30 */
6485   {
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6489   },
6490
6491   /* PREFIX_VEX_0F3A31 */
6492   {
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6496   },
6497
6498   /* PREFIX_VEX_0F3A32 */
6499   {
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6503   },
6504
6505   /* PREFIX_VEX_0F3A33 */
6506   {
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6510   },
6511
6512   /* PREFIX_VEX_0F3A38 */
6513   {
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6517   },
6518
6519   /* PREFIX_VEX_0F3A39 */
6520   {
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6524   },
6525
6526   /* PREFIX_VEX_0F3A40 */
6527   {
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6531   },
6532
6533   /* PREFIX_VEX_0F3A41 */
6534   {
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6538   },
6539
6540   /* PREFIX_VEX_0F3A42 */
6541   {
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6545   },
6546
6547   /* PREFIX_VEX_0F3A44 */
6548   {
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6552   },
6553
6554   /* PREFIX_VEX_0F3A46 */
6555   {
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6559   },
6560
6561   /* PREFIX_VEX_0F3A48 */
6562   {
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6566   },
6567
6568   /* PREFIX_VEX_0F3A49 */
6569   {
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6573   },
6574
6575   /* PREFIX_VEX_0F3A4A */
6576   {
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6580   },
6581
6582   /* PREFIX_VEX_0F3A4B */
6583   {
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6587   },
6588
6589   /* PREFIX_VEX_0F3A4C */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6594   },
6595
6596   /* PREFIX_VEX_0F3A5C */
6597   {
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6601   },
6602
6603   /* PREFIX_VEX_0F3A5D */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6608   },
6609
6610   /* PREFIX_VEX_0F3A5E */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6615   },
6616
6617   /* PREFIX_VEX_0F3A5F */
6618   {
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6622   },
6623
6624   /* PREFIX_VEX_0F3A60 */
6625   {
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6629     { Bad_Opcode },
6630   },
6631
6632   /* PREFIX_VEX_0F3A61 */
6633   {
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6637   },
6638
6639   /* PREFIX_VEX_0F3A62 */
6640   {
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6644   },
6645
6646   /* PREFIX_VEX_0F3A63 */
6647   {
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6651   },
6652
6653   /* PREFIX_VEX_0F3A68 */
6654   {
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6658   },
6659
6660   /* PREFIX_VEX_0F3A69 */
6661   {
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6665   },
6666
6667   /* PREFIX_VEX_0F3A6A */
6668   {
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6672   },
6673
6674   /* PREFIX_VEX_0F3A6B */
6675   {
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6679   },
6680
6681   /* PREFIX_VEX_0F3A6C */
6682   {
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6686   },
6687
6688   /* PREFIX_VEX_0F3A6D */
6689   {
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6693   },
6694
6695   /* PREFIX_VEX_0F3A6E */
6696   {
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6700   },
6701
6702   /* PREFIX_VEX_0F3A6F */
6703   {
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6707   },
6708
6709   /* PREFIX_VEX_0F3A78 */
6710   {
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6714   },
6715
6716   /* PREFIX_VEX_0F3A79 */
6717   {
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6721   },
6722
6723   /* PREFIX_VEX_0F3A7A */
6724   {
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6728   },
6729
6730   /* PREFIX_VEX_0F3A7B */
6731   {
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6735   },
6736
6737   /* PREFIX_VEX_0F3A7C */
6738   {
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6742     { Bad_Opcode },
6743   },
6744
6745   /* PREFIX_VEX_0F3A7D */
6746   {
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6750   },
6751
6752   /* PREFIX_VEX_0F3A7E */
6753   {
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6757   },
6758
6759   /* PREFIX_VEX_0F3A7F */
6760   {
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6764   },
6765
6766   /* PREFIX_VEX_0F3ACE */
6767   {
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6771   },
6772
6773   /* PREFIX_VEX_0F3ACF */
6774   {
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6778   },
6779
6780   /* PREFIX_VEX_0F3ADF */
6781   {
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6785   },
6786
6787   /* PREFIX_VEX_0F3AF0 */
6788   {
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6793   },
6794
6795 #include "i386-dis-evex-prefix.h"
6796 };
6797
6798 static const struct dis386 x86_64_table[][2] = {
6799   /* X86_64_06 */
6800   {
6801     { "pushP", { es }, 0 },
6802   },
6803
6804   /* X86_64_07 */
6805   {
6806     { "popP", { es }, 0 },
6807   },
6808
6809   /* X86_64_0D */
6810   {
6811     { "pushP", { cs }, 0 },
6812   },
6813
6814   /* X86_64_16 */
6815   {
6816     { "pushP", { ss }, 0 },
6817   },
6818
6819   /* X86_64_17 */
6820   {
6821     { "popP", { ss }, 0 },
6822   },
6823
6824   /* X86_64_1E */
6825   {
6826     { "pushP", { ds }, 0 },
6827   },
6828
6829   /* X86_64_1F */
6830   {
6831     { "popP", { ds }, 0 },
6832   },
6833
6834   /* X86_64_27 */
6835   {
6836     { "daa", { XX }, 0 },
6837   },
6838
6839   /* X86_64_2F */
6840   {
6841     { "das", { XX }, 0 },
6842   },
6843
6844   /* X86_64_37 */
6845   {
6846     { "aaa", { XX }, 0 },
6847   },
6848
6849   /* X86_64_3F */
6850   {
6851     { "aas", { XX }, 0 },
6852   },
6853
6854   /* X86_64_60 */
6855   {
6856     { "pushaP", { XX }, 0 },
6857   },
6858
6859   /* X86_64_61 */
6860   {
6861     { "popaP", { XX }, 0 },
6862   },
6863
6864   /* X86_64_62 */
6865   {
6866     { MOD_TABLE (MOD_62_32BIT) },
6867     { EVEX_TABLE (EVEX_0F) },
6868   },
6869
6870   /* X86_64_63 */
6871   {
6872     { "arpl", { Ew, Gw }, 0 },
6873     { "movs{lq|xd}", { Gv, Ed }, 0 },
6874   },
6875
6876   /* X86_64_6D */
6877   {
6878     { "ins{R|}", { Yzr, indirDX }, 0 },
6879     { "ins{G|}", { Yzr, indirDX }, 0 },
6880   },
6881
6882   /* X86_64_6F */
6883   {
6884     { "outs{R|}", { indirDXr, Xz }, 0 },
6885     { "outs{G|}", { indirDXr, Xz }, 0 },
6886   },
6887
6888   /* X86_64_82 */
6889   {
6890     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6891     { REG_TABLE (REG_80) },
6892   },
6893
6894   /* X86_64_9A */
6895   {
6896     { "Jcall{T|}", { Ap }, 0 },
6897   },
6898
6899   /* X86_64_C4 */
6900   {
6901     { MOD_TABLE (MOD_C4_32BIT) },
6902     { VEX_C4_TABLE (VEX_0F) },
6903   },
6904
6905   /* X86_64_C5 */
6906   {
6907     { MOD_TABLE (MOD_C5_32BIT) },
6908     { VEX_C5_TABLE (VEX_0F) },
6909   },
6910
6911   /* X86_64_CE */
6912   {
6913     { "into", { XX }, 0 },
6914   },
6915
6916   /* X86_64_D4 */
6917   {
6918     { "aam", { Ib }, 0 },
6919   },
6920
6921   /* X86_64_D5 */
6922   {
6923     { "aad", { Ib }, 0 },
6924   },
6925
6926   /* X86_64_E8 */
6927   {
6928     { "callP",          { Jv, BND }, 0 },
6929     { "call@",          { Jv, BND }, 0 }
6930   },
6931
6932   /* X86_64_E9 */
6933   {
6934     { "jmpP",           { Jv, BND }, 0 },
6935     { "jmp@",           { Jv, BND }, 0 }
6936   },
6937
6938   /* X86_64_EA */
6939   {
6940     { "Jjmp{T|}", { Ap }, 0 },
6941   },
6942
6943   /* X86_64_0F01_REG_0 */
6944   {
6945     { "sgdt{Q|IQ}", { M }, 0 },
6946     { "sgdt", { M }, 0 },
6947   },
6948
6949   /* X86_64_0F01_REG_1 */
6950   {
6951     { "sidt{Q|IQ}", { M }, 0 },
6952     { "sidt", { M }, 0 },
6953   },
6954
6955   /* X86_64_0F01_REG_2 */
6956   {
6957     { "lgdt{Q|Q}", { M }, 0 },
6958     { "lgdt", { M }, 0 },
6959   },
6960
6961   /* X86_64_0F01_REG_3 */
6962   {
6963     { "lidt{Q|Q}", { M }, 0 },
6964     { "lidt", { M }, 0 },
6965   },
6966 };
6967
6968 static const struct dis386 three_byte_table[][256] = {
6969
6970   /* THREE_BYTE_0F38 */
6971   {
6972     /* 00 */
6973     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6974     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6975     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6976     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6977     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6978     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6979     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6980     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6981     /* 08 */
6982     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6983     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6984     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6985     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     /* 10 */
6991     { PREFIX_TABLE (PREFIX_0F3810) },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { PREFIX_TABLE (PREFIX_0F3814) },
6996     { PREFIX_TABLE (PREFIX_0F3815) },
6997     { Bad_Opcode },
6998     { PREFIX_TABLE (PREFIX_0F3817) },
6999     /* 18 */
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7005     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7006     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7007     { Bad_Opcode },
7008     /* 20 */
7009     { PREFIX_TABLE (PREFIX_0F3820) },
7010     { PREFIX_TABLE (PREFIX_0F3821) },
7011     { PREFIX_TABLE (PREFIX_0F3822) },
7012     { PREFIX_TABLE (PREFIX_0F3823) },
7013     { PREFIX_TABLE (PREFIX_0F3824) },
7014     { PREFIX_TABLE (PREFIX_0F3825) },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     /* 28 */
7018     { PREFIX_TABLE (PREFIX_0F3828) },
7019     { PREFIX_TABLE (PREFIX_0F3829) },
7020     { PREFIX_TABLE (PREFIX_0F382A) },
7021     { PREFIX_TABLE (PREFIX_0F382B) },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     /* 30 */
7027     { PREFIX_TABLE (PREFIX_0F3830) },
7028     { PREFIX_TABLE (PREFIX_0F3831) },
7029     { PREFIX_TABLE (PREFIX_0F3832) },
7030     { PREFIX_TABLE (PREFIX_0F3833) },
7031     { PREFIX_TABLE (PREFIX_0F3834) },
7032     { PREFIX_TABLE (PREFIX_0F3835) },
7033     { Bad_Opcode },
7034     { PREFIX_TABLE (PREFIX_0F3837) },
7035     /* 38 */
7036     { PREFIX_TABLE (PREFIX_0F3838) },
7037     { PREFIX_TABLE (PREFIX_0F3839) },
7038     { PREFIX_TABLE (PREFIX_0F383A) },
7039     { PREFIX_TABLE (PREFIX_0F383B) },
7040     { PREFIX_TABLE (PREFIX_0F383C) },
7041     { PREFIX_TABLE (PREFIX_0F383D) },
7042     { PREFIX_TABLE (PREFIX_0F383E) },
7043     { PREFIX_TABLE (PREFIX_0F383F) },
7044     /* 40 */
7045     { PREFIX_TABLE (PREFIX_0F3840) },
7046     { PREFIX_TABLE (PREFIX_0F3841) },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     /* 48 */
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     /* 50 */
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     /* 58 */
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     /* 60 */
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     /* 68 */
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     /* 70 */
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     /* 78 */
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     /* 80 */
7117     { PREFIX_TABLE (PREFIX_0F3880) },
7118     { PREFIX_TABLE (PREFIX_0F3881) },
7119     { PREFIX_TABLE (PREFIX_0F3882) },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     /* 88 */
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     /* 90 */
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     /* 98 */
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     /* a0 */
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     /* a8 */
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     /* b0 */
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     /* b8 */
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     /* c0 */
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     /* c8 */
7198     { PREFIX_TABLE (PREFIX_0F38C8) },
7199     { PREFIX_TABLE (PREFIX_0F38C9) },
7200     { PREFIX_TABLE (PREFIX_0F38CA) },
7201     { PREFIX_TABLE (PREFIX_0F38CB) },
7202     { PREFIX_TABLE (PREFIX_0F38CC) },
7203     { PREFIX_TABLE (PREFIX_0F38CD) },
7204     { Bad_Opcode },
7205     { PREFIX_TABLE (PREFIX_0F38CF) },
7206     /* d0 */
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     /* d8 */
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { PREFIX_TABLE (PREFIX_0F38DB) },
7220     { PREFIX_TABLE (PREFIX_0F38DC) },
7221     { PREFIX_TABLE (PREFIX_0F38DD) },
7222     { PREFIX_TABLE (PREFIX_0F38DE) },
7223     { PREFIX_TABLE (PREFIX_0F38DF) },
7224     /* e0 */
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     /* e8 */
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     /* f0 */
7243     { PREFIX_TABLE (PREFIX_0F38F0) },
7244     { PREFIX_TABLE (PREFIX_0F38F1) },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { PREFIX_TABLE (PREFIX_0F38F5) },
7249     { PREFIX_TABLE (PREFIX_0F38F6) },
7250     { Bad_Opcode },
7251     /* f8 */
7252     { PREFIX_TABLE (PREFIX_0F38F8) },
7253     { PREFIX_TABLE (PREFIX_0F38F9) },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260   },
7261   /* THREE_BYTE_0F3A */
7262   {
7263     /* 00 */
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     /* 08 */
7273     { PREFIX_TABLE (PREFIX_0F3A08) },
7274     { PREFIX_TABLE (PREFIX_0F3A09) },
7275     { PREFIX_TABLE (PREFIX_0F3A0A) },
7276     { PREFIX_TABLE (PREFIX_0F3A0B) },
7277     { PREFIX_TABLE (PREFIX_0F3A0C) },
7278     { PREFIX_TABLE (PREFIX_0F3A0D) },
7279     { PREFIX_TABLE (PREFIX_0F3A0E) },
7280     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7281     /* 10 */
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { PREFIX_TABLE (PREFIX_0F3A14) },
7287     { PREFIX_TABLE (PREFIX_0F3A15) },
7288     { PREFIX_TABLE (PREFIX_0F3A16) },
7289     { PREFIX_TABLE (PREFIX_0F3A17) },
7290     /* 18 */
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     /* 20 */
7300     { PREFIX_TABLE (PREFIX_0F3A20) },
7301     { PREFIX_TABLE (PREFIX_0F3A21) },
7302     { PREFIX_TABLE (PREFIX_0F3A22) },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     /* 28 */
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     /* 30 */
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     /* 38 */
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     /* 40 */
7336     { PREFIX_TABLE (PREFIX_0F3A40) },
7337     { PREFIX_TABLE (PREFIX_0F3A41) },
7338     { PREFIX_TABLE (PREFIX_0F3A42) },
7339     { Bad_Opcode },
7340     { PREFIX_TABLE (PREFIX_0F3A44) },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     /* 48 */
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     /* 50 */
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     /* 58 */
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     /* 60 */
7372     { PREFIX_TABLE (PREFIX_0F3A60) },
7373     { PREFIX_TABLE (PREFIX_0F3A61) },
7374     { PREFIX_TABLE (PREFIX_0F3A62) },
7375     { PREFIX_TABLE (PREFIX_0F3A63) },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     /* 68 */
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     /* 70 */
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     /* 78 */
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     /* 80 */
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     /* 88 */
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     /* 90 */
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     /* 98 */
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     /* a0 */
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     /* a8 */
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     /* b0 */
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     /* b8 */
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     /* c0 */
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     /* c8 */
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { PREFIX_TABLE (PREFIX_0F3ACC) },
7494     { Bad_Opcode },
7495     { PREFIX_TABLE (PREFIX_0F3ACE) },
7496     { PREFIX_TABLE (PREFIX_0F3ACF) },
7497     /* d0 */
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     /* d8 */
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { PREFIX_TABLE (PREFIX_0F3ADF) },
7515     /* e0 */
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     /* e8 */
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     /* f0 */
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     /* f8 */
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551   },
7552 };
7553
7554 static const struct dis386 xop_table[][256] = {
7555   /* XOP_08 */
7556   {
7557     /* 00 */
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     /* 08 */
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     /* 10 */
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     /* 18 */
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     /* 20 */
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     /* 28 */
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     /* 30 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     /* 38 */
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     /* 40 */
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     /* 48 */
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     /* 50 */
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     /* 58 */
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     /* 60 */
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     /* 68 */
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     /* 70 */
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     /* 78 */
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     /* 80 */
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7708     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7709     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7710     /* 88 */
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7718     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7719     /* 90 */
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7726     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7727     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7728     /* 98 */
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7736     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7737     /* a0 */
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7741     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7745     { Bad_Opcode },
7746     /* a8 */
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     /* b0 */
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7763     { Bad_Opcode },
7764     /* b8 */
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     /* c0 */
7774     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7775     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7776     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7777     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     /* c8 */
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7788     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7789     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7790     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7791     /* d0 */
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     /* d8 */
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     /* e0 */
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     /* e8 */
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7824     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7825     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7826     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7827     /* f0 */
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     /* f8 */
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845   },
7846   /* XOP_09 */
7847   {
7848     /* 00 */
7849     { Bad_Opcode },
7850     { REG_TABLE (REG_XOP_TBM_01) },
7851     { REG_TABLE (REG_XOP_TBM_02) },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     /* 08 */
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     /* 10 */
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { REG_TABLE (REG_XOP_LWPCB) },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     /* 18 */
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     /* 20 */
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     /* 28 */
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     /* 30 */
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     /* 38 */
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     /* 40 */
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     /* 48 */
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     /* 50 */
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     /* 58 */
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     /* 60 */
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     /* 68 */
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     /* 70 */
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     /* 78 */
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     /* 80 */
7993     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7994     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7995     { "vfrczss",        { XM, EXd }, 0 },
7996     { "vfrczsd",        { XM, EXq }, 0 },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     /* 88 */
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     /* 90 */
8011     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8012     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8013     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8014     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8019     /* 98 */
8020     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8021     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8022     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8023     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     /* a0 */
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     /* a8 */
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     /* b0 */
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     /* b8 */
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     /* c0 */
8065     { Bad_Opcode },
8066     { "vphaddbw",       { XM, EXxmm }, 0 },
8067     { "vphaddbd",       { XM, EXxmm }, 0 },
8068     { "vphaddbq",       { XM, EXxmm }, 0 },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { "vphaddwd",       { XM, EXxmm }, 0 },
8072     { "vphaddwq",       { XM, EXxmm }, 0 },
8073     /* c8 */
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { "vphadddq",       { XM, EXxmm }, 0 },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     /* d0 */
8083     { Bad_Opcode },
8084     { "vphaddubw",      { XM, EXxmm }, 0 },
8085     { "vphaddubd",      { XM, EXxmm }, 0 },
8086     { "vphaddubq",      { XM, EXxmm }, 0 },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { "vphadduwd",      { XM, EXxmm }, 0 },
8090     { "vphadduwq",      { XM, EXxmm }, 0 },
8091     /* d8 */
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { "vphaddudq",      { XM, EXxmm }, 0 },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     /* e0 */
8101     { Bad_Opcode },
8102     { "vphsubbw",       { XM, EXxmm }, 0 },
8103     { "vphsubwd",       { XM, EXxmm }, 0 },
8104     { "vphsubdq",       { XM, EXxmm }, 0 },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     /* e8 */
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     /* f0 */
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     /* f8 */
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136   },
8137   /* XOP_0A */
8138   {
8139     /* 00 */
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     /* 08 */
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     /* 10 */
8158     { "bextr",  { Gv, Ev, Iq }, 0 },
8159     { Bad_Opcode },
8160     { REG_TABLE (REG_XOP_LWP) },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     /* 18 */
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     /* 20 */
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     /* 28 */
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     /* 30 */
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     /* 38 */
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     /* 40 */
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     /* 48 */
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     /* 50 */
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     /* 58 */
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     /* 60 */
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     /* 68 */
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     /* 70 */
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     /* 78 */
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     /* 80 */
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     /* 88 */
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     /* 90 */
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     /* 98 */
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     /* a0 */
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     /* a8 */
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     /* b0 */
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     /* b8 */
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     /* c0 */
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     /* c8 */
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     /* d0 */
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     /* d8 */
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     /* e0 */
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     /* e8 */
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     /* f0 */
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     /* f8 */
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427   },
8428 };
8429
8430 static const struct dis386 vex_table[][256] = {
8431   /* VEX_0F */
8432   {
8433     /* 00 */
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     /* 08 */
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     /* 10 */
8452     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8453     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8454     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8455     { MOD_TABLE (MOD_VEX_0F13) },
8456     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8457     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8458     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8459     { MOD_TABLE (MOD_VEX_0F17) },
8460     /* 18 */
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     /* 20 */
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     /* 28 */
8479     { "vmovapX",        { XM, EXx }, 0 },
8480     { "vmovapX",        { EXxS, XM }, 0 },
8481     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8482     { MOD_TABLE (MOD_VEX_0F2B) },
8483     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8485     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8486     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8487     /* 30 */
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     /* 38 */
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     /* 40 */
8506     { Bad_Opcode },
8507     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8508     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8509     { Bad_Opcode },
8510     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8511     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8514     /* 48 */
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8518     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     /* 50 */
8524     { MOD_TABLE (MOD_VEX_0F50) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8528     { "vandpX",         { XM, Vex, EXx }, 0 },
8529     { "vandnpX",        { XM, Vex, EXx }, 0 },
8530     { "vorpX",          { XM, Vex, EXx }, 0 },
8531     { "vxorpX",         { XM, Vex, EXx }, 0 },
8532     /* 58 */
8533     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8541     /* 60 */
8542     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8550     /* 68 */
8551     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8558     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8559     /* 70 */
8560     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8561     { REG_TABLE (REG_VEX_0F71) },
8562     { REG_TABLE (REG_VEX_0F72) },
8563     { REG_TABLE (REG_VEX_0F73) },
8564     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8568     /* 78 */
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8577     /* 80 */
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     /* 88 */
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     /* 90 */
8596     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     /* 98 */
8605     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8606     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     /* a0 */
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     /* a8 */
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { REG_TABLE (REG_VEX_0FAE) },
8630     { Bad_Opcode },
8631     /* b0 */
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     /* b8 */
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     /* c0 */
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8653     { Bad_Opcode },
8654     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8655     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8656     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8657     { Bad_Opcode },
8658     /* c8 */
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     /* d0 */
8668     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8676     /* d8 */
8677     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8685     /* e0 */
8686     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8694     /* e8 */
8695     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8703     /* f0 */
8704     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8712     /* f8 */
8713     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8720     { Bad_Opcode },
8721   },
8722   /* VEX_0F38 */
8723   {
8724     /* 00 */
8725     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8733     /* 08 */
8734     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8742     /* 10 */
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8751     /* 18 */
8752     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8755     { Bad_Opcode },
8756     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8759     { Bad_Opcode },
8760     /* 20 */
8761     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     /* 28 */
8770     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8778     /* 30 */
8779     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8787     /* 38 */
8788     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8796     /* 40 */
8797     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8805     /* 48 */
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     /* 50 */
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     /* 58 */
8824     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     /* 60 */
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     /* 68 */
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     /* 70 */
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     /* 78 */
8860     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8861     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     /* 80 */
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     /* 88 */
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8883     { Bad_Opcode },
8884     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8885     { Bad_Opcode },
8886     /* 90 */
8887     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8895     /* 98 */
8896     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8904     /* a0 */
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8913     /* a8 */
8914     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8922     /* b0 */
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8931     /* b8 */
8932     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8940     /* c0 */
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     /* c8 */
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8958     /* d0 */
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     /* d8 */
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8976     /* e0 */
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     /* e8 */
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     /* f0 */
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8998     { REG_TABLE (REG_VEX_0F38F3) },
8999     { Bad_Opcode },
9000     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9003     /* f8 */
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012   },
9013   /* VEX_0F3A */
9014   {
9015     /* 00 */
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9019     { Bad_Opcode },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9023     { Bad_Opcode },
9024     /* 08 */
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9033     /* 10 */
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9042     /* 18 */
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     /* 20 */
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     /* 28 */
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     /* 30 */
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     /* 38 */
9079     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9080     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     /* 40 */
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9091     { Bad_Opcode },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9093     { Bad_Opcode },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9095     { Bad_Opcode },
9096     /* 48 */
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     /* 50 */
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     /* 58 */
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9123     /* 60 */
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     /* 68 */
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9141     /* 70 */
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     /* 78 */
9151     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9159     /* 80 */
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     /* 88 */
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     /* 90 */
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     /* 98 */
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     /* a0 */
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     /* a8 */
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     /* b0 */
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     /* b8 */
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     /* c0 */
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     /* c8 */
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9248     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9249     /* d0 */
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     /* d8 */
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9267     /* e0 */
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     /* e8 */
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     /* f0 */
9286     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     /* f8 */
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303   },
9304 };
9305
9306 #include "i386-dis-evex.h"
9307
9308 static const struct dis386 vex_len_table[][2] = {
9309   /* VEX_LEN_0F12_P_0_M_0 */
9310   {
9311     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9312   },
9313
9314   /* VEX_LEN_0F12_P_0_M_1 */
9315   {
9316     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9317   },
9318
9319   /* VEX_LEN_0F12_P_2 */
9320   {
9321     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9322   },
9323
9324   /* VEX_LEN_0F13_M_0 */
9325   {
9326     { "vmovlpX",        { EXq, XM }, 0 },
9327   },
9328
9329   /* VEX_LEN_0F16_P_0_M_0 */
9330   {
9331     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9332   },
9333
9334   /* VEX_LEN_0F16_P_0_M_1 */
9335   {
9336     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9337   },
9338
9339   /* VEX_LEN_0F16_P_2 */
9340   {
9341     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9342   },
9343
9344   /* VEX_LEN_0F17_M_0 */
9345   {
9346     { "vmovhpX",        { EXq, XM }, 0 },
9347   },
9348
9349   /* VEX_LEN_0F2A_P_1 */
9350   {
9351     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9352     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9353   },
9354
9355   /* VEX_LEN_0F2A_P_3 */
9356   {
9357     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9358     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9359   },
9360
9361   /* VEX_LEN_0F2C_P_1 */
9362   {
9363     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9364     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9365   },
9366
9367   /* VEX_LEN_0F2C_P_3 */
9368   {
9369     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9370     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9371   },
9372
9373   /* VEX_LEN_0F2D_P_1 */
9374   {
9375     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9376     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9377   },
9378
9379   /* VEX_LEN_0F2D_P_3 */
9380   {
9381     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9382     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9383   },
9384
9385   /* VEX_LEN_0F41_P_0 */
9386   {
9387     { Bad_Opcode },
9388     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9389   },
9390   /* VEX_LEN_0F41_P_2 */
9391   {
9392     { Bad_Opcode },
9393     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9394   },
9395   /* VEX_LEN_0F42_P_0 */
9396   {
9397     { Bad_Opcode },
9398     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9399   },
9400   /* VEX_LEN_0F42_P_2 */
9401   {
9402     { Bad_Opcode },
9403     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9404   },
9405   /* VEX_LEN_0F44_P_0 */
9406   {
9407     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9408   },
9409   /* VEX_LEN_0F44_P_2 */
9410   {
9411     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9412   },
9413   /* VEX_LEN_0F45_P_0 */
9414   {
9415     { Bad_Opcode },
9416     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9417   },
9418   /* VEX_LEN_0F45_P_2 */
9419   {
9420     { Bad_Opcode },
9421     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9422   },
9423   /* VEX_LEN_0F46_P_0 */
9424   {
9425     { Bad_Opcode },
9426     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9427   },
9428   /* VEX_LEN_0F46_P_2 */
9429   {
9430     { Bad_Opcode },
9431     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9432   },
9433   /* VEX_LEN_0F47_P_0 */
9434   {
9435     { Bad_Opcode },
9436     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9437   },
9438   /* VEX_LEN_0F47_P_2 */
9439   {
9440     { Bad_Opcode },
9441     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9442   },
9443   /* VEX_LEN_0F4A_P_0 */
9444   {
9445     { Bad_Opcode },
9446     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9447   },
9448   /* VEX_LEN_0F4A_P_2 */
9449   {
9450     { Bad_Opcode },
9451     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9452   },
9453   /* VEX_LEN_0F4B_P_0 */
9454   {
9455     { Bad_Opcode },
9456     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9457   },
9458   /* VEX_LEN_0F4B_P_2 */
9459   {
9460     { Bad_Opcode },
9461     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9462   },
9463
9464   /* VEX_LEN_0F6E_P_2 */
9465   {
9466     { "vmovK",          { XMScalar, Edq }, 0 },
9467   },
9468
9469   /* VEX_LEN_0F77_P_1 */
9470   {
9471     { "vzeroupper",     { XX }, 0 },
9472     { "vzeroall",       { XX }, 0 },
9473   },
9474
9475   /* VEX_LEN_0F7E_P_1 */
9476   {
9477     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9478   },
9479
9480   /* VEX_LEN_0F7E_P_2 */
9481   {
9482     { "vmovK",          { Edq, XMScalar }, 0 },
9483   },
9484
9485   /* VEX_LEN_0F90_P_0 */
9486   {
9487     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9488   },
9489
9490   /* VEX_LEN_0F90_P_2 */
9491   {
9492     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9493   },
9494
9495   /* VEX_LEN_0F91_P_0 */
9496   {
9497     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9498   },
9499
9500   /* VEX_LEN_0F91_P_2 */
9501   {
9502     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9503   },
9504
9505   /* VEX_LEN_0F92_P_0 */
9506   {
9507     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9508   },
9509
9510   /* VEX_LEN_0F92_P_2 */
9511   {
9512     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9513   },
9514
9515   /* VEX_LEN_0F92_P_3 */
9516   {
9517     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9518   },
9519
9520   /* VEX_LEN_0F93_P_0 */
9521   {
9522     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9523   },
9524
9525   /* VEX_LEN_0F93_P_2 */
9526   {
9527     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9528   },
9529
9530   /* VEX_LEN_0F93_P_3 */
9531   {
9532     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9533   },
9534
9535   /* VEX_LEN_0F98_P_0 */
9536   {
9537     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9538   },
9539
9540   /* VEX_LEN_0F98_P_2 */
9541   {
9542     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9543   },
9544
9545   /* VEX_LEN_0F99_P_0 */
9546   {
9547     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9548   },
9549
9550   /* VEX_LEN_0F99_P_2 */
9551   {
9552     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9553   },
9554
9555   /* VEX_LEN_0FAE_R_2_M_0 */
9556   {
9557     { "vldmxcsr",       { Md }, 0 },
9558   },
9559
9560   /* VEX_LEN_0FAE_R_3_M_0 */
9561   {
9562     { "vstmxcsr",       { Md }, 0 },
9563   },
9564
9565   /* VEX_LEN_0FC4_P_2 */
9566   {
9567     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9568   },
9569
9570   /* VEX_LEN_0FC5_P_2 */
9571   {
9572     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9573   },
9574
9575   /* VEX_LEN_0FD6_P_2 */
9576   {
9577     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9578   },
9579
9580   /* VEX_LEN_0FF7_P_2 */
9581   {
9582     { "vmaskmovdqu",    { XM, XS }, 0 },
9583   },
9584
9585   /* VEX_LEN_0F3816_P_2 */
9586   {
9587     { Bad_Opcode },
9588     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9589   },
9590
9591   /* VEX_LEN_0F3819_P_2 */
9592   {
9593     { Bad_Opcode },
9594     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9595   },
9596
9597   /* VEX_LEN_0F381A_P_2_M_0 */
9598   {
9599     { Bad_Opcode },
9600     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9601   },
9602
9603   /* VEX_LEN_0F3836_P_2 */
9604   {
9605     { Bad_Opcode },
9606     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9607   },
9608
9609   /* VEX_LEN_0F3841_P_2 */
9610   {
9611     { "vphminposuw",    { XM, EXx }, 0 },
9612   },
9613
9614   /* VEX_LEN_0F385A_P_2_M_0 */
9615   {
9616     { Bad_Opcode },
9617     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9618   },
9619
9620   /* VEX_LEN_0F38DB_P_2 */
9621   {
9622     { "vaesimc",        { XM, EXx }, 0 },
9623   },
9624
9625   /* VEX_LEN_0F38F2_P_0 */
9626   {
9627     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9628   },
9629
9630   /* VEX_LEN_0F38F3_R_1_P_0 */
9631   {
9632     { "blsrS",          { VexGdq, Edq }, 0 },
9633   },
9634
9635   /* VEX_LEN_0F38F3_R_2_P_0 */
9636   {
9637     { "blsmskS",        { VexGdq, Edq }, 0 },
9638   },
9639
9640   /* VEX_LEN_0F38F3_R_3_P_0 */
9641   {
9642     { "blsiS",          { VexGdq, Edq }, 0 },
9643   },
9644
9645   /* VEX_LEN_0F38F5_P_0 */
9646   {
9647     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9648   },
9649
9650   /* VEX_LEN_0F38F5_P_1 */
9651   {
9652     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9653   },
9654
9655   /* VEX_LEN_0F38F5_P_3 */
9656   {
9657     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9658   },
9659
9660   /* VEX_LEN_0F38F6_P_3 */
9661   {
9662     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9663   },
9664
9665   /* VEX_LEN_0F38F7_P_0 */
9666   {
9667     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9668   },
9669
9670   /* VEX_LEN_0F38F7_P_1 */
9671   {
9672     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9673   },
9674
9675   /* VEX_LEN_0F38F7_P_2 */
9676   {
9677     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9678   },
9679
9680   /* VEX_LEN_0F38F7_P_3 */
9681   {
9682     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9683   },
9684
9685   /* VEX_LEN_0F3A00_P_2 */
9686   {
9687     { Bad_Opcode },
9688     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9689   },
9690
9691   /* VEX_LEN_0F3A01_P_2 */
9692   {
9693     { Bad_Opcode },
9694     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9695   },
9696
9697   /* VEX_LEN_0F3A06_P_2 */
9698   {
9699     { Bad_Opcode },
9700     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9701   },
9702
9703   /* VEX_LEN_0F3A14_P_2 */
9704   {
9705     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9706   },
9707
9708   /* VEX_LEN_0F3A15_P_2 */
9709   {
9710     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9711   },
9712
9713   /* VEX_LEN_0F3A16_P_2  */
9714   {
9715     { "vpextrK",        { Edq, XM, Ib }, 0 },
9716   },
9717
9718   /* VEX_LEN_0F3A17_P_2 */
9719   {
9720     { "vextractps",     { Edqd, XM, Ib }, 0 },
9721   },
9722
9723   /* VEX_LEN_0F3A18_P_2 */
9724   {
9725     { Bad_Opcode },
9726     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9727   },
9728
9729   /* VEX_LEN_0F3A19_P_2 */
9730   {
9731     { Bad_Opcode },
9732     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9733   },
9734
9735   /* VEX_LEN_0F3A20_P_2 */
9736   {
9737     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9738   },
9739
9740   /* VEX_LEN_0F3A21_P_2 */
9741   {
9742     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9743   },
9744
9745   /* VEX_LEN_0F3A22_P_2 */
9746   {
9747     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9748   },
9749
9750   /* VEX_LEN_0F3A30_P_2 */
9751   {
9752     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9753   },
9754
9755   /* VEX_LEN_0F3A31_P_2 */
9756   {
9757     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9758   },
9759
9760   /* VEX_LEN_0F3A32_P_2 */
9761   {
9762     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9763   },
9764
9765   /* VEX_LEN_0F3A33_P_2 */
9766   {
9767     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9768   },
9769
9770   /* VEX_LEN_0F3A38_P_2 */
9771   {
9772     { Bad_Opcode },
9773     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9774   },
9775
9776   /* VEX_LEN_0F3A39_P_2 */
9777   {
9778     { Bad_Opcode },
9779     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9780   },
9781
9782   /* VEX_LEN_0F3A41_P_2 */
9783   {
9784     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9785   },
9786
9787   /* VEX_LEN_0F3A46_P_2 */
9788   {
9789     { Bad_Opcode },
9790     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9791   },
9792
9793   /* VEX_LEN_0F3A60_P_2 */
9794   {
9795     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9796   },
9797
9798   /* VEX_LEN_0F3A61_P_2 */
9799   {
9800     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9801   },
9802
9803   /* VEX_LEN_0F3A62_P_2 */
9804   {
9805     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9806   },
9807
9808   /* VEX_LEN_0F3A63_P_2 */
9809   {
9810     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9811   },
9812
9813   /* VEX_LEN_0F3A6A_P_2 */
9814   {
9815     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9816   },
9817
9818   /* VEX_LEN_0F3A6B_P_2 */
9819   {
9820     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9821   },
9822
9823   /* VEX_LEN_0F3A6E_P_2 */
9824   {
9825     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9826   },
9827
9828   /* VEX_LEN_0F3A6F_P_2 */
9829   {
9830     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9831   },
9832
9833   /* VEX_LEN_0F3A7A_P_2 */
9834   {
9835     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9836   },
9837
9838   /* VEX_LEN_0F3A7B_P_2 */
9839   {
9840     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9841   },
9842
9843   /* VEX_LEN_0F3A7E_P_2 */
9844   {
9845     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9846   },
9847
9848   /* VEX_LEN_0F3A7F_P_2 */
9849   {
9850     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9851   },
9852
9853   /* VEX_LEN_0F3ADF_P_2 */
9854   {
9855     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9856   },
9857
9858   /* VEX_LEN_0F3AF0_P_3 */
9859   {
9860     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9861   },
9862
9863   /* VEX_LEN_0FXOP_08_CC */
9864   {
9865      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9866   },
9867
9868   /* VEX_LEN_0FXOP_08_CD */
9869   {
9870      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9871   },
9872
9873   /* VEX_LEN_0FXOP_08_CE */
9874   {
9875      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9876   },
9877
9878   /* VEX_LEN_0FXOP_08_CF */
9879   {
9880      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9881   },
9882
9883   /* VEX_LEN_0FXOP_08_EC */
9884   {
9885      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9886   },
9887
9888   /* VEX_LEN_0FXOP_08_ED */
9889   {
9890      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9891   },
9892
9893   /* VEX_LEN_0FXOP_08_EE */
9894   {
9895      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9896   },
9897
9898   /* VEX_LEN_0FXOP_08_EF */
9899   {
9900      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9901   },
9902
9903   /* VEX_LEN_0FXOP_09_80 */
9904   {
9905     { "vfrczps",        { XM, EXxmm }, 0 },
9906     { "vfrczps",        { XM, EXymmq }, 0 },
9907   },
9908
9909   /* VEX_LEN_0FXOP_09_81 */
9910   {
9911     { "vfrczpd",        { XM, EXxmm }, 0 },
9912     { "vfrczpd",        { XM, EXymmq }, 0 },
9913   },
9914 };
9915
9916 #include "i386-dis-evex-len.h"
9917
9918 static const struct dis386 vex_w_table[][2] = {
9919   {
9920     /* VEX_W_0F41_P_0_LEN_1 */
9921     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9922     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9923   },
9924   {
9925     /* VEX_W_0F41_P_2_LEN_1 */
9926     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9927     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9928   },
9929   {
9930     /* VEX_W_0F42_P_0_LEN_1 */
9931     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9932     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9933   },
9934   {
9935     /* VEX_W_0F42_P_2_LEN_1 */
9936     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9937     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9938   },
9939   {
9940     /* VEX_W_0F44_P_0_LEN_0 */
9941     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9942     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9943   },
9944   {
9945     /* VEX_W_0F44_P_2_LEN_0 */
9946     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9947     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9948   },
9949   {
9950     /* VEX_W_0F45_P_0_LEN_1 */
9951     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9952     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9953   },
9954   {
9955     /* VEX_W_0F45_P_2_LEN_1 */
9956     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9957     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9958   },
9959   {
9960     /* VEX_W_0F46_P_0_LEN_1 */
9961     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9962     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9963   },
9964   {
9965     /* VEX_W_0F46_P_2_LEN_1 */
9966     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9967     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9968   },
9969   {
9970     /* VEX_W_0F47_P_0_LEN_1 */
9971     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9972     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9973   },
9974   {
9975     /* VEX_W_0F47_P_2_LEN_1 */
9976     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9977     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9978   },
9979   {
9980     /* VEX_W_0F4A_P_0_LEN_1 */
9981     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9982     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9983   },
9984   {
9985     /* VEX_W_0F4A_P_2_LEN_1 */
9986     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9987     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9988   },
9989   {
9990     /* VEX_W_0F4B_P_0_LEN_1 */
9991     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9992     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9993   },
9994   {
9995     /* VEX_W_0F4B_P_2_LEN_1 */
9996     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9997   },
9998   {
9999     /* VEX_W_0F90_P_0_LEN_0 */
10000     { "kmovw",          { MaskG, MaskE }, 0 },
10001     { "kmovq",          { MaskG, MaskE }, 0 },
10002   },
10003   {
10004     /* VEX_W_0F90_P_2_LEN_0 */
10005     { "kmovb",          { MaskG, MaskBDE }, 0 },
10006     { "kmovd",          { MaskG, MaskBDE }, 0 },
10007   },
10008   {
10009     /* VEX_W_0F91_P_0_LEN_0 */
10010     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10011     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10012   },
10013   {
10014     /* VEX_W_0F91_P_2_LEN_0 */
10015     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10016     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10017   },
10018   {
10019     /* VEX_W_0F92_P_0_LEN_0 */
10020     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10021   },
10022   {
10023     /* VEX_W_0F92_P_2_LEN_0 */
10024     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10025   },
10026   {
10027     /* VEX_W_0F93_P_0_LEN_0 */
10028     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10029   },
10030   {
10031     /* VEX_W_0F93_P_2_LEN_0 */
10032     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10033   },
10034   {
10035     /* VEX_W_0F98_P_0_LEN_0 */
10036     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10037     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10038   },
10039   {
10040     /* VEX_W_0F98_P_2_LEN_0 */
10041     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10042     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10043   },
10044   {
10045     /* VEX_W_0F99_P_0_LEN_0 */
10046     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10047     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10048   },
10049   {
10050     /* VEX_W_0F99_P_2_LEN_0 */
10051     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10052     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10053   },
10054   {
10055     /* VEX_W_0F380C_P_2  */
10056     { "vpermilps",      { XM, Vex, EXx }, 0 },
10057   },
10058   {
10059     /* VEX_W_0F380D_P_2  */
10060     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10061   },
10062   {
10063     /* VEX_W_0F380E_P_2  */
10064     { "vtestps",        { XM, EXx }, 0 },
10065   },
10066   {
10067     /* VEX_W_0F380F_P_2  */
10068     { "vtestpd",        { XM, EXx }, 0 },
10069   },
10070   {
10071     /* VEX_W_0F3816_P_2  */
10072     { "vpermps",        { XM, Vex, EXx }, 0 },
10073   },
10074   {
10075     /* VEX_W_0F3818_P_2 */
10076     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10077   },
10078   {
10079     /* VEX_W_0F3819_P_2 */
10080     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10081   },
10082   {
10083     /* VEX_W_0F381A_P_2_M_0 */
10084     { "vbroadcastf128", { XM, Mxmm }, 0 },
10085   },
10086   {
10087     /* VEX_W_0F382C_P_2_M_0 */
10088     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10089   },
10090   {
10091     /* VEX_W_0F382D_P_2_M_0 */
10092     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10093   },
10094   {
10095     /* VEX_W_0F382E_P_2_M_0 */
10096     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10097   },
10098   {
10099     /* VEX_W_0F382F_P_2_M_0 */
10100     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10101   },
10102   {
10103     /* VEX_W_0F3836_P_2  */
10104     { "vpermd",         { XM, Vex, EXx }, 0 },
10105   },
10106   {
10107     /* VEX_W_0F3846_P_2 */
10108     { "vpsravd",        { XM, Vex, EXx }, 0 },
10109   },
10110   {
10111     /* VEX_W_0F3858_P_2 */
10112     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10113   },
10114   {
10115     /* VEX_W_0F3859_P_2 */
10116     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10117   },
10118   {
10119     /* VEX_W_0F385A_P_2_M_0 */
10120     { "vbroadcasti128", { XM, Mxmm }, 0 },
10121   },
10122   {
10123     /* VEX_W_0F3878_P_2 */
10124     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10125   },
10126   {
10127     /* VEX_W_0F3879_P_2 */
10128     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10129   },
10130   {
10131     /* VEX_W_0F38CF_P_2 */
10132     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10133   },
10134   {
10135     /* VEX_W_0F3A00_P_2 */
10136     { Bad_Opcode },
10137     { "vpermq",         { XM, EXx, Ib }, 0 },
10138   },
10139   {
10140     /* VEX_W_0F3A01_P_2 */
10141     { Bad_Opcode },
10142     { "vpermpd",        { XM, EXx, Ib }, 0 },
10143   },
10144   {
10145     /* VEX_W_0F3A02_P_2 */
10146     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10147   },
10148   {
10149     /* VEX_W_0F3A04_P_2 */
10150     { "vpermilps",      { XM, EXx, Ib }, 0 },
10151   },
10152   {
10153     /* VEX_W_0F3A05_P_2 */
10154     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10155   },
10156   {
10157     /* VEX_W_0F3A06_P_2 */
10158     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10159   },
10160   {
10161     /* VEX_W_0F3A18_P_2 */
10162     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10163   },
10164   {
10165     /* VEX_W_0F3A19_P_2 */
10166     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10167   },
10168   {
10169     /* VEX_W_0F3A30_P_2_LEN_0 */
10170     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10171     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10172   },
10173   {
10174     /* VEX_W_0F3A31_P_2_LEN_0 */
10175     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10176     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10177   },
10178   {
10179     /* VEX_W_0F3A32_P_2_LEN_0 */
10180     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10181     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10182   },
10183   {
10184     /* VEX_W_0F3A33_P_2_LEN_0 */
10185     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10186     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10187   },
10188   {
10189     /* VEX_W_0F3A38_P_2 */
10190     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10191   },
10192   {
10193     /* VEX_W_0F3A39_P_2 */
10194     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10195   },
10196   {
10197     /* VEX_W_0F3A46_P_2 */
10198     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10199   },
10200   {
10201     /* VEX_W_0F3A48_P_2 */
10202     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10203     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10204   },
10205   {
10206     /* VEX_W_0F3A49_P_2 */
10207     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10208     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10209   },
10210   {
10211     /* VEX_W_0F3A4A_P_2 */
10212     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10213   },
10214   {
10215     /* VEX_W_0F3A4B_P_2 */
10216     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10217   },
10218   {
10219     /* VEX_W_0F3A4C_P_2 */
10220     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10221   },
10222   {
10223     /* VEX_W_0F3ACE_P_2 */
10224     { Bad_Opcode },
10225     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10226   },
10227   {
10228     /* VEX_W_0F3ACF_P_2 */
10229     { Bad_Opcode },
10230     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10231   },
10232
10233 #include "i386-dis-evex-w.h"
10234 };
10235
10236 static const struct dis386 mod_table[][2] = {
10237   {
10238     /* MOD_8D */
10239     { "leaS",           { Gv, M }, 0 },
10240   },
10241   {
10242     /* MOD_C6_REG_7 */
10243     { Bad_Opcode },
10244     { RM_TABLE (RM_C6_REG_7) },
10245   },
10246   {
10247     /* MOD_C7_REG_7 */
10248     { Bad_Opcode },
10249     { RM_TABLE (RM_C7_REG_7) },
10250   },
10251   {
10252     /* MOD_FF_REG_3 */
10253     { "Jcall^", { indirEp }, 0 },
10254   },
10255   {
10256     /* MOD_FF_REG_5 */
10257     { "Jjmp^", { indirEp }, 0 },
10258   },
10259   {
10260     /* MOD_0F01_REG_0 */
10261     { X86_64_TABLE (X86_64_0F01_REG_0) },
10262     { RM_TABLE (RM_0F01_REG_0) },
10263   },
10264   {
10265     /* MOD_0F01_REG_1 */
10266     { X86_64_TABLE (X86_64_0F01_REG_1) },
10267     { RM_TABLE (RM_0F01_REG_1) },
10268   },
10269   {
10270     /* MOD_0F01_REG_2 */
10271     { X86_64_TABLE (X86_64_0F01_REG_2) },
10272     { RM_TABLE (RM_0F01_REG_2) },
10273   },
10274   {
10275     /* MOD_0F01_REG_3 */
10276     { X86_64_TABLE (X86_64_0F01_REG_3) },
10277     { RM_TABLE (RM_0F01_REG_3) },
10278   },
10279   {
10280     /* MOD_0F01_REG_5 */
10281     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10282     { RM_TABLE (RM_0F01_REG_5) },
10283   },
10284   {
10285     /* MOD_0F01_REG_7 */
10286     { "invlpg",         { Mb }, 0 },
10287     { RM_TABLE (RM_0F01_REG_7) },
10288   },
10289   {
10290     /* MOD_0F12_PREFIX_0 */
10291     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10292     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10293   },
10294   {
10295     /* MOD_0F13 */
10296     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10297   },
10298   {
10299     /* MOD_0F16_PREFIX_0 */
10300     { "movhps",         { XM, EXq }, 0 },
10301     { "movlhps",        { XM, EXq }, 0 },
10302   },
10303   {
10304     /* MOD_0F17 */
10305     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10306   },
10307   {
10308     /* MOD_0F18_REG_0 */
10309     { "prefetchnta",    { Mb }, 0 },
10310   },
10311   {
10312     /* MOD_0F18_REG_1 */
10313     { "prefetcht0",     { Mb }, 0 },
10314   },
10315   {
10316     /* MOD_0F18_REG_2 */
10317     { "prefetcht1",     { Mb }, 0 },
10318   },
10319   {
10320     /* MOD_0F18_REG_3 */
10321     { "prefetcht2",     { Mb }, 0 },
10322   },
10323   {
10324     /* MOD_0F18_REG_4 */
10325     { "nop/reserved",   { Mb }, 0 },
10326   },
10327   {
10328     /* MOD_0F18_REG_5 */
10329     { "nop/reserved",   { Mb }, 0 },
10330   },
10331   {
10332     /* MOD_0F18_REG_6 */
10333     { "nop/reserved",   { Mb }, 0 },
10334   },
10335   {
10336     /* MOD_0F18_REG_7 */
10337     { "nop/reserved",   { Mb }, 0 },
10338   },
10339   {
10340     /* MOD_0F1A_PREFIX_0 */
10341     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10342     { "nopQ",           { Ev }, 0 },
10343   },
10344   {
10345     /* MOD_0F1B_PREFIX_0 */
10346     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10347     { "nopQ",           { Ev }, 0 },
10348   },
10349   {
10350     /* MOD_0F1B_PREFIX_1 */
10351     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10352     { "nopQ",           { Ev }, 0 },
10353   },
10354   {
10355     /* MOD_0F1C_PREFIX_0 */
10356     { REG_TABLE (REG_0F1C_MOD_0) },
10357     { "nopQ",           { Ev }, 0 },
10358   },
10359   {
10360     /* MOD_0F1E_PREFIX_1 */
10361     { "nopQ",           { Ev }, 0 },
10362     { REG_TABLE (REG_0F1E_MOD_3) },
10363   },
10364   {
10365     /* MOD_0F24 */
10366     { Bad_Opcode },
10367     { "movL",           { Rd, Td }, 0 },
10368   },
10369   {
10370     /* MOD_0F26 */
10371     { Bad_Opcode },
10372     { "movL",           { Td, Rd }, 0 },
10373   },
10374   {
10375     /* MOD_0F2B_PREFIX_0 */
10376     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10377   },
10378   {
10379     /* MOD_0F2B_PREFIX_1 */
10380     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10381   },
10382   {
10383     /* MOD_0F2B_PREFIX_2 */
10384     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10385   },
10386   {
10387     /* MOD_0F2B_PREFIX_3 */
10388     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10389   },
10390   {
10391     /* MOD_0F51 */
10392     { Bad_Opcode },
10393     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10394   },
10395   {
10396     /* MOD_0F71_REG_2 */
10397     { Bad_Opcode },
10398     { "psrlw",          { MS, Ib }, 0 },
10399   },
10400   {
10401     /* MOD_0F71_REG_4 */
10402     { Bad_Opcode },
10403     { "psraw",          { MS, Ib }, 0 },
10404   },
10405   {
10406     /* MOD_0F71_REG_6 */
10407     { Bad_Opcode },
10408     { "psllw",          { MS, Ib }, 0 },
10409   },
10410   {
10411     /* MOD_0F72_REG_2 */
10412     { Bad_Opcode },
10413     { "psrld",          { MS, Ib }, 0 },
10414   },
10415   {
10416     /* MOD_0F72_REG_4 */
10417     { Bad_Opcode },
10418     { "psrad",          { MS, Ib }, 0 },
10419   },
10420   {
10421     /* MOD_0F72_REG_6 */
10422     { Bad_Opcode },
10423     { "pslld",          { MS, Ib }, 0 },
10424   },
10425   {
10426     /* MOD_0F73_REG_2 */
10427     { Bad_Opcode },
10428     { "psrlq",          { MS, Ib }, 0 },
10429   },
10430   {
10431     /* MOD_0F73_REG_3 */
10432     { Bad_Opcode },
10433     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10434   },
10435   {
10436     /* MOD_0F73_REG_6 */
10437     { Bad_Opcode },
10438     { "psllq",          { MS, Ib }, 0 },
10439   },
10440   {
10441     /* MOD_0F73_REG_7 */
10442     { Bad_Opcode },
10443     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10444   },
10445   {
10446     /* MOD_0FAE_REG_0 */
10447     { "fxsave",         { FXSAVE }, 0 },
10448     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10449   },
10450   {
10451     /* MOD_0FAE_REG_1 */
10452     { "fxrstor",        { FXSAVE }, 0 },
10453     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10454   },
10455   {
10456     /* MOD_0FAE_REG_2 */
10457     { "ldmxcsr",        { Md }, 0 },
10458     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10459   },
10460   {
10461     /* MOD_0FAE_REG_3 */
10462     { "stmxcsr",        { Md }, 0 },
10463     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10464   },
10465   {
10466     /* MOD_0FAE_REG_4 */
10467     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10468     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10469   },
10470   {
10471     /* MOD_0FAE_REG_5 */
10472     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10473     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10474   },
10475   {
10476     /* MOD_0FAE_REG_6 */
10477     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10478     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10479   },
10480   {
10481     /* MOD_0FAE_REG_7 */
10482     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10483     { RM_TABLE (RM_0FAE_REG_7) },
10484   },
10485   {
10486     /* MOD_0FB2 */
10487     { "lssS",           { Gv, Mp }, 0 },
10488   },
10489   {
10490     /* MOD_0FB4 */
10491     { "lfsS",           { Gv, Mp }, 0 },
10492   },
10493   {
10494     /* MOD_0FB5 */
10495     { "lgsS",           { Gv, Mp }, 0 },
10496   },
10497   {
10498     /* MOD_0FC3 */
10499     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10500   },
10501   {
10502     /* MOD_0FC7_REG_3 */
10503     { "xrstors",        { FXSAVE }, 0 },
10504   },
10505   {
10506     /* MOD_0FC7_REG_4 */
10507     { "xsavec",         { FXSAVE }, 0 },
10508   },
10509   {
10510     /* MOD_0FC7_REG_5 */
10511     { "xsaves",         { FXSAVE }, 0 },
10512   },
10513   {
10514     /* MOD_0FC7_REG_6 */
10515     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10516     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10517   },
10518   {
10519     /* MOD_0FC7_REG_7 */
10520     { "vmptrst",        { Mq }, 0 },
10521     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10522   },
10523   {
10524     /* MOD_0FD7 */
10525     { Bad_Opcode },
10526     { "pmovmskb",       { Gdq, MS }, 0 },
10527   },
10528   {
10529     /* MOD_0FE7_PREFIX_2 */
10530     { "movntdq",        { Mx, XM }, 0 },
10531   },
10532   {
10533     /* MOD_0FF0_PREFIX_3 */
10534     { "lddqu",          { XM, M }, 0 },
10535   },
10536   {
10537     /* MOD_0F382A_PREFIX_2 */
10538     { "movntdqa",       { XM, Mx }, 0 },
10539   },
10540   {
10541     /* MOD_0F38F5_PREFIX_2 */
10542     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10543   },
10544   {
10545     /* MOD_0F38F6_PREFIX_0 */
10546     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10547   },
10548   {
10549     /* MOD_0F38F8_PREFIX_1 */
10550     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10551   },
10552   {
10553     /* MOD_0F38F8_PREFIX_2 */
10554     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10555   },
10556   {
10557     /* MOD_0F38F8_PREFIX_3 */
10558     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10559   },
10560   {
10561     /* MOD_0F38F9_PREFIX_0 */
10562     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10563   },
10564   {
10565     /* MOD_62_32BIT */
10566     { "bound{S|}",      { Gv, Ma }, 0 },
10567     { EVEX_TABLE (EVEX_0F) },
10568   },
10569   {
10570     /* MOD_C4_32BIT */
10571     { "lesS",           { Gv, Mp }, 0 },
10572     { VEX_C4_TABLE (VEX_0F) },
10573   },
10574   {
10575     /* MOD_C5_32BIT */
10576     { "ldsS",           { Gv, Mp }, 0 },
10577     { VEX_C5_TABLE (VEX_0F) },
10578   },
10579   {
10580     /* MOD_VEX_0F12_PREFIX_0 */
10581     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10582     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10583   },
10584   {
10585     /* MOD_VEX_0F13 */
10586     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10587   },
10588   {
10589     /* MOD_VEX_0F16_PREFIX_0 */
10590     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10591     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10592   },
10593   {
10594     /* MOD_VEX_0F17 */
10595     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10596   },
10597   {
10598     /* MOD_VEX_0F2B */
10599     { "vmovntpX",       { Mx, XM }, 0 },
10600   },
10601   {
10602     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10603     { Bad_Opcode },
10604     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10605   },
10606   {
10607     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10608     { Bad_Opcode },
10609     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10610   },
10611   {
10612     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10613     { Bad_Opcode },
10614     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10615   },
10616   {
10617     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10618     { Bad_Opcode },
10619     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10620   },
10621   {
10622     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10623     { Bad_Opcode },
10624     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10625   },
10626   {
10627     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10628     { Bad_Opcode },
10629     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10630   },
10631   {
10632     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10633     { Bad_Opcode },
10634     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10635   },
10636   {
10637     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10638     { Bad_Opcode },
10639     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10640   },
10641   {
10642     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10643     { Bad_Opcode },
10644     { "knotw",          { MaskG, MaskR }, 0 },
10645   },
10646   {
10647     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10648     { Bad_Opcode },
10649     { "knotq",          { MaskG, MaskR }, 0 },
10650   },
10651   {
10652     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10653     { Bad_Opcode },
10654     { "knotb",          { MaskG, MaskR }, 0 },
10655   },
10656   {
10657     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10658     { Bad_Opcode },
10659     { "knotd",          { MaskG, MaskR }, 0 },
10660   },
10661   {
10662     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10663     { Bad_Opcode },
10664     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10665   },
10666   {
10667     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10668     { Bad_Opcode },
10669     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10670   },
10671   {
10672     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10673     { Bad_Opcode },
10674     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10675   },
10676   {
10677     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10678     { Bad_Opcode },
10679     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10680   },
10681  {
10682     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10683     { Bad_Opcode },
10684     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10685   },
10686   {
10687     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10688     { Bad_Opcode },
10689     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10690   },
10691   {
10692     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10693     { Bad_Opcode },
10694     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10695   },
10696   {
10697     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10698     { Bad_Opcode },
10699     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10700   },
10701   {
10702     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10703     { Bad_Opcode },
10704     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10705   },
10706   {
10707     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10708     { Bad_Opcode },
10709     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10710   },
10711   {
10712     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10713     { Bad_Opcode },
10714     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10715   },
10716   {
10717     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10718     { Bad_Opcode },
10719     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10720   },
10721   {
10722     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10723     { Bad_Opcode },
10724     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10725   },
10726   {
10727     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10728     { Bad_Opcode },
10729     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10730   },
10731   {
10732     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10733     { Bad_Opcode },
10734     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10735   },
10736   {
10737     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10738     { Bad_Opcode },
10739     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10740   },
10741   {
10742     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10743     { Bad_Opcode },
10744     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10745   },
10746   {
10747     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10748     { Bad_Opcode },
10749     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10750   },
10751   {
10752     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10753     { Bad_Opcode },
10754     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10755   },
10756   {
10757     /* MOD_VEX_0F50 */
10758     { Bad_Opcode },
10759     { "vmovmskpX",      { Gdq, XS }, 0 },
10760   },
10761   {
10762     /* MOD_VEX_0F71_REG_2 */
10763     { Bad_Opcode },
10764     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10765   },
10766   {
10767     /* MOD_VEX_0F71_REG_4 */
10768     { Bad_Opcode },
10769     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10770   },
10771   {
10772     /* MOD_VEX_0F71_REG_6 */
10773     { Bad_Opcode },
10774     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10775   },
10776   {
10777     /* MOD_VEX_0F72_REG_2 */
10778     { Bad_Opcode },
10779     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10780   },
10781   {
10782     /* MOD_VEX_0F72_REG_4 */
10783     { Bad_Opcode },
10784     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10785   },
10786   {
10787     /* MOD_VEX_0F72_REG_6 */
10788     { Bad_Opcode },
10789     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10790   },
10791   {
10792     /* MOD_VEX_0F73_REG_2 */
10793     { Bad_Opcode },
10794     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10795   },
10796   {
10797     /* MOD_VEX_0F73_REG_3 */
10798     { Bad_Opcode },
10799     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10800   },
10801   {
10802     /* MOD_VEX_0F73_REG_6 */
10803     { Bad_Opcode },
10804     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10805   },
10806   {
10807     /* MOD_VEX_0F73_REG_7 */
10808     { Bad_Opcode },
10809     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10810   },
10811   {
10812     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10813     { "kmovw",          { Ew, MaskG }, 0 },
10814     { Bad_Opcode },
10815   },
10816   {
10817     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10818     { "kmovq",          { Eq, MaskG }, 0 },
10819     { Bad_Opcode },
10820   },
10821   {
10822     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10823     { "kmovb",          { Eb, MaskG }, 0 },
10824     { Bad_Opcode },
10825   },
10826   {
10827     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10828     { "kmovd",          { Ed, MaskG }, 0 },
10829     { Bad_Opcode },
10830   },
10831   {
10832     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10833     { Bad_Opcode },
10834     { "kmovw",          { MaskG, Rdq }, 0 },
10835   },
10836   {
10837     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10838     { Bad_Opcode },
10839     { "kmovb",          { MaskG, Rdq }, 0 },
10840   },
10841   {
10842     /* MOD_VEX_0F92_P_3_LEN_0 */
10843     { Bad_Opcode },
10844     { "kmovK",          { MaskG, Rdq }, 0 },
10845   },
10846   {
10847     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10848     { Bad_Opcode },
10849     { "kmovw",          { Gdq, MaskR }, 0 },
10850   },
10851   {
10852     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10853     { Bad_Opcode },
10854     { "kmovb",          { Gdq, MaskR }, 0 },
10855   },
10856   {
10857     /* MOD_VEX_0F93_P_3_LEN_0 */
10858     { Bad_Opcode },
10859     { "kmovK",          { Gdq, MaskR }, 0 },
10860   },
10861   {
10862     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10863     { Bad_Opcode },
10864     { "kortestw", { MaskG, MaskR }, 0 },
10865   },
10866   {
10867     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10868     { Bad_Opcode },
10869     { "kortestq", { MaskG, MaskR }, 0 },
10870   },
10871   {
10872     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10873     { Bad_Opcode },
10874     { "kortestb", { MaskG, MaskR }, 0 },
10875   },
10876   {
10877     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10878     { Bad_Opcode },
10879     { "kortestd", { MaskG, MaskR }, 0 },
10880   },
10881   {
10882     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10883     { Bad_Opcode },
10884     { "ktestw", { MaskG, MaskR }, 0 },
10885   },
10886   {
10887     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10888     { Bad_Opcode },
10889     { "ktestq", { MaskG, MaskR }, 0 },
10890   },
10891   {
10892     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10893     { Bad_Opcode },
10894     { "ktestb", { MaskG, MaskR }, 0 },
10895   },
10896   {
10897     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10898     { Bad_Opcode },
10899     { "ktestd", { MaskG, MaskR }, 0 },
10900   },
10901   {
10902     /* MOD_VEX_0FAE_REG_2 */
10903     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10904   },
10905   {
10906     /* MOD_VEX_0FAE_REG_3 */
10907     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10908   },
10909   {
10910     /* MOD_VEX_0FD7_PREFIX_2 */
10911     { Bad_Opcode },
10912     { "vpmovmskb",      { Gdq, XS }, 0 },
10913   },
10914   {
10915     /* MOD_VEX_0FE7_PREFIX_2 */
10916     { "vmovntdq",       { Mx, XM }, 0 },
10917   },
10918   {
10919     /* MOD_VEX_0FF0_PREFIX_3 */
10920     { "vlddqu",         { XM, M }, 0 },
10921   },
10922   {
10923     /* MOD_VEX_0F381A_PREFIX_2 */
10924     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10925   },
10926   {
10927     /* MOD_VEX_0F382A_PREFIX_2 */
10928     { "vmovntdqa",      { XM, Mx }, 0 },
10929   },
10930   {
10931     /* MOD_VEX_0F382C_PREFIX_2 */
10932     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10933   },
10934   {
10935     /* MOD_VEX_0F382D_PREFIX_2 */
10936     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10937   },
10938   {
10939     /* MOD_VEX_0F382E_PREFIX_2 */
10940     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10941   },
10942   {
10943     /* MOD_VEX_0F382F_PREFIX_2 */
10944     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10945   },
10946   {
10947     /* MOD_VEX_0F385A_PREFIX_2 */
10948     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10949   },
10950   {
10951     /* MOD_VEX_0F388C_PREFIX_2 */
10952     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10953   },
10954   {
10955     /* MOD_VEX_0F388E_PREFIX_2 */
10956     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10957   },
10958   {
10959     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10960     { Bad_Opcode },
10961     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10962   },
10963   {
10964     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10965     { Bad_Opcode },
10966     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10967   },
10968   {
10969     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10970     { Bad_Opcode },
10971     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10972   },
10973   {
10974     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10975     { Bad_Opcode },
10976     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10977   },
10978   {
10979     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10980     { Bad_Opcode },
10981     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10982   },
10983   {
10984     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10985     { Bad_Opcode },
10986     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10987   },
10988   {
10989     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10990     { Bad_Opcode },
10991     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10992   },
10993   {
10994     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10995     { Bad_Opcode },
10996     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10997   },
10998
10999 #include "i386-dis-evex-mod.h"
11000 };
11001
11002 static const struct dis386 rm_table[][8] = {
11003   {
11004     /* RM_C6_REG_7 */
11005     { "xabort",         { Skip_MODRM, Ib }, 0 },
11006   },
11007   {
11008     /* RM_C7_REG_7 */
11009     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
11010   },
11011   {
11012     /* RM_0F01_REG_0 */
11013     { "enclv",          { Skip_MODRM }, 0 },
11014     { "vmcall",         { Skip_MODRM }, 0 },
11015     { "vmlaunch",       { Skip_MODRM }, 0 },
11016     { "vmresume",       { Skip_MODRM }, 0 },
11017     { "vmxoff",         { Skip_MODRM }, 0 },
11018     { "pconfig",        { Skip_MODRM }, 0 },
11019   },
11020   {
11021     /* RM_0F01_REG_1 */
11022     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11023     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11024     { "clac",           { Skip_MODRM }, 0 },
11025     { "stac",           { Skip_MODRM }, 0 },
11026     { Bad_Opcode },
11027     { Bad_Opcode },
11028     { Bad_Opcode },
11029     { "encls",          { Skip_MODRM }, 0 },
11030   },
11031   {
11032     /* RM_0F01_REG_2 */
11033     { "xgetbv",         { Skip_MODRM }, 0 },
11034     { "xsetbv",         { Skip_MODRM }, 0 },
11035     { Bad_Opcode },
11036     { Bad_Opcode },
11037     { "vmfunc",         { Skip_MODRM }, 0 },
11038     { "xend",           { Skip_MODRM }, 0 },
11039     { "xtest",          { Skip_MODRM }, 0 },
11040     { "enclu",          { Skip_MODRM }, 0 },
11041   },
11042   {
11043     /* RM_0F01_REG_3 */
11044     { "vmrun",          { Skip_MODRM }, 0 },
11045     { "vmmcall",        { Skip_MODRM }, 0 },
11046     { "vmload",         { Skip_MODRM }, 0 },
11047     { "vmsave",         { Skip_MODRM }, 0 },
11048     { "stgi",           { Skip_MODRM }, 0 },
11049     { "clgi",           { Skip_MODRM }, 0 },
11050     { "skinit",         { Skip_MODRM }, 0 },
11051     { "invlpga",        { Skip_MODRM }, 0 },
11052   },
11053   {
11054     /* RM_0F01_REG_5 */
11055     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11056     { Bad_Opcode },
11057     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11058     { Bad_Opcode },
11059     { Bad_Opcode },
11060     { Bad_Opcode },
11061     { "rdpkru",         { Skip_MODRM }, 0 },
11062     { "wrpkru",         { Skip_MODRM }, 0 },
11063   },
11064   {
11065     /* RM_0F01_REG_7 */
11066     { "swapgs",         { Skip_MODRM }, 0  },
11067     { "rdtscp",         { Skip_MODRM }, 0  },
11068     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
11069     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
11070     { "clzero",         { Skip_MODRM }, 0  },
11071   },
11072   {
11073     /* RM_0F1E_MOD_3_REG_7 */
11074     { "nopQ",           { Ev }, 0 },
11075     { "nopQ",           { Ev }, 0 },
11076     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11077     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11078     { "nopQ",           { Ev }, 0 },
11079     { "nopQ",           { Ev }, 0 },
11080     { "nopQ",           { Ev }, 0 },
11081     { "nopQ",           { Ev }, 0 },
11082   },
11083   {
11084     /* RM_0FAE_REG_6 */
11085     { "mfence",         { Skip_MODRM }, 0 },
11086   },
11087   {
11088     /* RM_0FAE_REG_7 */
11089     { "sfence",         { Skip_MODRM }, 0 },
11090
11091   },
11092 };
11093
11094 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11095
11096 /* We use the high bit to indicate different name for the same
11097    prefix.  */
11098 #define REP_PREFIX      (0xf3 | 0x100)
11099 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11100 #define XRELEASE_PREFIX (0xf3 | 0x400)
11101 #define BND_PREFIX      (0xf2 | 0x400)
11102 #define NOTRACK_PREFIX  (0x3e | 0x100)
11103
11104 static int
11105 ckprefix (void)
11106 {
11107   int newrex, i, length;
11108   rex = 0;
11109   rex_ignored = 0;
11110   prefixes = 0;
11111   used_prefixes = 0;
11112   rex_used = 0;
11113   last_lock_prefix = -1;
11114   last_repz_prefix = -1;
11115   last_repnz_prefix = -1;
11116   last_data_prefix = -1;
11117   last_addr_prefix = -1;
11118   last_rex_prefix = -1;
11119   last_seg_prefix = -1;
11120   fwait_prefix = -1;
11121   active_seg_prefix = 0;
11122   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11123     all_prefixes[i] = 0;
11124   i = 0;
11125   length = 0;
11126   /* The maximum instruction length is 15bytes.  */
11127   while (length < MAX_CODE_LENGTH - 1)
11128     {
11129       FETCH_DATA (the_info, codep + 1);
11130       newrex = 0;
11131       switch (*codep)
11132         {
11133         /* REX prefixes family.  */
11134         case 0x40:
11135         case 0x41:
11136         case 0x42:
11137         case 0x43:
11138         case 0x44:
11139         case 0x45:
11140         case 0x46:
11141         case 0x47:
11142         case 0x48:
11143         case 0x49:
11144         case 0x4a:
11145         case 0x4b:
11146         case 0x4c:
11147         case 0x4d:
11148         case 0x4e:
11149         case 0x4f:
11150           if (address_mode == mode_64bit)
11151             newrex = *codep;
11152           else
11153             return 1;
11154           last_rex_prefix = i;
11155           break;
11156         case 0xf3:
11157           prefixes |= PREFIX_REPZ;
11158           last_repz_prefix = i;
11159           break;
11160         case 0xf2:
11161           prefixes |= PREFIX_REPNZ;
11162           last_repnz_prefix = i;
11163           break;
11164         case 0xf0:
11165           prefixes |= PREFIX_LOCK;
11166           last_lock_prefix = i;
11167           break;
11168         case 0x2e:
11169           prefixes |= PREFIX_CS;
11170           last_seg_prefix = i;
11171           active_seg_prefix = PREFIX_CS;
11172           break;
11173         case 0x36:
11174           prefixes |= PREFIX_SS;
11175           last_seg_prefix = i;
11176           active_seg_prefix = PREFIX_SS;
11177           break;
11178         case 0x3e:
11179           prefixes |= PREFIX_DS;
11180           last_seg_prefix = i;
11181           active_seg_prefix = PREFIX_DS;
11182           break;
11183         case 0x26:
11184           prefixes |= PREFIX_ES;
11185           last_seg_prefix = i;
11186           active_seg_prefix = PREFIX_ES;
11187           break;
11188         case 0x64:
11189           prefixes |= PREFIX_FS;
11190           last_seg_prefix = i;
11191           active_seg_prefix = PREFIX_FS;
11192           break;
11193         case 0x65:
11194           prefixes |= PREFIX_GS;
11195           last_seg_prefix = i;
11196           active_seg_prefix = PREFIX_GS;
11197           break;
11198         case 0x66:
11199           prefixes |= PREFIX_DATA;
11200           last_data_prefix = i;
11201           break;
11202         case 0x67:
11203           prefixes |= PREFIX_ADDR;
11204           last_addr_prefix = i;
11205           break;
11206         case FWAIT_OPCODE:
11207           /* fwait is really an instruction.  If there are prefixes
11208              before the fwait, they belong to the fwait, *not* to the
11209              following instruction.  */
11210           fwait_prefix = i;
11211           if (prefixes || rex)
11212             {
11213               prefixes |= PREFIX_FWAIT;
11214               codep++;
11215               /* This ensures that the previous REX prefixes are noticed
11216                  as unused prefixes, as in the return case below.  */
11217               rex_used = rex;
11218               return 1;
11219             }
11220           prefixes = PREFIX_FWAIT;
11221           break;
11222         default:
11223           return 1;
11224         }
11225       /* Rex is ignored when followed by another prefix.  */
11226       if (rex)
11227         {
11228           rex_used = rex;
11229           return 1;
11230         }
11231       if (*codep != FWAIT_OPCODE)
11232         all_prefixes[i++] = *codep;
11233       rex = newrex;
11234       codep++;
11235       length++;
11236     }
11237   return 0;
11238 }
11239
11240 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11241    prefix byte.  */
11242
11243 static const char *
11244 prefix_name (int pref, int sizeflag)
11245 {
11246   static const char *rexes [16] =
11247     {
11248       "rex",            /* 0x40 */
11249       "rex.B",          /* 0x41 */
11250       "rex.X",          /* 0x42 */
11251       "rex.XB",         /* 0x43 */
11252       "rex.R",          /* 0x44 */
11253       "rex.RB",         /* 0x45 */
11254       "rex.RX",         /* 0x46 */
11255       "rex.RXB",        /* 0x47 */
11256       "rex.W",          /* 0x48 */
11257       "rex.WB",         /* 0x49 */
11258       "rex.WX",         /* 0x4a */
11259       "rex.WXB",        /* 0x4b */
11260       "rex.WR",         /* 0x4c */
11261       "rex.WRB",        /* 0x4d */
11262       "rex.WRX",        /* 0x4e */
11263       "rex.WRXB",       /* 0x4f */
11264     };
11265
11266   switch (pref)
11267     {
11268     /* REX prefixes family.  */
11269     case 0x40:
11270     case 0x41:
11271     case 0x42:
11272     case 0x43:
11273     case 0x44:
11274     case 0x45:
11275     case 0x46:
11276     case 0x47:
11277     case 0x48:
11278     case 0x49:
11279     case 0x4a:
11280     case 0x4b:
11281     case 0x4c:
11282     case 0x4d:
11283     case 0x4e:
11284     case 0x4f:
11285       return rexes [pref - 0x40];
11286     case 0xf3:
11287       return "repz";
11288     case 0xf2:
11289       return "repnz";
11290     case 0xf0:
11291       return "lock";
11292     case 0x2e:
11293       return "cs";
11294     case 0x36:
11295       return "ss";
11296     case 0x3e:
11297       return "ds";
11298     case 0x26:
11299       return "es";
11300     case 0x64:
11301       return "fs";
11302     case 0x65:
11303       return "gs";
11304     case 0x66:
11305       return (sizeflag & DFLAG) ? "data16" : "data32";
11306     case 0x67:
11307       if (address_mode == mode_64bit)
11308         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11309       else
11310         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11311     case FWAIT_OPCODE:
11312       return "fwait";
11313     case REP_PREFIX:
11314       return "rep";
11315     case XACQUIRE_PREFIX:
11316       return "xacquire";
11317     case XRELEASE_PREFIX:
11318       return "xrelease";
11319     case BND_PREFIX:
11320       return "bnd";
11321     case NOTRACK_PREFIX:
11322       return "notrack";
11323     default:
11324       return NULL;
11325     }
11326 }
11327
11328 static char op_out[MAX_OPERANDS][100];
11329 static int op_ad, op_index[MAX_OPERANDS];
11330 static int two_source_ops;
11331 static bfd_vma op_address[MAX_OPERANDS];
11332 static bfd_vma op_riprel[MAX_OPERANDS];
11333 static bfd_vma start_pc;
11334
11335 /*
11336  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11337  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11338  *   section of the "Virtual 8086 Mode" chapter.)
11339  * 'pc' should be the address of this instruction, it will
11340  *   be used to print the target address if this is a relative jump or call
11341  * The function returns the length of this instruction in bytes.
11342  */
11343
11344 static char intel_syntax;
11345 static char intel_mnemonic = !SYSV386_COMPAT;
11346 static char open_char;
11347 static char close_char;
11348 static char separator_char;
11349 static char scale_char;
11350
11351 enum x86_64_isa
11352 {
11353   amd64 = 0,
11354   intel64
11355 };
11356
11357 static enum x86_64_isa isa64;
11358
11359 /* Here for backwards compatibility.  When gdb stops using
11360    print_insn_i386_att and print_insn_i386_intel these functions can
11361    disappear, and print_insn_i386 be merged into print_insn.  */
11362 int
11363 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11364 {
11365   intel_syntax = 0;
11366
11367   return print_insn (pc, info);
11368 }
11369
11370 int
11371 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11372 {
11373   intel_syntax = 1;
11374
11375   return print_insn (pc, info);
11376 }
11377
11378 int
11379 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11380 {
11381   intel_syntax = -1;
11382
11383   return print_insn (pc, info);
11384 }
11385
11386 void
11387 print_i386_disassembler_options (FILE *stream)
11388 {
11389   fprintf (stream, _("\n\
11390 The following i386/x86-64 specific disassembler options are supported for use\n\
11391 with the -M switch (multiple options should be separated by commas):\n"));
11392
11393   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11394   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11395   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11396   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11397   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11398   fprintf (stream, _("  att-mnemonic\n"
11399                      "              Display instruction in AT&T mnemonic\n"));
11400   fprintf (stream, _("  intel-mnemonic\n"
11401                      "              Display instruction in Intel mnemonic\n"));
11402   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11403   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11404   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11405   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11406   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11407   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11408   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11409   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11410 }
11411
11412 /* Bad opcode.  */
11413 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11414
11415 /* Get a pointer to struct dis386 with a valid name.  */
11416
11417 static const struct dis386 *
11418 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11419 {
11420   int vindex, vex_table_index;
11421
11422   if (dp->name != NULL)
11423     return dp;
11424
11425   switch (dp->op[0].bytemode)
11426     {
11427     case USE_REG_TABLE:
11428       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11429       break;
11430
11431     case USE_MOD_TABLE:
11432       vindex = modrm.mod == 0x3 ? 1 : 0;
11433       dp = &mod_table[dp->op[1].bytemode][vindex];
11434       break;
11435
11436     case USE_RM_TABLE:
11437       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11438       break;
11439
11440     case USE_PREFIX_TABLE:
11441       if (need_vex)
11442         {
11443           /* The prefix in VEX is implicit.  */
11444           switch (vex.prefix)
11445             {
11446             case 0:
11447               vindex = 0;
11448               break;
11449             case REPE_PREFIX_OPCODE:
11450               vindex = 1;
11451               break;
11452             case DATA_PREFIX_OPCODE:
11453               vindex = 2;
11454               break;
11455             case REPNE_PREFIX_OPCODE:
11456               vindex = 3;
11457               break;
11458             default:
11459               abort ();
11460               break;
11461             }
11462         }
11463       else
11464         {
11465           int last_prefix = -1;
11466           int prefix = 0;
11467           vindex = 0;
11468           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11469              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11470              last one wins.  */
11471           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11472             {
11473               if (last_repz_prefix > last_repnz_prefix)
11474                 {
11475                   vindex = 1;
11476                   prefix = PREFIX_REPZ;
11477                   last_prefix = last_repz_prefix;
11478                 }
11479               else
11480                 {
11481                   vindex = 3;
11482                   prefix = PREFIX_REPNZ;
11483                   last_prefix = last_repnz_prefix;
11484                 }
11485
11486               /* Check if prefix should be ignored.  */
11487               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11488                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11489                    & prefix) != 0)
11490                 vindex = 0;
11491             }
11492
11493           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11494             {
11495               vindex = 2;
11496               prefix = PREFIX_DATA;
11497               last_prefix = last_data_prefix;
11498             }
11499
11500           if (vindex != 0)
11501             {
11502               used_prefixes |= prefix;
11503               all_prefixes[last_prefix] = 0;
11504             }
11505         }
11506       dp = &prefix_table[dp->op[1].bytemode][vindex];
11507       break;
11508
11509     case USE_X86_64_TABLE:
11510       vindex = address_mode == mode_64bit ? 1 : 0;
11511       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11512       break;
11513
11514     case USE_3BYTE_TABLE:
11515       FETCH_DATA (info, codep + 2);
11516       vindex = *codep++;
11517       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11518       end_codep = codep;
11519       modrm.mod = (*codep >> 6) & 3;
11520       modrm.reg = (*codep >> 3) & 7;
11521       modrm.rm = *codep & 7;
11522       break;
11523
11524     case USE_VEX_LEN_TABLE:
11525       if (!need_vex)
11526         abort ();
11527
11528       switch (vex.length)
11529         {
11530         case 128:
11531           vindex = 0;
11532           break;
11533         case 256:
11534           vindex = 1;
11535           break;
11536         default:
11537           abort ();
11538           break;
11539         }
11540
11541       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11542       break;
11543
11544     case USE_EVEX_LEN_TABLE:
11545       if (!vex.evex)
11546         abort ();
11547
11548       switch (vex.length)
11549         {
11550         case 128:
11551           vindex = 0;
11552           break;
11553         case 256:
11554           vindex = 1;
11555           break;
11556         case 512:
11557           vindex = 2;
11558           break;
11559         default:
11560           abort ();
11561           break;
11562         }
11563
11564       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11565       break;
11566
11567     case USE_XOP_8F_TABLE:
11568       FETCH_DATA (info, codep + 3);
11569       /* All bits in the REX prefix are ignored.  */
11570       rex_ignored = rex;
11571       rex = ~(*codep >> 5) & 0x7;
11572
11573       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11574       switch ((*codep & 0x1f))
11575         {
11576         default:
11577           dp = &bad_opcode;
11578           return dp;
11579         case 0x8:
11580           vex_table_index = XOP_08;
11581           break;
11582         case 0x9:
11583           vex_table_index = XOP_09;
11584           break;
11585         case 0xa:
11586           vex_table_index = XOP_0A;
11587           break;
11588         }
11589       codep++;
11590       vex.w = *codep & 0x80;
11591       if (vex.w && address_mode == mode_64bit)
11592         rex |= REX_W;
11593
11594       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11595       if (address_mode != mode_64bit)
11596         {
11597           /* In 16/32-bit mode REX_B is silently ignored.  */
11598           rex &= ~REX_B;
11599         }
11600
11601       vex.length = (*codep & 0x4) ? 256 : 128;
11602       switch ((*codep & 0x3))
11603         {
11604         case 0:
11605           break;
11606         case 1:
11607           vex.prefix = DATA_PREFIX_OPCODE;
11608           break;
11609         case 2:
11610           vex.prefix = REPE_PREFIX_OPCODE;
11611           break;
11612         case 3:
11613           vex.prefix = REPNE_PREFIX_OPCODE;
11614           break;
11615         }
11616       need_vex = 1;
11617       need_vex_reg = 1;
11618       codep++;
11619       vindex = *codep++;
11620       dp = &xop_table[vex_table_index][vindex];
11621
11622       end_codep = codep;
11623       FETCH_DATA (info, codep + 1);
11624       modrm.mod = (*codep >> 6) & 3;
11625       modrm.reg = (*codep >> 3) & 7;
11626       modrm.rm = *codep & 7;
11627       break;
11628
11629     case USE_VEX_C4_TABLE:
11630       /* VEX prefix.  */
11631       FETCH_DATA (info, codep + 3);
11632       /* All bits in the REX prefix are ignored.  */
11633       rex_ignored = rex;
11634       rex = ~(*codep >> 5) & 0x7;
11635       switch ((*codep & 0x1f))
11636         {
11637         default:
11638           dp = &bad_opcode;
11639           return dp;
11640         case 0x1:
11641           vex_table_index = VEX_0F;
11642           break;
11643         case 0x2:
11644           vex_table_index = VEX_0F38;
11645           break;
11646         case 0x3:
11647           vex_table_index = VEX_0F3A;
11648           break;
11649         }
11650       codep++;
11651       vex.w = *codep & 0x80;
11652       if (address_mode == mode_64bit)
11653         {
11654           if (vex.w)
11655             rex |= REX_W;
11656         }
11657       else
11658         {
11659           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11660              is ignored, other REX bits are 0 and the highest bit in
11661              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11662           rex = 0;
11663         }
11664       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11665       vex.length = (*codep & 0x4) ? 256 : 128;
11666       switch ((*codep & 0x3))
11667         {
11668         case 0:
11669           break;
11670         case 1:
11671           vex.prefix = DATA_PREFIX_OPCODE;
11672           break;
11673         case 2:
11674           vex.prefix = REPE_PREFIX_OPCODE;
11675           break;
11676         case 3:
11677           vex.prefix = REPNE_PREFIX_OPCODE;
11678           break;
11679         }
11680       need_vex = 1;
11681       need_vex_reg = 1;
11682       codep++;
11683       vindex = *codep++;
11684       dp = &vex_table[vex_table_index][vindex];
11685       end_codep = codep;
11686       /* There is no MODRM byte for VEX0F 77.  */
11687       if (vex_table_index != VEX_0F || vindex != 0x77)
11688         {
11689           FETCH_DATA (info, codep + 1);
11690           modrm.mod = (*codep >> 6) & 3;
11691           modrm.reg = (*codep >> 3) & 7;
11692           modrm.rm = *codep & 7;
11693         }
11694       break;
11695
11696     case USE_VEX_C5_TABLE:
11697       /* VEX prefix.  */
11698       FETCH_DATA (info, codep + 2);
11699       /* All bits in the REX prefix are ignored.  */
11700       rex_ignored = rex;
11701       rex = (*codep & 0x80) ? 0 : REX_R;
11702
11703       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11704          VEX.vvvv is 1.  */
11705       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11706       vex.length = (*codep & 0x4) ? 256 : 128;
11707       switch ((*codep & 0x3))
11708         {
11709         case 0:
11710           break;
11711         case 1:
11712           vex.prefix = DATA_PREFIX_OPCODE;
11713           break;
11714         case 2:
11715           vex.prefix = REPE_PREFIX_OPCODE;
11716           break;
11717         case 3:
11718           vex.prefix = REPNE_PREFIX_OPCODE;
11719           break;
11720         }
11721       need_vex = 1;
11722       need_vex_reg = 1;
11723       codep++;
11724       vindex = *codep++;
11725       dp = &vex_table[dp->op[1].bytemode][vindex];
11726       end_codep = codep;
11727       /* There is no MODRM byte for VEX 77.  */
11728       if (vindex != 0x77)
11729         {
11730           FETCH_DATA (info, codep + 1);
11731           modrm.mod = (*codep >> 6) & 3;
11732           modrm.reg = (*codep >> 3) & 7;
11733           modrm.rm = *codep & 7;
11734         }
11735       break;
11736
11737     case USE_VEX_W_TABLE:
11738       if (!need_vex)
11739         abort ();
11740
11741       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11742       break;
11743
11744     case USE_EVEX_TABLE:
11745       two_source_ops = 0;
11746       /* EVEX prefix.  */
11747       vex.evex = 1;
11748       FETCH_DATA (info, codep + 4);
11749       /* All bits in the REX prefix are ignored.  */
11750       rex_ignored = rex;
11751       /* The first byte after 0x62.  */
11752       rex = ~(*codep >> 5) & 0x7;
11753       vex.r = *codep & 0x10;
11754       switch ((*codep & 0xf))
11755         {
11756         default:
11757           return &bad_opcode;
11758         case 0x1:
11759           vex_table_index = EVEX_0F;
11760           break;
11761         case 0x2:
11762           vex_table_index = EVEX_0F38;
11763           break;
11764         case 0x3:
11765           vex_table_index = EVEX_0F3A;
11766           break;
11767         }
11768
11769       /* The second byte after 0x62.  */
11770       codep++;
11771       vex.w = *codep & 0x80;
11772       if (vex.w && address_mode == mode_64bit)
11773         rex |= REX_W;
11774
11775       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11776
11777       /* The U bit.  */
11778       if (!(*codep & 0x4))
11779         return &bad_opcode;
11780
11781       switch ((*codep & 0x3))
11782         {
11783         case 0:
11784           break;
11785         case 1:
11786           vex.prefix = DATA_PREFIX_OPCODE;
11787           break;
11788         case 2:
11789           vex.prefix = REPE_PREFIX_OPCODE;
11790           break;
11791         case 3:
11792           vex.prefix = REPNE_PREFIX_OPCODE;
11793           break;
11794         }
11795
11796       /* The third byte after 0x62.  */
11797       codep++;
11798
11799       /* Remember the static rounding bits.  */
11800       vex.ll = (*codep >> 5) & 3;
11801       vex.b = (*codep & 0x10) != 0;
11802
11803       vex.v = *codep & 0x8;
11804       vex.mask_register_specifier = *codep & 0x7;
11805       vex.zeroing = *codep & 0x80;
11806
11807       if (address_mode != mode_64bit)
11808         {
11809           /* In 16/32-bit mode silently ignore following bits.  */
11810           rex &= ~REX_B;
11811           vex.r = 1;
11812           vex.v = 1;
11813         }
11814
11815       need_vex = 1;
11816       need_vex_reg = 1;
11817       codep++;
11818       vindex = *codep++;
11819       dp = &evex_table[vex_table_index][vindex];
11820       end_codep = codep;
11821       FETCH_DATA (info, codep + 1);
11822       modrm.mod = (*codep >> 6) & 3;
11823       modrm.reg = (*codep >> 3) & 7;
11824       modrm.rm = *codep & 7;
11825
11826       /* Set vector length.  */
11827       if (modrm.mod == 3 && vex.b)
11828         vex.length = 512;
11829       else
11830         {
11831           switch (vex.ll)
11832             {
11833             case 0x0:
11834               vex.length = 128;
11835               break;
11836             case 0x1:
11837               vex.length = 256;
11838               break;
11839             case 0x2:
11840               vex.length = 512;
11841               break;
11842             default:
11843               return &bad_opcode;
11844             }
11845         }
11846       break;
11847
11848     case 0:
11849       dp = &bad_opcode;
11850       break;
11851
11852     default:
11853       abort ();
11854     }
11855
11856   if (dp->name != NULL)
11857     return dp;
11858   else
11859     return get_valid_dis386 (dp, info);
11860 }
11861
11862 static void
11863 get_sib (disassemble_info *info, int sizeflag)
11864 {
11865   /* If modrm.mod == 3, operand must be register.  */
11866   if (need_modrm
11867       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11868       && modrm.mod != 3
11869       && modrm.rm == 4)
11870     {
11871       FETCH_DATA (info, codep + 2);
11872       sib.index = (codep [1] >> 3) & 7;
11873       sib.scale = (codep [1] >> 6) & 3;
11874       sib.base = codep [1] & 7;
11875     }
11876 }
11877
11878 static int
11879 print_insn (bfd_vma pc, disassemble_info *info)
11880 {
11881   const struct dis386 *dp;
11882   int i;
11883   char *op_txt[MAX_OPERANDS];
11884   int needcomma;
11885   int sizeflag, orig_sizeflag;
11886   const char *p;
11887   struct dis_private priv;
11888   int prefix_length;
11889
11890   priv.orig_sizeflag = AFLAG | DFLAG;
11891   if ((info->mach & bfd_mach_i386_i386) != 0)
11892     address_mode = mode_32bit;
11893   else if (info->mach == bfd_mach_i386_i8086)
11894     {
11895       address_mode = mode_16bit;
11896       priv.orig_sizeflag = 0;
11897     }
11898   else
11899     address_mode = mode_64bit;
11900
11901   if (intel_syntax == (char) -1)
11902     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11903
11904   for (p = info->disassembler_options; p != NULL; )
11905     {
11906       if (CONST_STRNEQ (p, "amd64"))
11907         isa64 = amd64;
11908       else if (CONST_STRNEQ (p, "intel64"))
11909         isa64 = intel64;
11910       else if (CONST_STRNEQ (p, "x86-64"))
11911         {
11912           address_mode = mode_64bit;
11913           priv.orig_sizeflag = AFLAG | DFLAG;
11914         }
11915       else if (CONST_STRNEQ (p, "i386"))
11916         {
11917           address_mode = mode_32bit;
11918           priv.orig_sizeflag = AFLAG | DFLAG;
11919         }
11920       else if (CONST_STRNEQ (p, "i8086"))
11921         {
11922           address_mode = mode_16bit;
11923           priv.orig_sizeflag = 0;
11924         }
11925       else if (CONST_STRNEQ (p, "intel"))
11926         {
11927           intel_syntax = 1;
11928           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11929             intel_mnemonic = 1;
11930         }
11931       else if (CONST_STRNEQ (p, "att"))
11932         {
11933           intel_syntax = 0;
11934           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11935             intel_mnemonic = 0;
11936         }
11937       else if (CONST_STRNEQ (p, "addr"))
11938         {
11939           if (address_mode == mode_64bit)
11940             {
11941               if (p[4] == '3' && p[5] == '2')
11942                 priv.orig_sizeflag &= ~AFLAG;
11943               else if (p[4] == '6' && p[5] == '4')
11944                 priv.orig_sizeflag |= AFLAG;
11945             }
11946           else
11947             {
11948               if (p[4] == '1' && p[5] == '6')
11949                 priv.orig_sizeflag &= ~AFLAG;
11950               else if (p[4] == '3' && p[5] == '2')
11951                 priv.orig_sizeflag |= AFLAG;
11952             }
11953         }
11954       else if (CONST_STRNEQ (p, "data"))
11955         {
11956           if (p[4] == '1' && p[5] == '6')
11957             priv.orig_sizeflag &= ~DFLAG;
11958           else if (p[4] == '3' && p[5] == '2')
11959             priv.orig_sizeflag |= DFLAG;
11960         }
11961       else if (CONST_STRNEQ (p, "suffix"))
11962         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11963
11964       p = strchr (p, ',');
11965       if (p != NULL)
11966         p++;
11967     }
11968
11969   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11970     {
11971       (*info->fprintf_func) (info->stream,
11972                              _("64-bit address is disabled"));
11973       return -1;
11974     }
11975
11976   if (intel_syntax)
11977     {
11978       names64 = intel_names64;
11979       names32 = intel_names32;
11980       names16 = intel_names16;
11981       names8 = intel_names8;
11982       names8rex = intel_names8rex;
11983       names_seg = intel_names_seg;
11984       names_mm = intel_names_mm;
11985       names_bnd = intel_names_bnd;
11986       names_xmm = intel_names_xmm;
11987       names_ymm = intel_names_ymm;
11988       names_zmm = intel_names_zmm;
11989       index64 = intel_index64;
11990       index32 = intel_index32;
11991       names_mask = intel_names_mask;
11992       index16 = intel_index16;
11993       open_char = '[';
11994       close_char = ']';
11995       separator_char = '+';
11996       scale_char = '*';
11997     }
11998   else
11999     {
12000       names64 = att_names64;
12001       names32 = att_names32;
12002       names16 = att_names16;
12003       names8 = att_names8;
12004       names8rex = att_names8rex;
12005       names_seg = att_names_seg;
12006       names_mm = att_names_mm;
12007       names_bnd = att_names_bnd;
12008       names_xmm = att_names_xmm;
12009       names_ymm = att_names_ymm;
12010       names_zmm = att_names_zmm;
12011       index64 = att_index64;
12012       index32 = att_index32;
12013       names_mask = att_names_mask;
12014       index16 = att_index16;
12015       open_char = '(';
12016       close_char =  ')';
12017       separator_char = ',';
12018       scale_char = ',';
12019     }
12020
12021   /* The output looks better if we put 7 bytes on a line, since that
12022      puts most long word instructions on a single line.  Use 8 bytes
12023      for Intel L1OM.  */
12024   if ((info->mach & bfd_mach_l1om) != 0)
12025     info->bytes_per_line = 8;
12026   else
12027     info->bytes_per_line = 7;
12028
12029   info->private_data = &priv;
12030   priv.max_fetched = priv.the_buffer;
12031   priv.insn_start = pc;
12032
12033   obuf[0] = 0;
12034   for (i = 0; i < MAX_OPERANDS; ++i)
12035     {
12036       op_out[i][0] = 0;
12037       op_index[i] = -1;
12038     }
12039
12040   the_info = info;
12041   start_pc = pc;
12042   start_codep = priv.the_buffer;
12043   codep = priv.the_buffer;
12044
12045   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12046     {
12047       const char *name;
12048
12049       /* Getting here means we tried for data but didn't get it.  That
12050          means we have an incomplete instruction of some sort.  Just
12051          print the first byte as a prefix or a .byte pseudo-op.  */
12052       if (codep > priv.the_buffer)
12053         {
12054           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12055           if (name != NULL)
12056             (*info->fprintf_func) (info->stream, "%s", name);
12057           else
12058             {
12059               /* Just print the first byte as a .byte instruction.  */
12060               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12061                                      (unsigned int) priv.the_buffer[0]);
12062             }
12063
12064           return 1;
12065         }
12066
12067       return -1;
12068     }
12069
12070   obufp = obuf;
12071   sizeflag = priv.orig_sizeflag;
12072
12073   if (!ckprefix () || rex_used)
12074     {
12075       /* Too many prefixes or unused REX prefixes.  */
12076       for (i = 0;
12077            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12078            i++)
12079         (*info->fprintf_func) (info->stream, "%s%s",
12080                                i == 0 ? "" : " ",
12081                                prefix_name (all_prefixes[i], sizeflag));
12082       return i;
12083     }
12084
12085   insn_codep = codep;
12086
12087   FETCH_DATA (info, codep + 1);
12088   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12089
12090   if (((prefixes & PREFIX_FWAIT)
12091        && ((*codep < 0xd8) || (*codep > 0xdf))))
12092     {
12093       /* Handle prefixes before fwait.  */
12094       for (i = 0; i < fwait_prefix && all_prefixes[i];
12095            i++)
12096         (*info->fprintf_func) (info->stream, "%s ",
12097                                prefix_name (all_prefixes[i], sizeflag));
12098       (*info->fprintf_func) (info->stream, "fwait");
12099       return i + 1;
12100     }
12101
12102   if (*codep == 0x0f)
12103     {
12104       unsigned char threebyte;
12105
12106       codep++;
12107       FETCH_DATA (info, codep + 1);
12108       threebyte = *codep;
12109       dp = &dis386_twobyte[threebyte];
12110       need_modrm = twobyte_has_modrm[*codep];
12111       codep++;
12112     }
12113   else
12114     {
12115       dp = &dis386[*codep];
12116       need_modrm = onebyte_has_modrm[*codep];
12117       codep++;
12118     }
12119
12120   /* Save sizeflag for printing the extra prefixes later before updating
12121      it for mnemonic and operand processing.  The prefix names depend
12122      only on the address mode.  */
12123   orig_sizeflag = sizeflag;
12124   if (prefixes & PREFIX_ADDR)
12125     sizeflag ^= AFLAG;
12126   if ((prefixes & PREFIX_DATA))
12127     sizeflag ^= DFLAG;
12128
12129   end_codep = codep;
12130   if (need_modrm)
12131     {
12132       FETCH_DATA (info, codep + 1);
12133       modrm.mod = (*codep >> 6) & 3;
12134       modrm.reg = (*codep >> 3) & 7;
12135       modrm.rm = *codep & 7;
12136     }
12137
12138   need_vex = 0;
12139   need_vex_reg = 0;
12140   vex_w_done = 0;
12141   memset (&vex, 0, sizeof (vex));
12142
12143   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12144     {
12145       get_sib (info, sizeflag);
12146       dofloat (sizeflag);
12147     }
12148   else
12149     {
12150       dp = get_valid_dis386 (dp, info);
12151       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12152         {
12153           get_sib (info, sizeflag);
12154           for (i = 0; i < MAX_OPERANDS; ++i)
12155             {
12156               obufp = op_out[i];
12157               op_ad = MAX_OPERANDS - 1 - i;
12158               if (dp->op[i].rtn)
12159                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12160               /* For EVEX instruction after the last operand masking
12161                  should be printed.  */
12162               if (i == 0 && vex.evex)
12163                 {
12164                   /* Don't print {%k0}.  */
12165                   if (vex.mask_register_specifier)
12166                     {
12167                       oappend ("{");
12168                       oappend (names_mask[vex.mask_register_specifier]);
12169                       oappend ("}");
12170                     }
12171                   if (vex.zeroing)
12172                     oappend ("{z}");
12173                 }
12174             }
12175         }
12176     }
12177
12178   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12179      are all 0s in inverted form.  */
12180   if (need_vex && vex.register_specifier != 0)
12181     {
12182       (*info->fprintf_func) (info->stream, "(bad)");
12183       return end_codep - priv.the_buffer;
12184     }
12185
12186   /* Check if the REX prefix is used.  */
12187   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12188     all_prefixes[last_rex_prefix] = 0;
12189
12190   /* Check if the SEG prefix is used.  */
12191   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12192                    | PREFIX_FS | PREFIX_GS)) != 0
12193       && (used_prefixes & active_seg_prefix) != 0)
12194     all_prefixes[last_seg_prefix] = 0;
12195
12196   /* Check if the ADDR prefix is used.  */
12197   if ((prefixes & PREFIX_ADDR) != 0
12198       && (used_prefixes & PREFIX_ADDR) != 0)
12199     all_prefixes[last_addr_prefix] = 0;
12200
12201   /* Check if the DATA prefix is used.  */
12202   if ((prefixes & PREFIX_DATA) != 0
12203       && (used_prefixes & PREFIX_DATA) != 0)
12204     all_prefixes[last_data_prefix] = 0;
12205
12206   /* Print the extra prefixes.  */
12207   prefix_length = 0;
12208   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12209     if (all_prefixes[i])
12210       {
12211         const char *name;
12212         name = prefix_name (all_prefixes[i], orig_sizeflag);
12213         if (name == NULL)
12214           abort ();
12215         prefix_length += strlen (name) + 1;
12216         (*info->fprintf_func) (info->stream, "%s ", name);
12217       }
12218
12219   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12220      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12221      used by putop and MMX/SSE operand and may be overriden by the
12222      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12223      separately.  */
12224   if (dp->prefix_requirement == PREFIX_OPCODE
12225       && dp != &bad_opcode
12226       && (((prefixes
12227             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12228            && (used_prefixes
12229                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12230           || ((((prefixes
12231                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12232                 == PREFIX_DATA)
12233                && (used_prefixes & PREFIX_DATA) == 0))))
12234     {
12235       (*info->fprintf_func) (info->stream, "(bad)");
12236       return end_codep - priv.the_buffer;
12237     }
12238
12239   /* Check maximum code length.  */
12240   if ((codep - start_codep) > MAX_CODE_LENGTH)
12241     {
12242       (*info->fprintf_func) (info->stream, "(bad)");
12243       return MAX_CODE_LENGTH;
12244     }
12245
12246   obufp = mnemonicendp;
12247   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12248     oappend (" ");
12249   oappend (" ");
12250   (*info->fprintf_func) (info->stream, "%s", obuf);
12251
12252   /* The enter and bound instructions are printed with operands in the same
12253      order as the intel book; everything else is printed in reverse order.  */
12254   if (intel_syntax || two_source_ops)
12255     {
12256       bfd_vma riprel;
12257
12258       for (i = 0; i < MAX_OPERANDS; ++i)
12259         op_txt[i] = op_out[i];
12260
12261       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12262           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12263         {
12264           op_txt[2] = op_out[3];
12265           op_txt[3] = op_out[2];
12266         }
12267
12268       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12269         {
12270           op_ad = op_index[i];
12271           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12272           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12273           riprel = op_riprel[i];
12274           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12275           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12276         }
12277     }
12278   else
12279     {
12280       for (i = 0; i < MAX_OPERANDS; ++i)
12281         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12282     }
12283
12284   needcomma = 0;
12285   for (i = 0; i < MAX_OPERANDS; ++i)
12286     if (*op_txt[i])
12287       {
12288         if (needcomma)
12289           (*info->fprintf_func) (info->stream, ",");
12290         if (op_index[i] != -1 && !op_riprel[i])
12291           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12292         else
12293           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12294         needcomma = 1;
12295       }
12296
12297   for (i = 0; i < MAX_OPERANDS; i++)
12298     if (op_index[i] != -1 && op_riprel[i])
12299       {
12300         (*info->fprintf_func) (info->stream, "        # ");
12301         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12302                                                 + op_address[op_index[i]]), info);
12303         break;
12304       }
12305   return codep - priv.the_buffer;
12306 }
12307
12308 static const char *float_mem[] = {
12309   /* d8 */
12310   "fadd{s|}",
12311   "fmul{s|}",
12312   "fcom{s|}",
12313   "fcomp{s|}",
12314   "fsub{s|}",
12315   "fsubr{s|}",
12316   "fdiv{s|}",
12317   "fdivr{s|}",
12318   /* d9 */
12319   "fld{s|}",
12320   "(bad)",
12321   "fst{s|}",
12322   "fstp{s|}",
12323   "fldenvIC",
12324   "fldcw",
12325   "fNstenvIC",
12326   "fNstcw",
12327   /* da */
12328   "fiadd{l|}",
12329   "fimul{l|}",
12330   "ficom{l|}",
12331   "ficomp{l|}",
12332   "fisub{l|}",
12333   "fisubr{l|}",
12334   "fidiv{l|}",
12335   "fidivr{l|}",
12336   /* db */
12337   "fild{l|}",
12338   "fisttp{l|}",
12339   "fist{l|}",
12340   "fistp{l|}",
12341   "(bad)",
12342   "fld{t||t|}",
12343   "(bad)",
12344   "fstp{t||t|}",
12345   /* dc */
12346   "fadd{l|}",
12347   "fmul{l|}",
12348   "fcom{l|}",
12349   "fcomp{l|}",
12350   "fsub{l|}",
12351   "fsubr{l|}",
12352   "fdiv{l|}",
12353   "fdivr{l|}",
12354   /* dd */
12355   "fld{l|}",
12356   "fisttp{ll|}",
12357   "fst{l||}",
12358   "fstp{l|}",
12359   "frstorIC",
12360   "(bad)",
12361   "fNsaveIC",
12362   "fNstsw",
12363   /* de */
12364   "fiadd{s|}",
12365   "fimul{s|}",
12366   "ficom{s|}",
12367   "ficomp{s|}",
12368   "fisub{s|}",
12369   "fisubr{s|}",
12370   "fidiv{s|}",
12371   "fidivr{s|}",
12372   /* df */
12373   "fild{s|}",
12374   "fisttp{s|}",
12375   "fist{s|}",
12376   "fistp{s|}",
12377   "fbld",
12378   "fild{ll|}",
12379   "fbstp",
12380   "fistp{ll|}",
12381 };
12382
12383 static const unsigned char float_mem_mode[] = {
12384   /* d8 */
12385   d_mode,
12386   d_mode,
12387   d_mode,
12388   d_mode,
12389   d_mode,
12390   d_mode,
12391   d_mode,
12392   d_mode,
12393   /* d9 */
12394   d_mode,
12395   0,
12396   d_mode,
12397   d_mode,
12398   0,
12399   w_mode,
12400   0,
12401   w_mode,
12402   /* da */
12403   d_mode,
12404   d_mode,
12405   d_mode,
12406   d_mode,
12407   d_mode,
12408   d_mode,
12409   d_mode,
12410   d_mode,
12411   /* db */
12412   d_mode,
12413   d_mode,
12414   d_mode,
12415   d_mode,
12416   0,
12417   t_mode,
12418   0,
12419   t_mode,
12420   /* dc */
12421   q_mode,
12422   q_mode,
12423   q_mode,
12424   q_mode,
12425   q_mode,
12426   q_mode,
12427   q_mode,
12428   q_mode,
12429   /* dd */
12430   q_mode,
12431   q_mode,
12432   q_mode,
12433   q_mode,
12434   0,
12435   0,
12436   0,
12437   w_mode,
12438   /* de */
12439   w_mode,
12440   w_mode,
12441   w_mode,
12442   w_mode,
12443   w_mode,
12444   w_mode,
12445   w_mode,
12446   w_mode,
12447   /* df */
12448   w_mode,
12449   w_mode,
12450   w_mode,
12451   w_mode,
12452   t_mode,
12453   q_mode,
12454   t_mode,
12455   q_mode
12456 };
12457
12458 #define ST { OP_ST, 0 }
12459 #define STi { OP_STi, 0 }
12460
12461 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12462 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12463 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12464 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12465 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12466 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12467 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12468 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12469 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12470
12471 static const struct dis386 float_reg[][8] = {
12472   /* d8 */
12473   {
12474     { "fadd",   { ST, STi }, 0 },
12475     { "fmul",   { ST, STi }, 0 },
12476     { "fcom",   { STi }, 0 },
12477     { "fcomp",  { STi }, 0 },
12478     { "fsub",   { ST, STi }, 0 },
12479     { "fsubr",  { ST, STi }, 0 },
12480     { "fdiv",   { ST, STi }, 0 },
12481     { "fdivr",  { ST, STi }, 0 },
12482   },
12483   /* d9 */
12484   {
12485     { "fld",    { STi }, 0 },
12486     { "fxch",   { STi }, 0 },
12487     { FGRPd9_2 },
12488     { Bad_Opcode },
12489     { FGRPd9_4 },
12490     { FGRPd9_5 },
12491     { FGRPd9_6 },
12492     { FGRPd9_7 },
12493   },
12494   /* da */
12495   {
12496     { "fcmovb", { ST, STi }, 0 },
12497     { "fcmove", { ST, STi }, 0 },
12498     { "fcmovbe",{ ST, STi }, 0 },
12499     { "fcmovu", { ST, STi }, 0 },
12500     { Bad_Opcode },
12501     { FGRPda_5 },
12502     { Bad_Opcode },
12503     { Bad_Opcode },
12504   },
12505   /* db */
12506   {
12507     { "fcmovnb",{ ST, STi }, 0 },
12508     { "fcmovne",{ ST, STi }, 0 },
12509     { "fcmovnbe",{ ST, STi }, 0 },
12510     { "fcmovnu",{ ST, STi }, 0 },
12511     { FGRPdb_4 },
12512     { "fucomi", { ST, STi }, 0 },
12513     { "fcomi",  { ST, STi }, 0 },
12514     { Bad_Opcode },
12515   },
12516   /* dc */
12517   {
12518     { "fadd",   { STi, ST }, 0 },
12519     { "fmul",   { STi, ST }, 0 },
12520     { Bad_Opcode },
12521     { Bad_Opcode },
12522     { "fsub{!M|r}",     { STi, ST }, 0 },
12523     { "fsub{M|}",       { STi, ST }, 0 },
12524     { "fdiv{!M|r}",     { STi, ST }, 0 },
12525     { "fdiv{M|}",       { STi, ST }, 0 },
12526   },
12527   /* dd */
12528   {
12529     { "ffree",  { STi }, 0 },
12530     { Bad_Opcode },
12531     { "fst",    { STi }, 0 },
12532     { "fstp",   { STi }, 0 },
12533     { "fucom",  { STi }, 0 },
12534     { "fucomp", { STi }, 0 },
12535     { Bad_Opcode },
12536     { Bad_Opcode },
12537   },
12538   /* de */
12539   {
12540     { "faddp",  { STi, ST }, 0 },
12541     { "fmulp",  { STi, ST }, 0 },
12542     { Bad_Opcode },
12543     { FGRPde_3 },
12544     { "fsub{!M|r}p",    { STi, ST }, 0 },
12545     { "fsub{M|}p",      { STi, ST }, 0 },
12546     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12547     { "fdiv{M|}p",      { STi, ST }, 0 },
12548   },
12549   /* df */
12550   {
12551     { "ffreep", { STi }, 0 },
12552     { Bad_Opcode },
12553     { Bad_Opcode },
12554     { Bad_Opcode },
12555     { FGRPdf_4 },
12556     { "fucomip", { ST, STi }, 0 },
12557     { "fcomip", { ST, STi }, 0 },
12558     { Bad_Opcode },
12559   },
12560 };
12561
12562 static char *fgrps[][8] = {
12563   /* Bad opcode 0 */
12564   {
12565     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12566   },
12567
12568   /* d9_2  1 */
12569   {
12570     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12571   },
12572
12573   /* d9_4  2 */
12574   {
12575     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12576   },
12577
12578   /* d9_5  3 */
12579   {
12580     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12581   },
12582
12583   /* d9_6  4 */
12584   {
12585     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12586   },
12587
12588   /* d9_7  5 */
12589   {
12590     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12591   },
12592
12593   /* da_5  6 */
12594   {
12595     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12596   },
12597
12598   /* db_4  7 */
12599   {
12600     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12601     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12602   },
12603
12604   /* de_3  8 */
12605   {
12606     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12607   },
12608
12609   /* df_4  9 */
12610   {
12611     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12612   },
12613 };
12614
12615 static void
12616 swap_operand (void)
12617 {
12618   mnemonicendp[0] = '.';
12619   mnemonicendp[1] = 's';
12620   mnemonicendp += 2;
12621 }
12622
12623 static void
12624 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12625                int sizeflag ATTRIBUTE_UNUSED)
12626 {
12627   /* Skip mod/rm byte.  */
12628   MODRM_CHECK;
12629   codep++;
12630 }
12631
12632 static void
12633 dofloat (int sizeflag)
12634 {
12635   const struct dis386 *dp;
12636   unsigned char floatop;
12637
12638   floatop = codep[-1];
12639
12640   if (modrm.mod != 3)
12641     {
12642       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12643
12644       putop (float_mem[fp_indx], sizeflag);
12645       obufp = op_out[0];
12646       op_ad = 2;
12647       OP_E (float_mem_mode[fp_indx], sizeflag);
12648       return;
12649     }
12650   /* Skip mod/rm byte.  */
12651   MODRM_CHECK;
12652   codep++;
12653
12654   dp = &float_reg[floatop - 0xd8][modrm.reg];
12655   if (dp->name == NULL)
12656     {
12657       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12658
12659       /* Instruction fnstsw is only one with strange arg.  */
12660       if (floatop == 0xdf && codep[-1] == 0xe0)
12661         strcpy (op_out[0], names16[0]);
12662     }
12663   else
12664     {
12665       putop (dp->name, sizeflag);
12666
12667       obufp = op_out[0];
12668       op_ad = 2;
12669       if (dp->op[0].rtn)
12670         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12671
12672       obufp = op_out[1];
12673       op_ad = 1;
12674       if (dp->op[1].rtn)
12675         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12676     }
12677 }
12678
12679 /* Like oappend (below), but S is a string starting with '%'.
12680    In Intel syntax, the '%' is elided.  */
12681 static void
12682 oappend_maybe_intel (const char *s)
12683 {
12684   oappend (s + intel_syntax);
12685 }
12686
12687 static void
12688 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12689 {
12690   oappend_maybe_intel ("%st");
12691 }
12692
12693 static void
12694 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12695 {
12696   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12697   oappend_maybe_intel (scratchbuf);
12698 }
12699
12700 /* Capital letters in template are macros.  */
12701 static int
12702 putop (const char *in_template, int sizeflag)
12703 {
12704   const char *p;
12705   int alt = 0;
12706   int cond = 1;
12707   unsigned int l = 0, len = 1;
12708   char last[4];
12709
12710 #define SAVE_LAST(c)                    \
12711   if (l < len && l < sizeof (last))     \
12712     last[l++] = c;                      \
12713   else                                  \
12714     abort ();
12715
12716   for (p = in_template; *p; p++)
12717     {
12718       switch (*p)
12719         {
12720         default:
12721           *obufp++ = *p;
12722           break;
12723         case '%':
12724           len++;
12725           break;
12726         case '!':
12727           cond = 0;
12728           break;
12729         case '{':
12730           if (intel_syntax)
12731             {
12732               while (*++p != '|')
12733                 if (*p == '}' || *p == '\0')
12734                   abort ();
12735             }
12736           /* Fall through.  */
12737         case 'I':
12738           alt = 1;
12739           continue;
12740         case '|':
12741           while (*++p != '}')
12742             {
12743               if (*p == '\0')
12744                 abort ();
12745             }
12746           break;
12747         case '}':
12748           break;
12749         case 'A':
12750           if (intel_syntax)
12751             break;
12752           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12753             *obufp++ = 'b';
12754           break;
12755         case 'B':
12756           if (l == 0 && len == 1)
12757             {
12758 case_B:
12759               if (intel_syntax)
12760                 break;
12761               if (sizeflag & SUFFIX_ALWAYS)
12762                 *obufp++ = 'b';
12763             }
12764           else
12765             {
12766               if (l != 1
12767                   || len != 2
12768                   || last[0] != 'L')
12769                 {
12770                   SAVE_LAST (*p);
12771                   break;
12772                 }
12773
12774               if (address_mode == mode_64bit
12775                   && !(prefixes & PREFIX_ADDR))
12776                 {
12777                   *obufp++ = 'a';
12778                   *obufp++ = 'b';
12779                   *obufp++ = 's';
12780                 }
12781
12782               goto case_B;
12783             }
12784           break;
12785         case 'C':
12786           if (intel_syntax && !alt)
12787             break;
12788           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12789             {
12790               if (sizeflag & DFLAG)
12791                 *obufp++ = intel_syntax ? 'd' : 'l';
12792               else
12793                 *obufp++ = intel_syntax ? 'w' : 's';
12794               used_prefixes |= (prefixes & PREFIX_DATA);
12795             }
12796           break;
12797         case 'D':
12798           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12799             break;
12800           USED_REX (REX_W);
12801           if (modrm.mod == 3)
12802             {
12803               if (rex & REX_W)
12804                 *obufp++ = 'q';
12805               else
12806                 {
12807                   if (sizeflag & DFLAG)
12808                     *obufp++ = intel_syntax ? 'd' : 'l';
12809                   else
12810                     *obufp++ = 'w';
12811                   used_prefixes |= (prefixes & PREFIX_DATA);
12812                 }
12813             }
12814           else
12815             *obufp++ = 'w';
12816           break;
12817         case 'E':               /* For jcxz/jecxz */
12818           if (address_mode == mode_64bit)
12819             {
12820               if (sizeflag & AFLAG)
12821                 *obufp++ = 'r';
12822               else
12823                 *obufp++ = 'e';
12824             }
12825           else
12826             if (sizeflag & AFLAG)
12827               *obufp++ = 'e';
12828           used_prefixes |= (prefixes & PREFIX_ADDR);
12829           break;
12830         case 'F':
12831           if (intel_syntax)
12832             break;
12833           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12834             {
12835               if (sizeflag & AFLAG)
12836                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12837               else
12838                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12839               used_prefixes |= (prefixes & PREFIX_ADDR);
12840             }
12841           break;
12842         case 'G':
12843           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12844             break;
12845           if ((rex & REX_W) || (sizeflag & DFLAG))
12846             *obufp++ = 'l';
12847           else
12848             *obufp++ = 'w';
12849           if (!(rex & REX_W))
12850             used_prefixes |= (prefixes & PREFIX_DATA);
12851           break;
12852         case 'H':
12853           if (intel_syntax)
12854             break;
12855           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12856               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12857             {
12858               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12859               *obufp++ = ',';
12860               *obufp++ = 'p';
12861               if (prefixes & PREFIX_DS)
12862                 *obufp++ = 't';
12863               else
12864                 *obufp++ = 'n';
12865             }
12866           break;
12867         case 'J':
12868           if (intel_syntax)
12869             break;
12870           *obufp++ = 'l';
12871           break;
12872         case 'K':
12873           USED_REX (REX_W);
12874           if (rex & REX_W)
12875             *obufp++ = 'q';
12876           else
12877             *obufp++ = 'd';
12878           break;
12879         case 'Z':
12880           if (l != 0 || len != 1)
12881             {
12882               if (l != 1 || len != 2 || last[0] != 'X')
12883                 {
12884                   SAVE_LAST (*p);
12885                   break;
12886                 }
12887               if (!need_vex || !vex.evex)
12888                 abort ();
12889               if (intel_syntax
12890                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12891                 break;
12892               switch (vex.length)
12893                 {
12894                 case 128:
12895                   *obufp++ = 'x';
12896                   break;
12897                 case 256:
12898                   *obufp++ = 'y';
12899                   break;
12900                 case 512:
12901                   *obufp++ = 'z';
12902                   break;
12903                 default:
12904                   abort ();
12905                 }
12906               break;
12907             }
12908           if (intel_syntax)
12909             break;
12910           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12911             {
12912               *obufp++ = 'q';
12913               break;
12914             }
12915           /* Fall through.  */
12916           goto case_L;
12917         case 'L':
12918           if (l != 0 || len != 1)
12919             {
12920               SAVE_LAST (*p);
12921               break;
12922             }
12923 case_L:
12924           if (intel_syntax)
12925             break;
12926           if (sizeflag & SUFFIX_ALWAYS)
12927             *obufp++ = 'l';
12928           break;
12929         case 'M':
12930           if (intel_mnemonic != cond)
12931             *obufp++ = 'r';
12932           break;
12933         case 'N':
12934           if ((prefixes & PREFIX_FWAIT) == 0)
12935             *obufp++ = 'n';
12936           else
12937             used_prefixes |= PREFIX_FWAIT;
12938           break;
12939         case 'O':
12940           USED_REX (REX_W);
12941           if (rex & REX_W)
12942             *obufp++ = 'o';
12943           else if (intel_syntax && (sizeflag & DFLAG))
12944             *obufp++ = 'q';
12945           else
12946             *obufp++ = 'd';
12947           if (!(rex & REX_W))
12948             used_prefixes |= (prefixes & PREFIX_DATA);
12949           break;
12950         case '&':
12951           if (!intel_syntax
12952               && address_mode == mode_64bit
12953               && isa64 == intel64)
12954             {
12955               *obufp++ = 'q';
12956               break;
12957             }
12958           /* Fall through.  */
12959         case 'T':
12960           if (!intel_syntax
12961               && address_mode == mode_64bit
12962               && ((sizeflag & DFLAG) || (rex & REX_W)))
12963             {
12964               *obufp++ = 'q';
12965               break;
12966             }
12967           /* Fall through.  */
12968           goto case_P;
12969         case 'P':
12970           if (l == 0 && len == 1)
12971             {
12972 case_P:
12973               if (intel_syntax)
12974                 {
12975                   if ((rex & REX_W) == 0
12976                       && (prefixes & PREFIX_DATA))
12977                     {
12978                       if ((sizeflag & DFLAG) == 0)
12979                         *obufp++ = 'w';
12980                       used_prefixes |= (prefixes & PREFIX_DATA);
12981                     }
12982                   break;
12983                 }
12984               if ((prefixes & PREFIX_DATA)
12985                   || (rex & REX_W)
12986                   || (sizeflag & SUFFIX_ALWAYS))
12987                 {
12988                   USED_REX (REX_W);
12989                   if (rex & REX_W)
12990                     *obufp++ = 'q';
12991                   else
12992                     {
12993                       if (sizeflag & DFLAG)
12994                         *obufp++ = 'l';
12995                       else
12996                         *obufp++ = 'w';
12997                       used_prefixes |= (prefixes & PREFIX_DATA);
12998                     }
12999                 }
13000             }
13001           else
13002             {
13003               if (l != 1 || len != 2 || last[0] != 'L')
13004                 {
13005                   SAVE_LAST (*p);
13006                   break;
13007                 }
13008
13009               if ((prefixes & PREFIX_DATA)
13010                   || (rex & REX_W)
13011                   || (sizeflag & SUFFIX_ALWAYS))
13012                 {
13013                   USED_REX (REX_W);
13014                   if (rex & REX_W)
13015                     *obufp++ = 'q';
13016                   else
13017                     {
13018                       if (sizeflag & DFLAG)
13019                         *obufp++ = intel_syntax ? 'd' : 'l';
13020                       else
13021                         *obufp++ = 'w';
13022                       used_prefixes |= (prefixes & PREFIX_DATA);
13023                     }
13024                 }
13025             }
13026           break;
13027         case 'U':
13028           if (intel_syntax)
13029             break;
13030           if (address_mode == mode_64bit
13031               && ((sizeflag & DFLAG) || (rex & REX_W)))
13032             {
13033               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13034                 *obufp++ = 'q';
13035               break;
13036             }
13037           /* Fall through.  */
13038           goto case_Q;
13039         case 'Q':
13040           if (l == 0 && len == 1)
13041             {
13042 case_Q:
13043               if (intel_syntax && !alt)
13044                 break;
13045               USED_REX (REX_W);
13046               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13047                 {
13048                   if (rex & REX_W)
13049                     *obufp++ = 'q';
13050                   else
13051                     {
13052                       if (sizeflag & DFLAG)
13053                         *obufp++ = intel_syntax ? 'd' : 'l';
13054                       else
13055                         *obufp++ = 'w';
13056                       used_prefixes |= (prefixes & PREFIX_DATA);
13057                     }
13058                 }
13059             }
13060           else
13061             {
13062               if (l != 1 || len != 2 || last[0] != 'L')
13063                 {
13064                   SAVE_LAST (*p);
13065                   break;
13066                 }
13067               if (intel_syntax
13068                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13069                 break;
13070               if ((rex & REX_W))
13071                 {
13072                   USED_REX (REX_W);
13073                   *obufp++ = 'q';
13074                 }
13075               else
13076                 *obufp++ = 'l';
13077             }
13078           break;
13079         case 'R':
13080           USED_REX (REX_W);
13081           if (rex & REX_W)
13082             *obufp++ = 'q';
13083           else if (sizeflag & DFLAG)
13084             {
13085               if (intel_syntax)
13086                   *obufp++ = 'd';
13087               else
13088                   *obufp++ = 'l';
13089             }
13090           else
13091             *obufp++ = 'w';
13092           if (intel_syntax && !p[1]
13093               && ((rex & REX_W) || (sizeflag & DFLAG)))
13094             *obufp++ = 'e';
13095           if (!(rex & REX_W))
13096             used_prefixes |= (prefixes & PREFIX_DATA);
13097           break;
13098         case 'V':
13099           if (l == 0 && len == 1)
13100             {
13101               if (intel_syntax)
13102                 break;
13103               if (address_mode == mode_64bit
13104                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13105                 {
13106                   if (sizeflag & SUFFIX_ALWAYS)
13107                     *obufp++ = 'q';
13108                   break;
13109                 }
13110             }
13111           else
13112             {
13113               if (l != 1
13114                   || len != 2
13115                   || last[0] != 'L')
13116                 {
13117                   SAVE_LAST (*p);
13118                   break;
13119                 }
13120
13121               if (rex & REX_W)
13122                 {
13123                   *obufp++ = 'a';
13124                   *obufp++ = 'b';
13125                   *obufp++ = 's';
13126                 }
13127             }
13128           /* Fall through.  */
13129           goto case_S;
13130         case 'S':
13131           if (l == 0 && len == 1)
13132             {
13133 case_S:
13134               if (intel_syntax)
13135                 break;
13136               if (sizeflag & SUFFIX_ALWAYS)
13137                 {
13138                   if (rex & REX_W)
13139                     *obufp++ = 'q';
13140                   else
13141                     {
13142                       if (sizeflag & DFLAG)
13143                         *obufp++ = 'l';
13144                       else
13145                         *obufp++ = 'w';
13146                       used_prefixes |= (prefixes & PREFIX_DATA);
13147                     }
13148                 }
13149             }
13150           else
13151             {
13152               if (l != 1
13153                   || len != 2
13154                   || last[0] != 'L')
13155                 {
13156                   SAVE_LAST (*p);
13157                   break;
13158                 }
13159
13160               if (address_mode == mode_64bit
13161                   && !(prefixes & PREFIX_ADDR))
13162                 {
13163                   *obufp++ = 'a';
13164                   *obufp++ = 'b';
13165                   *obufp++ = 's';
13166                 }
13167
13168               goto case_S;
13169             }
13170           break;
13171         case 'X':
13172           if (l != 0 || len != 1)
13173             {
13174               SAVE_LAST (*p);
13175               break;
13176             }
13177           if (need_vex && vex.prefix)
13178             {
13179               if (vex.prefix == DATA_PREFIX_OPCODE)
13180                 *obufp++ = 'd';
13181               else
13182                 *obufp++ = 's';
13183             }
13184           else
13185             {
13186               if (prefixes & PREFIX_DATA)
13187                 *obufp++ = 'd';
13188               else
13189                 *obufp++ = 's';
13190               used_prefixes |= (prefixes & PREFIX_DATA);
13191             }
13192           break;
13193         case 'Y':
13194           if (l == 0 && len == 1)
13195             abort ();
13196           else
13197             {
13198               if (l != 1 || len != 2 || last[0] != 'X')
13199                 {
13200                   SAVE_LAST (*p);
13201                   break;
13202                 }
13203               if (!need_vex)
13204                 abort ();
13205               if (intel_syntax
13206                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13207                 break;
13208               switch (vex.length)
13209                 {
13210                 case 128:
13211                   *obufp++ = 'x';
13212                   break;
13213                 case 256:
13214                   *obufp++ = 'y';
13215                   break;
13216                 case 512:
13217                   if (!vex.evex)
13218                 default:
13219                     abort ();
13220                 }
13221             }
13222           break;
13223         case 'W':
13224           if (l == 0 && len == 1)
13225             {
13226               /* operand size flag for cwtl, cbtw */
13227               USED_REX (REX_W);
13228               if (rex & REX_W)
13229                 {
13230                   if (intel_syntax)
13231                     *obufp++ = 'd';
13232                   else
13233                     *obufp++ = 'l';
13234                 }
13235               else if (sizeflag & DFLAG)
13236                 *obufp++ = 'w';
13237               else
13238                 *obufp++ = 'b';
13239               if (!(rex & REX_W))
13240                 used_prefixes |= (prefixes & PREFIX_DATA);
13241             }
13242           else
13243             {
13244               if (l != 1
13245                   || len != 2
13246                   || (last[0] != 'X'
13247                       && last[0] != 'L'))
13248                 {
13249                   SAVE_LAST (*p);
13250                   break;
13251                 }
13252               if (!need_vex)
13253                 abort ();
13254               if (last[0] == 'X')
13255                 *obufp++ = vex.w ? 'd': 's';
13256               else
13257                 *obufp++ = vex.w ? 'q': 'd';
13258             }
13259           break;
13260         case '^':
13261           if (intel_syntax)
13262             break;
13263           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13264             {
13265               if (sizeflag & DFLAG)
13266                 *obufp++ = 'l';
13267               else
13268                 *obufp++ = 'w';
13269               used_prefixes |= (prefixes & PREFIX_DATA);
13270             }
13271           break;
13272         case '@':
13273           if (intel_syntax)
13274             break;
13275           if (address_mode == mode_64bit
13276               && (isa64 == intel64
13277                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13278               *obufp++ = 'q';
13279           else if ((prefixes & PREFIX_DATA))
13280             {
13281               if (!(sizeflag & DFLAG))
13282                 *obufp++ = 'w';
13283               used_prefixes |= (prefixes & PREFIX_DATA);
13284             }
13285           break;
13286         }
13287       alt = 0;
13288     }
13289   *obufp = 0;
13290   mnemonicendp = obufp;
13291   return 0;
13292 }
13293
13294 static void
13295 oappend (const char *s)
13296 {
13297   obufp = stpcpy (obufp, s);
13298 }
13299
13300 static void
13301 append_seg (void)
13302 {
13303   /* Only print the active segment register.  */
13304   if (!active_seg_prefix)
13305     return;
13306
13307   used_prefixes |= active_seg_prefix;
13308   switch (active_seg_prefix)
13309     {
13310     case PREFIX_CS:
13311       oappend_maybe_intel ("%cs:");
13312       break;
13313     case PREFIX_DS:
13314       oappend_maybe_intel ("%ds:");
13315       break;
13316     case PREFIX_SS:
13317       oappend_maybe_intel ("%ss:");
13318       break;
13319     case PREFIX_ES:
13320       oappend_maybe_intel ("%es:");
13321       break;
13322     case PREFIX_FS:
13323       oappend_maybe_intel ("%fs:");
13324       break;
13325     case PREFIX_GS:
13326       oappend_maybe_intel ("%gs:");
13327       break;
13328     default:
13329       break;
13330     }
13331 }
13332
13333 static void
13334 OP_indirE (int bytemode, int sizeflag)
13335 {
13336   if (!intel_syntax)
13337     oappend ("*");
13338   OP_E (bytemode, sizeflag);
13339 }
13340
13341 static void
13342 print_operand_value (char *buf, int hex, bfd_vma disp)
13343 {
13344   if (address_mode == mode_64bit)
13345     {
13346       if (hex)
13347         {
13348           char tmp[30];
13349           int i;
13350           buf[0] = '0';
13351           buf[1] = 'x';
13352           sprintf_vma (tmp, disp);
13353           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13354           strcpy (buf + 2, tmp + i);
13355         }
13356       else
13357         {
13358           bfd_signed_vma v = disp;
13359           char tmp[30];
13360           int i;
13361           if (v < 0)
13362             {
13363               *(buf++) = '-';
13364               v = -disp;
13365               /* Check for possible overflow on 0x8000000000000000.  */
13366               if (v < 0)
13367                 {
13368                   strcpy (buf, "9223372036854775808");
13369                   return;
13370                 }
13371             }
13372           if (!v)
13373             {
13374               strcpy (buf, "0");
13375               return;
13376             }
13377
13378           i = 0;
13379           tmp[29] = 0;
13380           while (v)
13381             {
13382               tmp[28 - i] = (v % 10) + '0';
13383               v /= 10;
13384               i++;
13385             }
13386           strcpy (buf, tmp + 29 - i);
13387         }
13388     }
13389   else
13390     {
13391       if (hex)
13392         sprintf (buf, "0x%x", (unsigned int) disp);
13393       else
13394         sprintf (buf, "%d", (int) disp);
13395     }
13396 }
13397
13398 /* Put DISP in BUF as signed hex number.  */
13399
13400 static void
13401 print_displacement (char *buf, bfd_vma disp)
13402 {
13403   bfd_signed_vma val = disp;
13404   char tmp[30];
13405   int i, j = 0;
13406
13407   if (val < 0)
13408     {
13409       buf[j++] = '-';
13410       val = -disp;
13411
13412       /* Check for possible overflow.  */
13413       if (val < 0)
13414         {
13415           switch (address_mode)
13416             {
13417             case mode_64bit:
13418               strcpy (buf + j, "0x8000000000000000");
13419               break;
13420             case mode_32bit:
13421               strcpy (buf + j, "0x80000000");
13422               break;
13423             case mode_16bit:
13424               strcpy (buf + j, "0x8000");
13425               break;
13426             }
13427           return;
13428         }
13429     }
13430
13431   buf[j++] = '0';
13432   buf[j++] = 'x';
13433
13434   sprintf_vma (tmp, (bfd_vma) val);
13435   for (i = 0; tmp[i] == '0'; i++)
13436     continue;
13437   if (tmp[i] == '\0')
13438     i--;
13439   strcpy (buf + j, tmp + i);
13440 }
13441
13442 static void
13443 intel_operand_size (int bytemode, int sizeflag)
13444 {
13445   if (vex.evex
13446       && vex.b
13447       && (bytemode == x_mode
13448           || bytemode == evex_half_bcst_xmmq_mode))
13449     {
13450       if (vex.w)
13451         oappend ("QWORD PTR ");
13452       else
13453         oappend ("DWORD PTR ");
13454       return;
13455     }
13456   switch (bytemode)
13457     {
13458     case b_mode:
13459     case b_swap_mode:
13460     case dqb_mode:
13461     case db_mode:
13462       oappend ("BYTE PTR ");
13463       break;
13464     case w_mode:
13465     case dw_mode:
13466     case dqw_mode:
13467       oappend ("WORD PTR ");
13468       break;
13469     case indir_v_mode:
13470       if (address_mode == mode_64bit && isa64 == intel64)
13471         {
13472           oappend ("QWORD PTR ");
13473           break;
13474         }
13475       /* Fall through.  */
13476     case stack_v_mode:
13477       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13478         {
13479           oappend ("QWORD PTR ");
13480           break;
13481         }
13482       /* Fall through.  */
13483     case v_mode:
13484     case v_swap_mode:
13485     case dq_mode:
13486       USED_REX (REX_W);
13487       if (rex & REX_W)
13488         oappend ("QWORD PTR ");
13489       else
13490         {
13491           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13492             oappend ("DWORD PTR ");
13493           else
13494             oappend ("WORD PTR ");
13495           used_prefixes |= (prefixes & PREFIX_DATA);
13496         }
13497       break;
13498     case z_mode:
13499       if ((rex & REX_W) || (sizeflag & DFLAG))
13500         *obufp++ = 'D';
13501       oappend ("WORD PTR ");
13502       if (!(rex & REX_W))
13503         used_prefixes |= (prefixes & PREFIX_DATA);
13504       break;
13505     case a_mode:
13506       if (sizeflag & DFLAG)
13507         oappend ("QWORD PTR ");
13508       else
13509         oappend ("DWORD PTR ");
13510       used_prefixes |= (prefixes & PREFIX_DATA);
13511       break;
13512     case d_mode:
13513     case d_scalar_mode:
13514     case d_scalar_swap_mode:
13515     case d_swap_mode:
13516     case dqd_mode:
13517       oappend ("DWORD PTR ");
13518       break;
13519     case q_mode:
13520     case q_scalar_mode:
13521     case q_scalar_swap_mode:
13522     case q_swap_mode:
13523       oappend ("QWORD PTR ");
13524       break;
13525     case dqa_mode:
13526     case m_mode:
13527       if (address_mode == mode_64bit)
13528         oappend ("QWORD PTR ");
13529       else
13530         oappend ("DWORD PTR ");
13531       break;
13532     case f_mode:
13533       if (sizeflag & DFLAG)
13534         oappend ("FWORD PTR ");
13535       else
13536         oappend ("DWORD PTR ");
13537       used_prefixes |= (prefixes & PREFIX_DATA);
13538       break;
13539     case t_mode:
13540       oappend ("TBYTE PTR ");
13541       break;
13542     case x_mode:
13543     case x_swap_mode:
13544     case evex_x_gscat_mode:
13545     case evex_x_nobcst_mode:
13546     case b_scalar_mode:
13547     case w_scalar_mode:
13548       if (need_vex)
13549         {
13550           switch (vex.length)
13551             {
13552             case 128:
13553               oappend ("XMMWORD PTR ");
13554               break;
13555             case 256:
13556               oappend ("YMMWORD PTR ");
13557               break;
13558             case 512:
13559               oappend ("ZMMWORD PTR ");
13560               break;
13561             default:
13562               abort ();
13563             }
13564         }
13565       else
13566         oappend ("XMMWORD PTR ");
13567       break;
13568     case xmm_mode:
13569       oappend ("XMMWORD PTR ");
13570       break;
13571     case ymm_mode:
13572       oappend ("YMMWORD PTR ");
13573       break;
13574     case xmmq_mode:
13575     case evex_half_bcst_xmmq_mode:
13576       if (!need_vex)
13577         abort ();
13578
13579       switch (vex.length)
13580         {
13581         case 128:
13582           oappend ("QWORD PTR ");
13583           break;
13584         case 256:
13585           oappend ("XMMWORD PTR ");
13586           break;
13587         case 512:
13588           oappend ("YMMWORD PTR ");
13589           break;
13590         default:
13591           abort ();
13592         }
13593       break;
13594     case xmm_mb_mode:
13595       if (!need_vex)
13596         abort ();
13597
13598       switch (vex.length)
13599         {
13600         case 128:
13601         case 256:
13602         case 512:
13603           oappend ("BYTE PTR ");
13604           break;
13605         default:
13606           abort ();
13607         }
13608       break;
13609     case xmm_mw_mode:
13610       if (!need_vex)
13611         abort ();
13612
13613       switch (vex.length)
13614         {
13615         case 128:
13616         case 256:
13617         case 512:
13618           oappend ("WORD PTR ");
13619           break;
13620         default:
13621           abort ();
13622         }
13623       break;
13624     case xmm_md_mode:
13625       if (!need_vex)
13626         abort ();
13627
13628       switch (vex.length)
13629         {
13630         case 128:
13631         case 256:
13632         case 512:
13633           oappend ("DWORD PTR ");
13634           break;
13635         default:
13636           abort ();
13637         }
13638       break;
13639     case xmm_mq_mode:
13640       if (!need_vex)
13641         abort ();
13642
13643       switch (vex.length)
13644         {
13645         case 128:
13646         case 256:
13647         case 512:
13648           oappend ("QWORD PTR ");
13649           break;
13650         default:
13651           abort ();
13652         }
13653       break;
13654     case xmmdw_mode:
13655       if (!need_vex)
13656         abort ();
13657
13658       switch (vex.length)
13659         {
13660         case 128:
13661           oappend ("WORD PTR ");
13662           break;
13663         case 256:
13664           oappend ("DWORD PTR ");
13665           break;
13666         case 512:
13667           oappend ("QWORD PTR ");
13668           break;
13669         default:
13670           abort ();
13671         }
13672       break;
13673     case xmmqd_mode:
13674       if (!need_vex)
13675         abort ();
13676
13677       switch (vex.length)
13678         {
13679         case 128:
13680           oappend ("DWORD PTR ");
13681           break;
13682         case 256:
13683           oappend ("QWORD PTR ");
13684           break;
13685         case 512:
13686           oappend ("XMMWORD PTR ");
13687           break;
13688         default:
13689           abort ();
13690         }
13691       break;
13692     case ymmq_mode:
13693       if (!need_vex)
13694         abort ();
13695
13696       switch (vex.length)
13697         {
13698         case 128:
13699           oappend ("QWORD PTR ");
13700           break;
13701         case 256:
13702           oappend ("YMMWORD PTR ");
13703           break;
13704         case 512:
13705           oappend ("ZMMWORD PTR ");
13706           break;
13707         default:
13708           abort ();
13709         }
13710       break;
13711     case ymmxmm_mode:
13712       if (!need_vex)
13713         abort ();
13714
13715       switch (vex.length)
13716         {
13717         case 128:
13718         case 256:
13719           oappend ("XMMWORD PTR ");
13720           break;
13721         default:
13722           abort ();
13723         }
13724       break;
13725     case o_mode:
13726       oappend ("OWORD PTR ");
13727       break;
13728     case xmm_mdq_mode:
13729     case vex_w_dq_mode:
13730     case vex_scalar_w_dq_mode:
13731       if (!need_vex)
13732         abort ();
13733
13734       if (vex.w)
13735         oappend ("QWORD PTR ");
13736       else
13737         oappend ("DWORD PTR ");
13738       break;
13739     case vex_vsib_d_w_dq_mode:
13740     case vex_vsib_q_w_dq_mode:
13741       if (!need_vex)
13742         abort ();
13743
13744       if (!vex.evex)
13745         {
13746           if (vex.w)
13747             oappend ("QWORD PTR ");
13748           else
13749             oappend ("DWORD PTR ");
13750         }
13751       else
13752         {
13753           switch (vex.length)
13754             {
13755             case 128:
13756               oappend ("XMMWORD PTR ");
13757               break;
13758             case 256:
13759               oappend ("YMMWORD PTR ");
13760               break;
13761             case 512:
13762               oappend ("ZMMWORD PTR ");
13763               break;
13764             default:
13765               abort ();
13766             }
13767         }
13768       break;
13769     case vex_vsib_q_w_d_mode:
13770     case vex_vsib_d_w_d_mode:
13771       if (!need_vex || !vex.evex)
13772         abort ();
13773
13774       switch (vex.length)
13775         {
13776         case 128:
13777           oappend ("QWORD PTR ");
13778           break;
13779         case 256:
13780           oappend ("XMMWORD PTR ");
13781           break;
13782         case 512:
13783           oappend ("YMMWORD PTR ");
13784           break;
13785         default:
13786           abort ();
13787         }
13788
13789       break;
13790     case mask_bd_mode:
13791       if (!need_vex || vex.length != 128)
13792         abort ();
13793       if (vex.w)
13794         oappend ("DWORD PTR ");
13795       else
13796         oappend ("BYTE PTR ");
13797       break;
13798     case mask_mode:
13799       if (!need_vex)
13800         abort ();
13801       if (vex.w)
13802         oappend ("QWORD PTR ");
13803       else
13804         oappend ("WORD PTR ");
13805       break;
13806     case v_bnd_mode:
13807     case v_bndmk_mode:
13808     default:
13809       break;
13810     }
13811 }
13812
13813 static void
13814 OP_E_register (int bytemode, int sizeflag)
13815 {
13816   int reg = modrm.rm;
13817   const char **names;
13818
13819   USED_REX (REX_B);
13820   if ((rex & REX_B))
13821     reg += 8;
13822
13823   if ((sizeflag & SUFFIX_ALWAYS)
13824       && (bytemode == b_swap_mode
13825           || bytemode == bnd_swap_mode
13826           || bytemode == v_swap_mode))
13827     swap_operand ();
13828
13829   switch (bytemode)
13830     {
13831     case b_mode:
13832     case b_swap_mode:
13833       USED_REX (0);
13834       if (rex)
13835         names = names8rex;
13836       else
13837         names = names8;
13838       break;
13839     case w_mode:
13840       names = names16;
13841       break;
13842     case d_mode:
13843     case dw_mode:
13844     case db_mode:
13845       names = names32;
13846       break;
13847     case q_mode:
13848       names = names64;
13849       break;
13850     case m_mode:
13851     case v_bnd_mode:
13852       names = address_mode == mode_64bit ? names64 : names32;
13853       break;
13854     case bnd_mode:
13855     case bnd_swap_mode:
13856       if (reg > 0x3)
13857         {
13858           oappend ("(bad)");
13859           return;
13860         }
13861       names = names_bnd;
13862       break;
13863     case indir_v_mode:
13864       if (address_mode == mode_64bit && isa64 == intel64)
13865         {
13866           names = names64;
13867           break;
13868         }
13869       /* Fall through.  */
13870     case stack_v_mode:
13871       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13872         {
13873           names = names64;
13874           break;
13875         }
13876       bytemode = v_mode;
13877       /* Fall through.  */
13878     case v_mode:
13879     case v_swap_mode:
13880     case dq_mode:
13881     case dqb_mode:
13882     case dqd_mode:
13883     case dqw_mode:
13884     case dqa_mode:
13885       USED_REX (REX_W);
13886       if (rex & REX_W)
13887         names = names64;
13888       else
13889         {
13890           if ((sizeflag & DFLAG)
13891               || (bytemode != v_mode
13892                   && bytemode != v_swap_mode))
13893             names = names32;
13894           else
13895             names = names16;
13896           used_prefixes |= (prefixes & PREFIX_DATA);
13897         }
13898       break;
13899     case va_mode:
13900       names = (address_mode == mode_64bit
13901                ? names64 : names32);
13902       if (!(prefixes & PREFIX_ADDR))
13903         names = (address_mode == mode_16bit
13904                      ? names16 : names);
13905       else
13906         {
13907           /* Remove "addr16/addr32".  */
13908           all_prefixes[last_addr_prefix] = 0;
13909           names = (address_mode != mode_32bit
13910                        ? names32 : names16);
13911           used_prefixes |= PREFIX_ADDR;
13912         }
13913       break;
13914     case mask_bd_mode:
13915     case mask_mode:
13916       if (reg > 0x7)
13917         {
13918           oappend ("(bad)");
13919           return;
13920         }
13921       names = names_mask;
13922       break;
13923     case 0:
13924       return;
13925     default:
13926       oappend (INTERNAL_DISASSEMBLER_ERROR);
13927       return;
13928     }
13929   oappend (names[reg]);
13930 }
13931
13932 static void
13933 OP_E_memory (int bytemode, int sizeflag)
13934 {
13935   bfd_vma disp = 0;
13936   int add = (rex & REX_B) ? 8 : 0;
13937   int riprel = 0;
13938   int shift;
13939
13940   if (vex.evex)
13941     {
13942       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13943       if (vex.b
13944           && bytemode != x_mode
13945           && bytemode != xmmq_mode
13946           && bytemode != evex_half_bcst_xmmq_mode)
13947         {
13948           BadOp ();
13949           return;
13950         }
13951       switch (bytemode)
13952         {
13953         case dqw_mode:
13954         case dw_mode:
13955           shift = 1;
13956           break;
13957         case dqb_mode:
13958         case db_mode:
13959           shift = 0;
13960           break;
13961         case dq_mode:
13962           if (address_mode != mode_64bit)
13963             {
13964               shift = 2;
13965               break;
13966             }
13967             /* fall through */
13968         case vex_vsib_d_w_dq_mode:
13969         case vex_vsib_d_w_d_mode:
13970         case vex_vsib_q_w_dq_mode:
13971         case vex_vsib_q_w_d_mode:
13972         case evex_x_gscat_mode:
13973         case xmm_mdq_mode:
13974           shift = vex.w ? 3 : 2;
13975           break;
13976         case x_mode:
13977         case evex_half_bcst_xmmq_mode:
13978         case xmmq_mode:
13979           if (vex.b)
13980             {
13981               shift = vex.w ? 3 : 2;
13982               break;
13983             }
13984           /* Fall through.  */
13985         case xmmqd_mode:
13986         case xmmdw_mode:
13987         case ymmq_mode:
13988         case evex_x_nobcst_mode:
13989         case x_swap_mode:
13990           switch (vex.length)
13991             {
13992             case 128:
13993               shift = 4;
13994               break;
13995             case 256:
13996               shift = 5;
13997               break;
13998             case 512:
13999               shift = 6;
14000               break;
14001             default:
14002               abort ();
14003             }
14004           break;
14005         case ymm_mode:
14006           shift = 5;
14007           break;
14008         case xmm_mode:
14009           shift = 4;
14010           break;
14011         case xmm_mq_mode:
14012         case q_mode:
14013         case q_scalar_mode:
14014         case q_swap_mode:
14015         case q_scalar_swap_mode:
14016           shift = 3;
14017           break;
14018         case dqd_mode:
14019         case xmm_md_mode:
14020         case d_mode:
14021         case d_scalar_mode:
14022         case d_swap_mode:
14023         case d_scalar_swap_mode:
14024           shift = 2;
14025           break;
14026         case w_scalar_mode:
14027         case xmm_mw_mode:
14028           shift = 1;
14029           break;
14030         case b_scalar_mode:
14031         case xmm_mb_mode:
14032           shift = 0;
14033           break;
14034         case dqa_mode:
14035           shift = address_mode == mode_64bit ? 3 : 2;
14036           break;
14037         default:
14038           abort ();
14039         }
14040       /* Make necessary corrections to shift for modes that need it.
14041          For these modes we currently have shift 4, 5 or 6 depending on
14042          vex.length (it corresponds to xmmword, ymmword or zmmword
14043          operand).  We might want to make it 3, 4 or 5 (e.g. for
14044          xmmq_mode).  In case of broadcast enabled the corrections
14045          aren't needed, as element size is always 32 or 64 bits.  */
14046       if (!vex.b
14047           && (bytemode == xmmq_mode
14048               || bytemode == evex_half_bcst_xmmq_mode))
14049         shift -= 1;
14050       else if (bytemode == xmmqd_mode)
14051         shift -= 2;
14052       else if (bytemode == xmmdw_mode)
14053         shift -= 3;
14054       else if (bytemode == ymmq_mode && vex.length == 128)
14055         shift -= 1;
14056     }
14057   else
14058     shift = 0;
14059
14060   USED_REX (REX_B);
14061   if (intel_syntax)
14062     intel_operand_size (bytemode, sizeflag);
14063   append_seg ();
14064
14065   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14066     {
14067       /* 32/64 bit address mode */
14068       int havedisp;
14069       int havesib;
14070       int havebase;
14071       int haveindex;
14072       int needindex;
14073       int needaddr32;
14074       int base, rbase;
14075       int vindex = 0;
14076       int scale = 0;
14077       int addr32flag = !((sizeflag & AFLAG)
14078                          || bytemode == v_bnd_mode
14079                          || bytemode == v_bndmk_mode
14080                          || bytemode == bnd_mode
14081                          || bytemode == bnd_swap_mode);
14082       const char **indexes64 = names64;
14083       const char **indexes32 = names32;
14084
14085       havesib = 0;
14086       havebase = 1;
14087       haveindex = 0;
14088       base = modrm.rm;
14089
14090       if (base == 4)
14091         {
14092           havesib = 1;
14093           vindex = sib.index;
14094           USED_REX (REX_X);
14095           if (rex & REX_X)
14096             vindex += 8;
14097           switch (bytemode)
14098             {
14099             case vex_vsib_d_w_dq_mode:
14100             case vex_vsib_d_w_d_mode:
14101             case vex_vsib_q_w_dq_mode:
14102             case vex_vsib_q_w_d_mode:
14103               if (!need_vex)
14104                 abort ();
14105               if (vex.evex)
14106                 {
14107                   if (!vex.v)
14108                     vindex += 16;
14109                 }
14110
14111               haveindex = 1;
14112               switch (vex.length)
14113                 {
14114                 case 128:
14115                   indexes64 = indexes32 = names_xmm;
14116                   break;
14117                 case 256:
14118                   if (!vex.w
14119                       || bytemode == vex_vsib_q_w_dq_mode
14120                       || bytemode == vex_vsib_q_w_d_mode)
14121                     indexes64 = indexes32 = names_ymm;
14122                   else
14123                     indexes64 = indexes32 = names_xmm;
14124                   break;
14125                 case 512:
14126                   if (!vex.w
14127                       || bytemode == vex_vsib_q_w_dq_mode
14128                       || bytemode == vex_vsib_q_w_d_mode)
14129                     indexes64 = indexes32 = names_zmm;
14130                   else
14131                     indexes64 = indexes32 = names_ymm;
14132                   break;
14133                 default:
14134                   abort ();
14135                 }
14136               break;
14137             default:
14138               haveindex = vindex != 4;
14139               break;
14140             }
14141           scale = sib.scale;
14142           base = sib.base;
14143           codep++;
14144         }
14145       rbase = base + add;
14146
14147       switch (modrm.mod)
14148         {
14149         case 0:
14150           if (base == 5)
14151             {
14152               havebase = 0;
14153               if (address_mode == mode_64bit && !havesib)
14154                 riprel = 1;
14155               disp = get32s ();
14156               if (riprel && bytemode == v_bndmk_mode)
14157                 {
14158                   oappend ("(bad)");
14159                   return;
14160                 }
14161             }
14162           break;
14163         case 1:
14164           FETCH_DATA (the_info, codep + 1);
14165           disp = *codep++;
14166           if ((disp & 0x80) != 0)
14167             disp -= 0x100;
14168           if (vex.evex && shift > 0)
14169             disp <<= shift;
14170           break;
14171         case 2:
14172           disp = get32s ();
14173           break;
14174         }
14175
14176       needindex = 0;
14177       needaddr32 = 0;
14178       if (havesib
14179           && !havebase
14180           && !haveindex
14181           && address_mode != mode_16bit)
14182         {
14183           if (address_mode == mode_64bit)
14184             {
14185               /* Display eiz instead of addr32.  */
14186               needindex = addr32flag;
14187               needaddr32 = 1;
14188             }
14189           else
14190             {
14191               /* In 32-bit mode, we need index register to tell [offset]
14192                  from [eiz*1 + offset].  */
14193               needindex = 1;
14194             }
14195         }
14196
14197       havedisp = (havebase
14198                   || needindex
14199                   || (havesib && (haveindex || scale != 0)));
14200
14201       if (!intel_syntax)
14202         if (modrm.mod != 0 || base == 5)
14203           {
14204             if (havedisp || riprel)
14205               print_displacement (scratchbuf, disp);
14206             else
14207               print_operand_value (scratchbuf, 1, disp);
14208             oappend (scratchbuf);
14209             if (riprel)
14210               {
14211                 set_op (disp, 1);
14212                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14213               }
14214           }
14215
14216       if ((havebase || haveindex || needaddr32 || riprel)
14217           && (bytemode != v_bnd_mode)
14218           && (bytemode != v_bndmk_mode)
14219           && (bytemode != bnd_mode)
14220           && (bytemode != bnd_swap_mode))
14221         used_prefixes |= PREFIX_ADDR;
14222
14223       if (havedisp || (intel_syntax && riprel))
14224         {
14225           *obufp++ = open_char;
14226           if (intel_syntax && riprel)
14227             {
14228               set_op (disp, 1);
14229               oappend (!addr32flag ? "rip" : "eip");
14230             }
14231           *obufp = '\0';
14232           if (havebase)
14233             oappend (address_mode == mode_64bit && !addr32flag
14234                      ? names64[rbase] : names32[rbase]);
14235           if (havesib)
14236             {
14237               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14238                  print index to tell base + index from base.  */
14239               if (scale != 0
14240                   || needindex
14241                   || haveindex
14242                   || (havebase && base != ESP_REG_NUM))
14243                 {
14244                   if (!intel_syntax || havebase)
14245                     {
14246                       *obufp++ = separator_char;
14247                       *obufp = '\0';
14248                     }
14249                   if (haveindex)
14250                     oappend (address_mode == mode_64bit && !addr32flag
14251                              ? indexes64[vindex] : indexes32[vindex]);
14252                   else
14253                     oappend (address_mode == mode_64bit && !addr32flag
14254                              ? index64 : index32);
14255
14256                   *obufp++ = scale_char;
14257                   *obufp = '\0';
14258                   sprintf (scratchbuf, "%d", 1 << scale);
14259                   oappend (scratchbuf);
14260                 }
14261             }
14262           if (intel_syntax
14263               && (disp || modrm.mod != 0 || base == 5))
14264             {
14265               if (!havedisp || (bfd_signed_vma) disp >= 0)
14266                 {
14267                   *obufp++ = '+';
14268                   *obufp = '\0';
14269                 }
14270               else if (modrm.mod != 1 && disp != -disp)
14271                 {
14272                   *obufp++ = '-';
14273                   *obufp = '\0';
14274                   disp = - (bfd_signed_vma) disp;
14275                 }
14276
14277               if (havedisp)
14278                 print_displacement (scratchbuf, disp);
14279               else
14280                 print_operand_value (scratchbuf, 1, disp);
14281               oappend (scratchbuf);
14282             }
14283
14284           *obufp++ = close_char;
14285           *obufp = '\0';
14286         }
14287       else if (intel_syntax)
14288         {
14289           if (modrm.mod != 0 || base == 5)
14290             {
14291               if (!active_seg_prefix)
14292                 {
14293                   oappend (names_seg[ds_reg - es_reg]);
14294                   oappend (":");
14295                 }
14296               print_operand_value (scratchbuf, 1, disp);
14297               oappend (scratchbuf);
14298             }
14299         }
14300     }
14301   else
14302     {
14303       /* 16 bit address mode */
14304       used_prefixes |= prefixes & PREFIX_ADDR;
14305       switch (modrm.mod)
14306         {
14307         case 0:
14308           if (modrm.rm == 6)
14309             {
14310               disp = get16 ();
14311               if ((disp & 0x8000) != 0)
14312                 disp -= 0x10000;
14313             }
14314           break;
14315         case 1:
14316           FETCH_DATA (the_info, codep + 1);
14317           disp = *codep++;
14318           if ((disp & 0x80) != 0)
14319             disp -= 0x100;
14320           if (vex.evex && shift > 0)
14321             disp <<= shift;
14322           break;
14323         case 2:
14324           disp = get16 ();
14325           if ((disp & 0x8000) != 0)
14326             disp -= 0x10000;
14327           break;
14328         }
14329
14330       if (!intel_syntax)
14331         if (modrm.mod != 0 || modrm.rm == 6)
14332           {
14333             print_displacement (scratchbuf, disp);
14334             oappend (scratchbuf);
14335           }
14336
14337       if (modrm.mod != 0 || modrm.rm != 6)
14338         {
14339           *obufp++ = open_char;
14340           *obufp = '\0';
14341           oappend (index16[modrm.rm]);
14342           if (intel_syntax
14343               && (disp || modrm.mod != 0 || modrm.rm == 6))
14344             {
14345               if ((bfd_signed_vma) disp >= 0)
14346                 {
14347                   *obufp++ = '+';
14348                   *obufp = '\0';
14349                 }
14350               else if (modrm.mod != 1)
14351                 {
14352                   *obufp++ = '-';
14353                   *obufp = '\0';
14354                   disp = - (bfd_signed_vma) disp;
14355                 }
14356
14357               print_displacement (scratchbuf, disp);
14358               oappend (scratchbuf);
14359             }
14360
14361           *obufp++ = close_char;
14362           *obufp = '\0';
14363         }
14364       else if (intel_syntax)
14365         {
14366           if (!active_seg_prefix)
14367             {
14368               oappend (names_seg[ds_reg - es_reg]);
14369               oappend (":");
14370             }
14371           print_operand_value (scratchbuf, 1, disp & 0xffff);
14372           oappend (scratchbuf);
14373         }
14374     }
14375   if (vex.evex && vex.b
14376       && (bytemode == x_mode
14377           || bytemode == xmmq_mode
14378           || bytemode == evex_half_bcst_xmmq_mode))
14379     {
14380       if (vex.w
14381           || bytemode == xmmq_mode
14382           || bytemode == evex_half_bcst_xmmq_mode)
14383         {
14384           switch (vex.length)
14385             {
14386             case 128:
14387               oappend ("{1to2}");
14388               break;
14389             case 256:
14390               oappend ("{1to4}");
14391               break;
14392             case 512:
14393               oappend ("{1to8}");
14394               break;
14395             default:
14396               abort ();
14397             }
14398         }
14399       else
14400         {
14401           switch (vex.length)
14402             {
14403             case 128:
14404               oappend ("{1to4}");
14405               break;
14406             case 256:
14407               oappend ("{1to8}");
14408               break;
14409             case 512:
14410               oappend ("{1to16}");
14411               break;
14412             default:
14413               abort ();
14414             }
14415         }
14416     }
14417 }
14418
14419 static void
14420 OP_E (int bytemode, int sizeflag)
14421 {
14422   /* Skip mod/rm byte.  */
14423   MODRM_CHECK;
14424   codep++;
14425
14426   if (modrm.mod == 3)
14427     OP_E_register (bytemode, sizeflag);
14428   else
14429     OP_E_memory (bytemode, sizeflag);
14430 }
14431
14432 static void
14433 OP_G (int bytemode, int sizeflag)
14434 {
14435   int add = 0;
14436   const char **names;
14437   USED_REX (REX_R);
14438   if (rex & REX_R)
14439     add += 8;
14440   switch (bytemode)
14441     {
14442     case b_mode:
14443       USED_REX (0);
14444       if (rex)
14445         oappend (names8rex[modrm.reg + add]);
14446       else
14447         oappend (names8[modrm.reg + add]);
14448       break;
14449     case w_mode:
14450       oappend (names16[modrm.reg + add]);
14451       break;
14452     case d_mode:
14453     case db_mode:
14454     case dw_mode:
14455       oappend (names32[modrm.reg + add]);
14456       break;
14457     case q_mode:
14458       oappend (names64[modrm.reg + add]);
14459       break;
14460     case bnd_mode:
14461       if (modrm.reg > 0x3)
14462         {
14463           oappend ("(bad)");
14464           return;
14465         }
14466       oappend (names_bnd[modrm.reg]);
14467       break;
14468     case v_mode:
14469     case dq_mode:
14470     case dqb_mode:
14471     case dqd_mode:
14472     case dqw_mode:
14473       USED_REX (REX_W);
14474       if (rex & REX_W)
14475         oappend (names64[modrm.reg + add]);
14476       else
14477         {
14478           if ((sizeflag & DFLAG) || bytemode != v_mode)
14479             oappend (names32[modrm.reg + add]);
14480           else
14481             oappend (names16[modrm.reg + add]);
14482           used_prefixes |= (prefixes & PREFIX_DATA);
14483         }
14484       break;
14485     case va_mode:
14486       names = (address_mode == mode_64bit
14487                ? names64 : names32);
14488       if (!(prefixes & PREFIX_ADDR))
14489         {
14490           if (address_mode == mode_16bit)
14491             names = names16;
14492         }
14493       else
14494         {
14495           /* Remove "addr16/addr32".  */
14496           all_prefixes[last_addr_prefix] = 0;
14497           names = (address_mode != mode_32bit
14498                        ? names32 : names16);
14499           used_prefixes |= PREFIX_ADDR;
14500         }
14501       oappend (names[modrm.reg + add]);
14502       break;
14503     case m_mode:
14504       if (address_mode == mode_64bit)
14505         oappend (names64[modrm.reg + add]);
14506       else
14507         oappend (names32[modrm.reg + add]);
14508       break;
14509     case mask_bd_mode:
14510     case mask_mode:
14511       if ((modrm.reg + add) > 0x7)
14512         {
14513           oappend ("(bad)");
14514           return;
14515         }
14516       oappend (names_mask[modrm.reg + add]);
14517       break;
14518     default:
14519       oappend (INTERNAL_DISASSEMBLER_ERROR);
14520       break;
14521     }
14522 }
14523
14524 static bfd_vma
14525 get64 (void)
14526 {
14527   bfd_vma x;
14528 #ifdef BFD64
14529   unsigned int a;
14530   unsigned int b;
14531
14532   FETCH_DATA (the_info, codep + 8);
14533   a = *codep++ & 0xff;
14534   a |= (*codep++ & 0xff) << 8;
14535   a |= (*codep++ & 0xff) << 16;
14536   a |= (*codep++ & 0xffu) << 24;
14537   b = *codep++ & 0xff;
14538   b |= (*codep++ & 0xff) << 8;
14539   b |= (*codep++ & 0xff) << 16;
14540   b |= (*codep++ & 0xffu) << 24;
14541   x = a + ((bfd_vma) b << 32);
14542 #else
14543   abort ();
14544   x = 0;
14545 #endif
14546   return x;
14547 }
14548
14549 static bfd_signed_vma
14550 get32 (void)
14551 {
14552   bfd_signed_vma x = 0;
14553
14554   FETCH_DATA (the_info, codep + 4);
14555   x = *codep++ & (bfd_signed_vma) 0xff;
14556   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14557   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14558   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14559   return x;
14560 }
14561
14562 static bfd_signed_vma
14563 get32s (void)
14564 {
14565   bfd_signed_vma x = 0;
14566
14567   FETCH_DATA (the_info, codep + 4);
14568   x = *codep++ & (bfd_signed_vma) 0xff;
14569   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14570   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14571   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14572
14573   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14574
14575   return x;
14576 }
14577
14578 static int
14579 get16 (void)
14580 {
14581   int x = 0;
14582
14583   FETCH_DATA (the_info, codep + 2);
14584   x = *codep++ & 0xff;
14585   x |= (*codep++ & 0xff) << 8;
14586   return x;
14587 }
14588
14589 static void
14590 set_op (bfd_vma op, int riprel)
14591 {
14592   op_index[op_ad] = op_ad;
14593   if (address_mode == mode_64bit)
14594     {
14595       op_address[op_ad] = op;
14596       op_riprel[op_ad] = riprel;
14597     }
14598   else
14599     {
14600       /* Mask to get a 32-bit address.  */
14601       op_address[op_ad] = op & 0xffffffff;
14602       op_riprel[op_ad] = riprel & 0xffffffff;
14603     }
14604 }
14605
14606 static void
14607 OP_REG (int code, int sizeflag)
14608 {
14609   const char *s;
14610   int add;
14611
14612   switch (code)
14613     {
14614     case es_reg: case ss_reg: case cs_reg:
14615     case ds_reg: case fs_reg: case gs_reg:
14616       oappend (names_seg[code - es_reg]);
14617       return;
14618     }
14619
14620   USED_REX (REX_B);
14621   if (rex & REX_B)
14622     add = 8;
14623   else
14624     add = 0;
14625
14626   switch (code)
14627     {
14628     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14629     case sp_reg: case bp_reg: case si_reg: case di_reg:
14630       s = names16[code - ax_reg + add];
14631       break;
14632     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14633     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14634       USED_REX (0);
14635       if (rex)
14636         s = names8rex[code - al_reg + add];
14637       else
14638         s = names8[code - al_reg];
14639       break;
14640     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14641     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14642       if (address_mode == mode_64bit
14643           && ((sizeflag & DFLAG) || (rex & REX_W)))
14644         {
14645           s = names64[code - rAX_reg + add];
14646           break;
14647         }
14648       code += eAX_reg - rAX_reg;
14649       /* Fall through.  */
14650     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14651     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14652       USED_REX (REX_W);
14653       if (rex & REX_W)
14654         s = names64[code - eAX_reg + add];
14655       else
14656         {
14657           if (sizeflag & DFLAG)
14658             s = names32[code - eAX_reg + add];
14659           else
14660             s = names16[code - eAX_reg + add];
14661           used_prefixes |= (prefixes & PREFIX_DATA);
14662         }
14663       break;
14664     default:
14665       s = INTERNAL_DISASSEMBLER_ERROR;
14666       break;
14667     }
14668   oappend (s);
14669 }
14670
14671 static void
14672 OP_IMREG (int code, int sizeflag)
14673 {
14674   const char *s;
14675
14676   switch (code)
14677     {
14678     case indir_dx_reg:
14679       if (intel_syntax)
14680         s = "dx";
14681       else
14682         s = "(%dx)";
14683       break;
14684     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14685     case sp_reg: case bp_reg: case si_reg: case di_reg:
14686       s = names16[code - ax_reg];
14687       break;
14688     case es_reg: case ss_reg: case cs_reg:
14689     case ds_reg: case fs_reg: case gs_reg:
14690       s = names_seg[code - es_reg];
14691       break;
14692     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14693     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14694       USED_REX (0);
14695       if (rex)
14696         s = names8rex[code - al_reg];
14697       else
14698         s = names8[code - al_reg];
14699       break;
14700     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14701     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14702       USED_REX (REX_W);
14703       if (rex & REX_W)
14704         s = names64[code - eAX_reg];
14705       else
14706         {
14707           if (sizeflag & DFLAG)
14708             s = names32[code - eAX_reg];
14709           else
14710             s = names16[code - eAX_reg];
14711           used_prefixes |= (prefixes & PREFIX_DATA);
14712         }
14713       break;
14714     case z_mode_ax_reg:
14715       if ((rex & REX_W) || (sizeflag & DFLAG))
14716         s = *names32;
14717       else
14718         s = *names16;
14719       if (!(rex & REX_W))
14720         used_prefixes |= (prefixes & PREFIX_DATA);
14721       break;
14722     default:
14723       s = INTERNAL_DISASSEMBLER_ERROR;
14724       break;
14725     }
14726   oappend (s);
14727 }
14728
14729 static void
14730 OP_I (int bytemode, int sizeflag)
14731 {
14732   bfd_signed_vma op;
14733   bfd_signed_vma mask = -1;
14734
14735   switch (bytemode)
14736     {
14737     case b_mode:
14738       FETCH_DATA (the_info, codep + 1);
14739       op = *codep++;
14740       mask = 0xff;
14741       break;
14742     case q_mode:
14743       if (address_mode == mode_64bit)
14744         {
14745           op = get32s ();
14746           break;
14747         }
14748       /* Fall through.  */
14749     case v_mode:
14750       USED_REX (REX_W);
14751       if (rex & REX_W)
14752         op = get32s ();
14753       else
14754         {
14755           if (sizeflag & DFLAG)
14756             {
14757               op = get32 ();
14758               mask = 0xffffffff;
14759             }
14760           else
14761             {
14762               op = get16 ();
14763               mask = 0xfffff;
14764             }
14765           used_prefixes |= (prefixes & PREFIX_DATA);
14766         }
14767       break;
14768     case w_mode:
14769       mask = 0xfffff;
14770       op = get16 ();
14771       break;
14772     case const_1_mode:
14773       if (intel_syntax)
14774         oappend ("1");
14775       return;
14776     default:
14777       oappend (INTERNAL_DISASSEMBLER_ERROR);
14778       return;
14779     }
14780
14781   op &= mask;
14782   scratchbuf[0] = '$';
14783   print_operand_value (scratchbuf + 1, 1, op);
14784   oappend_maybe_intel (scratchbuf);
14785   scratchbuf[0] = '\0';
14786 }
14787
14788 static void
14789 OP_I64 (int bytemode, int sizeflag)
14790 {
14791   bfd_signed_vma op;
14792   bfd_signed_vma mask = -1;
14793
14794   if (address_mode != mode_64bit)
14795     {
14796       OP_I (bytemode, sizeflag);
14797       return;
14798     }
14799
14800   switch (bytemode)
14801     {
14802     case b_mode:
14803       FETCH_DATA (the_info, codep + 1);
14804       op = *codep++;
14805       mask = 0xff;
14806       break;
14807     case v_mode:
14808       USED_REX (REX_W);
14809       if (rex & REX_W)
14810         op = get64 ();
14811       else
14812         {
14813           if (sizeflag & DFLAG)
14814             {
14815               op = get32 ();
14816               mask = 0xffffffff;
14817             }
14818           else
14819             {
14820               op = get16 ();
14821               mask = 0xfffff;
14822             }
14823           used_prefixes |= (prefixes & PREFIX_DATA);
14824         }
14825       break;
14826     case w_mode:
14827       mask = 0xfffff;
14828       op = get16 ();
14829       break;
14830     default:
14831       oappend (INTERNAL_DISASSEMBLER_ERROR);
14832       return;
14833     }
14834
14835   op &= mask;
14836   scratchbuf[0] = '$';
14837   print_operand_value (scratchbuf + 1, 1, op);
14838   oappend_maybe_intel (scratchbuf);
14839   scratchbuf[0] = '\0';
14840 }
14841
14842 static void
14843 OP_sI (int bytemode, int sizeflag)
14844 {
14845   bfd_signed_vma op;
14846
14847   switch (bytemode)
14848     {
14849     case b_mode:
14850     case b_T_mode:
14851       FETCH_DATA (the_info, codep + 1);
14852       op = *codep++;
14853       if ((op & 0x80) != 0)
14854         op -= 0x100;
14855       if (bytemode == b_T_mode)
14856         {
14857           if (address_mode != mode_64bit
14858               || !((sizeflag & DFLAG) || (rex & REX_W)))
14859             {
14860               /* The operand-size prefix is overridden by a REX prefix.  */
14861               if ((sizeflag & DFLAG) || (rex & REX_W))
14862                 op &= 0xffffffff;
14863               else
14864                 op &= 0xffff;
14865           }
14866         }
14867       else
14868         {
14869           if (!(rex & REX_W))
14870             {
14871               if (sizeflag & DFLAG)
14872                 op &= 0xffffffff;
14873               else
14874                 op &= 0xffff;
14875             }
14876         }
14877       break;
14878     case v_mode:
14879       /* The operand-size prefix is overridden by a REX prefix.  */
14880       if ((sizeflag & DFLAG) || (rex & REX_W))
14881         op = get32s ();
14882       else
14883         op = get16 ();
14884       break;
14885     default:
14886       oappend (INTERNAL_DISASSEMBLER_ERROR);
14887       return;
14888     }
14889
14890   scratchbuf[0] = '$';
14891   print_operand_value (scratchbuf + 1, 1, op);
14892   oappend_maybe_intel (scratchbuf);
14893 }
14894
14895 static void
14896 OP_J (int bytemode, int sizeflag)
14897 {
14898   bfd_vma disp;
14899   bfd_vma mask = -1;
14900   bfd_vma segment = 0;
14901
14902   switch (bytemode)
14903     {
14904     case b_mode:
14905       FETCH_DATA (the_info, codep + 1);
14906       disp = *codep++;
14907       if ((disp & 0x80) != 0)
14908         disp -= 0x100;
14909       break;
14910     case v_mode:
14911       if (isa64 == amd64)
14912         USED_REX (REX_W);
14913       if ((sizeflag & DFLAG)
14914           || (address_mode == mode_64bit
14915               && (isa64 != amd64 || (rex & REX_W))))
14916         disp = get32s ();
14917       else
14918         {
14919           disp = get16 ();
14920           if ((disp & 0x8000) != 0)
14921             disp -= 0x10000;
14922           /* In 16bit mode, address is wrapped around at 64k within
14923              the same segment.  Otherwise, a data16 prefix on a jump
14924              instruction means that the pc is masked to 16 bits after
14925              the displacement is added!  */
14926           mask = 0xffff;
14927           if ((prefixes & PREFIX_DATA) == 0)
14928             segment = ((start_pc + (codep - start_codep))
14929                        & ~((bfd_vma) 0xffff));
14930         }
14931       if (address_mode != mode_64bit
14932           || (isa64 == amd64 && !(rex & REX_W)))
14933         used_prefixes |= (prefixes & PREFIX_DATA);
14934       break;
14935     default:
14936       oappend (INTERNAL_DISASSEMBLER_ERROR);
14937       return;
14938     }
14939   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14940   set_op (disp, 0);
14941   print_operand_value (scratchbuf, 1, disp);
14942   oappend (scratchbuf);
14943 }
14944
14945 static void
14946 OP_SEG (int bytemode, int sizeflag)
14947 {
14948   if (bytemode == w_mode)
14949     oappend (names_seg[modrm.reg]);
14950   else
14951     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14952 }
14953
14954 static void
14955 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14956 {
14957   int seg, offset;
14958
14959   if (sizeflag & DFLAG)
14960     {
14961       offset = get32 ();
14962       seg = get16 ();
14963     }
14964   else
14965     {
14966       offset = get16 ();
14967       seg = get16 ();
14968     }
14969   used_prefixes |= (prefixes & PREFIX_DATA);
14970   if (intel_syntax)
14971     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14972   else
14973     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14974   oappend (scratchbuf);
14975 }
14976
14977 static void
14978 OP_OFF (int bytemode, int sizeflag)
14979 {
14980   bfd_vma off;
14981
14982   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14983     intel_operand_size (bytemode, sizeflag);
14984   append_seg ();
14985
14986   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14987     off = get32 ();
14988   else
14989     off = get16 ();
14990
14991   if (intel_syntax)
14992     {
14993       if (!active_seg_prefix)
14994         {
14995           oappend (names_seg[ds_reg - es_reg]);
14996           oappend (":");
14997         }
14998     }
14999   print_operand_value (scratchbuf, 1, off);
15000   oappend (scratchbuf);
15001 }
15002
15003 static void
15004 OP_OFF64 (int bytemode, int sizeflag)
15005 {
15006   bfd_vma off;
15007
15008   if (address_mode != mode_64bit
15009       || (prefixes & PREFIX_ADDR))
15010     {
15011       OP_OFF (bytemode, sizeflag);
15012       return;
15013     }
15014
15015   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15016     intel_operand_size (bytemode, sizeflag);
15017   append_seg ();
15018
15019   off = get64 ();
15020
15021   if (intel_syntax)
15022     {
15023       if (!active_seg_prefix)
15024         {
15025           oappend (names_seg[ds_reg - es_reg]);
15026           oappend (":");
15027         }
15028     }
15029   print_operand_value (scratchbuf, 1, off);
15030   oappend (scratchbuf);
15031 }
15032
15033 static void
15034 ptr_reg (int code, int sizeflag)
15035 {
15036   const char *s;
15037
15038   *obufp++ = open_char;
15039   used_prefixes |= (prefixes & PREFIX_ADDR);
15040   if (address_mode == mode_64bit)
15041     {
15042       if (!(sizeflag & AFLAG))
15043         s = names32[code - eAX_reg];
15044       else
15045         s = names64[code - eAX_reg];
15046     }
15047   else if (sizeflag & AFLAG)
15048     s = names32[code - eAX_reg];
15049   else
15050     s = names16[code - eAX_reg];
15051   oappend (s);
15052   *obufp++ = close_char;
15053   *obufp = 0;
15054 }
15055
15056 static void
15057 OP_ESreg (int code, int sizeflag)
15058 {
15059   if (intel_syntax)
15060     {
15061       switch (codep[-1])
15062         {
15063         case 0x6d:      /* insw/insl */
15064           intel_operand_size (z_mode, sizeflag);
15065           break;
15066         case 0xa5:      /* movsw/movsl/movsq */
15067         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15068         case 0xab:      /* stosw/stosl */
15069         case 0xaf:      /* scasw/scasl */
15070           intel_operand_size (v_mode, sizeflag);
15071           break;
15072         default:
15073           intel_operand_size (b_mode, sizeflag);
15074         }
15075     }
15076   oappend_maybe_intel ("%es:");
15077   ptr_reg (code, sizeflag);
15078 }
15079
15080 static void
15081 OP_DSreg (int code, int sizeflag)
15082 {
15083   if (intel_syntax)
15084     {
15085       switch (codep[-1])
15086         {
15087         case 0x6f:      /* outsw/outsl */
15088           intel_operand_size (z_mode, sizeflag);
15089           break;
15090         case 0xa5:      /* movsw/movsl/movsq */
15091         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15092         case 0xad:      /* lodsw/lodsl/lodsq */
15093           intel_operand_size (v_mode, sizeflag);
15094           break;
15095         default:
15096           intel_operand_size (b_mode, sizeflag);
15097         }
15098     }
15099   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15100      default segment register DS is printed.  */
15101   if (!active_seg_prefix)
15102     active_seg_prefix = PREFIX_DS;
15103   append_seg ();
15104   ptr_reg (code, sizeflag);
15105 }
15106
15107 static void
15108 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15109 {
15110   int add;
15111   if (rex & REX_R)
15112     {
15113       USED_REX (REX_R);
15114       add = 8;
15115     }
15116   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15117     {
15118       all_prefixes[last_lock_prefix] = 0;
15119       used_prefixes |= PREFIX_LOCK;
15120       add = 8;
15121     }
15122   else
15123     add = 0;
15124   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15125   oappend_maybe_intel (scratchbuf);
15126 }
15127
15128 static void
15129 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15130 {
15131   int add;
15132   USED_REX (REX_R);
15133   if (rex & REX_R)
15134     add = 8;
15135   else
15136     add = 0;
15137   if (intel_syntax)
15138     sprintf (scratchbuf, "db%d", modrm.reg + add);
15139   else
15140     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15141   oappend (scratchbuf);
15142 }
15143
15144 static void
15145 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15146 {
15147   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15148   oappend_maybe_intel (scratchbuf);
15149 }
15150
15151 static void
15152 OP_R (int bytemode, int sizeflag)
15153 {
15154   /* Skip mod/rm byte.  */
15155   MODRM_CHECK;
15156   codep++;
15157   OP_E_register (bytemode, sizeflag);
15158 }
15159
15160 static void
15161 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15162 {
15163   int reg = modrm.reg;
15164   const char **names;
15165
15166   used_prefixes |= (prefixes & PREFIX_DATA);
15167   if (prefixes & PREFIX_DATA)
15168     {
15169       names = names_xmm;
15170       USED_REX (REX_R);
15171       if (rex & REX_R)
15172         reg += 8;
15173     }
15174   else
15175     names = names_mm;
15176   oappend (names[reg]);
15177 }
15178
15179 static void
15180 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15181 {
15182   int reg = modrm.reg;
15183   const char **names;
15184
15185   USED_REX (REX_R);
15186   if (rex & REX_R)
15187     reg += 8;
15188   if (vex.evex)
15189     {
15190       if (!vex.r)
15191         reg += 16;
15192     }
15193
15194   if (need_vex
15195       && bytemode != xmm_mode
15196       && bytemode != xmmq_mode
15197       && bytemode != evex_half_bcst_xmmq_mode
15198       && bytemode != ymm_mode
15199       && bytemode != scalar_mode)
15200     {
15201       switch (vex.length)
15202         {
15203         case 128:
15204           names = names_xmm;
15205           break;
15206         case 256:
15207           if (vex.w
15208               || (bytemode != vex_vsib_q_w_dq_mode
15209                   && bytemode != vex_vsib_q_w_d_mode))
15210             names = names_ymm;
15211           else
15212             names = names_xmm;
15213           break;
15214         case 512:
15215           names = names_zmm;
15216           break;
15217         default:
15218           abort ();
15219         }
15220     }
15221   else if (bytemode == xmmq_mode
15222            || bytemode == evex_half_bcst_xmmq_mode)
15223     {
15224       switch (vex.length)
15225         {
15226         case 128:
15227         case 256:
15228           names = names_xmm;
15229           break;
15230         case 512:
15231           names = names_ymm;
15232           break;
15233         default:
15234           abort ();
15235         }
15236     }
15237   else if (bytemode == ymm_mode)
15238     names = names_ymm;
15239   else
15240     names = names_xmm;
15241   oappend (names[reg]);
15242 }
15243
15244 static void
15245 OP_EM (int bytemode, int sizeflag)
15246 {
15247   int reg;
15248   const char **names;
15249
15250   if (modrm.mod != 3)
15251     {
15252       if (intel_syntax
15253           && (bytemode == v_mode || bytemode == v_swap_mode))
15254         {
15255           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15256           used_prefixes |= (prefixes & PREFIX_DATA);
15257         }
15258       OP_E (bytemode, sizeflag);
15259       return;
15260     }
15261
15262   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15263     swap_operand ();
15264
15265   /* Skip mod/rm byte.  */
15266   MODRM_CHECK;
15267   codep++;
15268   used_prefixes |= (prefixes & PREFIX_DATA);
15269   reg = modrm.rm;
15270   if (prefixes & PREFIX_DATA)
15271     {
15272       names = names_xmm;
15273       USED_REX (REX_B);
15274       if (rex & REX_B)
15275         reg += 8;
15276     }
15277   else
15278     names = names_mm;
15279   oappend (names[reg]);
15280 }
15281
15282 /* cvt* are the only instructions in sse2 which have
15283    both SSE and MMX operands and also have 0x66 prefix
15284    in their opcode. 0x66 was originally used to differentiate
15285    between SSE and MMX instruction(operands). So we have to handle the
15286    cvt* separately using OP_EMC and OP_MXC */
15287 static void
15288 OP_EMC (int bytemode, int sizeflag)
15289 {
15290   if (modrm.mod != 3)
15291     {
15292       if (intel_syntax && bytemode == v_mode)
15293         {
15294           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15295           used_prefixes |= (prefixes & PREFIX_DATA);
15296         }
15297       OP_E (bytemode, sizeflag);
15298       return;
15299     }
15300
15301   /* Skip mod/rm byte.  */
15302   MODRM_CHECK;
15303   codep++;
15304   used_prefixes |= (prefixes & PREFIX_DATA);
15305   oappend (names_mm[modrm.rm]);
15306 }
15307
15308 static void
15309 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15310 {
15311   used_prefixes |= (prefixes & PREFIX_DATA);
15312   oappend (names_mm[modrm.reg]);
15313 }
15314
15315 static void
15316 OP_EX (int bytemode, int sizeflag)
15317 {
15318   int reg;
15319   const char **names;
15320
15321   /* Skip mod/rm byte.  */
15322   MODRM_CHECK;
15323   codep++;
15324
15325   if (modrm.mod != 3)
15326     {
15327       OP_E_memory (bytemode, sizeflag);
15328       return;
15329     }
15330
15331   reg = modrm.rm;
15332   USED_REX (REX_B);
15333   if (rex & REX_B)
15334     reg += 8;
15335   if (vex.evex)
15336     {
15337       USED_REX (REX_X);
15338       if ((rex & REX_X))
15339         reg += 16;
15340     }
15341
15342   if ((sizeflag & SUFFIX_ALWAYS)
15343       && (bytemode == x_swap_mode
15344           || bytemode == d_swap_mode
15345           || bytemode == d_scalar_swap_mode
15346           || bytemode == q_swap_mode
15347           || bytemode == q_scalar_swap_mode))
15348     swap_operand ();
15349
15350   if (need_vex
15351       && bytemode != xmm_mode
15352       && bytemode != xmmdw_mode
15353       && bytemode != xmmqd_mode
15354       && bytemode != xmm_mb_mode
15355       && bytemode != xmm_mw_mode
15356       && bytemode != xmm_md_mode
15357       && bytemode != xmm_mq_mode
15358       && bytemode != xmm_mdq_mode
15359       && bytemode != xmmq_mode
15360       && bytemode != evex_half_bcst_xmmq_mode
15361       && bytemode != ymm_mode
15362       && bytemode != d_scalar_mode
15363       && bytemode != d_scalar_swap_mode
15364       && bytemode != q_scalar_mode
15365       && bytemode != q_scalar_swap_mode
15366       && bytemode != vex_scalar_w_dq_mode)
15367     {
15368       switch (vex.length)
15369         {
15370         case 128:
15371           names = names_xmm;
15372           break;
15373         case 256:
15374           names = names_ymm;
15375           break;
15376         case 512:
15377           names = names_zmm;
15378           break;
15379         default:
15380           abort ();
15381         }
15382     }
15383   else if (bytemode == xmmq_mode
15384            || bytemode == evex_half_bcst_xmmq_mode)
15385     {
15386       switch (vex.length)
15387         {
15388         case 128:
15389         case 256:
15390           names = names_xmm;
15391           break;
15392         case 512:
15393           names = names_ymm;
15394           break;
15395         default:
15396           abort ();
15397         }
15398     }
15399   else if (bytemode == ymm_mode)
15400     names = names_ymm;
15401   else
15402     names = names_xmm;
15403   oappend (names[reg]);
15404 }
15405
15406 static void
15407 OP_MS (int bytemode, int sizeflag)
15408 {
15409   if (modrm.mod == 3)
15410     OP_EM (bytemode, sizeflag);
15411   else
15412     BadOp ();
15413 }
15414
15415 static void
15416 OP_XS (int bytemode, int sizeflag)
15417 {
15418   if (modrm.mod == 3)
15419     OP_EX (bytemode, sizeflag);
15420   else
15421     BadOp ();
15422 }
15423
15424 static void
15425 OP_M (int bytemode, int sizeflag)
15426 {
15427   if (modrm.mod == 3)
15428     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15429     BadOp ();
15430   else
15431     OP_E (bytemode, sizeflag);
15432 }
15433
15434 static void
15435 OP_0f07 (int bytemode, int sizeflag)
15436 {
15437   if (modrm.mod != 3 || modrm.rm != 0)
15438     BadOp ();
15439   else
15440     OP_E (bytemode, sizeflag);
15441 }
15442
15443 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15444    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15445
15446 static void
15447 NOP_Fixup1 (int bytemode, int sizeflag)
15448 {
15449   if ((prefixes & PREFIX_DATA) != 0
15450       || (rex != 0
15451           && rex != 0x48
15452           && address_mode == mode_64bit))
15453     OP_REG (bytemode, sizeflag);
15454   else
15455     strcpy (obuf, "nop");
15456 }
15457
15458 static void
15459 NOP_Fixup2 (int bytemode, int sizeflag)
15460 {
15461   if ((prefixes & PREFIX_DATA) != 0
15462       || (rex != 0
15463           && rex != 0x48
15464           && address_mode == mode_64bit))
15465     OP_IMREG (bytemode, sizeflag);
15466 }
15467
15468 static const char *const Suffix3DNow[] = {
15469 /* 00 */        NULL,           NULL,           NULL,           NULL,
15470 /* 04 */        NULL,           NULL,           NULL,           NULL,
15471 /* 08 */        NULL,           NULL,           NULL,           NULL,
15472 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15473 /* 10 */        NULL,           NULL,           NULL,           NULL,
15474 /* 14 */        NULL,           NULL,           NULL,           NULL,
15475 /* 18 */        NULL,           NULL,           NULL,           NULL,
15476 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15477 /* 20 */        NULL,           NULL,           NULL,           NULL,
15478 /* 24 */        NULL,           NULL,           NULL,           NULL,
15479 /* 28 */        NULL,           NULL,           NULL,           NULL,
15480 /* 2C */        NULL,           NULL,           NULL,           NULL,
15481 /* 30 */        NULL,           NULL,           NULL,           NULL,
15482 /* 34 */        NULL,           NULL,           NULL,           NULL,
15483 /* 38 */        NULL,           NULL,           NULL,           NULL,
15484 /* 3C */        NULL,           NULL,           NULL,           NULL,
15485 /* 40 */        NULL,           NULL,           NULL,           NULL,
15486 /* 44 */        NULL,           NULL,           NULL,           NULL,
15487 /* 48 */        NULL,           NULL,           NULL,           NULL,
15488 /* 4C */        NULL,           NULL,           NULL,           NULL,
15489 /* 50 */        NULL,           NULL,           NULL,           NULL,
15490 /* 54 */        NULL,           NULL,           NULL,           NULL,
15491 /* 58 */        NULL,           NULL,           NULL,           NULL,
15492 /* 5C */        NULL,           NULL,           NULL,           NULL,
15493 /* 60 */        NULL,           NULL,           NULL,           NULL,
15494 /* 64 */        NULL,           NULL,           NULL,           NULL,
15495 /* 68 */        NULL,           NULL,           NULL,           NULL,
15496 /* 6C */        NULL,           NULL,           NULL,           NULL,
15497 /* 70 */        NULL,           NULL,           NULL,           NULL,
15498 /* 74 */        NULL,           NULL,           NULL,           NULL,
15499 /* 78 */        NULL,           NULL,           NULL,           NULL,
15500 /* 7C */        NULL,           NULL,           NULL,           NULL,
15501 /* 80 */        NULL,           NULL,           NULL,           NULL,
15502 /* 84 */        NULL,           NULL,           NULL,           NULL,
15503 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15504 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15505 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15506 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15507 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15508 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15509 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15510 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15511 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15512 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15513 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15514 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15515 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15516 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15517 /* C0 */        NULL,           NULL,           NULL,           NULL,
15518 /* C4 */        NULL,           NULL,           NULL,           NULL,
15519 /* C8 */        NULL,           NULL,           NULL,           NULL,
15520 /* CC */        NULL,           NULL,           NULL,           NULL,
15521 /* D0 */        NULL,           NULL,           NULL,           NULL,
15522 /* D4 */        NULL,           NULL,           NULL,           NULL,
15523 /* D8 */        NULL,           NULL,           NULL,           NULL,
15524 /* DC */        NULL,           NULL,           NULL,           NULL,
15525 /* E0 */        NULL,           NULL,           NULL,           NULL,
15526 /* E4 */        NULL,           NULL,           NULL,           NULL,
15527 /* E8 */        NULL,           NULL,           NULL,           NULL,
15528 /* EC */        NULL,           NULL,           NULL,           NULL,
15529 /* F0 */        NULL,           NULL,           NULL,           NULL,
15530 /* F4 */        NULL,           NULL,           NULL,           NULL,
15531 /* F8 */        NULL,           NULL,           NULL,           NULL,
15532 /* FC */        NULL,           NULL,           NULL,           NULL,
15533 };
15534
15535 static void
15536 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15537 {
15538   const char *mnemonic;
15539
15540   FETCH_DATA (the_info, codep + 1);
15541   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15542      place where an 8-bit immediate would normally go.  ie. the last
15543      byte of the instruction.  */
15544   obufp = mnemonicendp;
15545   mnemonic = Suffix3DNow[*codep++ & 0xff];
15546   if (mnemonic)
15547     oappend (mnemonic);
15548   else
15549     {
15550       /* Since a variable sized modrm/sib chunk is between the start
15551          of the opcode (0x0f0f) and the opcode suffix, we need to do
15552          all the modrm processing first, and don't know until now that
15553          we have a bad opcode.  This necessitates some cleaning up.  */
15554       op_out[0][0] = '\0';
15555       op_out[1][0] = '\0';
15556       BadOp ();
15557     }
15558   mnemonicendp = obufp;
15559 }
15560
15561 static struct op simd_cmp_op[] =
15562 {
15563   { STRING_COMMA_LEN ("eq") },
15564   { STRING_COMMA_LEN ("lt") },
15565   { STRING_COMMA_LEN ("le") },
15566   { STRING_COMMA_LEN ("unord") },
15567   { STRING_COMMA_LEN ("neq") },
15568   { STRING_COMMA_LEN ("nlt") },
15569   { STRING_COMMA_LEN ("nle") },
15570   { STRING_COMMA_LEN ("ord") }
15571 };
15572
15573 static void
15574 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15575 {
15576   unsigned int cmp_type;
15577
15578   FETCH_DATA (the_info, codep + 1);
15579   cmp_type = *codep++ & 0xff;
15580   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15581     {
15582       char suffix [3];
15583       char *p = mnemonicendp - 2;
15584       suffix[0] = p[0];
15585       suffix[1] = p[1];
15586       suffix[2] = '\0';
15587       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15588       mnemonicendp += simd_cmp_op[cmp_type].len;
15589     }
15590   else
15591     {
15592       /* We have a reserved extension byte.  Output it directly.  */
15593       scratchbuf[0] = '$';
15594       print_operand_value (scratchbuf + 1, 1, cmp_type);
15595       oappend_maybe_intel (scratchbuf);
15596       scratchbuf[0] = '\0';
15597     }
15598 }
15599
15600 static void
15601 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15602           int sizeflag ATTRIBUTE_UNUSED)
15603 {
15604   /* mwaitx %eax,%ecx,%ebx */
15605   if (!intel_syntax)
15606     {
15607       const char **names = (address_mode == mode_64bit
15608                             ? names64 : names32);
15609       strcpy (op_out[0], names[0]);
15610       strcpy (op_out[1], names[1]);
15611       strcpy (op_out[2], names[3]);
15612       two_source_ops = 1;
15613     }
15614   /* Skip mod/rm byte.  */
15615   MODRM_CHECK;
15616   codep++;
15617 }
15618
15619 static void
15620 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15621           int sizeflag ATTRIBUTE_UNUSED)
15622 {
15623   /* mwait %eax,%ecx  */
15624   if (!intel_syntax)
15625     {
15626       const char **names = (address_mode == mode_64bit
15627                             ? names64 : names32);
15628       strcpy (op_out[0], names[0]);
15629       strcpy (op_out[1], names[1]);
15630       two_source_ops = 1;
15631     }
15632   /* Skip mod/rm byte.  */
15633   MODRM_CHECK;
15634   codep++;
15635 }
15636
15637 static void
15638 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15639             int sizeflag ATTRIBUTE_UNUSED)
15640 {
15641   /* monitor %eax,%ecx,%edx"  */
15642   if (!intel_syntax)
15643     {
15644       const char **op1_names;
15645       const char **names = (address_mode == mode_64bit
15646                             ? names64 : names32);
15647
15648       if (!(prefixes & PREFIX_ADDR))
15649         op1_names = (address_mode == mode_16bit
15650                      ? names16 : names);
15651       else
15652         {
15653           /* Remove "addr16/addr32".  */
15654           all_prefixes[last_addr_prefix] = 0;
15655           op1_names = (address_mode != mode_32bit
15656                        ? names32 : names16);
15657           used_prefixes |= PREFIX_ADDR;
15658         }
15659       strcpy (op_out[0], op1_names[0]);
15660       strcpy (op_out[1], names[1]);
15661       strcpy (op_out[2], names[2]);
15662       two_source_ops = 1;
15663     }
15664   /* Skip mod/rm byte.  */
15665   MODRM_CHECK;
15666   codep++;
15667 }
15668
15669 static void
15670 BadOp (void)
15671 {
15672   /* Throw away prefixes and 1st. opcode byte.  */
15673   codep = insn_codep + 1;
15674   oappend ("(bad)");
15675 }
15676
15677 static void
15678 REP_Fixup (int bytemode, int sizeflag)
15679 {
15680   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15681      lods and stos.  */
15682   if (prefixes & PREFIX_REPZ)
15683     all_prefixes[last_repz_prefix] = REP_PREFIX;
15684
15685   switch (bytemode)
15686     {
15687     case al_reg:
15688     case eAX_reg:
15689     case indir_dx_reg:
15690       OP_IMREG (bytemode, sizeflag);
15691       break;
15692     case eDI_reg:
15693       OP_ESreg (bytemode, sizeflag);
15694       break;
15695     case eSI_reg:
15696       OP_DSreg (bytemode, sizeflag);
15697       break;
15698     default:
15699       abort ();
15700       break;
15701     }
15702 }
15703
15704 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15705    "bnd".  */
15706
15707 static void
15708 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15709 {
15710   if (prefixes & PREFIX_REPNZ)
15711     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15712 }
15713
15714 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15715    "notrack".  */
15716
15717 static void
15718 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15719                int sizeflag ATTRIBUTE_UNUSED)
15720 {
15721   if (active_seg_prefix == PREFIX_DS
15722       && (address_mode != mode_64bit || last_data_prefix < 0))
15723     {
15724       /* NOTRACK prefix is only valid on indirect branch instructions.
15725          NB: DATA prefix is unsupported for Intel64.  */
15726       active_seg_prefix = 0;
15727       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15728     }
15729 }
15730
15731 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15732    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15733  */
15734
15735 static void
15736 HLE_Fixup1 (int bytemode, int sizeflag)
15737 {
15738   if (modrm.mod != 3
15739       && (prefixes & PREFIX_LOCK) != 0)
15740     {
15741       if (prefixes & PREFIX_REPZ)
15742         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15743       if (prefixes & PREFIX_REPNZ)
15744         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15745     }
15746
15747   OP_E (bytemode, sizeflag);
15748 }
15749
15750 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15751    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15752  */
15753
15754 static void
15755 HLE_Fixup2 (int bytemode, int sizeflag)
15756 {
15757   if (modrm.mod != 3)
15758     {
15759       if (prefixes & PREFIX_REPZ)
15760         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15761       if (prefixes & PREFIX_REPNZ)
15762         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15763     }
15764
15765   OP_E (bytemode, sizeflag);
15766 }
15767
15768 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15769    "xrelease" for memory operand.  No check for LOCK prefix.   */
15770
15771 static void
15772 HLE_Fixup3 (int bytemode, int sizeflag)
15773 {
15774   if (modrm.mod != 3
15775       && last_repz_prefix > last_repnz_prefix
15776       && (prefixes & PREFIX_REPZ) != 0)
15777     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15778
15779   OP_E (bytemode, sizeflag);
15780 }
15781
15782 static void
15783 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15784 {
15785   USED_REX (REX_W);
15786   if (rex & REX_W)
15787     {
15788       /* Change cmpxchg8b to cmpxchg16b.  */
15789       char *p = mnemonicendp - 2;
15790       mnemonicendp = stpcpy (p, "16b");
15791       bytemode = o_mode;
15792     }
15793   else if ((prefixes & PREFIX_LOCK) != 0)
15794     {
15795       if (prefixes & PREFIX_REPZ)
15796         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15797       if (prefixes & PREFIX_REPNZ)
15798         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15799     }
15800
15801   OP_M (bytemode, sizeflag);
15802 }
15803
15804 static void
15805 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15806 {
15807   const char **names;
15808
15809   if (need_vex)
15810     {
15811       switch (vex.length)
15812         {
15813         case 128:
15814           names = names_xmm;
15815           break;
15816         case 256:
15817           names = names_ymm;
15818           break;
15819         default:
15820           abort ();
15821         }
15822     }
15823   else
15824     names = names_xmm;
15825   oappend (names[reg]);
15826 }
15827
15828 static void
15829 CRC32_Fixup (int bytemode, int sizeflag)
15830 {
15831   /* Add proper suffix to "crc32".  */
15832   char *p = mnemonicendp;
15833
15834   switch (bytemode)
15835     {
15836     case b_mode:
15837       if (intel_syntax)
15838         goto skip;
15839
15840       *p++ = 'b';
15841       break;
15842     case v_mode:
15843       if (intel_syntax)
15844         goto skip;
15845
15846       USED_REX (REX_W);
15847       if (rex & REX_W)
15848         *p++ = 'q';
15849       else
15850         {
15851           if (sizeflag & DFLAG)
15852             *p++ = 'l';
15853           else
15854             *p++ = 'w';
15855           used_prefixes |= (prefixes & PREFIX_DATA);
15856         }
15857       break;
15858     default:
15859       oappend (INTERNAL_DISASSEMBLER_ERROR);
15860       break;
15861     }
15862   mnemonicendp = p;
15863   *p = '\0';
15864
15865 skip:
15866   if (modrm.mod == 3)
15867     {
15868       int add;
15869
15870       /* Skip mod/rm byte.  */
15871       MODRM_CHECK;
15872       codep++;
15873
15874       USED_REX (REX_B);
15875       add = (rex & REX_B) ? 8 : 0;
15876       if (bytemode == b_mode)
15877         {
15878           USED_REX (0);
15879           if (rex)
15880             oappend (names8rex[modrm.rm + add]);
15881           else
15882             oappend (names8[modrm.rm + add]);
15883         }
15884       else
15885         {
15886           USED_REX (REX_W);
15887           if (rex & REX_W)
15888             oappend (names64[modrm.rm + add]);
15889           else if ((prefixes & PREFIX_DATA))
15890             oappend (names16[modrm.rm + add]);
15891           else
15892             oappend (names32[modrm.rm + add]);
15893         }
15894     }
15895   else
15896     OP_E (bytemode, sizeflag);
15897 }
15898
15899 static void
15900 FXSAVE_Fixup (int bytemode, int sizeflag)
15901 {
15902   /* Add proper suffix to "fxsave" and "fxrstor".  */
15903   USED_REX (REX_W);
15904   if (rex & REX_W)
15905     {
15906       char *p = mnemonicendp;
15907       *p++ = '6';
15908       *p++ = '4';
15909       *p = '\0';
15910       mnemonicendp = p;
15911     }
15912   OP_M (bytemode, sizeflag);
15913 }
15914
15915 static void
15916 PCMPESTR_Fixup (int bytemode, int sizeflag)
15917 {
15918   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15919   if (!intel_syntax)
15920     {
15921       char *p = mnemonicendp;
15922
15923       USED_REX (REX_W);
15924       if (rex & REX_W)
15925         *p++ = 'q';
15926       else if (sizeflag & SUFFIX_ALWAYS)
15927         *p++ = 'l';
15928
15929       *p = '\0';
15930       mnemonicendp = p;
15931     }
15932
15933   OP_EX (bytemode, sizeflag);
15934 }
15935
15936 /* Display the destination register operand for instructions with
15937    VEX. */
15938
15939 static void
15940 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15941 {
15942   int reg;
15943   const char **names;
15944
15945   if (!need_vex)
15946     abort ();
15947
15948   if (!need_vex_reg)
15949     return;
15950
15951   reg = vex.register_specifier;
15952   vex.register_specifier = 0;
15953   if (address_mode != mode_64bit)
15954     reg &= 7;
15955   else if (vex.evex && !vex.v)
15956     reg += 16;
15957
15958   if (bytemode == vex_scalar_mode)
15959     {
15960       oappend (names_xmm[reg]);
15961       return;
15962     }
15963
15964   switch (vex.length)
15965     {
15966     case 128:
15967       switch (bytemode)
15968         {
15969         case vex_mode:
15970         case vex128_mode:
15971         case vex_vsib_q_w_dq_mode:
15972         case vex_vsib_q_w_d_mode:
15973           names = names_xmm;
15974           break;
15975         case dq_mode:
15976           if (rex & REX_W)
15977             names = names64;
15978           else
15979             names = names32;
15980           break;
15981         case mask_bd_mode:
15982         case mask_mode:
15983           if (reg > 0x7)
15984             {
15985               oappend ("(bad)");
15986               return;
15987             }
15988           names = names_mask;
15989           break;
15990         default:
15991           abort ();
15992           return;
15993         }
15994       break;
15995     case 256:
15996       switch (bytemode)
15997         {
15998         case vex_mode:
15999         case vex256_mode:
16000           names = names_ymm;
16001           break;
16002         case vex_vsib_q_w_dq_mode:
16003         case vex_vsib_q_w_d_mode:
16004           names = vex.w ? names_ymm : names_xmm;
16005           break;
16006         case mask_bd_mode:
16007         case mask_mode:
16008           if (reg > 0x7)
16009             {
16010               oappend ("(bad)");
16011               return;
16012             }
16013           names = names_mask;
16014           break;
16015         default:
16016           /* See PR binutils/20893 for a reproducer.  */
16017           oappend ("(bad)");
16018           return;
16019         }
16020       break;
16021     case 512:
16022       names = names_zmm;
16023       break;
16024     default:
16025       abort ();
16026       break;
16027     }
16028   oappend (names[reg]);
16029 }
16030
16031 /* Get the VEX immediate byte without moving codep.  */
16032
16033 static unsigned char
16034 get_vex_imm8 (int sizeflag, int opnum)
16035 {
16036   int bytes_before_imm = 0;
16037
16038   if (modrm.mod != 3)
16039     {
16040       /* There are SIB/displacement bytes.  */
16041       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16042         {
16043           /* 32/64 bit address mode */
16044           int base = modrm.rm;
16045
16046           /* Check SIB byte.  */
16047           if (base == 4)
16048             {
16049               FETCH_DATA (the_info, codep + 1);
16050               base = *codep & 7;
16051               /* When decoding the third source, don't increase
16052                  bytes_before_imm as this has already been incremented
16053                  by one in OP_E_memory while decoding the second
16054                  source operand.  */
16055               if (opnum == 0)
16056                 bytes_before_imm++;
16057             }
16058
16059           /* Don't increase bytes_before_imm when decoding the third source,
16060              it has already been incremented by OP_E_memory while decoding
16061              the second source operand.  */
16062           if (opnum == 0)
16063             {
16064               switch (modrm.mod)
16065                 {
16066                   case 0:
16067                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16068                        SIB == 5, there is a 4 byte displacement.  */
16069                     if (base != 5)
16070                       /* No displacement. */
16071                       break;
16072                     /* Fall through.  */
16073                   case 2:
16074                     /* 4 byte displacement.  */
16075                     bytes_before_imm += 4;
16076                     break;
16077                   case 1:
16078                     /* 1 byte displacement.  */
16079                     bytes_before_imm++;
16080                     break;
16081                 }
16082             }
16083         }
16084       else
16085         {
16086           /* 16 bit address mode */
16087           /* Don't increase bytes_before_imm when decoding the third source,
16088              it has already been incremented by OP_E_memory while decoding
16089              the second source operand.  */
16090           if (opnum == 0)
16091             {
16092               switch (modrm.mod)
16093                 {
16094                 case 0:
16095                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16096                   if (modrm.rm != 6)
16097                     /* No displacement. */
16098                     break;
16099                   /* Fall through.  */
16100                 case 2:
16101                   /* 2 byte displacement.  */
16102                   bytes_before_imm += 2;
16103                   break;
16104                 case 1:
16105                   /* 1 byte displacement: when decoding the third source,
16106                      don't increase bytes_before_imm as this has already
16107                      been incremented by one in OP_E_memory while decoding
16108                      the second source operand.  */
16109                   if (opnum == 0)
16110                     bytes_before_imm++;
16111
16112                   break;
16113                 }
16114             }
16115         }
16116     }
16117
16118   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16119   return codep [bytes_before_imm];
16120 }
16121
16122 static void
16123 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16124 {
16125   const char **names;
16126
16127   if (reg == -1 && modrm.mod != 3)
16128     {
16129       OP_E_memory (bytemode, sizeflag);
16130       return;
16131     }
16132   else
16133     {
16134       if (reg == -1)
16135         {
16136           reg = modrm.rm;
16137           USED_REX (REX_B);
16138           if (rex & REX_B)
16139             reg += 8;
16140         }
16141       if (address_mode != mode_64bit)
16142         reg &= 7;
16143     }
16144
16145   switch (vex.length)
16146     {
16147     case 128:
16148       names = names_xmm;
16149       break;
16150     case 256:
16151       names = names_ymm;
16152       break;
16153     default:
16154       abort ();
16155     }
16156   oappend (names[reg]);
16157 }
16158
16159 static void
16160 OP_EX_VexImmW (int bytemode, int sizeflag)
16161 {
16162   int reg = -1;
16163   static unsigned char vex_imm8;
16164
16165   if (vex_w_done == 0)
16166     {
16167       vex_w_done = 1;
16168
16169       /* Skip mod/rm byte.  */
16170       MODRM_CHECK;
16171       codep++;
16172
16173       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16174
16175       if (vex.w)
16176           reg = vex_imm8 >> 4;
16177
16178       OP_EX_VexReg (bytemode, sizeflag, reg);
16179     }
16180   else if (vex_w_done == 1)
16181     {
16182       vex_w_done = 2;
16183
16184       if (!vex.w)
16185           reg = vex_imm8 >> 4;
16186
16187       OP_EX_VexReg (bytemode, sizeflag, reg);
16188     }
16189   else
16190     {
16191       /* Output the imm8 directly.  */
16192       scratchbuf[0] = '$';
16193       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16194       oappend_maybe_intel (scratchbuf);
16195       scratchbuf[0] = '\0';
16196       codep++;
16197     }
16198 }
16199
16200 static void
16201 OP_Vex_2src (int bytemode, int sizeflag)
16202 {
16203   if (modrm.mod == 3)
16204     {
16205       int reg = modrm.rm;
16206       USED_REX (REX_B);
16207       if (rex & REX_B)
16208         reg += 8;
16209       oappend (names_xmm[reg]);
16210     }
16211   else
16212     {
16213       if (intel_syntax
16214           && (bytemode == v_mode || bytemode == v_swap_mode))
16215         {
16216           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16217           used_prefixes |= (prefixes & PREFIX_DATA);
16218         }
16219       OP_E (bytemode, sizeflag);
16220     }
16221 }
16222
16223 static void
16224 OP_Vex_2src_1 (int bytemode, int sizeflag)
16225 {
16226   if (modrm.mod == 3)
16227     {
16228       /* Skip mod/rm byte.   */
16229       MODRM_CHECK;
16230       codep++;
16231     }
16232
16233   if (vex.w)
16234     {
16235       unsigned int reg = vex.register_specifier;
16236       vex.register_specifier = 0;
16237
16238       if (address_mode != mode_64bit)
16239         reg &= 7;
16240       oappend (names_xmm[reg]);
16241     }
16242   else
16243     OP_Vex_2src (bytemode, sizeflag);
16244 }
16245
16246 static void
16247 OP_Vex_2src_2 (int bytemode, int sizeflag)
16248 {
16249   if (vex.w)
16250     OP_Vex_2src (bytemode, sizeflag);
16251   else
16252     {
16253       unsigned int reg = vex.register_specifier;
16254       vex.register_specifier = 0;
16255
16256       if (address_mode != mode_64bit)
16257         reg &= 7;
16258       oappend (names_xmm[reg]);
16259     }
16260 }
16261
16262 static void
16263 OP_EX_VexW (int bytemode, int sizeflag)
16264 {
16265   int reg = -1;
16266
16267   if (!vex_w_done)
16268     {
16269       /* Skip mod/rm byte.  */
16270       MODRM_CHECK;
16271       codep++;
16272
16273       if (vex.w)
16274         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16275     }
16276   else
16277     {
16278       if (!vex.w)
16279         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16280     }
16281
16282   OP_EX_VexReg (bytemode, sizeflag, reg);
16283
16284   if (vex_w_done)
16285     codep++;
16286   vex_w_done = 1;
16287 }
16288
16289 static void
16290 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16291 {
16292   int reg;
16293   const char **names;
16294
16295   FETCH_DATA (the_info, codep + 1);
16296   reg = *codep++;
16297
16298   if (bytemode != x_mode)
16299     abort ();
16300
16301   reg >>= 4;
16302   if (address_mode != mode_64bit)
16303     reg &= 7;
16304
16305   switch (vex.length)
16306     {
16307     case 128:
16308       names = names_xmm;
16309       break;
16310     case 256:
16311       names = names_ymm;
16312       break;
16313     default:
16314       abort ();
16315     }
16316   oappend (names[reg]);
16317 }
16318
16319 static void
16320 OP_XMM_VexW (int bytemode, int sizeflag)
16321 {
16322   /* Turn off the REX.W bit since it is used for swapping operands
16323      now.  */
16324   rex &= ~REX_W;
16325   OP_XMM (bytemode, sizeflag);
16326 }
16327
16328 static void
16329 OP_EX_Vex (int bytemode, int sizeflag)
16330 {
16331   if (modrm.mod != 3)
16332     need_vex_reg = 0;
16333   OP_EX (bytemode, sizeflag);
16334 }
16335
16336 static void
16337 OP_XMM_Vex (int bytemode, int sizeflag)
16338 {
16339   if (modrm.mod != 3)
16340     need_vex_reg = 0;
16341   OP_XMM (bytemode, sizeflag);
16342 }
16343
16344 static struct op vex_cmp_op[] =
16345 {
16346   { STRING_COMMA_LEN ("eq") },
16347   { STRING_COMMA_LEN ("lt") },
16348   { STRING_COMMA_LEN ("le") },
16349   { STRING_COMMA_LEN ("unord") },
16350   { STRING_COMMA_LEN ("neq") },
16351   { STRING_COMMA_LEN ("nlt") },
16352   { STRING_COMMA_LEN ("nle") },
16353   { STRING_COMMA_LEN ("ord") },
16354   { STRING_COMMA_LEN ("eq_uq") },
16355   { STRING_COMMA_LEN ("nge") },
16356   { STRING_COMMA_LEN ("ngt") },
16357   { STRING_COMMA_LEN ("false") },
16358   { STRING_COMMA_LEN ("neq_oq") },
16359   { STRING_COMMA_LEN ("ge") },
16360   { STRING_COMMA_LEN ("gt") },
16361   { STRING_COMMA_LEN ("true") },
16362   { STRING_COMMA_LEN ("eq_os") },
16363   { STRING_COMMA_LEN ("lt_oq") },
16364   { STRING_COMMA_LEN ("le_oq") },
16365   { STRING_COMMA_LEN ("unord_s") },
16366   { STRING_COMMA_LEN ("neq_us") },
16367   { STRING_COMMA_LEN ("nlt_uq") },
16368   { STRING_COMMA_LEN ("nle_uq") },
16369   { STRING_COMMA_LEN ("ord_s") },
16370   { STRING_COMMA_LEN ("eq_us") },
16371   { STRING_COMMA_LEN ("nge_uq") },
16372   { STRING_COMMA_LEN ("ngt_uq") },
16373   { STRING_COMMA_LEN ("false_os") },
16374   { STRING_COMMA_LEN ("neq_os") },
16375   { STRING_COMMA_LEN ("ge_oq") },
16376   { STRING_COMMA_LEN ("gt_oq") },
16377   { STRING_COMMA_LEN ("true_us") },
16378 };
16379
16380 static void
16381 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16382 {
16383   unsigned int cmp_type;
16384
16385   FETCH_DATA (the_info, codep + 1);
16386   cmp_type = *codep++ & 0xff;
16387   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16388     {
16389       char suffix [3];
16390       char *p = mnemonicendp - 2;
16391       suffix[0] = p[0];
16392       suffix[1] = p[1];
16393       suffix[2] = '\0';
16394       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16395       mnemonicendp += vex_cmp_op[cmp_type].len;
16396     }
16397   else
16398     {
16399       /* We have a reserved extension byte.  Output it directly.  */
16400       scratchbuf[0] = '$';
16401       print_operand_value (scratchbuf + 1, 1, cmp_type);
16402       oappend_maybe_intel (scratchbuf);
16403       scratchbuf[0] = '\0';
16404     }
16405 }
16406
16407 static void
16408 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16409              int sizeflag ATTRIBUTE_UNUSED)
16410 {
16411   unsigned int cmp_type;
16412
16413   if (!vex.evex)
16414     abort ();
16415
16416   FETCH_DATA (the_info, codep + 1);
16417   cmp_type = *codep++ & 0xff;
16418   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16419      If it's the case, print suffix, otherwise - print the immediate.  */
16420   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16421       && cmp_type != 3
16422       && cmp_type != 7)
16423     {
16424       char suffix [3];
16425       char *p = mnemonicendp - 2;
16426
16427       /* vpcmp* can have both one- and two-lettered suffix.  */
16428       if (p[0] == 'p')
16429         {
16430           p++;
16431           suffix[0] = p[0];
16432           suffix[1] = '\0';
16433         }
16434       else
16435         {
16436           suffix[0] = p[0];
16437           suffix[1] = p[1];
16438           suffix[2] = '\0';
16439         }
16440
16441       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16442       mnemonicendp += simd_cmp_op[cmp_type].len;
16443     }
16444   else
16445     {
16446       /* We have a reserved extension byte.  Output it directly.  */
16447       scratchbuf[0] = '$';
16448       print_operand_value (scratchbuf + 1, 1, cmp_type);
16449       oappend_maybe_intel (scratchbuf);
16450       scratchbuf[0] = '\0';
16451     }
16452 }
16453
16454 static const struct op xop_cmp_op[] =
16455 {
16456   { STRING_COMMA_LEN ("lt") },
16457   { STRING_COMMA_LEN ("le") },
16458   { STRING_COMMA_LEN ("gt") },
16459   { STRING_COMMA_LEN ("ge") },
16460   { STRING_COMMA_LEN ("eq") },
16461   { STRING_COMMA_LEN ("neq") },
16462   { STRING_COMMA_LEN ("false") },
16463   { STRING_COMMA_LEN ("true") }
16464 };
16465
16466 static void
16467 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16468              int sizeflag ATTRIBUTE_UNUSED)
16469 {
16470   unsigned int cmp_type;
16471
16472   FETCH_DATA (the_info, codep + 1);
16473   cmp_type = *codep++ & 0xff;
16474   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16475     {
16476       char suffix[3];
16477       char *p = mnemonicendp - 2;
16478
16479       /* vpcom* can have both one- and two-lettered suffix.  */
16480       if (p[0] == 'm')
16481         {
16482           p++;
16483           suffix[0] = p[0];
16484           suffix[1] = '\0';
16485         }
16486       else
16487         {
16488           suffix[0] = p[0];
16489           suffix[1] = p[1];
16490           suffix[2] = '\0';
16491         }
16492
16493       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16494       mnemonicendp += xop_cmp_op[cmp_type].len;
16495     }
16496   else
16497     {
16498       /* We have a reserved extension byte.  Output it directly.  */
16499       scratchbuf[0] = '$';
16500       print_operand_value (scratchbuf + 1, 1, cmp_type);
16501       oappend_maybe_intel (scratchbuf);
16502       scratchbuf[0] = '\0';
16503     }
16504 }
16505
16506 static const struct op pclmul_op[] =
16507 {
16508   { STRING_COMMA_LEN ("lql") },
16509   { STRING_COMMA_LEN ("hql") },
16510   { STRING_COMMA_LEN ("lqh") },
16511   { STRING_COMMA_LEN ("hqh") }
16512 };
16513
16514 static void
16515 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16516               int sizeflag ATTRIBUTE_UNUSED)
16517 {
16518   unsigned int pclmul_type;
16519
16520   FETCH_DATA (the_info, codep + 1);
16521   pclmul_type = *codep++ & 0xff;
16522   switch (pclmul_type)
16523     {
16524     case 0x10:
16525       pclmul_type = 2;
16526       break;
16527     case 0x11:
16528       pclmul_type = 3;
16529       break;
16530     default:
16531       break;
16532     }
16533   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16534     {
16535       char suffix [4];
16536       char *p = mnemonicendp - 3;
16537       suffix[0] = p[0];
16538       suffix[1] = p[1];
16539       suffix[2] = p[2];
16540       suffix[3] = '\0';
16541       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16542       mnemonicendp += pclmul_op[pclmul_type].len;
16543     }
16544   else
16545     {
16546       /* We have a reserved extension byte.  Output it directly.  */
16547       scratchbuf[0] = '$';
16548       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16549       oappend_maybe_intel (scratchbuf);
16550       scratchbuf[0] = '\0';
16551     }
16552 }
16553
16554 static void
16555 MOVBE_Fixup (int bytemode, int sizeflag)
16556 {
16557   /* Add proper suffix to "movbe".  */
16558   char *p = mnemonicendp;
16559
16560   switch (bytemode)
16561     {
16562     case v_mode:
16563       if (intel_syntax)
16564         goto skip;
16565
16566       USED_REX (REX_W);
16567       if (sizeflag & SUFFIX_ALWAYS)
16568         {
16569           if (rex & REX_W)
16570             *p++ = 'q';
16571           else
16572             {
16573               if (sizeflag & DFLAG)
16574                 *p++ = 'l';
16575               else
16576                 *p++ = 'w';
16577               used_prefixes |= (prefixes & PREFIX_DATA);
16578             }
16579         }
16580       break;
16581     default:
16582       oappend (INTERNAL_DISASSEMBLER_ERROR);
16583       break;
16584     }
16585   mnemonicendp = p;
16586   *p = '\0';
16587
16588 skip:
16589   OP_M (bytemode, sizeflag);
16590 }
16591
16592 static void
16593 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16594 {
16595   int reg;
16596   const char **names;
16597
16598   /* Skip mod/rm byte.  */
16599   MODRM_CHECK;
16600   codep++;
16601
16602   if (rex & REX_W)
16603     names = names64;
16604   else
16605     names = names32;
16606
16607   reg = modrm.rm;
16608   USED_REX (REX_B);
16609   if (rex & REX_B)
16610     reg += 8;
16611
16612   oappend (names[reg]);
16613 }
16614
16615 static void
16616 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16617 {
16618   const char **names;
16619   unsigned int reg = vex.register_specifier;
16620   vex.register_specifier = 0;
16621
16622   if (rex & REX_W)
16623     names = names64;
16624   else
16625     names = names32;
16626
16627   if (address_mode != mode_64bit)
16628     reg &= 7;
16629   oappend (names[reg]);
16630 }
16631
16632 static void
16633 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16634 {
16635   if (!vex.evex
16636       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16637     abort ();
16638
16639   USED_REX (REX_R);
16640   if ((rex & REX_R) != 0 || !vex.r)
16641     {
16642       BadOp ();
16643       return;
16644     }
16645
16646   oappend (names_mask [modrm.reg]);
16647 }
16648
16649 static void
16650 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16651 {
16652   if (!vex.evex
16653       || (bytemode != evex_rounding_mode
16654           && bytemode != evex_rounding_64_mode
16655           && bytemode != evex_sae_mode))
16656     abort ();
16657   if (modrm.mod == 3 && vex.b)
16658     switch (bytemode)
16659       {
16660       case evex_rounding_64_mode:
16661         if (address_mode != mode_64bit)
16662           {
16663             oappend ("(bad)");
16664             break;
16665           }
16666         /* Fall through.  */
16667       case evex_rounding_mode:
16668         oappend (names_rounding[vex.ll]);
16669         break;
16670       case evex_sae_mode:
16671         oappend ("{sae}");
16672         break;
16673       default:
16674         break;
16675       }
16676 }