opcodes/ppc-dis.c

   1 /* ppc-dis.c -- Disassemble PowerPC instructions
   2    Copyright (C) 1994-2020 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "disassemble.h"
  25 #include "elf-bfd.h"
  26 #include "elf/ppc.h"
  27 #include "opintl.h"
  28 #include "opcode/ppc.h"
  29 #include "libiberty.h"
  30
  31 /* This file provides several disassembler functions, all of which use
  32    the disassembler interface defined in dis-asm.h.  Several functions
  33    are provided because this file handles disassembly for the PowerPC
  34    in both big and little endian mode and also for the POWER (RS/6000)
  35    chip.  */
  36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
  37                                ppc_cpu_t);
  38
  39 struct dis_private
  40 {
  41   /* Stash the result of parsing disassembler_options here.  */
  42   ppc_cpu_t dialect;
  43 };
  44
  45 #define POWERPC_DIALECT(INFO) \
  46   (((struct dis_private *) ((INFO)->private_data))->dialect)
  47
  48 struct ppc_mopt {
  49   /* Option string, without -m or -M prefix.  */
  50   const char *opt;
  51   /* CPU option flags.  */
  52   ppc_cpu_t cpu;
  53   /* Flags that should stay on, even when combined with another cpu
  54      option.  This should only be used for generic options like
  55      "-many" or "-maltivec" where it is reasonable to add some
  56      capability to another cpu selection.  The added flags are sticky
  57      so that, for example, "-many -me500" and "-me500 -many" result in
  58      the same assembler or disassembler behaviour.  Do not use
  59      "sticky" for specific cpus, as this will prevent that cpu's flags
  60      from overriding the defaults set in powerpc_init_dialect or a
  61      prior -m option.  */
  62   ppc_cpu_t sticky;
  63 };
  64
  65 struct ppc_mopt ppc_opts[] = {
  66   { "403",     PPC_OPCODE_PPC | PPC_OPCODE_403,
  67     0 },
  68   { "405",     PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
  69     0 },
  70   { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  71                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  72     0 },
  73   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  74                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  75     0 },
  76   { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476
  77                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
  78     0 },
  79   { "601",     PPC_OPCODE_PPC | PPC_OPCODE_601,
  80     0 },
  81   { "603",     PPC_OPCODE_PPC,
  82     0 },
  83   { "604",     PPC_OPCODE_PPC,
  84     0 },
  85   { "620",     PPC_OPCODE_PPC | PPC_OPCODE_64,
  86     0 },
  87   { "7400",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  88     0 },
  89   { "7410",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  90     0 },
  91   { "7450",    PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
  92     0 },
  93   { "7455",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  94     0 },
  95   { "750cl",   PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
  96     , 0 },
  97   { "gekko",   PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
  98     , 0 },
  99   { "broadway", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
 100     , 0 },
 101   { "821",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 102     0 },
 103   { "850",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 104     0 },
 105   { "860",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 106     0 },
 107   { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
 108                 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
 109                 | PPC_OPCODE_A2),
 110     0 },
 111   { "altivec", PPC_OPCODE_PPC,
 112     PPC_OPCODE_ALTIVEC },
 113   { "any",     PPC_OPCODE_PPC,
 114     PPC_OPCODE_ANY },
 115   { "booke",   PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 116     0 },
 117   { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 118     0 },
 119   { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 120                 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
 121     0 },
 122   { "com",     PPC_OPCODE_COMMON,
 123     0 },
 124   { "e200z4",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 125                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 126                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 127                 | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
 128                 | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),
 129     0 },
 130   { "e300",    PPC_OPCODE_PPC | PPC_OPCODE_E300,
 131     0 },
 132   { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 133                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 134                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 135                 | PPC_OPCODE_E500),
 136     0 },
 137   { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 138                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 139                 | PPC_OPCODE_E500MC),
 140     0 },
 141   { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 142                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 143                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
 144                 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 145     0 },
 146   { "e5500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 147                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 148                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 149                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 150     0 },
 151   { "e6500",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 152                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 153                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
 154                 | PPC_OPCODE_E6500 | PPC_OPCODE_TMR | PPC_OPCODE_POWER4
 155                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 156     0 },
 157   { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 158                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 159                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 160                 | PPC_OPCODE_E500),
 161     0 },
 162   { "efs",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 163     0 },
 164   { "efs2",    PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
 165     0 },
 166   { "power4",  PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 167     0 },
 168   { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 169                 | PPC_OPCODE_POWER5),
 170     0 },
 171   { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 172                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 173     0 },
 174   { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 175                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 176                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 177     0 },
 178   { "power8",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 179                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 180                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 181                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 182     0 },
 183   { "power9",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 184                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 185                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 186                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 187     0 },
 188   { "power10", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 189                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 190                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 191                 | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 192     0 },
 193   { "future",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 194                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 195                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 196                 | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 197     0 },
 198   { "ppc",     PPC_OPCODE_PPC,
 199     0 },
 200   { "ppc32",   PPC_OPCODE_PPC,
 201     0 },
 202   { "32",      PPC_OPCODE_PPC,
 203     0 },
 204   { "ppc64",   PPC_OPCODE_PPC | PPC_OPCODE_64,
 205     0 },
 206   { "64",      PPC_OPCODE_PPC | PPC_OPCODE_64,
 207     0 },
 208   { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
 209     0 },
 210   { "ppcps",   PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
 211     0 },
 212   { "pwr",     PPC_OPCODE_POWER,
 213     0 },
 214   { "pwr2",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 215     0 },
 216   { "pwr4",    PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 217     0 },
 218   { "pwr5",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 219                 | PPC_OPCODE_POWER5),
 220     0 },
 221   { "pwr5x",   (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 222                 | PPC_OPCODE_POWER5),
 223     0 },
 224   { "pwr6",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 225                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 226     0 },
 227   { "pwr7",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 228                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 229                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 230     0 },
 231   { "pwr8",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 232                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 233                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 234                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 235     0 },
 236   { "pwr9",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 237                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 238                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 239                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 240     0 },
 241   { "pwrx",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 242     0 },
 243   { "raw",     PPC_OPCODE_PPC,
 244     PPC_OPCODE_RAW },
 245   { "spe",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 246     PPC_OPCODE_SPE },
 247   { "spe2",     PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE,
 248     PPC_OPCODE_SPE2 },
 249   { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
 250                 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
 251     0 },
 252   { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 253                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 254                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 255                 | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
 256     PPC_OPCODE_VLE },
 257   { "vsx",     PPC_OPCODE_PPC,
 258     PPC_OPCODE_VSX },
 259 };
 260
 261 /* Switch between Booke and VLE dialects for interlinked dumps.  */
 262 static ppc_cpu_t
 263 get_powerpc_dialect (struct disassemble_info *info)
 264 {
 265   ppc_cpu_t dialect = 0;
 266
 267   if (info->private_data)
 268     dialect = POWERPC_DIALECT (info);
 269
 270   /* Disassemble according to the section headers flags for VLE-mode.  */
 271   if (dialect & PPC_OPCODE_VLE
 272       && info->section != NULL && info->section->owner != NULL
 273       && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
 274       && elf_object_id (info->section->owner) == PPC32_ELF_DATA
 275       && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
 276     return dialect;
 277   else
 278     return dialect & ~ PPC_OPCODE_VLE;
 279 }
 280
 281 /* Handle -m and -M options that set cpu type, and .machine arg.  */
 282
 283 ppc_cpu_t
 284 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
 285 {
 286   unsigned int i;
 287
 288   for (i = 0; i < ARRAY_SIZE (ppc_opts); i++)
 289     if (disassembler_options_cmp (ppc_opts[i].opt, arg) == 0)
 290       {
 291         if (ppc_opts[i].sticky)
 292           {
 293             *sticky |= ppc_opts[i].sticky;
 294             if ((ppc_cpu & ~*sticky) != 0)
 295               break;
 296           }
 297         ppc_cpu = ppc_opts[i].cpu;
 298         break;
 299       }
 300   if (i >= ARRAY_SIZE (ppc_opts))
 301     return 0;
 302
 303   ppc_cpu |= *sticky;
 304   return ppc_cpu;
 305 }
 306
 307 /* Determine which set of machines to disassemble for.  */
 308
 309 static void
 310 powerpc_init_dialect (struct disassemble_info *info)
 311 {
 312   ppc_cpu_t dialect = 0;
 313   ppc_cpu_t sticky = 0;
 314   struct dis_private *priv = calloc (sizeof (*priv), 1);
 315
 316   if (priv == NULL)
 317     return;
 318
 319   switch (info->mach)
 320     {
 321     case bfd_mach_ppc_403:
 322     case bfd_mach_ppc_403gc:
 323       dialect = ppc_parse_cpu (dialect, &sticky, "403");
 324       break;
 325     case bfd_mach_ppc_405:
 326       dialect = ppc_parse_cpu (dialect, &sticky, "405");
 327       break;
 328     case bfd_mach_ppc_601:
 329       dialect = ppc_parse_cpu (dialect, &sticky, "601");
 330       break;
 331     case bfd_mach_ppc_750:
 332       dialect = ppc_parse_cpu (dialect, &sticky, "750cl");
 333       break;
 334     case bfd_mach_ppc_a35:
 335     case bfd_mach_ppc_rs64ii:
 336     case bfd_mach_ppc_rs64iii:
 337       dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
 338       break;
 339     case bfd_mach_ppc_e500:
 340       dialect = ppc_parse_cpu (dialect, &sticky, "e500");
 341       break;
 342     case bfd_mach_ppc_e500mc:
 343       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
 344       break;
 345     case bfd_mach_ppc_e500mc64:
 346       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
 347       break;
 348     case bfd_mach_ppc_e5500:
 349       dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
 350       break;
 351     case bfd_mach_ppc_e6500:
 352       dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
 353       break;
 354     case bfd_mach_ppc_titan:
 355       dialect = ppc_parse_cpu (dialect, &sticky, "titan");
 356       break;
 357     case bfd_mach_ppc_vle:
 358       dialect = ppc_parse_cpu (dialect, &sticky, "vle");
 359       break;
 360     default:
 361       if (info->arch == bfd_arch_powerpc)
 362         dialect = ppc_parse_cpu (dialect, &sticky, "power10") | PPC_OPCODE_ANY;
 363       else
 364         dialect = ppc_parse_cpu (dialect, &sticky, "pwr");
 365       break;
 366     }
 367
 368   const char *opt;
 369   FOR_EACH_DISASSEMBLER_OPTION (opt, info->disassembler_options)
 370     {
 371       ppc_cpu_t new_cpu = 0;
 372
 373       if (disassembler_options_cmp (opt, "32") == 0)
 374         dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
 375       else if (disassembler_options_cmp (opt, "64") == 0)
 376         dialect |= PPC_OPCODE_64;
 377       else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0)
 378         dialect = new_cpu;
 379       else
 380         /* xgettext: c-format */
 381         opcodes_error_handler (_("warning: ignoring unknown -M%s option"), opt);
 382     }
 383
 384   info->private_data = priv;
 385   POWERPC_DIALECT(info) = dialect;
 386 }
 387
 388 #define PPC_OPCD_SEGS (1 + PPC_OP (-1))
 389 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS + 1];
 390 #define PREFIX_OPCD_SEGS (1 + PPC_PREFIX_SEG (-1))
 391 static unsigned short prefix_opcd_indices[PREFIX_OPCD_SEGS + 1];
 392 #define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff)))
 393 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS + 1];
 394 #define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))
 395 static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS + 1];
 396
 397 /* Calculate opcode table indices to speed up disassembly,
 398    and init dialect.  */
 399
 400 void
 401 disassemble_init_powerpc (struct disassemble_info *info)
 402 {
 403   if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
 404     {
 405       unsigned seg, idx, op;
 406
 407       /* PPC opcodes */
 408       for (seg = 0, idx = 0; seg <= PPC_OPCD_SEGS; seg++)
 409         {
 410           powerpc_opcd_indices[seg] = idx;
 411           for (; idx < powerpc_num_opcodes; idx++)
 412             if (seg < PPC_OP (powerpc_opcodes[idx].opcode))
 413               break;
 414         }
 415
 416       /* 64-bit prefix opcodes */
 417       for (seg = 0, idx = 0; seg <= PREFIX_OPCD_SEGS; seg++)
 418         {
 419           prefix_opcd_indices[seg] = idx;
 420           for (; idx < prefix_num_opcodes; idx++)
 421             if (seg < PPC_PREFIX_SEG (prefix_opcodes[idx].opcode))
 422               break;
 423         }
 424
 425       /* VLE opcodes */
 426       for (seg = 0, idx = 0; seg <= VLE_OPCD_SEGS; seg++)
 427         {
 428           vle_opcd_indices[seg] = idx;
 429           for (; idx < vle_num_opcodes; idx++)
 430             {
 431               op = VLE_OP (vle_opcodes[idx].opcode, vle_opcodes[idx].mask);
 432               if (seg < VLE_OP_TO_SEG (op))
 433                 break;
 434             }
 435         }
 436
 437       /* SPE2 opcodes */
 438       for (seg = 0, idx = 0; seg <= SPE2_OPCD_SEGS; seg++)
 439         {
 440           spe2_opcd_indices[seg] = idx;
 441           for (; idx < spe2_num_opcodes; idx++)
 442             {
 443               op = SPE2_XOP (spe2_opcodes[idx].opcode);
 444               if (seg < SPE2_XOP_TO_SEG (op))
 445                 break;
 446             }
 447         }
 448     }
 449
 450   powerpc_init_dialect (info);
 451 }
 452
 453 /* Print a big endian PowerPC instruction.  */
 454
 455 int
 456 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 457 {
 458   return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
 459 }
 460
 461 /* Print a little endian PowerPC instruction.  */
 462
 463 int
 464 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 465 {
 466   return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
 467 }
 468
 469 /* Extract the operand value from the PowerPC or POWER instruction.  */
 470
 471 static int64_t
 472 operand_value_powerpc (const struct powerpc_operand *operand,
 473                        uint64_t insn, ppc_cpu_t dialect)
 474 {
 475   int64_t value;
 476   int invalid = 0;
 477   /* Extract the value from the instruction.  */
 478   if (operand->extract)
 479     value = (*operand->extract) (insn, dialect, &invalid);
 480   else
 481     {
 482       if (operand->shift >= 0)
 483         value = (insn >> operand->shift) & operand->bitm;
 484       else
 485         value = (insn << -operand->shift) & operand->bitm;
 486       if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
 487         {
 488           /* BITM is always some number of zeros followed by some
 489              number of ones, followed by some number of zeros.  */
 490           uint64_t top = operand->bitm;
 491           /* top & -top gives the rightmost 1 bit, so this
 492              fills in any trailing zeros.  */
 493           top |= (top & -top) - 1;
 494           top &= ~(top >> 1);
 495           value = (value ^ top) - top;
 496         }
 497     }
 498
 499   return value;
 500 }
 501
 502 /* Determine whether the optional operand(s) should be printed.  */
 503
 504 static bfd_boolean
 505 skip_optional_operands (const unsigned char *opindex,
 506                         uint64_t insn, ppc_cpu_t dialect)
 507 {
 508   const struct powerpc_operand *operand;
 509   int num_optional;
 510
 511   for (num_optional = 0; *opindex != 0; opindex++)
 512     {
 513       operand = &powerpc_operands[*opindex];
 514       if ((operand->flags & PPC_OPERAND_NEXT) != 0)
 515         return FALSE;
 516       if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
 517         {
 518           /* Negative count is used as a flag to extract function.  */
 519           --num_optional;
 520           if (operand_value_powerpc (operand, insn, dialect)
 521               != ppc_optional_operand_value (operand, insn, dialect,
 522                                              num_optional))
 523             return FALSE;
 524         }
 525     }
 526
 527   return TRUE;
 528 }
 529
 530 /* Find a match for INSN in the opcode table, given machine DIALECT.  */
 531
 532 static const struct powerpc_opcode *
 533 lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
 534 {
 535   const struct powerpc_opcode *opcode, *opcode_end, *last;
 536   unsigned long op;
 537
 538   /* Get the major opcode of the instruction.  */
 539   op = PPC_OP (insn);
 540
 541   /* Find the first match in the opcode table for this major opcode.  */
 542   opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
 543   last = NULL;
 544   for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
 545        opcode < opcode_end;
 546        ++opcode)
 547     {
 548       const unsigned char *opindex;
 549       const struct powerpc_operand *operand;
 550       int invalid;
 551
 552       if ((insn & opcode->mask) != opcode->opcode
 553           || ((dialect & PPC_OPCODE_ANY) == 0
 554               && ((opcode->flags & dialect) == 0
 555                   || (opcode->deprecated & dialect) != 0)))
 556         continue;
 557
 558       /* Check validity of operands.  */
 559       invalid = 0;
 560       for (opindex = opcode->operands; *opindex != 0; opindex++)
 561         {
 562           operand = powerpc_operands + *opindex;
 563           if (operand->extract)
 564             (*operand->extract) (insn, dialect, &invalid);
 565         }
 566       if (invalid)
 567         continue;
 568
 569       if ((dialect & PPC_OPCODE_RAW) == 0)
 570         return opcode;
 571
 572       /* The raw machine insn is one that is not a specialization.  */
 573       if (last == NULL
 574           || (last->mask & ~opcode->mask) != 0)
 575         last = opcode;
 576     }
 577
 578   return last;
 579 }
 580
 581 /* Find a match for INSN in the PREFIX opcode table.  */
 582
 583 static const struct powerpc_opcode *
 584 lookup_prefix (uint64_t insn, ppc_cpu_t dialect)
 585 {
 586   const struct powerpc_opcode *opcode, *opcode_end, *last;
 587   unsigned long seg;
 588
 589   /* Get the opcode segment of the instruction.  */
 590   seg = PPC_PREFIX_SEG (insn);
 591
 592   /* Find the first match in the opcode table for this major opcode.  */
 593   opcode_end = prefix_opcodes + prefix_opcd_indices[seg + 1];
 594   last = NULL;
 595   for (opcode = prefix_opcodes + prefix_opcd_indices[seg];
 596        opcode < opcode_end;
 597        ++opcode)
 598     {
 599       const unsigned char *opindex;
 600       const struct powerpc_operand *operand;
 601       int invalid;
 602
 603       if ((insn & opcode->mask) != opcode->opcode
 604           || ((dialect & PPC_OPCODE_ANY) == 0
 605               && ((opcode->flags & dialect) == 0
 606                   || (opcode->deprecated & dialect) != 0)))
 607         continue;
 608
 609       /* Check validity of operands.  */
 610       invalid = 0;
 611       for (opindex = opcode->operands; *opindex != 0; opindex++)
 612         {
 613           operand = powerpc_operands + *opindex;
 614           if (operand->extract)
 615             (*operand->extract) (insn, dialect, &invalid);
 616         }
 617       if (invalid)
 618         continue;
 619
 620       if ((dialect & PPC_OPCODE_RAW) == 0)
 621         return opcode;
 622
 623       /* The raw machine insn is one that is not a specialization.  */
 624       if (last == NULL
 625           || (last->mask & ~opcode->mask) != 0)
 626         last = opcode;
 627     }
 628
 629   return last;
 630 }
 631
 632 /* Find a match for INSN in the VLE opcode table.  */
 633
 634 static const struct powerpc_opcode *
 635 lookup_vle (uint64_t insn)
 636 {
 637   const struct powerpc_opcode *opcode;
 638   const struct powerpc_opcode *opcode_end;
 639   unsigned op, seg;
 640
 641   op = PPC_OP (insn);
 642   if (op >= 0x20 && op <= 0x37)
 643     {
 644       /* This insn has a 4-bit opcode.  */
 645       op &= 0x3c;
 646     }
 647   seg = VLE_OP_TO_SEG (op);
 648
 649   /* Find the first match in the opcode table for this major opcode.  */
 650   opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
 651   for (opcode = vle_opcodes + vle_opcd_indices[seg];
 652        opcode < opcode_end;
 653        ++opcode)
 654     {
 655       uint64_t table_opcd = opcode->opcode;
 656       uint64_t table_mask = opcode->mask;
 657       bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
 658       uint64_t insn2;
 659       const unsigned char *opindex;
 660       const struct powerpc_operand *operand;
 661       int invalid;
 662
 663       insn2 = insn;
 664       if (table_op_is_short)
 665         insn2 >>= 16;
 666       if ((insn2 & table_mask) != table_opcd)
 667         continue;
 668
 669       /* Check validity of operands.  */
 670       invalid = 0;
 671       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 672         {
 673           operand = powerpc_operands + *opindex;
 674           if (operand->extract)
 675             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 676         }
 677       if (invalid)
 678         continue;
 679
 680       return opcode;
 681     }
 682
 683   return NULL;
 684 }
 685
 686 /* Find a match for INSN in the SPE2 opcode table.  */
 687
 688 static const struct powerpc_opcode *
 689 lookup_spe2 (uint64_t insn)
 690 {
 691   const struct powerpc_opcode *opcode, *opcode_end;
 692   unsigned op, xop, seg;
 693
 694   op = PPC_OP (insn);
 695   if (op != 0x4)
 696     {
 697       /* This is not SPE2 insn.
 698        * All SPE2 instructions have OP=4 and differs by XOP  */
 699       return NULL;
 700     }
 701   xop = SPE2_XOP (insn);
 702   seg = SPE2_XOP_TO_SEG (xop);
 703
 704   /* Find the first match in the opcode table for this major opcode.  */
 705   opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
 706   for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
 707        opcode < opcode_end;
 708        ++opcode)
 709     {
 710       uint64_t table_opcd = opcode->opcode;
 711       uint64_t table_mask = opcode->mask;
 712       uint64_t insn2;
 713       const unsigned char *opindex;
 714       const struct powerpc_operand *operand;
 715       int invalid;
 716
 717       insn2 = insn;
 718       if ((insn2 & table_mask) != table_opcd)
 719         continue;
 720
 721       /* Check validity of operands.  */
 722       invalid = 0;
 723       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 724         {
 725           operand = powerpc_operands + *opindex;
 726           if (operand->extract)
 727             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 728         }
 729       if (invalid)
 730         continue;
 731
 732       return opcode;
 733     }
 734
 735   return NULL;
 736 }
 737
 738 /* Print a PowerPC or POWER instruction.  */
 739
 740 static int
 741 print_insn_powerpc (bfd_vma memaddr,
 742                     struct disassemble_info *info,
 743                     int bigendian,
 744                     ppc_cpu_t dialect)
 745 {
 746   bfd_byte buffer[4];
 747   int status;
 748   uint64_t insn;
 749   const struct powerpc_opcode *opcode;
 750   int insn_length = 4;  /* Assume we have a normal 4-byte instruction.  */
 751
 752   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
 753
 754   /* The final instruction may be a 2-byte VLE insn.  */
 755   if (status != 0 && (dialect & PPC_OPCODE_VLE) != 0)
 756     {
 757       /* Clear buffer so unused bytes will not have garbage in them.  */
 758       buffer[2] = buffer[3] = 0;
 759       status = (*info->read_memory_func) (memaddr, buffer, 2, info);
 760       insn_length = 2;
 761     }
 762
 763   if (status != 0)
 764     {
 765       (*info->memory_error_func) (status, memaddr, info);
 766       return -1;
 767     }
 768
 769   if (bigendian)
 770     insn = bfd_getb32 (buffer);
 771   else
 772     insn = bfd_getl32 (buffer);
 773
 774   /* Get the major opcode of the insn.  */
 775   opcode = NULL;
 776   if ((dialect & PPC_OPCODE_POWER10) != 0
 777       && PPC_OP (insn) == 0x1)
 778     {
 779       uint64_t temp_insn, suffix;
 780       status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
 781       if (status == 0)
 782         {
 783           if (bigendian)
 784             suffix = bfd_getb32 (buffer);
 785           else
 786             suffix = bfd_getl32 (buffer);
 787           temp_insn = (insn << 32) | suffix;
 788           opcode = lookup_prefix (temp_insn, dialect & ~PPC_OPCODE_ANY);
 789           if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
 790             opcode = lookup_prefix (temp_insn, dialect);
 791           if (opcode != NULL)
 792             {
 793               insn = temp_insn;
 794               insn_length = 8;
 795               if ((info->flags & WIDE_OUTPUT) != 0)
 796                 info->bytes_per_line = 8;
 797             }
 798         }
 799     }
 800   if (opcode == NULL && (dialect & PPC_OPCODE_VLE) != 0)
 801     {
 802       opcode = lookup_vle (insn);
 803       if (opcode != NULL && PPC_OP_SE_VLE (opcode->mask))
 804         {
 805           /* The operands will be fetched out of the 16-bit instruction.  */
 806           insn >>= 16;
 807           insn_length = 2;
 808         }
 809     }
 810   if (opcode == NULL && insn_length == 4)
 811     {
 812       if ((dialect & PPC_OPCODE_SPE2) != 0)
 813         opcode = lookup_spe2 (insn);
 814       if (opcode == NULL)
 815         opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
 816       if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
 817         opcode = lookup_powerpc (insn, dialect);
 818     }
 819
 820   if (opcode != NULL)
 821     {
 822       const unsigned char *opindex;
 823       const struct powerpc_operand *operand;
 824       enum {
 825         need_comma = 0,
 826         need_1space = 1,
 827         need_2spaces = 2,
 828         need_3spaces = 3,
 829         need_4spaces = 4,
 830         need_5spaces = 5,
 831         need_6spaces = 6,
 832         need_7spaces = 7,
 833         need_paren
 834       } op_separator;
 835       bfd_boolean skip_optional;
 836       int blanks;
 837
 838       (*info->fprintf_func) (info->stream, "%s", opcode->name);
 839       /* gdb fprintf_func doesn't return count printed.  */
 840       blanks = 8 - strlen (opcode->name);
 841       if (blanks <= 0)
 842         blanks = 1;
 843
 844       /* Now extract and print the operands.  */
 845       op_separator = blanks;
 846       skip_optional = FALSE;
 847       for (opindex = opcode->operands; *opindex != 0; opindex++)
 848         {
 849           int64_t value;
 850
 851           operand = powerpc_operands + *opindex;
 852
 853           /* If all of the optional operands past this one have their
 854              default value, then don't print any of them.  Except in
 855              raw mode, print them all.  */
 856           if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
 857               && (dialect & PPC_OPCODE_RAW) == 0)
 858             {
 859               if (!skip_optional)
 860                 skip_optional = skip_optional_operands (opindex, insn, dialect);
 861               if (skip_optional)
 862                 continue;
 863             }
 864
 865           value = operand_value_powerpc (operand, insn, dialect);
 866
 867           if (op_separator == need_comma)
 868             (*info->fprintf_func) (info->stream, ",");
 869           else if (op_separator == need_paren)
 870             (*info->fprintf_func) (info->stream, "(");
 871           else
 872             (*info->fprintf_func) (info->stream, "%*s", op_separator, " ");
 873
 874           /* Print the operand as directed by the flags.  */
 875           if ((operand->flags & PPC_OPERAND_GPR) != 0
 876               || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
 877             (*info->fprintf_func) (info->stream, "r%" PRId64, value);
 878           else if ((operand->flags & PPC_OPERAND_FPR) != 0)
 879             (*info->fprintf_func) (info->stream, "f%" PRId64, value);
 880           else if ((operand->flags & PPC_OPERAND_VR) != 0)
 881             (*info->fprintf_func) (info->stream, "v%" PRId64, value);
 882           else if ((operand->flags & PPC_OPERAND_VSR) != 0)
 883             (*info->fprintf_func) (info->stream, "vs%" PRId64, value);
 884           else if ((operand->flags & PPC_OPERAND_ACC) != 0)
 885             (*info->fprintf_func) (info->stream, "a%" PRId64, value);
 886           else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
 887             (*info->print_address_func) (memaddr + value, info);
 888           else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
 889             (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
 890           else if ((operand->flags & PPC_OPERAND_FSL) != 0)
 891             (*info->fprintf_func) (info->stream, "fsl%" PRId64, value);
 892           else if ((operand->flags & PPC_OPERAND_FCR) != 0)
 893             (*info->fprintf_func) (info->stream, "fcr%" PRId64, value);
 894           else if ((operand->flags & PPC_OPERAND_UDI) != 0)
 895             (*info->fprintf_func) (info->stream, "%" PRId64, value);
 896           else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
 897                    && (operand->flags & PPC_OPERAND_CR_BIT) == 0
 898                    && (((dialect & PPC_OPCODE_PPC) != 0)
 899                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 900             (*info->fprintf_func) (info->stream, "cr%" PRId64, value);
 901           else if ((operand->flags & PPC_OPERAND_CR_BIT) != 0
 902                    && (operand->flags & PPC_OPERAND_CR_REG) == 0
 903                    && (((dialect & PPC_OPCODE_PPC) != 0)
 904                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 905             {
 906               static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
 907               int cr;
 908               int cc;
 909
 910               cr = value >> 2;
 911               if (cr != 0)
 912                 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
 913               cc = value & 3;
 914               (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
 915             }
 916           else
 917             (*info->fprintf_func) (info->stream, "%" PRId64, value);
 918
 919           if (op_separator == need_paren)
 920             (*info->fprintf_func) (info->stream, ")");
 921
 922           op_separator = need_comma;
 923           if ((operand->flags & PPC_OPERAND_PARENS) != 0)
 924             op_separator = need_paren;
 925         }
 926
 927       /* We have found and printed an instruction.  */
 928       return insn_length;
 929     }
 930
 931   /* We could not find a match.  */
 932   if (insn_length == 4)
 933     (*info->fprintf_func) (info->stream, ".long 0x%x",
 934                            (unsigned int) insn);
 935   else
 936     (*info->fprintf_func) (info->stream, ".word 0x%x",
 937                            (unsigned int) insn >> 16);
 938   return insn_length;
 939 }
 940
 941 const disasm_options_and_args_t *
 942 disassembler_options_powerpc (void)
 943 {
 944   static disasm_options_and_args_t *opts_and_args;
 945
 946   if (opts_and_args == NULL)
 947     {
 948       size_t i, num_options = ARRAY_SIZE (ppc_opts);
 949       disasm_options_t *opts;
 950
 951       opts_and_args = XNEW (disasm_options_and_args_t);
 952       opts_and_args->args = NULL;
 953
 954       opts = &opts_and_args->options;
 955       opts->name = XNEWVEC (const char *, num_options + 1);
 956       opts->description = NULL;
 957       opts->arg = NULL;
 958       for (i = 0; i < num_options; i++)
 959         opts->name[i] = ppc_opts[i].opt;
 960       /* The array we return must be NULL terminated.  */
 961       opts->name[i] = NULL;
 962     }
 963
 964   return opts_and_args;
 965 }
 966
 967 void
 968 print_ppc_disassembler_options (FILE *stream)
 969 {
 970   unsigned int i, col;
 971
 972   fprintf (stream, _("\n\
 973 The following PPC specific disassembler options are supported for use with\n\
 974 the -M switch:\n"));
 975
 976   for (col = 0, i = 0; i < ARRAY_SIZE (ppc_opts); i++)
 977     {
 978       col += fprintf (stream, " %s,", ppc_opts[i].opt);
 979       if (col > 66)
 980         {
 981           fprintf (stream, "\n");
 982           col = 0;
 983         }
 984     }
 985   fprintf (stream, "\n");
 986 }