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gdb: add target_ops::supports_displaced_step
[deliverable/binutils-gdb.git] / opcodes / riscv-opc.c
1 /* RISC-V opcode list
2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of the GNU opcodes library.
8
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23 #include "sysdep.h"
24 #include "opcode/riscv.h"
25 #include <stdio.h>
26
27 /* Register names used by gas and objdump. */
28
29 const char * const riscv_gpr_names_numeric[NGPR] =
30 {
31 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
32 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
33 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
34 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31"
35 };
36
37 const char * const riscv_gpr_names_abi[NGPR] = {
38 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
39 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
40 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
41 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"
42 };
43
44 const char * const riscv_fpr_names_numeric[NFPR] =
45 {
46 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
47 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
48 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
49 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
50 };
51
52 const char * const riscv_fpr_names_abi[NFPR] = {
53 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
54 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
55 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
56 "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
57 };
58
59 /* The order of overloaded instructions matters. Label arguments and
60 register arguments look the same. Instructions that can have either
61 for arguments must apear in the correct order in this table for the
62 assembler to pick the right one. In other words, entries with
63 immediate operands must apear after the same instruction with
64 registers.
65
66 Because of the lookup algorithm used, entries with the same opcode
67 name must be contiguous. */
68
69 #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1)
70 #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2)
71 #define MASK_RD (OP_MASK_RD << OP_SH_RD)
72 #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2)
73 #define MASK_IMM ENCODE_ITYPE_IMM (-1U)
74 #define MASK_RVC_IMM ENCODE_RVC_IMM (-1U)
75 #define MASK_UIMM ENCODE_UTYPE_IMM (-1U)
76 #define MASK_RM (OP_MASK_RM << OP_SH_RM)
77 #define MASK_PRED (OP_MASK_PRED << OP_SH_PRED)
78 #define MASK_SUCC (OP_MASK_SUCC << OP_SH_SUCC)
79 #define MASK_AQ (OP_MASK_AQ << OP_SH_AQ)
80 #define MASK_RL (OP_MASK_RL << OP_SH_RL)
81 #define MASK_AQRL (MASK_AQ | MASK_RL)
82
83 static int
84 match_opcode (const struct riscv_opcode *op, insn_t insn)
85 {
86 return ((insn ^ op->match) & op->mask) == 0;
87 }
88
89 static int
90 match_never (const struct riscv_opcode *op ATTRIBUTE_UNUSED,
91 insn_t insn ATTRIBUTE_UNUSED)
92 {
93 return 0;
94 }
95
96 static int
97 match_rs1_eq_rs2 (const struct riscv_opcode *op, insn_t insn)
98 {
99 int rs1 = (insn & MASK_RS1) >> OP_SH_RS1;
100 int rs2 = (insn & MASK_RS2) >> OP_SH_RS2;
101 return match_opcode (op, insn) && rs1 == rs2;
102 }
103
104 static int
105 match_rd_nonzero (const struct riscv_opcode *op, insn_t insn)
106 {
107 return match_opcode (op, insn) && ((insn & MASK_RD) != 0);
108 }
109
110 static int
111 match_c_add (const struct riscv_opcode *op, insn_t insn)
112 {
113 return match_rd_nonzero (op, insn) && ((insn & MASK_CRS2) != 0);
114 }
115
116 /* We don't allow mv zero,X to become a c.mv hint, so we need a separate
117 matching function for this. */
118
119 static int
120 match_c_add_with_hint (const struct riscv_opcode *op, insn_t insn)
121 {
122 return match_opcode (op, insn) && ((insn & MASK_CRS2) != 0);
123 }
124
125 static int
126 match_c_nop (const struct riscv_opcode *op, insn_t insn)
127 {
128 return (match_opcode (op, insn)
129 && (((insn & MASK_RD) >> OP_SH_RD) == 0));
130 }
131
132 static int
133 match_c_addi16sp (const struct riscv_opcode *op, insn_t insn)
134 {
135 return (match_opcode (op, insn)
136 && (((insn & MASK_RD) >> OP_SH_RD) == 2)
137 && EXTRACT_RVC_ADDI16SP_IMM (insn) != 0);
138 }
139
140 static int
141 match_c_lui (const struct riscv_opcode *op, insn_t insn)
142 {
143 return (match_rd_nonzero (op, insn)
144 && (((insn & MASK_RD) >> OP_SH_RD) != 2)
145 && EXTRACT_RVC_LUI_IMM (insn) != 0);
146 }
147
148 /* We don't allow lui zero,X to become a c.lui hint, so we need a separate
149 matching function for this. */
150
151 static int
152 match_c_lui_with_hint (const struct riscv_opcode *op, insn_t insn)
153 {
154 return (match_opcode (op, insn)
155 && (((insn & MASK_RD) >> OP_SH_RD) != 2)
156 && EXTRACT_RVC_LUI_IMM (insn) != 0);
157 }
158
159 static int
160 match_c_addi4spn (const struct riscv_opcode *op, insn_t insn)
161 {
162 return match_opcode (op, insn) && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0;
163 }
164
165 /* This requires a non-zero shift. A zero rd is a hint, so is allowed. */
166
167 static int
168 match_c_slli (const struct riscv_opcode *op, insn_t insn)
169 {
170 return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
171 }
172
173 /* This requires a non-zero rd, and a non-zero shift. */
174
175 static int
176 match_slli_as_c_slli (const struct riscv_opcode *op, insn_t insn)
177 {
178 return match_rd_nonzero (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
179 }
180
181 /* This requires a zero shift. A zero rd is a hint, so is allowed. */
182
183 static int
184 match_c_slli64 (const struct riscv_opcode *op, insn_t insn)
185 {
186 return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) == 0;
187 }
188
189 /* This is used for both srli and srai. This requires a non-zero shift.
190 A zero rd is not possible. */
191
192 static int
193 match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn)
194 {
195 return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
196 }
197
198 const struct riscv_opcode riscv_opcodes[] =
199 {
200 /* name, xlen, isa, operands, match, mask, match_func, pinfo. */
201 {"unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, INSN_ALIAS },
202 {"unimp", 0, INSN_CLASS_I, "", MATCH_CSRRW | (CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */
203 {"ebreak", 0, INSN_CLASS_C, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS },
204 {"ebreak", 0, INSN_CLASS_I, "", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 },
205 {"sbreak", 0, INSN_CLASS_C, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS },
206 {"sbreak", 0, INSN_CLASS_I, "", MATCH_EBREAK, MASK_EBREAK, match_opcode, INSN_ALIAS },
207 {"ret", 0, INSN_CLASS_C, "", MATCH_C_JR | (X_RA << OP_SH_RD), MASK_C_JR | MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
208 {"ret", 0, INSN_CLASS_I, "", MATCH_JALR | (X_RA << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS|INSN_BRANCH },
209 {"jr", 0, INSN_CLASS_C, "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS|INSN_BRANCH },
210 {"jr", 0, INSN_CLASS_I, "s", MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS|INSN_BRANCH },
211 {"jr", 0, INSN_CLASS_I, "o(s)", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
212 {"jr", 0, INSN_CLASS_I, "s,j", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
213 {"jalr", 0, INSN_CLASS_C, "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS|INSN_JSR },
214 {"jalr", 0, INSN_CLASS_I, "s", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR },
215 {"jalr", 0, INSN_CLASS_I, "o(s)", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
216 {"jalr", 0, INSN_CLASS_I, "s,j", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
217 {"jalr", 0, INSN_CLASS_I, "d,s", MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR },
218 {"jalr", 0, INSN_CLASS_I, "d,o(s)", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR },
219 {"jalr", 0, INSN_CLASS_I, "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR },
220 {"j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH },
221 {"j", 0, INSN_CLASS_I, "a", MATCH_JAL, MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
222 {"jal", 0, INSN_CLASS_I, "d,a", MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR },
223 {"jal", 32, INSN_CLASS_C, "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR },
224 {"jal", 0, INSN_CLASS_I, "a", MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
225 {"call", 0, INSN_CLASS_I, "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
226 {"call", 0, INSN_CLASS_I, "c", (X_RA << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
227 {"tail", 0, INSN_CLASS_I, "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
228 {"jump", 0, INSN_CLASS_I, "c,s", 0, (int) M_CALL, match_never, INSN_MACRO },
229 {"nop", 0, INSN_CLASS_C, "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS },
230 {"nop", 0, INSN_CLASS_I, "", MATCH_ADDI, MASK_ADDI | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS },
231 {"lui", 0, INSN_CLASS_C, "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS },
232 {"lui", 0, INSN_CLASS_I, "d,u", MATCH_LUI, MASK_LUI, match_opcode, 0 },
233 {"li", 0, INSN_CLASS_C, "d,Cv", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS },
234 {"li", 0, INSN_CLASS_C, "d,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS },
235 {"li", 0, INSN_CLASS_I, "d,j", MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode, INSN_ALIAS }, /* addi */
236 {"li", 0, INSN_CLASS_I, "d,I", 0, (int) M_LI, match_never, INSN_MACRO },
237 {"mv", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
238 {"mv", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS },
239 {"move", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
240 {"move", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS },
241 {"andi", 0, INSN_CLASS_C, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
242 {"andi", 0, INSN_CLASS_I, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
243 {"and", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
244 {"and", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
245 {"and", 0, INSN_CLASS_C, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
246 {"and", 0, INSN_CLASS_I, "d,s,t", MATCH_AND, MASK_AND, match_opcode, 0 },
247 {"and", 0, INSN_CLASS_I, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
248 {"beqz", 0, INSN_CLASS_C, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
249 {"beqz", 0, INSN_CLASS_I, "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
250 {"beq", 0, INSN_CLASS_C, "Cs,Cz,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
251 {"beq", 0, INSN_CLASS_I, "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, INSN_CONDBRANCH },
252 {"blez", 0, INSN_CLASS_I, "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
253 {"bgez", 0, INSN_CLASS_I, "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
254 {"bge", 0, INSN_CLASS_I, "s,t,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_CONDBRANCH },
255 {"bgeu", 0, INSN_CLASS_I, "s,t,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_CONDBRANCH },
256 {"ble", 0, INSN_CLASS_I, "t,s,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
257 {"bleu", 0, INSN_CLASS_I, "t,s,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
258 {"bltz", 0, INSN_CLASS_I, "s,p", MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
259 {"bgtz", 0, INSN_CLASS_I, "t,p", MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
260 {"blt", 0, INSN_CLASS_I, "s,t,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_CONDBRANCH },
261 {"bltu", 0, INSN_CLASS_I, "s,t,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_CONDBRANCH },
262 {"bgt", 0, INSN_CLASS_I, "t,s,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
263 {"bgtu", 0, INSN_CLASS_I, "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
264 {"bnez", 0, INSN_CLASS_C, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
265 {"bnez", 0, INSN_CLASS_I, "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
266 {"bne", 0, INSN_CLASS_C, "Cs,Cz,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
267 {"bne", 0, INSN_CLASS_I, "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, INSN_CONDBRANCH },
268 {"addi", 0, INSN_CLASS_C, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
269 {"addi", 0, INSN_CLASS_C, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
270 {"addi", 0, INSN_CLASS_C, "d,CU,z", MATCH_C_NOP, MASK_C_ADDI | MASK_RVC_IMM, match_c_nop, INSN_ALIAS },
271 {"addi", 0, INSN_CLASS_C, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
272 {"addi", 0, INSN_CLASS_C, "d,Cz,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS },
273 {"addi", 0, INSN_CLASS_I, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 },
274 {"add", 0, INSN_CLASS_C, "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
275 {"add", 0, INSN_CLASS_C, "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
276 {"add", 0, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
277 {"add", 0, INSN_CLASS_C, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
278 {"add", 0, INSN_CLASS_C, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
279 {"add", 0, INSN_CLASS_C, "d,Cz,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
280 {"add", 0, INSN_CLASS_I, "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 },
281 /* This is used for TLS, where the fourth arg is %tprel_add, to get a reloc
282 applied to an add instruction, for relaxation to use. */
283 {"add", 0, INSN_CLASS_I, "d,s,t,1",MATCH_ADD, MASK_ADD, match_opcode, 0 },
284 {"add", 0, INSN_CLASS_I, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS },
285 {"la", 0, INSN_CLASS_I, "d,B", 0, (int) M_LA, match_never, INSN_MACRO },
286 {"lla", 0, INSN_CLASS_I, "d,B", 0, (int) M_LLA, match_never, INSN_MACRO },
287 {"la.tls.gd", 0, INSN_CLASS_I, "d,A", 0, (int) M_LA_TLS_GD, match_never, INSN_MACRO },
288 {"la.tls.ie", 0, INSN_CLASS_I, "d,A", 0, (int) M_LA_TLS_IE, match_never, INSN_MACRO },
289 {"neg", 0, INSN_CLASS_I, "d,t", MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */
290 {"slli", 0, INSN_CLASS_C, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS },
291 {"slli", 0, INSN_CLASS_I, "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, 0 },
292 {"sll", 0, INSN_CLASS_C, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS },
293 {"sll", 0, INSN_CLASS_I, "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 },
294 {"sll", 0, INSN_CLASS_I, "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS },
295 {"srli", 0, INSN_CLASS_C, "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS },
296 {"srli", 0, INSN_CLASS_I, "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 },
297 {"srl", 0, INSN_CLASS_C, "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS },
298 {"srl", 0, INSN_CLASS_I, "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 },
299 {"srl", 0, INSN_CLASS_I, "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS },
300 {"srai", 0, INSN_CLASS_C, "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS },
301 {"srai", 0, INSN_CLASS_I, "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 },
302 {"sra", 0, INSN_CLASS_C, "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS },
303 {"sra", 0, INSN_CLASS_I, "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 },
304 {"sra", 0, INSN_CLASS_I, "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS },
305 {"sub", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS },
306 {"sub", 0, INSN_CLASS_I, "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, 0 },
307 {"lb", 0, INSN_CLASS_I, "d,o(s)", MATCH_LB, MASK_LB, match_opcode, INSN_DREF|INSN_1_BYTE },
308 {"lb", 0, INSN_CLASS_I, "d,A", 0, (int) M_LB, match_never, INSN_MACRO },
309 {"lbu", 0, INSN_CLASS_I, "d,o(s)", MATCH_LBU, MASK_LBU, match_opcode, INSN_DREF|INSN_1_BYTE },
310 {"lbu", 0, INSN_CLASS_I, "d,A", 0, (int) M_LBU, match_never, INSN_MACRO },
311 {"lh", 0, INSN_CLASS_I, "d,o(s)", MATCH_LH, MASK_LH, match_opcode, INSN_DREF|INSN_2_BYTE },
312 {"lh", 0, INSN_CLASS_I, "d,A", 0, (int) M_LH, match_never, INSN_MACRO },
313 {"lhu", 0, INSN_CLASS_I, "d,o(s)", MATCH_LHU, MASK_LHU, match_opcode, INSN_DREF|INSN_2_BYTE },
314 {"lhu", 0, INSN_CLASS_I, "d,A", 0, (int) M_LHU, match_never, INSN_MACRO },
315 {"lw", 0, INSN_CLASS_C, "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
316 {"lw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
317 {"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE },
318 {"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO },
319 {"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI | MASK_IMM, MASK_XORI | MASK_IMM, match_opcode, INSN_ALIAS },
320 {"ori", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 },
321 {"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
322 {"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
323 {"or", 0, INSN_CLASS_I, "d,s,t", MATCH_OR, MASK_OR, match_opcode, 0 },
324 {"or", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS },
325 {"auipc", 0, INSN_CLASS_I, "d,u", MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 },
326 {"seqz", 0, INSN_CLASS_I, "d,s", MATCH_SLTIU | ENCODE_ITYPE_IMM (1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS },
327 {"snez", 0, INSN_CLASS_I, "d,t", MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS },
328 {"sltz", 0, INSN_CLASS_I, "d,s", MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS },
329 {"sgtz", 0, INSN_CLASS_I, "d,t", MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS },
330 {"slti", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
331 {"slt", 0, INSN_CLASS_I, "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 },
332 {"slt", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS },
333 {"sltiu", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 },
334 {"sltu", 0, INSN_CLASS_I, "d,s,t", MATCH_SLTU, MASK_SLTU, match_opcode, 0 },
335 {"sltu", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS },
336 {"sgt", 0, INSN_CLASS_I, "d,t,s", MATCH_SLT, MASK_SLT, match_opcode, INSN_ALIAS },
337 {"sgtu", 0, INSN_CLASS_I, "d,t,s", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS },
338 {"sb", 0, INSN_CLASS_I, "t,q(s)", MATCH_SB, MASK_SB, match_opcode, INSN_DREF|INSN_1_BYTE },
339 {"sb", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SB, match_never, INSN_MACRO },
340 {"sh", 0, INSN_CLASS_I, "t,q(s)", MATCH_SH, MASK_SH, match_opcode, INSN_DREF|INSN_2_BYTE },
341 {"sh", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SH, match_never, INSN_MACRO },
342 {"sw", 0, INSN_CLASS_C, "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
343 {"sw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
344 {"sw", 0, INSN_CLASS_I, "t,q(s)", MATCH_SW, MASK_SW, match_opcode, INSN_DREF|INSN_4_BYTE },
345 {"sw", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO },
346 {"fence", 0, INSN_CLASS_I, "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS },
347 {"fence", 0, INSN_CLASS_I, "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
348 {"fence.i", 0, INSN_CLASS_I, "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 },
349 {"fence.tso", 0, INSN_CLASS_I, "", MATCH_FENCE_TSO, MASK_FENCE_TSO | MASK_RD | MASK_RS1, match_opcode, INSN_ALIAS },
350 {"rdcycle", 0, INSN_CLASS_I, "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS },
351 {"rdinstret", 0, INSN_CLASS_I, "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS },
352 {"rdtime", 0, INSN_CLASS_I, "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS },
353 {"rdcycleh", 32, INSN_CLASS_I, "d", MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, INSN_ALIAS },
354 {"rdinstreth", 32, INSN_CLASS_I, "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS },
355 {"rdtimeh", 32, INSN_CLASS_I, "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS },
356 {"ecall", 0, INSN_CLASS_I, "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
357 {"scall", 0, INSN_CLASS_I, "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
358 {"xori", 0, INSN_CLASS_I, "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, 0 },
359 {"xor", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
360 {"xor", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
361 {"xor", 0, INSN_CLASS_I, "d,s,t", MATCH_XOR, MASK_XOR, match_opcode, 0 },
362 {"xor", 0, INSN_CLASS_I, "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS },
363 {"lwu", 64, INSN_CLASS_I, "d,o(s)", MATCH_LWU, MASK_LWU, match_opcode, INSN_DREF|INSN_4_BYTE },
364 {"lwu", 64, INSN_CLASS_I, "d,A", 0, (int) M_LWU, match_never, INSN_MACRO },
365 {"ld", 64, INSN_CLASS_C, "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
366 {"ld", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
367 {"ld", 64, INSN_CLASS_I, "d,o(s)", MATCH_LD, MASK_LD, match_opcode, INSN_DREF|INSN_8_BYTE },
368 {"ld", 64, INSN_CLASS_I, "d,A", 0, (int) M_LD, match_never, INSN_MACRO },
369 {"sd", 64, INSN_CLASS_C, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
370 {"sd", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
371 {"sd", 64, INSN_CLASS_I, "t,q(s)", MATCH_SD, MASK_SD, match_opcode, INSN_DREF|INSN_8_BYTE },
372 {"sd", 64, INSN_CLASS_I, "t,A,s", 0, (int) M_SD, match_never, INSN_MACRO },
373 {"sext.w", 64, INSN_CLASS_C, "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
374 {"sext.w", 64, INSN_CLASS_I, "d,s", MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode, INSN_ALIAS },
375 {"addiw", 64, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
376 {"addiw", 64, INSN_CLASS_I, "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 },
377 {"addw", 64, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS },
378 {"addw", 64, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS },
379 {"addw", 64, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
380 {"addw", 64, INSN_CLASS_I, "d,s,t", MATCH_ADDW, MASK_ADDW, match_opcode, 0 },
381 {"addw", 64, INSN_CLASS_I, "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS },
382 {"negw", 64, INSN_CLASS_I, "d,t", MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */
383 {"slliw", 64, INSN_CLASS_I, "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 },
384 {"sllw", 64, INSN_CLASS_I, "d,s,t", MATCH_SLLW, MASK_SLLW, match_opcode, 0 },
385 {"sllw", 64, INSN_CLASS_I, "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS },
386 {"srliw", 64, INSN_CLASS_I, "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, 0 },
387 {"srlw", 64, INSN_CLASS_I, "d,s,t", MATCH_SRLW, MASK_SRLW, match_opcode, 0 },
388 {"srlw", 64, INSN_CLASS_I, "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, INSN_ALIAS },
389 {"sraiw", 64, INSN_CLASS_I, "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 },
390 {"sraw", 64, INSN_CLASS_I, "d,s,t", MATCH_SRAW, MASK_SRAW, match_opcode, 0 },
391 {"sraw", 64, INSN_CLASS_I, "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS },
392 {"subw", 64, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS },
393 {"subw", 64, INSN_CLASS_I, "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, 0 },
394
395 /* Atomic memory operation instruction subset */
396 {"lr.w", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
397 {"sc.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
398 {"amoadd.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
399 {"amoswap.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
400 {"amoand.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
401 {"amoor.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
402 {"amoxor.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
403 {"amomax.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
404 {"amomaxu.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
405 {"amomin.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
406 {"amominu.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
407 {"lr.w.aq", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W | MASK_AQ, MASK_LR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
408 {"sc.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W | MASK_AQ, MASK_SC_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
409 {"amoadd.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W | MASK_AQ, MASK_AMOADD_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
410 {"amoswap.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQ, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
411 {"amoand.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W | MASK_AQ, MASK_AMOAND_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
412 {"amoor.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W | MASK_AQ, MASK_AMOOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
413 {"amoxor.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQ, MASK_AMOXOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
414 {"amomax.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQ, MASK_AMOMAX_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
415 {"amomaxu.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQ, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
416 {"amomin.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQ, MASK_AMOMIN_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
417 {"amominu.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQ, MASK_AMOMINU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
418 {"lr.w.rl", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W | MASK_RL, MASK_LR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
419 {"sc.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W | MASK_RL, MASK_SC_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
420 {"amoadd.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W | MASK_RL, MASK_AMOADD_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
421 {"amoswap.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W | MASK_RL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
422 {"amoand.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W | MASK_RL, MASK_AMOAND_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
423 {"amoor.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W | MASK_RL, MASK_AMOOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
424 {"amoxor.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W | MASK_RL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
425 {"amomax.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W | MASK_RL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
426 {"amomaxu.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W | MASK_RL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
427 {"amomin.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W | MASK_RL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
428 {"amominu.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W | MASK_RL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
429 {"lr.w.aqrl", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W | MASK_AQRL, MASK_LR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
430 {"sc.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W | MASK_AQRL, MASK_SC_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
431 {"amoadd.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W | MASK_AQRL, MASK_AMOADD_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
432 {"amoswap.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQRL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
433 {"amoand.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W | MASK_AQRL, MASK_AMOAND_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
434 {"amoor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W | MASK_AQRL, MASK_AMOOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
435 {"amoxor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQRL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
436 {"amomax.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQRL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
437 {"amomaxu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQRL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
438 {"amomin.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQRL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
439 {"amominu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQRL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
440 {"lr.d", 64, INSN_CLASS_A , "d,0(s)", MATCH_LR_D, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
441 {"sc.d", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_SC_D, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
442 {"amoadd.d", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
443 {"amoswap.d", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
444 {"amoand.d", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
445 {"amoor.d", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
446 {"amoxor.d", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
447 {"amomax.d", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
448 {"amomaxu.d", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
449 {"amomin.d", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
450 {"amominu.d", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
451 {"lr.d.aq", 64, INSN_CLASS_A , "d,0(s)", MATCH_LR_D | MASK_AQ, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
452 {"sc.d.aq", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_SC_D | MASK_AQ, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
453 {"amoadd.d.aq", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOADD_D | MASK_AQ, MASK_AMOADD_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
454 {"amoswap.d.aq", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQ, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
455 {"amoand.d.aq", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOAND_D | MASK_AQ, MASK_AMOAND_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
456 {"amoor.d.aq", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOOR_D | MASK_AQ, MASK_AMOOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
457 {"amoxor.d.aq", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQ, MASK_AMOXOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
458 {"amomax.d.aq", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQ, MASK_AMOMAX_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
459 {"amomaxu.d.aq", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQ, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
460 {"amomin.d.aq", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQ, MASK_AMOMIN_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
461 {"amominu.d.aq", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQ, MASK_AMOMINU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
462 {"lr.d.rl", 64, INSN_CLASS_A , "d,0(s)", MATCH_LR_D | MASK_RL, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
463 {"sc.d.rl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_SC_D | MASK_RL, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
464 {"amoadd.d.rl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOADD_D | MASK_RL, MASK_AMOADD_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
465 {"amoswap.d.rl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOSWAP_D | MASK_RL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
466 {"amoand.d.rl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOAND_D | MASK_RL, MASK_AMOAND_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
467 {"amoor.d.rl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOOR_D | MASK_RL, MASK_AMOOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
468 {"amoxor.d.rl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOXOR_D | MASK_RL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
469 {"amomax.d.rl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMAX_D | MASK_RL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
470 {"amomaxu.d.rl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMAXU_D | MASK_RL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
471 {"amomin.d.rl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMIN_D | MASK_RL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
472 {"amominu.d.rl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMINU_D | MASK_RL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
473 {"lr.d.aqrl", 64, INSN_CLASS_A , "d,0(s)", MATCH_LR_D | MASK_AQRL, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
474 {"sc.d.aqrl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_SC_D | MASK_AQRL, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
475 {"amoadd.d.aqrl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOADD_D | MASK_AQRL, MASK_AMOADD_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
476 {"amoswap.d.aqrl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQRL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
477 {"amoand.d.aqrl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOAND_D | MASK_AQRL, MASK_AMOAND_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
478 {"amoor.d.aqrl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOOR_D | MASK_AQRL, MASK_AMOOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
479 {"amoxor.d.aqrl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQRL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
480 {"amomax.d.aqrl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQRL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
481 {"amomaxu.d.aqrl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQRL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
482 {"amomin.d.aqrl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQRL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
483 {"amominu.d.aqrl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQRL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
484
485 /* Multiply/Divide instruction subset */
486 {"mul", 0, INSN_CLASS_M, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 },
487 {"mulh", 0, INSN_CLASS_M, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 },
488 {"mulhu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
489 {"mulhsu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
490 {"div", 0, INSN_CLASS_M, "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, 0 },
491 {"divu", 0, INSN_CLASS_M, "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, 0 },
492 {"rem", 0, INSN_CLASS_M, "d,s,t", MATCH_REM, MASK_REM, match_opcode, 0 },
493 {"remu", 0, INSN_CLASS_M, "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, 0 },
494 {"mulw", 64, INSN_CLASS_M, "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 },
495 {"divw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
496 {"divuw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 },
497 {"remw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 },
498 {"remuw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
499
500 /* Single-precision floating-point instruction subset */
501 {"frcsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
502 {"frsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
503 {"fscsr", 0, INSN_CLASS_F, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS },
504 {"fscsr", 0, INSN_CLASS_F, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
505 {"fssr", 0, INSN_CLASS_F, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS },
506 {"fssr", 0, INSN_CLASS_F, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
507 {"frrm", 0, INSN_CLASS_F, "d", MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS },
508 {"fsrm", 0, INSN_CLASS_F, "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, INSN_ALIAS },
509 {"fsrm", 0, INSN_CLASS_F, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS },
510 {"fsrmi", 0, INSN_CLASS_F, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS },
511 {"fsrmi", 0, INSN_CLASS_F, "Z", MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, INSN_ALIAS },
512 {"frflags", 0, INSN_CLASS_F, "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS },
513 {"fsflags", 0, INSN_CLASS_F, "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, INSN_ALIAS },
514 {"fsflags", 0, INSN_CLASS_F, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS },
515 {"fsflagsi", 0, INSN_CLASS_F, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS },
516 {"fsflagsi", 0, INSN_CLASS_F, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, INSN_ALIAS },
517 {"flw", 32, INSN_CLASS_F_AND_C, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
518 {"flw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
519 {"flw", 0, INSN_CLASS_F, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE },
520 {"flw", 0, INSN_CLASS_F, "D,A,s", 0, (int) M_FLW, match_never, INSN_MACRO },
521 {"fsw", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
522 {"fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
523 {"fsw", 0, INSN_CLASS_F, "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
524 {"fsw", 0, INSN_CLASS_F, "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO },
525
526 {"fmv.x.w", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
527 {"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
528
529 {"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
530 {"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
531
532 {"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
533 {"fneg.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
534 {"fabs.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
535 {"fsgnj.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
536 {"fsgnjn.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
537 {"fsgnjx.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
538 {"fadd.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FADD_S | MASK_RM, MASK_FADD_S | MASK_RM, match_opcode, 0 },
539 {"fadd.s", 0, INSN_CLASS_F, "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
540 {"fsub.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FSUB_S | MASK_RM, MASK_FSUB_S | MASK_RM, match_opcode, 0 },
541 {"fsub.s", 0, INSN_CLASS_F, "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
542 {"fmul.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FMUL_S | MASK_RM, MASK_FMUL_S | MASK_RM, match_opcode, 0 },
543 {"fmul.s", 0, INSN_CLASS_F, "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
544 {"fdiv.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FDIV_S | MASK_RM, MASK_FDIV_S | MASK_RM, match_opcode, 0 },
545 {"fdiv.s", 0, INSN_CLASS_F, "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
546 {"fsqrt.s", 0, INSN_CLASS_F, "D,S", MATCH_FSQRT_S | MASK_RM, MASK_FSQRT_S | MASK_RM, match_opcode, 0 },
547 {"fsqrt.s", 0, INSN_CLASS_F, "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
548 {"fmin.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
549 {"fmax.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
550 {"fmadd.s", 0, INSN_CLASS_F, "D,S,T,R", MATCH_FMADD_S | MASK_RM, MASK_FMADD_S | MASK_RM, match_opcode, 0 },
551 {"fmadd.s", 0, INSN_CLASS_F, "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
552 {"fnmadd.s", 0, INSN_CLASS_F, "D,S,T,R", MATCH_FNMADD_S | MASK_RM, MASK_FNMADD_S | MASK_RM, match_opcode, 0 },
553 {"fnmadd.s", 0, INSN_CLASS_F, "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
554 {"fmsub.s", 0, INSN_CLASS_F, "D,S,T,R", MATCH_FMSUB_S | MASK_RM, MASK_FMSUB_S | MASK_RM, match_opcode, 0 },
555 {"fmsub.s", 0, INSN_CLASS_F, "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
556 {"fnmsub.s", 0, INSN_CLASS_F, "D,S,T,R", MATCH_FNMSUB_S | MASK_RM, MASK_FNMSUB_S | MASK_RM, match_opcode, 0 },
557 {"fnmsub.s", 0, INSN_CLASS_F, "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
558 {"fcvt.w.s", 0, INSN_CLASS_F, "d,S", MATCH_FCVT_W_S | MASK_RM, MASK_FCVT_W_S | MASK_RM, match_opcode, 0 },
559 {"fcvt.w.s", 0, INSN_CLASS_F, "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
560 {"fcvt.wu.s", 0, INSN_CLASS_F, "d,S", MATCH_FCVT_WU_S | MASK_RM, MASK_FCVT_WU_S | MASK_RM, match_opcode, 0 },
561 {"fcvt.wu.s", 0, INSN_CLASS_F, "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
562 {"fcvt.s.w", 0, INSN_CLASS_F, "D,s", MATCH_FCVT_S_W | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 },
563 {"fcvt.s.w", 0, INSN_CLASS_F, "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
564 {"fcvt.s.wu", 0, INSN_CLASS_F, "D,s", MATCH_FCVT_S_WU | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 },
565 {"fcvt.s.wu", 0, INSN_CLASS_F, "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
566 {"fclass.s", 0, INSN_CLASS_F, "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
567 {"feq.s", 0, INSN_CLASS_F, "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
568 {"flt.s", 0, INSN_CLASS_F, "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
569 {"fle.s", 0, INSN_CLASS_F, "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
570 {"fgt.s", 0, INSN_CLASS_F, "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
571 {"fge.s", 0, INSN_CLASS_F, "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
572 {"fcvt.l.s", 64, INSN_CLASS_F, "d,S", MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode, 0 },
573 {"fcvt.l.s", 64, INSN_CLASS_F, "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
574 {"fcvt.lu.s", 64, INSN_CLASS_F, "d,S", MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode, 0 },
575 {"fcvt.lu.s", 64, INSN_CLASS_F, "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
576 {"fcvt.s.l", 64, INSN_CLASS_F, "D,s", MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 },
577 {"fcvt.s.l", 64, INSN_CLASS_F, "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
578 {"fcvt.s.lu", 64, INSN_CLASS_F, "D,s", MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 },
579 {"fcvt.s.lu", 64, INSN_CLASS_F, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
580
581 /* Double-precision floating-point instruction subset */
582 {"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
583 {"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
584 {"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE },
585 {"fld", 0, INSN_CLASS_D, "D,A,s", 0, (int) M_FLD, match_never, INSN_MACRO },
586 {"fsd", 0, INSN_CLASS_D_AND_C, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
587 {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
588 {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE },
589 {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO },
590 {"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS },
591 {"fneg.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
592 {"fabs.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
593 {"fsgnj.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
594 {"fsgnjn.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
595 {"fsgnjx.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
596 {"fadd.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode, 0 },
597 {"fadd.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
598 {"fsub.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode, 0 },
599 {"fsub.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
600 {"fmul.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode, 0 },
601 {"fmul.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
602 {"fdiv.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode, 0 },
603 {"fdiv.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
604 {"fsqrt.d", 0, INSN_CLASS_D, "D,S", MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode, 0 },
605 {"fsqrt.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
606 {"fmin.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
607 {"fmax.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
608 {"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode, 0 },
609 {"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
610 {"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode, 0 },
611 {"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
612 {"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode, 0 },
613 {"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
614 {"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode, 0 },
615 {"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
616 {"fcvt.w.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode, 0 },
617 {"fcvt.w.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
618 {"fcvt.wu.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode, 0 },
619 {"fcvt.wu.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
620 {"fcvt.d.w", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode, 0 },
621 {"fcvt.d.wu", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode, 0 },
622 {"fcvt.d.s", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode, 0 },
623 {"fcvt.s.d", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode, 0 },
624 {"fcvt.s.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
625 {"fclass.d", 0, INSN_CLASS_D, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
626 {"feq.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
627 {"flt.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
628 {"fle.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
629 {"fgt.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
630 {"fge.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
631 {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 },
632 {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 },
633 {"fcvt.l.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode, 0 },
634 {"fcvt.l.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
635 {"fcvt.lu.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode, 0 },
636 {"fcvt.lu.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
637 {"fcvt.d.l", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 },
638 {"fcvt.d.l", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
639 {"fcvt.d.lu", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 },
640 {"fcvt.d.lu", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
641
642 /* Quad-precision floating-point instruction subset */
643 {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE },
644 {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO },
645 {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE },
646 {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO },
647 {"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
648 {"fneg.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
649 {"fabs.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
650 {"fsgnj.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
651 {"fsgnjn.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
652 {"fsgnjx.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
653 {"fadd.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FADD_Q | MASK_RM, MASK_FADD_Q | MASK_RM, match_opcode, 0 },
654 {"fadd.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
655 {"fsub.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSUB_Q | MASK_RM, MASK_FSUB_Q | MASK_RM, match_opcode, 0 },
656 {"fsub.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
657 {"fmul.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMUL_Q | MASK_RM, MASK_FMUL_Q | MASK_RM, match_opcode, 0 },
658 {"fmul.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
659 {"fdiv.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FDIV_Q | MASK_RM, MASK_FDIV_Q | MASK_RM, match_opcode, 0 },
660 {"fdiv.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
661 {"fsqrt.q", 0, INSN_CLASS_Q, "D,S", MATCH_FSQRT_Q | MASK_RM, MASK_FSQRT_Q | MASK_RM, match_opcode, 0 },
662 {"fsqrt.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
663 {"fmin.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
664 {"fmax.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
665 {"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMADD_Q | MASK_RM, MASK_FMADD_Q | MASK_RM, match_opcode, 0 },
666 {"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
667 {"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMADD_Q | MASK_RM, MASK_FNMADD_Q | MASK_RM, match_opcode, 0 },
668 {"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
669 {"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMSUB_Q | MASK_RM, MASK_FMSUB_Q | MASK_RM, match_opcode, 0 },
670 {"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
671 {"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMSUB_Q | MASK_RM, MASK_FNMSUB_Q | MASK_RM, match_opcode, 0 },
672 {"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
673 {"fcvt.w.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_W_Q | MASK_RM, MASK_FCVT_W_Q | MASK_RM, match_opcode, 0 },
674 {"fcvt.w.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
675 {"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_WU_Q | MASK_RM, MASK_FCVT_WU_Q | MASK_RM, match_opcode, 0 },
676 {"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
677 {"fcvt.q.w", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W | MASK_RM, match_opcode, 0 },
678 {"fcvt.q.wu", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU | MASK_RM, match_opcode, 0 },
679 {"fcvt.q.s", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S | MASK_RM, match_opcode, 0 },
680 {"fcvt.q.d", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D | MASK_RM, match_opcode, 0 },
681 {"fcvt.s.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_S_Q | MASK_RM, MASK_FCVT_S_Q | MASK_RM, match_opcode, 0 },
682 {"fcvt.s.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
683 {"fcvt.d.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_D_Q | MASK_RM, MASK_FCVT_D_Q | MASK_RM, match_opcode, 0 },
684 {"fcvt.d.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
685 {"fclass.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
686 {"feq.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
687 {"flt.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
688 {"fle.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
689 {"fgt.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
690 {"fge.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
691 {"fmv.x.q", 64, INSN_CLASS_Q, "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 },
692 {"fmv.q.x", 64, INSN_CLASS_Q, "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 },
693 {"fcvt.l.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_L_Q | MASK_RM, MASK_FCVT_L_Q | MASK_RM, match_opcode, 0 },
694 {"fcvt.l.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
695 {"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_LU_Q | MASK_RM, MASK_FCVT_LU_Q | MASK_RM, match_opcode, 0 },
696 {"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
697 {"fcvt.q.l", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_L | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 },
698 {"fcvt.q.l", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
699 {"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_LU | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 },
700 {"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
701
702 /* Compressed instructions. */
703 {"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 },
704 {"c.ebreak", 0, INSN_CLASS_C, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 },
705 {"c.jr", 0, INSN_CLASS_C, "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_BRANCH },
706 {"c.jalr", 0, INSN_CLASS_C, "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_JSR },
707 {"c.j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_BRANCH },
708 {"c.jal", 32, INSN_CLASS_C, "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_JSR },
709 {"c.beqz", 0, INSN_CLASS_C, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_CONDBRANCH },
710 {"c.bnez", 0, INSN_CLASS_C, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_CONDBRANCH },
711 {"c.lwsp", 0, INSN_CLASS_C, "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 },
712 {"c.lw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_DREF|INSN_4_BYTE },
713 {"c.swsp", 0, INSN_CLASS_C, "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_DREF|INSN_4_BYTE },
714 {"c.sw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_DREF|INSN_4_BYTE },
715 {"c.nop", 0, INSN_CLASS_C, "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS },
716 {"c.nop", 0, INSN_CLASS_C, "Cj", MATCH_C_ADDI, MASK_C_ADDI | MASK_RD, match_opcode, INSN_ALIAS },
717 {"c.mv", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add_with_hint, 0 },
718 {"c.lui", 0, INSN_CLASS_C, "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui_with_hint, 0 },
719 {"c.li", 0, INSN_CLASS_C, "d,Co", MATCH_C_LI, MASK_C_LI, match_opcode, 0 },
720 {"c.addi4spn", 0, INSN_CLASS_C, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, 0 },
721 {"c.addi16sp", 0, INSN_CLASS_C, "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, 0 },
722 {"c.addi", 0, INSN_CLASS_C, "d,Co", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 },
723 {"c.add", 0, INSN_CLASS_C, "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add_with_hint, 0 },
724 {"c.sub", 0, INSN_CLASS_C, "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 },
725 {"c.and", 0, INSN_CLASS_C, "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 },
726 {"c.or", 0, INSN_CLASS_C, "Cs,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, 0 },
727 {"c.xor", 0, INSN_CLASS_C, "Cs,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 },
728 {"c.slli", 0, INSN_CLASS_C, "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_c_slli, 0 },
729 {"c.srli", 0, INSN_CLASS_C, "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_c_slli, 0 },
730 {"c.srai", 0, INSN_CLASS_C, "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_c_slli, 0 },
731 {"c.slli64", 0, INSN_CLASS_C, "d", MATCH_C_SLLI64, MASK_C_SLLI64, match_c_slli64, 0 },
732 {"c.srli64", 0, INSN_CLASS_C, "Cs", MATCH_C_SRLI64, MASK_C_SRLI64, match_c_slli64, 0 },
733 {"c.srai64", 0, INSN_CLASS_C, "Cs", MATCH_C_SRAI64, MASK_C_SRAI64, match_c_slli64, 0 },
734 {"c.andi", 0, INSN_CLASS_C, "Cs,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 },
735 {"c.addiw", 64, INSN_CLASS_C, "d,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 },
736 {"c.addw", 64, INSN_CLASS_C, "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 },
737 {"c.subw", 64, INSN_CLASS_C, "Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 },
738 {"c.ldsp", 64, INSN_CLASS_C, "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_DREF|INSN_8_BYTE },
739 {"c.ld", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_DREF|INSN_8_BYTE },
740 {"c.sdsp", 64, INSN_CLASS_C, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_DREF|INSN_8_BYTE },
741 {"c.sd", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_DREF|INSN_8_BYTE },
742 {"c.fldsp", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_DREF|INSN_8_BYTE },
743 {"c.fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_DREF|INSN_8_BYTE },
744 {"c.fsdsp", 0, INSN_CLASS_D_AND_C, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_DREF|INSN_8_BYTE },
745 {"c.fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_DREF|INSN_8_BYTE },
746 {"c.flwsp", 32, INSN_CLASS_F_AND_C, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_DREF|INSN_4_BYTE },
747 {"c.flw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_DREF|INSN_4_BYTE },
748 {"c.fswsp", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE },
749 {"c.fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
750
751 /* Supervisor instructions */
752 {"csrr", 0, INSN_CLASS_I, "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, INSN_ALIAS },
753 {"csrwi", 0, INSN_CLASS_I, "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS },
754 {"csrsi", 0, INSN_CLASS_I, "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS },
755 {"csrci", 0, INSN_CLASS_I, "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS },
756 {"csrw", 0, INSN_CLASS_I, "E,s", MATCH_CSRRW, MASK_CSRRW | MASK_RD, match_opcode, INSN_ALIAS },
757 {"csrw", 0, INSN_CLASS_I, "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS },
758 {"csrs", 0, INSN_CLASS_I, "E,s", MATCH_CSRRS, MASK_CSRRS | MASK_RD, match_opcode, INSN_ALIAS },
759 {"csrs", 0, INSN_CLASS_I, "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS },
760 {"csrc", 0, INSN_CLASS_I, "E,s", MATCH_CSRRC, MASK_CSRRC | MASK_RD, match_opcode, INSN_ALIAS },
761 {"csrc", 0, INSN_CLASS_I, "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS },
762 {"csrrwi", 0, INSN_CLASS_I, "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 },
763 {"csrrsi", 0, INSN_CLASS_I, "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 },
764 {"csrrci", 0, INSN_CLASS_I, "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 },
765 {"csrrw", 0, INSN_CLASS_I, "d,E,s", MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 },
766 {"csrrw", 0, INSN_CLASS_I, "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, INSN_ALIAS },
767 {"csrrs", 0, INSN_CLASS_I, "d,E,s", MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 },
768 {"csrrs", 0, INSN_CLASS_I, "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, INSN_ALIAS },
769 {"csrrc", 0, INSN_CLASS_I, "d,E,s", MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 },
770 {"csrrc", 0, INSN_CLASS_I, "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, INSN_ALIAS },
771 {"uret", 0, INSN_CLASS_I, "", MATCH_URET, MASK_URET, match_opcode, 0 },
772 {"sret", 0, INSN_CLASS_I, "", MATCH_SRET, MASK_SRET, match_opcode, 0 },
773 {"hret", 0, INSN_CLASS_I, "", MATCH_HRET, MASK_HRET, match_opcode, 0 },
774 {"mret", 0, INSN_CLASS_I, "", MATCH_MRET, MASK_MRET, match_opcode, 0 },
775 {"dret", 0, INSN_CLASS_I, "", MATCH_DRET, MASK_DRET, match_opcode, 0 },
776 {"sfence.vm", 0, INSN_CLASS_I, "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 },
777 {"sfence.vm", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 },
778 {"sfence.vma", 0, INSN_CLASS_I, "", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS1 | MASK_RS2, match_opcode, INSN_ALIAS },
779 {"sfence.vma", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS2, match_opcode, INSN_ALIAS },
780 {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
781 {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
782
783 /* Terminate the list. */
784 {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
785 };
786
787 /* Instruction format for .insn directive. */
788 const struct riscv_opcode riscv_insn_types[] =
789 {
790 /* name, xlen, isa, operands, match, mask, match_func, pinfo. */
791 {"r", 0, INSN_CLASS_I, "O4,F3,F7,d,s,t", 0, 0, match_opcode, 0 },
792 {"r", 0, INSN_CLASS_F, "O4,F3,F7,D,s,t", 0, 0, match_opcode, 0 },
793 {"r", 0, INSN_CLASS_F, "O4,F3,F7,d,S,t", 0, 0, match_opcode, 0 },
794 {"r", 0, INSN_CLASS_F, "O4,F3,F7,D,S,t", 0, 0, match_opcode, 0 },
795 {"r", 0, INSN_CLASS_F, "O4,F3,F7,d,s,T", 0, 0, match_opcode, 0 },
796 {"r", 0, INSN_CLASS_F, "O4,F3,F7,D,s,T", 0, 0, match_opcode, 0 },
797 {"r", 0, INSN_CLASS_F, "O4,F3,F7,d,S,T", 0, 0, match_opcode, 0 },
798 {"r", 0, INSN_CLASS_F, "O4,F3,F7,D,S,T", 0, 0, match_opcode, 0 },
799
800 {"r", 0, INSN_CLASS_I, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode, 0 },
801 {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, 0 },
802 {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, 0 },
803 {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode, 0 },
804 {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode, 0 },
805 {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode, 0 },
806 {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode, 0 },
807 {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode, 0 },
808 {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode, 0 },
809 {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode, 0 },
810 {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode, 0 },
811 {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode, 0 },
812 {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode, 0 },
813 {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode, 0 },
814 {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, 0 },
815 {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, 0 },
816
817 {"r4", 0, INSN_CLASS_I, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode, 0 },
818 {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, 0 },
819 {"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, 0 },
820 {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode, 0 },
821 {"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode, 0 },
822 {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode, 0 },
823 {"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode, 0 },
824 {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode, 0 },
825 {"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode, 0 },
826 {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode, 0 },
827 {"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode, 0 },
828 {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode, 0 },
829 {"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode, 0 },
830 {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode, 0 },
831 {"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, 0 },
832 {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, 0 },
833
834 {"i", 0, INSN_CLASS_I, "O4,F3,d,s,j", 0, 0, match_opcode, 0 },
835 {"i", 0, INSN_CLASS_F, "O4,F3,D,s,j", 0, 0, match_opcode, 0 },
836 {"i", 0, INSN_CLASS_F, "O4,F3,d,S,j", 0, 0, match_opcode, 0 },
837 {"i", 0, INSN_CLASS_F, "O4,F3,D,S,j", 0, 0, match_opcode, 0 },
838
839 {"i", 0, INSN_CLASS_I, "O4,F3,d,o(s)", 0, 0, match_opcode, 0 },
840 {"i", 0, INSN_CLASS_F, "O4,F3,D,o(s)", 0, 0, match_opcode, 0 },
841
842 {"s", 0, INSN_CLASS_I, "O4,F3,t,q(s)", 0, 0, match_opcode, 0 },
843 {"s", 0, INSN_CLASS_F, "O4,F3,T,q(s)", 0, 0, match_opcode, 0 },
844
845 {"sb", 0, INSN_CLASS_I, "O4,F3,s,t,p", 0, 0, match_opcode, 0 },
846 {"sb", 0, INSN_CLASS_F, "O4,F3,S,t,p", 0, 0, match_opcode, 0 },
847 {"sb", 0, INSN_CLASS_F, "O4,F3,s,T,p", 0, 0, match_opcode, 0 },
848 {"sb", 0, INSN_CLASS_F, "O4,F3,S,T,p", 0, 0, match_opcode, 0 },
849
850 {"b", 0, INSN_CLASS_I, "O4,F3,s,t,p", 0, 0, match_opcode, 0 },
851 {"b", 0, INSN_CLASS_F, "O4,F3,S,t,p", 0, 0, match_opcode, 0 },
852 {"b", 0, INSN_CLASS_F, "O4,F3,s,T,p", 0, 0, match_opcode, 0 },
853 {"b", 0, INSN_CLASS_F, "O4,F3,S,T,p", 0, 0, match_opcode, 0 },
854
855 {"u", 0, INSN_CLASS_I, "O4,d,u", 0, 0, match_opcode, 0 },
856 {"u", 0, INSN_CLASS_F, "O4,D,u", 0, 0, match_opcode, 0 },
857
858 {"uj", 0, INSN_CLASS_I, "O4,d,a", 0, 0, match_opcode, 0 },
859 {"uj", 0, INSN_CLASS_F, "O4,D,a", 0, 0, match_opcode, 0 },
860
861 {"j", 0, INSN_CLASS_I, "O4,d,a", 0, 0, match_opcode, 0 },
862 {"j", 0, INSN_CLASS_F, "O4,D,a", 0, 0, match_opcode, 0 },
863
864 {"cr", 0, INSN_CLASS_C, "O2,CF4,d,CV", 0, 0, match_opcode, 0 },
865 {"cr", 0, INSN_CLASS_F_AND_C, "O2,CF4,D,CV", 0, 0, match_opcode, 0 },
866 {"cr", 0, INSN_CLASS_F_AND_C, "O2,CF4,d,CT", 0, 0, match_opcode, 0 },
867 {"cr", 0, INSN_CLASS_F_AND_C, "O2,CF4,D,CT", 0, 0, match_opcode, 0 },
868
869 {"ci", 0, INSN_CLASS_C, "O2,CF3,d,Co", 0, 0, match_opcode, 0 },
870 {"ci", 0, INSN_CLASS_F_AND_C, "O2,CF3,D,Co", 0, 0, match_opcode, 0 },
871
872 {"ciw", 0, INSN_CLASS_C, "O2,CF3,Ct,C8", 0, 0, match_opcode, 0 },
873 {"ciw", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C8", 0, 0, match_opcode, 0 },
874
875 {"ca", 0, INSN_CLASS_C, "O2,CF6,CF2,Cs,Ct", 0, 0, match_opcode, 0 },
876 {"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,CS,Ct", 0, 0, match_opcode, 0 },
877 {"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,Cs,CD", 0, 0, match_opcode, 0 },
878 {"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,CS,CD", 0, 0, match_opcode, 0 },
879
880 {"cb", 0, INSN_CLASS_C, "O2,CF3,Cs,Cp", 0, 0, match_opcode, 0 },
881 {"cb", 0, INSN_CLASS_F_AND_C, "O2,CF3,CS,Cp", 0, 0, match_opcode, 0 },
882
883 {"cj", 0, INSN_CLASS_C, "O2,CF3,Ca", 0, 0, match_opcode, 0 },
884 /* Terminate the list. */
885 {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
886 };
887
888 /* All standard extensions defined in all supported ISA spec. */
889 const struct riscv_ext_version riscv_ext_version_table[] =
890 {
891 /* name, ISA spec, major version, minor_version. */
892 {"e", ISA_SPEC_CLASS_20191213, 1, 9},
893 {"e", ISA_SPEC_CLASS_20190608, 1, 9},
894 {"e", ISA_SPEC_CLASS_2P2, 1, 9},
895
896 {"i", ISA_SPEC_CLASS_20191213, 2, 1},
897 {"i", ISA_SPEC_CLASS_20190608, 2, 1},
898 {"i", ISA_SPEC_CLASS_2P2, 2, 0},
899
900 {"m", ISA_SPEC_CLASS_20191213, 2, 0},
901 {"m", ISA_SPEC_CLASS_20190608, 2, 0},
902 {"m", ISA_SPEC_CLASS_2P2, 2, 0},
903
904 {"a", ISA_SPEC_CLASS_20191213, 2, 1},
905 {"a", ISA_SPEC_CLASS_20190608, 2, 0},
906 {"a", ISA_SPEC_CLASS_2P2, 2, 0},
907
908 {"f", ISA_SPEC_CLASS_20191213, 2, 2},
909 {"f", ISA_SPEC_CLASS_20190608, 2, 2},
910 {"f", ISA_SPEC_CLASS_2P2, 2, 0},
911
912 {"d", ISA_SPEC_CLASS_20191213, 2, 2},
913 {"d", ISA_SPEC_CLASS_20190608, 2, 2},
914 {"d", ISA_SPEC_CLASS_2P2, 2, 0},
915
916 {"q", ISA_SPEC_CLASS_20191213, 2, 2},
917 {"q", ISA_SPEC_CLASS_20190608, 2, 2},
918 {"q", ISA_SPEC_CLASS_2P2, 2, 0},
919
920 {"c", ISA_SPEC_CLASS_20191213, 2, 0},
921 {"c", ISA_SPEC_CLASS_20190608, 2, 0},
922 {"c", ISA_SPEC_CLASS_2P2, 2, 0},
923
924 {"p", ISA_SPEC_CLASS_20191213, 0, 2},
925 {"p", ISA_SPEC_CLASS_20190608, 0, 2},
926 {"p", ISA_SPEC_CLASS_2P2, 0, 1},
927
928 {"v", ISA_SPEC_CLASS_20191213, 0, 7},
929 {"v", ISA_SPEC_CLASS_20190608, 0, 7},
930 {"v", ISA_SPEC_CLASS_2P2, 0, 7},
931
932 {"n", ISA_SPEC_CLASS_20190608, 1, 1},
933 {"n", ISA_SPEC_CLASS_2P2, 1, 1},
934
935 {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
936 {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
937
938 /* Terminate the list. */
939 {NULL, 0, 0, 0}
940 };
941
942 struct isa_spec_t
943 {
944 const char *name;
945 enum riscv_isa_spec_class class;
946 };
947
948 /* List for all supported ISA spec versions. */
949 static const struct isa_spec_t isa_specs[] =
950 {
951 {"2.2", ISA_SPEC_CLASS_2P2},
952 {"20190608", ISA_SPEC_CLASS_20190608},
953 {"20191213", ISA_SPEC_CLASS_20191213},
954
955 /* Terminate the list. */
956 {NULL, 0}
957 };
958
959 /* Get the corresponding ISA spec class by giving a ISA spec string. */
960
961 int
962 riscv_get_isa_spec_class (const char *s,
963 enum riscv_isa_spec_class *class)
964 {
965 const struct isa_spec_t *version;
966
967 if (s == NULL)
968 return 0;
969
970 for (version = &isa_specs[0]; version->name != NULL; ++version)
971 if (strcmp (version->name, s) == 0)
972 {
973 *class = version->class;
974 return 1;
975 }
976
977 /* Can not find the supported ISA spec. */
978 return 0;
979 }
980
981 struct priv_spec_t
982 {
983 const char *name;
984 enum riscv_priv_spec_class class;
985 };
986
987 /* List for all supported privilege versions. */
988 static const struct priv_spec_t priv_specs[] =
989 {
990 {"1.9", PRIV_SPEC_CLASS_1P9},
991 {"1.9.1", PRIV_SPEC_CLASS_1P9P1},
992 {"1.10", PRIV_SPEC_CLASS_1P10},
993 {"1.11", PRIV_SPEC_CLASS_1P11},
994
995 /* Terminate the list. */
996 {NULL, 0}
997 };
998
999 /* Get the corresponding CSR version class by giving a privilege
1000 version string. */
1001
1002 int
1003 riscv_get_priv_spec_class (const char *s,
1004 enum riscv_priv_spec_class *class)
1005 {
1006 const struct priv_spec_t *version;
1007
1008 if (s == NULL)
1009 return 0;
1010
1011 for (version = &priv_specs[0]; version->name != NULL; ++version)
1012 if (strcmp (version->name, s) == 0)
1013 {
1014 *class = version->class;
1015 return 1;
1016 }
1017
1018 /* Can not find the supported privilege version. */
1019 return 0;
1020 }
1021
1022 /* Get the corresponding privilege version string by giving a CSR
1023 version class. */
1024
1025 const char *
1026 riscv_get_priv_spec_name (enum riscv_priv_spec_class class)
1027 {
1028 /* The first enum is PRIV_SPEC_CLASS_NONE. */
1029 return priv_specs[class - 1].name;
1030 }
GDB Binutils - Deliverables
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