opcodes/tic4x-dis.c

   1 /* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils.
   2
   3    Copyright (C) 2002-2020 Free Software Foundation, Inc.
   4
   5    Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
   6
   7    This file is part of the GNU opcodes library.
   8
   9    This library is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <math.h>
  26 #include "libiberty.h"
  27 #include "disassemble.h"
  28 #include "opcode/tic4x.h"
  29
  30 #define TIC4X_DEBUG 0
  31
  32 #define TIC4X_HASH_SIZE   11   /* 11 (bits) and above should give unique entries.  */
  33 #define TIC4X_SPESOP_SIZE 8    /* Max 8. ops for special instructions.  */
  34
  35 typedef enum
  36 {
  37   IMMED_SINT,
  38   IMMED_SUINT,
  39   IMMED_SFLOAT,
  40   IMMED_INT,
  41   IMMED_UINT,
  42   IMMED_FLOAT
  43 }
  44 immed_t;
  45
  46 typedef enum
  47 {
  48   INDIRECT_SHORT,
  49   INDIRECT_LONG,
  50   INDIRECT_TIC4X
  51 }
  52 indirect_t;
  53
  54 static int tic4x_version = 0;
  55 static int tic4x_dp = 0;
  56
  57 static int
  58 tic4x_pc_offset (unsigned int op)
  59 {
  60   /* Determine the PC offset for a C[34]x instruction.
  61      This could be simplified using some boolean algebra
  62      but at the expense of readability.  */
  63   switch (op >> 24)
  64     {
  65     case 0x60:  /* br */
  66     case 0x62:  /* call  (C4x) */
  67     case 0x64:  /* rptb  (C4x) */
  68       return 1;
  69     case 0x61:  /* brd */
  70     case 0x63:  /* laj */
  71     case 0x65:  /* rptbd (C4x) */
  72       return 3;
  73     case 0x66:  /* swi */
  74     case 0x67:
  75       return 0;
  76     default:
  77       break;
  78     }
  79
  80   switch ((op & 0xffe00000) >> 20)
  81     {
  82     case 0x6a0: /* bB */
  83     case 0x720: /* callB */
  84     case 0x740: /* trapB */
  85       return 1;
  86
  87     case 0x6a2: /* bBd */
  88     case 0x6a6: /* bBat */
  89     case 0x6aa: /* bBaf */
  90     case 0x722: /* lajB */
  91     case 0x748: /* latB */
  92     case 0x798: /* rptbd */
  93       return 3;
  94
  95     default:
  96       break;
  97     }
  98
  99   switch ((op & 0xfe200000) >> 20)
 100     {
 101     case 0x6e0: /* dbB */
 102       return 1;
 103
 104     case 0x6e2: /* dbBd */
 105       return 3;
 106
 107     default:
 108       break;
 109     }
 110
 111   return 0;
 112 }
 113
 114 static int
 115 tic4x_print_char (struct disassemble_info * info, char ch)
 116 {
 117   if (info != NULL)
 118     (*info->fprintf_func) (info->stream, "%c", ch);
 119   return 1;
 120 }
 121
 122 static int
 123 tic4x_print_str (struct disassemble_info *info, const char *str)
 124 {
 125   if (info != NULL)
 126     (*info->fprintf_func) (info->stream, "%s", str);
 127   return 1;
 128 }
 129
 130 static int
 131 tic4x_print_register (struct disassemble_info *info, unsigned long regno)
 132 {
 133   static tic4x_register_t ** registertable = NULL;
 134   unsigned int i;
 135
 136   if (registertable == NULL)
 137     {
 138       registertable = xmalloc (sizeof (tic4x_register_t *) * REG_TABLE_SIZE);
 139       for (i = 0; i < tic3x_num_registers; i++)
 140         registertable[tic3x_registers[i].regno]
 141           = (tic4x_register_t *) (tic3x_registers + i);
 142       if (IS_CPU_TIC4X (tic4x_version))
 143         {
 144           /* Add C4x additional registers, overwriting
 145              any C3x registers if necessary.  */
 146           for (i = 0; i < tic4x_num_registers; i++)
 147             registertable[tic4x_registers[i].regno]
 148               = (tic4x_register_t *)(tic4x_registers + i);
 149         }
 150     }
 151   if (regno > (IS_CPU_TIC4X (tic4x_version) ? TIC4X_REG_MAX : TIC3X_REG_MAX))
 152     return 0;
 153   if (info != NULL)
 154     (*info->fprintf_func) (info->stream, "%s", registertable[regno]->name);
 155   return 1;
 156 }
 157
 158 static int
 159 tic4x_print_addr (struct disassemble_info *info, unsigned long addr)
 160 {
 161   if (info != NULL)
 162     (*info->print_address_func)(addr, info);
 163   return 1;
 164 }
 165
 166 static int
 167 tic4x_print_relative (struct disassemble_info *info,
 168                       unsigned long pc,
 169                       long offset,
 170                       unsigned long opcode)
 171 {
 172   return tic4x_print_addr (info, pc + offset + tic4x_pc_offset (opcode));
 173 }
 174
 175 static int
 176 tic4x_print_direct (struct disassemble_info *info, unsigned long arg)
 177 {
 178   if (info != NULL)
 179     {
 180       (*info->fprintf_func) (info->stream, "@");
 181       tic4x_print_addr (info, arg + (tic4x_dp << 16));
 182     }
 183   return 1;
 184 }
 185 #if 0
 186 /* FIXME: make the floating point stuff not rely on host
 187    floating point arithmetic.  */
 188
 189 static void
 190 tic4x_print_ftoa (unsigned int val, FILE *stream, fprintf_ftype pfunc)
 191 {
 192   int e;
 193   int s;
 194   int f;
 195   double num = 0.0;
 196
 197   e = EXTRS (val, 31, 24);      /* Exponent.  */
 198   if (e != -128)
 199     {
 200       s = EXTRU (val, 23, 23);  /* Sign bit.  */
 201       f = EXTRU (val, 22, 0);   /* Mantissa.  */
 202       if (s)
 203         f += -2 * (1 << 23);
 204       else
 205         f += (1 << 23);
 206       num = f / (double)(1 << 23);
 207       num = ldexp (num, e);
 208     }
 209   (*pfunc)(stream, "%.9g", num);
 210 }
 211 #endif
 212
 213 static int
 214 tic4x_print_immed (struct disassemble_info *info,
 215                    immed_t type,
 216                    unsigned long arg)
 217 {
 218   int s;
 219   int f;
 220   int e;
 221   double num = 0.0;
 222
 223   if (info == NULL)
 224     return 1;
 225   switch (type)
 226     {
 227     case IMMED_SINT:
 228     case IMMED_INT:
 229       (*info->fprintf_func) (info->stream, "%ld", (long) arg);
 230       break;
 231
 232     case IMMED_SUINT:
 233     case IMMED_UINT:
 234       (*info->fprintf_func) (info->stream, "%lu", arg);
 235       break;
 236
 237     case IMMED_SFLOAT:
 238       e = EXTRS (arg, 15, 12);
 239       if (e != -8)
 240         {
 241           s = EXTRU (arg, 11, 11);
 242           f = EXTRU (arg, 10, 0);
 243           if (s)
 244             f += -2 * (1 << 11);
 245           else
 246             f += (1 << 11);
 247           num = f / (double)(1 << 11);
 248           num = ldexp (num, e);
 249         }
 250       (*info->fprintf_func) (info->stream, "%f", num);
 251       break;
 252     case IMMED_FLOAT:
 253       e = EXTRS (arg, 31, 24);
 254       if (e != -128)
 255         {
 256           s = EXTRU (arg, 23, 23);
 257           f = EXTRU (arg, 22, 0);
 258           if (s)
 259             f += -2 * (1 << 23);
 260           else
 261             f += (1 << 23);
 262           num = f / (double)(1 << 23);
 263           num = ldexp (num, e);
 264         }
 265       (*info->fprintf_func) (info->stream, "%f", num);
 266       break;
 267     }
 268   return 1;
 269 }
 270
 271 static int
 272 tic4x_print_cond (struct disassemble_info *info, unsigned int cond)
 273 {
 274   static tic4x_cond_t **condtable = NULL;
 275   unsigned int i;
 276
 277   if (condtable == NULL)
 278     {
 279       condtable = xcalloc (32, sizeof (tic4x_cond_t *));
 280       for (i = 0; i < tic4x_num_conds; i++)
 281         condtable[tic4x_conds[i].cond] = (tic4x_cond_t *)(tic4x_conds + i);
 282     }
 283   if (cond > 31 || condtable[cond] == NULL)
 284     return 0;
 285   if (info != NULL)
 286     (*info->fprintf_func) (info->stream, "%s", condtable[cond]->name);
 287   return 1;
 288 }
 289
 290 static int
 291 tic4x_print_indirect (struct disassemble_info *info,
 292                       indirect_t type,
 293                       unsigned long arg)
 294 {
 295   unsigned int aregno;
 296   unsigned int modn;
 297   unsigned int disp;
 298   const char *a;
 299
 300   aregno = 0;
 301   modn = 0;
 302   disp = 1;
 303   switch(type)
 304     {
 305     case INDIRECT_TIC4X:                /* *+ARn(disp) */
 306       disp = EXTRU (arg, 7, 3);
 307       aregno = EXTRU (arg, 2, 0) + REG_AR0;
 308       modn = 0;
 309       break;
 310     case INDIRECT_SHORT:
 311       disp = 1;
 312       aregno = EXTRU (arg, 2, 0) + REG_AR0;
 313       modn = EXTRU (arg, 7, 3);
 314       break;
 315     case INDIRECT_LONG:
 316       disp = EXTRU (arg, 7, 0);
 317       aregno = EXTRU (arg, 10, 8) + REG_AR0;
 318       modn = EXTRU (arg, 15, 11);
 319       if (modn > 7 && disp != 0)
 320         return 0;
 321       break;
 322     default:
 323         (*info->fprintf_func)(info->stream, "# internal error: Unknown indirect type %d", type);
 324         return 0;
 325     }
 326   if (modn > TIC3X_MODN_MAX)
 327     return 0;
 328   a = tic4x_indirects[modn].name;
 329   while (*a)
 330     {
 331       switch (*a)
 332         {
 333         case 'a':
 334           tic4x_print_register (info, aregno);
 335           break;
 336         case 'd':
 337           tic4x_print_immed (info, IMMED_UINT, disp);
 338           break;
 339         case 'y':
 340           tic4x_print_str (info, "ir0");
 341           break;
 342         case 'z':
 343           tic4x_print_str (info, "ir1");
 344           break;
 345         default:
 346           tic4x_print_char (info, *a);
 347           break;
 348         }
 349       a++;
 350     }
 351   return 1;
 352 }
 353
 354 static int
 355 tic4x_print_op (struct disassemble_info *info,
 356                 unsigned long instruction,
 357                 tic4x_inst_t *p,
 358                 unsigned long pc)
 359 {
 360   int val;
 361   const char *s;
 362   const char *parallel = NULL;
 363
 364   /* Print instruction name.  */
 365   s = p->name;
 366   while (*s && parallel == NULL)
 367     {
 368       switch (*s)
 369         {
 370         case 'B':
 371           if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16)))
 372             return 0;
 373           break;
 374         case 'C':
 375           if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23)))
 376             return 0;
 377           break;
 378         case '_':
 379           parallel = s + 1;     /* Skip past `_' in name.  */
 380           break;
 381         default:
 382           tic4x_print_char (info, *s);
 383           break;
 384         }
 385       s++;
 386     }
 387
 388   /* Print arguments.  */
 389   s = p->args;
 390   if (*s)
 391     tic4x_print_char (info, ' ');
 392
 393   while (*s)
 394     {
 395       switch (*s)
 396         {
 397         case '*': /* Indirect 0--15.  */
 398           if (! tic4x_print_indirect (info, INDIRECT_LONG,
 399                                       EXTRU (instruction, 15, 0)))
 400             return 0;
 401           break;
 402
 403         case '#': /* Only used for ldp, ldpk.  */
 404           tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
 405           break;
 406
 407         case '@': /* Direct 0--15.  */
 408           tic4x_print_direct (info, EXTRU (instruction, 15, 0));
 409           break;
 410
 411         case 'A': /* Address register 24--22.  */
 412           if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) +
 413                                       REG_AR0))
 414             return 0;
 415           break;
 416
 417         case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb
 418                      address 0--23.  */
 419           if (IS_CPU_TIC4X (tic4x_version))
 420             tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0),
 421                                   p->opcode);
 422           else
 423             tic4x_print_addr (info, EXTRU (instruction, 23, 0));
 424           break;
 425
 426         case 'C': /* Indirect (short C4x) 0--7.  */
 427           if (! IS_CPU_TIC4X (tic4x_version))
 428             return 0;
 429           if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
 430                                       EXTRU (instruction, 7, 0)))
 431             return 0;
 432           break;
 433
 434         case 'D':
 435           /* Cockup if get here...  */
 436           break;
 437
 438         case 'E': /* Register 0--7.  */
 439         case 'e':
 440           if (! tic4x_print_register (info, EXTRU (instruction, 7, 0)))
 441             return 0;
 442           break;
 443
 444         case 'F': /* 16-bit float immediate 0--15.  */
 445           tic4x_print_immed (info, IMMED_SFLOAT,
 446                              EXTRU (instruction, 15, 0));
 447           break;
 448
 449         case 'i': /* Extended indirect 0--7.  */
 450           if (EXTRU (instruction, 7, 5) == 7)
 451             {
 452               if (!tic4x_print_register (info, EXTRU (instruction, 4, 0)))
 453                 return 0;
 454               break;
 455             }
 456           /* Fallthrough */
 457
 458         case 'I': /* Indirect (short) 0--7.  */
 459           if (! tic4x_print_indirect (info, INDIRECT_SHORT,
 460                                       EXTRU (instruction, 7, 0)))
 461             return 0;
 462           break;
 463
 464         case 'j': /* Extended indirect 8--15 */
 465           if (EXTRU (instruction, 15, 13) == 7)
 466             {
 467               if (! tic4x_print_register (info, EXTRU (instruction, 12, 8)))
 468                 return 0;
 469               break;
 470             }
 471           /* Fall through.  */
 472
 473         case 'J': /* Indirect (short) 8--15.  */
 474           if (! tic4x_print_indirect (info, INDIRECT_SHORT,
 475                                       EXTRU (instruction, 15, 8)))
 476             return 0;
 477           break;
 478
 479         case 'G': /* Register 8--15.  */
 480         case 'g':
 481           if (! tic4x_print_register (info, EXTRU (instruction, 15, 8)))
 482             return 0;
 483           break;
 484
 485         case 'H': /* Register 16--18.  */
 486           if (! tic4x_print_register (info, EXTRU (instruction, 18, 16)))
 487             return 0;
 488           break;
 489
 490         case 'K': /* Register 19--21.  */
 491           if (! tic4x_print_register (info, EXTRU (instruction, 21, 19)))
 492             return 0;
 493           break;
 494
 495         case 'L': /* Register 22--24.  */
 496           if (! tic4x_print_register (info, EXTRU (instruction, 24, 22)))
 497             return 0;
 498           break;
 499
 500         case 'M': /* Register 22--22.  */
 501           tic4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2);
 502           break;
 503
 504         case 'N': /* Register 23--23.  */
 505           tic4x_print_register (info, EXTRU (instruction, 23, 23) + REG_R0);
 506           break;
 507
 508         case 'O': /* Indirect (short C4x) 8--15.  */
 509           if (! IS_CPU_TIC4X (tic4x_version))
 510             return 0;
 511           if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
 512                                       EXTRU (instruction, 15, 8)))
 513             return 0;
 514           break;
 515
 516         case 'P': /* Displacement 0--15 (used by Bcond and BcondD).  */
 517           tic4x_print_relative (info, pc, EXTRS (instruction, 15, 0),
 518                                 p->opcode);
 519           break;
 520
 521         case 'Q': /* Register 0--15.  */
 522         case 'q':
 523           if (! tic4x_print_register (info, EXTRU (instruction, 15, 0)))
 524             return 0;
 525           break;
 526
 527         case 'R': /* Register 16--20.  */
 528         case 'r':
 529           if (! tic4x_print_register (info, EXTRU (instruction, 20, 16)))
 530             return 0;
 531           break;
 532
 533         case 'S': /* 16-bit signed immediate 0--15.  */
 534           tic4x_print_immed (info, IMMED_SINT,
 535                              EXTRS (instruction, 15, 0));
 536           break;
 537
 538         case 'T': /* 5-bit signed immediate 16--20  (C4x stik).  */
 539           if (! IS_CPU_TIC4X (tic4x_version))
 540             return 0;
 541           if (! tic4x_print_immed (info, IMMED_SUINT,
 542                                    EXTRU (instruction, 20, 16)))
 543             return 0;
 544           break;
 545
 546         case 'U': /* 16-bit unsigned int immediate 0--15.  */
 547           tic4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0));
 548           break;
 549
 550         case 'V': /* 5/9-bit unsigned vector 0--4/8.  */
 551           tic4x_print_immed (info, IMMED_SUINT,
 552                              IS_CPU_TIC4X (tic4x_version) ?
 553                              EXTRU (instruction, 8, 0) :
 554                              EXTRU (instruction, 4, 0) & ~0x20);
 555           break;
 556
 557         case 'W': /* 8-bit signed immediate 0--7.  */
 558           if (! IS_CPU_TIC4X (tic4x_version))
 559             return 0;
 560           tic4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0));
 561           break;
 562
 563         case 'X': /* Expansion register 4--0.  */
 564           val = EXTRU (instruction, 4, 0) + REG_IVTP;
 565           if (val < REG_IVTP || val > REG_TVTP)
 566             return 0;
 567           if (! tic4x_print_register (info, val))
 568             return 0;
 569           break;
 570
 571         case 'Y': /* Address register 16--20.  */
 572           val = EXTRU (instruction, 20, 16);
 573           if (val < REG_AR0 || val > REG_SP)
 574             return 0;
 575           if (! tic4x_print_register (info, val))
 576             return 0;
 577           break;
 578
 579         case 'Z': /* Expansion register 16--20.  */
 580           val = EXTRU (instruction, 20, 16) + REG_IVTP;
 581           if (val < REG_IVTP || val > REG_TVTP)
 582             return 0;
 583           if (! tic4x_print_register (info, val))
 584             return 0;
 585           break;
 586
 587         case '|':       /* Parallel instruction.  */
 588           tic4x_print_str (info, " || ");
 589           tic4x_print_str (info, parallel);
 590           tic4x_print_char (info, ' ');
 591           break;
 592
 593         case ';':
 594           tic4x_print_char (info, ',');
 595           break;
 596
 597         default:
 598           tic4x_print_char (info, *s);
 599           break;
 600         }
 601       s++;
 602     }
 603   return 1;
 604 }
 605
 606 static void
 607 tic4x_hash_opcode_special (tic4x_inst_t **optable_special,
 608                            const tic4x_inst_t *inst)
 609 {
 610   int i;
 611
 612   for (i = 0;i < TIC4X_SPESOP_SIZE; i++)
 613     if (optable_special[i] != NULL
 614         && optable_special[i]->opcode == inst->opcode)
 615       {
 616         /* Collision (we have it already) - overwrite.  */
 617         optable_special[i] = (tic4x_inst_t *) inst;
 618         return;
 619       }
 620
 621   for (i = 0; i < TIC4X_SPESOP_SIZE; i++)
 622     if (optable_special[i] == NULL)
 623       {
 624         /* Add the new opcode.  */
 625         optable_special[i] = (tic4x_inst_t *) inst;
 626         return;
 627       }
 628
 629   /* This should never occur. This happens if the number of special
 630      instructions exceeds TIC4X_SPESOP_SIZE. Please increase the variable
 631      of this variable */
 632 #if TIC4X_DEBUG
 633   printf ("optable_special[] is full, please increase TIC4X_SPESOP_SIZE!\n");
 634 #endif
 635 }
 636
 637 static void
 638 tic4x_hash_opcode (tic4x_inst_t **optable,
 639                    tic4x_inst_t **optable_special,
 640                    const tic4x_inst_t *inst,
 641                    const unsigned long tic4x_oplevel)
 642 {
 643   unsigned int j;
 644   unsigned int opcode = inst->opcode >> (32 - TIC4X_HASH_SIZE);
 645   unsigned int opmask = inst->opmask >> (32 - TIC4X_HASH_SIZE);
 646
 647   /* Use a TIC4X_HASH_SIZE bit index as a hash index.  We should
 648      have unique entries so there's no point having a linked list
 649      for each entry?  */
 650   for (j = opcode; j < opmask; j++)
 651     if ((j & opmask) == opcode
 652          && inst->oplevel & tic4x_oplevel)
 653       {
 654 #if TIC4X_DEBUG
 655         /* We should only have collisions for synonyms like
 656            ldp for ldi.  */
 657         if (optable[j] != NULL)
 658           printf ("Collision at index %d, %s and %s\n",
 659                   j, optable[j]->name, inst->name);
 660 #endif
 661         /* Catch those ops that collide with others already inside the
 662            hash, and have a opmask greater than the one we use in the
 663            hash. Store them in a special-list, that will handle full
 664            32-bit INSN, not only the first 11-bit (or so). */
 665         if (optable[j] != NULL
 666             && inst->opmask & ~(opmask << (32 - TIC4X_HASH_SIZE)))
 667           {
 668             /* Add the instruction already on the list.  */
 669             tic4x_hash_opcode_special (optable_special, optable[j]);
 670
 671             /* Add the new instruction.  */
 672             tic4x_hash_opcode_special (optable_special, inst);
 673           }
 674
 675         optable[j] = (tic4x_inst_t *) inst;
 676       }
 677 }
 678
 679 /* Disassemble the instruction in 'instruction'.
 680    'pc' should be the address of this instruction, it will
 681    be used to print the target address if this is a relative jump or call
 682    the disassembled instruction is written to 'info'.
 683    The function returns the length of this instruction in words.  */
 684
 685 static int
 686 tic4x_disassemble (unsigned long pc,
 687                    unsigned long instruction,
 688                    struct disassemble_info *info)
 689 {
 690   static tic4x_inst_t **optable = NULL;
 691   static tic4x_inst_t **optable_special = NULL;
 692   tic4x_inst_t *p;
 693   int i;
 694   unsigned long tic4x_oplevel;
 695
 696   tic4x_version = info->mach;
 697
 698   tic4x_oplevel  = (IS_CPU_TIC4X (tic4x_version)) ? OP_C4X : 0;
 699   tic4x_oplevel |= OP_C3X | OP_LPWR | OP_IDLE2 | OP_ENH;
 700
 701   if (optable == NULL)
 702     {
 703       optable = xcalloc (sizeof (tic4x_inst_t *), (1 << TIC4X_HASH_SIZE));
 704
 705       optable_special = xcalloc (sizeof (tic4x_inst_t *), TIC4X_SPESOP_SIZE);
 706
 707       /* Install opcodes in reverse order so that preferred
 708          forms overwrite synonyms.  */
 709       for (i = tic4x_num_insts - 1; i >= 0; i--)
 710         tic4x_hash_opcode (optable, optable_special, &tic4x_insts[i],
 711                            tic4x_oplevel);
 712
 713       /* We now need to remove the insn that are special from the
 714          "normal" optable, to make the disasm search this extra list
 715          for them.  */
 716       for (i = 0; i < TIC4X_SPESOP_SIZE; i++)
 717         if (optable_special[i] != NULL)
 718           optable[optable_special[i]->opcode >> (32 - TIC4X_HASH_SIZE)] = NULL;
 719     }
 720
 721   /* See if we can pick up any loading of the DP register...  */
 722   if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70)
 723     tic4x_dp = EXTRU (instruction, 15, 0);
 724
 725   p = optable[instruction >> (32 - TIC4X_HASH_SIZE)];
 726   if (p != NULL)
 727     {
 728       if (((instruction & p->opmask) == p->opcode)
 729            && tic4x_print_op (NULL, instruction, p, pc))
 730         tic4x_print_op (info, instruction, p, pc);
 731       else
 732         (*info->fprintf_func) (info->stream, "%08lx", instruction);
 733     }
 734   else
 735     {
 736       for (i = 0; i<TIC4X_SPESOP_SIZE; i++)
 737         if (optable_special[i] != NULL
 738             && optable_special[i]->opcode == instruction)
 739           {
 740             (*info->fprintf_func)(info->stream, "%s", optable_special[i]->name);
 741             break;
 742           }
 743       if (i == TIC4X_SPESOP_SIZE)
 744         (*info->fprintf_func) (info->stream, "%08lx", instruction);
 745     }
 746
 747   /* Return size of insn in words.  */
 748   return 1;
 749 }
 750
 751 /* The entry point from objdump and gdb.  */
 752 int
 753 print_insn_tic4x (bfd_vma memaddr, struct disassemble_info *info)
 754 {
 755   int status;
 756   unsigned long pc;
 757   unsigned long op;
 758   bfd_byte buffer[4];
 759
 760   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
 761   if (status != 0)
 762     {
 763       (*info->memory_error_func) (status, memaddr, info);
 764       return -1;
 765     }
 766
 767   pc = memaddr;
 768   op = bfd_getl32 (buffer);
 769   info->bytes_per_line = 4;
 770   info->bytes_per_chunk = 4;
 771   info->octets_per_byte = 4;
 772   info->display_endian = BFD_ENDIAN_LITTLE;
 773   return tic4x_disassemble (pc, op, info) * 4;
 774 }