opcodes/xstormy16-desc.c

   1 /* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
   2 /* CPU data for xstormy16.
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5
   6 Copyright (C) 1996-2020 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   9
  10    This file is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 3, or (at your option)
  13    any later version.
  14
  15    It is distributed in the hope that it will be useful, but WITHOUT
  16    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  17    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  18    License for more details.
  19
  20    You should have received a copy of the GNU General Public License along
  21    with this program; if not, write to the Free Software Foundation, Inc.,
  22    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include "sysdep.h"
  27 #include <stdio.h>
  28 #include <stdarg.h>
  29 #include "ansidecl.h"
  30 #include "bfd.h"
  31 #include "symcat.h"
  32 #include "xstormy16-desc.h"
  33 #include "xstormy16-opc.h"
  34 #include "opintl.h"
  35 #include "libiberty.h"
  36 #include "xregex.h"
  37
  38 /* Attributes.  */
  39
  40 static const CGEN_ATTR_ENTRY bool_attr[] =
  41 {
  42   { "#f", 0 },
  43   { "#t", 1 },
  44   { 0, 0 }
  45 };
  46
  47 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
  48 {
  49   { "base", MACH_BASE },
  50   { "xstormy16", MACH_XSTORMY16 },
  51   { "max", MACH_MAX },
  52   { 0, 0 }
  53 };
  54
  55 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
  56 {
  57   { "xstormy16", ISA_XSTORMY16 },
  58   { "max", ISA_MAX },
  59   { 0, 0 }
  60 };
  61
  62 const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[] =
  63 {
  64   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  65   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  66   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  67   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  68   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  69   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  70   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  71   { 0, 0, 0 }
  72 };
  73
  74 const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[] =
  75 {
  76   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  77   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  78   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  79   { "PC", &bool_attr[0], &bool_attr[0] },
  80   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  81   { 0, 0, 0 }
  82 };
  83
  84 const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[] =
  85 {
  86   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  87   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  88   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  89   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  90   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  91   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  92   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
  93   { "RELAX", &bool_attr[0], &bool_attr[0] },
  94   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
  95   { 0, 0, 0 }
  96 };
  97
  98 const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] =
  99 {
 100   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 101   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 102   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 103   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 104   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 105   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 106   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 107   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 108   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 109   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 110   { "PBB", &bool_attr[0], &bool_attr[0] },
 111   { 0, 0, 0 }
 112 };
 113
 114 /* Instruction set variants.  */
 115
 116 static const CGEN_ISA xstormy16_cgen_isa_table[] = {
 117   { "xstormy16", 32, 32, 16, 32 },
 118   { 0, 0, 0, 0, 0 }
 119 };
 120
 121 /* Machine variants.  */
 122
 123 static const CGEN_MACH xstormy16_cgen_mach_table[] = {
 124   { "xstormy16", "xstormy16", MACH_XSTORMY16, 16 },
 125   { 0, 0, 0, 0 }
 126 };
 127
 128 static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_names_entries[] =
 129 {
 130   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
 131   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
 132   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
 133   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
 134   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
 135   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
 136   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
 137   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
 138   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
 139   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
 140   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
 141   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
 142   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
 143   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
 144   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
 145   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
 146   { "psw", 14, {0, {{{0, 0}}}}, 0, 0 },
 147   { "sp", 15, {0, {{{0, 0}}}}, 0, 0 }
 148 };
 149
 150 CGEN_KEYWORD xstormy16_cgen_opval_gr_names =
 151 {
 152   & xstormy16_cgen_opval_gr_names_entries[0],
 153   18,
 154   0, 0, 0, 0, ""
 155 };
 156
 157 static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_Rb_names_entries[] =
 158 {
 159   { "r8", 0, {0, {{{0, 0}}}}, 0, 0 },
 160   { "r9", 1, {0, {{{0, 0}}}}, 0, 0 },
 161   { "r10", 2, {0, {{{0, 0}}}}, 0, 0 },
 162   { "r11", 3, {0, {{{0, 0}}}}, 0, 0 },
 163   { "r12", 4, {0, {{{0, 0}}}}, 0, 0 },
 164   { "r13", 5, {0, {{{0, 0}}}}, 0, 0 },
 165   { "r14", 6, {0, {{{0, 0}}}}, 0, 0 },
 166   { "r15", 7, {0, {{{0, 0}}}}, 0, 0 },
 167   { "psw", 6, {0, {{{0, 0}}}}, 0, 0 },
 168   { "sp", 7, {0, {{{0, 0}}}}, 0, 0 }
 169 };
 170
 171 CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names =
 172 {
 173   & xstormy16_cgen_opval_gr_Rb_names_entries[0],
 174   10,
 175   0, 0, 0, 0, ""
 176 };
 177
 178 static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_branchcond_entries[] =
 179 {
 180   { "ge", 0, {0, {{{0, 0}}}}, 0, 0 },
 181   { "nc", 1, {0, {{{0, 0}}}}, 0, 0 },
 182   { "lt", 2, {0, {{{0, 0}}}}, 0, 0 },
 183   { "c", 3, {0, {{{0, 0}}}}, 0, 0 },
 184   { "gt", 4, {0, {{{0, 0}}}}, 0, 0 },
 185   { "hi", 5, {0, {{{0, 0}}}}, 0, 0 },
 186   { "le", 6, {0, {{{0, 0}}}}, 0, 0 },
 187   { "ls", 7, {0, {{{0, 0}}}}, 0, 0 },
 188   { "pl", 8, {0, {{{0, 0}}}}, 0, 0 },
 189   { "nv", 9, {0, {{{0, 0}}}}, 0, 0 },
 190   { "mi", 10, {0, {{{0, 0}}}}, 0, 0 },
 191   { "v", 11, {0, {{{0, 0}}}}, 0, 0 },
 192   { "nz.b", 12, {0, {{{0, 0}}}}, 0, 0 },
 193   { "nz", 13, {0, {{{0, 0}}}}, 0, 0 },
 194   { "z.b", 14, {0, {{{0, 0}}}}, 0, 0 },
 195   { "z", 15, {0, {{{0, 0}}}}, 0, 0 }
 196 };
 197
 198 CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond =
 199 {
 200   & xstormy16_cgen_opval_h_branchcond_entries[0],
 201   16,
 202   0, 0, 0, 0, ""
 203 };
 204
 205 static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_wordsize_entries[] =
 206 {
 207   { ".b", 0, {0, {{{0, 0}}}}, 0, 0 },
 208   { ".w", 1, {0, {{{0, 0}}}}, 0, 0 },
 209   { "", 1, {0, {{{0, 0}}}}, 0, 0 }
 210 };
 211
 212 CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize =
 213 {
 214   & xstormy16_cgen_opval_h_wordsize_entries[0],
 215   3,
 216   0, 0, 0, 0, ""
 217 };
 218
 219
 220 /* The hardware table.  */
 221
 222 #define A(a) (1 << CGEN_HW_##a)
 223
 224 const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] =
 225 {
 226   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 227   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 228   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 229   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 230   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 231   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
 232   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 233   { "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
 234   { "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
 235   { "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
 236   { "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
 237   { "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
 238   { "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
 239   { "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
 240   { "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
 241   { "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
 242   { "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
 243   { "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 244   { "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 245   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 246 };
 247
 248 #undef A
 249
 250
 251 /* The instruction field table.  */
 252
 253 #define A(a) (1 << CGEN_IFLD_##a)
 254
 255 const CGEN_IFLD xstormy16_cgen_ifld_table[] =
 256 {
 257   { XSTORMY16_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 258   { XSTORMY16_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 259   { XSTORMY16_F_RD, "f-Rd", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 260   { XSTORMY16_F_RDM, "f-Rdm", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 261   { XSTORMY16_F_RM, "f-Rm", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 262   { XSTORMY16_F_RS, "f-Rs", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 263   { XSTORMY16_F_RB, "f-Rb", 0, 32, 17, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 264   { XSTORMY16_F_RBJ, "f-Rbj", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 265   { XSTORMY16_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 266   { XSTORMY16_F_OP2, "f-op2", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 267   { XSTORMY16_F_OP2A, "f-op2a", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 268   { XSTORMY16_F_OP2M, "f-op2m", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 269   { XSTORMY16_F_OP3, "f-op3", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 270   { XSTORMY16_F_OP3A, "f-op3a", 0, 32, 8, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 271   { XSTORMY16_F_OP3B, "f-op3b", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 272   { XSTORMY16_F_OP4, "f-op4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 273   { XSTORMY16_F_OP4M, "f-op4m", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 274   { XSTORMY16_F_OP4B, "f-op4b", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 275   { XSTORMY16_F_OP5, "f-op5", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 276   { XSTORMY16_F_OP5A, "f-op5a", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 277   { XSTORMY16_F_OP, "f-op", 0, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 278   { XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 279   { XSTORMY16_F_IMM3, "f-imm3", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 280   { XSTORMY16_F_IMM3B, "f-imm3b", 0, 32, 17, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 281   { XSTORMY16_F_IMM4, "f-imm4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 282   { XSTORMY16_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 283   { XSTORMY16_F_IMM12, "f-imm12", 0, 32, 20, 12, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 284   { XSTORMY16_F_IMM16, "f-imm16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
 285   { XSTORMY16_F_LMEM8, "f-lmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 286   { XSTORMY16_F_HMEM8, "f-hmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 287   { XSTORMY16_F_REL8_2, "f-rel8-2", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 288   { XSTORMY16_F_REL8_4, "f-rel8-4", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 289   { XSTORMY16_F_REL12, "f-rel12", 0, 32, 20, 12, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 290   { XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 291   { XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 292   { XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 293   { XSTORMY16_F_ABS24, "f-abs24", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
 294   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 295 };
 296
 297 #undef A
 298
 299
 300
 301 /* multi ifield declarations */
 302
 303 const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [];
 304
 305
 306 /* multi ifield definitions */
 307
 308 const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [] =
 309 {
 310     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_1] } },
 311     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_2] } },
 312     { 0, { (const PTR) 0 } }
 313 };
 314
 315 /* The operand table.  */
 316
 317 #define A(a) (1 << CGEN_OPERAND_##a)
 318 #define OPERAND(op) XSTORMY16_OPERAND_##op
 319
 320 const CGEN_OPERAND xstormy16_cgen_operand_table[] =
 321 {
 322 /* pc: program counter */
 323   { "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0,
 324     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_NIL] } },
 325     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 326 /* psw-z8:  */
 327   { "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0,
 328     { 0, { (const PTR) 0 } },
 329     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 330 /* psw-z16:  */
 331   { "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0,
 332     { 0, { (const PTR) 0 } },
 333     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 334 /* psw-cy:  */
 335   { "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0,
 336     { 0, { (const PTR) 0 } },
 337     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 338 /* psw-hc:  */
 339   { "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0,
 340     { 0, { (const PTR) 0 } },
 341     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 342 /* psw-ov:  */
 343   { "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0,
 344     { 0, { (const PTR) 0 } },
 345     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 346 /* psw-pt:  */
 347   { "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0,
 348     { 0, { (const PTR) 0 } },
 349     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 350 /* psw-s:  */
 351   { "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0,
 352     { 0, { (const PTR) 0 } },
 353     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 354 /* Rd: general register destination */
 355   { "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4,
 356     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RD] } },
 357     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 358 /* Rdm: general register destination */
 359   { "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3,
 360     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RDM] } },
 361     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 362 /* Rm: general register for memory */
 363   { "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3,
 364     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RM] } },
 365     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 366 /* Rs: general register source */
 367   { "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4,
 368     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RS] } },
 369     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 370 /* Rb: base register */
 371   { "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3,
 372     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RB] } },
 373     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 374 /* Rbj: base register for jump */
 375   { "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1,
 376     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RBJ] } },
 377     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 378 /* bcond2: branch condition opcode */
 379   { "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4,
 380     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2] } },
 381     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 382 /* ws2: word size opcode */
 383   { "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1,
 384     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2M] } },
 385     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 386 /* bcond5: branch condition opcode */
 387   { "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4,
 388     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP5] } },
 389     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 390 /* imm2: 2 bit unsigned immediate */
 391   { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
 392     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM2] } },
 393     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 394 /* imm3: 3 bit unsigned immediate */
 395   { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
 396     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3] } },
 397     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 398 /* imm3b: 3 bit unsigned immediate for bit tests */
 399   { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
 400     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3B] } },
 401     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 402 /* imm4: 4 bit unsigned immediate */
 403   { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
 404     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM4] } },
 405     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 406 /* imm8: 8 bit unsigned immediate */
 407   { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
 408     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
 409     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 410 /* imm8small: 8 bit unsigned immediate */
 411   { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
 412     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
 413     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 414 /* imm12: 12 bit signed immediate */
 415   { "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12,
 416     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM12] } },
 417     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 418 /* imm16: 16 bit immediate */
 419   { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
 420     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM16] } },
 421     { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
 422 /* lmem8: 8 bit unsigned immediate low memory */
 423   { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
 424     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_LMEM8] } },
 425     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 426 /* hmem8: 8 bit unsigned immediate high memory */
 427   { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
 428     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_HMEM8] } },
 429     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 430 /* rel8-2: 8 bit relative address */
 431   { "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8,
 432     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_2] } },
 433     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 434 /* rel8-4: 8 bit relative address */
 435   { "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8,
 436     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_4] } },
 437     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 438 /* rel12: 12 bit relative address */
 439   { "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12,
 440     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12] } },
 441     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 442 /* rel12a: 12 bit relative address */
 443   { "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11,
 444     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12A] } },
 445     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 446 /* abs24: 24 bit absolute address */
 447   { "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24,
 448     { 2, { (const PTR) &XSTORMY16_F_ABS24_MULTI_IFIELD[0] } },
 449     { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
 450 /* psw: program status word */
 451   { "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0,
 452     { 0, { (const PTR) 0 } },
 453     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 454 /* Rpsw: N0-N3 of the program status word */
 455   { "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0,
 456     { 0, { (const PTR) 0 } },
 457     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 458 /* sp: stack pointer */
 459   { "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0,
 460     { 0, { (const PTR) 0 } },
 461     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 462 /* R0: R0 */
 463   { "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0,
 464     { 0, { (const PTR) 0 } },
 465     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 466 /* R1: R1 */
 467   { "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0,
 468     { 0, { (const PTR) 0 } },
 469     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 470 /* R2: R2 */
 471   { "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0,
 472     { 0, { (const PTR) 0 } },
 473     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 474 /* R8: R8 */
 475   { "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0,
 476     { 0, { (const PTR) 0 } },
 477     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 478 /* sentinel */
 479   { 0, 0, 0, 0, 0,
 480     { 0, { (const PTR) 0 } },
 481     { 0, { { { (1<<MACH_BASE), 0 } } } } }
 482 };
 483
 484 #undef A
 485
 486
 487 /* The instruction table.  */
 488
 489 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 490 #define A(a) (1 << CGEN_INSN_##a)
 491
 492 static const CGEN_IBASE xstormy16_cgen_insn_table[MAX_INSNS] =
 493 {
 494   /* Special null first entry.
 495      A `num' value of zero is thus invalid.
 496      Also, the special `invalid' insn resides here.  */
 497   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 498 /* mov$ws2 $lmem8,#$imm16 */
 499   {
 500     XSTORMY16_INSN_MOVLMEMIMM, "movlmemimm", "mov", 32,
 501     { 0, { { { (1<<MACH_BASE), 0 } } } }
 502   },
 503 /* mov$ws2 $hmem8,#$imm16 */
 504   {
 505     XSTORMY16_INSN_MOVHMEMIMM, "movhmemimm", "mov", 32,
 506     { 0, { { { (1<<MACH_BASE), 0 } } } }
 507   },
 508 /* mov$ws2 $Rm,$lmem8 */
 509   {
 510     XSTORMY16_INSN_MOVLGRMEM, "movlgrmem", "mov", 16,
 511     { 0, { { { (1<<MACH_BASE), 0 } } } }
 512   },
 513 /* mov$ws2 $Rm,$hmem8 */
 514   {
 515     XSTORMY16_INSN_MOVHGRMEM, "movhgrmem", "mov", 16,
 516     { 0, { { { (1<<MACH_BASE), 0 } } } }
 517   },
 518 /* mov$ws2 $lmem8,$Rm */
 519   {
 520     XSTORMY16_INSN_MOVLMEMGR, "movlmemgr", "mov", 16,
 521     { 0, { { { (1<<MACH_BASE), 0 } } } }
 522   },
 523 /* mov$ws2 $hmem8,$Rm */
 524   {
 525     XSTORMY16_INSN_MOVHMEMGR, "movhmemgr", "mov", 16,
 526     { 0, { { { (1<<MACH_BASE), 0 } } } }
 527   },
 528 /* mov$ws2 $Rdm,($Rs) */
 529   {
 530     XSTORMY16_INSN_MOVGRGRI, "movgrgri", "mov", 16,
 531     { 0, { { { (1<<MACH_BASE), 0 } } } }
 532   },
 533 /* mov$ws2 $Rdm,($Rs++) */
 534   {
 535     XSTORMY16_INSN_MOVGRGRIPOSTINC, "movgrgripostinc", "mov", 16,
 536     { 0, { { { (1<<MACH_BASE), 0 } } } }
 537   },
 538 /* mov$ws2 $Rdm,(--$Rs) */
 539   {
 540     XSTORMY16_INSN_MOVGRGRIPREDEC, "movgrgripredec", "mov", 16,
 541     { 0, { { { (1<<MACH_BASE), 0 } } } }
 542   },
 543 /* mov$ws2 ($Rs),$Rdm */
 544   {
 545     XSTORMY16_INSN_MOVGRIGR, "movgrigr", "mov", 16,
 546     { 0, { { { (1<<MACH_BASE), 0 } } } }
 547   },
 548 /* mov$ws2 ($Rs++),$Rdm */
 549   {
 550     XSTORMY16_INSN_MOVGRIPOSTINCGR, "movgripostincgr", "mov", 16,
 551     { 0, { { { (1<<MACH_BASE), 0 } } } }
 552   },
 553 /* mov$ws2 (--$Rs),$Rdm */
 554   {
 555     XSTORMY16_INSN_MOVGRIPREDECGR, "movgripredecgr", "mov", 16,
 556     { 0, { { { (1<<MACH_BASE), 0 } } } }
 557   },
 558 /* mov$ws2 $Rdm,($Rs,$imm12) */
 559   {
 560     XSTORMY16_INSN_MOVGRGRII, "movgrgrii", "mov", 32,
 561     { 0, { { { (1<<MACH_BASE), 0 } } } }
 562   },
 563 /* mov$ws2 $Rdm,($Rs++,$imm12) */
 564   {
 565     XSTORMY16_INSN_MOVGRGRIIPOSTINC, "movgrgriipostinc", "mov", 32,
 566     { 0, { { { (1<<MACH_BASE), 0 } } } }
 567   },
 568 /* mov$ws2 $Rdm,(--$Rs,$imm12) */
 569   {
 570     XSTORMY16_INSN_MOVGRGRIIPREDEC, "movgrgriipredec", "mov", 32,
 571     { 0, { { { (1<<MACH_BASE), 0 } } } }
 572   },
 573 /* mov$ws2 ($Rs,$imm12),$Rdm */
 574   {
 575     XSTORMY16_INSN_MOVGRIIGR, "movgriigr", "mov", 32,
 576     { 0, { { { (1<<MACH_BASE), 0 } } } }
 577   },
 578 /* mov$ws2 ($Rs++,$imm12),$Rdm */
 579   {
 580     XSTORMY16_INSN_MOVGRIIPOSTINCGR, "movgriipostincgr", "mov", 32,
 581     { 0, { { { (1<<MACH_BASE), 0 } } } }
 582   },
 583 /* mov$ws2 (--$Rs,$imm12),$Rdm */
 584   {
 585     XSTORMY16_INSN_MOVGRIIPREDECGR, "movgriipredecgr", "mov", 32,
 586     { 0, { { { (1<<MACH_BASE), 0 } } } }
 587   },
 588 /* mov $Rd,$Rs */
 589   {
 590     XSTORMY16_INSN_MOVGRGR, "movgrgr", "mov", 16,
 591     { 0, { { { (1<<MACH_BASE), 0 } } } }
 592   },
 593 /* mov.w Rx,#$imm8 */
 594   {
 595     XSTORMY16_INSN_MOVWIMM8, "movwimm8", "mov.w", 16,
 596     { 0, { { { (1<<MACH_BASE), 0 } } } }
 597   },
 598 /* mov.w $Rm,#$imm8small */
 599   {
 600     XSTORMY16_INSN_MOVWGRIMM8, "movwgrimm8", "mov.w", 16,
 601     { 0, { { { (1<<MACH_BASE), 0 } } } }
 602   },
 603 /* mov.w $Rd,#$imm16 */
 604   {
 605     XSTORMY16_INSN_MOVWGRIMM16, "movwgrimm16", "mov.w", 32,
 606     { 0, { { { (1<<MACH_BASE), 0 } } } }
 607   },
 608 /* mov.b $Rd,RxL */
 609   {
 610     XSTORMY16_INSN_MOVLOWGR, "movlowgr", "mov.b", 16,
 611     { 0, { { { (1<<MACH_BASE), 0 } } } }
 612   },
 613 /* mov.b $Rd,RxH */
 614   {
 615     XSTORMY16_INSN_MOVHIGHGR, "movhighgr", "mov.b", 16,
 616     { 0, { { { (1<<MACH_BASE), 0 } } } }
 617   },
 618 /* movf$ws2 $Rdm,($Rs) */
 619   {
 620     XSTORMY16_INSN_MOVFGRGRI, "movfgrgri", "movf", 16,
 621     { 0, { { { (1<<MACH_BASE), 0 } } } }
 622   },
 623 /* movf$ws2 $Rdm,($Rs++) */
 624   {
 625     XSTORMY16_INSN_MOVFGRGRIPOSTINC, "movfgrgripostinc", "movf", 16,
 626     { 0, { { { (1<<MACH_BASE), 0 } } } }
 627   },
 628 /* movf$ws2 $Rdm,(--$Rs) */
 629   {
 630     XSTORMY16_INSN_MOVFGRGRIPREDEC, "movfgrgripredec", "movf", 16,
 631     { 0, { { { (1<<MACH_BASE), 0 } } } }
 632   },
 633 /* movf$ws2 ($Rs),$Rdm */
 634   {
 635     XSTORMY16_INSN_MOVFGRIGR, "movfgrigr", "movf", 16,
 636     { 0, { { { (1<<MACH_BASE), 0 } } } }
 637   },
 638 /* movf$ws2 ($Rs++),$Rdm */
 639   {
 640     XSTORMY16_INSN_MOVFGRIPOSTINCGR, "movfgripostincgr", "movf", 16,
 641     { 0, { { { (1<<MACH_BASE), 0 } } } }
 642   },
 643 /* movf$ws2 (--$Rs),$Rdm */
 644   {
 645     XSTORMY16_INSN_MOVFGRIPREDECGR, "movfgripredecgr", "movf", 16,
 646     { 0, { { { (1<<MACH_BASE), 0 } } } }
 647   },
 648 /* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */
 649   {
 650     XSTORMY16_INSN_MOVFGRGRII, "movfgrgrii", "movf", 32,
 651     { 0, { { { (1<<MACH_BASE), 0 } } } }
 652   },
 653 /* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */
 654   {
 655     XSTORMY16_INSN_MOVFGRGRIIPOSTINC, "movfgrgriipostinc", "movf", 32,
 656     { 0, { { { (1<<MACH_BASE), 0 } } } }
 657   },
 658 /* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */
 659   {
 660     XSTORMY16_INSN_MOVFGRGRIIPREDEC, "movfgrgriipredec", "movf", 32,
 661     { 0, { { { (1<<MACH_BASE), 0 } } } }
 662   },
 663 /* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */
 664   {
 665     XSTORMY16_INSN_MOVFGRIIGR, "movfgriigr", "movf", 32,
 666     { 0, { { { (1<<MACH_BASE), 0 } } } }
 667   },
 668 /* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */
 669   {
 670     XSTORMY16_INSN_MOVFGRIIPOSTINCGR, "movfgriipostincgr", "movf", 32,
 671     { 0, { { { (1<<MACH_BASE), 0 } } } }
 672   },
 673 /* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */
 674   {
 675     XSTORMY16_INSN_MOVFGRIIPREDECGR, "movfgriipredecgr", "movf", 32,
 676     { 0, { { { (1<<MACH_BASE), 0 } } } }
 677   },
 678 /* mask $Rd,$Rs */
 679   {
 680     XSTORMY16_INSN_MASKGRGR, "maskgrgr", "mask", 16,
 681     { 0, { { { (1<<MACH_BASE), 0 } } } }
 682   },
 683 /* mask $Rd,#$imm16 */
 684   {
 685     XSTORMY16_INSN_MASKGRIMM16, "maskgrimm16", "mask", 32,
 686     { 0, { { { (1<<MACH_BASE), 0 } } } }
 687   },
 688 /* push $Rd */
 689   {
 690     XSTORMY16_INSN_PUSHGR, "pushgr", "push", 16,
 691     { 0, { { { (1<<MACH_BASE), 0 } } } }
 692   },
 693 /* pop $Rd */
 694   {
 695     XSTORMY16_INSN_POPGR, "popgr", "pop", 16,
 696     { 0, { { { (1<<MACH_BASE), 0 } } } }
 697   },
 698 /* swpn $Rd */
 699   {
 700     XSTORMY16_INSN_SWPN, "swpn", "swpn", 16,
 701     { 0, { { { (1<<MACH_BASE), 0 } } } }
 702   },
 703 /* swpb $Rd */
 704   {
 705     XSTORMY16_INSN_SWPB, "swpb", "swpb", 16,
 706     { 0, { { { (1<<MACH_BASE), 0 } } } }
 707   },
 708 /* swpw $Rd,$Rs */
 709   {
 710     XSTORMY16_INSN_SWPW, "swpw", "swpw", 16,
 711     { 0, { { { (1<<MACH_BASE), 0 } } } }
 712   },
 713 /* and $Rd,$Rs */
 714   {
 715     XSTORMY16_INSN_ANDGRGR, "andgrgr", "and", 16,
 716     { 0, { { { (1<<MACH_BASE), 0 } } } }
 717   },
 718 /* and Rx,#$imm8 */
 719   {
 720     XSTORMY16_INSN_ANDIMM8, "andimm8", "and", 16,
 721     { 0, { { { (1<<MACH_BASE), 0 } } } }
 722   },
 723 /* and $Rd,#$imm16 */
 724   {
 725     XSTORMY16_INSN_ANDGRIMM16, "andgrimm16", "and", 32,
 726     { 0, { { { (1<<MACH_BASE), 0 } } } }
 727   },
 728 /* or $Rd,$Rs */
 729   {
 730     XSTORMY16_INSN_ORGRGR, "orgrgr", "or", 16,
 731     { 0, { { { (1<<MACH_BASE), 0 } } } }
 732   },
 733 /* or Rx,#$imm8 */
 734   {
 735     XSTORMY16_INSN_ORIMM8, "orimm8", "or", 16,
 736     { 0, { { { (1<<MACH_BASE), 0 } } } }
 737   },
 738 /* or $Rd,#$imm16 */
 739   {
 740     XSTORMY16_INSN_ORGRIMM16, "orgrimm16", "or", 32,
 741     { 0, { { { (1<<MACH_BASE), 0 } } } }
 742   },
 743 /* xor $Rd,$Rs */
 744   {
 745     XSTORMY16_INSN_XORGRGR, "xorgrgr", "xor", 16,
 746     { 0, { { { (1<<MACH_BASE), 0 } } } }
 747   },
 748 /* xor Rx,#$imm8 */
 749   {
 750     XSTORMY16_INSN_XORIMM8, "xorimm8", "xor", 16,
 751     { 0, { { { (1<<MACH_BASE), 0 } } } }
 752   },
 753 /* xor $Rd,#$imm16 */
 754   {
 755     XSTORMY16_INSN_XORGRIMM16, "xorgrimm16", "xor", 32,
 756     { 0, { { { (1<<MACH_BASE), 0 } } } }
 757   },
 758 /* not $Rd */
 759   {
 760     XSTORMY16_INSN_NOTGR, "notgr", "not", 16,
 761     { 0, { { { (1<<MACH_BASE), 0 } } } }
 762   },
 763 /* add $Rd,$Rs */
 764   {
 765     XSTORMY16_INSN_ADDGRGR, "addgrgr", "add", 16,
 766     { 0, { { { (1<<MACH_BASE), 0 } } } }
 767   },
 768 /* add $Rd,#$imm4 */
 769   {
 770     XSTORMY16_INSN_ADDGRIMM4, "addgrimm4", "add", 16,
 771     { 0, { { { (1<<MACH_BASE), 0 } } } }
 772   },
 773 /* add Rx,#$imm8 */
 774   {
 775     XSTORMY16_INSN_ADDIMM8, "addimm8", "add", 16,
 776     { 0, { { { (1<<MACH_BASE), 0 } } } }
 777   },
 778 /* add $Rd,#$imm16 */
 779   {
 780     XSTORMY16_INSN_ADDGRIMM16, "addgrimm16", "add", 32,
 781     { 0, { { { (1<<MACH_BASE), 0 } } } }
 782   },
 783 /* adc $Rd,$Rs */
 784   {
 785     XSTORMY16_INSN_ADCGRGR, "adcgrgr", "adc", 16,
 786     { 0, { { { (1<<MACH_BASE), 0 } } } }
 787   },
 788 /* adc $Rd,#$imm4 */
 789   {
 790     XSTORMY16_INSN_ADCGRIMM4, "adcgrimm4", "adc", 16,
 791     { 0, { { { (1<<MACH_BASE), 0 } } } }
 792   },
 793 /* adc Rx,#$imm8 */
 794   {
 795     XSTORMY16_INSN_ADCIMM8, "adcimm8", "adc", 16,
 796     { 0, { { { (1<<MACH_BASE), 0 } } } }
 797   },
 798 /* adc $Rd,#$imm16 */
 799   {
 800     XSTORMY16_INSN_ADCGRIMM16, "adcgrimm16", "adc", 32,
 801     { 0, { { { (1<<MACH_BASE), 0 } } } }
 802   },
 803 /* sub $Rd,$Rs */
 804   {
 805     XSTORMY16_INSN_SUBGRGR, "subgrgr", "sub", 16,
 806     { 0, { { { (1<<MACH_BASE), 0 } } } }
 807   },
 808 /* sub $Rd,#$imm4 */
 809   {
 810     XSTORMY16_INSN_SUBGRIMM4, "subgrimm4", "sub", 16,
 811     { 0, { { { (1<<MACH_BASE), 0 } } } }
 812   },
 813 /* sub Rx,#$imm8 */
 814   {
 815     XSTORMY16_INSN_SUBIMM8, "subimm8", "sub", 16,
 816     { 0, { { { (1<<MACH_BASE), 0 } } } }
 817   },
 818 /* sub $Rd,#$imm16 */
 819   {
 820     XSTORMY16_INSN_SUBGRIMM16, "subgrimm16", "sub", 32,
 821     { 0, { { { (1<<MACH_BASE), 0 } } } }
 822   },
 823 /* sbc $Rd,$Rs */
 824   {
 825     XSTORMY16_INSN_SBCGRGR, "sbcgrgr", "sbc", 16,
 826     { 0, { { { (1<<MACH_BASE), 0 } } } }
 827   },
 828 /* sbc $Rd,#$imm4 */
 829   {
 830     XSTORMY16_INSN_SBCGRIMM4, "sbcgrimm4", "sbc", 16,
 831     { 0, { { { (1<<MACH_BASE), 0 } } } }
 832   },
 833 /* sbc Rx,#$imm8 */
 834   {
 835     XSTORMY16_INSN_SBCGRIMM8, "sbcgrimm8", "sbc", 16,
 836     { 0, { { { (1<<MACH_BASE), 0 } } } }
 837   },
 838 /* sbc $Rd,#$imm16 */
 839   {
 840     XSTORMY16_INSN_SBCGRIMM16, "sbcgrimm16", "sbc", 32,
 841     { 0, { { { (1<<MACH_BASE), 0 } } } }
 842   },
 843 /* inc $Rd,#$imm2 */
 844   {
 845     XSTORMY16_INSN_INCGRIMM2, "incgrimm2", "inc", 16,
 846     { 0, { { { (1<<MACH_BASE), 0 } } } }
 847   },
 848 /* dec $Rd,#$imm2 */
 849   {
 850     XSTORMY16_INSN_DECGRIMM2, "decgrimm2", "dec", 16,
 851     { 0, { { { (1<<MACH_BASE), 0 } } } }
 852   },
 853 /* rrc $Rd,$Rs */
 854   {
 855     XSTORMY16_INSN_RRCGRGR, "rrcgrgr", "rrc", 16,
 856     { 0, { { { (1<<MACH_BASE), 0 } } } }
 857   },
 858 /* rrc $Rd,#$imm4 */
 859   {
 860     XSTORMY16_INSN_RRCGRIMM4, "rrcgrimm4", "rrc", 16,
 861     { 0, { { { (1<<MACH_BASE), 0 } } } }
 862   },
 863 /* rlc $Rd,$Rs */
 864   {
 865     XSTORMY16_INSN_RLCGRGR, "rlcgrgr", "rlc", 16,
 866     { 0, { { { (1<<MACH_BASE), 0 } } } }
 867   },
 868 /* rlc $Rd,#$imm4 */
 869   {
 870     XSTORMY16_INSN_RLCGRIMM4, "rlcgrimm4", "rlc", 16,
 871     { 0, { { { (1<<MACH_BASE), 0 } } } }
 872   },
 873 /* shr $Rd,$Rs */
 874   {
 875     XSTORMY16_INSN_SHRGRGR, "shrgrgr", "shr", 16,
 876     { 0, { { { (1<<MACH_BASE), 0 } } } }
 877   },
 878 /* shr $Rd,#$imm4 */
 879   {
 880     XSTORMY16_INSN_SHRGRIMM, "shrgrimm", "shr", 16,
 881     { 0, { { { (1<<MACH_BASE), 0 } } } }
 882   },
 883 /* shl $Rd,$Rs */
 884   {
 885     XSTORMY16_INSN_SHLGRGR, "shlgrgr", "shl", 16,
 886     { 0, { { { (1<<MACH_BASE), 0 } } } }
 887   },
 888 /* shl $Rd,#$imm4 */
 889   {
 890     XSTORMY16_INSN_SHLGRIMM, "shlgrimm", "shl", 16,
 891     { 0, { { { (1<<MACH_BASE), 0 } } } }
 892   },
 893 /* asr $Rd,$Rs */
 894   {
 895     XSTORMY16_INSN_ASRGRGR, "asrgrgr", "asr", 16,
 896     { 0, { { { (1<<MACH_BASE), 0 } } } }
 897   },
 898 /* asr $Rd,#$imm4 */
 899   {
 900     XSTORMY16_INSN_ASRGRIMM, "asrgrimm", "asr", 16,
 901     { 0, { { { (1<<MACH_BASE), 0 } } } }
 902   },
 903 /* set1 $Rd,#$imm4 */
 904   {
 905     XSTORMY16_INSN_SET1GRIMM, "set1grimm", "set1", 16,
 906     { 0, { { { (1<<MACH_BASE), 0 } } } }
 907   },
 908 /* set1 $Rd,$Rs */
 909   {
 910     XSTORMY16_INSN_SET1GRGR, "set1grgr", "set1", 16,
 911     { 0, { { { (1<<MACH_BASE), 0 } } } }
 912   },
 913 /* set1 $lmem8,#$imm3 */
 914   {
 915     XSTORMY16_INSN_SET1LMEMIMM, "set1lmemimm", "set1", 16,
 916     { 0, { { { (1<<MACH_BASE), 0 } } } }
 917   },
 918 /* set1 $hmem8,#$imm3 */
 919   {
 920     XSTORMY16_INSN_SET1HMEMIMM, "set1hmemimm", "set1", 16,
 921     { 0, { { { (1<<MACH_BASE), 0 } } } }
 922   },
 923 /* clr1 $Rd,#$imm4 */
 924   {
 925     XSTORMY16_INSN_CLR1GRIMM, "clr1grimm", "clr1", 16,
 926     { 0, { { { (1<<MACH_BASE), 0 } } } }
 927   },
 928 /* clr1 $Rd,$Rs */
 929   {
 930     XSTORMY16_INSN_CLR1GRGR, "clr1grgr", "clr1", 16,
 931     { 0, { { { (1<<MACH_BASE), 0 } } } }
 932   },
 933 /* clr1 $lmem8,#$imm3 */
 934   {
 935     XSTORMY16_INSN_CLR1LMEMIMM, "clr1lmemimm", "clr1", 16,
 936     { 0, { { { (1<<MACH_BASE), 0 } } } }
 937   },
 938 /* clr1 $hmem8,#$imm3 */
 939   {
 940     XSTORMY16_INSN_CLR1HMEMIMM, "clr1hmemimm", "clr1", 16,
 941     { 0, { { { (1<<MACH_BASE), 0 } } } }
 942   },
 943 /* cbw $Rd */
 944   {
 945     XSTORMY16_INSN_CBWGR, "cbwgr", "cbw", 16,
 946     { 0, { { { (1<<MACH_BASE), 0 } } } }
 947   },
 948 /* rev $Rd */
 949   {
 950     XSTORMY16_INSN_REVGR, "revgr", "rev", 16,
 951     { 0, { { { (1<<MACH_BASE), 0 } } } }
 952   },
 953 /* b$bcond5 $Rd,$Rs,$rel12 */
 954   {
 955     XSTORMY16_INSN_BCCGRGR, "bccgrgr", "b", 32,
 956     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
 957   },
 958 /* b$bcond5 $Rm,#$imm8,$rel12 */
 959   {
 960     XSTORMY16_INSN_BCCGRIMM8, "bccgrimm8", "b", 32,
 961     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
 962   },
 963 /* b$bcond2 Rx,#$imm16,${rel8-4} */
 964   {
 965     XSTORMY16_INSN_BCCIMM16, "bccimm16", "b", 32,
 966     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
 967   },
 968 /* bn $Rd,#$imm4,$rel12 */
 969   {
 970     XSTORMY16_INSN_BNGRIMM4, "bngrimm4", "bn", 32,
 971     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
 972   },
 973 /* bn $Rd,$Rs,$rel12 */
 974   {
 975     XSTORMY16_INSN_BNGRGR, "bngrgr", "bn", 32,
 976     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
 977   },
 978 /* bn $lmem8,#$imm3b,$rel12 */
 979   {
 980     XSTORMY16_INSN_BNLMEMIMM, "bnlmemimm", "bn", 32,
 981     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
 982   },
 983 /* bn $hmem8,#$imm3b,$rel12 */
 984   {
 985     XSTORMY16_INSN_BNHMEMIMM, "bnhmemimm", "bn", 32,
 986     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
 987   },
 988 /* bp $Rd,#$imm4,$rel12 */
 989   {
 990     XSTORMY16_INSN_BPGRIMM4, "bpgrimm4", "bp", 32,
 991     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
 992   },
 993 /* bp $Rd,$Rs,$rel12 */
 994   {
 995     XSTORMY16_INSN_BPGRGR, "bpgrgr", "bp", 32,
 996     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
 997   },
 998 /* bp $lmem8,#$imm3b,$rel12 */
 999   {
1000     XSTORMY16_INSN_BPLMEMIMM, "bplmemimm", "bp", 32,
1001     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1002   },
1003 /* bp $hmem8,#$imm3b,$rel12 */
1004   {
1005     XSTORMY16_INSN_BPHMEMIMM, "bphmemimm", "bp", 32,
1006     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1007   },
1008 /* b$bcond2 ${rel8-2} */
1009   {
1010     XSTORMY16_INSN_BCC, "bcc", "b", 16,
1011     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1012   },
1013 /* br $Rd */
1014   {
1015     XSTORMY16_INSN_BGR, "bgr", "br", 16,
1016     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1017   },
1018 /* br $rel12a */
1019   {
1020     XSTORMY16_INSN_BR, "br", "br", 16,
1021     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1022   },
1023 /* jmp $Rbj,$Rd */
1024   {
1025     XSTORMY16_INSN_JMP, "jmp", "jmp", 16,
1026     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1027   },
1028 /* jmpf $abs24 */
1029   {
1030     XSTORMY16_INSN_JMPF, "jmpf", "jmpf", 32,
1031     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1032   },
1033 /* callr $Rd */
1034   {
1035     XSTORMY16_INSN_CALLRGR, "callrgr", "callr", 16,
1036     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1037   },
1038 /* callr $rel12a */
1039   {
1040     XSTORMY16_INSN_CALLRIMM, "callrimm", "callr", 16,
1041     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1042   },
1043 /* call $Rbj,$Rd */
1044   {
1045     XSTORMY16_INSN_CALLGR, "callgr", "call", 16,
1046     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1047   },
1048 /* callf $abs24 */
1049   {
1050     XSTORMY16_INSN_CALLFIMM, "callfimm", "callf", 32,
1051     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1052   },
1053 /* icallr $Rd */
1054   {
1055     XSTORMY16_INSN_ICALLRGR, "icallrgr", "icallr", 16,
1056     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1057   },
1058 /* icall $Rbj,$Rd */
1059   {
1060     XSTORMY16_INSN_ICALLGR, "icallgr", "icall", 16,
1061     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1062   },
1063 /* icallf $abs24 */
1064   {
1065     XSTORMY16_INSN_ICALLFIMM, "icallfimm", "icallf", 32,
1066     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1067   },
1068 /* iret */
1069   {
1070     XSTORMY16_INSN_IRET, "iret", "iret", 16,
1071     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1072   },
1073 /* ret */
1074   {
1075     XSTORMY16_INSN_RET, "ret", "ret", 16,
1076     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1077   },
1078 /* mul */
1079   {
1080     XSTORMY16_INSN_MUL, "mul", "mul", 16,
1081     { 0, { { { (1<<MACH_BASE), 0 } } } }
1082   },
1083 /* div */
1084   {
1085     XSTORMY16_INSN_DIV, "div", "div", 16,
1086     { 0, { { { (1<<MACH_BASE), 0 } } } }
1087   },
1088 /* sdiv */
1089   {
1090     XSTORMY16_INSN_SDIV, "sdiv", "sdiv", 16,
1091     { 0, { { { (1<<MACH_BASE), 0 } } } }
1092   },
1093 /* sdivlh */
1094   {
1095     XSTORMY16_INSN_SDIVLH, "sdivlh", "sdivlh", 16,
1096     { 0, { { { (1<<MACH_BASE), 0 } } } }
1097   },
1098 /* divlh */
1099   {
1100     XSTORMY16_INSN_DIVLH, "divlh", "divlh", 16,
1101     { 0, { { { (1<<MACH_BASE), 0 } } } }
1102   },
1103 /* reset */
1104   {
1105     XSTORMY16_INSN_RESET, "reset", "reset", 16,
1106     { 0, { { { (1<<MACH_BASE), 0 } } } }
1107   },
1108 /* nop */
1109   {
1110     XSTORMY16_INSN_NOP, "nop", "nop", 16,
1111     { 0, { { { (1<<MACH_BASE), 0 } } } }
1112   },
1113 /* halt */
1114   {
1115     XSTORMY16_INSN_HALT, "halt", "halt", 16,
1116     { 0, { { { (1<<MACH_BASE), 0 } } } }
1117   },
1118 /* hold */
1119   {
1120     XSTORMY16_INSN_HOLD, "hold", "hold", 16,
1121     { 0, { { { (1<<MACH_BASE), 0 } } } }
1122   },
1123 /* holdx */
1124   {
1125     XSTORMY16_INSN_HOLDX, "holdx", "holdx", 16,
1126     { 0, { { { (1<<MACH_BASE), 0 } } } }
1127   },
1128 /* brk */
1129   {
1130     XSTORMY16_INSN_BRK, "brk", "brk", 16,
1131     { 0, { { { (1<<MACH_BASE), 0 } } } }
1132   },
1133 /* --unused-- */
1134   {
1135     XSTORMY16_INSN_SYSCALL, "syscall", "--unused--", 16,
1136     { 0, { { { (1<<MACH_BASE), 0 } } } }
1137   },
1138 };
1139
1140 #undef OP
1141 #undef A
1142
1143 /* Initialize anything needed to be done once, before any cpu_open call.  */
1144
1145 static void
1146 init_tables (void)
1147 {
1148 }
1149
1150 #ifndef opcodes_error_handler
1151 #define opcodes_error_handler(...) \
1152   fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
1153 #endif
1154
1155 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1156 static void build_hw_table      (CGEN_CPU_TABLE *);
1157 static void build_ifield_table  (CGEN_CPU_TABLE *);
1158 static void build_operand_table (CGEN_CPU_TABLE *);
1159 static void build_insn_table    (CGEN_CPU_TABLE *);
1160 static void xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1161
1162 /* Subroutine of xstormy16_cgen_cpu_open to look up a mach via its bfd name.  */
1163
1164 static const CGEN_MACH *
1165 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1166 {
1167   while (table->name)
1168     {
1169       if (strcmp (name, table->bfd_name) == 0)
1170         return table;
1171       ++table;
1172     }
1173   return NULL;
1174 }
1175
1176 /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.  */
1177
1178 static void
1179 build_hw_table (CGEN_CPU_TABLE *cd)
1180 {
1181   int i;
1182   int machs = cd->machs;
1183   const CGEN_HW_ENTRY *init = & xstormy16_cgen_hw_table[0];
1184   /* MAX_HW is only an upper bound on the number of selected entries.
1185      However each entry is indexed by it's enum so there can be holes in
1186      the table.  */
1187   const CGEN_HW_ENTRY **selected =
1188     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1189
1190   cd->hw_table.init_entries = init;
1191   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1192   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1193   /* ??? For now we just use machs to determine which ones we want.  */
1194   for (i = 0; init[i].name != NULL; ++i)
1195     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1196         & machs)
1197       selected[init[i].type] = &init[i];
1198   cd->hw_table.entries = selected;
1199   cd->hw_table.num_entries = MAX_HW;
1200 }
1201
1202 /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.  */
1203
1204 static void
1205 build_ifield_table (CGEN_CPU_TABLE *cd)
1206 {
1207   cd->ifld_table = & xstormy16_cgen_ifld_table[0];
1208 }
1209
1210 /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.  */
1211
1212 static void
1213 build_operand_table (CGEN_CPU_TABLE *cd)
1214 {
1215   int i;
1216   int machs = cd->machs;
1217   const CGEN_OPERAND *init = & xstormy16_cgen_operand_table[0];
1218   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1219      However each entry is indexed by it's enum so there can be holes in
1220      the table.  */
1221   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1222
1223   cd->operand_table.init_entries = init;
1224   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1225   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1226   /* ??? For now we just use mach to determine which ones we want.  */
1227   for (i = 0; init[i].name != NULL; ++i)
1228     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1229         & machs)
1230       selected[init[i].type] = &init[i];
1231   cd->operand_table.entries = selected;
1232   cd->operand_table.num_entries = MAX_OPERANDS;
1233 }
1234
1235 /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.
1236    ??? This could leave out insns not supported by the specified mach/isa,
1237    but that would cause errors like "foo only supported by bar" to become
1238    "unknown insn", so for now we include all insns and require the app to
1239    do the checking later.
1240    ??? On the other hand, parsing of such insns may require their hardware or
1241    operand elements to be in the table [which they mightn't be].  */
1242
1243 static void
1244 build_insn_table (CGEN_CPU_TABLE *cd)
1245 {
1246   int i;
1247   const CGEN_IBASE *ib = & xstormy16_cgen_insn_table[0];
1248   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1249
1250   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1251   for (i = 0; i < MAX_INSNS; ++i)
1252     insns[i].base = &ib[i];
1253   cd->insn_table.init_entries = insns;
1254   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1255   cd->insn_table.num_init_entries = MAX_INSNS;
1256 }
1257
1258 /* Subroutine of xstormy16_cgen_cpu_open to rebuild the tables.  */
1259
1260 static void
1261 xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1262 {
1263   int i;
1264   CGEN_BITSET *isas = cd->isas;
1265   unsigned int machs = cd->machs;
1266
1267   cd->int_insn_p = CGEN_INT_INSN_P;
1268
1269   /* Data derived from the isa spec.  */
1270 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1271   cd->default_insn_bitsize = UNSET;
1272   cd->base_insn_bitsize = UNSET;
1273   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
1274   cd->max_insn_bitsize = 0;
1275   for (i = 0; i < MAX_ISAS; ++i)
1276     if (cgen_bitset_contains (isas, i))
1277       {
1278         const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i];
1279
1280         /* Default insn sizes of all selected isas must be
1281            equal or we set the result to 0, meaning "unknown".  */
1282         if (cd->default_insn_bitsize == UNSET)
1283           cd->default_insn_bitsize = isa->default_insn_bitsize;
1284         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1285           ; /* This is ok.  */
1286         else
1287           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1288
1289         /* Base insn sizes of all selected isas must be equal
1290            or we set the result to 0, meaning "unknown".  */
1291         if (cd->base_insn_bitsize == UNSET)
1292           cd->base_insn_bitsize = isa->base_insn_bitsize;
1293         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1294           ; /* This is ok.  */
1295         else
1296           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1297
1298         /* Set min,max insn sizes.  */
1299         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1300           cd->min_insn_bitsize = isa->min_insn_bitsize;
1301         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1302           cd->max_insn_bitsize = isa->max_insn_bitsize;
1303       }
1304
1305   /* Data derived from the mach spec.  */
1306   for (i = 0; i < MAX_MACHS; ++i)
1307     if (((1 << i) & machs) != 0)
1308       {
1309         const CGEN_MACH *mach = & xstormy16_cgen_mach_table[i];
1310
1311         if (mach->insn_chunk_bitsize != 0)
1312         {
1313           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1314             {
1315               opcodes_error_handler
1316                 (/* xgettext:c-format */
1317                  _("internal error: xstormy16_cgen_rebuild_tables: "
1318                    "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
1319                  cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1320               abort ();
1321             }
1322
1323           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1324         }
1325       }
1326
1327   /* Determine which hw elements are used by MACH.  */
1328   build_hw_table (cd);
1329
1330   /* Build the ifield table.  */
1331   build_ifield_table (cd);
1332
1333   /* Determine which operands are used by MACH/ISA.  */
1334   build_operand_table (cd);
1335
1336   /* Build the instruction table.  */
1337   build_insn_table (cd);
1338 }
1339
1340 /* Initialize a cpu table and return a descriptor.
1341    It's much like opening a file, and must be the first function called.
1342    The arguments are a set of (type/value) pairs, terminated with
1343    CGEN_CPU_OPEN_END.
1344
1345    Currently supported values:
1346    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1347    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1348    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1349    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1350    CGEN_CPU_OPEN_END:     terminates arguments
1351
1352    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1353    precluded.  */
1354
1355 CGEN_CPU_DESC
1356 xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1357 {
1358   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1359   static int init_p;
1360   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
1361   unsigned int machs = 0; /* 0 = "unspecified" */
1362   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1363   va_list ap;
1364
1365   if (! init_p)
1366     {
1367       init_tables ();
1368       init_p = 1;
1369     }
1370
1371   memset (cd, 0, sizeof (*cd));
1372
1373   va_start (ap, arg_type);
1374   while (arg_type != CGEN_CPU_OPEN_END)
1375     {
1376       switch (arg_type)
1377         {
1378         case CGEN_CPU_OPEN_ISAS :
1379           isas = va_arg (ap, CGEN_BITSET *);
1380           break;
1381         case CGEN_CPU_OPEN_MACHS :
1382           machs = va_arg (ap, unsigned int);
1383           break;
1384         case CGEN_CPU_OPEN_BFDMACH :
1385           {
1386             const char *name = va_arg (ap, const char *);
1387             const CGEN_MACH *mach =
1388               lookup_mach_via_bfd_name (xstormy16_cgen_mach_table, name);
1389
1390             if (mach != NULL)
1391               machs |= 1 << mach->num;
1392             break;
1393           }
1394         case CGEN_CPU_OPEN_ENDIAN :
1395           endian = va_arg (ap, enum cgen_endian);
1396           break;
1397         default :
1398           opcodes_error_handler
1399             (/* xgettext:c-format */
1400              _("internal error: xstormy16_cgen_cpu_open: "
1401                "unsupported argument `%d'"),
1402              arg_type);
1403           abort (); /* ??? return NULL? */
1404         }
1405       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1406     }
1407   va_end (ap);
1408
1409   /* Mach unspecified means "all".  */
1410   if (machs == 0)
1411     machs = (1 << MAX_MACHS) - 1;
1412   /* Base mach is always selected.  */
1413   machs |= 1;
1414   if (endian == CGEN_ENDIAN_UNKNOWN)
1415     {
1416       /* ??? If target has only one, could have a default.  */
1417       opcodes_error_handler
1418         (/* xgettext:c-format */
1419          _("internal error: xstormy16_cgen_cpu_open: no endianness specified"));
1420       abort ();
1421     }
1422
1423   cd->isas = cgen_bitset_copy (isas);
1424   cd->machs = machs;
1425   cd->endian = endian;
1426   /* FIXME: for the sparc case we can determine insn-endianness statically.
1427      The worry here is where both data and insn endian can be independently
1428      chosen, in which case this function will need another argument.
1429      Actually, will want to allow for more arguments in the future anyway.  */
1430   cd->insn_endian = endian;
1431
1432   /* Table (re)builder.  */
1433   cd->rebuild_tables = xstormy16_cgen_rebuild_tables;
1434   xstormy16_cgen_rebuild_tables (cd);
1435
1436   /* Default to not allowing signed overflow.  */
1437   cd->signed_overflow_ok_p = 0;
1438
1439   return (CGEN_CPU_DESC) cd;
1440 }
1441
1442 /* Cover fn to xstormy16_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1443    MACH_NAME is the bfd name of the mach.  */
1444
1445 CGEN_CPU_DESC
1446 xstormy16_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
1447 {
1448   return xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1449                                CGEN_CPU_OPEN_ENDIAN, endian,
1450                                CGEN_CPU_OPEN_END);
1451 }
1452
1453 /* Close a cpu table.
1454    ??? This can live in a machine independent file, but there's currently
1455    no place to put this file (there's no libcgen).  libopcodes is the wrong
1456    place as some simulator ports use this but they don't use libopcodes.  */
1457
1458 void
1459 xstormy16_cgen_cpu_close (CGEN_CPU_DESC cd)
1460 {
1461   unsigned int i;
1462   const CGEN_INSN *insns;
1463
1464   if (cd->macro_insn_table.init_entries)
1465     {
1466       insns = cd->macro_insn_table.init_entries;
1467       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1468         if (CGEN_INSN_RX ((insns)))
1469           regfree (CGEN_INSN_RX (insns));
1470     }
1471
1472   if (cd->insn_table.init_entries)
1473     {
1474       insns = cd->insn_table.init_entries;
1475       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1476         if (CGEN_INSN_RX (insns))
1477           regfree (CGEN_INSN_RX (insns));
1478     }
1479
1480   free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1481   free ((CGEN_INSN *) cd->insn_table.init_entries);
1482   free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1483   free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1484   free (cd);
1485 }
1486