Correct disassembly of dot product instructions.

Dot products deviate from the normal disassembly rules for lane indexed
instruction. Their canonical representation is in the form of:

v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote
that these instructions select 4x 1 byte elements instead of a single 1 byte
element.

Previously we were disassembling them following the normal rules, this patch
corrects the disassembly.

gas/

	PR gas/22559
	* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B.
	* gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly.

include/

	PR gas/22559
	* aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B.

opcodes/

	PR gas/22559
	* aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to
	AARCH64_OPND_QLF_S_4B
	* aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to
	AARCH64_OPND_QLF_S_4B
	* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
	* aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 608d39bd2696a7fe8209893279a8707699d39e30..525f771f0be89f5c66528ee610c3eb16744f590e 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2017-12-19  Tamar Christina  <tamar.christina@arm.com>
+
+       PR 22559
+       * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B.
+       * gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly.
+
 2017-12-19  Tamar Christina  <tamar.christina@arm.com>
 
        PR 22529

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 6b5179ee571403d3e4ce4bd8b220ccb77740b556..9e2cd505189715caada2ca721c14571c73e3f254 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4929,8 +4929,14 @@ vectype_to_qualifier (const struct vector_type_el *vectype)
   gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
 
   if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH))
-    /* Vector element register.  */
-    return AARCH64_OPND_QLF_S_B + vectype->type;
+    {
+      /* Special case S_4B.  */
+      if (vectype->type == NT_b && vectype->width == 4)
+       return AARCH64_OPND_QLF_S_4B;
+
+      /* Vector element register.  */
+      return AARCH64_OPND_QLF_S_B + vectype->type;
+    }
   else
     {
       /* Vector register.  */

diff --git a/gas/testsuite/gas/aarch64/dotproduct.d b/gas/testsuite/gas/aarch64/dotproduct.d
index 58669ff3476a10ac8289b5099d1910dbe1933d18..54ac62be634890f57d6c1d84d57db42629359ca9 100644 (file)
--- a/gas/testsuite/gas/aarch64/dotproduct.d
+++ b/gas/testsuite/gas/aarch64/dotproduct.d
@@ -114,435 +114,435 @@ Disassembly of section \.text:
 [^:]+:\s+4e8096d6      sdot    v22.4s, v22.16b, v0.16b
 [^:]+:\s+4e8b96d6      sdot    v22.4s, v22.16b, v11.16b
 [^:]+:\s+4e9696d6      sdot    v22.4s, v22.16b, v22.16b
-[^:]+:\s+2f80e000      udot    v0.2s, v0.8b, v0.b\[0\]
-[^:]+:\s+2f8be000      udot    v0.2s, v0.8b, v11.b\[0\]
-[^:]+:\s+2f96e000      udot    v0.2s, v0.8b, v22.b\[0\]
-[^:]+:\s+2fa0e000      udot    v0.2s, v0.8b, v0.b\[1\]
-[^:]+:\s+2fabe000      udot    v0.2s, v0.8b, v11.b\[1\]
-[^:]+:\s+2fb6e000      udot    v0.2s, v0.8b, v22.b\[1\]
-[^:]+:\s+2f80e800      udot    v0.2s, v0.8b, v0.b\[2\]
-[^:]+:\s+2f8be800      udot    v0.2s, v0.8b, v11.b\[2\]
-[^:]+:\s+2f96e800      udot    v0.2s, v0.8b, v22.b\[2\]
-[^:]+:\s+2fa0e800      udot    v0.2s, v0.8b, v0.b\[3\]
-[^:]+:\s+2fabe800      udot    v0.2s, v0.8b, v11.b\[3\]
-[^:]+:\s+2fb6e800      udot    v0.2s, v0.8b, v22.b\[3\]
-[^:]+:\s+2f80e160      udot    v0.2s, v11.8b, v0.b\[0\]
-[^:]+:\s+2f8be160      udot    v0.2s, v11.8b, v11.b\[0\]
-[^:]+:\s+2f96e160      udot    v0.2s, v11.8b, v22.b\[0\]
-[^:]+:\s+2fa0e160      udot    v0.2s, v11.8b, v0.b\[1\]
-[^:]+:\s+2fabe160      udot    v0.2s, v11.8b, v11.b\[1\]
-[^:]+:\s+2fb6e160      udot    v0.2s, v11.8b, v22.b\[1\]
-[^:]+:\s+2f80e960      udot    v0.2s, v11.8b, v0.b\[2\]
-[^:]+:\s+2f8be960      udot    v0.2s, v11.8b, v11.b\[2\]
-[^:]+:\s+2f96e960      udot    v0.2s, v11.8b, v22.b\[2\]
-[^:]+:\s+2fa0e960      udot    v0.2s, v11.8b, v0.b\[3\]
-[^:]+:\s+2fabe960      udot    v0.2s, v11.8b, v11.b\[3\]
-[^:]+:\s+2fb6e960      udot    v0.2s, v11.8b, v22.b\[3\]
-[^:]+:\s+2f80e2c0      udot    v0.2s, v22.8b, v0.b\[0\]
-[^:]+:\s+2f8be2c0      udot    v0.2s, v22.8b, v11.b\[0\]
-[^:]+:\s+2f96e2c0      udot    v0.2s, v22.8b, v22.b\[0\]
-[^:]+:\s+2fa0e2c0      udot    v0.2s, v22.8b, v0.b\[1\]
-[^:]+:\s+2fabe2c0      udot    v0.2s, v22.8b, v11.b\[1\]
-[^:]+:\s+2fb6e2c0      udot    v0.2s, v22.8b, v22.b\[1\]
-[^:]+:\s+2f80eac0      udot    v0.2s, v22.8b, v0.b\[2\]
-[^:]+:\s+2f8beac0      udot    v0.2s, v22.8b, v11.b\[2\]
-[^:]+:\s+2f96eac0      udot    v0.2s, v22.8b, v22.b\[2\]
-[^:]+:\s+2fa0eac0      udot    v0.2s, v22.8b, v0.b\[3\]
-[^:]+:\s+2fabeac0      udot    v0.2s, v22.8b, v11.b\[3\]
-[^:]+:\s+2fb6eac0      udot    v0.2s, v22.8b, v22.b\[3\]
-[^:]+:\s+2f80e00b      udot    v11.2s, v0.8b, v0.b\[0\]
-[^:]+:\s+2f8be00b      udot    v11.2s, v0.8b, v11.b\[0\]
-[^:]+:\s+2f96e00b      udot    v11.2s, v0.8b, v22.b\[0\]
-[^:]+:\s+2fa0e00b      udot    v11.2s, v0.8b, v0.b\[1\]
-[^:]+:\s+2fabe00b      udot    v11.2s, v0.8b, v11.b\[1\]
-[^:]+:\s+2fb6e00b      udot    v11.2s, v0.8b, v22.b\[1\]
-[^:]+:\s+2f80e80b      udot    v11.2s, v0.8b, v0.b\[2\]
-[^:]+:\s+2f8be80b      udot    v11.2s, v0.8b, v11.b\[2\]
-[^:]+:\s+2f96e80b      udot    v11.2s, v0.8b, v22.b\[2\]
-[^:]+:\s+2fa0e80b      udot    v11.2s, v0.8b, v0.b\[3\]
-[^:]+:\s+2fabe80b      udot    v11.2s, v0.8b, v11.b\[3\]
-[^:]+:\s+2fb6e80b      udot    v11.2s, v0.8b, v22.b\[3\]
-[^:]+:\s+2f80e16b      udot    v11.2s, v11.8b, v0.b\[0\]
-[^:]+:\s+2f8be16b      udot    v11.2s, v11.8b, v11.b\[0\]
-[^:]+:\s+2f96e16b      udot    v11.2s, v11.8b, v22.b\[0\]
-[^:]+:\s+2fa0e16b      udot    v11.2s, v11.8b, v0.b\[1\]
-[^:]+:\s+2fabe16b      udot    v11.2s, v11.8b, v11.b\[1\]
-[^:]+:\s+2fb6e16b      udot    v11.2s, v11.8b, v22.b\[1\]
-[^:]+:\s+2f80e96b      udot    v11.2s, v11.8b, v0.b\[2\]
-[^:]+:\s+2f8be96b      udot    v11.2s, v11.8b, v11.b\[2\]
-[^:]+:\s+2f96e96b      udot    v11.2s, v11.8b, v22.b\[2\]
-[^:]+:\s+2fa0e96b      udot    v11.2s, v11.8b, v0.b\[3\]
-[^:]+:\s+2fabe96b      udot    v11.2s, v11.8b, v11.b\[3\]
-[^:]+:\s+2fb6e96b      udot    v11.2s, v11.8b, v22.b\[3\]
-[^:]+:\s+2f80e2cb      udot    v11.2s, v22.8b, v0.b\[0\]
-[^:]+:\s+2f8be2cb      udot    v11.2s, v22.8b, v11.b\[0\]
-[^:]+:\s+2f96e2cb      udot    v11.2s, v22.8b, v22.b\[0\]
-[^:]+:\s+2fa0e2cb      udot    v11.2s, v22.8b, v0.b\[1\]
-[^:]+:\s+2fabe2cb      udot    v11.2s, v22.8b, v11.b\[1\]
-[^:]+:\s+2fb6e2cb      udot    v11.2s, v22.8b, v22.b\[1\]
-[^:]+:\s+2f80eacb      udot    v11.2s, v22.8b, v0.b\[2\]
-[^:]+:\s+2f8beacb      udot    v11.2s, v22.8b, v11.b\[2\]
-[^:]+:\s+2f96eacb      udot    v11.2s, v22.8b, v22.b\[2\]
-[^:]+:\s+2fa0eacb      udot    v11.2s, v22.8b, v0.b\[3\]
-[^:]+:\s+2fabeacb      udot    v11.2s, v22.8b, v11.b\[3\]
-[^:]+:\s+2fb6eacb      udot    v11.2s, v22.8b, v22.b\[3\]
-[^:]+:\s+2f80e016      udot    v22.2s, v0.8b, v0.b\[0\]
-[^:]+:\s+2f8be016      udot    v22.2s, v0.8b, v11.b\[0\]
-[^:]+:\s+2f96e016      udot    v22.2s, v0.8b, v22.b\[0\]
-[^:]+:\s+2fa0e016      udot    v22.2s, v0.8b, v0.b\[1\]
-[^:]+:\s+2fabe016      udot    v22.2s, v0.8b, v11.b\[1\]
-[^:]+:\s+2fb6e016      udot    v22.2s, v0.8b, v22.b\[1\]
-[^:]+:\s+2f80e816      udot    v22.2s, v0.8b, v0.b\[2\]
-[^:]+:\s+2f8be816      udot    v22.2s, v0.8b, v11.b\[2\]
-[^:]+:\s+2f96e816      udot    v22.2s, v0.8b, v22.b\[2\]
-[^:]+:\s+2fa0e816      udot    v22.2s, v0.8b, v0.b\[3\]
-[^:]+:\s+2fabe816      udot    v22.2s, v0.8b, v11.b\[3\]
-[^:]+:\s+2fb6e816      udot    v22.2s, v0.8b, v22.b\[3\]
-[^:]+:\s+2f80e176      udot    v22.2s, v11.8b, v0.b\[0\]
-[^:]+:\s+2f8be176      udot    v22.2s, v11.8b, v11.b\[0\]
-[^:]+:\s+2f96e176      udot    v22.2s, v11.8b, v22.b\[0\]
-[^:]+:\s+2fa0e176      udot    v22.2s, v11.8b, v0.b\[1\]
-[^:]+:\s+2fabe176      udot    v22.2s, v11.8b, v11.b\[1\]
-[^:]+:\s+2fb6e176      udot    v22.2s, v11.8b, v22.b\[1\]
-[^:]+:\s+2f80e976      udot    v22.2s, v11.8b, v0.b\[2\]
-[^:]+:\s+2f8be976      udot    v22.2s, v11.8b, v11.b\[2\]
-[^:]+:\s+2f96e976      udot    v22.2s, v11.8b, v22.b\[2\]
-[^:]+:\s+2fa0e976      udot    v22.2s, v11.8b, v0.b\[3\]
-[^:]+:\s+2fabe976      udot    v22.2s, v11.8b, v11.b\[3\]
-[^:]+:\s+2fb6e976      udot    v22.2s, v11.8b, v22.b\[3\]
-[^:]+:\s+2f80e2d6      udot    v22.2s, v22.8b, v0.b\[0\]
-[^:]+:\s+2f8be2d6      udot    v22.2s, v22.8b, v11.b\[0\]
-[^:]+:\s+2f96e2d6      udot    v22.2s, v22.8b, v22.b\[0\]
-[^:]+:\s+2fa0e2d6      udot    v22.2s, v22.8b, v0.b\[1\]
-[^:]+:\s+2fabe2d6      udot    v22.2s, v22.8b, v11.b\[1\]
-[^:]+:\s+2fb6e2d6      udot    v22.2s, v22.8b, v22.b\[1\]
-[^:]+:\s+2f80ead6      udot    v22.2s, v22.8b, v0.b\[2\]
-[^:]+:\s+2f8bead6      udot    v22.2s, v22.8b, v11.b\[2\]
-[^:]+:\s+2f96ead6      udot    v22.2s, v22.8b, v22.b\[2\]
-[^:]+:\s+2fa0ead6      udot    v22.2s, v22.8b, v0.b\[3\]
-[^:]+:\s+2fabead6      udot    v22.2s, v22.8b, v11.b\[3\]
-[^:]+:\s+2fb6ead6      udot    v22.2s, v22.8b, v22.b\[3\]
-[^:]+:\s+0f80e000      sdot    v0.2s, v0.8b, v0.b\[0\]
-[^:]+:\s+0f8be000      sdot    v0.2s, v0.8b, v11.b\[0\]
-[^:]+:\s+0f96e000      sdot    v0.2s, v0.8b, v22.b\[0\]
-[^:]+:\s+0fa0e000      sdot    v0.2s, v0.8b, v0.b\[1\]
-[^:]+:\s+0fabe000      sdot    v0.2s, v0.8b, v11.b\[1\]
-[^:]+:\s+0fb6e000      sdot    v0.2s, v0.8b, v22.b\[1\]
-[^:]+:\s+0f80e800      sdot    v0.2s, v0.8b, v0.b\[2\]
-[^:]+:\s+0f8be800      sdot    v0.2s, v0.8b, v11.b\[2\]
-[^:]+:\s+0f96e800      sdot    v0.2s, v0.8b, v22.b\[2\]
-[^:]+:\s+0fa0e800      sdot    v0.2s, v0.8b, v0.b\[3\]
-[^:]+:\s+0fabe800      sdot    v0.2s, v0.8b, v11.b\[3\]
-[^:]+:\s+0fb6e800      sdot    v0.2s, v0.8b, v22.b\[3\]
-[^:]+:\s+0f80e160      sdot    v0.2s, v11.8b, v0.b\[0\]
-[^:]+:\s+0f8be160      sdot    v0.2s, v11.8b, v11.b\[0\]
-[^:]+:\s+0f96e160      sdot    v0.2s, v11.8b, v22.b\[0\]
-[^:]+:\s+0fa0e160      sdot    v0.2s, v11.8b, v0.b\[1\]
-[^:]+:\s+0fabe160      sdot    v0.2s, v11.8b, v11.b\[1\]
-[^:]+:\s+0fb6e160      sdot    v0.2s, v11.8b, v22.b\[1\]
-[^:]+:\s+0f80e960      sdot    v0.2s, v11.8b, v0.b\[2\]
-[^:]+:\s+0f8be960      sdot    v0.2s, v11.8b, v11.b\[2\]
-[^:]+:\s+0f96e960      sdot    v0.2s, v11.8b, v22.b\[2\]
-[^:]+:\s+0fa0e960      sdot    v0.2s, v11.8b, v0.b\[3\]
-[^:]+:\s+0fabe960      sdot    v0.2s, v11.8b, v11.b\[3\]
-[^:]+:\s+0fb6e960      sdot    v0.2s, v11.8b, v22.b\[3\]
-[^:]+:\s+0f80e2c0      sdot    v0.2s, v22.8b, v0.b\[0\]
-[^:]+:\s+0f8be2c0      sdot    v0.2s, v22.8b, v11.b\[0\]
-[^:]+:\s+0f96e2c0      sdot    v0.2s, v22.8b, v22.b\[0\]
-[^:]+:\s+0fa0e2c0      sdot    v0.2s, v22.8b, v0.b\[1\]
-[^:]+:\s+0fabe2c0      sdot    v0.2s, v22.8b, v11.b\[1\]
-[^:]+:\s+0fb6e2c0      sdot    v0.2s, v22.8b, v22.b\[1\]
-[^:]+:\s+0f80eac0      sdot    v0.2s, v22.8b, v0.b\[2\]
-[^:]+:\s+0f8beac0      sdot    v0.2s, v22.8b, v11.b\[2\]
-[^:]+:\s+0f96eac0      sdot    v0.2s, v22.8b, v22.b\[2\]
-[^:]+:\s+0fa0eac0      sdot    v0.2s, v22.8b, v0.b\[3\]
-[^:]+:\s+0fabeac0      sdot    v0.2s, v22.8b, v11.b\[3\]
-[^:]+:\s+0fb6eac0      sdot    v0.2s, v22.8b, v22.b\[3\]
-[^:]+:\s+0f80e00b      sdot    v11.2s, v0.8b, v0.b\[0\]
-[^:]+:\s+0f8be00b      sdot    v11.2s, v0.8b, v11.b\[0\]
-[^:]+:\s+0f96e00b      sdot    v11.2s, v0.8b, v22.b\[0\]
-[^:]+:\s+0fa0e00b      sdot    v11.2s, v0.8b, v0.b\[1\]
-[^:]+:\s+0fabe00b      sdot    v11.2s, v0.8b, v11.b\[1\]
-[^:]+:\s+0fb6e00b      sdot    v11.2s, v0.8b, v22.b\[1\]
-[^:]+:\s+0f80e80b      sdot    v11.2s, v0.8b, v0.b\[2\]
-[^:]+:\s+0f8be80b      sdot    v11.2s, v0.8b, v11.b\[2\]
-[^:]+:\s+0f96e80b      sdot    v11.2s, v0.8b, v22.b\[2\]
-[^:]+:\s+0fa0e80b      sdot    v11.2s, v0.8b, v0.b\[3\]
-[^:]+:\s+0fabe80b      sdot    v11.2s, v0.8b, v11.b\[3\]
-[^:]+:\s+0fb6e80b      sdot    v11.2s, v0.8b, v22.b\[3\]
-[^:]+:\s+0f80e16b      sdot    v11.2s, v11.8b, v0.b\[0\]
-[^:]+:\s+0f8be16b      sdot    v11.2s, v11.8b, v11.b\[0\]
-[^:]+:\s+0f96e16b      sdot    v11.2s, v11.8b, v22.b\[0\]
-[^:]+:\s+0fa0e16b      sdot    v11.2s, v11.8b, v0.b\[1\]
-[^:]+:\s+0fabe16b      sdot    v11.2s, v11.8b, v11.b\[1\]
-[^:]+:\s+0fb6e16b      sdot    v11.2s, v11.8b, v22.b\[1\]
-[^:]+:\s+0f80e96b      sdot    v11.2s, v11.8b, v0.b\[2\]
-[^:]+:\s+0f8be96b      sdot    v11.2s, v11.8b, v11.b\[2\]
-[^:]+:\s+0f96e96b      sdot    v11.2s, v11.8b, v22.b\[2\]
-[^:]+:\s+0fa0e96b      sdot    v11.2s, v11.8b, v0.b\[3\]
-[^:]+:\s+0fabe96b      sdot    v11.2s, v11.8b, v11.b\[3\]
-[^:]+:\s+0fb6e96b      sdot    v11.2s, v11.8b, v22.b\[3\]
-[^:]+:\s+0f80e2cb      sdot    v11.2s, v22.8b, v0.b\[0\]
-[^:]+:\s+0f8be2cb      sdot    v11.2s, v22.8b, v11.b\[0\]
-[^:]+:\s+0f96e2cb      sdot    v11.2s, v22.8b, v22.b\[0\]
-[^:]+:\s+0fa0e2cb      sdot    v11.2s, v22.8b, v0.b\[1\]
-[^:]+:\s+0fabe2cb      sdot    v11.2s, v22.8b, v11.b\[1\]
-[^:]+:\s+0fb6e2cb      sdot    v11.2s, v22.8b, v22.b\[1\]
-[^:]+:\s+0f80eacb      sdot    v11.2s, v22.8b, v0.b\[2\]
-[^:]+:\s+0f8beacb      sdot    v11.2s, v22.8b, v11.b\[2\]
-[^:]+:\s+0f96eacb      sdot    v11.2s, v22.8b, v22.b\[2\]
-[^:]+:\s+0fa0eacb      sdot    v11.2s, v22.8b, v0.b\[3\]
-[^:]+:\s+0fabeacb      sdot    v11.2s, v22.8b, v11.b\[3\]
-[^:]+:\s+0fb6eacb      sdot    v11.2s, v22.8b, v22.b\[3\]
-[^:]+:\s+0f80e016      sdot    v22.2s, v0.8b, v0.b\[0\]
-[^:]+:\s+0f8be016      sdot    v22.2s, v0.8b, v11.b\[0\]
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+[^:]+:\s+4fa0e2cb      sdot    v11.4s, v22.16b, v0.4b\[1\]
+[^:]+:\s+4fabe2cb      sdot    v11.4s, v22.16b, v11.4b\[1\]
+[^:]+:\s+4fb6e2cb      sdot    v11.4s, v22.16b, v22.4b\[1\]
+[^:]+:\s+4f80eacb      sdot    v11.4s, v22.16b, v0.4b\[2\]
+[^:]+:\s+4f8beacb      sdot    v11.4s, v22.16b, v11.4b\[2\]
+[^:]+:\s+4f96eacb      sdot    v11.4s, v22.16b, v22.4b\[2\]
+[^:]+:\s+4fa0eacb      sdot    v11.4s, v22.16b, v0.4b\[3\]
+[^:]+:\s+4fabeacb      sdot    v11.4s, v22.16b, v11.4b\[3\]
+[^:]+:\s+4fb6eacb      sdot    v11.4s, v22.16b, v22.4b\[3\]
+[^:]+:\s+4f80e016      sdot    v22.4s, v0.16b, v0.4b\[0\]
+[^:]+:\s+4f8be016      sdot    v22.4s, v0.16b, v11.4b\[0\]
+[^:]+:\s+4f96e016      sdot    v22.4s, v0.16b, v22.4b\[0\]
+[^:]+:\s+4fa0e016      sdot    v22.4s, v0.16b, v0.4b\[1\]
+[^:]+:\s+4fabe016      sdot    v22.4s, v0.16b, v11.4b\[1\]
+[^:]+:\s+4fb6e016      sdot    v22.4s, v0.16b, v22.4b\[1\]
+[^:]+:\s+4f80e816      sdot    v22.4s, v0.16b, v0.4b\[2\]
+[^:]+:\s+4f8be816      sdot    v22.4s, v0.16b, v11.4b\[2\]
+[^:]+:\s+4f96e816      sdot    v22.4s, v0.16b, v22.4b\[2\]
+[^:]+:\s+4fa0e816      sdot    v22.4s, v0.16b, v0.4b\[3\]
+[^:]+:\s+4fabe816      sdot    v22.4s, v0.16b, v11.4b\[3\]
+[^:]+:\s+4fb6e816      sdot    v22.4s, v0.16b, v22.4b\[3\]
+[^:]+:\s+4f80e176      sdot    v22.4s, v11.16b, v0.4b\[0\]
+[^:]+:\s+4f8be176      sdot    v22.4s, v11.16b, v11.4b\[0\]
+[^:]+:\s+4f96e176      sdot    v22.4s, v11.16b, v22.4b\[0\]
+[^:]+:\s+4fa0e176      sdot    v22.4s, v11.16b, v0.4b\[1\]
+[^:]+:\s+4fabe176      sdot    v22.4s, v11.16b, v11.4b\[1\]
+[^:]+:\s+4fb6e176      sdot    v22.4s, v11.16b, v22.4b\[1\]
+[^:]+:\s+4f80e976      sdot    v22.4s, v11.16b, v0.4b\[2\]
+[^:]+:\s+4f8be976      sdot    v22.4s, v11.16b, v11.4b\[2\]
+[^:]+:\s+4f96e976      sdot    v22.4s, v11.16b, v22.4b\[2\]
+[^:]+:\s+4fa0e976      sdot    v22.4s, v11.16b, v0.4b\[3\]
+[^:]+:\s+4fabe976      sdot    v22.4s, v11.16b, v11.4b\[3\]
+[^:]+:\s+4fb6e976      sdot    v22.4s, v11.16b, v22.4b\[3\]
+[^:]+:\s+4f80e2d6      sdot    v22.4s, v22.16b, v0.4b\[0\]
+[^:]+:\s+4f8be2d6      sdot    v22.4s, v22.16b, v11.4b\[0\]
+[^:]+:\s+4f96e2d6      sdot    v22.4s, v22.16b, v22.4b\[0\]
+[^:]+:\s+4fa0e2d6      sdot    v22.4s, v22.16b, v0.4b\[1\]
+[^:]+:\s+4fabe2d6      sdot    v22.4s, v22.16b, v11.4b\[1\]
+[^:]+:\s+4fb6e2d6      sdot    v22.4s, v22.16b, v22.4b\[1\]
+[^:]+:\s+4f80ead6      sdot    v22.4s, v22.16b, v0.4b\[2\]
+[^:]+:\s+4f8bead6      sdot    v22.4s, v22.16b, v11.4b\[2\]
+[^:]+:\s+4f96ead6      sdot    v22.4s, v22.16b, v22.4b\[2\]
+[^:]+:\s+4fa0ead6      sdot    v22.4s, v22.16b, v0.4b\[3\]
+[^:]+:\s+4fabead6      sdot    v22.4s, v22.16b, v11.4b\[3\]
+[^:]+:\s+4fb6ead6      sdot    v22.4s, v22.16b, v22.4b\[3\]

diff --git a/include/ChangeLog b/include/ChangeLog
index ecfd766af92b4341fbf78f3571a6961f52a687e3..144c1382ce7887358bf7020dfb14d39475c0ab09 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2017-12-19  Tamar Christina  <tamar.christina@arm.com>
+
+       PR gas/22559
+       * aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B.
+
 2017-12-19  Tamar Christina  <tamar.christina@arm.com>
 
        PR gas/22529

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 453b1771f02a9884652b44ec9c16ea5bbced1a83..1ebc4920e4de3c4cb944e9506057a0a366a133e3 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -396,6 +396,11 @@ enum aarch64_opnd_qualifier
   AARCH64_OPND_QLF_S_S,
   AARCH64_OPND_QLF_S_D,
   AARCH64_OPND_QLF_S_Q,
+  /* This type qualifier has a special meaning in that it means that 4 x 1 byte
+     are selected by the instruction.  Other than that it has no difference
+     with AARCH64_OPND_QLF_S_B in encoding.  It is here purely for syntactical
+     reasons and is an exception from normal AArch64 disassembly scheme.  */
+  AARCH64_OPND_QLF_S_4B,
 
   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
      register list; indicating register shape.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a8b8dba5be3805f099126739c05d9742ef9673dc..aa31dd30138e3eafd991a7ef742fc1ac16d08d29 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2017-12-19  Tamar Christina  <tamar.christina@arm.com>
+
+       PR gas/22559
+       * aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to
+       AARCH64_OPND_QLF_S_4B
+       * aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to
+       AARCH64_OPND_QLF_S_4B
+       * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
+       * aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
+
 2017-12-19  Tamar Christina  <tamar.christina@arm.com>
 
        PR gas/22529

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 9294910a113049ba15f4cccd91ec1857c8935649..92de737eb17591b5f42bda18bfd38cf2e5e24d98 100644 (file)
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -126,7 +126,7 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
       unsigned reglane_index = info->reglane.index;
       switch (info->qualifier)
        {
-       case AARCH64_OPND_QLF_S_B:
+       case AARCH64_OPND_QLF_S_4B:
          /* L:H */
          assert (reglane_index < 4);
          insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 8fd1ecfc920a4970104422a6444503102fadf526..aa38adb9020eb916515a1154aa5270db1f090830 100644 (file)
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -331,7 +331,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
       info->qualifier = get_expected_qualifier (inst, info->idx);
       switch (info->qualifier)
        {
-       case AARCH64_OPND_QLF_S_B:
+       case AARCH64_OPND_QLF_S_4B:
          /* L:H */
          info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
          info->reglane.regno &= 0x1f;

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index eac027955374bb4018546e0a32d21cdadc579340..2cccb0c1d7d923016dbdee5e5594b3e0a379335a 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -698,6 +698,7 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] =
   {4, 1, 0x2, "s", OQK_OPD_VARIANT},
   {8, 1, 0x3, "d", OQK_OPD_VARIANT},
   {16, 1, 0x4, "q", OQK_OPD_VARIANT},
+  {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
 
   {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
   {1, 8, 0x0, "8b", OQK_OPD_VARIANT},

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 11587dc5733ec2d62b9ab7eda253bfadb455d850..e38ab2083834976ea2bf29999641ba06fa44b9f5 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1992,8 +1992,8 @@
 /* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.4B[<index>].  */
 #define QL_V2DOT        \
 {                       \
-  QLF3(V_2S, V_8B,  S_B),\
-  QLF3(V_4S, V_16B, S_B),\
+  QLF3(V_2S, V_8B,  S_4B),\
+  QLF3(V_4S, V_16B, S_4B),\
 }
 
 /* e.g. SHA512H <Qd>, <Qn>, <Vm>.2D\f.  */