+2020-06-30 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (riscv_csr_class_check): Removed. Move the
+ checking into riscv_csr_address.
+ (riscv_csr_version_check): Likewise.
+ (riscv_csr_address): New function. Return the suitable CSR address
+ after checking the ISA dependency and versions. Issue warnings if
+ we find any conflict and -mcsr-check is set. CSR_CLASS_F and
+ CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the
+ priv spec versions for them.
+ (reg_csr_lookup_internal): Call riscv_csr_address to find the
+ suitable CSR address.
+ * testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11.
+ * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-fext.l: We don't care the
+ priv spec warnings here. These warnings are added by accident.
+ Remove them and only focus on the ISA dependency warnings.
+ * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since
+ dscratch0 and dscratch1 are regarded as the unprivileged CSR rather
+ than the privileged ones.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
+ * testsuite/gas/riscv/priv-reg.s: Likewise. Add missing debug CSR.
+ * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
+ * testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
+ * testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
+
2020-06-29 H.J. Lu <hongjiu.lu@intel.com>
* tc-i386.c (build_vex_prefix): Support VEX base opcode length > 1.
pre_entry->next = entry;
}
-/* Check wether the CSR is valid according to the ISA. */
+/* Return the suitable CSR address after checking the ISA dependency and
+ priv spec versions. */
-static void
-riscv_csr_class_check (const char *s,
- enum riscv_csr_class csr_class)
+static unsigned int
+riscv_csr_address (const char *csr_name,
+ struct riscv_csr_extra *entry)
{
+ struct riscv_csr_extra *saved_entry = entry;
+ enum riscv_csr_class csr_class = entry->csr_class;
+ bfd_boolean need_check_version = TRUE;
bfd_boolean result = TRUE;
- /* Don't check the ISA dependency when -mcsr-check isn't set. */
- if (!riscv_opts.csr_check)
- return;
-
switch (csr_class)
{
case CSR_CLASS_I:
result = riscv_subset_supports ("i");
break;
+ case CSR_CLASS_I_32:
+ result = (xlen == 32 && riscv_subset_supports ("i"));
+ break;
case CSR_CLASS_F:
result = riscv_subset_supports ("f");
+ need_check_version = FALSE;
break;
- case CSR_CLASS_I_32:
- result = (xlen == 32 && riscv_subset_supports ("i"));
+ case CSR_CLASS_DEBUG:
+ need_check_version = FALSE;
break;
default:
as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
}
- if (!result)
- as_warn (_("Invalid CSR `%s' for the current ISA"), s);
-}
-
-/* Check and find the CSR address according to the privilege spec version. */
-
-static void
-riscv_csr_version_check (const char *csr_name,
- struct riscv_csr_extra **entryP)
-{
- struct riscv_csr_extra *entry = *entryP;
+ /* Don't report the ISA conflict when -mcsr-check isn't set. */
+ if (riscv_opts.csr_check && !result)
+ as_warn (_("Invalid CSR `%s' for the current ISA"), csr_name);
while (entry != NULL)
{
- if (default_priv_spec >= entry->define_version
- && default_priv_spec < entry->abort_version)
+ if (!need_check_version
+ || (default_priv_spec >= entry->define_version
+ && default_priv_spec < entry->abort_version))
{
/* Find the suitable CSR according to the specific version. */
- *entryP = entry;
- return;
+ return entry->address;
}
entry = entry->next;
}
as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
csr_name, priv_name);
}
+
+ return saved_entry->address;
}
/* Once the CSR is defined, including the old privilege spec, then we call
will regard it as a "Unknown CSR" and report error. If user use number
to set the CSR, but over the range (> 0xfff), then assembler will report
"Improper CSR" error for it. */
- riscv_csr_class_check (s, r->csr_class);
- riscv_csr_version_check (s, &r);
-
- return r->address;
+ return riscv_csr_address (s, r);
}
static unsigned int
DW_CFA_offset_extended_sf: r4162 \(ucause\) at cfa\+264
DW_CFA_offset_extended_sf: r4163 \(utval\) at cfa\+268
DW_CFA_offset_extended_sf: r4164 \(uip\) at cfa\+272
- DW_CFA_offset_extended_sf: r4097 \(fflags\) at cfa\+4
- DW_CFA_offset_extended_sf: r4098 \(frm\) at cfa\+8
- DW_CFA_offset_extended_sf: r4099 \(fcsr\) at cfa\+12
DW_CFA_offset_extended_sf: r7168 \(cycle\) at cfa\+12288
DW_CFA_offset_extended_sf: r7169 \(time\) at cfa\+12292
DW_CFA_offset_extended_sf: r7170 \(instret\) at cfa\+12296
DW_CFA_offset_extended_sf: r4925 \(mhpmevent29\) at cfa\+3316
DW_CFA_offset_extended_sf: r4926 \(mhpmevent30\) at cfa\+3320
DW_CFA_offset_extended_sf: r4927 \(mhpmevent31\) at cfa\+3324
- DW_CFA_offset_extended_sf: r6048 \(tselect\) at cfa\+7808
- DW_CFA_offset_extended_sf: r6049 \(tdata1\) at cfa\+7812
- DW_CFA_offset_extended_sf: r6050 \(tdata2\) at cfa\+7816
- DW_CFA_offset_extended_sf: r6051 \(tdata3\) at cfa\+7820
- DW_CFA_offset_extended_sf: r6064 \(dcsr\) at cfa\+7872
- DW_CFA_offset_extended_sf: r6065 \(dpc\) at cfa\+7876
- DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
- DW_CFA_offset_extended_sf: r6067 \(dscratch1\) at cfa\+7884
DW_CFA_offset_extended_sf: r4608 \(hstatus\) at cfa\+2048
DW_CFA_offset_extended_sf: r4610 \(hedeleg\) at cfa\+2056
DW_CFA_offset_extended_sf: r4611 \(hideleg\) at cfa\+2060
DW_CFA_offset_extended_sf: r4997 \(mdbound\) at cfa\+3604
DW_CFA_offset_extended_sf: r4897 \(mscounteren\) at cfa\+3204
DW_CFA_offset_extended_sf: r4898 \(mhcounteren\) at cfa\+3208
+ DW_CFA_offset_extended_sf: r4097 \(fflags\) at cfa\+4
+ DW_CFA_offset_extended_sf: r4098 \(frm\) at cfa\+8
+ DW_CFA_offset_extended_sf: r4099 \(fcsr\) at cfa\+12
+ DW_CFA_offset_extended_sf: r6064 \(dcsr\) at cfa\+7872
+ DW_CFA_offset_extended_sf: r6065 \(dpc\) at cfa\+7876
+ DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
+ DW_CFA_offset_extended_sf: r6067 \(dscratch1\) at cfa\+7884
+ DW_CFA_offset_extended_sf: r6048 \(tselect\) at cfa\+7808
+ DW_CFA_offset_extended_sf: r6049 \(tdata1\) at cfa\+7812
+ DW_CFA_offset_extended_sf: r6050 \(tdata2\) at cfa\+7816
+ DW_CFA_offset_extended_sf: r6051 \(tdata3\) at cfa\+7820
+ DW_CFA_offset_extended_sf: r6052 \(tinfo\) at cfa\+7824
+ DW_CFA_offset_extended_sf: r6053 \(tcontrol\) at cfa\+7828
+ DW_CFA_offset_extended_sf: r6056 \(mcontext\) at cfa\+7840
+ DW_CFA_offset_extended_sf: r6058 \(scontext\) at cfa\+7848
DW_CFA_offset_extended_sf: r4163 \(utval\) at cfa\+268
DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
- DW_CFA_nop
+ DW_CFA_offset_extended_sf: r6049 \(tdata1\) at cfa\+7812
+ DW_CFA_offset_extended_sf: r6049 \(tdata1\) at cfa\+7812
+ DW_CFA_offset_extended_sf: r6049 \(tdata1\) at cfa\+7812
+ DW_CFA_offset_extended_sf: r6049 \(tdata1\) at cfa\+7812
+ DW_CFA_offset_extended_sf: r6051 \(tdata3\) at cfa\+7820
+ DW_CFA_offset_extended_sf: r6051 \(tdata3\) at cfa\+7820
#...
.cfi_offset ucause, 264
.cfi_offset utval, 268
.cfi_offset uip, 272
- .cfi_offset fflags, 4
- .cfi_offset frm, 8
- .cfi_offset fcsr, 12
.cfi_offset cycle, 12288
.cfi_offset time, 12292
.cfi_offset instret, 12296
.cfi_offset mhpmevent29, 3316
.cfi_offset mhpmevent30, 3320
.cfi_offset mhpmevent31, 3324
- .cfi_offset tselect, 7808
- .cfi_offset tdata1, 7812
- .cfi_offset tdata2, 7816
- .cfi_offset tdata3, 7820
- .cfi_offset dcsr, 7872
- .cfi_offset dpc, 7876
- .cfi_offset dscratch0, 7880
- .cfi_offset dscratch1, 7884
-
- # dropped in the current 1.11 priv spec.
+ # dropped
.cfi_offset hstatus, 2048
.cfi_offset hedeleg, 2056
.cfi_offset hideleg, 2060
.cfi_offset mdbound, 3604
.cfi_offset mscounteren, 3204
.cfi_offset mhcounteren, 3208
+ # unprivileged
+ .cfi_offset fflags, 4
+ .cfi_offset frm, 8
+ .cfi_offset fcsr, 12
+ .cfi_offset dcsr, 7872
+ .cfi_offset dpc, 7876
+ .cfi_offset dscratch0, 7880
+ .cfi_offset dscratch1, 7884
+ .cfi_offset tselect, 7808
+ .cfi_offset tdata1, 7812
+ .cfi_offset tdata2, 7816
+ .cfi_offset tdata3, 7820
+ .cfi_offset tinfo, 7824
+ .cfi_offset tcontrol, 7828
+ .cfi_offset mcontext, 7840
+ .cfi_offset scontext, 7848
+ # aliases
.cfi_offset ubadaddr, 268
.cfi_offset sbadaddr, 1292
.cfi_offset sptbr, 1536
.cfi_offset mbadaddr, 3340
.cfi_offset mucounteren, 3200
.cfi_offset dscratch, 7880
+ .cfi_offset mcontrol, 7812
+ .cfi_offset icount, 7812
+ .cfi_offset itrigger, 7812
+ .cfi_offset etrigger, 7812
+ .cfi_offset textra32, 7820
+ .cfi_offset textra64, 7820
nop
.cfi_endproc
-#as: -march=rv32i -mcsr-check -mpriv-spec=1.11
+#as: -march=rv32i -mcsr-check
#source: priv-reg.s
#warning_output: priv-reg-fail-fext.l
.*Assembler messages:
+#...
.*Warning: Invalid CSR `fflags' for the current ISA
.*Warning: Invalid CSR `frm' for the current ISA
.*Warning: Invalid CSR `fcsr' for the current ISA
-
-.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.11'
-.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.11'
-.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
-.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
-.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mibound' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mdbase' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mdbound' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.11'
+#...
-#as: -march=rv32if -mcsr-check -mpriv-spec=1.11
+#as: -march=rv32if -mcsr-check
#source: priv-reg-fail-read-only-01.s
#warning_output: priv-reg-fail-read-only-01.l
.*Assembler messages:
+#...
.*Warning: Read-only CSR is written `csrw cycle,a1'
.*Warning: Read-only CSR is written `csrw time,a1'
.*Warning: Read-only CSR is written `csrw instret,a1'
.*Warning: Read-only CSR is written `csrw marchid,a1'
.*Warning: Read-only CSR is written `csrw mimpid,a1'
.*Warning: Read-only CSR is written `csrw mhartid,a1'
-
-.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.11'
-.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.11'
-.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
-.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
-.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mibound' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mdbase' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mdbound' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.11'
+#...
-#as: -march=rv64if -mcsr-check -mpriv-spec=1.11
+#as: -march=rv64if -mcsr-check
#source: priv-reg.s
#warning_output: priv-reg-fail-rv32-only.l
.*Assembler messages:
+#...
.*Warning: Invalid CSR `cycleh' for the current ISA
.*Warning: Invalid CSR `timeh' for the current ISA
.*Warning: Invalid CSR `instreth' for the current ISA
.*Warning: Invalid CSR `mhpmcounter29h' for the current ISA
.*Warning: Invalid CSR `mhpmcounter30h' for the current ISA
.*Warning: Invalid CSR `mhpmcounter31h' for the current ISA
-
-.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.11'
-.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.11'
-.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
-.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
-.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
-.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mibound' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mdbase' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mdbound' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.11'
-.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.11'
+#...
.*Assembler messages:
.*Warning: Invalid CSR `mcountinhibit' for the privilege spec `1.10'
-.*Warning: Invalid CSR `dscratch0' for the privilege spec `1.10'
-.*Warning: Invalid CSR `dscratch1' for the privilege spec `1.10'
.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.10'
.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.10'
.*Warning: Invalid CSR `sptbr' for the privilege spec `1.10'
.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
-.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
.*Warning: Invalid CSR `pmpaddr14' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `pmpaddr15' for the privilege spec `1.9.1'
.*Warning: Invalid CSR `mcountinhibit' for the privilege spec `1.9.1'
-.*Warning: Invalid CSR `dscratch0' for the privilege spec `1.9.1'
-.*Warning: Invalid CSR `dscratch1' for the privilege spec `1.9.1'
[ ]+[0-9a-f]+:[ ]+04202573[ ]+csrr[ ]+a0,ucause
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
[ ]+[0-9a-f]+:[ ]+04402573[ ]+csrr[ ]+a0,uip
-[ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
-[ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
-[ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0002573[ ]+rdcycle[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0102573[ ]+rdtime[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0202573[ ]+rdinstret[ ]+a0
[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
-[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
-[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
-[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
-[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
-[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
-[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
-[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
-[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,0x7b3
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,0x320
-[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,0x200
[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,0x202
[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,0x203
[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,0x385
[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,0x321
[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,0x322
+[ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
+[ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
+[ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
+[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
+[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
+[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
+[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
+[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
+[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
+[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+7a402573[ ]+csrr[ ]+a0,tinfo
+[ ]+[0-9a-f]+:[ ]+7a502573[ ]+csrr[ ]+a0,tcontrol
+[ ]+[0-9a-f]+:[ ]+7a802573[ ]+csrr[ ]+a0,mcontext
+[ ]+[0-9a-f]+:[ ]+7aa02573[ ]+csrr[ ]+a0,scontext
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+04202573[ ]+csrr[ ]+a0,ucause
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
[ ]+[0-9a-f]+:[ ]+04402573[ ]+csrr[ ]+a0,uip
-[ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
-[ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
-[ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0002573[ ]+rdcycle[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0102573[ ]+rdtime[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0202573[ ]+rdinstret[ ]+a0
[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
-[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
-[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
-[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
-[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
-[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
-[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
-[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
-[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
-[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,0x200
[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,0x202
[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,0x203
[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,0x385
[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,0x321
[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,0x322
+[ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
+[ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
+[ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
+[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
+[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
+[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
+[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
+[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
+[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
+[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+7a402573[ ]+csrr[ ]+a0,tinfo
+[ ]+[0-9a-f]+:[ ]+7a502573[ ]+csrr[ ]+a0,tcontrol
+[ ]+[0-9a-f]+:[ ]+7a802573[ ]+csrr[ ]+a0,mcontext
+[ ]+[0-9a-f]+:[ ]+7aa02573[ ]+csrr[ ]+a0,scontext
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+04202573[ ]+csrr[ ]+a0,ucause
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,ubadaddr
[ ]+[0-9a-f]+:[ ]+04402573[ ]+csrr[ ]+a0,uip
-[ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
-[ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
-[ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0002573[ ]+rdcycle[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0102573[ ]+rdtime[ ]+a0
[ ]+[0-9a-f]+:[ ]+c0202573[ ]+rdinstret[ ]+a0
[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
-[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
-[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
-[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
-[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
-[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
-[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
-[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
-[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,0x7b3
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,ubadaddr
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,sbadaddr
[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,sptbr
[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mbadaddr
[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mucounteren
-[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
+[ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
+[ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
+[ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
+[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
+[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
+[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
+[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
+[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
+[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
+[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+7a402573[ ]+csrr[ ]+a0,tinfo
+[ ]+[0-9a-f]+:[ ]+7a502573[ ]+csrr[ ]+a0,tcontrol
+[ ]+[0-9a-f]+:[ ]+7a802573[ ]+csrr[ ]+a0,mcontext
+[ ]+[0-9a-f]+:[ ]+7aa02573[ ]+csrr[ ]+a0,scontext
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
csr utval # Added in 1.10
csr uip
- csr fflags
- csr frm
- csr fcsr
-
csr cycle
csr time
csr instret
csr mhpmevent30
csr mhpmevent31
- csr tselect
- csr tdata1
- csr tdata2
- csr tdata3
-
- csr dcsr
- csr dpc
- csr dscratch0 # Added in 1.11
- csr dscratch1 # Added in 1.11
-
# Supported in previous priv spec, but dropped now.
csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10
csr sbadaddr # 0x143 in 1.9.1, but the value is stval since 1.10
csr sptbr # 0x180 in 1.9.1, but the value is satp since 1.10
csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10
csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11
- csr dscratch # 0x7b2 in 1.10, but the value is dscratch0 since 1.11
csr hstatus # 0x200, dropped in 1.10
csr hedeleg # 0x202, dropped in 1.10
csr mdbound # 0x385, dropped in 1.10
csr mscounteren # 0x321, dropped in 1.10
csr mhcounteren # 0x322, dropped in 1.10
+
+ # Unprivileged CSR which are not controlled by privilege spec.
+
+ # Float
+ csr fflags
+ csr frm
+ csr fcsr
+
+ # Core debug
+ csr dcsr
+ csr dpc
+ csr dscratch0
+ csr dscratch1
+ csr dscratch # 0x7b2, alias to dscratch0
+
+ # Trigger debug
+ csr tselect
+ csr tdata1
+ csr tdata2
+ csr tdata3
+ csr tinfo
+ csr tcontrol
+ csr mcontext
+ csr scontext
+ csr mcontrol # 0x7a1, alias to tdata1
+ csr icount # 0x7a1, alias to tdata1
+ csr itrigger # 0x7a1, alias to tdata1
+ csr etrigger # 0x7a1, alias to tdata1
+ csr textra32 # 0x7a3, alias to tdata3
+ csr textra64 # 0x7a3, alias to tdata3
+2020-06-30 Nelson Chu <nelson.chu@sifive.com>
+
+ * opcode/riscv-opc.h: Support the unprivileged CSR. The versions
+ of the unprivileged CSR should be PRIV_SPEC_CLASS_NONE for now.
+ * opcode/riscv.h (enum riscv_csr_class): Add CSR_CLASS_DEBUG.
+
2020-06-30 Nelson Chu <nelson.chu@sifive.com>
* opcode/riscv-opc.h: Cleanup and remove the unused macros.
#define MASK_CUSTOM3_RD_RS1 0x707f
#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
-/* CSR addresses (priv spec v1.11). */
+/* Privileged CSR addresses (v1.11). */
#define CSR_USTATUS 0x0
#define CSR_UIE 0x4
#define CSR_UTVEC 0x5
#define CSR_UCAUSE 0x42
#define CSR_UTVAL 0x43
#define CSR_UIP 0x44
-#define CSR_FFLAGS 0x1
-#define CSR_FRM 0x2
-#define CSR_FCSR 0x3
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
#define CSR_INSTRET 0xc02
#define CSR_MHPMEVENT29 0x33d
#define CSR_MHPMEVENT30 0x33e
#define CSR_MHPMEVENT31 0x33f
-#define CSR_TSELECT 0x7a0
-#define CSR_TDATA1 0x7a1
-#define CSR_TDATA2 0x7a2
-#define CSR_TDATA3 0x7a3
-#define CSR_DCSR 0x7b0
-#define CSR_DPC 0x7b1
-#define CSR_DSCRATCH0 0x7b2
-#define CSR_DSCRATCH1 0x7b3
#define CSR_HSTATUS 0x200
#define CSR_HEDELEG 0x202
#define CSR_HIDELEG 0x203
#define CSR_MDBOUND 0x385
#define CSR_MSCOUNTEREN 0x321
#define CSR_MHCOUNTEREN 0x322
+/* Unprivileged CSR addresses. */
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH0 0x7b2
+#define CSR_DSCRATCH1 0x7b3
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_TINFO 0x7a4
+#define CSR_TCONTROL 0x7a5
+#define CSR_MCONTEXT 0x7a8
+#define CSR_SCONTEXT 0x7aa
#endif /* RISCV_ENCODING_H. */
#ifdef DECLARE_INSN
DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
#endif /* DECLARE_INSN. */
#ifdef DECLARE_CSR
+/* Privileged. */
DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT)
+/* Dropped. */
DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
+/* Unprivileged. */
+DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
#endif /* DECLARE_CSR. */
#ifdef DECLARE_CSR_ALIAS
DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
-DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P11)
+DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(mcontrol, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(icount, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(itrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
#endif /* DECLARE_CSR_ALIAS. */
CSR_CLASS_I,
CSR_CLASS_I_32, /* rv32 only */
CSR_CLASS_F, /* f-ext only */
+ CSR_CLASS_DEBUG /* debug CSR */
};
/* The current supported privilege spec versions. */
+2020-06-30 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
+ unprivileged CSR can also be initialized.
+
2020-06-29 Alan Modra <amodra@gmail.com>
* arm-dis.c: Use C style comments.
if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1;
-#define DECLARE_CSR(name, num, class, define_version, abort_version) \
- if (default_priv_spec >= define_version \
- && default_priv_spec < abort_version) \
+#define DECLARE_CSR(name, num, class, define_version, abort_version) \
+ if (riscv_csr_hash[num] == NULL \
+ && ((define_version == PRIV_SPEC_CLASS_NONE \
+ && abort_version == PRIV_SPEC_CLASS_NONE) \
+ || (default_priv_spec >= define_version \
+ && default_priv_spec < abort_version))) \
riscv_csr_hash[num] = #name;
#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
DECLARE_CSR (name, num, class, define_version, abort_version)
projects / deliverable / binutils-gdb.git / commitdiff
