Correct ordering of args for cmov insn.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fe75e9d2455bdb34b0770b30ead8dae359798195..c836b2a4b2ba1e677f89a9d70f935833a8fcdc49 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+start-sanitize-v850e
+Fri Sep 19 11:45:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * v850-opc.c ("cmov"): Order reg param r1, r2 not r2, r2.
+
+end-sanitize-v850e
 Thu Sep 18 11:21:43 1997  Doug Evans  <dje@canuck.cygnus.com>
 
        * sparc-opc.c (sparclet_cpreg_table): Add %ccsr2, %cccrr, %ccrstr.

diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index bafb985af2b38f3d7a27fb34169418f9a56b104a..5376bdc09ad601ed63fca752d85f9ae8d70be4b2 100644 (file)
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -638,7 +638,7 @@ const struct v850_opcode v850_opcodes[] =
 /* arithmetic operation instructions */
 { "setf",      two (0x07e0, 0x0000),   two (0x07f0, 0xffff),   {CCCC, R2},             0, PROCESSOR_ALL },
 /* start-sanitize-v850e */
-{ "cmov",      two (0x07e0, 0x0320),   two (0x07e0, 0x07e1),   {MOVCC, R2, R1, R3},    0, PROCESSOR_NOT_V850 },
+{ "cmov",      two (0x07e0, 0x0320),   two (0x07e0, 0x07e1),   {MOVCC, R1, R2, R3},    0, PROCESSOR_NOT_V850 },
 { "cmov",      two (0x07e0, 0x0300),   two (0x07e0, 0x07e1),   {MOVCC, I5, R2, R3},    0, PROCESSOR_NOT_V850 },
 
 { "mul",       two (0x07e0, 0x0220),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_NOT_V850 },