Fix generation of AArhc64 instruction table.

	* aarch64-gen.c (VERIFIER): Define.
	* aarch64-opc.c (VERIFIER): Define.
	(verify_ldpsw): Use static linkage.
	* aarch64-opc.h (verify_ldpsw): Remove.
	* aarch64-tbl.h: Use VERIFIER for verifiers.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a66e93fb8e2c0f9c00dd4f971ba72d9114c71644..d1663252c9bc5343e234532b20b18f1b8d11b622 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+       * aarch64-gen.c (VERIFIER): Define.
+       * aarch64-opc.c (VERIFIER): Define.
+       (verify_ldpsw): Use static linkage.
+       * aarch64-opc.h (verify_ldpsw): Remove.
+       * aarch64-tbl.h: Use VERIFIER for verifiers.
+
 2016-04-28  Nick Clifton  <nickc@redhat.com>
 
        PR target/19722

diff --git a/opcodes/aarch64-gen.c b/opcodes/aarch64-gen.c
index c106c7d7f56e95767bc37ec79f6175f67670e3db..ed0834a7ac64a92dda238b74b05f22d0302f8a6b 100644 (file)
--- a/opcodes/aarch64-gen.c
+++ b/opcodes/aarch64-gen.c
@@ -28,6 +28,7 @@
 #include "getopt.h"
 #include "opcode/aarch64.h"
 
+#define VERIFIER(x) NULL
 #include "aarch64-tbl.h"
 
 static int debug = 0;

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 8fbea46f4bbd239b23fd741c81522e7767e938ac..d9a31e83a5e1659a8614d4815ed1c4c00b6d69f8 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3420,7 +3420,7 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
 #define BIT(INSN,BT)     (((INSN) >> (BT)) & 1)
 #define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
 
-bfd_boolean
+static bfd_boolean
 verify_ldpsw (const struct aarch64_opcode * opcode ATTRIBUTE_UNUSED,
              const aarch64_insn insn)
 {
@@ -3447,4 +3447,5 @@ verify_ldpsw (const struct aarch64_opcode * opcode ATTRIBUTE_UNUSED,
 
 /* Include the opcode description table as well as the operand description
    table.  */
+#define VERIFIER(x) verify_##x
 #include "aarch64-tbl.h"

diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index c5bcbb82df48c42f25c559a0eed9896041bcab66..08494c678a5503a1ac5b1eda3f399b20996ea623 100644 (file)
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -390,7 +390,4 @@ get_logsz (unsigned int size)
   return ls[size - 1];
 }
 
-/* Instruction Verifiers.  */
-extern bfd_boolean verify_ldpsw (const struct aarch64_opcode *, const aarch64_insn);
-
 #endif /* OPCODES_AARCH64_OPC_H */

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 7a47a17582b3bd36a31fcf3c7da384fb517bef55..c223d18703e130f6c9460f7de48fe1c31278a571 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -21,6 +21,10 @@
 
 #include "aarch64-opc.h"
 
+#ifndef VERIFIER
+#error  VERIFIER must be defined.
+#endif
+
 /* Operand type.  */
 
 #define OPND(x)        AARCH64_OPND_##x
@@ -2383,13 +2387,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
   CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
   CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
-  {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, verify_ldpsw},
+  {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, VERIFIER (ldpsw)},
   /* Load/store register pair (indexed).  */
   CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
   CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
   CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
   CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
-  {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, verify_ldpsw},
+  {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, VERIFIER (ldpsw)},
   /* Load register (literal).  */
   {"ldr",   0x18000000, 0xbf000000, loadlit, OP_LDR_LIT,   CORE, OP2 (Rt, ADDR_PCREL19),    QL_R_PCREL, F_GPRSIZE_IN_Q, NULL},
   {"ldr",   0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT,  CORE, OP2 (Ft, ADDR_PCREL19),    QL_FP_PCREL, 0, NULL},