Add AArch32 support for arm gold linker.

diff --git a/elfcpp/ChangeLog b/elfcpp/ChangeLog
index f298d806a06dcf880006d853d733a51b0e46e07a..5cc38cb77bc76e52580b9b76b8b27a49d799d7e2 100644 (file)
--- a/elfcpp/ChangeLog
+++ b/elfcpp/ChangeLog
@@ -1,3 +1,7 @@
+2015-04-07  HC Yen <hc.yen@mediatek.com>
+
+       * arm.h: Add TAG_CPU_ARCH_V8 in Tag_CPU_arch EABI attribute.
+
 2015-02-09  Mark Wielaard  <mjw@redhat.com>
 
        * dwarf.h (enum DW_LANG): Add DW_LANG_C_plus_plus_11,

diff --git a/elfcpp/arm.h b/elfcpp/arm.h
index c9cb753e3203ae5a2e4cb72c3c1df621bb805068..14109b9797c9ec072d3f9a6b6ea1562baa02ff44 100644 (file)
--- a/elfcpp/arm.h
+++ b/elfcpp/arm.h
@@ -248,7 +248,8 @@ enum
   TAG_CPU_ARCH_V6_M,
   TAG_CPU_ARCH_V6S_M,
   TAG_CPU_ARCH_V7E_M,
-  MAX_TAG_CPU_ARCH = TAG_CPU_ARCH_V7E_M,
+  TAG_CPU_ARCH_V8,
+  MAX_TAG_CPU_ARCH = TAG_CPU_ARCH_V8,
   // Pseudo-architecture to allow objects to be compatible with the subset of
   // armv4t and armv6-m.  This value should never be stored in object files.
   TAG_CPU_ARCH_V4T_PLUS_V6_M = (MAX_TAG_CPU_ARCH + 1)

diff --git a/gold/ChangeLog b/gold/ChangeLog
index ee0abcbaeca1b871e87ef637854e979aa39c7ee1..fa82e421e0c77dbf98a289732e635e224a2b1c16 100644 (file)
--- a/gold/ChangeLog
+++ b/gold/ChangeLog
@@ -1,3 +1,9 @@
+2015-04-07  HC Yen <hc.yen@mediatek.com>
+
+       Add AArch32 support for gold linker.
+       gold/
+       * arm.cc: Add V8 arch combine table.
+
 2015-04-06  Rafael Ávila de Espíndola <rafael.espindola@gmail.com>
 
        * aarch64.cc (do_reloc_addend): Fix signature to match the parent one.

diff --git a/gold/arm.cc b/gold/arm.cc
index f1d4fe930bb70a8356a6b12293048d69073e165c..9812c8888fc869e4d9b65dcd6c40680da930ff2a 100644 (file)
--- a/gold/arm.cc
+++ b/gold/arm.cc
@@ -10759,6 +10759,24 @@ Target_arm<big_endian>::tag_cpu_arch_combine(
       T(V7E_M),        // V6S_M.
       T(V7E_M) // V7E_M.
     };
+  static const int v8[] =
+    {
+      T(V8),   // PRE_V4.
+      T(V8),   // V4.
+      T(V8),   // V4T.
+      T(V8),   // V5T.
+      T(V8),   // V5TE.
+      T(V8),   // V5TEJ.
+      T(V8),   // V6.
+      T(V8),   // V6KZ.
+      T(V8),   // V6T2.
+      T(V8),   // V6K.
+      T(V8),   // V7.
+      T(V8),   // V6_M.
+      T(V8),   // V6S_M.
+      T(V8),   // V7E_M.
+      T(V8)    // V8.
+    };
   static const int v4t_plus_v6_m[] =
     {
       -1,              // PRE_V4.
@@ -10775,6 +10793,7 @@ Target_arm<big_endian>::tag_cpu_arch_combine(
       T(V6_M),         // V6_M.
       T(V6S_M),                // V6S_M.
       T(V7E_M),                // V7E_M.
+      T(V8),           // V8.
       T(V4T_PLUS_V6_M) // V4T plus V6_M.
     };
   static const int* comb[] =
@@ -10785,6 +10804,7 @@ Target_arm<big_endian>::tag_cpu_arch_combine(
       v6_m,
       v6s_m,
       v7e_m,
+      v8,
       // Pseudo-architecture.
       v4t_plus_v6_m
     };
@@ -10882,7 +10902,8 @@ Target_arm<big_endian>::tag_cpu_name_value(unsigned int value)
    "ARM v7",
    "ARM v6-M",
    "ARM v6S-M",
-   "ARM v7E-M"
+   "ARM v7E-M",
+   "ARM v8"
  };
  const size_t name_table_size = sizeof(name_table) / sizeof(name_table[0]);