aarch64*-*-*ilp32 gas tests
authorAlan Modra <amodra@gmail.com>
Sat, 7 Dec 2019 12:01:43 +0000 (22:31 +1030)
committerAlan Modra <amodra@gmail.com>
Sun, 8 Dec 2019 11:33:53 +0000 (22:03 +1030)
The new pac_negate_ra_state test adds yet another failure on aarch64
ipl32 targets.  This patch fixes that particular problem and a few
more that are trivial to fix.

* testsuite/gas/aarch64/bfloat16.d: Match 32-bit and 64-bit output.
* testsuite/gas/aarch64/dgh.d: Likewise.
* testsuite/gas/aarch64/f32mm.d: Likewise.
* testsuite/gas/aarch64/f64mm.d: Likewise.
* testsuite/gas/aarch64/i8mm.d: Likewise.
* testsuite/gas/aarch64/pac_ab_key.d: Likewise.
* testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise.
* testsuite/gas/aarch64/reloc-prel_g0.d: Likewise.
* testsuite/gas/aarch64/reloc-prel_g0_nc.d: Likewise.
* testsuite/gas/aarch64/reloc-prel_g1.d: Likewise.
* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx-mm.d: Likewise.
* testsuite/gas/aarch64/sve2.d: Likewise.

14 files changed:
gas/ChangeLog
gas/testsuite/gas/aarch64/bfloat16.d
gas/testsuite/gas/aarch64/dgh.d
gas/testsuite/gas/aarch64/f32mm.d
gas/testsuite/gas/aarch64/f64mm.d
gas/testsuite/gas/aarch64/i8mm.d
gas/testsuite/gas/aarch64/pac_ab_key.d
gas/testsuite/gas/aarch64/pac_negate_ra_state.d
gas/testsuite/gas/aarch64/reloc-prel_g0.d
gas/testsuite/gas/aarch64/reloc-prel_g0_nc.d
gas/testsuite/gas/aarch64/reloc-prel_g1.d
gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d
gas/testsuite/gas/aarch64/sve-movprfx-mm.d
gas/testsuite/gas/aarch64/sve2.d

index 95712ae85c2f9828b9c065c8d5d298ad9a34cc0b..0e9a585432de421258881554945ef7c6fbeeb24e 100644 (file)
@@ -1,3 +1,19 @@
+2019-12-08  Alan Modra  <amodra@gmail.com>
+
+       * testsuite/gas/aarch64/bfloat16.d: Match 32-bit and 64-bit output.
+       * testsuite/gas/aarch64/dgh.d: Likewise.
+       * testsuite/gas/aarch64/f32mm.d: Likewise.
+       * testsuite/gas/aarch64/f64mm.d: Likewise.
+       * testsuite/gas/aarch64/i8mm.d: Likewise.
+       * testsuite/gas/aarch64/pac_ab_key.d: Likewise.
+       * testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise.
+       * testsuite/gas/aarch64/reloc-prel_g0.d: Likewise.
+       * testsuite/gas/aarch64/reloc-prel_g0_nc.d: Likewise.
+       * testsuite/gas/aarch64/reloc-prel_g1.d: Likewise.
+       * testsuite/gas/aarch64/sve-bfloat-movprfx.d: Likewise.
+       * testsuite/gas/aarch64/sve-movprfx-mm.d: Likewise.
+       * testsuite/gas/aarch64/sve2.d: Likewise.
+
 2019-12-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        * dw2gencfi.c (cfi_pseudo_table): Add cfi_negate_ra_state.
index 78d10cb3cadb98c00763ba299d55c548d2209d31..176af8b520fb7ecbf8582dc08fb40e4dab3afd57 100644 (file)
@@ -6,7 +6,7 @@
 
 Disassembly of section \.text:
 
-0000000000000000 <\.text>:
+0+ <\.text>:
  *[0-9a-f]+:   647b82b1        bfdot   z17\.s, z21\.h, z27\.h
  *[0-9a-f]+:   64608000        bfdot   z0\.s, z0\.h, z0\.h
  *[0-9a-f]+:   647d42b1        bfdot   z17\.s, z21\.h, z5\.h\[3\]
index 6e196015a6f0acb470a137fb971c931ce3f445bf..9d11bec971253dd575a8009874806689d2972eee 100644 (file)
@@ -6,6 +6,6 @@
 
 Disassembly of section \.text:
 
-0000000000000000 <\.text>:
+0+ <\.text>:
  *[0-9a-f]*:   d50320df        hint    #0x6
  *[0-9a-f]*:   d50320df        hint    #0x6
index 8f1cdffa5ec3973c6208d4f081cc26b2251c3eca..0481852def66244ebd4164e39f47c392a813eb58 100644 (file)
@@ -6,6 +6,6 @@
 
 Disassembly of section \.text:
 
-0000000000000000 <\.text>:
+0+ <\.text>:
  *[0-9a-f]+:   64bbe6b1        fmmla   z17\.s, z21\.s, z27\.s
  *[0-9a-f]+:   64a0e400        fmmla   z0\.s, z0\.s, z0\.s
index 9540c136c82cfaeffa326121d643ca37de714aa2..a09179a93be5a64c809c02df4a15c926c8709fcd 100644 (file)
@@ -5,7 +5,7 @@
 
 Disassembly of section \.text:
 
-0000000000000000 <\.text>:
+0+ <\.text>:
  *[0-9a-f]+:   64dbe6b1        fmmla   z17\.d, z21\.d, z27\.d
  *[0-9a-f]+:   64c0e400        fmmla   z0\.d, z0\.d, z0\.d
  *[0-9a-f]+:   a43b17f1        ld1rob  {z17\.b}, p5/z, \[sp, x27\]
index 14db65f7404ca383c2d57b3e2b9105b5424e38be..5d667f56c9cfcd90aee9cac08acea5b82368104c 100644 (file)
@@ -6,7 +6,7 @@
 
 Disassembly of section \.text:
 
-0000000000000000 <\.text>:
+0+ <\.text>:
  *[0-9a-f]+:   451b9ab1        smmla   z17\.s, z21\.b, z27\.b
  *[0-9a-f]+:   45009800        smmla   z0\.s, z0\.b, z0\.b
  *[0-9a-f]+:   45db9ab1        ummla   z17\.s, z21\.b, z27\.b
index a428633448900123d76edff641f03234a418f348..ea9cf2fb38a132dd75a26d89c406a9952b8747e0 100644 (file)
@@ -7,7 +7,7 @@
 
 Contents of the .eh_frame section:
 
-00000000 0000000000000010 00000000 CIE
+0+ 0+10 0+ CIE
   Version:               1
   Augmentation:          "zR"
   Code alignment factor: 4
@@ -16,17 +16,17 @@ Contents of the .eh_frame section:
   Augmentation data:     1b
   DW_CFA_def_cfa: r31 \(sp\) ofs 0
 
-00000014 0000000000000018 00000018 FDE cie=00000000 pc=0000000000000000..0000000000000008
-  DW_CFA_advance_loc: 4 to 0000000000000004
+0+14 0+18 0+18 FDE cie=0+ pc=0+\.\.0+8
+  DW_CFA_advance_loc: 4 to 0+4
   DW_CFA_GNU_window_save
-  DW_CFA_advance_loc: 4 to 0000000000000008
+  DW_CFA_advance_loc: 4 to 0+8
   DW_CFA_def_cfa_offset: 16
   DW_CFA_offset: r29 \(x29\) at cfa-16
   DW_CFA_offset: r30 \(x30\) at cfa-8
   DW_CFA_nop
   DW_CFA_nop
 
-00000030 0000000000000014 00000000 CIE
+0+30 0+14 0+ CIE
   Version:               1
   Augmentation:          "zRB"
   Code alignment factor: 4
@@ -38,17 +38,17 @@ Contents of the .eh_frame section:
   DW_CFA_nop
   DW_CFA_nop
 
-00000048 000000000000001c 0000001c FDE cie=00000030 pc=0000000000000008..0000000000000010
-  DW_CFA_advance_loc: 4 to 000000000000000c
+0+48 0+1(c|8) 0+1c FDE cie=0+30 pc=0+8\.\.0+10
+  DW_CFA_advance_loc: 4 to 0+c
   DW_CFA_GNU_window_save
-  DW_CFA_advance_loc: 4 to 0000000000000010
+  DW_CFA_advance_loc: 4 to 0+10
   DW_CFA_def_cfa_offset: 16
   DW_CFA_offset: r29 \(x29\) at cfa-16
   DW_CFA_offset: r30 \(x30\) at cfa-8
   DW_CFA_nop
   DW_CFA_nop
-  DW_CFA_nop
-  DW_CFA_nop
-  DW_CFA_nop
-  DW_CFA_nop
+#?  DW_CFA_nop
+#?  DW_CFA_nop
+#?  DW_CFA_nop
+#?  DW_CFA_nop
 
index 7ab0f2369dece1a71fc064ae38f6e273128bf074..cef533a7343da54d2c63fa73e6e7a289ac37cf93 100644 (file)
@@ -4,7 +4,7 @@
 
 Contents of the .eh_frame section:
 
-00000000 0000000000000010 00000000 CIE
+0+ 0+10 0+ CIE
   Version:               1
   Augmentation:          "zR"
   Code alignment factor: 4
@@ -13,14 +13,12 @@ Contents of the .eh_frame section:
   Augmentation data:     1b
   DW_CFA_def_cfa: r31 \(sp\) ofs 0
 
-00000014 0000000000000018 00000018 FDE cie=00000000 pc=0000000000000000..0000000000000008
-  DW_CFA_advance_loc: 4 to 0000000000000004
+0+14 0+18 0+18 FDE cie=0+ pc=0+\.\.0+8
+  DW_CFA_advance_loc: 4 to 0+4
   DW_CFA_GNU_window_save
-  DW_CFA_advance_loc: 4 to 0000000000000008
+  DW_CFA_advance_loc: 4 to 0+8
   DW_CFA_def_cfa_offset: 16
   DW_CFA_offset: r29 \(x29\) at cfa-16
   DW_CFA_offset: r30 \(x30\) at cfa-8
   DW_CFA_nop
   DW_CFA_nop
-
-
index 9ba990e0d889e814a6a701d3c46a4764b76405f4..c5a7685b3817bf24805c650aead5be51f7bf89ed 100644 (file)
@@ -4,10 +4,10 @@
 
 Disassembly of section \.text:
 
-0000000000000000 <.*>:
+0+ <.*>:
    0:  8a000000        and     x0, x0, x0
    4:  92400000        and     x0, x0, #0x1
    8:  d2800004        mov     x4, #0x0                        // #0
-                       8: R_AARCH64_MOVW_PREL_G0       tempy
+                       8: R_AARCH64_(P32_|)MOVW_PREL_G0        tempy
    c:  d2800011        mov     x17, #0x0                       // #0
-                       c: R_AARCH64_MOVW_PREL_G0       tempy2
+                       c: R_AARCH64_(P32_|)MOVW_PREL_G0        tempy2
index 4127ce7bbef6d0e378648b23ab1f2ad593abbd9d..f7a29194be2102229b4a065b5823fa7d3d390641 100644 (file)
@@ -4,12 +4,12 @@
 
 Disassembly of section \.text:
 
-0000000000000000 <.*>:
+0+ <.*>:
    0:  8a000000        and     x0, x0, x0
    4:  92400000        and     x0, x0, #0x1
    8:  f2800004        movk    x4, #0x0
-                       8: R_AARCH64_MOVW_PREL_G0_NC    tempy
+                       8: R_AARCH64_(P32_|)MOVW_PREL_G0_NC     tempy
    c:  f2800007        movk    x7, #0x0
-                       c: R_AARCH64_MOVW_PREL_G0_NC    tempy2
+                       c: R_AARCH64_(P32_|)MOVW_PREL_G0_NC     tempy2
   10:  f2800011        movk    x17, #0x0
-                       10: R_AARCH64_MOVW_PREL_G0_NC   tempy3
+                       10: R_AARCH64_(P32_|)MOVW_PREL_G0_NC    tempy3
index 1a161f8ea809e6793524ac88b333ff845bb392ca..63c91e0d7e8c3b234d37f586e79f9088bb2dc125 100644 (file)
@@ -4,10 +4,10 @@
 
 Disassembly of section \.text:
 
-0000000000000000 <.*>:
+0+ <.*>:
    0:  8a000000        and     x0, x0, x0
    4:  92400000        and     x0, x0, #0x1
    8:  d2a00004        movz    x4, #0x0, lsl #16
-                       8: R_AARCH64_MOVW_PREL_G1       tempy
+                       8: R_AARCH64_(P32_|)MOVW_PREL_G1        tempy
    c:  d2a00011        movz    x17, #0x0, lsl #16
-                       c: R_AARCH64_MOVW_PREL_G1       tempy2
+                       c: R_AARCH64_(P32_|)MOVW_PREL_G1        tempy2
index a7971586f74f5a07374f811fcfb50189f7842515..4ba95b89505e1f84f0cdc5dc522a5252a3a48984 100644 (file)
@@ -6,7 +6,7 @@
 
 Disassembly of section \.text:
 
-0000000000000000 <\.text>:
+0+ <\.text>:
  *[0-9a-f]+:   0420bc20        movprfx z0, z1
  *[0-9a-f]+:   64638040        bfdot   z0\.s, z2\.h, z3\.h
  *[0-9a-f]+:   0420bc20        movprfx z0, z1
index 197f69fae84949bc73e3919ea01f3d730995b2ff..88415ef098fee4dce7d0b753c390777fcf8caa4b 100644 (file)
@@ -5,7 +5,7 @@
 
 Disassembly of section \.text:
 
-0000000000000000 <\.text>:
+0+ <\.text>:
  *[0-9a-f]+:   0420bc11        movprfx z17, z0
  *[0-9a-f]+:   451b9ab1        smmla   z17\.s, z21\.b, z27\.b
  *[0-9a-f]+:   0420bc11        movprfx z17, z0
index f8be1c57c3287dd84a12d9554d1fffa6260c14f5..beb76b5ffefd970b436517deb3d76d496433deab 100644 (file)
@@ -6,7 +6,7 @@
 
 Disassembly of section \.text:
 
-0000000000000000 <\.text>:
+0+ <\.text>:
  *[0-9a-f]+:   0420bc20        movprfx z0, z1
  *[0-9a-f]+:   4542d020        adclb   z0\.d, z1\.d, z2\.d
  *[0-9a-f]+:   451bd2b1        adclb   z17\.s, z21\.s, z27\.s
This page took 0.047272 seconds and 4 git commands to generate.