I'm flying blind here, not having an s+core s3 insn set reference,
but this seems reasonably obvious from what is done by the assembler.
s3_do16_rpop does some mixing of imm and reg values to place in the
rpop reg field, but I'm not going to try to fix the disassembly
there.
* score-dis.c (print_insn_score16): Move rpush/rpop imm field
value adjustment so that it doesn't affect reg field too.
+2019-12-16 Alan Modra <amodra@gmail.com>
+
+ * score-dis.c (print_insn_score16): Move rpush/rpop imm field
+ value adjustment so that it doesn't affect reg field too.
+
2019-12-16 Alan Modra <amodra@gmail.com>
* crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
2019-12-16 Alan Modra <amodra@gmail.com>
* crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
- /* Check rpush rd, 0 and rpop! rd, 0.
- If reg = 0, then set to 32. */
- if (((given & 0x00007c00) == 0x00006c00
- || (given & 0x00007c00) == 0x00006800)
- && reg == 0)
- {
- reg = 32;
- }
-
func (stream, "%s", score_regnames[reg]);
break;
case 'd':
func (stream, "%s", score_regnames[reg]);
break;
case 'd':
+ /* Check rpush rd, 0 and rpop! rd, 0.
+ If 0, then print 32. */
+ if (((given & 0x00007c00) == 0x00006c00
+ || (given & 0x00007c00) == 0x00006800)
+ && reg == 0)
+ reg = 32;
+
if (*(c + 1) == '\0')
func (stream, "%ld", reg);
else
if (*(c + 1) == '\0')
func (stream, "%ld", reg);
else