+2020-03-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * testsuite/gas/i386/i386.exp: Run new tests.
+ * testsuite/gas/i386/lfence-byte.d: New file.
+ * testsuite/gas/i386/lfence-byte.e: Likewise.
+ * testsuite/gas/i386/lfence-byte.s: Likewise.
+ * testsuite/gas/i386/lfence-indbr-a.d: Likewise.
+ * testsuite/gas/i386/lfence-indbr-b.d: Likewise.
+ * testsuite/gas/i386/lfence-indbr-c.d: Likewise.
+ * testsuite/gas/i386/lfence-indbr.e: Likewise.
+ * testsuite/gas/i386/lfence-indbr.s: Likewise.
+ * testsuite/gas/i386/lfence-load.d: Likewise.
+ * testsuite/gas/i386/lfence-load.s: Likewise.
+ * testsuite/gas/i386/lfence-ret-a.d: Likewise.
+ * testsuite/gas/i386/lfence-ret-b.d: Likewise.
+ * testsuite/gas/i386/lfence-ret.s: Likewise.
+ * testsuite/gas/i386/x86-64-lfence-byte.d: Likewise.
+ * testsuite/gas/i386/x86-64-lfence-byte.e: Likewise.
+ * testsuite/gas/i386/x86-64-lfence-byte.s: Likewise.
+ * testsuite/gas/i386/x86-64-lfence-indbr-a.d: Likewise.
+ * testsuite/gas/i386/x86-64-lfence-indbr-b.d: Likewise.
+ * testsuite/gas/i386/x86-64-lfence-indbr-c.d: Likewise.
+ * testsuite/gas/i386/x86-64-lfence-indbr.e: Likewise.
+ * testsuite/gas/i386/x86-64-lfence-indbr.s: Likewise.
+ * testsuite/gas/i386/x86-64-lfence-load.d: Likewise.
+ * testsuite/gas/i386/x86-64-lfence-load.s: Likewise.
+ * testsuite/gas/i386/x86-64-lfence-ret-a.d: Likewise.
+ * testsuite/gas/i386/x86-64-lfence-ret-b.d: Likewise.
+
2020-03-11 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (lfence_after_load): New.
run_dump_test "align-branch-7"
run_dump_test "align-branch-8"
run_dump_test "align-branch-9"
+ run_dump_test "lfence-load"
+ run_dump_test "lfence-indbr-a"
+ run_dump_test "lfence-indbr-b"
+ run_dump_test "lfence-indbr-c"
+ run_dump_test "lfence-ret-a"
+ run_dump_test "lfence-ret-b"
+ run_dump_test "lfence-byte"
# These tests require support for 8 and 16 bit relocs,
# so we only run them for ELF and COFF targets.
run_dump_test "x86-64-align-branch-7"
run_dump_test "x86-64-align-branch-8"
run_dump_test "x86-64-align-branch-9"
+ run_dump_test "x86-64-lfence-load"
+ run_dump_test "x86-64-lfence-indbr-a"
+ run_dump_test "x86-64-lfence-indbr-b"
+ run_dump_test "x86-64-lfence-indbr-c"
+ run_dump_test "x86-64-lfence-ret-a"
+ run_dump_test "x86-64-lfence-ret-b"
+ run_dump_test "x86-64-lfence-byte"
if { ![istarget "*-*-aix*"]
&& ![istarget "*-*-beos*"]
--- /dev/null
+#as: -mlfence-before-indirect-branch=all -mlfence-before-ret=or
+#warning_output: lfence-byte.e
+#objdump: -dw
+#name: -mlfence-before-indirect-branch=all -mlfence-before-ret=or
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: f3 aa rep stos %al,%es:\(%edi\)
+ +[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f3 c3 repz ret
+ +[a-f0-9]+: f3 c3 repz ret
+ +[a-f0-9]+: f3 c3 repz ret
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: ff d0 call \*%eax
+ +[a-f0-9]+: f3 c3 repz ret
+ +[a-f0-9]+: 66 66 c3 data16 retw
+ +[a-f0-9]+: f3 c3 repz ret
+ +[a-f0-9]+: 9b fwait
+ +[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f3 c3 repz ret
+ +[a-f0-9]+: f3 c3 repz ret
+ +[a-f0-9]+: c3 ret
+ +[a-f0-9]+: f3 ff d0 repz call \*%eax
+#pass
--- /dev/null
+.*: Assembler messages:
+.*:5: Warning: `rep` skips -mlfence-before-ret on `ret`
+.*:7: Warning: `rep` skips -mlfence-before-ret on `ret`
+.*:10: Warning: constant directive skips -mlfence-before-ret and -mlfence-before-indirect-branch
+.*:13: Warning: `rep` skips -mlfence-before-ret on `ret`
+.*:17: Warning: constant directive skips -mlfence-before-ret and -mlfence-before-indirect-branch
+.*:17: Warning: `constant directive` skips -mlfence-before-ret on `ret`
+.*:20: Warning: constant directive skips -mlfence-before-ret and -mlfence-before-indirect-branch
+.*:20: Warning: `constant directive` skips -mlfence-before-indirect-branch on `call`
--- /dev/null
+ .text
+_start:
+ rep; stosb
+ rep ret
+ rep
+ ret
+ rep
+ ret
+ call *%eax
+ .byte 0xf3, 0xc3
+ .word 0x6666
+ .byte 0xc3
+ rep
+ ret
+ fwait
+ rep ret
+ .byte 0xf3
+ .byte 0xc3
+ ret
+ .byte 0xf3
+ call *%eax
+ .data
+ .byte 0
--- /dev/null
+#source: lfence-indbr.s
+#as: -mlfence-before-indirect-branch=all
+#warning_output: lfence-indbr.e
+#objdump: -dw
+#name: -mlfence-before-indirect-branch=all
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: ff d2 call \*%edx
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: ff e2 jmp \*%edx
+ +[a-f0-9]+: ff 12 call \*\(%edx\)
+ +[a-f0-9]+: ff 22 jmp \*\(%edx\)
+ +[a-f0-9]+: ff 15 00 00 00 00 call \*0x0
+ +[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0
+#pass
--- /dev/null
+#source: lfence-indbr.s
+#as: -mlfence-before-indirect-branch=register
+#objdump: -dw
+#name: -mlfence-before-indirect-branch=register
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: ff d2 call \*%edx
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: ff e2 jmp \*%edx
+ +[a-f0-9]+: ff 12 call \*\(%edx\)
+ +[a-f0-9]+: ff 22 jmp \*\(%edx\)
+ +[a-f0-9]+: ff 15 00 00 00 00 call \*0x0
+ +[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0
+#pass
--- /dev/null
+#source: lfence-indbr.s
+#as: -mlfence-before-indirect-branch=memory
+#warning_output: lfence-indbr.e
+#objdump: -dw
+#name: -mlfence-before-indirect-branch=memory
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: ff d2 call \*%edx
+ +[a-f0-9]+: ff e2 jmp \*%edx
+ +[a-f0-9]+: ff 12 call \*\(%edx\)
+ +[a-f0-9]+: ff 22 jmp \*\(%edx\)
+ +[a-f0-9]+: ff 15 00 00 00 00 call \*0x0
+ +[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0
+#pass
--- /dev/null
+.*: Assembler messages:
+.*:5: Warning: indirect `call` with memory operand should be avoided
+.*:6: Warning: indirect `jmp` with memory operand should be avoided
+.*:7: Warning: indirect `call` with memory operand should be avoided
+.*:8: Warning: indirect `jmp` with memory operand should be avoided
--- /dev/null
+ .text
+_start:
+ call *%edx
+ jmp *%edx
+ call *(%edx)
+ jmp *(%edx)
+ call *foo
+ jmp *foo
--- /dev/null
+#as: -mlfence-after-load=yes
+#objdump: -dw
+#name: -mlfence-after-load=yes
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr 0x0\(%ebp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 0f 01 55 00 lgdtl 0x0\(%ebp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 0f c7 75 00 vmptrld 0x0\(%ebp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 66 0f c7 75 00 vmclear 0x0\(%ebp\)
+ +[a-f0-9]+: d9 55 00 fsts 0x0\(%ebp\)
+ +[a-f0-9]+: d9 45 00 flds 0x0\(%ebp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: db 55 00 fistl 0x0\(%ebp\)
+ +[a-f0-9]+: df 55 00 fists 0x0\(%ebp\)
+ +[a-f0-9]+: db 45 00 fildl 0x0\(%ebp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: df 45 00 filds 0x0\(%ebp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 9b dd 75 00 fsave 0x0\(%ebp\)
+ +[a-f0-9]+: dd 65 00 frstor 0x0\(%ebp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: df 45 00 filds 0x0\(%ebp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: df 4d 00 fisttps 0x0\(%ebp\)
+ +[a-f0-9]+: d9 65 00 fldenv 0x0\(%ebp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 9b d9 75 00 fstenv 0x0\(%ebp\)
+ +[a-f0-9]+: d8 45 00 fadds 0x0\(%ebp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: d8 04 24 fadds \(%esp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: d8 c3 fadd %st\(3\),%st
+ +[a-f0-9]+: d8 01 fadds \(%ecx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: df 01 filds \(%ecx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: df 11 fists \(%ecx\)
+ +[a-f0-9]+: 0f ae 29 xrstor \(%ecx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 0f 18 01 prefetchnta \(%ecx\)
+ +[a-f0-9]+: 0f c7 09 cmpxchg8b \(%ecx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 41 inc %ecx
+ +[a-f0-9]+: 0f 01 10 lgdtl \(%eax\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 0f 0f 66 02 b0 pfcmpeq 0x2\(%esi\),%mm4
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 8f 00 popl \(%eax\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 58 pop %eax
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 66 d1 11 rclw \(%ecx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f7 01 01 00 00 00 testl \$0x1,\(%ecx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: ff 01 incl \(%ecx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f7 11 notl \(%ecx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f7 31 divl \(%ecx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f7 21 mull \(%ecx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f7 39 idivl \(%ecx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f7 29 imull \(%ecx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 8d 04 40 lea \(%eax,%eax,2\),%eax
+ +[a-f0-9]+: c9 leave
+ +[a-f0-9]+: 6e outsb %ds:\(%esi\),\(%dx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: ac lods %ds:\(%esi\),%al
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f3 a5 rep movsl %ds:\(%esi\),%es:\(%edi\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f3 af repz scas %es:\(%edi\),%eax
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f3 a7 repz cmpsl %es:\(%edi\),%ds:\(%esi\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f3 ad rep lods %ds:\(%esi\),%eax
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 83 00 01 addl \$0x1,\(%eax\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 0f ba 20 01 btl \$0x1,\(%eax\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 0f c1 03 xadd %eax,\(%ebx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 0f c1 c3 xadd %eax,%ebx
+ +[a-f0-9]+: 87 03 xchg %eax,\(%ebx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 93 xchg %eax,%ebx
+ +[a-f0-9]+: 39 45 40 cmp %eax,0x40\(%ebp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 3b 45 40 cmp 0x40\(%ebp\),%eax
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 01 45 40 add %eax,0x40\(%ebp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 03 00 add \(%eax\),%eax
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 85 45 40 test %eax,0x40\(%ebp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 85 45 40 test %eax,0x40\(%ebp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+#pass
--- /dev/null
+ .text
+_start:
+ vldmxcsr (%ebp)
+ lgdt (%ebp)
+ vmptrld (%ebp)
+ vmclear (%ebp)
+ fsts (%ebp)
+ flds (%ebp)
+ fistl (%ebp)
+ fists (%ebp)
+ fildl (%ebp)
+ filds (%ebp)
+ fsave (%ebp)
+ frstor (%ebp)
+ filds (%ebp)
+ fisttps (%ebp)
+ fldenv (%ebp)
+ fstenv (%ebp)
+ fadds (%ebp)
+ fadds (%esp)
+ fadd %st(3),%st
+ fadds (%ecx)
+ filds (%ecx)
+ fists (%ecx)
+ xrstor (%ecx)
+ prefetchnta (%ecx)
+ cmpxchg8b (%ecx)
+ incl %ecx
+ lgdt (%eax)
+ pfcmpeq 2(%esi),%mm4
+ popl (%eax)
+ popl %eax
+ rclw (%ecx)
+ testl $1,(%ecx)
+ incl (%ecx)
+ notl (%ecx)
+ divl (%ecx)
+ mull (%ecx)
+ idivl (%ecx)
+ imull (%ecx)
+ leal (%eax,%eax,2), %eax
+ leave
+ outsb
+ lodsb
+ rep movsl
+ rep scasl
+ rep cmpsl
+ rep lodsl
+ addl $1, (%eax)
+ btl $1, (%eax)
+ xadd %eax,(%ebx)
+ xadd %eax,%ebx
+ xchg %eax,(%ebx)
+ xchg %eax,%ebx
+ cmp %eax,0x40(%ebp)
+ cmp 0x40(%ebp),%eax
+ add %eax,0x40(%ebp)
+ add (%eax),%eax
+ test %eax,0x40(%ebp)
+ test 0x40(%ebp),%eax
--- /dev/null
+#source: lfence-ret.s
+#as: -mlfence-before-ret=or
+#objdump: -dw
+#name: -mlfence-before-ret=or
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: c3 ret
+ +[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: c2 1e 00 ret \$0x1e
+#pass
--- /dev/null
+#source: lfence-ret.s
+#as: -mlfence-before-ret=not
+#objdump: -dw
+#name: -mlfence-before-ret=not
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: f7 14 24 notl \(%esp\)
+ +[a-f0-9]+: f7 14 24 notl \(%esp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: c3 ret
+ +[a-f0-9]+: f7 14 24 notl \(%esp\)
+ +[a-f0-9]+: f7 14 24 notl \(%esp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: c2 1e 00 ret \$0x1e
+#pass
--- /dev/null
+ .text
+_start:
+ ret
+ ret $30
--- /dev/null
+#as: -mlfence-before-indirect-branch=all -mlfence-before-ret=or
+#warning_output: x86-64-lfence-byte.e
+#objdump: -dw
+#name: x86-64 -mlfence-before-indirect-branch=all -mlfence-before-ret=or
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: f3 aa rep stos %al,%es:\(%rdi\)
+ +[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f3 c3 repz retq
+ +[a-f0-9]+: f3 c3 repz retq
+ +[a-f0-9]+: f3 c3 repz retq
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: ff d0 callq \*%rax
+ +[a-f0-9]+: f3 c3 repz retq
+ +[a-f0-9]+: 66 66 c3 data16 retw
+ +[a-f0-9]+: f3 c3 repz retq
+ +[a-f0-9]+: 9b fwait
+ +[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f3 c3 repz retq
+ +[a-f0-9]+: f3 c3 repz retq
+ +[a-f0-9]+: c3 retq
+ +[a-f0-9]+: f3 ff d0 repz callq \*%rax
+#pass
--- /dev/null
+.*: Assembler messages:
+.*:5: Warning: `rep` skips -mlfence-before-ret on `ret`
+.*:7: Warning: `rep` skips -mlfence-before-ret on `ret`
+.*:10: Warning: constant directive skips -mlfence-before-ret and -mlfence-before-indirect-branch
+.*:13: Warning: `rep` skips -mlfence-before-ret on `ret`
+.*:17: Warning: constant directive skips -mlfence-before-ret and -mlfence-before-indirect-branch
+.*:17: Warning: `constant directive` skips -mlfence-before-ret on `ret`
+.*:20: Warning: constant directive skips -mlfence-before-ret and -mlfence-before-indirect-branch
+.*:20: Warning: `constant directive` skips -mlfence-before-indirect-branch on `call`
--- /dev/null
+ .text
+_start:
+ rep; stosb
+ rep ret
+ rep
+ ret
+ rep
+ ret
+ call *%rax
+ .byte 0xf3, 0xc3
+ .word 0x6666
+ .byte 0xc3
+ rep
+ ret
+ fwait
+ rep ret
+ .byte 0xf3
+ .byte 0xc3
+ ret
+ .byte 0xf3
+ call *%rax
+ .data
+ .byte 0
--- /dev/null
+#source: x86-64-lfence-indbr.s
+#as: -mlfence-before-indirect-branch=all
+#warning_output: x86-64-lfence-indbr.e
+#objdump: -dw
+#name: x86-64 -mlfence-before-indirect-branch=all
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: ff d2 callq \*%rdx
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: ff e2 jmpq \*%rdx
+ +[a-f0-9]+: ff 12 callq \*\(%rdx\)
+ +[a-f0-9]+: ff 22 jmpq \*\(%rdx\)
+ +[a-f0-9]+: ff 14 25 00 00 00 00 callq \*0x0
+ +[a-f0-9]+: ff 24 25 00 00 00 00 jmpq \*0x0
+#pass
--- /dev/null
+#source: x86-64-lfence-indbr.s
+#as: -mlfence-before-indirect-branch=register
+#objdump: -dw
+#name: x86-64 -mlfence-before-indirect-branch=register
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: ff d2 callq \*%rdx
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: ff e2 jmpq \*%rdx
+ +[a-f0-9]+: ff 12 callq \*\(%rdx\)
+ +[a-f0-9]+: ff 22 jmpq \*\(%rdx\)
+ +[a-f0-9]+: ff 14 25 00 00 00 00 callq \*0x0
+ +[a-f0-9]+: ff 24 25 00 00 00 00 jmpq \*0x0
+#pass
--- /dev/null
+#source: x86-64-lfence-indbr.s
+#as: -mlfence-before-indirect-branch=memory
+#warning_output: x86-64-lfence-indbr.e
+#objdump: -dw
+#name: x86-64 -mlfence-before-indirect-branch=memory
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: ff d2 callq \*%rdx
+ +[a-f0-9]+: ff e2 jmpq \*%rdx
+ +[a-f0-9]+: ff 12 callq \*\(%rdx\)
+ +[a-f0-9]+: ff 22 jmpq \*\(%rdx\)
+ +[a-f0-9]+: ff 14 25 00 00 00 00 callq \*0x0
+ +[a-f0-9]+: ff 24 25 00 00 00 00 jmpq \*0x0
+#pass
--- /dev/null
+.*: Assembler messages:
+.*:5: Warning: indirect `call` with memory operand should be avoided
+.*:6: Warning: indirect `jmp` with memory operand should be avoided
+.*:7: Warning: indirect `call` with memory operand should be avoided
+.*:8: Warning: indirect `jmp` with memory operand should be avoided
--- /dev/null
+ .text
+_start:
+ call *%rdx
+ jmp *%rdx
+ call *(%rdx)
+ jmp *(%rdx)
+ call *foo
+ jmp *foo
--- /dev/null
+#as: -mlfence-after-load=yes
+#objdump: -dw
+#name: x86-64 -mlfence-after-load=yes
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr 0x0\(%rbp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 0f 01 55 00 lgdt 0x0\(%rbp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 0f c7 75 00 vmptrld 0x0\(%rbp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 66 0f c7 75 00 vmclear 0x0\(%rbp\)
+ +[a-f0-9]+: d9 55 00 fsts 0x0\(%rbp\)
+ +[a-f0-9]+: d9 45 00 flds 0x0\(%rbp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: db 55 00 fistl 0x0\(%rbp\)
+ +[a-f0-9]+: df 55 00 fists 0x0\(%rbp\)
+ +[a-f0-9]+: db 45 00 fildl 0x0\(%rbp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: df 45 00 filds 0x0\(%rbp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 9b dd 75 00 fsave 0x0\(%rbp\)
+ +[a-f0-9]+: dd 65 00 frstor 0x0\(%rbp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: df 45 00 filds 0x0\(%rbp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: df 4d 00 fisttps 0x0\(%rbp\)
+ +[a-f0-9]+: d9 65 00 fldenv 0x0\(%rbp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 9b d9 75 00 fstenv 0x0\(%rbp\)
+ +[a-f0-9]+: d8 45 00 fadds 0x0\(%rbp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: d8 04 24 fadds \(%rsp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: d8 c3 fadd %st\(3\),%st
+ +[a-f0-9]+: d8 01 fadds \(%rcx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: df 01 filds \(%rcx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: df 11 fists \(%rcx\)
+ +[a-f0-9]+: 0f ae 29 xrstor \(%rcx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 0f 18 01 prefetchnta \(%rcx\)
+ +[a-f0-9]+: 0f c7 09 cmpxchg8b \(%rcx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 48 0f c7 09 cmpxchg16b \(%rcx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: ff c1 inc %ecx
+ +[a-f0-9]+: 0f 01 10 lgdt \(%rax\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 0f 0f 66 02 b0 pfcmpeq 0x2\(%rsi\),%mm4
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 8f 00 popq \(%rax\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 58 pop %rax
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 66 d1 11 rclw \(%rcx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f7 01 01 00 00 00 testl \$0x1,\(%rcx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: ff 01 incl \(%rcx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f7 11 notl \(%rcx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f7 31 divl \(%rcx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f7 21 mull \(%rcx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f7 39 idivl \(%rcx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f7 29 imull \(%rcx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 48 8d 04 40 lea \(%rax,%rax,2\),%rax
+ +[a-f0-9]+: c9 leaveq
+ +[a-f0-9]+: 6e outsb %ds:\(%rsi\),\(%dx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: ac lods %ds:\(%rsi\),%al
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f3 a5 rep movsl %ds:\(%rsi\),%es:\(%rdi\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f3 af repz scas %es:\(%rdi\),%eax
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f3 a7 repz cmpsl %es:\(%rdi\),%ds:\(%rsi\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: f3 ad rep lods %ds:\(%rsi\),%eax
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 41 83 03 01 addl \$0x1,\(%r11\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 41 0f ba 23 01 btl \$0x1,\(%r11\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 48 0f c1 03 xadd %rax,\(%rbx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 48 0f c1 c3 xadd %rax,%rbx
+ +[a-f0-9]+: 48 87 03 xchg %rax,\(%rbx\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 48 93 xchg %rax,%rbx
+ +[a-f0-9]+: 48 39 45 40 cmp %rax,0x40\(%rbp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 48 3b 45 40 cmp 0x40\(%rbp\),%rax
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 48 01 45 40 add %rax,0x40\(%rbp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 48 03 00 add \(%rax\),%rax
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 48 85 45 40 test %rax,0x40\(%rbp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: 48 85 45 40 test %rax,0x40\(%rbp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+#pass
--- /dev/null
+ .text
+_start:
+ vldmxcsr (%rbp)
+ lgdt (%rbp)
+ vmptrld (%rbp)
+ vmclear (%rbp)
+ fsts (%rbp)
+ flds (%rbp)
+ fistl (%rbp)
+ fists (%rbp)
+ fildl (%rbp)
+ filds (%rbp)
+ fsave (%rbp)
+ frstor (%rbp)
+ filds (%rbp)
+ fisttps (%rbp)
+ fldenv (%rbp)
+ fstenv (%rbp)
+ fadds (%rbp)
+ fadds (%rsp)
+ fadd %st(3),%st
+ fadds (%rcx)
+ filds (%rcx)
+ fists (%rcx)
+ xrstor (%rcx)
+ prefetchnta (%rcx)
+ cmpxchg8b (%rcx)
+ cmpxchg16b (%rcx)
+ incl %ecx
+ lgdt (%rax)
+ pfcmpeq 2(%rsi),%mm4
+ popq (%rax)
+ popq %rax
+ rclw (%rcx)
+ testl $1,(%rcx)
+ incl (%rcx)
+ notl (%rcx)
+ divl (%rcx)
+ mull (%rcx)
+ idivl (%rcx)
+ imull (%rcx)
+ leaq (%rax,%rax,2), %rax
+ leave
+ outsb
+ lodsb
+ rep movsl
+ rep scasl
+ rep cmpsl
+ rep lodsl
+ addl $1, (%r11)
+ btl $1, (%r11)
+ xadd %rax,(%rbx)
+ xadd %rax,%rbx
+ xchg %rax,(%rbx)
+ xchg %rax,%rbx
+ cmp %rax,0x40(%rbp)
+ cmp 0x40(%rbp),%rax
+ add %rax,0x40(%rbp)
+ add (%rax),%rax
+ test %rax,0x40(%rbp)
+ test 0x40(%rbp),%rax
--- /dev/null
+#source: lfence-ret.s
+#as: -mlfence-before-ret=or
+#objdump: -dw
+#name: x86-64 -mlfence-before-ret=or
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: c3 retq
+ +[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: c2 1e 00 retq \$0x1e
+#pass
--- /dev/null
+#source: lfence-ret.s
+#as: -mlfence-before-ret=not
+#objdump: -dw
+#name: x86-64 -mlfence-before-ret=not
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
+ +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: c3 retq
+ +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
+ +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
+ +[a-f0-9]+: 0f ae e8 lfence
+ +[a-f0-9]+: c2 1e 00 retq \$0x1e
+#pass
projects / deliverable / binutils-gdb.git / commitdiff
