+2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
+ Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB,
+ M_SCDP_AB>: New cases and expansions for paired instructions.
+ * testsuite/gas/mips/llpscp-32.s: New test source.
+ * testsuite/gas/mips/llpscp-64.s: Likewise.
+ * testsuite/gas/mips/llpscp-32.d: New test.
+ * testsuite/gas/mips/llpscp-64.d: Likewise.
+ * testsuite/gas/mips/mips.exp: Run the new tests.
+ * testsuite/gas/mips/r6.s: Add new instructions to test source.
+ * testsuite/gas/mips/r6-64.s: Likewise.
+ * testsuite/gas/mips/r6-64-n32.d: Check new instructions.
+ * testsuite/gas/mips/r6-64-n64.d: Likewise.
+ * testsuite/gas/mips/r6-n32.d: Likewise.
+ * testsuite/gas/mips/r6-n64.d: Likwwise.
+ * testsuite/gas/mips/r6.d: Likewise.
+
2019-04-26 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24485
int imm = 0;
int ust = 0;
int lp = 0;
+ int ll_sc_paired = 0;
bfd_boolean large_offset;
int off;
int hold_mips_optimize;
offbits = 12;
lp = 1;
goto ld;
+ case M_LLDP_AB:
+ case M_LLWP_AB:
+ s = ip->insn_mo->name;
+ fmt = "t,d,s";
+ ll_sc_paired = 1;
+ offbits = 0;
+ goto ld;
case M_LWM_AB:
gas_assert (mips_opts.micromips);
s = "lwm";
goto ld_st;
ld:
- /* We don't want to use $0 as tempreg. */
- if (op[2] == op[0] + lp || op[0] + lp == ZERO)
- goto ld_st;
+ /* Try to use one the the load registers to compute the base address.
+ We don't want to use $0 as tempreg. */
+ if (ll_sc_paired)
+ {
+ if ((op[0] == ZERO && op[3] == op[1])
+ || (op[1] == ZERO && op[3] == op[0])
+ || (op[0] == ZERO && op[1] == ZERO))
+ goto ld_st;
+ else if (op[0] != op[3] && op[0] != ZERO)
+ tempreg = op[0];
+ else
+ tempreg = op[1];
+ }
else
- tempreg = op[0] + lp;
+ {
+ if (op[2] == op[0] + lp || op[0] + lp == ZERO)
+ goto ld_st;
+ else
+ tempreg = op[0] + lp;
+ }
goto ld_noat;
case M_SB_AB:
: ISA_IS_R6 (mips_opts.isa) ? 9
: 16);
goto ld_st;
+ case M_SCDP_AB:
+ case M_SCWP_AB:
+ s = ip->insn_mo->name;
+ fmt = "t,d,s";
+ ll_sc_paired = 1;
+ offbits = 0;
+ goto ld_st;
case M_CACHE_AB:
s = "cache";
fmt = (mips_opts.micromips ? "k,~(b)"
ld_st:
tempreg = AT;
ld_noat:
- breg = op[2];
+ breg = ll_sc_paired ? op[3] : op[2];
if (small_offset_p (0, align, 16))
{
/* The first case exists for M_LD_AB and M_SD_AB, which are
else if (small_offset_p (0, align, offbits))
{
if (offbits == 0)
- macro_build (NULL, s, fmt, op[0], breg);
+ {
+ if (ll_sc_paired)
+ macro_build (NULL, s, fmt, op[0], op[1], breg);
+ else
+ macro_build (NULL, s, fmt, op[0], breg);
+ }
else
macro_build (NULL, s, fmt, op[0],
(int) offset_expr.X_add_number, breg);
tempreg, breg, -1, offset_reloc[0],
offset_reloc[1], offset_reloc[2]);
if (offbits == 0)
- macro_build (NULL, s, fmt, op[0], tempreg);
+ {
+ if (ll_sc_paired)
+ macro_build (NULL, s, fmt, op[0], op[1], tempreg);
+ else
+ macro_build (NULL, s, fmt, op[0], tempreg);
+ }
else
macro_build (NULL, s, fmt, op[0], 0, tempreg);
}
if (offset_expr.X_add_number != 0)
macro_build (&offset_expr, ADDRESS_ADDI_INSN,
"t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
- macro_build (NULL, s, fmt, op[0], tempreg);
+ if (ll_sc_paired)
+ macro_build (NULL, s, fmt, op[0], op[1], tempreg);
+ else
+ macro_build (NULL, s, fmt, op[0], tempreg);
}
else if (offbits == 16)
macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
tempreg, tempreg, breg);
if (offbits == 0)
- macro_build (NULL, s, fmt, op[0], tempreg);
+ {
+ if (ll_sc_paired)
+ macro_build (NULL, s, fmt, op[0], op[1], tempreg);
+ else
+ macro_build (NULL, s, fmt, op[0], tempreg);
+ }
else
macro_build (NULL, s, fmt, op[0], 0, tempreg);
}
--- /dev/null
+#objdump: -dr
+#name: Paired LL/SC for mips32r6
+#as: -32
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <test>:
+ 0: 7c821876 llwp v0,v1,a0
+ 4: 7c821876 llwp v0,v1,a0
+ 8: 24821234 addiu v0,a0,4660
+ c: 7c420076 llwp v0,zero,v0
+ 10: 24430000 addiu v1,v0,0
+ 10: R_MIPS_LO16 .data
+ 14: 7c621876 llwp v0,v1,v1
+ 18: 3c020123 lui v0,0x123
+ 1c: 00431021 addu v0,v0,v1
+ 20: 24424567 addiu v0,v0,17767
+ 24: 7c421876 llwp v0,v1,v0
+ 28: 3c010000 lui at,0x0
+ 28: R_MIPS_HI16 .data
+ 2c: 24210000 addiu at,at,0
+ 2c: R_MIPS_LO16 .data
+ 30: 00240821 addu at,at,a0
+ 34: 7c200076 llwp zero,zero,at
+ 38: 7c821866 scwp v0,v1,a0
+ 3c: 7c821866 scwp v0,v1,a0
+ 40: 24811234 addiu at,a0,4660
+ 44: 7c220066 scwp v0,zero,at
+ 48: 24410000 addiu at,v0,0
+ 48: R_MIPS_LO16 .data
+ 4c: 7c221866 scwp v0,v1,at
+ 50: 3c010123 lui at,0x123
+ 54: 00230821 addu at,at,v1
+ 58: 24214567 addiu at,at,17767
+ 5c: 7c221866 scwp v0,v1,at
+ 60: 3c010000 lui at,0x0
+ 60: R_MIPS_HI16 .data
+ 64: 24210000 addiu at,at,0
+ 64: R_MIPS_LO16 .data
+ 68: 00240821 addu at,at,a0
+ 6c: 7c200066 scwp zero,zero,at
+ ...
--- /dev/null
+ .text
+test:
+ llwp $2, $3, $4 /* No macro expansion needed */
+ llwp $2, $3, 0($4)
+ llwp $2, $0, 0x1234($4)
+ llwp $2, $3, %lo(sync_mem)($2)
+ llwp $2, $3, 0xffffffff01234567($3)
+ llwp $0, $0, sync_mem($4)
+
+ scwp $2, $3, $4 /* No macro expansion needed */
+ scwp $2, $3, 0($4)
+ scwp $2, $0, 0x1234($4)
+ scwp $2, $3, %lo(sync_mem)($2)
+ scwp $2, $3, 0xffffffff01234567($3)
+ scwp $0, $0, sync_mem($4)
+ .space 8
+
+ .data
+sync_mem:
+ .word
+ .word
+
+ .space 8
--- /dev/null
+#objdump: -dr
+#name: Paired LL/SC for mips64r6
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <test>:
+ 0: 7c821877 lldp v0,v1,a0
+ 4: 7c821877 lldp v0,v1,a0
+ 8: 24821234 addiu v0,a0,4660
+ c: 7c420077 lldp v0,zero,v0
+ 10: 24430000 addiu v1,v0,0
+ 10: R_MIPS_LO16 .data
+ 14: 7c621877 lldp v0,v1,v1
+ 18: 3c020123 lui v0,0x123
+ 1c: 00431021 addu v0,v0,v1
+ 20: 24424567 addiu v0,v0,17767
+ 24: 7c421877 lldp v0,v1,v0
+ 28: 3c010000 lui at,0x0
+ 28: R_MIPS_HI16 .data
+ 2c: 24210000 addiu at,at,0
+ 2c: R_MIPS_LO16 .data
+ 30: 00240821 addu at,at,a0
+ 34: 7c200077 lldp zero,zero,at
+ 38: 7c821867 scdp v0,v1,a0
+ 3c: 7c821867 scdp v0,v1,a0
+ 40: 24811234 addiu at,a0,4660
+ 44: 7c220067 scdp v0,zero,at
+ 48: 24410000 addiu at,v0,0
+ 48: R_MIPS_LO16 .data
+ 4c: 7c221867 scdp v0,v1,at
+ 50: 3c010123 lui at,0x123
+ 54: 00230821 addu at,at,v1
+ 58: 24214567 addiu at,at,17767
+ 5c: 7c221867 scdp v0,v1,at
+ 60: 3c010000 lui at,0x0
+ 60: R_MIPS_HI16 .data
+ 64: 24210000 addiu at,at,0
+ 64: R_MIPS_LO16 .data
+ 68: 00240821 addu at,at,a0
+ 6c: 7c200067 scdp zero,zero,at
+ ...
--- /dev/null
+ .text
+test:
+ lldp $2, $3, $4 /* No macro expansion needed */
+ lldp $2, $3, 0($4)
+ lldp $2, $0, 0x1234($4)
+ lldp $2, $3, %lo(sync_mem)($2)
+ lldp $2, $3, 0xffffffff01234567($3)
+ lldp $0, $0, sync_mem($4)
+
+ scdp $2, $3, $4 /* No macro expansion needed */
+ scdp $2, $3, 0($4)
+ scdp $2, $0, 0x1234($4)
+ scdp $2, $3, %lo(sync_mem)($2)
+ scdp $2, $3, 0xffffffff01234567($3)
+ scdp $0, $0, sync_mem($4)
+
+ .space 8
+
+ .data
+sync_mem:
+ .word
+ .word
+ .space 8
run_dump_test_arches "ginv" [mips_arch_list_matching mips32r6]
run_dump_test_arches "ginv-err" [mips_arch_list_matching mips32r6]
+
+ run_dump_test_arches "llpscp-32" [mips_arch_list_matching mips32r6]
+ run_dump_test_arch "llpscp-64" "" mips64r6
}
0+00a4 <[^>]*> ec9a0000 ldpc a0,fff000a0 <[^>]*>
0+00a8 <[^>]*> ec99ffff ldpc a0,001000a0 <[^>]*>
0+00ac <[^>]*> ec99ffff ldpc a0,001000a0 <[^>]*>
+0+00b0 <[^>]*> 7cc52077 lldp a1,a0,a2
+0+00b4 <[^>]*> 7cc52067 scdp a1,a0,a2
\.\.\.
0+00a4 <[^>]*> ec9a0000 ldpc a0,f+ff000a0 <[^>]*>
0+00a8 <[^>]*> ec99ffff ldpc a0,0+01000a0 <[^>]*>
0+00ac <[^>]*> ec99ffff ldpc a0,0+01000a0 <[^>]*>
+0+00b0 <[^>]*> 7cc52077 lldp a1,a0,a2
+0+00b4 <[^>]*> 7cc52067 scdp a1,a0,a2
\.\.\.
ld $4, (131071 << 3)($pc)
.align 3
1:
- nop
+ lldp $5, $4, $6
+ scdp $5, $4, $6
+ nop
nop
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
0+05a0 <[^>]*> 41620024 dvp v0
0+05a4 <[^>]*> 04170000 sigrie 0x0
0+05a8 <[^>]*> 0417ffff sigrie 0xffff
+0+05ac <[^>]*> 7cc52076 llwp a1,a0,a2
+0+05b0 <[^>]*> 7cc52066 scwp a1,a0,a2
+
\.\.\.
0+05a0 <[^>]*> 41620024 dvp v0
0+05a4 <[^>]*> 04170000 sigrie 0x0
0+05a8 <[^>]*> 0417ffff sigrie 0xffff
+0+05ac <[^>]*> 7cc52076 llwp a1,a0,a2
+0+05b0 <[^>]*> 7cc52066 scwp a1,a0,a2
\.\.\.
0+05a0 <[^>]*> 41620024 dvp v0
0+05a4 <[^>]*> 04170000 sigrie 0x0
0+05a8 <[^>]*> 0417ffff sigrie 0xffff
+0+05ac <[^>]*> 7cc52076 llwp a1,a0,a2
+0+05b0 <[^>]*> 7cc52066 scwp a1,a0,a2
\.\.\.
sigrie 0
sigrie 0xffff
+ llwp $5, $4, $6
+ scwp $5, $4, $6
+
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 2
.space 8
+2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
+ Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
+ (M_SCWP_AB, M_SCDP_AB): Likewise.
+
2019-04-25 Maciej W. Rozycki <macro@linux-mips.org>
* opcode/mips.h: Update comment for MIPS32 CODE20 operand.
M_LI_SS,
M_LL_AB,
M_LLD_AB,
+ M_LLDP_AB,
M_LLE_AB,
+ M_LLWP_AB,
M_LQ_AB,
M_LW_AB,
M_LWE_AB,
M_SAAD_AB,
M_SC_AB,
M_SCD_AB,
+ M_SCDP_AB,
M_SCE_AB,
+ M_SCWP_AB,
M_SD_AB,
M_SDC1_AB,
M_SDC2_AB,
+2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
+ Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
+
2019-04-24 John Darrington <john@darrington.wattle.id.au>
* s12z-opc.h: Add extern "C" bracketing to help
{"lld", "t,+j(b)", 0x7c000037, 0xfc00007f, WR_1|RD_3|LM, 0, I69, 0, 0 },
{"lld", "t,o(b)", 0xd0000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, EE|I69 },
{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, 0, EE },
+{"lldp", "t,d,s", 0x7c000077, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I69, 0, 0 },
+{"lldp", "t,d,A(b)", 0, (int) M_LLDP_AB, INSN_MACRO, 0, I69, 0, 0 },
+{"llwp", "t,d,s", 0x7c000076, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I37, 0, 0 },
+{"llwp", "t,d,A(b)", 0, (int) M_LLWP_AB, INSN_MACRO, 0, I37, 0, 0 },
{"lq", "t,o(b)", 0x78000000, 0xfc000000, WR_1|RD_3|LM, 0, MMI, 0, 0 },
{"lq", "t,A(b)", 0, (int) M_LQ_AB, INSN_MACRO, 0, MMI, 0, 0 },
{"lqc2", "+7,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_C2|LM, 0, EE, 0, 0 },
{"scd", "t,+j(b)", 0x7c000027, 0xfc00007f, MOD_1|RD_3|SM, 0, I69, 0, 0 },
{"scd", "t,o(b)", 0xf0000000, 0xfc000000, MOD_1|RD_3|SM, 0, I3, 0, EE|I69 },
{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3, 0, EE },
+{"scdp", "t,d,s", 0x7c000067, 0xfc0007ff, MOD_1|RD_2|RD_3|SM, 0, I69, 0, 0 },
+{"scdp", "t,d,A(b)", 0, (int) M_SCDP_AB, INSN_MACRO, 0, I69, 0, 0 },
+{"scwp", "t,d,s", 0x7c000066, 0xfc0007ff, MOD_1|RD_2|RD_3|SM, 0, I37, 0, 0 },
+{"scwp", "t,d,A(b)", 0, (int) M_SCWP_AB, INSN_MACRO, 0, I37, 0, 0 },
/* The macro has to be first to handle o32 correctly. */
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1, 0, 0 },
{"sd", "t,o(b)", 0xfc000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, 0 },
projects / deliverable / binutils-gdb.git / commitdiff
