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[AArch64] Add separate feature flag for weaker release consistent load insns
authorSzabolcs Nagy <szabolcs.nagy@arm.com>
Wed, 4 Jan 2017 12:27:10 +0000 (12:27 +0000)
committerSzabolcs Nagy <szabolcs.nagy@arm.com>
Wed, 4 Jan 2017 12:31:08 +0000 (12:31 +0000)
The weaker release consistency support of ARMv8.3-A is allowed as an optional
extension for ARMv8.2-A, so separate command line option and feature flag is
added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on.

opcodes/
* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
(aarch64_opcode_table): Use RCPC_INSN.

include/
* opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
(AARCH64_ARCH_V8_3): Update.

gas/
* config/tc-aarch64.c (aarch64_features): Add rcpc.
* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.d: This.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.s: This.
* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.

gas/ChangeLog patch | blob | blame | history
gas/config/tc-aarch64.c patch | blob | blame | history
gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d [deleted file] patch | blob | blame | history
gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.s [deleted file] patch | blob | blame | history
gas/testsuite/gas/aarch64/ldst-rcpc-armv8_2.d [new file with mode: 0644] patch | blob
gas/testsuite/gas/aarch64/ldst-rcpc.d [new file with mode: 0644] patch | blob
gas/testsuite/gas/aarch64/ldst-rcpc.s [new file with mode: 0644] patch | blob
include/ChangeLog patch | blob | blame | history
include/opcode/aarch64.h patch | blob | blame | history
opcodes/ChangeLog patch | blob | blame | history
opcodes/aarch64-tbl.h patch | blob | blame | history

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 1e4eb92db55c6b6946bcc9569a324d719b06a660..c93a61bc19d8e8ca12e2588bde9f2f65efa190f2 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+       * config/tc-aarch64.c (aarch64_features): Add rcpc.
+       * doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
+       * testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
+       * testsuite/gas/aarch64/ldst-rcpc.d: This.
+       * testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
+       * testsuite/gas/aarch64/ldst-rcpc.s: This.
+       * testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
+
 2017-01-04  Norm Jacobs  <norm.jacobs@oracle.com>
 
        PR gas/20992
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index e75bebe35774a7b2c0679560eac200d60f425ca3..c236df1e3aa11996c0fcdef020d85aaf69195076 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8438,6 +8438,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"sve",              AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0),
                        AARCH64_FEATURE (AARCH64_FEATURE_FP
                                         | AARCH64_FEATURE_SIMD, 0)},
+  {"rcpc",             AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0),
+                       AARCH64_ARCH_NONE},
   {NULL,               AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
 };
 
diff --git a/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d b/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d
deleted file mode 100644 (file)
index 73a0c9f..0000000
--- a/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d
+++ /dev/null
@@ -1,20 +0,0 @@
-#objdump: -dr
-#as: -march=armv8.3-a
-
-.*:     file format .*
-
-Disassembly of section \.text:
-
-0+ <.*>:
-   0:  38bfc0e1        ldaprb  w1, \[x7\]
-   4:  38bfc0e1        ldaprb  w1, \[x7\]
-   8:  38bfc0e1        ldaprb  w1, \[x7\]
-   c:  78bfc0e1        ldaprh  w1, \[x7\]
-  10:  78bfc0e1        ldaprh  w1, \[x7\]
-  14:  78bfc0e1        ldaprh  w1, \[x7\]
-  18:  b8bfc0e1        ldapr   w1, \[x7\]
-  1c:  b8bfc0e1        ldapr   w1, \[x7\]
-  20:  b8bfc0e1        ldapr   w1, \[x7\]
-  24:  f8bfc0e1        ldapr   x1, \[x7\]
-  28:  f8bfc0e1        ldapr   x1, \[x7\]
-  2c:  f8bfc0e1        ldapr   x1, \[x7\]
diff --git a/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.s b/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.s
deleted file mode 100644 (file)
index bfa41e0..0000000
--- a/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.s
+++ /dev/null
@@ -1,22 +0,0 @@
-       /* ARMv8.3 weaker release consistency load instructions.  */
-
-       /* <mnemonic>   <Wt>, [<Xn|SP>{,#0}] */
-       .macro LR32 op
-       \op     w1, [x7]
-       \op     w1, [x7, #0]
-       \op     w1, [x7, 0]
-       .endm
-
-       /* <mnemonic>   <Xt>, [<Xn|SP>{,#0}] */
-       .macro LR64 op
-       \op     x1, [x7]
-       \op     x1, [x7, #0]
-       \op     x1, [x7, 0]
-       .endm
-
-func:
-       .irp    op, ldaprb, ldaprh, ldapr
-       LR32    \op
-       .endr
-
-       LR64    ldapr
diff --git a/gas/testsuite/gas/aarch64/ldst-rcpc-armv8_2.d b/gas/testsuite/gas/aarch64/ldst-rcpc-armv8_2.d
new file mode 100644 (file)
index 0000000..ac8938f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ldst-rcpc-armv8_2.d
@@ -0,0 +1,21 @@
+#objdump: -dr
+#as: -march=armv8.2-a+rcpc
+#source: ldst-rcpc.s
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+   0:  38bfc0e1        ldaprb  w1, \[x7\]
+   4:  38bfc0e1        ldaprb  w1, \[x7\]
+   8:  38bfc0e1        ldaprb  w1, \[x7\]
+   c:  78bfc0e1        ldaprh  w1, \[x7\]
+  10:  78bfc0e1        ldaprh  w1, \[x7\]
+  14:  78bfc0e1        ldaprh  w1, \[x7\]
+  18:  b8bfc0e1        ldapr   w1, \[x7\]
+  1c:  b8bfc0e1        ldapr   w1, \[x7\]
+  20:  b8bfc0e1        ldapr   w1, \[x7\]
+  24:  f8bfc0e1        ldapr   x1, \[x7\]
+  28:  f8bfc0e1        ldapr   x1, \[x7\]
+  2c:  f8bfc0e1        ldapr   x1, \[x7\]
diff --git a/gas/testsuite/gas/aarch64/ldst-rcpc.d b/gas/testsuite/gas/aarch64/ldst-rcpc.d
new file mode 100644 (file)
index 0000000..73a0c9f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ldst-rcpc.d
@@ -0,0 +1,20 @@
+#objdump: -dr
+#as: -march=armv8.3-a
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+   0:  38bfc0e1        ldaprb  w1, \[x7\]
+   4:  38bfc0e1        ldaprb  w1, \[x7\]
+   8:  38bfc0e1        ldaprb  w1, \[x7\]
+   c:  78bfc0e1        ldaprh  w1, \[x7\]
+  10:  78bfc0e1        ldaprh  w1, \[x7\]
+  14:  78bfc0e1        ldaprh  w1, \[x7\]
+  18:  b8bfc0e1        ldapr   w1, \[x7\]
+  1c:  b8bfc0e1        ldapr   w1, \[x7\]
+  20:  b8bfc0e1        ldapr   w1, \[x7\]
+  24:  f8bfc0e1        ldapr   x1, \[x7\]
+  28:  f8bfc0e1        ldapr   x1, \[x7\]
+  2c:  f8bfc0e1        ldapr   x1, \[x7\]
diff --git a/gas/testsuite/gas/aarch64/ldst-rcpc.s b/gas/testsuite/gas/aarch64/ldst-rcpc.s
new file mode 100644 (file)
index 0000000..bfa41e0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ldst-rcpc.s
@@ -0,0 +1,22 @@
+       /* ARMv8.3 weaker release consistency load instructions.  */
+
+       /* <mnemonic>   <Wt>, [<Xn|SP>{,#0}] */
+       .macro LR32 op
+       \op     w1, [x7]
+       \op     w1, [x7, #0]
+       \op     w1, [x7, 0]
+       .endm
+
+       /* <mnemonic>   <Xt>, [<Xn|SP>{,#0}] */
+       .macro LR64 op
+       \op     x1, [x7]
+       \op     x1, [x7, #0]
+       \op     x1, [x7, 0]
+       .endm
+
+func:
+       .irp    op, ldaprb, ldaprh, ldapr
+       LR32    \op
+       .endr
+
+       LR64    ldapr
diff --git a/include/ChangeLog b/include/ChangeLog
index 87083b6db831a338b33ff13d6492a911629a7cd7..a51834233d0457af35b14528f7890b2c17d4834e 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+       * opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
+       (AARCH64_ARCH_V8_3): Update.
+
 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 
        * opcode/riscv-opc.h: Add support for the "q" ISA extension.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index d3d86ca8f8e8f2cf9710ec9063def2f3fc914133..c4f75e52d1fb8c3df48db1bd87e0e9f397e69b2e 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -53,6 +53,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_RAS    0x04000000      /* RAS Extensions.  */
 #define AARCH64_FEATURE_PROFILE        0x08000000      /* Statistical Profiling.  */
 #define AARCH64_FEATURE_SVE    0x10000000      /* SVE instructions.  */
+#define AARCH64_FEATURE_RCPC   0x20000000      /* RCPC instructions.  */
 
 /* Architectures are the sum of the base and extensions.  */
 #define AARCH64_ARCH_V8                AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@@ -70,7 +71,8 @@ typedef uint32_t aarch64_insn;
                                                 | AARCH64_FEATURE_F16  \
                                                 | AARCH64_FEATURE_RAS)
 #define AARCH64_ARCH_V8_3      AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
-                                                AARCH64_FEATURE_V8_3)
+                                                AARCH64_FEATURE_V8_3   \
+                                                | AARCH64_FEATURE_RCPC)
 
 #define AARCH64_ARCH_NONE      AARCH64_FEATURE (0, 0)
 #define AARCH64_ANY            AARCH64_FEATURE (-1, 0) /* Any basic core.  */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d01cbde1ece88e940228387a05b100c1fee30d5a..555a37957be1468d6a78fe46c1fdaa460dc6c98c 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+       * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
+       (aarch64_opcode_table): Use RCPC_INSN.
+
 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 
        * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 4bfee0322b0bf2034fb5500b899c08ec964f17ef..472205f7f542b09b29c3211fbe83e993e596fa85 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1940,6 +1940,8 @@ static const aarch64_feature_set aarch64_feature_fp_v8_3 =
   AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_FP, 0);
 static const aarch64_feature_set aarch64_feature_simd_v8_3 =
   AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_SIMD, 0);
+static const aarch64_feature_set aarch64_feature_rcpc =
+  AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0);
 
 #define CORE           &aarch64_feature_v8
 #define FP             &aarch64_feature_fp
@@ -1958,6 +1960,7 @@ static const aarch64_feature_set aarch64_feature_simd_v8_3 =
 #define ARMV8_3                &aarch64_feature_v8_3
 #define FP_V8_3                &aarch64_feature_fp_v8_3
 #define SIMD_V8_3      &aarch64_feature_simd_v8_3
+#define RCPC           &aarch64_feature_rcpc
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, NULL }
@@ -1986,6 +1989,8 @@ static const aarch64_feature_set aarch64_feature_simd_v8_3 =
     FLAGS | F_STRICT, TIED, NULL }
 #define V8_3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, ARMV8_3, OPS, QUALS, FLAGS, 0, NULL }
+#define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, NULL }
 
 struct aarch64_opcode aarch64_opcode_table[] =
 {
@@ -2982,9 +2987,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
   CORE_INSN ("stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
   CORE_INSN ("ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
-  V8_3_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
-  V8_3_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
-  V8_3_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
+  RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
+  RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
+  RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
   /* Limited Ordering Regions load/store instructions.  */
   _LOR_INSN ("ldlar",  0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL,       F_GPRSIZE_IN_Q),
   _LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
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