Regenerate pot files.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
2016-12-23  Tristan GingoldRegenerate pot files.
2016-12-21  Alan ModraChangeLog formatting fixes
2016-12-21  Andrew WatermanAvoid creating symbol table entries for registers
2016-12-20  Maciej W. RozyckiMIPS16/opcodes: Respect ISA and ASE in disassembly
2016-12-20  Maciej W. RozyckiMIPS16: Switch to 32-bit opcode table interpretation
2016-12-20  Maciej W. RozyckiMIPS16/opcodes: Correct 64-bit macros' ISA membership
2016-12-20  Maciej W. RozyckiMIPS16/opcodes: Correct I64/SDRASP opcode's ISA membership
2016-12-20  Andrew WatermanCorrect assembler mnemonic for RISC-V aqrl AMOs
2016-12-20  Andrew WatermanFix disassembly of RISC-V CSR instructions under -Mno...
2016-12-20  Andrew WatermanAdd canonical JALR for RISC-V
2016-12-20  Andrew WatermanRe-work RISC-V gas flags: now we just support -mabi...
2016-12-20  Andrew WatermanFormatting changes for RISC-V
2016-12-20  Alan ModraAdd opcodes RISC-V dependencies
2016-12-19  Maciej W. RozyckiMIPS/opcodes: Only examine ELF file structures if SYMTA...
2016-12-19  Maciej W. RozyckiMIPS/opcodes: Only call `bfd_mips_elf_get_abiflags...
2016-12-16  Nick CliftonFix compile time warning building arm-dis.c
2016-12-14  Maciej W. RozyckiMIPS/opcodes: Also set disassembler's ASE flags from...
2016-12-14  Maciej W. RozyckiMIPS/opcodes: Reorder ELF file header flag handling...
2016-12-14  Maciej W. RozyckiMIPS16: Fix SP-relative SD instruction annotation
2016-12-14  Maciej W. RozyckiMIPS16/opcodes: Fix and clarify MIPS16e commentary
2016-12-13  Renlin Li[Binutils][AARCH64]Remove Cn register for coprocessor...
2016-12-12  Yao QiHandle memory error in print_insn_rx
2016-12-12  Yao QiHandle memory error in print_insn_rl78_common
2016-12-09  Maciej W. RozyckiMIPS16: Remove unused `>' operand code
2016-12-09  Maciej W. RozyckiMIPS16/opcodes: Use hexadecimal interpretation for...
2016-12-09  Maciej W. RozyckiMIPS16/opcodes: Reformat raw EXTEND and undecoded output
2016-12-08  Maciej W. RozyckiMIPS16/opcodes: Fix off-by-one indentation in `print_mi...
2016-12-08  Maciej W. RozyckiMIPS16/opcodes: Fix PC-relative operation delay-slot...
2016-12-08  Maciej W. RozyckiAArch64/opcodes: Correct another `index' global shadowi...
2016-12-08  Luis MachadoFix crash when disassembling invalid range on powerpc vle
2016-12-07  Maciej W. RozyckiMIPS/opcodes: Correct an `interaction' comment typo
2016-12-07  Maciej W. RozyckiMIPS16/opcodes: Update opcode table comment
2016-12-07  Maciej W. RozyckiMIPS/opcodes: Reformat `-M' disassembler option's help...
2016-12-05  Szabolcs Nagy[ARM] Add ARMv8.3 VCMLA and VCADD instructions
2016-12-05  Szabolcs Nagy[ARM] Add ARMv8.3 VJCVT instruction
2016-12-01  Nick CliftonFix abort in x86 disassembler.
2016-11-29  Claudiu Zissulescu[ARC] Add checking for LP_COUNT reg usage, improve...
2016-11-29  Claudiu Zissulescu[ARC] Fix disassembler option.
2016-11-28  Amit PawarX86: Ignore REX_B bit for 32-bit XOP instructions
2016-11-22  Ambrogino ModiglianiFix spelling mistakes in comments in configure scripts
2016-11-22  Jose E. Marchesigas,opcodes: fix hardware capabilities bumping in the...
2016-11-22  Claudiu Zissulescu[ARC] Fix printing 'b' mnemonics.
2016-11-18  Szabolcs Nagy[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
2016-11-18  Szabolcs Nagy[AArch64] Add ARMv8.3 weaker release consistency load...
2016-11-18  Szabolcs Nagy[AArch64] Add ARMv8.3 javascript floating-point convers...
2016-11-18  Szabolcs Nagy[AArch64] Add ARMv8.3 combined pointer authentication...
2016-11-11  Szabolcs Nagy[AArch64] Add ARMv8.3 combined pointer authentication...
2016-11-11  Szabolcs Nagy[AArch64] Add ARMv8.3 PACGA instruction
2016-11-11  Szabolcs Nagy[AArch64] Add ARMv8.3 single source PAC instructions
2016-11-11  Szabolcs Nagy[AArch64] Add ARMv8.3 pointer authentication key registers
2016-11-11  Szabolcs Nagy[AArch64] Add ARMv8.3 instructions which are in the...
2016-11-11  Szabolcs Nagy[AArch64] Increase max_num_aliases in aarch64-gen
2016-11-09  H.J. LuX86: Remove the .s suffix from EVEX vpextrw
2016-11-09  H.J. LuUpdate opcodes/ChangeLog
2016-11-09  H.J. LuX86: Merge AVX512F vmovq
2016-11-08  H.J. LuX86: Remove the THREE_BYTE_0F7A entry
2016-11-07  H.J. LuX86: Properly handle bad FPU opcode
2016-11-04  Andrew Burgessarc/nps400: Validate address type operands correctly
2016-11-03  Graham Markallarc: Implement NPS-400 dcmac instruction
2016-11-03  Andrew Burgessarc: Change max instruction length to 64-bits
2016-11-03  Graham Markallarc: Swap highbyte and lowbyte in print_insn_arc
2016-11-03  Graham Markallarc: Replace ARC_SHORT macro with arc_opcode_len function
2016-11-03  Andrew Burgessarc/opcodes/nps400: Fix some instruction masks
2016-11-03  H.J. LuX86: Reuse opcode 0x80 decoder for opcode 0x82
2016-11-03  H.J. LuX86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode
2016-11-03  H.J. LuX86: Rename REG_82 to REG_83
2016-11-02  Igor TsimbalistEnable Intel AVX512_4VNNIW instructions
2016-11-02  Igor TsimbalistEnable Intel AVX512_4FMAPS instructions
2016-11-01  Nick CliftonAdd support for RISC-V architecture.
2016-10-21  H.J. LuX86: Remove pcommit instruction
2016-10-20  H.J. LuCheck invalid mask registers
2016-10-18  H.J. LuCheck addr32flag instead of sizeflag for rip/eip
2016-10-18  H.J. LuRemove the remaining SSE5 support
2016-10-18  Maciej W. RozyckiAArch64/opcodes: Correct an `index' global shadowing...
2016-10-17  Cupertino MirandaRemoved pseudo invalid instructions opcodes.
2016-10-14  Claudiu Zissulescu[ARC] Disassembler: fix LIMM detection for short instru...
2016-10-11  Jiong Wang[AArch64] PR target/20666, fix wrong encoding of new...
2016-10-07  Jiong Wang[AArch64] PR target/20667, fix disassembler for the...
2016-10-07  Alan Modrabfd_merge_private_bfd_data tidy
2016-10-05  Alan Modra-Wimplicit-fallthrough warning fixes
2016-10-05  Alan Modra-Wimplicit-fallthrough error fixes
2016-10-05  Alan ModraDon't use boolean OR in arithmetic expressions
2016-09-30  H.J. LuDon't assign alt twice
2016-09-30  Jiong Wang[AArch64] PR target/20553, fix opcode mask for SIMD...
2016-09-29  Alan ModraDisallow 3-operand cmp[l][i] for ppc64
2016-09-26  Vlad ZakharovWhen building target binaries, ensure that the warning...
2016-09-26  Claudiu Zissulescu[ARC] ISA alignment.
2016-09-21  Richard Sandiford[AArch64] Print spaces after commas in addresses
2016-09-21  Richard Sandiford[AArch64] Use "must" rather than "should" in error...
2016-09-21  Richard Sandiford[AArch64] Add SVE condition codes
2016-09-21  Richard Sandiford[AArch64][SVE 31/32] Add SVE instructions
2016-09-21  Richard Sandiford[AArch64][SVE 30/32] Add SVE instruction classes
2016-09-21  Richard Sandiford[AArch64][SVE 29/32] Add new SVE core & FP register...
2016-09-21  Richard Sandiford[AArch64][SVE 28/32] Add SVE FP immediate operands
2016-09-21  Richard Sandiford[AArch64][SVE 27/32] Add SVE integer immediate operands
2016-09-21  Richard Sandiford[AArch64][SVE 26/32] Add SVE MUL VL addressing modes
2016-09-21  Richard Sandiford[AArch64][SVE 25/32] Add support for SVE addressing...
2016-09-21  Richard Sandiford[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
2016-09-21  Richard Sandiford[AArch64][SVE 23/32] Add SVE pattern and prfop operands
2016-09-21  Richard Sandiford[AArch64][SVE 22/32] Add qualifiers for merging and...
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