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perf/x86/intel: Add Haswell TSX event aliases
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_event_intel.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
de0428a7 15
3a632cb2 16#include <asm/cpufeature.h>
de0428a7
KW		 17#include <asm/hardirq.h>
18#include <asm/apic.h>
19
20#include "perf_event.h"
a7e3ed1e 21
f22f54f4 22/*
b622d644 23 * Intel PerfMon, used on Core and later.
f22f54f4 24 */
ec75a716 25static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 26{
c3b7cdf1
PE		 27 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
28 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
29 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
30 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
31 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
32 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
33 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
34 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 35};
36
5c543e3c 37static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 38{
39 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
40 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
41 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
42 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
43 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
44 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
45 EVENT_CONSTRAINT_END
46};
47
5c543e3c 48static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 49{
b622d644
PZ		 50 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
51 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 52 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 53 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
54 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
55 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
56 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
57 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
58 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
59 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
60 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 61 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 62 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
63 EVENT_CONSTRAINT_END
64};
65
5c543e3c 66static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 67{
b622d644
PZ		 68 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
69 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 70 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 71 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
72 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
73 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
74 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
75 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
76 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
77 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
78 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
79 EVENT_CONSTRAINT_END
80};
81
5c543e3c 82static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 83{
53ad0447
YZ		 84 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
85 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
f20093ee 86 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 87 EVENT_EXTRA_END
88};
89
5c543e3c 90static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 91{
b622d644
PZ		 92 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
93 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 94 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 95 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
96 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
97 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 98 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 99 EVENT_CONSTRAINT_END
100};
101
5c543e3c 102static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 103{
104 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
105 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 106 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
fd4a5aef
SE		 107 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
108 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
109 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
110 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
b06b3d49 111 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 112 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
113 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
f8378f52
AK		 114 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
115 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
b06b3d49
LM		 116 EVENT_CONSTRAINT_END
117};
118
69943182
SE		 119static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
120{
121 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
122 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
123 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
124 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
125 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
126 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
6113af14 127 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
69943182
SE		 128 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
129 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
130 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
131 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
132 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
133 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
741a698f
PZ		 134 /*
135 * Errata BV98 -- MEM_*_RETIRED events can leak between counters of SMT
136 * siblings; disable these events because they can corrupt unrelated
137 * counters.
138 */
139 INTEL_EVENT_CONSTRAINT(0xd0, 0x0), /* MEM_UOPS_RETIRED.* */
140 INTEL_EVENT_CONSTRAINT(0xd1, 0x0), /* MEM_LOAD_UOPS_RETIRED.* */
141 INTEL_EVENT_CONSTRAINT(0xd2, 0x0), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
142 INTEL_EVENT_CONSTRAINT(0xd3, 0x0), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
69943182
SE		 143 EVENT_CONSTRAINT_END
144};
145
5c543e3c 146static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 147{
53ad0447
YZ		 148 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
149 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
150 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
f20093ee 151 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 152 EVENT_EXTRA_END
153};
154
0af3ac1f
AK		 155static struct event_constraint intel_v1_event_constraints[] __read_mostly =
156{
157 EVENT_CONSTRAINT_END
158};
159
5c543e3c 160static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 161{
b622d644
PZ		 162 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
163 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 164 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 165 EVENT_CONSTRAINT_END
166};
167
1fa64180
YZ		 168static struct event_constraint intel_slm_event_constraints[] __read_mostly =
169{
170 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
171 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
172 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF */
173 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
174 EVENT_CONSTRAINT_END
175};
176
ee89cbc2 177static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
53ad0447
YZ		 178 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
179 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
180 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
f20093ee 181 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
f1923820
SE		 182 EVENT_EXTRA_END
183};
184
185static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
53ad0447
YZ		 186 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
187 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
188 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
f1a52789 189 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
ee89cbc2
SE		 190 EVENT_EXTRA_END
191};
192
f20093ee
SE		 193EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
194EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
9ad64c0f 195EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
f20093ee
SE		 196
197struct attribute *nhm_events_attrs[] = {
198 EVENT_PTR(mem_ld_nhm),
199 NULL,
200};
201
202struct attribute *snb_events_attrs[] = {
203 EVENT_PTR(mem_ld_snb),
9ad64c0f 204 EVENT_PTR(mem_st_snb),
f20093ee
SE		 205 NULL,
206};
207
3a632cb2
AK		 208static struct event_constraint intel_hsw_event_constraints[] = {
209 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
210 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
211 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
212 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
213 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
214 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
215 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
216 INTEL_EVENT_CONSTRAINT(0x08a3, 0x4),
217 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
218 INTEL_EVENT_CONSTRAINT(0x0ca3, 0x4),
219 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
220 INTEL_EVENT_CONSTRAINT(0x04a3, 0xf),
221 EVENT_CONSTRAINT_END
222};
223
f22f54f4
PZ		 224static u64 intel_pmu_event_map(int hw_event)
225{
226 return intel_perfmon_event_map[hw_event];
227}
228
74e6543f
YZ		 229#define SNB_DMND_DATA_RD (1ULL << 0)
230#define SNB_DMND_RFO (1ULL << 1)
231#define SNB_DMND_IFETCH (1ULL << 2)
232#define SNB_DMND_WB (1ULL << 3)
233#define SNB_PF_DATA_RD (1ULL << 4)
234#define SNB_PF_RFO (1ULL << 5)
235#define SNB_PF_IFETCH (1ULL << 6)
236#define SNB_LLC_DATA_RD (1ULL << 7)
237#define SNB_LLC_RFO (1ULL << 8)
238#define SNB_LLC_IFETCH (1ULL << 9)
239#define SNB_BUS_LOCKS (1ULL << 10)
240#define SNB_STRM_ST (1ULL << 11)
241#define SNB_OTHER (1ULL << 15)
242#define SNB_RESP_ANY (1ULL << 16)
243#define SNB_NO_SUPP (1ULL << 17)
244#define SNB_LLC_HITM (1ULL << 18)
245#define SNB_LLC_HITE (1ULL << 19)
246#define SNB_LLC_HITS (1ULL << 20)
247#define SNB_LLC_HITF (1ULL << 21)
248#define SNB_LOCAL (1ULL << 22)
249#define SNB_REMOTE (0xffULL << 23)
250#define SNB_SNP_NONE (1ULL << 31)
251#define SNB_SNP_NOT_NEEDED (1ULL << 32)
252#define SNB_SNP_MISS (1ULL << 33)
253#define SNB_NO_FWD (1ULL << 34)
254#define SNB_SNP_FWD (1ULL << 35)
255#define SNB_HITM (1ULL << 36)
256#define SNB_NON_DRAM (1ULL << 37)
257
258#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
259#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
260#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
261
262#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
263 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
264 SNB_HITM)
265
266#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
267#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
268
269#define SNB_L3_ACCESS SNB_RESP_ANY
270#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
271
272static __initconst const u64 snb_hw_cache_extra_regs
273 [PERF_COUNT_HW_CACHE_MAX]
274 [PERF_COUNT_HW_CACHE_OP_MAX]
275 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
276{
277 [ C(LL ) ] = {
278 [ C(OP_READ) ] = {
279 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
280 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
281 },
282 [ C(OP_WRITE) ] = {
283 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
284 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
285 },
286 [ C(OP_PREFETCH) ] = {
287 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
288 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
289 },
290 },
291 [ C(NODE) ] = {
292 [ C(OP_READ) ] = {
293 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
294 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
295 },
296 [ C(OP_WRITE) ] = {
297 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
298 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
299 },
300 [ C(OP_PREFETCH) ] = {
301 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
302 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
303 },
304 },
305};
306
b06b3d49
LM		 307static __initconst const u64 snb_hw_cache_event_ids
308 [PERF_COUNT_HW_CACHE_MAX]
309 [PERF_COUNT_HW_CACHE_OP_MAX]
310 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
311{
312 [ C(L1D) ] = {
313 [ C(OP_READ) ] = {
314 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
315 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
316 },
317 [ C(OP_WRITE) ] = {
318 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
319 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
320 },
321 [ C(OP_PREFETCH) ] = {
322 [ C(RESULT_ACCESS) ] = 0x0,
323 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
324 },
325 },
326 [ C(L1I ) ] = {
327 [ C(OP_READ) ] = {
328 [ C(RESULT_ACCESS) ] = 0x0,
329 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
330 },
331 [ C(OP_WRITE) ] = {
332 [ C(RESULT_ACCESS) ] = -1,
333 [ C(RESULT_MISS) ] = -1,
334 },
335 [ C(OP_PREFETCH) ] = {
336 [ C(RESULT_ACCESS) ] = 0x0,
337 [ C(RESULT_MISS) ] = 0x0,
338 },
339 },
340 [ C(LL ) ] = {
b06b3d49 341 [ C(OP_READ) ] = {
63b6a675 342 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 343 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 344 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
345 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 346 },
347 [ C(OP_WRITE) ] = {
63b6a675 348 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 349 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 350 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
351 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 352 },
353 [ C(OP_PREFETCH) ] = {
63b6a675 354 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 355 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 356 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
357 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 358 },
359 },
360 [ C(DTLB) ] = {
361 [ C(OP_READ) ] = {
362 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
363 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
364 },
365 [ C(OP_WRITE) ] = {
366 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
367 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
368 },
369 [ C(OP_PREFETCH) ] = {
370 [ C(RESULT_ACCESS) ] = 0x0,
371 [ C(RESULT_MISS) ] = 0x0,
372 },
373 },
374 [ C(ITLB) ] = {
375 [ C(OP_READ) ] = {
376 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
377 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
378 },
379 [ C(OP_WRITE) ] = {
380 [ C(RESULT_ACCESS) ] = -1,
381 [ C(RESULT_MISS) ] = -1,
382 },
383 [ C(OP_PREFETCH) ] = {
384 [ C(RESULT_ACCESS) ] = -1,
385 [ C(RESULT_MISS) ] = -1,
386 },
387 },
388 [ C(BPU ) ] = {
389 [ C(OP_READ) ] = {
390 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
391 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
392 },
393 [ C(OP_WRITE) ] = {
394 [ C(RESULT_ACCESS) ] = -1,
395 [ C(RESULT_MISS) ] = -1,
396 },
397 [ C(OP_PREFETCH) ] = {
398 [ C(RESULT_ACCESS) ] = -1,
399 [ C(RESULT_MISS) ] = -1,
400 },
401 },
89d6c0b5
PZ		 402 [ C(NODE) ] = {
403 [ C(OP_READ) ] = {
74e6543f
YZ		 404 [ C(RESULT_ACCESS) ] = 0x01b7,
405 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 406 },
407 [ C(OP_WRITE) ] = {
74e6543f
YZ		 408 [ C(RESULT_ACCESS) ] = 0x01b7,
409 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 410 },
411 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 412 [ C(RESULT_ACCESS) ] = 0x01b7,
413 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 414 },
415 },
416
b06b3d49
LM		 417};
418
caaa8be3 419static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 420 [PERF_COUNT_HW_CACHE_MAX]
421 [PERF_COUNT_HW_CACHE_OP_MAX]
422 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
423{
424 [ C(L1D) ] = {
425 [ C(OP_READ) ] = {
426 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
427 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
428 },
429 [ C(OP_WRITE) ] = {
430 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
431 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
432 },
433 [ C(OP_PREFETCH) ] = {
434 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
435 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
436 },
437 },
438 [ C(L1I ) ] = {
439 [ C(OP_READ) ] = {
440 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
441 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
442 },
443 [ C(OP_WRITE) ] = {
444 [ C(RESULT_ACCESS) ] = -1,
445 [ C(RESULT_MISS) ] = -1,
446 },
447 [ C(OP_PREFETCH) ] = {
448 [ C(RESULT_ACCESS) ] = 0x0,
449 [ C(RESULT_MISS) ] = 0x0,
450 },
451 },
452 [ C(LL ) ] = {
453 [ C(OP_READ) ] = {
63b6a675 454 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 455 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 456 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
457 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 458 },
e994d7d2
AK		 459 /*
460 * Use RFO, not WRITEBACK, because a write miss would typically occur
461 * on RFO.
462 */
f22f54f4 463 [ C(OP_WRITE) ] = {
63b6a675
PZ		 464 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
465 [ C(RESULT_ACCESS) ] = 0x01b7,
466 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 467 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 468 },
469 [ C(OP_PREFETCH) ] = {
63b6a675 470 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 471 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 472 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
473 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 474 },
475 },
476 [ C(DTLB) ] = {
477 [ C(OP_READ) ] = {
478 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
479 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
480 },
481 [ C(OP_WRITE) ] = {
482 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
483 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
484 },
485 [ C(OP_PREFETCH) ] = {
486 [ C(RESULT_ACCESS) ] = 0x0,
487 [ C(RESULT_MISS) ] = 0x0,
488 },
489 },
490 [ C(ITLB) ] = {
491 [ C(OP_READ) ] = {
492 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
493 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
494 },
495 [ C(OP_WRITE) ] = {
496 [ C(RESULT_ACCESS) ] = -1,
497 [ C(RESULT_MISS) ] = -1,
498 },
499 [ C(OP_PREFETCH) ] = {
500 [ C(RESULT_ACCESS) ] = -1,
501 [ C(RESULT_MISS) ] = -1,
502 },
503 },
504 [ C(BPU ) ] = {
505 [ C(OP_READ) ] = {
506 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
507 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
508 },
509 [ C(OP_WRITE) ] = {
510 [ C(RESULT_ACCESS) ] = -1,
511 [ C(RESULT_MISS) ] = -1,
512 },
513 [ C(OP_PREFETCH) ] = {
514 [ C(RESULT_ACCESS) ] = -1,
515 [ C(RESULT_MISS) ] = -1,
516 },
517 },
89d6c0b5
PZ		 518 [ C(NODE) ] = {
519 [ C(OP_READ) ] = {
520 [ C(RESULT_ACCESS) ] = 0x01b7,
521 [ C(RESULT_MISS) ] = 0x01b7,
522 },
523 [ C(OP_WRITE) ] = {
524 [ C(RESULT_ACCESS) ] = 0x01b7,
525 [ C(RESULT_MISS) ] = 0x01b7,
526 },
527 [ C(OP_PREFETCH) ] = {
528 [ C(RESULT_ACCESS) ] = 0x01b7,
529 [ C(RESULT_MISS) ] = 0x01b7,
530 },
531 },
f22f54f4
PZ		 532};
533
e994d7d2 534/*
63b6a675
PZ		 535 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
536 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 537 */
538
63b6a675
PZ		 539#define NHM_DMND_DATA_RD (1 << 0)
540#define NHM_DMND_RFO (1 << 1)
541#define NHM_DMND_IFETCH (1 << 2)
542#define NHM_DMND_WB (1 << 3)
543#define NHM_PF_DATA_RD (1 << 4)
544#define NHM_PF_DATA_RFO (1 << 5)
545#define NHM_PF_IFETCH (1 << 6)
546#define NHM_OFFCORE_OTHER (1 << 7)
547#define NHM_UNCORE_HIT (1 << 8)
548#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
549#define NHM_OTHER_CORE_HITM (1 << 10)
550 /* reserved */
551#define NHM_REMOTE_CACHE_FWD (1 << 12)
552#define NHM_REMOTE_DRAM (1 << 13)
553#define NHM_LOCAL_DRAM (1 << 14)
554#define NHM_NON_DRAM (1 << 15)
555
87e24f4b
PZ		 556#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
557#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 558
559#define NHM_DMND_READ (NHM_DMND_DATA_RD)
560#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
561#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
562
563#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 564#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 565#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 566
567static __initconst const u64 nehalem_hw_cache_extra_regs
568 [PERF_COUNT_HW_CACHE_MAX]
569 [PERF_COUNT_HW_CACHE_OP_MAX]
570 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
571{
572 [ C(LL ) ] = {
573 [ C(OP_READ) ] = {
63b6a675
PZ		 574 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
575 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 576 },
577 [ C(OP_WRITE) ] = {
63b6a675
PZ		 578 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
579 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 580 },
581 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 582 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
583 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 584 },
89d6c0b5
PZ		 585 },
586 [ C(NODE) ] = {
587 [ C(OP_READ) ] = {
87e24f4b
PZ		 588 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
589 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 590 },
591 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 592 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
593 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 594 },
595 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 596 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
597 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 598 },
599 },
e994d7d2
AK		 600};
601
caaa8be3 602static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 603 [PERF_COUNT_HW_CACHE_MAX]
604 [PERF_COUNT_HW_CACHE_OP_MAX]
605 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
606{
607 [ C(L1D) ] = {
608 [ C(OP_READ) ] = {
f4929bd3
PZ		 609 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
610 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 611 },
612 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 613 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
614 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 615 },
616 [ C(OP_PREFETCH) ] = {
617 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
618 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
619 },
620 },
621 [ C(L1I ) ] = {
622 [ C(OP_READ) ] = {
623 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
624 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
625 },
626 [ C(OP_WRITE) ] = {
627 [ C(RESULT_ACCESS) ] = -1,
628 [ C(RESULT_MISS) ] = -1,
629 },
630 [ C(OP_PREFETCH) ] = {
631 [ C(RESULT_ACCESS) ] = 0x0,
632 [ C(RESULT_MISS) ] = 0x0,
633 },
634 },
635 [ C(LL ) ] = {
636 [ C(OP_READ) ] = {
e994d7d2
AK		 637 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
638 [ C(RESULT_ACCESS) ] = 0x01b7,
639 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
640 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 641 },
e994d7d2
AK		 642 /*
643 * Use RFO, not WRITEBACK, because a write miss would typically occur
644 * on RFO.
645 */
f22f54f4 646 [ C(OP_WRITE) ] = {
e994d7d2
AK		 647 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
648 [ C(RESULT_ACCESS) ] = 0x01b7,
649 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
650 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 651 },
652 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 653 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
654 [ C(RESULT_ACCESS) ] = 0x01b7,
655 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
656 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 657 },
658 },
659 [ C(DTLB) ] = {
660 [ C(OP_READ) ] = {
661 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
662 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
663 },
664 [ C(OP_WRITE) ] = {
665 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
666 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
667 },
668 [ C(OP_PREFETCH) ] = {
669 [ C(RESULT_ACCESS) ] = 0x0,
670 [ C(RESULT_MISS) ] = 0x0,
671 },
672 },
673 [ C(ITLB) ] = {
674 [ C(OP_READ) ] = {
675 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
676 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
677 },
678 [ C(OP_WRITE) ] = {
679 [ C(RESULT_ACCESS) ] = -1,
680 [ C(RESULT_MISS) ] = -1,
681 },
682 [ C(OP_PREFETCH) ] = {
683 [ C(RESULT_ACCESS) ] = -1,
684 [ C(RESULT_MISS) ] = -1,
685 },
686 },
687 [ C(BPU ) ] = {
688 [ C(OP_READ) ] = {
689 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
690 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
691 },
692 [ C(OP_WRITE) ] = {
693 [ C(RESULT_ACCESS) ] = -1,
694 [ C(RESULT_MISS) ] = -1,
695 },
696 [ C(OP_PREFETCH) ] = {
697 [ C(RESULT_ACCESS) ] = -1,
698 [ C(RESULT_MISS) ] = -1,
699 },
700 },
89d6c0b5
PZ		 701 [ C(NODE) ] = {
702 [ C(OP_READ) ] = {
703 [ C(RESULT_ACCESS) ] = 0x01b7,
704 [ C(RESULT_MISS) ] = 0x01b7,
705 },
706 [ C(OP_WRITE) ] = {
707 [ C(RESULT_ACCESS) ] = 0x01b7,
708 [ C(RESULT_MISS) ] = 0x01b7,
709 },
710 [ C(OP_PREFETCH) ] = {
711 [ C(RESULT_ACCESS) ] = 0x01b7,
712 [ C(RESULT_MISS) ] = 0x01b7,
713 },
714 },
f22f54f4
PZ		 715};
716
caaa8be3 717static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 718 [PERF_COUNT_HW_CACHE_MAX]
719 [PERF_COUNT_HW_CACHE_OP_MAX]
720 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
721{
722 [ C(L1D) ] = {
723 [ C(OP_READ) ] = {
724 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
725 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
726 },
727 [ C(OP_WRITE) ] = {
728 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
729 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
730 },
731 [ C(OP_PREFETCH) ] = {
732 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
733 [ C(RESULT_MISS) ] = 0,
734 },
735 },
736 [ C(L1I ) ] = {
737 [ C(OP_READ) ] = {
738 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
739 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
740 },
741 [ C(OP_WRITE) ] = {
742 [ C(RESULT_ACCESS) ] = -1,
743 [ C(RESULT_MISS) ] = -1,
744 },
745 [ C(OP_PREFETCH) ] = {
746 [ C(RESULT_ACCESS) ] = 0,
747 [ C(RESULT_MISS) ] = 0,
748 },
749 },
750 [ C(LL ) ] = {
751 [ C(OP_READ) ] = {
752 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
753 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
754 },
755 [ C(OP_WRITE) ] = {
756 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
757 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
758 },
759 [ C(OP_PREFETCH) ] = {
760 [ C(RESULT_ACCESS) ] = 0,
761 [ C(RESULT_MISS) ] = 0,
762 },
763 },
764 [ C(DTLB) ] = {
765 [ C(OP_READ) ] = {
766 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
767 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
768 },
769 [ C(OP_WRITE) ] = {
770 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
771 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
772 },
773 [ C(OP_PREFETCH) ] = {
774 [ C(RESULT_ACCESS) ] = 0,
775 [ C(RESULT_MISS) ] = 0,
776 },
777 },
778 [ C(ITLB) ] = {
779 [ C(OP_READ) ] = {
780 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
781 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
782 },
783 [ C(OP_WRITE) ] = {
784 [ C(RESULT_ACCESS) ] = -1,
785 [ C(RESULT_MISS) ] = -1,
786 },
787 [ C(OP_PREFETCH) ] = {
788 [ C(RESULT_ACCESS) ] = -1,
789 [ C(RESULT_MISS) ] = -1,
790 },
791 },
792 [ C(BPU ) ] = {
793 [ C(OP_READ) ] = {
794 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
795 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
796 },
797 [ C(OP_WRITE) ] = {
798 [ C(RESULT_ACCESS) ] = -1,
799 [ C(RESULT_MISS) ] = -1,
800 },
801 [ C(OP_PREFETCH) ] = {
802 [ C(RESULT_ACCESS) ] = -1,
803 [ C(RESULT_MISS) ] = -1,
804 },
805 },
806};
807
caaa8be3 808static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 809 [PERF_COUNT_HW_CACHE_MAX]
810 [PERF_COUNT_HW_CACHE_OP_MAX]
811 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
812{
813 [ C(L1D) ] = {
814 [ C(OP_READ) ] = {
815 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
816 [ C(RESULT_MISS) ] = 0,
817 },
818 [ C(OP_WRITE) ] = {
819 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
820 [ C(RESULT_MISS) ] = 0,
821 },
822 [ C(OP_PREFETCH) ] = {
823 [ C(RESULT_ACCESS) ] = 0x0,
824 [ C(RESULT_MISS) ] = 0,
825 },
826 },
827 [ C(L1I ) ] = {
828 [ C(OP_READ) ] = {
829 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
830 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
831 },
832 [ C(OP_WRITE) ] = {
833 [ C(RESULT_ACCESS) ] = -1,
834 [ C(RESULT_MISS) ] = -1,
835 },
836 [ C(OP_PREFETCH) ] = {
837 [ C(RESULT_ACCESS) ] = 0,
838 [ C(RESULT_MISS) ] = 0,
839 },
840 },
841 [ C(LL ) ] = {
842 [ C(OP_READ) ] = {
843 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
844 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
845 },
846 [ C(OP_WRITE) ] = {
847 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
848 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
849 },
850 [ C(OP_PREFETCH) ] = {
851 [ C(RESULT_ACCESS) ] = 0,
852 [ C(RESULT_MISS) ] = 0,
853 },
854 },
855 [ C(DTLB) ] = {
856 [ C(OP_READ) ] = {
857 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
858 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
859 },
860 [ C(OP_WRITE) ] = {
861 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
862 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
863 },
864 [ C(OP_PREFETCH) ] = {
865 [ C(RESULT_ACCESS) ] = 0,
866 [ C(RESULT_MISS) ] = 0,
867 },
868 },
869 [ C(ITLB) ] = {
870 [ C(OP_READ) ] = {
871 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
872 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
873 },
874 [ C(OP_WRITE) ] = {
875 [ C(RESULT_ACCESS) ] = -1,
876 [ C(RESULT_MISS) ] = -1,
877 },
878 [ C(OP_PREFETCH) ] = {
879 [ C(RESULT_ACCESS) ] = -1,
880 [ C(RESULT_MISS) ] = -1,
881 },
882 },
883 [ C(BPU ) ] = {
884 [ C(OP_READ) ] = {
885 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
886 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
887 },
888 [ C(OP_WRITE) ] = {
889 [ C(RESULT_ACCESS) ] = -1,
890 [ C(RESULT_MISS) ] = -1,
891 },
892 [ C(OP_PREFETCH) ] = {
893 [ C(RESULT_ACCESS) ] = -1,
894 [ C(RESULT_MISS) ] = -1,
895 },
896 },
897};
898
1fa64180
YZ		 899static struct extra_reg intel_slm_extra_regs[] __read_mostly =
900{
901 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
06c939c1
PZ		 902 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
903 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x768005ffffull, RSP_1),
1fa64180
YZ		 904 EVENT_EXTRA_END
905};
906
907#define SLM_DMND_READ SNB_DMND_DATA_RD
908#define SLM_DMND_WRITE SNB_DMND_RFO
909#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
910
911#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
912#define SLM_LLC_ACCESS SNB_RESP_ANY
913#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
914
915static __initconst const u64 slm_hw_cache_extra_regs
916 [PERF_COUNT_HW_CACHE_MAX]
917 [PERF_COUNT_HW_CACHE_OP_MAX]
918 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
919{
920 [ C(LL ) ] = {
921 [ C(OP_READ) ] = {
922 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
923 [ C(RESULT_MISS) ] = SLM_DMND_READ|SLM_LLC_MISS,
924 },
925 [ C(OP_WRITE) ] = {
926 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
927 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
928 },
929 [ C(OP_PREFETCH) ] = {
930 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
931 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
932 },
933 },
934};
935
936static __initconst const u64 slm_hw_cache_event_ids
937 [PERF_COUNT_HW_CACHE_MAX]
938 [PERF_COUNT_HW_CACHE_OP_MAX]
939 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
940{
941 [ C(L1D) ] = {
942 [ C(OP_READ) ] = {
943 [ C(RESULT_ACCESS) ] = 0,
944 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
945 },
946 [ C(OP_WRITE) ] = {
947 [ C(RESULT_ACCESS) ] = 0,
948 [ C(RESULT_MISS) ] = 0,
949 },
950 [ C(OP_PREFETCH) ] = {
951 [ C(RESULT_ACCESS) ] = 0,
952 [ C(RESULT_MISS) ] = 0,
953 },
954 },
955 [ C(L1I ) ] = {
956 [ C(OP_READ) ] = {
957 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
958 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
959 },
960 [ C(OP_WRITE) ] = {
961 [ C(RESULT_ACCESS) ] = -1,
962 [ C(RESULT_MISS) ] = -1,
963 },
964 [ C(OP_PREFETCH) ] = {
965 [ C(RESULT_ACCESS) ] = 0,
966 [ C(RESULT_MISS) ] = 0,
967 },
968 },
969 [ C(LL ) ] = {
970 [ C(OP_READ) ] = {
971 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
972 [ C(RESULT_ACCESS) ] = 0x01b7,
973 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
974 [ C(RESULT_MISS) ] = 0x01b7,
975 },
976 [ C(OP_WRITE) ] = {
977 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
978 [ C(RESULT_ACCESS) ] = 0x01b7,
979 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
980 [ C(RESULT_MISS) ] = 0x01b7,
981 },
982 [ C(OP_PREFETCH) ] = {
983 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
984 [ C(RESULT_ACCESS) ] = 0x01b7,
985 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
986 [ C(RESULT_MISS) ] = 0x01b7,
987 },
988 },
989 [ C(DTLB) ] = {
990 [ C(OP_READ) ] = {
991 [ C(RESULT_ACCESS) ] = 0,
992 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
993 },
994 [ C(OP_WRITE) ] = {
995 [ C(RESULT_ACCESS) ] = 0,
996 [ C(RESULT_MISS) ] = 0,
997 },
998 [ C(OP_PREFETCH) ] = {
999 [ C(RESULT_ACCESS) ] = 0,
1000 [ C(RESULT_MISS) ] = 0,
1001 },
1002 },
1003 [ C(ITLB) ] = {
1004 [ C(OP_READ) ] = {
1005 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1006 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1007 },
1008 [ C(OP_WRITE) ] = {
1009 [ C(RESULT_ACCESS) ] = -1,
1010 [ C(RESULT_MISS) ] = -1,
1011 },
1012 [ C(OP_PREFETCH) ] = {
1013 [ C(RESULT_ACCESS) ] = -1,
1014 [ C(RESULT_MISS) ] = -1,
1015 },
1016 },
1017 [ C(BPU ) ] = {
1018 [ C(OP_READ) ] = {
1019 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1020 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1021 },
1022 [ C(OP_WRITE) ] = {
1023 [ C(RESULT_ACCESS) ] = -1,
1024 [ C(RESULT_MISS) ] = -1,
1025 },
1026 [ C(OP_PREFETCH) ] = {
1027 [ C(RESULT_ACCESS) ] = -1,
1028 [ C(RESULT_MISS) ] = -1,
1029 },
1030 },
1031};
1032
60ce0fbd
SE		 1033static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
1034{
1035 /* user explicitly requested branch sampling */
1036 if (has_branch_stack(event))
1037 return true;
1038
1039 /* implicit branch sampling to correct PEBS skid */
3044318f
AK		 1040 if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1 &&
1041 x86_pmu.intel_cap.pebs_format < 2)
60ce0fbd
SE		 1042 return true;
1043
1044 return false;
1045}
1046
f22f54f4
PZ		 1047static void intel_pmu_disable_all(void)
1048{
1049 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1050
1051 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1052
15c7ad51 1053 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 1054 intel_pmu_disable_bts();
ca037701
PZ		 1055
1056 intel_pmu_pebs_disable_all();
caff2bef 1057 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 1058}
1059
11164cd4 1060static void intel_pmu_enable_all(int added)
f22f54f4
PZ		 1061{
1062 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1063
d329527e
PZ		 1064 intel_pmu_pebs_enable_all();
1065 intel_pmu_lbr_enable_all();
144d31e6
GN		 1066 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1067 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 1068
15c7ad51 1069 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 1070 struct perf_event *event =
15c7ad51 1071 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 1072
1073 if (WARN_ON_ONCE(!event))
1074 return;
1075
1076 intel_pmu_enable_bts(event->hw.config);
1077 }
1078}
1079
11164cd4
PZ		 1080/*
1081 * Workaround for:
1082 * Intel Errata AAK100 (model 26)
1083 * Intel Errata AAP53 (model 30)
40b91cd1 1084 * Intel Errata BD53 (model 44)
11164cd4 1085 *
351af072
ZY		 1086 * The official story:
1087 * These chips need to be 'reset' when adding counters by programming the
1088 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1089 * in sequence on the same PMC or on different PMCs.
1090 *
1091 * In practise it appears some of these events do in fact count, and
1092 * we need to programm all 4 events.
11164cd4 1093 */
351af072 1094static void intel_pmu_nhm_workaround(void)
11164cd4 1095{
351af072
ZY		 1096 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1097 static const unsigned long nhm_magic[4] = {
1098 0x4300B5,
1099 0x4300D2,
1100 0x4300B1,
1101 0x4300B1
1102 };
1103 struct perf_event *event;
1104 int i;
11164cd4 1105
351af072
ZY		 1106 /*
1107 * The Errata requires below steps:
1108 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1109 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1110 * the corresponding PMCx;
1111 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1112 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1113 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1114 */
11164cd4 1115
351af072
ZY		 1116 /*
1117 * The real steps we choose are a little different from above.
1118 * A) To reduce MSR operations, we don't run step 1) as they
1119 * are already cleared before this function is called;
1120 * B) Call x86_perf_event_update to save PMCx before configuring
1121 * PERFEVTSELx with magic number;
1122 * C) With step 5), we do clear only when the PERFEVTSELx is
1123 * not used currently.
1124 * D) Call x86_perf_event_set_period to restore PMCx;
1125 */
11164cd4 1126
351af072
ZY		 1127 /* We always operate 4 pairs of PERF Counters */
1128 for (i = 0; i < 4; i++) {
1129 event = cpuc->events[i];
1130 if (event)
1131 x86_perf_event_update(event);
1132 }
11164cd4 1133
351af072
ZY		 1134 for (i = 0; i < 4; i++) {
1135 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1136 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1137 }
1138
1139 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1140 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 1141
351af072
ZY		 1142 for (i = 0; i < 4; i++) {
1143 event = cpuc->events[i];
1144
1145 if (event) {
1146 x86_perf_event_set_period(event);
31fa58af 1147 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 1148 ARCH_PERFMON_EVENTSEL_ENABLE);
1149 } else
1150 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 1151 }
351af072
ZY		 1152}
1153
1154static void intel_pmu_nhm_enable_all(int added)
1155{
1156 if (added)
1157 intel_pmu_nhm_workaround();
11164cd4
PZ		 1158 intel_pmu_enable_all(added);
1159}
1160
f22f54f4
PZ		 1161static inline u64 intel_pmu_get_status(void)
1162{
1163 u64 status;
1164
1165 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1166
1167 return status;
1168}
1169
1170static inline void intel_pmu_ack_status(u64 ack)
1171{
1172 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1173}
1174
ca037701 1175static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 1176{
15c7ad51 1177 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 1178 u64 ctrl_val, mask;
1179
1180 mask = 0xfULL << (idx * 4);
1181
1182 rdmsrl(hwc->config_base, ctrl_val);
1183 ctrl_val &= ~mask;
7645a24c 1184 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1185}
1186
ca037701 1187static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 1188{
aff3d91a 1189 struct hw_perf_event *hwc = &event->hw;
144d31e6 1190 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a 1191
15c7ad51 1192 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 1193 intel_pmu_disable_bts();
1194 intel_pmu_drain_bts_buffer();
1195 return;
1196 }
1197
144d31e6
GN		 1198 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1199 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1200
60ce0fbd
SE		 1201 /*
1202 * must disable before any actual event
1203 * because any event may be combined with LBR
1204 */
1205 if (intel_pmu_needs_lbr_smpl(event))
1206 intel_pmu_lbr_disable(event);
1207
f22f54f4 1208 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1209 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 1210 return;
1211 }
1212
aff3d91a 1213 x86_pmu_disable_event(event);
ca037701 1214
ab608344 1215 if (unlikely(event->attr.precise_ip))
ef21f683 1216 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 1217}
1218
ca037701 1219static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 1220{
15c7ad51 1221 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4 1222 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 1223
1224 /*
1225 * Enable IRQ generation (0x8),
1226 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1227 * if requested:
1228 */
1229 bits = 0x8ULL;
1230 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1231 bits |= 0x2;
1232 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1233 bits |= 0x1;
1234
1235 /*
1236 * ANY bit is supported in v3 and up
1237 */
1238 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1239 bits |= 0x4;
1240
1241 bits <<= (idx * 4);
1242 mask = 0xfULL << (idx * 4);
1243
1244 rdmsrl(hwc->config_base, ctrl_val);
1245 ctrl_val &= ~mask;
1246 ctrl_val |= bits;
7645a24c 1247 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1248}
1249
aff3d91a 1250static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 1251{
aff3d91a 1252 struct hw_perf_event *hwc = &event->hw;
144d31e6 1253 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a 1254
15c7ad51 1255 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 1256 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 1257 return;
1258
1259 intel_pmu_enable_bts(hwc->config);
1260 return;
1261 }
60ce0fbd
SE		 1262 /*
1263 * must enabled before any actual event
1264 * because any event may be combined with LBR
1265 */
1266 if (intel_pmu_needs_lbr_smpl(event))
1267 intel_pmu_lbr_enable(event);
f22f54f4 1268
144d31e6
GN		 1269 if (event->attr.exclude_host)
1270 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1271 if (event->attr.exclude_guest)
1272 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1273
f22f54f4 1274 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1275 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 1276 return;
1277 }
1278
ab608344 1279 if (unlikely(event->attr.precise_ip))
ef21f683 1280 intel_pmu_pebs_enable(event);
ca037701 1281
31fa58af 1282 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 1283}
1284
2dbf0116
AK		 1285static inline bool event_is_checkpointed(struct perf_event *event)
1286{
1287 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1288}
1289
f22f54f4
PZ		 1290/*
1291 * Save and restart an expired event. Called by NMI contexts,
1292 * so it has to be careful about preempting normal event ops:
1293 */
de0428a7 1294int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 1295{
cc2ad4ba 1296 x86_perf_event_update(event);
2dbf0116
AK		 1297 /*
1298 * For a checkpointed counter always reset back to 0. This
1299 * avoids a situation where the counter overflows, aborts the
1300 * transaction and is then set back to shortly before the
1301 * overflow, and overflows and aborts again.
1302 */
1303 if (unlikely(event_is_checkpointed(event))) {
1304 /* No race with NMIs because the counter should not be armed */
1305 wrmsrl(event->hw.event_base, 0);
1306 local64_set(&event->hw.prev_count, 0);
1307 }
cc2ad4ba 1308 return x86_perf_event_set_period(event);
f22f54f4
PZ		 1309}
1310
1311static void intel_pmu_reset(void)
1312{
0a3aee0d 1313 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 1314 unsigned long flags;
1315 int idx;
1316
948b1bb8 1317 if (!x86_pmu.num_counters)
f22f54f4
PZ		 1318 return;
1319
1320 local_irq_save(flags);
1321
c767a54b 1322 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 1323
948b1bb8 1324 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 1325 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1326 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 1327 }
948b1bb8 1328 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 1329 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 1330
f22f54f4
PZ		 1331 if (ds)
1332 ds->bts_index = ds->bts_buffer_base;
1333
1334 local_irq_restore(flags);
1335}
1336
1337/*
1338 * This handler is triggered by the local APIC, so the APIC IRQ handling
1339 * rules apply:
1340 */
1341static int intel_pmu_handle_irq(struct pt_regs *regs)
1342{
1343 struct perf_sample_data data;
1344 struct cpu_hw_events *cpuc;
1345 int bit, loops;
2e556b5b 1346 u64 status;
b0b2072d 1347 int handled;
f22f54f4 1348
f22f54f4
PZ		 1349 cpuc = &__get_cpu_var(cpu_hw_events);
1350
2bce5dac 1351 /*
72db5596
AK		 1352 * No known reason to not always do late ACK,
1353 * but just in case do it opt-in.
2bce5dac 1354 */
72db5596
AK		 1355 if (!x86_pmu.late_ack)
1356 apic_write(APIC_LVTPC, APIC_DM_NMI);
3fb2b8dd 1357 intel_pmu_disable_all();
b0b2072d 1358 handled = intel_pmu_drain_bts_buffer();
f22f54f4
PZ		 1359 status = intel_pmu_get_status();
1360 if (!status) {
11164cd4 1361 intel_pmu_enable_all(0);
b0b2072d 1362 return handled;
f22f54f4
PZ		 1363 }
1364
1365 loops = 0;
1366again:
2e556b5b 1367 intel_pmu_ack_status(status);
f22f54f4 1368 if (++loops > 100) {
ae0def05
DH		 1369 static bool warned = false;
1370 if (!warned) {
1371 WARN(1, "perfevents: irq loop stuck!\n");
1372 perf_event_print_debug();
1373 warned = true;
1374 }
f22f54f4 1375 intel_pmu_reset();
3fb2b8dd 1376 goto done;
f22f54f4
PZ		 1377 }
1378
1379 inc_irq_stat(apic_perf_irqs);
ca037701 1380
caff2bef
PZ		 1381 intel_pmu_lbr_read();
1382
ca037701
PZ		 1383 /*
1384 * PEBS overflow sets bit 62 in the global status register
1385 */
de725dec
PZ		 1386 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1387 handled++;
ca037701 1388 x86_pmu.drain_pebs(regs);
de725dec 1389 }
ca037701 1390
2dbf0116
AK		 1391 /*
1392 * To avoid spurious interrupts with perf stat always reset checkpointed
1393 * counters.
1394 */
1395 if (cpuc->events[2] && event_is_checkpointed(cpuc->events[2]))
1396 status |= (1ULL << 2);
1397
984b3f57 1398 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 1399 struct perf_event *event = cpuc->events[bit];
1400
de725dec
PZ		 1401 handled++;
1402
f22f54f4
PZ		 1403 if (!test_bit(bit, cpuc->active_mask))
1404 continue;
1405
1406 if (!intel_pmu_save_and_restart(event))
1407 continue;
1408
fd0d000b 1409 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 1410
60ce0fbd
SE		 1411 if (has_branch_stack(event))
1412 data.br_stack = &cpuc->lbr_stack;
1413
a8b0ca17 1414 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 1415 x86_pmu_stop(event, 0);
f22f54f4
PZ		 1416 }
1417
f22f54f4
PZ		 1418 /*
1419 * Repeat if there is more work to be done:
1420 */
1421 status = intel_pmu_get_status();
1422 if (status)
1423 goto again;
1424
3fb2b8dd 1425done:
11164cd4 1426 intel_pmu_enable_all(0);
72db5596
AK		 1427 /*
1428 * Only unmask the NMI after the overflow counters
1429 * have been reset. This avoids spurious NMIs on
1430 * Haswell CPUs.
1431 */
1432 if (x86_pmu.late_ack)
1433 apic_write(APIC_LVTPC, APIC_DM_NMI);
de725dec 1434 return handled;
f22f54f4
PZ		 1435}
1436
f22f54f4 1437static struct event_constraint *
ca037701 1438intel_bts_constraints(struct perf_event *event)
f22f54f4 1439{
ca037701
PZ		 1440 struct hw_perf_event *hwc = &event->hw;
1441 unsigned int hw_event, bts_event;
f22f54f4 1442
18a073a3
PZ		 1443 if (event->attr.freq)
1444 return NULL;
1445
ca037701
PZ		 1446 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1447 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1448
ca037701 1449 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1450 return &bts_constraint;
ca037701 1451
f22f54f4
PZ		 1452 return NULL;
1453}
1454
5a425294 1455static int intel_alt_er(int idx)
b79e8941
PZ		 1456{
1457 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
5a425294 1458 return idx;
b79e8941 1459
5a425294
PZ		 1460 if (idx == EXTRA_REG_RSP_0)
1461 return EXTRA_REG_RSP_1;
1462
1463 if (idx == EXTRA_REG_RSP_1)
1464 return EXTRA_REG_RSP_0;
1465
1466 return idx;
1467}
1468
1469static void intel_fixup_er(struct perf_event *event, int idx)
1470{
1471 event->hw.extra_reg.idx = idx;
1472
1473 if (idx == EXTRA_REG_RSP_0) {
b79e8941 1474 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 1475 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
b79e8941 1476 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 1477 } else if (idx == EXTRA_REG_RSP_1) {
1478 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 1479 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
5a425294 1480 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 1481 }
b79e8941
PZ		 1482}
1483
efc9f05d
SE		 1484/*
1485 * manage allocation of shared extra msr for certain events
1486 *
1487 * sharing can be:
1488 * per-cpu: to be shared between the various events on a single PMU
1489 * per-core: per-cpu + shared by HT threads
1490 */
a7e3ed1e 1491static struct event_constraint *
efc9f05d 1492__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 1493 struct perf_event *event,
1494 struct hw_perf_event_extra *reg)
a7e3ed1e 1495{
efc9f05d 1496 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 1497 struct er_account *era;
cd8a38d3 1498 unsigned long flags;
5a425294 1499 int idx = reg->idx;
a7e3ed1e 1500
5a425294
PZ		 1501 /*
1502 * reg->alloc can be set due to existing state, so for fake cpuc we
1503 * need to ignore this, otherwise we might fail to allocate proper fake
1504 * state for this extra reg constraint. Also see the comment below.
1505 */
1506 if (reg->alloc && !cpuc->is_fake)
b36817e8 1507 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 1508
b79e8941 1509again:
5a425294 1510 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 1511 /*
1512 * we use spin_lock_irqsave() to avoid lockdep issues when
1513 * passing a fake cpuc
1514 */
1515 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 1516
1517 if (!atomic_read(&era->ref) || era->config == reg->config) {
1518
5a425294
PZ		 1519 /*
1520 * If its a fake cpuc -- as per validate_{group,event}() we
1521 * shouldn't touch event state and we can avoid doing so
1522 * since both will only call get_event_constraints() once
1523 * on each event, this avoids the need for reg->alloc.
1524 *
1525 * Not doing the ER fixup will only result in era->reg being
1526 * wrong, but since we won't actually try and program hardware
1527 * this isn't a problem either.
1528 */
1529 if (!cpuc->is_fake) {
1530 if (idx != reg->idx)
1531 intel_fixup_er(event, idx);
1532
1533 /*
1534 * x86_schedule_events() can call get_event_constraints()
1535 * multiple times on events in the case of incremental
1536 * scheduling(). reg->alloc ensures we only do the ER
1537 * allocation once.
1538 */
1539 reg->alloc = 1;
1540 }
1541
efc9f05d
SE		 1542 /* lock in msr value */
1543 era->config = reg->config;
1544 era->reg = reg->reg;
1545
1546 /* one more user */
1547 atomic_inc(&era->ref);
1548
a7e3ed1e 1549 /*
b36817e8
SE		 1550 * need to call x86_get_event_constraint()
1551 * to check if associated event has constraints
a7e3ed1e 1552 */
b36817e8 1553 c = NULL;
5a425294
PZ		 1554 } else {
1555 idx = intel_alt_er(idx);
1556 if (idx != reg->idx) {
1557 raw_spin_unlock_irqrestore(&era->lock, flags);
1558 goto again;
1559 }
a7e3ed1e 1560 }
cd8a38d3 1561 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 1562
efc9f05d
SE		 1563 return c;
1564}
1565
1566static void
1567__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1568 struct hw_perf_event_extra *reg)
1569{
1570 struct er_account *era;
1571
1572 /*
5a425294
PZ		 1573 * Only put constraint if extra reg was actually allocated. Also takes
1574 * care of event which do not use an extra shared reg.
1575 *
1576 * Also, if this is a fake cpuc we shouldn't touch any event state
1577 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1578 * either since it'll be thrown out.
efc9f05d 1579 */
5a425294 1580 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 1581 return;
1582
1583 era = &cpuc->shared_regs->regs[reg->idx];
1584
1585 /* one fewer user */
1586 atomic_dec(&era->ref);
1587
1588 /* allocate again next time */
1589 reg->alloc = 0;
1590}
1591
1592static struct event_constraint *
1593intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1594 struct perf_event *event)
1595{
b36817e8
SE		 1596 struct event_constraint *c = NULL, *d;
1597 struct hw_perf_event_extra *xreg, *breg;
1598
1599 xreg = &event->hw.extra_reg;
1600 if (xreg->idx != EXTRA_REG_NONE) {
1601 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1602 if (c == &emptyconstraint)
1603 return c;
1604 }
1605 breg = &event->hw.branch_reg;
1606 if (breg->idx != EXTRA_REG_NONE) {
1607 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1608 if (d == &emptyconstraint) {
1609 __intel_shared_reg_put_constraints(cpuc, xreg);
1610 c = d;
1611 }
1612 }
efc9f05d 1613 return c;
a7e3ed1e
AK		 1614}
1615
de0428a7
KW		 1616struct event_constraint *
1617x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1618{
1619 struct event_constraint *c;
1620
1621 if (x86_pmu.event_constraints) {
1622 for_each_event_constraint(c, x86_pmu.event_constraints) {
9fac2cf3 1623 if ((event->hw.config & c->cmask) == c->code) {
9fac2cf3 1624 event->hw.flags |= c->flags;
de0428a7 1625 return c;
9fac2cf3 1626 }
de0428a7
KW		 1627 }
1628 }
1629
1630 return &unconstrained;
1631}
1632
f22f54f4
PZ		 1633static struct event_constraint *
1634intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1635{
1636 struct event_constraint *c;
1637
ca037701
PZ		 1638 c = intel_bts_constraints(event);
1639 if (c)
1640 return c;
1641
1642 c = intel_pebs_constraints(event);
f22f54f4
PZ		 1643 if (c)
1644 return c;
1645
efc9f05d 1646 c = intel_shared_regs_constraints(cpuc, event);
a7e3ed1e
AK		 1647 if (c)
1648 return c;
1649
f22f54f4
PZ		 1650 return x86_get_event_constraints(cpuc, event);
1651}
1652
efc9f05d
SE		 1653static void
1654intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 1655 struct perf_event *event)
1656{
efc9f05d 1657 struct hw_perf_event_extra *reg;
a7e3ed1e 1658
efc9f05d
SE		 1659 reg = &event->hw.extra_reg;
1660 if (reg->idx != EXTRA_REG_NONE)
1661 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 1662
1663 reg = &event->hw.branch_reg;
1664 if (reg->idx != EXTRA_REG_NONE)
1665 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 1666}
a7e3ed1e 1667
efc9f05d
SE		 1668static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1669 struct perf_event *event)
1670{
1671 intel_put_shared_regs_event_constraints(cpuc, event);
a7e3ed1e
AK		 1672}
1673
0780c927 1674static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 1675{
0780c927 1676 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 1677 /*
1678 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1679 * (0x003c) so that we can use it with PEBS.
1680 *
1681 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1682 * PEBS capable. However we can use INST_RETIRED.ANY_P
1683 * (0x00c0), which is a PEBS capable event, to get the same
1684 * count.
1685 *
1686 * INST_RETIRED.ANY_P counts the number of cycles that retires
1687 * CNTMASK instructions. By setting CNTMASK to a value (16)
1688 * larger than the maximum number of instructions that can be
1689 * retired per cycle (4) and then inverting the condition, we
1690 * count all cycles that retire 16 or less instructions, which
1691 * is every cycle.
1692 *
1693 * Thereby we gain a PEBS capable cycle counter.
1694 */
f9b4eeb8
PZ		 1695 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1696
0780c927
PZ		 1697 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1698 event->hw.config = alt_config;
1699 }
1700}
1701
1702static void intel_pebs_aliases_snb(struct perf_event *event)
1703{
1704 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1705 /*
1706 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1707 * (0x003c) so that we can use it with PEBS.
1708 *
1709 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1710 * PEBS capable. However we can use UOPS_RETIRED.ALL
1711 * (0x01c2), which is a PEBS capable event, to get the same
1712 * count.
1713 *
1714 * UOPS_RETIRED.ALL counts the number of cycles that retires
1715 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
1716 * larger than the maximum number of micro-ops that can be
1717 * retired per cycle (4) and then inverting the condition, we
1718 * count all cycles that retire 16 or less micro-ops, which
1719 * is every cycle.
1720 *
1721 * Thereby we gain a PEBS capable cycle counter.
1722 */
1723 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 1724
1725 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1726 event->hw.config = alt_config;
1727 }
0780c927
PZ		 1728}
1729
1730static int intel_pmu_hw_config(struct perf_event *event)
1731{
1732 int ret = x86_pmu_hw_config(event);
1733
1734 if (ret)
1735 return ret;
1736
1737 if (event->attr.precise_ip && x86_pmu.pebs_aliases)
1738 x86_pmu.pebs_aliases(event);
7639dae0 1739
60ce0fbd
SE		 1740 if (intel_pmu_needs_lbr_smpl(event)) {
1741 ret = intel_pmu_setup_lbr_filter(event);
1742 if (ret)
1743 return ret;
1744 }
1745
b4cdc5c2
PZ		 1746 if (event->attr.type != PERF_TYPE_RAW)
1747 return 0;
1748
1749 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1750 return 0;
1751
1752 if (x86_pmu.version < 3)
1753 return -EINVAL;
1754
1755 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1756 return -EACCES;
1757
1758 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1759
1760 return 0;
1761}
1762
144d31e6
GN		 1763struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1764{
1765 if (x86_pmu.guest_get_msrs)
1766 return x86_pmu.guest_get_msrs(nr);
1767 *nr = 0;
1768 return NULL;
1769}
1770EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1771
1772static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1773{
1774 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1775 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1776
1777 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1778 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1779 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 1780 /*
1781 * If PMU counter has PEBS enabled it is not enough to disable counter
1782 * on a guest entry since PEBS memory write can overshoot guest entry
1783 * and corrupt guest memory. Disabling PEBS solves the problem.
1784 */
1785 arr[1].msr = MSR_IA32_PEBS_ENABLE;
1786 arr[1].host = cpuc->pebs_enabled;
1787 arr[1].guest = 0;
144d31e6 1788
26a4f3c0 1789 *nr = 2;
144d31e6
GN		 1790 return arr;
1791}
1792
1793static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1794{
1795 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1796 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1797 int idx;
1798
1799 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1800 struct perf_event *event = cpuc->events[idx];
1801
1802 arr[idx].msr = x86_pmu_config_addr(idx);
1803 arr[idx].host = arr[idx].guest = 0;
1804
1805 if (!test_bit(idx, cpuc->active_mask))
1806 continue;
1807
1808 arr[idx].host = arr[idx].guest =
1809 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1810
1811 if (event->attr.exclude_host)
1812 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1813 else if (event->attr.exclude_guest)
1814 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1815 }
1816
1817 *nr = x86_pmu.num_counters;
1818 return arr;
1819}
1820
1821static void core_pmu_enable_event(struct perf_event *event)
1822{
1823 if (!event->attr.exclude_host)
1824 x86_pmu_enable_event(event);
1825}
1826
1827static void core_pmu_enable_all(int added)
1828{
1829 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1830 int idx;
1831
1832 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1833 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1834
1835 if (!test_bit(idx, cpuc->active_mask) ||
1836 cpuc->events[idx]->attr.exclude_host)
1837 continue;
1838
1839 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1840 }
1841}
1842
3a632cb2
AK		 1843static int hsw_hw_config(struct perf_event *event)
1844{
1845 int ret = intel_pmu_hw_config(event);
1846
1847 if (ret)
1848 return ret;
1849 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
1850 return 0;
1851 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
1852
1853 /*
1854 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
1855 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
1856 * this combination.
1857 */
1858 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
1859 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
1860 event->attr.precise_ip > 0))
1861 return -EOPNOTSUPP;
1862
2dbf0116
AK		 1863 if (event_is_checkpointed(event)) {
1864 /*
1865 * Sampling of checkpointed events can cause situations where
1866 * the CPU constantly aborts because of a overflow, which is
1867 * then checkpointed back and ignored. Forbid checkpointing
1868 * for sampling.
1869 *
1870 * But still allow a long sampling period, so that perf stat
1871 * from KVM works.
1872 */
1873 if (event->attr.sample_period > 0 &&
1874 event->attr.sample_period < 0x7fffffff)
1875 return -EOPNOTSUPP;
1876 }
3a632cb2
AK		 1877 return 0;
1878}
1879
1880static struct event_constraint counter2_constraint =
1881 EVENT_CONSTRAINT(0, 0x4, 0);
1882
1883static struct event_constraint *
1884hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1885{
1886 struct event_constraint *c = intel_get_event_constraints(cpuc, event);
1887
1888 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
1889 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
1890 if (c->idxmsk64 & (1U << 2))
1891 return &counter2_constraint;
1892 return &emptyconstraint;
1893 }
1894
1895 return c;
1896}
1897
641cc938
JO		 1898PMU_FORMAT_ATTR(event, "config:0-7" );
1899PMU_FORMAT_ATTR(umask, "config:8-15" );
1900PMU_FORMAT_ATTR(edge, "config:18" );
1901PMU_FORMAT_ATTR(pc, "config:19" );
1902PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
1903PMU_FORMAT_ATTR(inv, "config:23" );
1904PMU_FORMAT_ATTR(cmask, "config:24-31" );
3a632cb2
AK		 1905PMU_FORMAT_ATTR(in_tx, "config:32");
1906PMU_FORMAT_ATTR(in_tx_cp, "config:33");
641cc938
JO		 1907
1908static struct attribute *intel_arch_formats_attr[] = {
1909 &format_attr_event.attr,
1910 &format_attr_umask.attr,
1911 &format_attr_edge.attr,
1912 &format_attr_pc.attr,
1913 &format_attr_inv.attr,
1914 &format_attr_cmask.attr,
1915 NULL,
1916};
1917
0bf79d44
JO		 1918ssize_t intel_event_sysfs_show(char *page, u64 config)
1919{
1920 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
1921
1922 return x86_event_sysfs_show(page, config, event);
1923}
1924
caaa8be3 1925static __initconst const struct x86_pmu core_pmu = {
f22f54f4
PZ		 1926 .name = "core",
1927 .handle_irq = x86_pmu_handle_irq,
1928 .disable_all = x86_pmu_disable_all,
144d31e6
GN		 1929 .enable_all = core_pmu_enable_all,
1930 .enable = core_pmu_enable_event,
f22f54f4 1931 .disable = x86_pmu_disable_event,
b4cdc5c2 1932 .hw_config = x86_pmu_hw_config,
a072738e 1933 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1934 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1935 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1936 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1937 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1938 .apic = 1,
1939 /*
1940 * Intel PMCs cannot be accessed sanely above 32 bit width,
1941 * so we install an artificial 1<<31 period regardless of
1942 * the generic event period:
1943 */
1944 .max_period = (1ULL << 31) - 1,
1945 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1946 .put_event_constraints = intel_put_event_constraints,
f22f54f4 1947 .event_constraints = intel_core_event_constraints,
144d31e6 1948 .guest_get_msrs = core_guest_get_msrs,
641cc938 1949 .format_attrs = intel_arch_formats_attr,
0bf79d44 1950 .events_sysfs_show = intel_event_sysfs_show,
f22f54f4
PZ		 1951};
1952
de0428a7 1953struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 1954{
1955 struct intel_shared_regs *regs;
1956 int i;
1957
1958 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1959 GFP_KERNEL, cpu_to_node(cpu));
1960 if (regs) {
1961 /*
1962 * initialize the locks to keep lockdep happy
1963 */
1964 for (i = 0; i < EXTRA_REG_MAX; i++)
1965 raw_spin_lock_init(&regs->regs[i].lock);
1966
1967 regs->core_id = -1;
1968 }
1969 return regs;
1970}
1971
a7e3ed1e
AK		 1972static int intel_pmu_cpu_prepare(int cpu)
1973{
1974 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1975
b36817e8 1976 if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
69092624
LM		 1977 return NOTIFY_OK;
1978
efc9f05d
SE		 1979 cpuc->shared_regs = allocate_shared_regs(cpu);
1980 if (!cpuc->shared_regs)
a7e3ed1e
AK		 1981 return NOTIFY_BAD;
1982
a7e3ed1e
AK		 1983 return NOTIFY_OK;
1984}
1985
74846d35
PZ		 1986static void intel_pmu_cpu_starting(int cpu)
1987{
a7e3ed1e
AK		 1988 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1989 int core_id = topology_core_id(cpu);
1990 int i;
1991
69092624
LM		 1992 init_debug_store_on_cpu(cpu);
1993 /*
1994 * Deal with CPUs that don't clear their LBRs on power-up.
1995 */
1996 intel_pmu_lbr_reset();
1997
b36817e8
SE		 1998 cpuc->lbr_sel = NULL;
1999
2000 if (!cpuc->shared_regs)
69092624
LM		 2001 return;
2002
b36817e8
SE		 2003 if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
2004 for_each_cpu(i, topology_thread_cpumask(cpu)) {
2005 struct intel_shared_regs *pc;
a7e3ed1e 2006
b36817e8
SE		 2007 pc = per_cpu(cpu_hw_events, i).shared_regs;
2008 if (pc && pc->core_id == core_id) {
2009 cpuc->kfree_on_online = cpuc->shared_regs;
2010 cpuc->shared_regs = pc;
2011 break;
2012 }
a7e3ed1e 2013 }
b36817e8
SE		 2014 cpuc->shared_regs->core_id = core_id;
2015 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 2016 }
2017
b36817e8
SE		 2018 if (x86_pmu.lbr_sel_map)
2019 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
74846d35
PZ		 2020}
2021
2022static void intel_pmu_cpu_dying(int cpu)
2023{
a7e3ed1e 2024 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
efc9f05d 2025 struct intel_shared_regs *pc;
a7e3ed1e 2026
efc9f05d 2027 pc = cpuc->shared_regs;
a7e3ed1e
AK		 2028 if (pc) {
2029 if (pc->core_id == -1 || --pc->refcnt == 0)
2030 kfree(pc);
efc9f05d 2031 cpuc->shared_regs = NULL;
a7e3ed1e
AK		 2032 }
2033
74846d35
PZ		 2034 fini_debug_store_on_cpu(cpu);
2035}
2036
d010b332
SE		 2037static void intel_pmu_flush_branch_stack(void)
2038{
2039 /*
2040 * Intel LBR does not tag entries with the
2041 * PID of the current task, then we need to
2042 * flush it on ctxsw
2043 * For now, we simply reset it
2044 */
2045 if (x86_pmu.lbr_nr)
2046 intel_pmu_lbr_reset();
2047}
2048
641cc938
JO		 2049PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
2050
a63fcab4
SE		 2051PMU_FORMAT_ATTR(ldlat, "config1:0-15");
2052
641cc938
JO		 2053static struct attribute *intel_arch3_formats_attr[] = {
2054 &format_attr_event.attr,
2055 &format_attr_umask.attr,
2056 &format_attr_edge.attr,
2057 &format_attr_pc.attr,
2058 &format_attr_any.attr,
2059 &format_attr_inv.attr,
2060 &format_attr_cmask.attr,
3a632cb2
AK		 2061 &format_attr_in_tx.attr,
2062 &format_attr_in_tx_cp.attr,
641cc938
JO		 2063
2064 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
a63fcab4 2065 &format_attr_ldlat.attr, /* PEBS load latency */
641cc938
JO		 2066 NULL,
2067};
2068
caaa8be3 2069static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 2070 .name = "Intel",
2071 .handle_irq = intel_pmu_handle_irq,
2072 .disable_all = intel_pmu_disable_all,
2073 .enable_all = intel_pmu_enable_all,
2074 .enable = intel_pmu_enable_event,
2075 .disable = intel_pmu_disable_event,
b4cdc5c2 2076 .hw_config = intel_pmu_hw_config,
a072738e 2077 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 2078 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2079 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2080 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 2081 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2082 .apic = 1,
2083 /*
2084 * Intel PMCs cannot be accessed sanely above 32 bit width,
2085 * so we install an artificial 1<<31 period regardless of
2086 * the generic event period:
2087 */
2088 .max_period = (1ULL << 31) - 1,
3f6da390 2089 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 2090 .put_event_constraints = intel_put_event_constraints,
0780c927 2091 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 2092
641cc938 2093 .format_attrs = intel_arch3_formats_attr,
0bf79d44 2094 .events_sysfs_show = intel_event_sysfs_show,
641cc938 2095
a7e3ed1e 2096 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 2097 .cpu_starting = intel_pmu_cpu_starting,
2098 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 2099 .guest_get_msrs = intel_guest_get_msrs,
d010b332 2100 .flush_branch_stack = intel_pmu_flush_branch_stack,
f22f54f4
PZ		 2101};
2102
c1d6f42f 2103static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 2104{
2105 /*
2106 * PEBS is unreliable due to:
2107 *
2108 * AJ67 - PEBS may experience CPL leaks
2109 * AJ68 - PEBS PMI may be delayed by one event
2110 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
2111 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
2112 *
2113 * AJ67 could be worked around by restricting the OS/USR flags.
2114 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
2115 *
2116 * AJ106 could possibly be worked around by not allowing LBR
2117 * usage from PEBS, including the fixup.
2118 * AJ68 could possibly be worked around by always programming
ec75a716 2119 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 2120 *
2121 * But taken together it might just make sense to not enable PEBS on
2122 * these chips.
2123 */
c767a54b 2124 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 2125 x86_pmu.pebs = 0;
2126 x86_pmu.pebs_constraints = NULL;
2127}
2128
c93dc84c
PZ		 2129static int intel_snb_pebs_broken(int cpu)
2130{
2131 u32 rev = UINT_MAX; /* default to broken for unknown models */
2132
2133 switch (cpu_data(cpu).x86_model) {
2134 case 42: /* SNB */
2135 rev = 0x28;
2136 break;
2137
2138 case 45: /* SNB-EP */
2139 switch (cpu_data(cpu).x86_mask) {
2140 case 6: rev = 0x618; break;
2141 case 7: rev = 0x70c; break;
2142 }
2143 }
2144
2145 return (cpu_data(cpu).microcode < rev);
2146}
2147
2148static void intel_snb_check_microcode(void)
2149{
2150 int pebs_broken = 0;
2151 int cpu;
2152
2153 get_online_cpus();
2154 for_each_online_cpu(cpu) {
2155 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
2156 break;
2157 }
2158 put_online_cpus();
2159
2160 if (pebs_broken == x86_pmu.pebs_broken)
2161 return;
2162
2163 /*
2164 * Serialized by the microcode lock..
2165 */
2166 if (x86_pmu.pebs_broken) {
2167 pr_info("PEBS enabled due to microcode update\n");
2168 x86_pmu.pebs_broken = 0;
2169 } else {
2170 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
2171 x86_pmu.pebs_broken = 1;
2172 }
2173}
2174
c1d6f42f 2175static __init void intel_sandybridge_quirk(void)
6a600a8b 2176{
c93dc84c
PZ		 2177 x86_pmu.check_microcode = intel_snb_check_microcode;
2178 intel_snb_check_microcode();
6a600a8b
PZ		 2179}
2180
c1d6f42f
PZ		 2181static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
2182 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
2183 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
2184 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
2185 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
2186 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
2187 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
2188 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 2189};
2190
c1d6f42f
PZ		 2191static __init void intel_arch_events_quirk(void)
2192{
2193 int bit;
2194
2195 /* disable event that reported as not presend by cpuid */
2196 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
2197 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 2198 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2199 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 2200 }
2201}
2202
2203static __init void intel_nehalem_quirk(void)
2204{
2205 union cpuid10_ebx ebx;
2206
2207 ebx.full = x86_pmu.events_maskl;
2208 if (ebx.split.no_branch_misses_retired) {
2209 /*
2210 * Erratum AAJ80 detected, we work it around by using
2211 * the BR_MISP_EXEC.ANY event. This will over-count
2212 * branch-misses, but it's still much better than the
2213 * architectural event which is often completely bogus:
2214 */
2215 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
2216 ebx.split.no_branch_misses_retired = 0;
2217 x86_pmu.events_maskl = ebx.full;
c767a54b 2218 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 2219 }
2220}
2221
f9134f36
AK		 2222EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
2223EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
2224
4b2c4f1f
AK		 2225/* Haswell special events */
2226EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
2227EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
2228EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
2229EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
2230EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
2231EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
2232EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
2233EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
2234EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
2235EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
2236EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
2237EVENT_ATTR_STR(cycles-ct, cycles_ct,
2238 "event=0x3c,in_tx=1,in_tx_cp=1");
2239
f9134f36 2240static struct attribute *hsw_events_attrs[] = {
4b2c4f1f
AK		 2241 EVENT_PTR(tx_start),
2242 EVENT_PTR(tx_commit),
2243 EVENT_PTR(tx_abort),
2244 EVENT_PTR(tx_capacity),
2245 EVENT_PTR(tx_conflict),
2246 EVENT_PTR(el_start),
2247 EVENT_PTR(el_commit),
2248 EVENT_PTR(el_abort),
2249 EVENT_PTR(el_capacity),
2250 EVENT_PTR(el_conflict),
2251 EVENT_PTR(cycles_t),
2252 EVENT_PTR(cycles_ct),
f9134f36
AK		 2253 EVENT_PTR(mem_ld_hsw),
2254 EVENT_PTR(mem_st_hsw),
2255 NULL
2256};
2257
de0428a7 2258__init int intel_pmu_init(void)
f22f54f4
PZ		 2259{
2260 union cpuid10_edx edx;
2261 union cpuid10_eax eax;
ffb871bc 2262 union cpuid10_ebx ebx;
a1eac7ac 2263 struct event_constraint *c;
f22f54f4 2264 unsigned int unused;
f22f54f4
PZ		 2265 int version;
2266
2267 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 2268 switch (boot_cpu_data.x86) {
2269 case 0x6:
2270 return p6_pmu_init();
e717bf4e
VW		 2271 case 0xb:
2272 return knc_pmu_init();
a072738e
CG		 2273 case 0xf:
2274 return p4_pmu_init();
2275 }
f22f54f4 2276 return -ENODEV;
f22f54f4
PZ		 2277 }
2278
2279 /*
2280 * Check whether the Architectural PerfMon supports
2281 * Branch Misses Retired hw_event or not.
2282 */
ffb871bc
GN		 2283 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
2284 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 2285 return -ENODEV;
2286
2287 version = eax.split.version_id;
2288 if (version < 2)
2289 x86_pmu = core_pmu;
2290 else
2291 x86_pmu = intel_pmu;
2292
2293 x86_pmu.version = version;
948b1bb8
RR		 2294 x86_pmu.num_counters = eax.split.num_counters;
2295 x86_pmu.cntval_bits = eax.split.bit_width;
2296 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 2297
c1d6f42f
PZ		 2298 x86_pmu.events_maskl = ebx.full;
2299 x86_pmu.events_mask_len = eax.split.mask_length;
2300
70ab7003
AK		 2301 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
2302
f22f54f4
PZ		 2303 /*
2304 * Quirk: v2 perfmon does not report fixed-purpose events, so
2305 * assume at least 3 events:
2306 */
2307 if (version > 1)
948b1bb8 2308 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 2309
8db909a7
PZ		 2310 /*
2311 * v2 and above have a perf capabilities MSR
2312 */
2313 if (version > 1) {
2314 u64 capabilities;
2315
2316 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
2317 x86_pmu.intel_cap.capabilities = capabilities;
2318 }
2319
ca037701
PZ		 2320 intel_ds_init();
2321
c1d6f42f
PZ		 2322 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
2323
f22f54f4
PZ		 2324 /*
2325 * Install the hw-cache-events table:
2326 */
2327 switch (boot_cpu_data.x86_model) {
2328 case 14: /* 65 nm core solo/duo, "Yonah" */
2329 pr_cont("Core events, ");
2330 break;
2331
2332 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
c1d6f42f 2333 x86_add_quirk(intel_clovertown_quirk);
f22f54f4
PZ		 2334 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
2335 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
2336 case 29: /* six-core 45 nm xeon "Dunnington" */
2337 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2338 sizeof(hw_cache_event_ids));
2339
caff2bef
PZ		 2340 intel_pmu_lbr_init_core();
2341
f22f54f4 2342 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 2343 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 2344 pr_cont("Core2 events, ");
2345 break;
2346
2347 case 26: /* 45 nm nehalem, "Bloomfield" */
2348 case 30: /* 45 nm nehalem, "Lynnfield" */
134fbadf 2349 case 46: /* 45 nm nehalem-ex, "Beckton" */
f22f54f4
PZ		 2350 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2351 sizeof(hw_cache_event_ids));
e994d7d2
AK		 2352 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2353 sizeof(hw_cache_extra_regs));
f22f54f4 2354
caff2bef
PZ		 2355 intel_pmu_lbr_init_nhm();
2356
f22f54f4 2357 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 2358 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 2359 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 2360 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 2361
f20093ee
SE		 2362 x86_pmu.cpu_events = nhm_events_attrs;
2363
91fc4cc0 2364 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 2365 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2366 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 2367 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2368 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2369 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 2370
c1d6f42f 2371 x86_add_quirk(intel_nehalem_quirk);
ec75a716 2372
11164cd4 2373 pr_cont("Nehalem events, ");
f22f54f4 2374 break;
caff2bef 2375
b622d644 2376 case 28: /* Atom */
0927b482
SL		 2377 case 38: /* Lincroft */
2378 case 39: /* Penwell */
2379 case 53: /* Cloverview */
2380 case 54: /* Cedarview */
f22f54f4
PZ		 2381 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2382 sizeof(hw_cache_event_ids));
2383
caff2bef
PZ		 2384 intel_pmu_lbr_init_atom();
2385
f22f54f4 2386 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 2387 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
f22f54f4
PZ		 2388 pr_cont("Atom events, ");
2389 break;
2390
1fa64180
YZ		 2391 case 55: /* Atom 22nm "Silvermont" */
2392 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
2393 sizeof(hw_cache_event_ids));
2394 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
2395 sizeof(hw_cache_extra_regs));
2396
2397 intel_pmu_lbr_init_atom();
2398
2399 x86_pmu.event_constraints = intel_slm_event_constraints;
2400 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
2401 x86_pmu.extra_regs = intel_slm_extra_regs;
2402 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2403 pr_cont("Silvermont events, ");
2404 break;
2405
f22f54f4
PZ		 2406 case 37: /* 32 nm nehalem, "Clarkdale" */
2407 case 44: /* 32 nm nehalem, "Gulftown" */
b2508e82 2408 case 47: /* 32 nm Xeon E7 */
f22f54f4
PZ		 2409 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
2410 sizeof(hw_cache_event_ids));
e994d7d2
AK		 2411 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2412 sizeof(hw_cache_extra_regs));
f22f54f4 2413
caff2bef
PZ		 2414 intel_pmu_lbr_init_nhm();
2415
f22f54f4 2416 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 2417 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 2418 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 2419 x86_pmu.extra_regs = intel_westmere_extra_regs;
b79e8941 2420 x86_pmu.er_flags |= ERF_HAS_RSP_1;
30112039 2421
f20093ee
SE		 2422 x86_pmu.cpu_events = nhm_events_attrs;
2423
30112039 2424 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 2425 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2426 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 2427 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2428 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2429 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 2430
f22f54f4
PZ		 2431 pr_cont("Westmere events, ");
2432 break;
b622d644 2433
b06b3d49 2434 case 42: /* SandyBridge */
a34668f6 2435 case 45: /* SandyBridge, "Romely-EP" */
47a8863d 2436 x86_add_quirk(intel_sandybridge_quirk);
b06b3d49
LM		 2437 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2438 sizeof(hw_cache_event_ids));
74e6543f
YZ		 2439 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2440 sizeof(hw_cache_extra_regs));
b06b3d49 2441
c5cc2cd9 2442 intel_pmu_lbr_init_snb();
b06b3d49
LM		 2443
2444 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 2445 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 2446 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 2447 if (boot_cpu_data.x86_model == 45)
2448 x86_pmu.extra_regs = intel_snbep_extra_regs;
2449 else
2450 x86_pmu.extra_regs = intel_snb_extra_regs;
ee89cbc2 2451 /* all extra regs are per-cpu when HT is on */
b79e8941
PZ		 2452 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2453 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
e04d1b23 2454
f20093ee
SE		 2455 x86_pmu.cpu_events = snb_events_attrs;
2456
e04d1b23 2457 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 2458 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2459 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2460 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 2461 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2462 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2463
b06b3d49
LM		 2464 pr_cont("SandyBridge events, ");
2465 break;
20a36e39 2466 case 58: /* IvyBridge */
923d8697 2467 case 62: /* IvyBridge EP */
20a36e39
SE		 2468 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2469 sizeof(hw_cache_event_ids));
2470 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2471 sizeof(hw_cache_extra_regs));
2472
2473 intel_pmu_lbr_init_snb();
2474
69943182 2475 x86_pmu.event_constraints = intel_ivb_event_constraints;
20a36e39
SE		 2476 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
2477 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 2478 if (boot_cpu_data.x86_model == 62)
2479 x86_pmu.extra_regs = intel_snbep_extra_regs;
2480 else
2481 x86_pmu.extra_regs = intel_snb_extra_regs;
20a36e39
SE		 2482 /* all extra regs are per-cpu when HT is on */
2483 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2484 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2485
f20093ee
SE		 2486 x86_pmu.cpu_events = snb_events_attrs;
2487
20a36e39
SE		 2488 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2489 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2490 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2491
2492 pr_cont("IvyBridge events, ");
2493 break;
2494
b06b3d49 2495
3a632cb2
AK		 2496 case 60: /* Haswell Client */
2497 case 70:
2498 case 71:
2499 case 63:
0499bd86 2500 case 69:
72db5596 2501 x86_pmu.late_ack = true;
3a632cb2
AK		 2502 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
2503 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
2504
2505 intel_pmu_lbr_init_snb();
2506
2507 x86_pmu.event_constraints = intel_hsw_event_constraints;
3044318f 2508 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3a632cb2 2509 x86_pmu.extra_regs = intel_snb_extra_regs;
3044318f 2510 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3a632cb2
AK		 2511 /* all extra regs are per-cpu when HT is on */
2512 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2513 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2514
2515 x86_pmu.hw_config = hsw_hw_config;
2516 x86_pmu.get_event_constraints = hsw_get_event_constraints;
f9134f36 2517 x86_pmu.cpu_events = hsw_events_attrs;
3a632cb2
AK		 2518 pr_cont("Haswell events, ");
2519 break;
2520
f22f54f4 2521 default:
0af3ac1f
AK		 2522 switch (x86_pmu.version) {
2523 case 1:
2524 x86_pmu.event_constraints = intel_v1_event_constraints;
2525 pr_cont("generic architected perfmon v1, ");
2526 break;
2527 default:
2528 /*
2529 * default constraints for v2 and up
2530 */
2531 x86_pmu.event_constraints = intel_gen_event_constraints;
2532 pr_cont("generic architected perfmon, ");
2533 break;
2534 }
f22f54f4 2535 }
ffb871bc 2536
a1eac7ac
RR		 2537 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
2538 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2539 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
2540 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
2541 }
2542 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2543
2544 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
2545 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2546 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
2547 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
2548 }
2549
2550 x86_pmu.intel_ctrl |=
2551 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
2552
2553 if (x86_pmu.event_constraints) {
2554 /*
2555 * event on fixed counter2 (REF_CYCLES) only works on this
2556 * counter, so do not extend mask to generic counters
2557 */
2558 for_each_event_constraint(c, x86_pmu.event_constraints) {
3a632cb2 2559 if (c->cmask != FIXED_EVENT_FLAGS
a1eac7ac
RR		 2560 || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
2561 continue;
2562 }
2563
2564 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
2565 c->weight += x86_pmu.num_counters;
2566 }
2567 }
2568
069e0c3c
AK		 2569 /* Support full width counters using alternative MSR range */
2570 if (x86_pmu.intel_cap.full_width_write) {
2571 x86_pmu.max_period = x86_pmu.cntval_mask;
2572 x86_pmu.perfctr = MSR_IA32_PMC0;
2573 pr_cont("full-width counters, ");
2574 }
2575
f22f54f4
PZ		 2576 return 0;
2577}
Linux kernel - Deliverables
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