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net/macb: add scatter-gather hw feature
[deliverable/linux.git] / drivers / net / ethernet / cadence / macb.c
CommitLineData
89e5785f 1/*
f75ba50b 2 * Cadence MACB/GEM Ethernet Controller driver
89e5785f
HS		 3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
c220f8cd 11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
89e5785f
HS		 12#include <linux/clk.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
909a8583 17#include <linux/circ_buf.h>
89e5785f
HS		 18#include <linux/slab.h>
19#include <linux/init.h>
60fe716f 20#include <linux/io.h>
2dbfdbb9 21#include <linux/gpio.h>
a6b7a407 22#include <linux/interrupt.h>
89e5785f
HS		 23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
89e5785f 25#include <linux/dma-mapping.h>
84e0cdb0 26#include <linux/platform_data/macb.h>
89e5785f 27#include <linux/platform_device.h>
6c36a707 28#include <linux/phy.h>
b17471f5 29#include <linux/of.h>
fb97a846 30#include <linux/of_device.h>
148cbb53 31#include <linux/of_mdio.h>
fb97a846 32#include <linux/of_net.h>
8ef29f8a 33#include <linux/pinctrl/consumer.h>
89e5785f 34
89e5785f
HS		 35#include "macb.h"
36
1b44791a 37#define MACB_RX_BUFFER_SIZE 128
1b44791a 38#define RX_BUFFER_MULTIPLE 64 /* bytes */
55054a16
HS		 39#define RX_RING_SIZE 512 /* must be power of 2 */
40#define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
89e5785f 41
55054a16
HS		 42#define TX_RING_SIZE 128 /* must be power of 2 */
43#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
89e5785f 44
909a8583
NF		 45/* level of occupied TX descriptors under which we wake up TX process */
46#define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
89e5785f
HS		 47
48#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
49 | MACB_BIT(ISR_ROVR))
e86cd53a
NF		 50#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
51 | MACB_BIT(ISR_RLE) \
52 | MACB_BIT(TXERR))
53#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
54
a4c35ed3
CP		 55#define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
56#define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
57
e86cd53a
NF		 58/*
59 * Graceful stop timeouts in us. We should allow up to
60 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
61 */
62#define MACB_HALT_TIMEOUT 1230
89e5785f 63
55054a16
HS		 64/* Ring buffer accessors */
65static unsigned int macb_tx_ring_wrap(unsigned int index)
66{
67 return index & (TX_RING_SIZE - 1);
68}
69
55054a16
HS		 70static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
71{
72 return &bp->tx_ring[macb_tx_ring_wrap(index)];
73}
74
75static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
76{
77 return &bp->tx_skb[macb_tx_ring_wrap(index)];
78}
79
80static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
81{
82 dma_addr_t offset;
83
84 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
85
86 return bp->tx_ring_dma + offset;
87}
88
89static unsigned int macb_rx_ring_wrap(unsigned int index)
90{
91 return index & (RX_RING_SIZE - 1);
92}
93
94static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
95{
96 return &bp->rx_ring[macb_rx_ring_wrap(index)];
97}
98
99static void *macb_rx_buffer(struct macb *bp, unsigned int index)
100{
1b44791a 101 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
55054a16
HS		 102}
103
314bccc4 104void macb_set_hwaddr(struct macb *bp)
89e5785f
HS		 105{
106 u32 bottom;
107 u16 top;
108
109 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
f75ba50b 110 macb_or_gem_writel(bp, SA1B, bottom);
89e5785f 111 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
f75ba50b 112 macb_or_gem_writel(bp, SA1T, top);
3629a6ce
JE		 113
114 /* Clear unused address register sets */
115 macb_or_gem_writel(bp, SA2B, 0);
116 macb_or_gem_writel(bp, SA2T, 0);
117 macb_or_gem_writel(bp, SA3B, 0);
118 macb_or_gem_writel(bp, SA3T, 0);
119 macb_or_gem_writel(bp, SA4B, 0);
120 macb_or_gem_writel(bp, SA4T, 0);
89e5785f 121}
314bccc4 122EXPORT_SYMBOL_GPL(macb_set_hwaddr);
89e5785f 123
314bccc4 124void macb_get_hwaddr(struct macb *bp)
89e5785f 125{
d25e78aa 126 struct macb_platform_data *pdata;
89e5785f
HS		 127 u32 bottom;
128 u16 top;
129 u8 addr[6];
17b8bb3e
JE		 130 int i;
131
c607a0d9 132 pdata = dev_get_platdata(&bp->pdev->dev);
d25e78aa 133
17b8bb3e
JE		 134 /* Check all 4 address register for vaild address */
135 for (i = 0; i < 4; i++) {
136 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
137 top = macb_or_gem_readl(bp, SA1T + i * 8);
138
d25e78aa
JE		 139 if (pdata && pdata->rev_eth_addr) {
140 addr[5] = bottom & 0xff;
141 addr[4] = (bottom >> 8) & 0xff;
142 addr[3] = (bottom >> 16) & 0xff;
143 addr[2] = (bottom >> 24) & 0xff;
144 addr[1] = top & 0xff;
145 addr[0] = (top & 0xff00) >> 8;
146 } else {
147 addr[0] = bottom & 0xff;
148 addr[1] = (bottom >> 8) & 0xff;
149 addr[2] = (bottom >> 16) & 0xff;
150 addr[3] = (bottom >> 24) & 0xff;
151 addr[4] = top & 0xff;
152 addr[5] = (top >> 8) & 0xff;
153 }
17b8bb3e
JE		 154
155 if (is_valid_ether_addr(addr)) {
156 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
157 return;
158 }
d1d5741d 159 }
17b8bb3e
JE		 160
161 netdev_info(bp->dev, "invalid hw address, using random\n");
162 eth_hw_addr_random(bp->dev);
89e5785f 163}
314bccc4 164EXPORT_SYMBOL_GPL(macb_get_hwaddr);
89e5785f 165
6c36a707 166static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
89e5785f 167{
6c36a707 168 struct macb *bp = bus->priv;
89e5785f
HS		 169 int value;
170
89e5785f
HS		 171 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
172 | MACB_BF(RW, MACB_MAN_READ)
6c36a707
R		 173 | MACB_BF(PHYA, mii_id)
174 | MACB_BF(REGA, regnum)
89e5785f
HS		 175 | MACB_BF(CODE, MACB_MAN_CODE)));
176
6c36a707
R		 177 /* wait for end of transfer */
178 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
179 cpu_relax();
89e5785f
HS		 180
181 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
89e5785f
HS		 182
183 return value;
184}
185
6c36a707
R		 186static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
187 u16 value)
89e5785f 188{
6c36a707 189 struct macb *bp = bus->priv;
89e5785f
HS		 190
191 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
192 | MACB_BF(RW, MACB_MAN_WRITE)
6c36a707
R		 193 | MACB_BF(PHYA, mii_id)
194 | MACB_BF(REGA, regnum)
89e5785f 195 | MACB_BF(CODE, MACB_MAN_CODE)
6c36a707 196 | MACB_BF(DATA, value)));
89e5785f 197
6c36a707
R		 198 /* wait for end of transfer */
199 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
200 cpu_relax();
201
202 return 0;
203}
89e5785f 204
e1824dfe
SB		 205/**
206 * macb_set_tx_clk() - Set a clock to a new frequency
207 * @clk Pointer to the clock to change
208 * @rate New frequency in Hz
209 * @dev Pointer to the struct net_device
210 */
211static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
212{
213 long ferr, rate, rate_rounded;
214
215 switch (speed) {
216 case SPEED_10:
217 rate = 2500000;
218 break;
219 case SPEED_100:
220 rate = 25000000;
221 break;
222 case SPEED_1000:
223 rate = 125000000;
224 break;
225 default:
9319e47c 226 return;
e1824dfe
SB		 227 }
228
229 rate_rounded = clk_round_rate(clk, rate);
230 if (rate_rounded < 0)
231 return;
232
233 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
234 * is not satisfied.
235 */
236 ferr = abs(rate_rounded - rate);
237 ferr = DIV_ROUND_UP(ferr, rate / 100000);
238 if (ferr > 5)
239 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
240 rate);
241
242 if (clk_set_rate(clk, rate_rounded))
243 netdev_err(dev, "adjusting tx_clk failed.\n");
244}
245
6c36a707 246static void macb_handle_link_change(struct net_device *dev)
89e5785f 247{
6c36a707
R		 248 struct macb *bp = netdev_priv(dev);
249 struct phy_device *phydev = bp->phy_dev;
250 unsigned long flags;
89e5785f 251
6c36a707 252 int status_change = 0;
89e5785f 253
6c36a707
R		 254 spin_lock_irqsave(&bp->lock, flags);
255
256 if (phydev->link) {
257 if ((bp->speed != phydev->speed) ||
258 (bp->duplex != phydev->duplex)) {
259 u32 reg;
260
261 reg = macb_readl(bp, NCFGR);
262 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
140b7552
PV		 263 if (macb_is_gem(bp))
264 reg &= ~GEM_BIT(GBE);
6c36a707
R		 265
266 if (phydev->duplex)
267 reg |= MACB_BIT(FD);
179956f4 268 if (phydev->speed == SPEED_100)
6c36a707 269 reg |= MACB_BIT(SPD);
e175587f
NF		 270 if (phydev->speed == SPEED_1000 &&
271 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
140b7552 272 reg |= GEM_BIT(GBE);
6c36a707 273
140b7552 274 macb_or_gem_writel(bp, NCFGR, reg);
6c36a707
R		 275
276 bp->speed = phydev->speed;
277 bp->duplex = phydev->duplex;
278 status_change = 1;
279 }
89e5785f
HS		 280 }
281
6c36a707 282 if (phydev->link != bp->link) {
c8f15686 283 if (!phydev->link) {
6c36a707
R		 284 bp->speed = 0;
285 bp->duplex = -1;
286 }
287 bp->link = phydev->link;
89e5785f 288
6c36a707
R		 289 status_change = 1;
290 }
89e5785f 291
6c36a707
R		 292 spin_unlock_irqrestore(&bp->lock, flags);
293
e1824dfe
SB		 294 if (!IS_ERR(bp->tx_clk))
295 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
296
6c36a707 297 if (status_change) {
03fc4721
NF		 298 if (phydev->link) {
299 netif_carrier_on(dev);
c220f8cd
JI		 300 netdev_info(dev, "link up (%d/%s)\n",
301 phydev->speed,
302 phydev->duplex == DUPLEX_FULL ?
303 "Full" : "Half");
03fc4721
NF		 304 } else {
305 netif_carrier_off(dev);
c220f8cd 306 netdev_info(dev, "link down\n");
03fc4721 307 }
6c36a707 308 }
89e5785f
HS		 309}
310
6c36a707
R		 311/* based on au1000_eth. c*/
312static int macb_mii_probe(struct net_device *dev)
89e5785f 313{
6c36a707 314 struct macb *bp = netdev_priv(dev);
2dbfdbb9 315 struct macb_platform_data *pdata;
7455a76f 316 struct phy_device *phydev;
2dbfdbb9 317 int phy_irq;
7455a76f 318 int ret;
6c36a707 319
7455a76f 320 phydev = phy_find_first(bp->mii_bus);
6c36a707 321 if (!phydev) {
c220f8cd 322 netdev_err(dev, "no PHY found\n");
7daa78e3 323 return -ENXIO;
6c36a707
R		 324 }
325
2dbfdbb9
JE		 326 pdata = dev_get_platdata(&bp->pdev->dev);
327 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
328 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
329 if (!ret) {
330 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
331 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
332 }
333 }
6c36a707
R		 334
335 /* attach the mac to the phy */
f9a8f83b 336 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
fb97a846 337 bp->phy_interface);
7455a76f 338 if (ret) {
c220f8cd 339 netdev_err(dev, "Could not attach to PHY\n");
7455a76f 340 return ret;
6c36a707
R		 341 }
342
343 /* mask with MAC supported features */
e175587f 344 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
140b7552
PV		 345 phydev->supported &= PHY_GBIT_FEATURES;
346 else
347 phydev->supported &= PHY_BASIC_FEATURES;
6c36a707
R		 348
349 phydev->advertising = phydev->supported;
350
351 bp->link = 0;
352 bp->speed = 0;
353 bp->duplex = -1;
354 bp->phy_dev = phydev;
355
356 return 0;
89e5785f
HS		 357}
358
0005f541 359int macb_mii_init(struct macb *bp)
89e5785f 360{
84e0cdb0 361 struct macb_platform_data *pdata;
148cbb53 362 struct device_node *np;
6c36a707 363 int err = -ENXIO, i;
89e5785f 364
3dbda77e 365 /* Enable management port */
6c36a707 366 macb_writel(bp, NCR, MACB_BIT(MPE));
89e5785f 367
298cf9be
LB		 368 bp->mii_bus = mdiobus_alloc();
369 if (bp->mii_bus == NULL) {
370 err = -ENOMEM;
371 goto err_out;
372 }
373
374 bp->mii_bus->name = "MACB_mii_bus";
375 bp->mii_bus->read = &macb_mdio_read;
376 bp->mii_bus->write = &macb_mdio_write;
98d5e57e
FF		 377 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
378 bp->pdev->name, bp->pdev->id);
298cf9be
LB		 379 bp->mii_bus->priv = bp;
380 bp->mii_bus->parent = &bp->dev->dev;
c607a0d9 381 pdata = dev_get_platdata(&bp->pdev->dev);
89e5785f 382
298cf9be
LB		 383 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
384 if (!bp->mii_bus->irq) {
6c36a707 385 err = -ENOMEM;
298cf9be 386 goto err_out_free_mdiobus;
89e5785f
HS		 387 }
388
91523947 389 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
89e5785f 390
148cbb53
BB		 391 np = bp->pdev->dev.of_node;
392 if (np) {
393 /* try dt phy registration */
394 err = of_mdiobus_register(bp->mii_bus, np);
395
396 /* fallback to standard phy registration if no phy were
397 found during dt phy registration */
398 if (!err && !phy_find_first(bp->mii_bus)) {
399 for (i = 0; i < PHY_MAX_ADDR; i++) {
400 struct phy_device *phydev;
401
402 phydev = mdiobus_scan(bp->mii_bus, i);
403 if (IS_ERR(phydev)) {
404 err = PTR_ERR(phydev);
405 break;
406 }
407 }
408
409 if (err)
410 goto err_out_unregister_bus;
411 }
412 } else {
413 for (i = 0; i < PHY_MAX_ADDR; i++)
414 bp->mii_bus->irq[i] = PHY_POLL;
415
416 if (pdata)
417 bp->mii_bus->phy_mask = pdata->phy_mask;
418
419 err = mdiobus_register(bp->mii_bus);
420 }
421
422 if (err)
6c36a707 423 goto err_out_free_mdio_irq;
89e5785f 424
7daa78e3
BB		 425 err = macb_mii_probe(bp->dev);
426 if (err)
6c36a707 427 goto err_out_unregister_bus;
89e5785f 428
6c36a707 429 return 0;
89e5785f 430
6c36a707 431err_out_unregister_bus:
298cf9be 432 mdiobus_unregister(bp->mii_bus);
6c36a707 433err_out_free_mdio_irq:
298cf9be
LB		 434 kfree(bp->mii_bus->irq);
435err_out_free_mdiobus:
436 mdiobus_free(bp->mii_bus);
6c36a707
R		 437err_out:
438 return err;
89e5785f 439}
0005f541 440EXPORT_SYMBOL_GPL(macb_mii_init);
89e5785f
HS		 441
442static void macb_update_stats(struct macb *bp)
443{
444 u32 __iomem *reg = bp->regs + MACB_PFR;
a494ed8e
JI		 445 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
446 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
89e5785f
HS		 447
448 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
449
450 for(; p < end; p++, reg++)
0f0d84e5 451 *p += __raw_readl(reg);
89e5785f
HS		 452}
453
e86cd53a 454static int macb_halt_tx(struct macb *bp)
89e5785f 455{
e86cd53a
NF		 456 unsigned long halt_time, timeout;
457 u32 status;
89e5785f 458
e86cd53a 459 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
89e5785f 460
e86cd53a
NF		 461 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
462 do {
463 halt_time = jiffies;
464 status = macb_readl(bp, TSR);
465 if (!(status & MACB_BIT(TGO)))
466 return 0;
89e5785f 467
e86cd53a
NF		 468 usleep_range(10, 250);
469 } while (time_before(halt_time, timeout));
bdcba151 470
e86cd53a
NF		 471 return -ETIMEDOUT;
472}
39eddb4c 473
a4c35ed3
CP		 474static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
475{
476 if (tx_skb->mapping) {
477 if (tx_skb->mapped_as_page)
478 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
479 tx_skb->size, DMA_TO_DEVICE);
480 else
481 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
482 tx_skb->size, DMA_TO_DEVICE);
483 tx_skb->mapping = 0;
484 }
485
486 if (tx_skb->skb) {
487 dev_kfree_skb_any(tx_skb->skb);
488 tx_skb->skb = NULL;
489 }
490}
491
e86cd53a
NF		 492static void macb_tx_error_task(struct work_struct *work)
493{
494 struct macb *bp = container_of(work, struct macb, tx_error_task);
495 struct macb_tx_skb *tx_skb;
496 struct sk_buff *skb;
497 unsigned int tail;
bdcba151 498
e86cd53a
NF		 499 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n",
500 bp->tx_tail, bp->tx_head);
bdcba151 501
e86cd53a
NF		 502 /* Make sure nobody is trying to queue up new packets */
503 netif_stop_queue(bp->dev);
d3e61457 504
e86cd53a
NF		 505 /*
506 * Stop transmission now
507 * (in case we have just queued new packets)
508 */
509 if (macb_halt_tx(bp))
510 /* Just complain for now, reinitializing TX path can be good */
511 netdev_err(bp->dev, "BUG: halt tx timed out\n");
bdcba151 512
e86cd53a 513 /* No need for the lock here as nobody will interrupt us anymore */
bdcba151 514
e86cd53a
NF		 515 /*
516 * Treat frames in TX queue including the ones that caused the error.
517 * Free transmit buffers in upper layer.
518 */
519 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) {
520 struct macb_dma_desc *desc;
521 u32 ctrl;
55054a16 522
e86cd53a
NF		 523 desc = macb_tx_desc(bp, tail);
524 ctrl = desc->ctrl;
525 tx_skb = macb_tx_skb(bp, tail);
526 skb = tx_skb->skb;
bdcba151 527
e86cd53a 528 if (ctrl & MACB_BIT(TX_USED)) {
a4c35ed3
CP		 529 /* skb is set for the last buffer of the frame */
530 while (!skb) {
531 macb_tx_unmap(bp, tx_skb);
532 tail++;
533 tx_skb = macb_tx_skb(bp, tail);
534 skb = tx_skb->skb;
535 }
536
537 /* ctrl still refers to the first buffer descriptor
538 * since it's the only one written back by the hardware
539 */
540 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
541 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
542 macb_tx_ring_wrap(tail), skb->data);
543 bp->stats.tx_packets++;
544 bp->stats.tx_bytes += skb->len;
545 }
e86cd53a
NF		 546 } else {
547 /*
548 * "Buffers exhausted mid-frame" errors may only happen
549 * if the driver is buggy, so complain loudly about those.
550 * Statistics are updated by hardware.
551 */
552 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
553 netdev_err(bp->dev,
554 "BUG: TX buffers exhausted mid-frame\n");
39eddb4c 555
e86cd53a
NF		 556 desc->ctrl = ctrl | MACB_BIT(TX_USED);
557 }
558
a4c35ed3 559 macb_tx_unmap(bp, tx_skb);
89e5785f
HS		 560 }
561
e86cd53a
NF		 562 /* Make descriptor updates visible to hardware */
563 wmb();
564
565 /* Reinitialize the TX desc queue */
566 macb_writel(bp, TBQP, bp->tx_ring_dma);
567 /* Make TX ring reflect state of hardware */
568 bp->tx_head = bp->tx_tail = 0;
569
570 /* Now we are ready to start transmission again */
571 netif_wake_queue(bp->dev);
572
573 /* Housework before enabling TX IRQ */
574 macb_writel(bp, TSR, macb_readl(bp, TSR));
575 macb_writel(bp, IER, MACB_TX_INT_FLAGS);
576}
577
578static void macb_tx_interrupt(struct macb *bp)
579{
580 unsigned int tail;
581 unsigned int head;
582 u32 status;
583
584 status = macb_readl(bp, TSR);
585 macb_writel(bp, TSR, status);
586
581df9e1
NF		 587 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
588 macb_writel(bp, ISR, MACB_BIT(TCOMP));
749a2b66 589
e86cd53a
NF		 590 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
591 (unsigned long)status);
89e5785f
HS		 592
593 head = bp->tx_head;
55054a16
HS		 594 for (tail = bp->tx_tail; tail != head; tail++) {
595 struct macb_tx_skb *tx_skb;
596 struct sk_buff *skb;
597 struct macb_dma_desc *desc;
598 u32 ctrl;
89e5785f 599
55054a16 600 desc = macb_tx_desc(bp, tail);
89e5785f 601
03dbe05f 602 /* Make hw descriptor updates visible to CPU */
89e5785f 603 rmb();
03dbe05f 604
55054a16 605 ctrl = desc->ctrl;
89e5785f 606
a4c35ed3
CP		 607 /* TX_USED bit is only set by hardware on the very first buffer
608 * descriptor of the transmitted frame.
609 */
55054a16 610 if (!(ctrl & MACB_BIT(TX_USED)))
89e5785f
HS		 611 break;
612
a4c35ed3
CP		 613 /* Process all buffers of the current transmitted frame */
614 for (;; tail++) {
615 tx_skb = macb_tx_skb(bp, tail);
616 skb = tx_skb->skb;
617
618 /* First, update TX stats if needed */
619 if (skb) {
620 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
621 macb_tx_ring_wrap(tail), skb->data);
622 bp->stats.tx_packets++;
623 bp->stats.tx_bytes += skb->len;
624 }
55054a16 625
a4c35ed3
CP		 626 /* Now we can safely release resources */
627 macb_tx_unmap(bp, tx_skb);
628
629 /* skb is set only for the last buffer of the frame.
630 * WARNING: at this point skb has been freed by
631 * macb_tx_unmap().
632 */
633 if (skb)
634 break;
635 }
89e5785f
HS		 636 }
637
638 bp->tx_tail = tail;
55054a16 639 if (netif_queue_stopped(bp->dev)
909a8583
NF		 640 && CIRC_CNT(bp->tx_head, bp->tx_tail,
641 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
89e5785f
HS		 642 netif_wake_queue(bp->dev);
643}
644
4df95131
NF		 645static void gem_rx_refill(struct macb *bp)
646{
647 unsigned int entry;
648 struct sk_buff *skb;
4df95131
NF		 649 dma_addr_t paddr;
650
651 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
4df95131 652 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
4df95131
NF		 653
654 /* Make hw descriptor updates visible to CPU */
655 rmb();
656
4df95131
NF		 657 bp->rx_prepared_head++;
658
4df95131
NF		 659 if (bp->rx_skbuff[entry] == NULL) {
660 /* allocate sk_buff for this free entry in ring */
661 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
662 if (unlikely(skb == NULL)) {
663 netdev_err(bp->dev,
664 "Unable to allocate sk_buff\n");
665 break;
666 }
4df95131
NF		 667
668 /* now fill corresponding descriptor entry */
669 paddr = dma_map_single(&bp->pdev->dev, skb->data,
670 bp->rx_buffer_size, DMA_FROM_DEVICE);
92030908
SB		 671 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
672 dev_kfree_skb(skb);
673 break;
674 }
675
676 bp->rx_skbuff[entry] = skb;
4df95131
NF		 677
678 if (entry == RX_RING_SIZE - 1)
679 paddr |= MACB_BIT(RX_WRAP);
680 bp->rx_ring[entry].addr = paddr;
681 bp->rx_ring[entry].ctrl = 0;
682
683 /* properly align Ethernet header */
684 skb_reserve(skb, NET_IP_ALIGN);
685 }
686 }
687
688 /* Make descriptor updates visible to hardware */
689 wmb();
690
691 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
692 bp->rx_prepared_head, bp->rx_tail);
693}
694
695/* Mark DMA descriptors from begin up to and not including end as unused */
696static void discard_partial_frame(struct macb *bp, unsigned int begin,
697 unsigned int end)
698{
699 unsigned int frag;
700
701 for (frag = begin; frag != end; frag++) {
702 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
703 desc->addr &= ~MACB_BIT(RX_USED);
704 }
705
706 /* Make descriptor updates visible to hardware */
707 wmb();
708
709 /*
710 * When this happens, the hardware stats registers for
711 * whatever caused this is updated, so we don't have to record
712 * anything.
713 */
714}
715
716static int gem_rx(struct macb *bp, int budget)
717{
718 unsigned int len;
719 unsigned int entry;
720 struct sk_buff *skb;
721 struct macb_dma_desc *desc;
722 int count = 0;
723
724 while (count < budget) {
725 u32 addr, ctrl;
726
727 entry = macb_rx_ring_wrap(bp->rx_tail);
728 desc = &bp->rx_ring[entry];
729
730 /* Make hw descriptor updates visible to CPU */
731 rmb();
732
733 addr = desc->addr;
734 ctrl = desc->ctrl;
735
736 if (!(addr & MACB_BIT(RX_USED)))
737 break;
738
4df95131
NF		 739 bp->rx_tail++;
740 count++;
741
742 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
743 netdev_err(bp->dev,
744 "not whole frame pointed by descriptor\n");
745 bp->stats.rx_dropped++;
746 break;
747 }
748 skb = bp->rx_skbuff[entry];
749 if (unlikely(!skb)) {
750 netdev_err(bp->dev,
751 "inconsistent Rx descriptor chain\n");
752 bp->stats.rx_dropped++;
753 break;
754 }
755 /* now everything is ready for receiving packet */
756 bp->rx_skbuff[entry] = NULL;
757 len = MACB_BFEXT(RX_FRMLEN, ctrl);
758
759 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
760
761 skb_put(skb, len);
762 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
763 dma_unmap_single(&bp->pdev->dev, addr,
48330e08 764 bp->rx_buffer_size, DMA_FROM_DEVICE);
4df95131
NF		 765
766 skb->protocol = eth_type_trans(skb, bp->dev);
767 skb_checksum_none_assert(skb);
768
769 bp->stats.rx_packets++;
770 bp->stats.rx_bytes += skb->len;
771
772#if defined(DEBUG) && defined(VERBOSE_DEBUG)
773 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
774 skb->len, skb->csum);
775 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
776 skb->mac_header, 16, true);
777 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
778 skb->data, 32, true);
779#endif
780
781 netif_receive_skb(skb);
782 }
783
784 gem_rx_refill(bp);
785
786 return count;
787}
788
89e5785f
HS		 789static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
790 unsigned int last_frag)
791{
792 unsigned int len;
793 unsigned int frag;
29bc2e1e 794 unsigned int offset;
89e5785f 795 struct sk_buff *skb;
55054a16 796 struct macb_dma_desc *desc;
89e5785f 797
55054a16
HS		 798 desc = macb_rx_desc(bp, last_frag);
799 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
89e5785f 800
a268adb1 801 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
55054a16
HS		 802 macb_rx_ring_wrap(first_frag),
803 macb_rx_ring_wrap(last_frag), len);
89e5785f 804
29bc2e1e
HS		 805 /*
806 * The ethernet header starts NET_IP_ALIGN bytes into the
807 * first buffer. Since the header is 14 bytes, this makes the
808 * payload word-aligned.
809 *
810 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
811 * the two padding bytes into the skb so that we avoid hitting
812 * the slowpath in memcpy(), and pull them off afterwards.
813 */
814 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
89e5785f
HS		 815 if (!skb) {
816 bp->stats.rx_dropped++;
55054a16
HS		 817 for (frag = first_frag; ; frag++) {
818 desc = macb_rx_desc(bp, frag);
819 desc->addr &= ~MACB_BIT(RX_USED);
89e5785f
HS		 820 if (frag == last_frag)
821 break;
822 }
03dbe05f
HS		 823
824 /* Make descriptor updates visible to hardware */
89e5785f 825 wmb();
03dbe05f 826
89e5785f
HS		 827 return 1;
828 }
829
29bc2e1e
HS		 830 offset = 0;
831 len += NET_IP_ALIGN;
bc8acf2c 832 skb_checksum_none_assert(skb);
89e5785f
HS		 833 skb_put(skb, len);
834
55054a16 835 for (frag = first_frag; ; frag++) {
1b44791a 836 unsigned int frag_len = bp->rx_buffer_size;
89e5785f
HS		 837
838 if (offset + frag_len > len) {
839 BUG_ON(frag != last_frag);
840 frag_len = len - offset;
841 }
27d7ff46 842 skb_copy_to_linear_data_offset(skb, offset,
55054a16 843 macb_rx_buffer(bp, frag), frag_len);
1b44791a 844 offset += bp->rx_buffer_size;
55054a16
HS		 845 desc = macb_rx_desc(bp, frag);
846 desc->addr &= ~MACB_BIT(RX_USED);
89e5785f
HS		 847
848 if (frag == last_frag)
849 break;
850 }
851
03dbe05f
HS		 852 /* Make descriptor updates visible to hardware */
853 wmb();
854
29bc2e1e 855 __skb_pull(skb, NET_IP_ALIGN);
89e5785f
HS		 856 skb->protocol = eth_type_trans(skb, bp->dev);
857
858 bp->stats.rx_packets++;
29bc2e1e 859 bp->stats.rx_bytes += skb->len;
a268adb1 860 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
c220f8cd 861 skb->len, skb->csum);
89e5785f
HS		 862 netif_receive_skb(skb);
863
864 return 0;
865}
866
89e5785f
HS		 867static int macb_rx(struct macb *bp, int budget)
868{
869 int received = 0;
55054a16 870 unsigned int tail;
89e5785f
HS		 871 int first_frag = -1;
872
55054a16
HS		 873 for (tail = bp->rx_tail; budget > 0; tail++) {
874 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
89e5785f
HS		 875 u32 addr, ctrl;
876
03dbe05f 877 /* Make hw descriptor updates visible to CPU */
89e5785f 878 rmb();
03dbe05f 879
55054a16
HS		 880 addr = desc->addr;
881 ctrl = desc->ctrl;
89e5785f
HS		 882
883 if (!(addr & MACB_BIT(RX_USED)))
884 break;
885
886 if (ctrl & MACB_BIT(RX_SOF)) {
887 if (first_frag != -1)
888 discard_partial_frame(bp, first_frag, tail);
889 first_frag = tail;
890 }
891
892 if (ctrl & MACB_BIT(RX_EOF)) {
893 int dropped;
894 BUG_ON(first_frag == -1);
895
896 dropped = macb_rx_frame(bp, first_frag, tail);
897 first_frag = -1;
898 if (!dropped) {
899 received++;
900 budget--;
901 }
902 }
903 }
904
905 if (first_frag != -1)
906 bp->rx_tail = first_frag;
907 else
908 bp->rx_tail = tail;
909
910 return received;
911}
912
bea3348e 913static int macb_poll(struct napi_struct *napi, int budget)
89e5785f 914{
bea3348e 915 struct macb *bp = container_of(napi, struct macb, napi);
bea3348e 916 int work_done;
89e5785f
HS		 917 u32 status;
918
919 status = macb_readl(bp, RSR);
920 macb_writel(bp, RSR, status);
921
bea3348e 922 work_done = 0;
89e5785f 923
a268adb1 924 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
c220f8cd 925 (unsigned long)status, budget);
89e5785f 926
4df95131 927 work_done = bp->macbgem_ops.mog_rx(bp, budget);
b336369c 928 if (work_done < budget) {
288379f0 929 napi_complete(napi);
89e5785f 930
8770e91a
NF		 931 /* Packets received while interrupts were disabled */
932 status = macb_readl(bp, RSR);
504ad98d 933 if (status) {
02f7a34f
SB		 934 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
935 macb_writel(bp, ISR, MACB_BIT(RCOMP));
8770e91a 936 napi_reschedule(napi);
02f7a34f
SB		 937 } else {
938 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
939 }
b336369c 940 }
89e5785f
HS		 941
942 /* TODO: Handle errors */
943
bea3348e 944 return work_done;
89e5785f
HS		 945}
946
947static irqreturn_t macb_interrupt(int irq, void *dev_id)
948{
949 struct net_device *dev = dev_id;
950 struct macb *bp = netdev_priv(dev);
951 u32 status;
952
953 status = macb_readl(bp, ISR);
954
955 if (unlikely(!status))
956 return IRQ_NONE;
957
958 spin_lock(&bp->lock);
959
960 while (status) {
89e5785f
HS		 961 /* close possible race with dev_close */
962 if (unlikely(!netif_running(dev))) {
95ebcea6 963 macb_writel(bp, IDR, -1);
89e5785f
HS		 964 break;
965 }
966
a268adb1
HS		 967 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
968
89e5785f 969 if (status & MACB_RX_INT_FLAGS) {
b336369c
JH		 970 /*
971 * There's no point taking any more interrupts
972 * until we have processed the buffers. The
973 * scheduling call may fail if the poll routine
974 * is already scheduled, so disable interrupts
975 * now.
976 */
977 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
581df9e1
NF		 978 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
979 macb_writel(bp, ISR, MACB_BIT(RCOMP));
b336369c 980
288379f0 981 if (napi_schedule_prep(&bp->napi)) {
a268adb1 982 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
288379f0 983 __napi_schedule(&bp->napi);
89e5785f
HS		 984 }
985 }
986
e86cd53a
NF		 987 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
988 macb_writel(bp, IDR, MACB_TX_INT_FLAGS);
989 schedule_work(&bp->tx_error_task);
6a027b70
SB		 990
991 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
992 macb_writel(bp, ISR, MACB_TX_ERR_FLAGS);
993
e86cd53a
NF		 994 break;
995 }
996
997 if (status & MACB_BIT(TCOMP))
998 macb_tx_interrupt(bp);
89e5785f
HS		 999
1000 /*
1001 * Link change detection isn't possible with RMII, so we'll
1002 * add that if/when we get our hands on a full-blown MII PHY.
1003 */
1004
b19f7f71
AS		 1005 if (status & MACB_BIT(ISR_ROVR)) {
1006 /* We missed at least one packet */
f75ba50b
JI		 1007 if (macb_is_gem(bp))
1008 bp->hw_stats.gem.rx_overruns++;
1009 else
1010 bp->hw_stats.macb.rx_overruns++;
6a027b70
SB		 1011
1012 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1013 macb_writel(bp, ISR, MACB_BIT(ISR_ROVR));
b19f7f71
AS		 1014 }
1015
89e5785f
HS		 1016 if (status & MACB_BIT(HRESP)) {
1017 /*
c220f8cd
JI		 1018 * TODO: Reset the hardware, and maybe move the
1019 * netdev_err to a lower-priority context as well
1020 * (work queue?)
89e5785f 1021 */
c220f8cd 1022 netdev_err(dev, "DMA bus error: HRESP not OK\n");
6a027b70
SB		 1023
1024 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1025 macb_writel(bp, ISR, MACB_BIT(HRESP));
89e5785f
HS		 1026 }
1027
1028 status = macb_readl(bp, ISR);
1029 }
1030
1031 spin_unlock(&bp->lock);
1032
1033 return IRQ_HANDLED;
1034}
1035
6e8cf5c0
TP		 1036#ifdef CONFIG_NET_POLL_CONTROLLER
1037/*
1038 * Polling receive - used by netconsole and other diagnostic tools
1039 * to allow network i/o with interrupts disabled.
1040 */
1041static void macb_poll_controller(struct net_device *dev)
1042{
1043 unsigned long flags;
1044
1045 local_irq_save(flags);
1046 macb_interrupt(dev->irq, dev);
1047 local_irq_restore(flags);
1048}
1049#endif
1050
a4c35ed3
CP		 1051static inline unsigned int macb_count_tx_descriptors(struct macb *bp,
1052 unsigned int len)
1053{
1054 return (len + bp->max_tx_length - 1) / bp->max_tx_length;
1055}
1056
1057static unsigned int macb_tx_map(struct macb *bp,
1058 struct sk_buff *skb)
89e5785f 1059{
89e5785f 1060 dma_addr_t mapping;
a4c35ed3
CP		 1061 unsigned int len, entry, i, tx_head = bp->tx_head;
1062 struct macb_tx_skb *tx_skb = NULL;
55054a16 1063 struct macb_dma_desc *desc;
a4c35ed3
CP		 1064 unsigned int offset, size, count = 0;
1065 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1066 unsigned int eof = 1;
89e5785f 1067 u32 ctrl;
a4c35ed3
CP		 1068
1069 /* First, map non-paged data */
1070 len = skb_headlen(skb);
1071 offset = 0;
1072 while (len) {
1073 size = min(len, bp->max_tx_length);
1074 entry = macb_tx_ring_wrap(tx_head);
1075 tx_skb = &bp->tx_skb[entry];
1076
1077 mapping = dma_map_single(&bp->pdev->dev,
1078 skb->data + offset,
1079 size, DMA_TO_DEVICE);
1080 if (dma_mapping_error(&bp->pdev->dev, mapping))
1081 goto dma_error;
1082
1083 /* Save info to properly release resources */
1084 tx_skb->skb = NULL;
1085 tx_skb->mapping = mapping;
1086 tx_skb->size = size;
1087 tx_skb->mapped_as_page = false;
1088
1089 len -= size;
1090 offset += size;
1091 count++;
1092 tx_head++;
1093 }
1094
1095 /* Then, map paged data from fragments */
1096 for (f = 0; f < nr_frags; f++) {
1097 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1098
1099 len = skb_frag_size(frag);
1100 offset = 0;
1101 while (len) {
1102 size = min(len, bp->max_tx_length);
1103 entry = macb_tx_ring_wrap(tx_head);
1104 tx_skb = &bp->tx_skb[entry];
1105
1106 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1107 offset, size, DMA_TO_DEVICE);
1108 if (dma_mapping_error(&bp->pdev->dev, mapping))
1109 goto dma_error;
1110
1111 /* Save info to properly release resources */
1112 tx_skb->skb = NULL;
1113 tx_skb->mapping = mapping;
1114 tx_skb->size = size;
1115 tx_skb->mapped_as_page = true;
1116
1117 len -= size;
1118 offset += size;
1119 count++;
1120 tx_head++;
1121 }
1122 }
1123
1124 /* Should never happen */
1125 if (unlikely(tx_skb == NULL)) {
1126 netdev_err(bp->dev, "BUG! empty skb!\n");
1127 return 0;
1128 }
1129
1130 /* This is the last buffer of the frame: save socket buffer */
1131 tx_skb->skb = skb;
1132
1133 /* Update TX ring: update buffer descriptors in reverse order
1134 * to avoid race condition
1135 */
1136
1137 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1138 * to set the end of TX queue
1139 */
1140 i = tx_head;
1141 entry = macb_tx_ring_wrap(i);
1142 ctrl = MACB_BIT(TX_USED);
1143 desc = &bp->tx_ring[entry];
1144 desc->ctrl = ctrl;
1145
1146 do {
1147 i--;
1148 entry = macb_tx_ring_wrap(i);
1149 tx_skb = &bp->tx_skb[entry];
1150 desc = &bp->tx_ring[entry];
1151
1152 ctrl = (u32)tx_skb->size;
1153 if (eof) {
1154 ctrl |= MACB_BIT(TX_LAST);
1155 eof = 0;
1156 }
1157 if (unlikely(entry == (TX_RING_SIZE - 1)))
1158 ctrl |= MACB_BIT(TX_WRAP);
1159
1160 /* Set TX buffer descriptor */
1161 desc->addr = tx_skb->mapping;
1162 /* desc->addr must be visible to hardware before clearing
1163 * 'TX_USED' bit in desc->ctrl.
1164 */
1165 wmb();
1166 desc->ctrl = ctrl;
1167 } while (i != bp->tx_head);
1168
1169 bp->tx_head = tx_head;
1170
1171 return count;
1172
1173dma_error:
1174 netdev_err(bp->dev, "TX DMA map failed\n");
1175
1176 for (i = bp->tx_head; i != tx_head; i++) {
1177 tx_skb = macb_tx_skb(bp, i);
1178
1179 macb_tx_unmap(bp, tx_skb);
1180 }
1181
1182 return 0;
1183}
1184
1185static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1186{
1187 struct macb *bp = netdev_priv(dev);
4871953c 1188 unsigned long flags;
a4c35ed3 1189 unsigned int count, nr_frags, frag_size, f;
89e5785f 1190
a268adb1
HS		 1191#if defined(DEBUG) && defined(VERBOSE_DEBUG)
1192 netdev_vdbg(bp->dev,
c220f8cd
JI		 1193 "start_xmit: len %u head %p data %p tail %p end %p\n",
1194 skb->len, skb->head, skb->data,
1195 skb_tail_pointer(skb), skb_end_pointer(skb));
1196 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1197 skb->data, 16, true);
89e5785f
HS		 1198#endif
1199
a4c35ed3
CP		 1200 /* Count how many TX buffer descriptors are needed to send this
1201 * socket buffer: skb fragments of jumbo frames may need to be
1202 * splitted into many buffer descriptors.
1203 */
1204 count = macb_count_tx_descriptors(bp, skb_headlen(skb));
1205 nr_frags = skb_shinfo(skb)->nr_frags;
1206 for (f = 0; f < nr_frags; f++) {
1207 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1208 count += macb_count_tx_descriptors(bp, frag_size);
1209 }
1210
4871953c 1211 spin_lock_irqsave(&bp->lock, flags);
89e5785f
HS		 1212
1213 /* This is a hard error, log it. */
a4c35ed3 1214 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < count) {
89e5785f 1215 netif_stop_queue(dev);
4871953c 1216 spin_unlock_irqrestore(&bp->lock, flags);
c220f8cd
JI		 1217 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1218 bp->tx_head, bp->tx_tail);
5b548140 1219 return NETDEV_TX_BUSY;
89e5785f
HS		 1220 }
1221
a4c35ed3
CP		 1222 /* Map socket buffer for DMA transfer */
1223 if (!macb_tx_map(bp, skb)) {
c88b5b6a 1224 dev_kfree_skb_any(skb);
92030908
SB		 1225 goto unlock;
1226 }
55054a16 1227
03dbe05f 1228 /* Make newly initialized descriptor visible to hardware */
89e5785f
HS		 1229 wmb();
1230
e072092f
RC		 1231 skb_tx_timestamp(skb);
1232
89e5785f
HS		 1233 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1234
909a8583 1235 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1)
89e5785f
HS		 1236 netif_stop_queue(dev);
1237
92030908 1238unlock:
4871953c 1239 spin_unlock_irqrestore(&bp->lock, flags);
89e5785f 1240
6ed10654 1241 return NETDEV_TX_OK;
89e5785f
HS		 1242}
1243
4df95131 1244static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1b44791a
NF		 1245{
1246 if (!macb_is_gem(bp)) {
1247 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1248 } else {
4df95131 1249 bp->rx_buffer_size = size;
1b44791a 1250
1b44791a 1251 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
4df95131
NF		 1252 netdev_dbg(bp->dev,
1253 "RX buffer must be multiple of %d bytes, expanding\n",
1b44791a
NF		 1254 RX_BUFFER_MULTIPLE);
1255 bp->rx_buffer_size =
4df95131 1256 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1b44791a 1257 }
1b44791a 1258 }
4df95131
NF		 1259
1260 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1261 bp->dev->mtu, bp->rx_buffer_size);
1b44791a
NF		 1262}
1263
4df95131
NF		 1264static void gem_free_rx_buffers(struct macb *bp)
1265{
1266 struct sk_buff *skb;
1267 struct macb_dma_desc *desc;
1268 dma_addr_t addr;
1269 int i;
1270
1271 if (!bp->rx_skbuff)
1272 return;
1273
1274 for (i = 0; i < RX_RING_SIZE; i++) {
1275 skb = bp->rx_skbuff[i];
1276
1277 if (skb == NULL)
1278 continue;
1279
1280 desc = &bp->rx_ring[i];
1281 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
ccd6d0a9 1282 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
4df95131
NF		 1283 DMA_FROM_DEVICE);
1284 dev_kfree_skb_any(skb);
1285 skb = NULL;
1286 }
1287
1288 kfree(bp->rx_skbuff);
1289 bp->rx_skbuff = NULL;
1290}
1291
1292static void macb_free_rx_buffers(struct macb *bp)
1293{
1294 if (bp->rx_buffers) {
1295 dma_free_coherent(&bp->pdev->dev,
1296 RX_RING_SIZE * bp->rx_buffer_size,
1297 bp->rx_buffers, bp->rx_buffers_dma);
1298 bp->rx_buffers = NULL;
1299 }
1300}
1b44791a 1301
89e5785f
HS		 1302static void macb_free_consistent(struct macb *bp)
1303{
1304 if (bp->tx_skb) {
1305 kfree(bp->tx_skb);
1306 bp->tx_skb = NULL;
1307 }
4df95131 1308 bp->macbgem_ops.mog_free_rx_buffers(bp);
89e5785f
HS		 1309 if (bp->rx_ring) {
1310 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1311 bp->rx_ring, bp->rx_ring_dma);
1312 bp->rx_ring = NULL;
1313 }
1314 if (bp->tx_ring) {
1315 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1316 bp->tx_ring, bp->tx_ring_dma);
1317 bp->tx_ring = NULL;
1318 }
4df95131
NF		 1319}
1320
1321static int gem_alloc_rx_buffers(struct macb *bp)
1322{
1323 int size;
1324
1325 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1326 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1327 if (!bp->rx_skbuff)
1328 return -ENOMEM;
1329 else
1330 netdev_dbg(bp->dev,
1331 "Allocated %d RX struct sk_buff entries at %p\n",
1332 RX_RING_SIZE, bp->rx_skbuff);
1333 return 0;
1334}
1335
1336static int macb_alloc_rx_buffers(struct macb *bp)
1337{
1338 int size;
1339
1340 size = RX_RING_SIZE * bp->rx_buffer_size;
1341 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1342 &bp->rx_buffers_dma, GFP_KERNEL);
1343 if (!bp->rx_buffers)
1344 return -ENOMEM;
1345 else
1346 netdev_dbg(bp->dev,
1347 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1348 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1349 return 0;
89e5785f
HS		 1350}
1351
1352static int macb_alloc_consistent(struct macb *bp)
1353{
1354 int size;
1355
55054a16 1356 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
89e5785f
HS		 1357 bp->tx_skb = kmalloc(size, GFP_KERNEL);
1358 if (!bp->tx_skb)
1359 goto out_err;
1360
1361 size = RX_RING_BYTES;
1362 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1363 &bp->rx_ring_dma, GFP_KERNEL);
1364 if (!bp->rx_ring)
1365 goto out_err;
c220f8cd
JI		 1366 netdev_dbg(bp->dev,
1367 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1368 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
89e5785f
HS		 1369
1370 size = TX_RING_BYTES;
1371 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1372 &bp->tx_ring_dma, GFP_KERNEL);
1373 if (!bp->tx_ring)
1374 goto out_err;
c220f8cd
JI		 1375 netdev_dbg(bp->dev,
1376 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
1377 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
89e5785f 1378
4df95131 1379 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
89e5785f 1380 goto out_err;
89e5785f
HS		 1381
1382 return 0;
1383
1384out_err:
1385 macb_free_consistent(bp);
1386 return -ENOMEM;
1387}
1388
4df95131
NF		 1389static void gem_init_rings(struct macb *bp)
1390{
1391 int i;
1392
1393 for (i = 0; i < TX_RING_SIZE; i++) {
1394 bp->tx_ring[i].addr = 0;
1395 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1396 }
1397 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1398
1399 bp->rx_tail = bp->rx_prepared_head = bp->tx_head = bp->tx_tail = 0;
1400
1401 gem_rx_refill(bp);
1402}
1403
89e5785f
HS		 1404static void macb_init_rings(struct macb *bp)
1405{
1406 int i;
1407 dma_addr_t addr;
1408
1409 addr = bp->rx_buffers_dma;
1410 for (i = 0; i < RX_RING_SIZE; i++) {
1411 bp->rx_ring[i].addr = addr;
1412 bp->rx_ring[i].ctrl = 0;
1b44791a 1413 addr += bp->rx_buffer_size;
89e5785f
HS		 1414 }
1415 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1416
1417 for (i = 0; i < TX_RING_SIZE; i++) {
1418 bp->tx_ring[i].addr = 0;
1419 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1420 }
1421 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1422
1423 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
1424}
1425
1426static void macb_reset_hw(struct macb *bp)
1427{
89e5785f
HS		 1428 /*
1429 * Disable RX and TX (XXX: Should we halt the transmission
1430 * more gracefully?)
1431 */
1432 macb_writel(bp, NCR, 0);
1433
1434 /* Clear the stats registers (XXX: Update stats first?) */
1435 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1436
1437 /* Clear all status flags */
95ebcea6
JE		 1438 macb_writel(bp, TSR, -1);
1439 macb_writel(bp, RSR, -1);
89e5785f
HS		 1440
1441 /* Disable all interrupts */
95ebcea6 1442 macb_writel(bp, IDR, -1);
89e5785f
HS		 1443 macb_readl(bp, ISR);
1444}
1445
70c9f3d4
JI		 1446static u32 gem_mdc_clk_div(struct macb *bp)
1447{
1448 u32 config;
1449 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1450
1451 if (pclk_hz <= 20000000)
1452 config = GEM_BF(CLK, GEM_CLK_DIV8);
1453 else if (pclk_hz <= 40000000)
1454 config = GEM_BF(CLK, GEM_CLK_DIV16);
1455 else if (pclk_hz <= 80000000)
1456 config = GEM_BF(CLK, GEM_CLK_DIV32);
1457 else if (pclk_hz <= 120000000)
1458 config = GEM_BF(CLK, GEM_CLK_DIV48);
1459 else if (pclk_hz <= 160000000)
1460 config = GEM_BF(CLK, GEM_CLK_DIV64);
1461 else
1462 config = GEM_BF(CLK, GEM_CLK_DIV96);
1463
1464 return config;
1465}
1466
1467static u32 macb_mdc_clk_div(struct macb *bp)
1468{
1469 u32 config;
1470 unsigned long pclk_hz;
1471
1472 if (macb_is_gem(bp))
1473 return gem_mdc_clk_div(bp);
1474
1475 pclk_hz = clk_get_rate(bp->pclk);
1476 if (pclk_hz <= 20000000)
1477 config = MACB_BF(CLK, MACB_CLK_DIV8);
1478 else if (pclk_hz <= 40000000)
1479 config = MACB_BF(CLK, MACB_CLK_DIV16);
1480 else if (pclk_hz <= 80000000)
1481 config = MACB_BF(CLK, MACB_CLK_DIV32);
1482 else
1483 config = MACB_BF(CLK, MACB_CLK_DIV64);
1484
1485 return config;
1486}
1487
757a03c6
JI		 1488/*
1489 * Get the DMA bus width field of the network configuration register that we
1490 * should program. We find the width from decoding the design configuration
1491 * register to find the maximum supported data bus width.
1492 */
1493static u32 macb_dbw(struct macb *bp)
1494{
1495 if (!macb_is_gem(bp))
1496 return 0;
1497
1498 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1499 case 4:
1500 return GEM_BF(DBW, GEM_DBW128);
1501 case 2:
1502 return GEM_BF(DBW, GEM_DBW64);
1503 case 1:
1504 default:
1505 return GEM_BF(DBW, GEM_DBW32);
1506 }
1507}
1508
0116da4f 1509/*
b3e3bd71
NF		 1510 * Configure the receive DMA engine
1511 * - use the correct receive buffer size
e175587f 1512 * - set best burst length for DMA operations
b3e3bd71
NF		 1513 * (if not supported by FIFO, it will fallback to default)
1514 * - set both rx/tx packet buffers to full memory size
1515 * These are configurable parameters for GEM.
0116da4f
JI		 1516 */
1517static void macb_configure_dma(struct macb *bp)
1518{
1519 u32 dmacfg;
1520
1521 if (macb_is_gem(bp)) {
1522 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1b44791a 1523 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
e175587f
NF		 1524 if (bp->dma_burst_length)
1525 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
b3e3bd71 1526 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
a1ae385d 1527 dmacfg &= ~GEM_BIT(ENDIA);
e175587f
NF		 1528 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1529 dmacfg);
0116da4f
JI		 1530 gem_writel(bp, DMACFG, dmacfg);
1531 }
1532}
1533
89e5785f
HS		 1534static void macb_init_hw(struct macb *bp)
1535{
1536 u32 config;
1537
1538 macb_reset_hw(bp);
314bccc4 1539 macb_set_hwaddr(bp);
89e5785f 1540
70c9f3d4 1541 config = macb_mdc_clk_div(bp);
29bc2e1e 1542 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
89e5785f
HS		 1543 config |= MACB_BIT(PAE); /* PAuse Enable */
1544 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
8dd4bd00 1545 config |= MACB_BIT(BIG); /* Receive oversized frames */
89e5785f
HS		 1546 if (bp->dev->flags & IFF_PROMISC)
1547 config |= MACB_BIT(CAF); /* Copy All Frames */
1548 if (!(bp->dev->flags & IFF_BROADCAST))
1549 config |= MACB_BIT(NBC); /* No BroadCast */
757a03c6 1550 config |= macb_dbw(bp);
89e5785f 1551 macb_writel(bp, NCFGR, config);
26cdfb49
VD		 1552 bp->speed = SPEED_10;
1553 bp->duplex = DUPLEX_HALF;
89e5785f 1554
0116da4f
JI		 1555 macb_configure_dma(bp);
1556
89e5785f
HS		 1557 /* Initialize TX and RX buffers */
1558 macb_writel(bp, RBQP, bp->rx_ring_dma);
1559 macb_writel(bp, TBQP, bp->tx_ring_dma);
1560
1561 /* Enable TX and RX */
6c36a707 1562 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
89e5785f
HS		 1563
1564 /* Enable interrupts */
e86cd53a
NF		 1565 macb_writel(bp, IER, (MACB_RX_INT_FLAGS
1566 | MACB_TX_INT_FLAGS
89e5785f 1567 | MACB_BIT(HRESP)));
89e5785f 1568
89e5785f
HS		 1569}
1570
446ebd01
PV		 1571/*
1572 * The hash address register is 64 bits long and takes up two
1573 * locations in the memory map. The least significant bits are stored
1574 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1575 *
1576 * The unicast hash enable and the multicast hash enable bits in the
1577 * network configuration register enable the reception of hash matched
1578 * frames. The destination address is reduced to a 6 bit index into
1579 * the 64 bit hash register using the following hash function. The
1580 * hash function is an exclusive or of every sixth bit of the
1581 * destination address.
1582 *
1583 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1584 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1585 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1586 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1587 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1588 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1589 *
1590 * da[0] represents the least significant bit of the first byte
1591 * received, that is, the multicast/unicast indicator, and da[47]
1592 * represents the most significant bit of the last byte received. If
1593 * the hash index, hi[n], points to a bit that is set in the hash
1594 * register then the frame will be matched according to whether the
1595 * frame is multicast or unicast. A multicast match will be signalled
1596 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1597 * index points to a bit set in the hash register. A unicast match
1598 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1599 * and the hash index points to a bit set in the hash register. To
1600 * receive all multicast frames, the hash register should be set with
1601 * all ones and the multicast hash enable bit should be set in the
1602 * network configuration register.
1603 */
1604
1605static inline int hash_bit_value(int bitnr, __u8 *addr)
1606{
1607 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1608 return 1;
1609 return 0;
1610}
1611
1612/*
1613 * Return the hash index value for the specified address.
1614 */
1615static int hash_get_index(__u8 *addr)
1616{
1617 int i, j, bitval;
1618 int hash_index = 0;
1619
1620 for (j = 0; j < 6; j++) {
1621 for (i = 0, bitval = 0; i < 8; i++)
1622 bitval ^= hash_bit_value(i*6 + j, addr);
1623
1624 hash_index |= (bitval << j);
1625 }
1626
1627 return hash_index;
1628}
1629
1630/*
1631 * Add multicast addresses to the internal multicast-hash table.
1632 */
1633static void macb_sethashtable(struct net_device *dev)
1634{
22bedad3 1635 struct netdev_hw_addr *ha;
446ebd01 1636 unsigned long mc_filter[2];
f9dcbcc9 1637 unsigned int bitnr;
446ebd01
PV		 1638 struct macb *bp = netdev_priv(dev);
1639
1640 mc_filter[0] = mc_filter[1] = 0;
1641
22bedad3
JP		 1642 netdev_for_each_mc_addr(ha, dev) {
1643 bitnr = hash_get_index(ha->addr);
446ebd01
PV		 1644 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1645 }
1646
f75ba50b
JI		 1647 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1648 macb_or_gem_writel(bp, HRT, mc_filter[1]);
446ebd01
PV		 1649}
1650
1651/*
1652 * Enable/Disable promiscuous and multicast modes.
1653 */
e0da1f14 1654void macb_set_rx_mode(struct net_device *dev)
446ebd01
PV		 1655{
1656 unsigned long cfg;
1657 struct macb *bp = netdev_priv(dev);
1658
1659 cfg = macb_readl(bp, NCFGR);
1660
1661 if (dev->flags & IFF_PROMISC)
1662 /* Enable promiscuous mode */
1663 cfg |= MACB_BIT(CAF);
1664 else if (dev->flags & (~IFF_PROMISC))
1665 /* Disable promiscuous mode */
1666 cfg &= ~MACB_BIT(CAF);
1667
1668 if (dev->flags & IFF_ALLMULTI) {
1669 /* Enable all multicast mode */
f75ba50b
JI		 1670 macb_or_gem_writel(bp, HRB, -1);
1671 macb_or_gem_writel(bp, HRT, -1);
446ebd01 1672 cfg |= MACB_BIT(NCFGR_MTI);
4cd24eaf 1673 } else if (!netdev_mc_empty(dev)) {
446ebd01
PV		 1674 /* Enable specific multicasts */
1675 macb_sethashtable(dev);
1676 cfg |= MACB_BIT(NCFGR_MTI);
1677 } else if (dev->flags & (~IFF_ALLMULTI)) {
1678 /* Disable all multicast mode */
f75ba50b
JI		 1679 macb_or_gem_writel(bp, HRB, 0);
1680 macb_or_gem_writel(bp, HRT, 0);
446ebd01
PV		 1681 cfg &= ~MACB_BIT(NCFGR_MTI);
1682 }
1683
1684 macb_writel(bp, NCFGR, cfg);
1685}
e0da1f14 1686EXPORT_SYMBOL_GPL(macb_set_rx_mode);
446ebd01 1687
89e5785f
HS		 1688static int macb_open(struct net_device *dev)
1689{
1690 struct macb *bp = netdev_priv(dev);
4df95131 1691 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
89e5785f
HS		 1692 int err;
1693
c220f8cd 1694 netdev_dbg(bp->dev, "open\n");
89e5785f 1695
03fc4721
NF		 1696 /* carrier starts down */
1697 netif_carrier_off(dev);
1698
6c36a707
R		 1699 /* if the phy is not yet register, retry later*/
1700 if (!bp->phy_dev)
1701 return -EAGAIN;
1b44791a
NF		 1702
1703 /* RX buffers initialization */
4df95131 1704 macb_init_rx_buffer_size(bp, bufsz);
6c36a707 1705
89e5785f
HS		 1706 err = macb_alloc_consistent(bp);
1707 if (err) {
c220f8cd
JI		 1708 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1709 err);
89e5785f
HS		 1710 return err;
1711 }
1712
bea3348e
SH		 1713 napi_enable(&bp->napi);
1714
4df95131 1715 bp->macbgem_ops.mog_init_rings(bp);
89e5785f 1716 macb_init_hw(bp);
89e5785f 1717
6c36a707
R		 1718 /* schedule a link state check */
1719 phy_start(bp->phy_dev);
89e5785f 1720
6c36a707 1721 netif_start_queue(dev);
89e5785f
HS		 1722
1723 return 0;
1724}
1725
1726static int macb_close(struct net_device *dev)
1727{
1728 struct macb *bp = netdev_priv(dev);
1729 unsigned long flags;
1730
89e5785f 1731 netif_stop_queue(dev);
bea3348e 1732 napi_disable(&bp->napi);
89e5785f 1733
6c36a707
R		 1734 if (bp->phy_dev)
1735 phy_stop(bp->phy_dev);
1736
89e5785f
HS		 1737 spin_lock_irqsave(&bp->lock, flags);
1738 macb_reset_hw(bp);
1739 netif_carrier_off(dev);
1740 spin_unlock_irqrestore(&bp->lock, flags);
1741
1742 macb_free_consistent(bp);
1743
1744 return 0;
1745}
1746
a494ed8e
JI		 1747static void gem_update_stats(struct macb *bp)
1748{
1749 u32 __iomem *reg = bp->regs + GEM_OTX;
1750 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1751 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1752
1753 for (; p < end; p++, reg++)
1754 *p += __raw_readl(reg);
1755}
1756
1757static struct net_device_stats *gem_get_stats(struct macb *bp)
1758{
1759 struct gem_stats *hwstat = &bp->hw_stats.gem;
1760 struct net_device_stats *nstat = &bp->stats;
1761
1762 gem_update_stats(bp);
1763
1764 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1765 hwstat->rx_alignment_errors +
1766 hwstat->rx_resource_errors +
1767 hwstat->rx_overruns +
1768 hwstat->rx_oversize_frames +
1769 hwstat->rx_jabbers +
1770 hwstat->rx_undersized_frames +
1771 hwstat->rx_length_field_frame_errors);
1772 nstat->tx_errors = (hwstat->tx_late_collisions +
1773 hwstat->tx_excessive_collisions +
1774 hwstat->tx_underrun +
1775 hwstat->tx_carrier_sense_errors);
1776 nstat->multicast = hwstat->rx_multicast_frames;
1777 nstat->collisions = (hwstat->tx_single_collision_frames +
1778 hwstat->tx_multiple_collision_frames +
1779 hwstat->tx_excessive_collisions);
1780 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1781 hwstat->rx_jabbers +
1782 hwstat->rx_undersized_frames +
1783 hwstat->rx_length_field_frame_errors);
1784 nstat->rx_over_errors = hwstat->rx_resource_errors;
1785 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1786 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1787 nstat->rx_fifo_errors = hwstat->rx_overruns;
1788 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1789 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1790 nstat->tx_fifo_errors = hwstat->tx_underrun;
1791
1792 return nstat;
1793}
1794
2ea32eed 1795struct net_device_stats *macb_get_stats(struct net_device *dev)
89e5785f
HS		 1796{
1797 struct macb *bp = netdev_priv(dev);
1798 struct net_device_stats *nstat = &bp->stats;
a494ed8e
JI		 1799 struct macb_stats *hwstat = &bp->hw_stats.macb;
1800
1801 if (macb_is_gem(bp))
1802 return gem_get_stats(bp);
89e5785f 1803
6c36a707
R		 1804 /* read stats from hardware */
1805 macb_update_stats(bp);
1806
89e5785f
HS		 1807 /* Convert HW stats into netdevice stats */
1808 nstat->rx_errors = (hwstat->rx_fcs_errors +
1809 hwstat->rx_align_errors +
1810 hwstat->rx_resource_errors +
1811 hwstat->rx_overruns +
1812 hwstat->rx_oversize_pkts +
1813 hwstat->rx_jabbers +
1814 hwstat->rx_undersize_pkts +
1815 hwstat->sqe_test_errors +
1816 hwstat->rx_length_mismatch);
1817 nstat->tx_errors = (hwstat->tx_late_cols +
1818 hwstat->tx_excessive_cols +
1819 hwstat->tx_underruns +
1820 hwstat->tx_carrier_errors);
1821 nstat->collisions = (hwstat->tx_single_cols +
1822 hwstat->tx_multiple_cols +
1823 hwstat->tx_excessive_cols);
1824 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1825 hwstat->rx_jabbers +
1826 hwstat->rx_undersize_pkts +
1827 hwstat->rx_length_mismatch);
b19f7f71
AS		 1828 nstat->rx_over_errors = hwstat->rx_resource_errors +
1829 hwstat->rx_overruns;
89e5785f
HS		 1830 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1831 nstat->rx_frame_errors = hwstat->rx_align_errors;
1832 nstat->rx_fifo_errors = hwstat->rx_overruns;
1833 /* XXX: What does "missed" mean? */
1834 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1835 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1836 nstat->tx_fifo_errors = hwstat->tx_underruns;
1837 /* Don't know about heartbeat or window errors... */
1838
1839 return nstat;
1840}
2ea32eed 1841EXPORT_SYMBOL_GPL(macb_get_stats);
89e5785f
HS		 1842
1843static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1844{
1845 struct macb *bp = netdev_priv(dev);
6c36a707
R		 1846 struct phy_device *phydev = bp->phy_dev;
1847
1848 if (!phydev)
1849 return -ENODEV;
89e5785f 1850
6c36a707 1851 return phy_ethtool_gset(phydev, cmd);
89e5785f
HS		 1852}
1853
1854static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1855{
1856 struct macb *bp = netdev_priv(dev);
6c36a707 1857 struct phy_device *phydev = bp->phy_dev;
89e5785f 1858
6c36a707
R		 1859 if (!phydev)
1860 return -ENODEV;
1861
1862 return phy_ethtool_sset(phydev, cmd);
89e5785f
HS		 1863}
1864
d1d1b53d
NF		 1865static int macb_get_regs_len(struct net_device *netdev)
1866{
1867 return MACB_GREGS_NBR * sizeof(u32);
1868}
1869
1870static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1871 void *p)
1872{
1873 struct macb *bp = netdev_priv(dev);
1874 unsigned int tail, head;
1875 u32 *regs_buff = p;
1876
1877 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1878 | MACB_GREGS_VERSION;
1879
1880 tail = macb_tx_ring_wrap(bp->tx_tail);
1881 head = macb_tx_ring_wrap(bp->tx_head);
1882
1883 regs_buff[0] = macb_readl(bp, NCR);
1884 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1885 regs_buff[2] = macb_readl(bp, NSR);
1886 regs_buff[3] = macb_readl(bp, TSR);
1887 regs_buff[4] = macb_readl(bp, RBQP);
1888 regs_buff[5] = macb_readl(bp, TBQP);
1889 regs_buff[6] = macb_readl(bp, RSR);
1890 regs_buff[7] = macb_readl(bp, IMR);
1891
1892 regs_buff[8] = tail;
1893 regs_buff[9] = head;
1894 regs_buff[10] = macb_tx_dma(bp, tail);
1895 regs_buff[11] = macb_tx_dma(bp, head);
1896
1897 if (macb_is_gem(bp)) {
1898 regs_buff[12] = gem_readl(bp, USRIO);
1899 regs_buff[13] = gem_readl(bp, DMACFG);
1900 }
1901}
1902
0005f541 1903const struct ethtool_ops macb_ethtool_ops = {
89e5785f
HS		 1904 .get_settings = macb_get_settings,
1905 .set_settings = macb_set_settings,
d1d1b53d
NF		 1906 .get_regs_len = macb_get_regs_len,
1907 .get_regs = macb_get_regs,
89e5785f 1908 .get_link = ethtool_op_get_link,
17f393e8 1909 .get_ts_info = ethtool_op_get_ts_info,
89e5785f 1910};
0005f541 1911EXPORT_SYMBOL_GPL(macb_ethtool_ops);
89e5785f 1912
0005f541 1913int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
89e5785f
HS		 1914{
1915 struct macb *bp = netdev_priv(dev);
6c36a707 1916 struct phy_device *phydev = bp->phy_dev;
89e5785f
HS		 1917
1918 if (!netif_running(dev))
1919 return -EINVAL;
1920
6c36a707
R		 1921 if (!phydev)
1922 return -ENODEV;
89e5785f 1923
28b04113 1924 return phy_mii_ioctl(phydev, rq, cmd);
89e5785f 1925}
0005f541 1926EXPORT_SYMBOL_GPL(macb_ioctl);
89e5785f 1927
5f1fa992
AB		 1928static const struct net_device_ops macb_netdev_ops = {
1929 .ndo_open = macb_open,
1930 .ndo_stop = macb_close,
1931 .ndo_start_xmit = macb_start_xmit,
afc4b13d 1932 .ndo_set_rx_mode = macb_set_rx_mode,
5f1fa992
AB		 1933 .ndo_get_stats = macb_get_stats,
1934 .ndo_do_ioctl = macb_ioctl,
1935 .ndo_validate_addr = eth_validate_addr,
1936 .ndo_change_mtu = eth_change_mtu,
1937 .ndo_set_mac_address = eth_mac_addr,
6e8cf5c0
TP		 1938#ifdef CONFIG_NET_POLL_CONTROLLER
1939 .ndo_poll_controller = macb_poll_controller,
1940#endif
5f1fa992
AB		 1941};
1942
fb97a846 1943#if defined(CONFIG_OF)
e175587f 1944static struct macb_config pc302gem_config = {
a4c35ed3
CP		 1945 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
1946 .dma_burst_length = 16,
1947};
1948
1949static struct macb_config sama5d3_config = {
1950 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
e175587f
NF		 1951 .dma_burst_length = 16,
1952};
1953
fb97a846
JCPV		 1954static const struct of_device_id macb_dt_ids[] = {
1955 { .compatible = "cdns,at32ap7000-macb" },
1956 { .compatible = "cdns,at91sam9260-macb" },
1957 { .compatible = "cdns,macb" },
e175587f
NF		 1958 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
1959 { .compatible = "cdns,gem", .data = &pc302gem_config },
a4c35ed3 1960 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
fb97a846
JCPV		 1961 { /* sentinel */ }
1962};
fb97a846 1963MODULE_DEVICE_TABLE(of, macb_dt_ids);
fb97a846
JCPV		 1964#endif
1965
e175587f
NF		 1966/*
1967 * Configure peripheral capacities according to device tree
1968 * and integration options used
1969 */
1970static void macb_configure_caps(struct macb *bp)
1971{
1972 u32 dcfg;
1973 const struct of_device_id *match;
1974 const struct macb_config *config;
1975
1976 if (bp->pdev->dev.of_node) {
1977 match = of_match_node(macb_dt_ids, bp->pdev->dev.of_node);
1978 if (match && match->data) {
1979 config = (const struct macb_config *)match->data;
1980
1981 bp->caps = config->caps;
1982 /*
1983 * As we have access to the matching node, configure
1984 * DMA burst length as well
1985 */
1986 bp->dma_burst_length = config->dma_burst_length;
1987 }
1988 }
1989
1990 if (MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2)
1991 bp->caps |= MACB_CAPS_MACB_IS_GEM;
1992
1993 if (macb_is_gem(bp)) {
1994 dcfg = gem_readl(bp, DCFG1);
1995 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
1996 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
1997 dcfg = gem_readl(bp, DCFG2);
1998 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
1999 bp->caps |= MACB_CAPS_FIFO_MODE;
2000 }
2001
2002 netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps);
2003}
2004
06c3fd6a 2005static int __init macb_probe(struct platform_device *pdev)
89e5785f 2006{
84e0cdb0 2007 struct macb_platform_data *pdata;
89e5785f
HS		 2008 struct resource *regs;
2009 struct net_device *dev;
2010 struct macb *bp;
6c36a707 2011 struct phy_device *phydev;
89e5785f
HS		 2012 u32 config;
2013 int err = -ENXIO;
8ef29f8a 2014 struct pinctrl *pinctrl;
50907043 2015 const char *mac;
89e5785f
HS		 2016
2017 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2018 if (!regs) {
2019 dev_err(&pdev->dev, "no mmio resource defined\n");
2020 goto err_out;
2021 }
2022
8ef29f8a
JCPV		 2023 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
2024 if (IS_ERR(pinctrl)) {
2025 err = PTR_ERR(pinctrl);
2026 if (err == -EPROBE_DEFER)
2027 goto err_out;
2028
2029 dev_warn(&pdev->dev, "No pinctrl provided\n");
2030 }
2031
89e5785f
HS		 2032 err = -ENOMEM;
2033 dev = alloc_etherdev(sizeof(*bp));
41de8d4c 2034 if (!dev)
89e5785f 2035 goto err_out;
89e5785f 2036
89e5785f
HS		 2037 SET_NETDEV_DEV(dev, &pdev->dev);
2038
89e5785f
HS		 2039 bp = netdev_priv(dev);
2040 bp->pdev = pdev;
2041 bp->dev = dev;
2042
2043 spin_lock_init(&bp->lock);
e86cd53a 2044 INIT_WORK(&bp->tx_error_task, macb_tx_error_task);
89e5785f 2045
b48e0bab 2046 bp->pclk = devm_clk_get(&pdev->dev, "pclk");
0cc8674f 2047 if (IS_ERR(bp->pclk)) {
b48e0bab
SB		 2048 err = PTR_ERR(bp->pclk);
2049 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
0cc8674f
AV		 2050 goto err_out_free_dev;
2051 }
461845db 2052
b48e0bab 2053 bp->hclk = devm_clk_get(&pdev->dev, "hclk");
89e5785f 2054 if (IS_ERR(bp->hclk)) {
b48e0bab
SB		 2055 err = PTR_ERR(bp->hclk);
2056 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
2057 goto err_out_free_dev;
2058 }
2059
e1824dfe
SB		 2060 bp->tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2061
b48e0bab
SB		 2062 err = clk_prepare_enable(bp->pclk);
2063 if (err) {
2064 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2065 goto err_out_free_dev;
2066 }
2067
2068 err = clk_prepare_enable(bp->hclk);
2069 if (err) {
2070 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
2071 goto err_out_disable_pclk;
89e5785f 2072 }
89e5785f 2073
e1824dfe
SB		 2074 if (!IS_ERR(bp->tx_clk)) {
2075 err = clk_prepare_enable(bp->tx_clk);
2076 if (err) {
2077 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n",
2078 err);
2079 goto err_out_disable_hclk;
2080 }
2081 }
2082
60fe716f 2083 bp->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
89e5785f
HS		 2084 if (!bp->regs) {
2085 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
2086 err = -ENOMEM;
2087 goto err_out_disable_clocks;
2088 }
2089
2090 dev->irq = platform_get_irq(pdev, 0);
0a4acf08
SB		 2091 err = devm_request_irq(&pdev->dev, dev->irq, macb_interrupt, 0,
2092 dev->name, dev);
89e5785f 2093 if (err) {
c220f8cd
JI		 2094 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
2095 dev->irq, err);
60fe716f 2096 goto err_out_disable_clocks;
89e5785f
HS		 2097 }
2098
5f1fa992 2099 dev->netdev_ops = &macb_netdev_ops;
bea3348e 2100 netif_napi_add(dev, &bp->napi, macb_poll, 64);
89e5785f
HS		 2101 dev->ethtool_ops = &macb_ethtool_ops;
2102
2103 dev->base_addr = regs->start;
2104
e175587f
NF		 2105 /* setup capacities */
2106 macb_configure_caps(bp);
2107
4df95131
NF		 2108 /* setup appropriated routines according to adapter type */
2109 if (macb_is_gem(bp)) {
a4c35ed3 2110 bp->max_tx_length = GEM_MAX_TX_LEN;
4df95131
NF		 2111 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2112 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2113 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2114 bp->macbgem_ops.mog_rx = gem_rx;
2115 } else {
a4c35ed3 2116 bp->max_tx_length = MACB_MAX_TX_LEN;
4df95131
NF		 2117 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2118 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2119 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2120 bp->macbgem_ops.mog_rx = macb_rx;
2121 }
2122
a4c35ed3
CP		 2123 /* Set features */
2124 dev->hw_features = NETIF_F_SG;
2125 if (bp->caps & MACB_CAPS_SG_DISABLED)
2126 dev->hw_features &= ~NETIF_F_SG;
2127 dev->features = dev->hw_features;
2128
89e5785f 2129 /* Set MII management clock divider */
70c9f3d4 2130 config = macb_mdc_clk_div(bp);
757a03c6 2131 config |= macb_dbw(bp);
89e5785f
HS		 2132 macb_writel(bp, NCFGR, config);
2133
50907043
GR		 2134 mac = of_get_mac_address(pdev->dev.of_node);
2135 if (mac)
2136 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
2137 else
fb97a846
JCPV		 2138 macb_get_hwaddr(bp);
2139
50907043 2140 err = of_get_phy_mode(pdev->dev.of_node);
fb97a846 2141 if (err < 0) {
c607a0d9 2142 pdata = dev_get_platdata(&pdev->dev);
fb97a846
JCPV		 2143 if (pdata && pdata->is_rmii)
2144 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
2145 else
2146 bp->phy_interface = PHY_INTERFACE_MODE_MII;
2147 } else {
2148 bp->phy_interface = err;
2149 }
6c36a707 2150
140b7552
PV		 2151 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2152 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
2153 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
0cc8674f 2154#if defined(CONFIG_ARCH_AT91)
f75ba50b
JI		 2155 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
2156 MACB_BIT(CLKEN)));
0cc8674f 2157#else
f75ba50b 2158 macb_or_gem_writel(bp, USRIO, 0);
0cc8674f 2159#endif
89e5785f 2160 else
0cc8674f 2161#if defined(CONFIG_ARCH_AT91)
f75ba50b 2162 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
0cc8674f 2163#else
f75ba50b 2164 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
0cc8674f 2165#endif
89e5785f 2166
89e5785f
HS		 2167 err = register_netdev(dev);
2168 if (err) {
2169 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
0a4acf08 2170 goto err_out_disable_clocks;
89e5785f
HS		 2171 }
2172
72ca820b
NF		 2173 err = macb_mii_init(bp);
2174 if (err)
6c36a707 2175 goto err_out_unregister_netdev;
89e5785f 2176
6c36a707 2177 platform_set_drvdata(pdev, dev);
89e5785f 2178
03fc4721
NF		 2179 netif_carrier_off(dev);
2180
f75ba50b
JI		 2181 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
2182 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
2183 dev->irq, dev->dev_addr);
89e5785f 2184
6c36a707 2185 phydev = bp->phy_dev;
c220f8cd
JI		 2186 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2187 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
6c36a707 2188
89e5785f
HS		 2189 return 0;
2190
6c36a707
R		 2191err_out_unregister_netdev:
2192 unregister_netdev(dev);
89e5785f 2193err_out_disable_clocks:
e1824dfe
SB		 2194 if (!IS_ERR(bp->tx_clk))
2195 clk_disable_unprepare(bp->tx_clk);
2196err_out_disable_hclk:
ace58010 2197 clk_disable_unprepare(bp->hclk);
b48e0bab 2198err_out_disable_pclk:
ace58010 2199 clk_disable_unprepare(bp->pclk);
89e5785f
HS		 2200err_out_free_dev:
2201 free_netdev(dev);
2202err_out:
89e5785f
HS		 2203 return err;
2204}
2205
06c3fd6a 2206static int __exit macb_remove(struct platform_device *pdev)
89e5785f
HS		 2207{
2208 struct net_device *dev;
2209 struct macb *bp;
2210
2211 dev = platform_get_drvdata(pdev);
2212
2213 if (dev) {
2214 bp = netdev_priv(dev);
84b7901f
AN		 2215 if (bp->phy_dev)
2216 phy_disconnect(bp->phy_dev);
298cf9be
LB		 2217 mdiobus_unregister(bp->mii_bus);
2218 kfree(bp->mii_bus->irq);
2219 mdiobus_free(bp->mii_bus);
89e5785f 2220 unregister_netdev(dev);
e1824dfe
SB		 2221 if (!IS_ERR(bp->tx_clk))
2222 clk_disable_unprepare(bp->tx_clk);
ace58010 2223 clk_disable_unprepare(bp->hclk);
ace58010 2224 clk_disable_unprepare(bp->pclk);
89e5785f 2225 free_netdev(dev);
89e5785f
HS		 2226 }
2227
2228 return 0;
2229}
2230
c1f598fd 2231#ifdef CONFIG_PM
0dfc3e18 2232static int macb_suspend(struct device *dev)
c1f598fd 2233{
0dfc3e18 2234 struct platform_device *pdev = to_platform_device(dev);
c1f598fd
HS		 2235 struct net_device *netdev = platform_get_drvdata(pdev);
2236 struct macb *bp = netdev_priv(netdev);
2237
03fc4721 2238 netif_carrier_off(netdev);
c1f598fd
HS		 2239 netif_device_detach(netdev);
2240
e1824dfe
SB		 2241 if (!IS_ERR(bp->tx_clk))
2242 clk_disable_unprepare(bp->tx_clk);
ace58010
ST		 2243 clk_disable_unprepare(bp->hclk);
2244 clk_disable_unprepare(bp->pclk);
c1f598fd
HS		 2245
2246 return 0;
2247}
2248
0dfc3e18 2249static int macb_resume(struct device *dev)
c1f598fd 2250{
0dfc3e18 2251 struct platform_device *pdev = to_platform_device(dev);
c1f598fd
HS		 2252 struct net_device *netdev = platform_get_drvdata(pdev);
2253 struct macb *bp = netdev_priv(netdev);
2254
ace58010
ST		 2255 clk_prepare_enable(bp->pclk);
2256 clk_prepare_enable(bp->hclk);
e1824dfe
SB		 2257 if (!IS_ERR(bp->tx_clk))
2258 clk_prepare_enable(bp->tx_clk);
c1f598fd
HS		 2259
2260 netif_device_attach(netdev);
2261
2262 return 0;
2263}
c1f598fd
HS		 2264#endif
2265
0dfc3e18
SB		 2266static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
2267
89e5785f 2268static struct platform_driver macb_driver = {
06c3fd6a 2269 .remove = __exit_p(macb_remove),
89e5785f
HS		 2270 .driver = {
2271 .name = "macb",
72abb461 2272 .owner = THIS_MODULE,
fb97a846 2273 .of_match_table = of_match_ptr(macb_dt_ids),
0dfc3e18 2274 .pm = &macb_pm_ops,
89e5785f
HS		 2275 },
2276};
2277
b543a8d8 2278module_platform_driver_probe(macb_driver, macb_probe);
89e5785f
HS		 2279
2280MODULE_LICENSE("GPL");
f75ba50b 2281MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
e05503ef 2282MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
72abb461 2283MODULE_ALIAS("platform:macb");
Linux kernel - Deliverables
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