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net/mlx5_core: Set flow steering dest only for forward rules
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
86d722ad 33#include <linux/mlx5/fs.h>
b3f63c3d 34#include <net/vxlan.h>
f62b8bb8 35#include "en.h"
66e49ded 36#include "eswitch.h"
b3f63c3d 37#include "vxlan.h"
f62b8bb8
AV		 38
39struct mlx5e_rq_param {
40 u32 rqc[MLX5_ST_SZ_DW(rqc)];
41 struct mlx5_wq_param wq;
42};
43
44struct mlx5e_sq_param {
45 u32 sqc[MLX5_ST_SZ_DW(sqc)];
46 struct mlx5_wq_param wq;
58d52291 47 u16 max_inline;
f62b8bb8
AV		 48};
49
50struct mlx5e_cq_param {
51 u32 cqc[MLX5_ST_SZ_DW(cqc)];
52 struct mlx5_wq_param wq;
53 u16 eq_ix;
54};
55
56struct mlx5e_channel_param {
57 struct mlx5e_rq_param rq;
58 struct mlx5e_sq_param sq;
59 struct mlx5e_cq_param rx_cq;
60 struct mlx5e_cq_param tx_cq;
61};
62
63static void mlx5e_update_carrier(struct mlx5e_priv *priv)
64{
65 struct mlx5_core_dev *mdev = priv->mdev;
66 u8 port_state;
67
68 port_state = mlx5_query_vport_state(mdev,
e7546514 69 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8
AV		 70
71 if (port_state == VPORT_STATE_UP)
72 netif_carrier_on(priv->netdev);
73 else
74 netif_carrier_off(priv->netdev);
75}
76
77static void mlx5e_update_carrier_work(struct work_struct *work)
78{
79 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
80 update_carrier_work);
81
82 mutex_lock(&priv->state_lock);
83 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
84 mlx5e_update_carrier(priv);
85 mutex_unlock(&priv->state_lock);
86}
87
efea389d
GP		 88static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
89{
90 struct mlx5_core_dev *mdev = priv->mdev;
91 struct mlx5e_pport_stats *s = &priv->stats.pport;
92 u32 *in;
93 u32 *out;
94 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
95
96 in = mlx5_vzalloc(sz);
97 out = mlx5_vzalloc(sz);
98 if (!in || !out)
99 goto free_out;
100
101 MLX5_SET(ppcnt_reg, in, local_port, 1);
102
103 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
104 mlx5_core_access_reg(mdev, in, sz, out,
105 sz, MLX5_REG_PPCNT, 0, 0);
106 memcpy(s->IEEE_802_3_counters,
107 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
108 sizeof(s->IEEE_802_3_counters));
109
110 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
111 mlx5_core_access_reg(mdev, in, sz, out,
112 sz, MLX5_REG_PPCNT, 0, 0);
113 memcpy(s->RFC_2863_counters,
114 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
115 sizeof(s->RFC_2863_counters));
116
117 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
118 mlx5_core_access_reg(mdev, in, sz, out,
119 sz, MLX5_REG_PPCNT, 0, 0);
120 memcpy(s->RFC_2819_counters,
121 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
122 sizeof(s->RFC_2819_counters));
123
124free_out:
125 kvfree(in);
126 kvfree(out);
127}
128
f62b8bb8
AV		 129void mlx5e_update_stats(struct mlx5e_priv *priv)
130{
131 struct mlx5_core_dev *mdev = priv->mdev;
132 struct mlx5e_vport_stats *s = &priv->stats.vport;
133 struct mlx5e_rq_stats *rq_stats;
134 struct mlx5e_sq_stats *sq_stats;
135 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
136 u32 *out;
137 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
138 u64 tx_offload_none;
139 int i, j;
140
141 out = mlx5_vzalloc(outlen);
142 if (!out)
143 return;
144
145 /* Collect firts the SW counters and then HW for consistency */
faf4478b
GP		 146 s->rx_packets = 0;
147 s->rx_bytes = 0;
148 s->tx_packets = 0;
149 s->tx_bytes = 0;
f62b8bb8
AV		 150 s->tso_packets = 0;
151 s->tso_bytes = 0;
89db09eb
MF		 152 s->tso_inner_packets = 0;
153 s->tso_inner_bytes = 0;
f62b8bb8
AV		 154 s->tx_queue_stopped = 0;
155 s->tx_queue_wake = 0;
156 s->tx_queue_dropped = 0;
89db09eb 157 s->tx_csum_inner = 0;
f62b8bb8
AV		 158 tx_offload_none = 0;
159 s->lro_packets = 0;
160 s->lro_bytes = 0;
161 s->rx_csum_none = 0;
bbceefce 162 s->rx_csum_sw = 0;
f62b8bb8
AV		 163 s->rx_wqe_err = 0;
164 for (i = 0; i < priv->params.num_channels; i++) {
165 rq_stats = &priv->channel[i]->rq.stats;
166
faf4478b
GP		 167 s->rx_packets += rq_stats->packets;
168 s->rx_bytes += rq_stats->bytes;
f62b8bb8
AV		 169 s->lro_packets += rq_stats->lro_packets;
170 s->lro_bytes += rq_stats->lro_bytes;
171 s->rx_csum_none += rq_stats->csum_none;
bbceefce 172 s->rx_csum_sw += rq_stats->csum_sw;
f62b8bb8
AV		 173 s->rx_wqe_err += rq_stats->wqe_err;
174
a4418a6c 175 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 176 sq_stats = &priv->channel[i]->sq[j].stats;
177
faf4478b
GP		 178 s->tx_packets += sq_stats->packets;
179 s->tx_bytes += sq_stats->bytes;
f62b8bb8
AV		 180 s->tso_packets += sq_stats->tso_packets;
181 s->tso_bytes += sq_stats->tso_bytes;
89db09eb
MF		 182 s->tso_inner_packets += sq_stats->tso_inner_packets;
183 s->tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 184 s->tx_queue_stopped += sq_stats->stopped;
185 s->tx_queue_wake += sq_stats->wake;
186 s->tx_queue_dropped += sq_stats->dropped;
89db09eb 187 s->tx_csum_inner += sq_stats->csum_offload_inner;
f62b8bb8
AV		 188 tx_offload_none += sq_stats->csum_offload_none;
189 }
190 }
191
192 /* HW counters */
193 memset(in, 0, sizeof(in));
194
195 MLX5_SET(query_vport_counter_in, in, opcode,
196 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
197 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
198 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
199
200 memset(out, 0, outlen);
201
202 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
203 goto free_out;
204
205#define MLX5_GET_CTR(p, x) \
206 MLX5_GET64(query_vport_counter_out, p, x)
207
208 s->rx_error_packets =
209 MLX5_GET_CTR(out, received_errors.packets);
210 s->rx_error_bytes =
211 MLX5_GET_CTR(out, received_errors.octets);
212 s->tx_error_packets =
213 MLX5_GET_CTR(out, transmit_errors.packets);
214 s->tx_error_bytes =
215 MLX5_GET_CTR(out, transmit_errors.octets);
216
217 s->rx_unicast_packets =
218 MLX5_GET_CTR(out, received_eth_unicast.packets);
219 s->rx_unicast_bytes =
220 MLX5_GET_CTR(out, received_eth_unicast.octets);
221 s->tx_unicast_packets =
222 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
223 s->tx_unicast_bytes =
224 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
225
226 s->rx_multicast_packets =
227 MLX5_GET_CTR(out, received_eth_multicast.packets);
228 s->rx_multicast_bytes =
229 MLX5_GET_CTR(out, received_eth_multicast.octets);
230 s->tx_multicast_packets =
231 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
232 s->tx_multicast_bytes =
233 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
234
235 s->rx_broadcast_packets =
236 MLX5_GET_CTR(out, received_eth_broadcast.packets);
237 s->rx_broadcast_bytes =
238 MLX5_GET_CTR(out, received_eth_broadcast.octets);
239 s->tx_broadcast_packets =
240 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
241 s->tx_broadcast_bytes =
242 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
243
f62b8bb8 244 /* Update calculated offload counters */
89db09eb 245 s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
bbceefce
AS		 246 s->rx_csum_good = s->rx_packets - s->rx_csum_none -
247 s->rx_csum_sw;
f62b8bb8 248
efea389d 249 mlx5e_update_pport_counters(priv);
f62b8bb8
AV		 250free_out:
251 kvfree(out);
252}
253
254static void mlx5e_update_stats_work(struct work_struct *work)
255{
256 struct delayed_work *dwork = to_delayed_work(work);
257 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
258 update_stats_work);
259 mutex_lock(&priv->state_lock);
260 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
261 mlx5e_update_stats(priv);
262 schedule_delayed_work(dwork,
263 msecs_to_jiffies(
264 MLX5E_UPDATE_STATS_INTERVAL));
265 }
266 mutex_unlock(&priv->state_lock);
267}
268
daa21560
TT		 269static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
270 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 271{
daa21560
TT		 272 struct mlx5e_priv *priv = vpriv;
273
274 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
275 return;
276
f62b8bb8
AV		 277 switch (event) {
278 case MLX5_DEV_EVENT_PORT_UP:
279 case MLX5_DEV_EVENT_PORT_DOWN:
280 schedule_work(&priv->update_carrier_work);
281 break;
282
283 default:
284 break;
285 }
286}
287
f62b8bb8
AV		 288static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
289{
290 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
291}
292
293static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
294{
f62b8bb8 295 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
daa21560 296 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 297}
298
facc9699
SM		 299#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
300#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
301
f62b8bb8
AV		 302static int mlx5e_create_rq(struct mlx5e_channel *c,
303 struct mlx5e_rq_param *param,
304 struct mlx5e_rq *rq)
305{
306 struct mlx5e_priv *priv = c->priv;
307 struct mlx5_core_dev *mdev = priv->mdev;
308 void *rqc = param->rqc;
309 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
310 int wq_sz;
311 int err;
312 int i;
313
311c7c71
SM		 314 param->wq.db_numa_node = cpu_to_node(c->cpu);
315
f62b8bb8
AV		 316 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
317 &rq->wq_ctrl);
318 if (err)
319 return err;
320
321 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
322
323 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
324 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
325 cpu_to_node(c->cpu));
326 if (!rq->skb) {
327 err = -ENOMEM;
328 goto err_rq_wq_destroy;
329 }
330
331 rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
facc9699 332 MLX5E_SW2HW_MTU(priv->netdev->mtu);
fc11fbf9 333 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
f62b8bb8
AV		 334
335 for (i = 0; i < wq_sz; i++) {
336 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
fc11fbf9 337 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
f62b8bb8
AV		 338
339 wqe->data.lkey = c->mkey_be;
fc11fbf9
SM		 340 wqe->data.byte_count =
341 cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
f62b8bb8
AV		 342 }
343
344 rq->pdev = c->pdev;
345 rq->netdev = c->netdev;
ef9814de 346 rq->tstamp = &priv->tstamp;
f62b8bb8
AV		 347 rq->channel = c;
348 rq->ix = c->ix;
50cfa25a 349 rq->priv = c->priv;
f62b8bb8
AV		 350
351 return 0;
352
353err_rq_wq_destroy:
354 mlx5_wq_destroy(&rq->wq_ctrl);
355
356 return err;
357}
358
359static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
360{
361 kfree(rq->skb);
362 mlx5_wq_destroy(&rq->wq_ctrl);
363}
364
365static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
366{
50cfa25a 367 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 368 struct mlx5_core_dev *mdev = priv->mdev;
369
370 void *in;
371 void *rqc;
372 void *wq;
373 int inlen;
374 int err;
375
376 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
377 sizeof(u64) * rq->wq_ctrl.buf.npages;
378 in = mlx5_vzalloc(inlen);
379 if (!in)
380 return -ENOMEM;
381
382 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
383 wq = MLX5_ADDR_OF(rqc, rqc, wq);
384
385 memcpy(rqc, param->rqc, sizeof(param->rqc));
386
97de9f31 387 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8
AV		 388 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
389 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
f62b8bb8 390 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 391 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 392 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
393
394 mlx5_fill_page_array(&rq->wq_ctrl.buf,
395 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
396
7db22ffb 397 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 398
399 kvfree(in);
400
401 return err;
402}
403
404static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
405{
406 struct mlx5e_channel *c = rq->channel;
407 struct mlx5e_priv *priv = c->priv;
408 struct mlx5_core_dev *mdev = priv->mdev;
409
410 void *in;
411 void *rqc;
412 int inlen;
413 int err;
414
415 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
416 in = mlx5_vzalloc(inlen);
417 if (!in)
418 return -ENOMEM;
419
420 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
421
422 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
423 MLX5_SET(rqc, rqc, state, next_state);
424
7db22ffb 425 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 426
427 kvfree(in);
428
429 return err;
430}
431
432static void mlx5e_disable_rq(struct mlx5e_rq *rq)
433{
50cfa25a 434 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 435}
436
437static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
438{
01c196a2 439 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 440 struct mlx5e_channel *c = rq->channel;
441 struct mlx5e_priv *priv = c->priv;
442 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 443
01c196a2 444 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 445 if (wq->cur_sz >= priv->params.min_rx_wqes)
446 return 0;
447
448 msleep(20);
449 }
450
451 return -ETIMEDOUT;
452}
453
454static int mlx5e_open_rq(struct mlx5e_channel *c,
455 struct mlx5e_rq_param *param,
456 struct mlx5e_rq *rq)
457{
458 int err;
459
460 err = mlx5e_create_rq(c, param, rq);
461 if (err)
462 return err;
463
464 err = mlx5e_enable_rq(rq, param);
465 if (err)
466 goto err_destroy_rq;
467
468 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
469 if (err)
470 goto err_disable_rq;
471
472 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
12be4b21 473 mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 474
475 return 0;
476
477err_disable_rq:
478 mlx5e_disable_rq(rq);
479err_destroy_rq:
480 mlx5e_destroy_rq(rq);
481
482 return err;
483}
484
485static void mlx5e_close_rq(struct mlx5e_rq *rq)
486{
487 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
488 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
489
490 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
491 while (!mlx5_wq_ll_is_empty(&rq->wq))
492 msleep(20);
493
494 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
495 napi_synchronize(&rq->channel->napi);
496
497 mlx5e_disable_rq(rq);
498 mlx5e_destroy_rq(rq);
499}
500
501static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
502{
34802a42 503 kfree(sq->wqe_info);
f62b8bb8
AV		 504 kfree(sq->dma_fifo);
505 kfree(sq->skb);
506}
507
508static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
509{
510 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
511 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
512
513 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
514 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
515 numa);
34802a42
AS		 516 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
517 numa);
f62b8bb8 518
34802a42 519 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
f62b8bb8
AV		 520 mlx5e_free_sq_db(sq);
521 return -ENOMEM;
522 }
523
524 sq->dma_fifo_mask = df_sz - 1;
525
526 return 0;
527}
528
529static int mlx5e_create_sq(struct mlx5e_channel *c,
530 int tc,
531 struct mlx5e_sq_param *param,
532 struct mlx5e_sq *sq)
533{
534 struct mlx5e_priv *priv = c->priv;
535 struct mlx5_core_dev *mdev = priv->mdev;
536
537 void *sqc = param->sqc;
538 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
03289b88 539 int txq_ix;
f62b8bb8
AV		 540 int err;
541
0ba42241 542 err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
f62b8bb8
AV		 543 if (err)
544 return err;
545
311c7c71
SM		 546 param->wq.db_numa_node = cpu_to_node(c->cpu);
547
f62b8bb8
AV		 548 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
549 &sq->wq_ctrl);
550 if (err)
551 goto err_unmap_free_uar;
552
553 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 554 if (sq->uar.bf_map) {
555 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
556 sq->uar_map = sq->uar.bf_map;
557 } else {
558 sq->uar_map = sq->uar.map;
559 }
f62b8bb8 560 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 561 sq->max_inline = param->max_inline;
f62b8bb8 562
7ec0bb22
DC		 563 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
564 if (err)
f62b8bb8
AV		 565 goto err_sq_wq_destroy;
566
03289b88
SM		 567 txq_ix = c->ix + tc * priv->params.num_channels;
568 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
f62b8bb8 569
88a85f99 570 sq->pdev = c->pdev;
ef9814de 571 sq->tstamp = &priv->tstamp;
88a85f99
AS		 572 sq->mkey_be = c->mkey_be;
573 sq->channel = c;
574 sq->tc = tc;
575 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
576 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
03289b88 577 priv->txq_to_sq_map[txq_ix] = sq;
f62b8bb8
AV		 578
579 return 0;
580
581err_sq_wq_destroy:
582 mlx5_wq_destroy(&sq->wq_ctrl);
583
584err_unmap_free_uar:
585 mlx5_unmap_free_uar(mdev, &sq->uar);
586
587 return err;
588}
589
590static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
591{
592 struct mlx5e_channel *c = sq->channel;
593 struct mlx5e_priv *priv = c->priv;
594
595 mlx5e_free_sq_db(sq);
596 mlx5_wq_destroy(&sq->wq_ctrl);
597 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
598}
599
600static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
601{
602 struct mlx5e_channel *c = sq->channel;
603 struct mlx5e_priv *priv = c->priv;
604 struct mlx5_core_dev *mdev = priv->mdev;
605
606 void *in;
607 void *sqc;
608 void *wq;
609 int inlen;
610 int err;
611
612 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
613 sizeof(u64) * sq->wq_ctrl.buf.npages;
614 in = mlx5_vzalloc(inlen);
615 if (!in)
616 return -ENOMEM;
617
618 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
619 wq = MLX5_ADDR_OF(sqc, sqc, wq);
620
621 memcpy(sqc, param->sqc, sizeof(param->sqc));
622
f62b8bb8
AV		 623 MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
624 MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
625 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
626 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
627 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
628
629 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
630 MLX5_SET(wq, wq, uar_page, sq->uar.index);
631 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 632 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 633 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
634
635 mlx5_fill_page_array(&sq->wq_ctrl.buf,
636 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
637
7db22ffb 638 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 639
640 kvfree(in);
641
642 return err;
643}
644
645static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
646{
647 struct mlx5e_channel *c = sq->channel;
648 struct mlx5e_priv *priv = c->priv;
649 struct mlx5_core_dev *mdev = priv->mdev;
650
651 void *in;
652 void *sqc;
653 int inlen;
654 int err;
655
656 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
657 in = mlx5_vzalloc(inlen);
658 if (!in)
659 return -ENOMEM;
660
661 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
662
663 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
664 MLX5_SET(sqc, sqc, state, next_state);
665
7db22ffb 666 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 667
668 kvfree(in);
669
670 return err;
671}
672
673static void mlx5e_disable_sq(struct mlx5e_sq *sq)
674{
675 struct mlx5e_channel *c = sq->channel;
676 struct mlx5e_priv *priv = c->priv;
677 struct mlx5_core_dev *mdev = priv->mdev;
678
7db22ffb 679 mlx5_core_destroy_sq(mdev, sq->sqn);
f62b8bb8
AV		 680}
681
682static int mlx5e_open_sq(struct mlx5e_channel *c,
683 int tc,
684 struct mlx5e_sq_param *param,
685 struct mlx5e_sq *sq)
686{
687 int err;
688
689 err = mlx5e_create_sq(c, tc, param, sq);
690 if (err)
691 return err;
692
693 err = mlx5e_enable_sq(sq, param);
694 if (err)
695 goto err_destroy_sq;
696
697 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
698 if (err)
699 goto err_disable_sq;
700
701 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
702 netdev_tx_reset_queue(sq->txq);
703 netif_tx_start_queue(sq->txq);
704
705 return 0;
706
707err_disable_sq:
708 mlx5e_disable_sq(sq);
709err_destroy_sq:
710 mlx5e_destroy_sq(sq);
711
712 return err;
713}
714
715static inline void netif_tx_disable_queue(struct netdev_queue *txq)
716{
717 __netif_tx_lock_bh(txq);
718 netif_tx_stop_queue(txq);
719 __netif_tx_unlock_bh(txq);
720}
721
722static void mlx5e_close_sq(struct mlx5e_sq *sq)
723{
724 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
725 napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
726 netif_tx_disable_queue(sq->txq);
727
728 /* ensure hw is notified of all pending wqes */
729 if (mlx5e_sq_has_room_for(sq, 1))
12be4b21 730 mlx5e_send_nop(sq, true);
f62b8bb8
AV		 731
732 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
733 while (sq->cc != sq->pc) /* wait till sq is empty */
734 msleep(20);
735
736 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
737 napi_synchronize(&sq->channel->napi);
738
739 mlx5e_disable_sq(sq);
740 mlx5e_destroy_sq(sq);
741}
742
743static int mlx5e_create_cq(struct mlx5e_channel *c,
744 struct mlx5e_cq_param *param,
745 struct mlx5e_cq *cq)
746{
747 struct mlx5e_priv *priv = c->priv;
748 struct mlx5_core_dev *mdev = priv->mdev;
749 struct mlx5_core_cq *mcq = &cq->mcq;
750 int eqn_not_used;
0b6e26ce 751 unsigned int irqn;
f62b8bb8
AV		 752 int err;
753 u32 i;
754
311c7c71
SM		 755 param->wq.buf_numa_node = cpu_to_node(c->cpu);
756 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 757 param->eq_ix = c->ix;
758
759 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
760 &cq->wq_ctrl);
761 if (err)
762 return err;
763
764 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
765
766 cq->napi = &c->napi;
767
768 mcq->cqe_sz = 64;
769 mcq->set_ci_db = cq->wq_ctrl.db.db;
770 mcq->arm_db = cq->wq_ctrl.db.db + 1;
771 *mcq->set_ci_db = 0;
772 *mcq->arm_db = 0;
773 mcq->vector = param->eq_ix;
774 mcq->comp = mlx5e_completion_event;
775 mcq->event = mlx5e_cq_error_event;
776 mcq->irqn = irqn;
777 mcq->uar = &priv->cq_uar;
778
779 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
780 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
781
782 cqe->op_own = 0xf1;
783 }
784
785 cq->channel = c;
50cfa25a 786 cq->priv = priv;
f62b8bb8
AV		 787
788 return 0;
789}
790
791static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
792{
793 mlx5_wq_destroy(&cq->wq_ctrl);
794}
795
796static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
797{
50cfa25a 798 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 799 struct mlx5_core_dev *mdev = priv->mdev;
800 struct mlx5_core_cq *mcq = &cq->mcq;
801
802 void *in;
803 void *cqc;
804 int inlen;
0b6e26ce 805 unsigned int irqn_not_used;
f62b8bb8
AV		 806 int eqn;
807 int err;
808
809 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
810 sizeof(u64) * cq->wq_ctrl.buf.npages;
811 in = mlx5_vzalloc(inlen);
812 if (!in)
813 return -ENOMEM;
814
815 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
816
817 memcpy(cqc, param->cqc, sizeof(param->cqc));
818
819 mlx5_fill_page_array(&cq->wq_ctrl.buf,
820 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
821
822 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
823
824 MLX5_SET(cqc, cqc, c_eqn, eqn);
825 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
826 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 827 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 828 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
829
830 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
831
832 kvfree(in);
833
834 if (err)
835 return err;
836
837 mlx5e_cq_arm(cq);
838
839 return 0;
840}
841
842static void mlx5e_disable_cq(struct mlx5e_cq *cq)
843{
50cfa25a 844 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 845 struct mlx5_core_dev *mdev = priv->mdev;
846
847 mlx5_core_destroy_cq(mdev, &cq->mcq);
848}
849
850static int mlx5e_open_cq(struct mlx5e_channel *c,
851 struct mlx5e_cq_param *param,
852 struct mlx5e_cq *cq,
853 u16 moderation_usecs,
854 u16 moderation_frames)
855{
856 int err;
857 struct mlx5e_priv *priv = c->priv;
858 struct mlx5_core_dev *mdev = priv->mdev;
859
860 err = mlx5e_create_cq(c, param, cq);
861 if (err)
862 return err;
863
864 err = mlx5e_enable_cq(cq, param);
865 if (err)
866 goto err_destroy_cq;
867
7524a5d8
GP		 868 if (MLX5_CAP_GEN(mdev, cq_moderation))
869 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
870 moderation_usecs,
871 moderation_frames);
f62b8bb8
AV		 872 return 0;
873
874err_destroy_cq:
875 mlx5e_destroy_cq(cq);
876
877 return err;
878}
879
880static void mlx5e_close_cq(struct mlx5e_cq *cq)
881{
882 mlx5e_disable_cq(cq);
883 mlx5e_destroy_cq(cq);
884}
885
886static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
887{
888 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
889}
890
891static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
892 struct mlx5e_channel_param *cparam)
893{
894 struct mlx5e_priv *priv = c->priv;
895 int err;
896 int tc;
897
898 for (tc = 0; tc < c->num_tc; tc++) {
899 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
900 priv->params.tx_cq_moderation_usec,
901 priv->params.tx_cq_moderation_pkts);
902 if (err)
903 goto err_close_tx_cqs;
f62b8bb8
AV		 904 }
905
906 return 0;
907
908err_close_tx_cqs:
909 for (tc--; tc >= 0; tc--)
910 mlx5e_close_cq(&c->sq[tc].cq);
911
912 return err;
913}
914
915static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
916{
917 int tc;
918
919 for (tc = 0; tc < c->num_tc; tc++)
920 mlx5e_close_cq(&c->sq[tc].cq);
921}
922
923static int mlx5e_open_sqs(struct mlx5e_channel *c,
924 struct mlx5e_channel_param *cparam)
925{
926 int err;
927 int tc;
928
929 for (tc = 0; tc < c->num_tc; tc++) {
930 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
931 if (err)
932 goto err_close_sqs;
933 }
934
935 return 0;
936
937err_close_sqs:
938 for (tc--; tc >= 0; tc--)
939 mlx5e_close_sq(&c->sq[tc]);
940
941 return err;
942}
943
944static void mlx5e_close_sqs(struct mlx5e_channel *c)
945{
946 int tc;
947
948 for (tc = 0; tc < c->num_tc; tc++)
949 mlx5e_close_sq(&c->sq[tc]);
950}
951
5283af89 952static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 953{
954 int i;
955
956 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
5283af89
RS		 957 priv->channeltc_to_txq_map[ix][i] =
958 ix + i * priv->params.num_channels;
03289b88
SM		 959}
960
f62b8bb8
AV		 961static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
962 struct mlx5e_channel_param *cparam,
963 struct mlx5e_channel **cp)
964{
965 struct net_device *netdev = priv->netdev;
966 int cpu = mlx5e_get_cpu(priv, ix);
967 struct mlx5e_channel *c;
968 int err;
969
970 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
971 if (!c)
972 return -ENOMEM;
973
974 c->priv = priv;
975 c->ix = ix;
976 c->cpu = cpu;
977 c->pdev = &priv->mdev->pdev->dev;
978 c->netdev = priv->netdev;
979 c->mkey_be = cpu_to_be32(priv->mr.key);
a4418a6c 980 c->num_tc = priv->params.num_tc;
f62b8bb8 981
5283af89 982 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 983
f62b8bb8
AV		 984 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
985
986 err = mlx5e_open_tx_cqs(c, cparam);
987 if (err)
988 goto err_napi_del;
989
990 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
991 priv->params.rx_cq_moderation_usec,
992 priv->params.rx_cq_moderation_pkts);
993 if (err)
994 goto err_close_tx_cqs;
f62b8bb8
AV		 995
996 napi_enable(&c->napi);
997
998 err = mlx5e_open_sqs(c, cparam);
999 if (err)
1000 goto err_disable_napi;
1001
1002 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1003 if (err)
1004 goto err_close_sqs;
1005
1006 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1007 *cp = c;
1008
1009 return 0;
1010
1011err_close_sqs:
1012 mlx5e_close_sqs(c);
1013
1014err_disable_napi:
1015 napi_disable(&c->napi);
1016 mlx5e_close_cq(&c->rq.cq);
1017
1018err_close_tx_cqs:
1019 mlx5e_close_tx_cqs(c);
1020
1021err_napi_del:
1022 netif_napi_del(&c->napi);
7ae92ae5 1023 napi_hash_del(&c->napi);
f62b8bb8
AV		 1024 kfree(c);
1025
1026 return err;
1027}
1028
1029static void mlx5e_close_channel(struct mlx5e_channel *c)
1030{
1031 mlx5e_close_rq(&c->rq);
1032 mlx5e_close_sqs(c);
1033 napi_disable(&c->napi);
1034 mlx5e_close_cq(&c->rq.cq);
1035 mlx5e_close_tx_cqs(c);
1036 netif_napi_del(&c->napi);
7ae92ae5
ED		 1037
1038 napi_hash_del(&c->napi);
1039 synchronize_rcu();
1040
f62b8bb8
AV		 1041 kfree(c);
1042}
1043
1044static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1045 struct mlx5e_rq_param *param)
1046{
1047 void *rqc = param->rqc;
1048 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1049
1050 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1051 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1052 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1053 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1054 MLX5_SET(wq, wq, pd, priv->pdn);
1055
311c7c71 1056 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1057 param->wq.linear = 1;
1058}
1059
556dd1b9
TT		 1060static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1061{
1062 void *rqc = param->rqc;
1063 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1064
1065 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1066 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1067}
1068
f62b8bb8
AV		 1069static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1070 struct mlx5e_sq_param *param)
1071{
1072 void *sqc = param->sqc;
1073 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1074
1075 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1076 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1077 MLX5_SET(wq, wq, pd, priv->pdn);
1078
311c7c71 1079 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
58d52291 1080 param->max_inline = priv->params.tx_max_inline;
f62b8bb8
AV		 1081}
1082
1083static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1084 struct mlx5e_cq_param *param)
1085{
1086 void *cqc = param->cqc;
1087
1088 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1089}
1090
1091static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1092 struct mlx5e_cq_param *param)
1093{
1094 void *cqc = param->cqc;
1095
1096 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1097
1098 mlx5e_build_common_cq_param(priv, param);
1099}
1100
1101static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1102 struct mlx5e_cq_param *param)
1103{
1104 void *cqc = param->cqc;
1105
1106 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1107
1108 mlx5e_build_common_cq_param(priv, param);
1109}
1110
1111static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1112 struct mlx5e_channel_param *cparam)
1113{
1114 memset(cparam, 0, sizeof(*cparam));
1115
1116 mlx5e_build_rq_param(priv, &cparam->rq);
1117 mlx5e_build_sq_param(priv, &cparam->sq);
1118 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1119 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1120}
1121
1122static int mlx5e_open_channels(struct mlx5e_priv *priv)
1123{
1124 struct mlx5e_channel_param cparam;
a4418a6c 1125 int nch = priv->params.num_channels;
03289b88 1126 int err = -ENOMEM;
f62b8bb8
AV		 1127 int i;
1128 int j;
1129
a4418a6c
AS		 1130 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1131 GFP_KERNEL);
03289b88 1132
a4418a6c 1133 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1134 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1135
1136 if (!priv->channel || !priv->txq_to_sq_map)
1137 goto err_free_txq_to_sq_map;
f62b8bb8
AV		 1138
1139 mlx5e_build_channel_param(priv, &cparam);
a4418a6c 1140 for (i = 0; i < nch; i++) {
f62b8bb8
AV		 1141 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1142 if (err)
1143 goto err_close_channels;
1144 }
1145
a4418a6c 1146 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1147 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1148 if (err)
1149 goto err_close_channels;
1150 }
1151
1152 return 0;
1153
1154err_close_channels:
1155 for (i--; i >= 0; i--)
1156 mlx5e_close_channel(priv->channel[i]);
1157
03289b88
SM		 1158err_free_txq_to_sq_map:
1159 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1160 kfree(priv->channel);
1161
1162 return err;
1163}
1164
1165static void mlx5e_close_channels(struct mlx5e_priv *priv)
1166{
1167 int i;
1168
1169 for (i = 0; i < priv->params.num_channels; i++)
1170 mlx5e_close_channel(priv->channel[i]);
1171
03289b88 1172 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1173 kfree(priv->channel);
1174}
1175
2be6967c
SM		 1176static int mlx5e_rx_hash_fn(int hfunc)
1177{
1178 return (hfunc == ETH_RSS_HASH_TOP) ?
1179 MLX5_RX_HASH_FN_TOEPLITZ :
1180 MLX5_RX_HASH_FN_INVERTED_XOR8;
1181}
1182
1183static int mlx5e_bits_invert(unsigned long a, int size)
1184{
1185 int inv = 0;
1186 int i;
1187
1188 for (i = 0; i < size; i++)
1189 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1190
1191 return inv;
1192}
1193
936896e9
AS		 1194static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1195{
1196 int i;
1197
1198 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1199 int ix = i;
1200
1201 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1202 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1203
2d75b2bc 1204 ix = priv->params.indirection_rqt[ix];
936896e9
AS		 1205 MLX5_SET(rqtc, rqtc, rq_num[i],
1206 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1207 priv->channel[ix]->rq.rqn :
1208 priv->drop_rq.rqn);
1209 }
1210}
1211
4cbeaff5
AS		 1212static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1213 enum mlx5e_rqt_ix rqt_ix)
1214{
4cbeaff5
AS		 1215
1216 switch (rqt_ix) {
1217 case MLX5E_INDIRECTION_RQT:
936896e9 1218 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
4cbeaff5
AS		 1219
1220 break;
1221
1222 default: /* MLX5E_SINGLE_RQ_RQT */
1223 MLX5_SET(rqtc, rqtc, rq_num[0],
5c50368f
AS		 1224 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1225 priv->channel[0]->rq.rqn :
1226 priv->drop_rq.rqn);
4cbeaff5
AS		 1227
1228 break;
1229 }
1230}
1231
40ab6a6e 1232static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8
AV		 1233{
1234 struct mlx5_core_dev *mdev = priv->mdev;
1235 u32 *in;
f62b8bb8
AV		 1236 void *rqtc;
1237 int inlen;
4cbeaff5 1238 int sz;
f62b8bb8 1239 int err;
4cbeaff5 1240
936896e9 1241 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
f62b8bb8 1242
f62b8bb8
AV		 1243 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1244 in = mlx5_vzalloc(inlen);
1245 if (!in)
1246 return -ENOMEM;
1247
1248 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1249
1250 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1251 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1252
4cbeaff5 1253 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
2be6967c 1254
4cbeaff5 1255 err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1256
1257 kvfree(in);
1258
1259 return err;
1260}
1261
2d75b2bc 1262int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
5c50368f
AS		 1263{
1264 struct mlx5_core_dev *mdev = priv->mdev;
1265 u32 *in;
1266 void *rqtc;
1267 int inlen;
5c50368f
AS		 1268 int sz;
1269 int err;
1270
936896e9 1271 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
5c50368f
AS		 1272
1273 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1274 in = mlx5_vzalloc(inlen);
1275 if (!in)
1276 return -ENOMEM;
1277
1278 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1279
1280 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1281
1282 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1283
1284 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1285
1286 err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1287
1288 kvfree(in);
1289
1290 return err;
1291}
1292
40ab6a6e 1293static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8 1294{
4cbeaff5 1295 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1296}
1297
40ab6a6e
AS		 1298static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1299{
1300 mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1301 mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1302}
1303
5c50368f
AS		 1304static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1305{
1306 if (!priv->params.lro_en)
1307 return;
1308
1309#define ROUGH_MAX_L2_L3_HDR_SZ 256
1310
1311 MLX5_SET(tirc, tirc, lro_enable_mask,
1312 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1313 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1314 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1315 (priv->params.lro_wqe_sz -
1316 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1317 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1318 MLX5_CAP_ETH(priv->mdev,
d9a40271 1319 lro_timer_supported_periods[2]));
5c50368f
AS		 1320}
1321
bdfc028d
TT		 1322void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1323{
1324 MLX5_SET(tirc, tirc, rx_hash_fn,
1325 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1326 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1327 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1328 rx_hash_toeplitz_key);
1329 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1330 rx_hash_toeplitz_key);
1331
1332 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1333 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1334 }
1335}
1336
ab0394fe 1337static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 1338{
1339 struct mlx5_core_dev *mdev = priv->mdev;
1340
1341 void *in;
1342 void *tirc;
1343 int inlen;
1344 int err;
ab0394fe 1345 int tt;
5c50368f
AS		 1346
1347 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1348 in = mlx5_vzalloc(inlen);
1349 if (!in)
1350 return -ENOMEM;
1351
1352 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1353 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1354
1355 mlx5e_build_tir_ctx_lro(tirc, priv);
1356
ab0394fe
TT		 1357 for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1358 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1359 if (err)
1360 break;
1361 }
5c50368f
AS		 1362
1363 kvfree(in);
1364
1365 return err;
1366}
1367
66189961
TT		 1368static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1369 u32 tirn)
1370{
1371 void *in;
1372 int inlen;
1373 int err;
1374
1375 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1376 in = mlx5_vzalloc(inlen);
1377 if (!in)
1378 return -ENOMEM;
1379
1380 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1381
1382 err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1383
1384 kvfree(in);
1385
1386 return err;
1387}
1388
1389static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1390{
1391 int err;
1392 int i;
1393
1394 for (i = 0; i < MLX5E_NUM_TT; i++) {
1395 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1396 priv->tirn[i]);
1397 if (err)
1398 return err;
1399 }
1400
1401 return 0;
1402}
1403
40ab6a6e
AS		 1404static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1405{
1406 struct mlx5e_priv *priv = netdev_priv(netdev);
1407 struct mlx5_core_dev *mdev = priv->mdev;
1408 int hw_mtu;
1409 int err;
1410
1411 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1412 if (err)
1413 return err;
1414
1415 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1416
1417 if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1418 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1419 __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1420
1421 netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1422 return 0;
1423}
1424
08fb1dac
SM		 1425static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1426{
1427 struct mlx5e_priv *priv = netdev_priv(netdev);
1428 int nch = priv->params.num_channels;
1429 int ntc = priv->params.num_tc;
1430 int tc;
1431
1432 netdev_reset_tc(netdev);
1433
1434 if (ntc == 1)
1435 return;
1436
1437 netdev_set_num_tc(netdev, ntc);
1438
1439 for (tc = 0; tc < ntc; tc++)
1440 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1441}
1442
40ab6a6e
AS		 1443int mlx5e_open_locked(struct net_device *netdev)
1444{
1445 struct mlx5e_priv *priv = netdev_priv(netdev);
1446 int num_txqs;
1447 int err;
1448
1449 set_bit(MLX5E_STATE_OPENED, &priv->state);
1450
08fb1dac
SM		 1451 mlx5e_netdev_set_tcs(netdev);
1452
40ab6a6e
AS		 1453 num_txqs = priv->params.num_channels * priv->params.num_tc;
1454 netif_set_real_num_tx_queues(netdev, num_txqs);
1455 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1456
1457 err = mlx5e_set_dev_port_mtu(netdev);
1458 if (err)
343b29f3 1459 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1460
1461 err = mlx5e_open_channels(priv);
1462 if (err) {
1463 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1464 __func__, err);
343b29f3 1465 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1466 }
1467
66189961
TT		 1468 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1469 if (err) {
1470 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1471 __func__, err);
1472 goto err_close_channels;
1473 }
1474
40ab6a6e 1475 mlx5e_redirect_rqts(priv);
ce89ef36 1476 mlx5e_update_carrier(priv);
ef9814de 1477 mlx5e_timestamp_init(priv);
40ab6a6e
AS		 1478
1479 schedule_delayed_work(&priv->update_stats_work, 0);
40ab6a6e 1480
9b37b07f 1481 return 0;
343b29f3 1482
66189961
TT		 1483err_close_channels:
1484 mlx5e_close_channels(priv);
343b29f3
AS		 1485err_clear_state_opened_flag:
1486 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1487 return err;
40ab6a6e
AS		 1488}
1489
1490static int mlx5e_open(struct net_device *netdev)
1491{
1492 struct mlx5e_priv *priv = netdev_priv(netdev);
1493 int err;
1494
1495 mutex_lock(&priv->state_lock);
1496 err = mlx5e_open_locked(netdev);
1497 mutex_unlock(&priv->state_lock);
1498
1499 return err;
1500}
1501
1502int mlx5e_close_locked(struct net_device *netdev)
1503{
1504 struct mlx5e_priv *priv = netdev_priv(netdev);
1505
a1985740
AS		 1506 /* May already be CLOSED in case a previous configuration operation
1507 * (e.g RX/TX queue size change) that involves close&open failed.
1508 */
1509 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1510 return 0;
1511
40ab6a6e
AS		 1512 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1513
ef9814de 1514 mlx5e_timestamp_cleanup(priv);
40ab6a6e 1515 netif_carrier_off(priv->netdev);
ce89ef36 1516 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 1517 mlx5e_close_channels(priv);
1518
1519 return 0;
1520}
1521
1522static int mlx5e_close(struct net_device *netdev)
1523{
1524 struct mlx5e_priv *priv = netdev_priv(netdev);
1525 int err;
1526
1527 mutex_lock(&priv->state_lock);
1528 err = mlx5e_close_locked(netdev);
1529 mutex_unlock(&priv->state_lock);
1530
1531 return err;
1532}
1533
1534static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1535 struct mlx5e_rq *rq,
1536 struct mlx5e_rq_param *param)
1537{
1538 struct mlx5_core_dev *mdev = priv->mdev;
1539 void *rqc = param->rqc;
1540 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1541 int err;
1542
1543 param->wq.db_numa_node = param->wq.buf_numa_node;
1544
1545 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1546 &rq->wq_ctrl);
1547 if (err)
1548 return err;
1549
1550 rq->priv = priv;
1551
1552 return 0;
1553}
1554
1555static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1556 struct mlx5e_cq *cq,
1557 struct mlx5e_cq_param *param)
1558{
1559 struct mlx5_core_dev *mdev = priv->mdev;
1560 struct mlx5_core_cq *mcq = &cq->mcq;
1561 int eqn_not_used;
0b6e26ce 1562 unsigned int irqn;
40ab6a6e
AS		 1563 int err;
1564
1565 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1566 &cq->wq_ctrl);
1567 if (err)
1568 return err;
1569
1570 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1571
1572 mcq->cqe_sz = 64;
1573 mcq->set_ci_db = cq->wq_ctrl.db.db;
1574 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1575 *mcq->set_ci_db = 0;
1576 *mcq->arm_db = 0;
1577 mcq->vector = param->eq_ix;
1578 mcq->comp = mlx5e_completion_event;
1579 mcq->event = mlx5e_cq_error_event;
1580 mcq->irqn = irqn;
1581 mcq->uar = &priv->cq_uar;
1582
1583 cq->priv = priv;
1584
1585 return 0;
1586}
1587
1588static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1589{
1590 struct mlx5e_cq_param cq_param;
1591 struct mlx5e_rq_param rq_param;
1592 struct mlx5e_rq *rq = &priv->drop_rq;
1593 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1594 int err;
1595
1596 memset(&cq_param, 0, sizeof(cq_param));
1597 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 1598 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 1599
1600 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1601 if (err)
1602 return err;
1603
1604 err = mlx5e_enable_cq(cq, &cq_param);
1605 if (err)
1606 goto err_destroy_cq;
1607
1608 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1609 if (err)
1610 goto err_disable_cq;
1611
1612 err = mlx5e_enable_rq(rq, &rq_param);
1613 if (err)
1614 goto err_destroy_rq;
1615
1616 return 0;
1617
1618err_destroy_rq:
1619 mlx5e_destroy_rq(&priv->drop_rq);
1620
1621err_disable_cq:
1622 mlx5e_disable_cq(&priv->drop_rq.cq);
1623
1624err_destroy_cq:
1625 mlx5e_destroy_cq(&priv->drop_rq.cq);
1626
1627 return err;
1628}
1629
1630static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1631{
1632 mlx5e_disable_rq(&priv->drop_rq);
1633 mlx5e_destroy_rq(&priv->drop_rq);
1634 mlx5e_disable_cq(&priv->drop_rq.cq);
1635 mlx5e_destroy_cq(&priv->drop_rq.cq);
1636}
1637
1638static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1639{
1640 struct mlx5_core_dev *mdev = priv->mdev;
1641 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1642 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1643
1644 memset(in, 0, sizeof(in));
1645
08fb1dac 1646 MLX5_SET(tisc, tisc, prio, tc << 1);
40ab6a6e
AS		 1647 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1648
1649 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1650}
1651
1652static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1653{
1654 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1655}
1656
1657static int mlx5e_create_tises(struct mlx5e_priv *priv)
1658{
1659 int err;
1660 int tc;
1661
08fb1dac 1662 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
40ab6a6e
AS		 1663 err = mlx5e_create_tis(priv, tc);
1664 if (err)
1665 goto err_close_tises;
1666 }
1667
1668 return 0;
1669
1670err_close_tises:
1671 for (tc--; tc >= 0; tc--)
1672 mlx5e_destroy_tis(priv, tc);
1673
1674 return err;
1675}
1676
1677static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1678{
1679 int tc;
1680
08fb1dac 1681 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
40ab6a6e
AS		 1682 mlx5e_destroy_tis(priv, tc);
1683}
1684
f62b8bb8
AV		 1685static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1686{
1687 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1688
3191e05f
AS		 1689 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1690
5a6f8aef
AS		 1691#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1692 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 1693
5a6f8aef
AS		 1694#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1695 MLX5_HASH_FIELD_SEL_DST_IP |\
1696 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1697 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 1698
a741749f
AS		 1699#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1700 MLX5_HASH_FIELD_SEL_DST_IP |\
1701 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1702
5c50368f 1703 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 1704
4cbeaff5
AS		 1705 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1706
f62b8bb8
AV		 1707 switch (tt) {
1708 case MLX5E_TT_ANY:
4cbeaff5
AS		 1709 MLX5_SET(tirc, tirc, indirect_table,
1710 priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1711 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
f62b8bb8
AV		 1712 break;
1713 default:
f62b8bb8 1714 MLX5_SET(tirc, tirc, indirect_table,
4cbeaff5 1715 priv->rqtn[MLX5E_INDIRECTION_RQT]);
bdfc028d 1716 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 1717 break;
1718 }
1719
1720 switch (tt) {
1721 case MLX5E_TT_IPV4_TCP:
1722 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1723 MLX5_L3_PROT_TYPE_IPV4);
1724 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1725 MLX5_L4_PROT_TYPE_TCP);
1726 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1727 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1728 break;
1729
1730 case MLX5E_TT_IPV6_TCP:
1731 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1732 MLX5_L3_PROT_TYPE_IPV6);
1733 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1734 MLX5_L4_PROT_TYPE_TCP);
1735 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1736 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1737 break;
1738
1739 case MLX5E_TT_IPV4_UDP:
1740 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1741 MLX5_L3_PROT_TYPE_IPV4);
1742 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1743 MLX5_L4_PROT_TYPE_UDP);
1744 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1745 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1746 break;
1747
1748 case MLX5E_TT_IPV6_UDP:
1749 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1750 MLX5_L3_PROT_TYPE_IPV6);
1751 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1752 MLX5_L4_PROT_TYPE_UDP);
1753 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1754 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1755 break;
1756
a741749f
AS		 1757 case MLX5E_TT_IPV4_IPSEC_AH:
1758 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1759 MLX5_L3_PROT_TYPE_IPV4);
1760 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1761 MLX5_HASH_IP_IPSEC_SPI);
1762 break;
1763
1764 case MLX5E_TT_IPV6_IPSEC_AH:
1765 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1766 MLX5_L3_PROT_TYPE_IPV6);
1767 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1768 MLX5_HASH_IP_IPSEC_SPI);
1769 break;
1770
1771 case MLX5E_TT_IPV4_IPSEC_ESP:
1772 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1773 MLX5_L3_PROT_TYPE_IPV4);
1774 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1775 MLX5_HASH_IP_IPSEC_SPI);
1776 break;
1777
1778 case MLX5E_TT_IPV6_IPSEC_ESP:
1779 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1780 MLX5_L3_PROT_TYPE_IPV6);
1781 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1782 MLX5_HASH_IP_IPSEC_SPI);
1783 break;
1784
f62b8bb8
AV		 1785 case MLX5E_TT_IPV4:
1786 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1787 MLX5_L3_PROT_TYPE_IPV4);
1788 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1789 MLX5_HASH_IP);
1790 break;
1791
1792 case MLX5E_TT_IPV6:
1793 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1794 MLX5_L3_PROT_TYPE_IPV6);
1795 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1796 MLX5_HASH_IP);
1797 break;
1798 }
1799}
1800
40ab6a6e 1801static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
f62b8bb8
AV		 1802{
1803 struct mlx5_core_dev *mdev = priv->mdev;
1804 u32 *in;
1805 void *tirc;
1806 int inlen;
1807 int err;
1808
1809 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1810 in = mlx5_vzalloc(inlen);
1811 if (!in)
1812 return -ENOMEM;
1813
1814 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1815
1816 mlx5e_build_tir_ctx(priv, tirc, tt);
1817
7db22ffb 1818 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
f62b8bb8
AV		 1819
1820 kvfree(in);
1821
1822 return err;
1823}
1824
40ab6a6e 1825static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
f62b8bb8 1826{
7db22ffb 1827 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
f62b8bb8
AV		 1828}
1829
40ab6a6e 1830static int mlx5e_create_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 1831{
1832 int err;
1833 int i;
1834
1835 for (i = 0; i < MLX5E_NUM_TT; i++) {
40ab6a6e 1836 err = mlx5e_create_tir(priv, i);
f62b8bb8 1837 if (err)
40ab6a6e 1838 goto err_destroy_tirs;
f62b8bb8
AV		 1839 }
1840
1841 return 0;
1842
40ab6a6e 1843err_destroy_tirs:
f62b8bb8 1844 for (i--; i >= 0; i--)
40ab6a6e 1845 mlx5e_destroy_tir(priv, i);
f62b8bb8
AV		 1846
1847 return err;
1848}
1849
40ab6a6e 1850static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 1851{
1852 int i;
1853
1854 for (i = 0; i < MLX5E_NUM_TT; i++)
40ab6a6e 1855 mlx5e_destroy_tir(priv, i);
f62b8bb8
AV		 1856}
1857
08fb1dac
SM		 1858static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
1859{
1860 struct mlx5e_priv *priv = netdev_priv(netdev);
1861 bool was_opened;
1862 int err = 0;
1863
1864 if (tc && tc != MLX5E_MAX_NUM_TC)
1865 return -EINVAL;
1866
1867 mutex_lock(&priv->state_lock);
1868
1869 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1870 if (was_opened)
1871 mlx5e_close_locked(priv->netdev);
1872
1873 priv->params.num_tc = tc ? tc : 1;
1874
1875 if (was_opened)
1876 err = mlx5e_open_locked(priv->netdev);
1877
1878 mutex_unlock(&priv->state_lock);
1879
1880 return err;
1881}
1882
1883static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
1884 __be16 proto, struct tc_to_netdev *tc)
1885{
1886 if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO)
1887 return -EINVAL;
1888
1889 return mlx5e_setup_tc(dev, tc->tc);
1890}
1891
f62b8bb8
AV		 1892static struct rtnl_link_stats64 *
1893mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1894{
1895 struct mlx5e_priv *priv = netdev_priv(dev);
1896 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1897
1898 stats->rx_packets = vstats->rx_packets;
1899 stats->rx_bytes = vstats->rx_bytes;
1900 stats->tx_packets = vstats->tx_packets;
1901 stats->tx_bytes = vstats->tx_bytes;
1902 stats->multicast = vstats->rx_multicast_packets +
1903 vstats->tx_multicast_packets;
1904 stats->tx_errors = vstats->tx_error_packets;
1905 stats->rx_errors = vstats->rx_error_packets;
1906 stats->tx_dropped = vstats->tx_queue_dropped;
1907 stats->rx_crc_errors = 0;
1908 stats->rx_length_errors = 0;
1909
1910 return stats;
1911}
1912
1913static void mlx5e_set_rx_mode(struct net_device *dev)
1914{
1915 struct mlx5e_priv *priv = netdev_priv(dev);
1916
1917 schedule_work(&priv->set_rx_mode_work);
1918}
1919
1920static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1921{
1922 struct mlx5e_priv *priv = netdev_priv(netdev);
1923 struct sockaddr *saddr = addr;
1924
1925 if (!is_valid_ether_addr(saddr->sa_data))
1926 return -EADDRNOTAVAIL;
1927
1928 netif_addr_lock_bh(netdev);
1929 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1930 netif_addr_unlock_bh(netdev);
1931
1932 schedule_work(&priv->set_rx_mode_work);
1933
1934 return 0;
1935}
1936
1937static int mlx5e_set_features(struct net_device *netdev,
1938 netdev_features_t features)
1939{
1940 struct mlx5e_priv *priv = netdev_priv(netdev);
98e81b0a 1941 int err = 0;
f62b8bb8 1942 netdev_features_t changes = features ^ netdev->features;
f62b8bb8
AV		 1943
1944 mutex_lock(&priv->state_lock);
f62b8bb8
AV		 1945
1946 if (changes & NETIF_F_LRO) {
98e81b0a
AS		 1947 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1948
1949 if (was_opened)
1950 mlx5e_close_locked(priv->netdev);
f62b8bb8 1951
98e81b0a 1952 priv->params.lro_en = !!(features & NETIF_F_LRO);
ab0394fe
TT		 1953 err = mlx5e_modify_tirs_lro(priv);
1954 if (err)
1955 mlx5_core_warn(priv->mdev, "lro modify failed, %d\n",
1956 err);
98e81b0a
AS		 1957
1958 if (was_opened)
1959 err = mlx5e_open_locked(priv->netdev);
1960 }
f62b8bb8 1961
9b37b07f
AS		 1962 mutex_unlock(&priv->state_lock);
1963
f62b8bb8
AV		 1964 if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1965 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1966 mlx5e_enable_vlan_filter(priv);
1967 else
1968 mlx5e_disable_vlan_filter(priv);
1969 }
1970
fe9f4fe5 1971 return err;
f62b8bb8
AV		 1972}
1973
1974static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1975{
1976 struct mlx5e_priv *priv = netdev_priv(netdev);
1977 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 1978 bool was_opened;
f62b8bb8 1979 int max_mtu;
98e81b0a 1980 int err = 0;
f62b8bb8 1981
facc9699 1982 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 1983
50a9eea6
DT		 1984 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
1985
facc9699
SM		 1986 if (new_mtu > max_mtu) {
1987 netdev_err(netdev,
1988 "%s: Bad MTU (%d) > (%d) Max\n",
1989 __func__, new_mtu, max_mtu);
f62b8bb8
AV		 1990 return -EINVAL;
1991 }
1992
1993 mutex_lock(&priv->state_lock);
98e81b0a
AS		 1994
1995 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1996 if (was_opened)
1997 mlx5e_close_locked(netdev);
1998
f62b8bb8 1999 netdev->mtu = new_mtu;
98e81b0a
AS		 2000
2001 if (was_opened)
2002 err = mlx5e_open_locked(netdev);
2003
f62b8bb8
AV		 2004 mutex_unlock(&priv->state_lock);
2005
2006 return err;
2007}
2008
ef9814de
EBE		 2009static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2010{
2011 switch (cmd) {
2012 case SIOCSHWTSTAMP:
2013 return mlx5e_hwstamp_set(dev, ifr);
2014 case SIOCGHWTSTAMP:
2015 return mlx5e_hwstamp_get(dev, ifr);
2016 default:
2017 return -EOPNOTSUPP;
2018 }
2019}
2020
66e49ded
SM		 2021static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2022{
2023 struct mlx5e_priv *priv = netdev_priv(dev);
2024 struct mlx5_core_dev *mdev = priv->mdev;
2025
2026 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2027}
2028
2029static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2030{
2031 struct mlx5e_priv *priv = netdev_priv(dev);
2032 struct mlx5_core_dev *mdev = priv->mdev;
2033
2034 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2035 vlan, qos);
2036}
2037
2038static int mlx5_vport_link2ifla(u8 esw_link)
2039{
2040 switch (esw_link) {
2041 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2042 return IFLA_VF_LINK_STATE_DISABLE;
2043 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2044 return IFLA_VF_LINK_STATE_ENABLE;
2045 }
2046 return IFLA_VF_LINK_STATE_AUTO;
2047}
2048
2049static int mlx5_ifla_link2vport(u8 ifla_link)
2050{
2051 switch (ifla_link) {
2052 case IFLA_VF_LINK_STATE_DISABLE:
2053 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2054 case IFLA_VF_LINK_STATE_ENABLE:
2055 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2056 }
2057 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2058}
2059
2060static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2061 int link_state)
2062{
2063 struct mlx5e_priv *priv = netdev_priv(dev);
2064 struct mlx5_core_dev *mdev = priv->mdev;
2065
2066 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2067 mlx5_ifla_link2vport(link_state));
2068}
2069
2070static int mlx5e_get_vf_config(struct net_device *dev,
2071 int vf, struct ifla_vf_info *ivi)
2072{
2073 struct mlx5e_priv *priv = netdev_priv(dev);
2074 struct mlx5_core_dev *mdev = priv->mdev;
2075 int err;
2076
2077 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2078 if (err)
2079 return err;
2080 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2081 return 0;
2082}
2083
2084static int mlx5e_get_vf_stats(struct net_device *dev,
2085 int vf, struct ifla_vf_stats *vf_stats)
2086{
2087 struct mlx5e_priv *priv = netdev_priv(dev);
2088 struct mlx5_core_dev *mdev = priv->mdev;
2089
2090 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2091 vf_stats);
2092}
2093
b3f63c3d
MF		 2094static void mlx5e_add_vxlan_port(struct net_device *netdev,
2095 sa_family_t sa_family, __be16 port)
2096{
2097 struct mlx5e_priv *priv = netdev_priv(netdev);
2098
2099 if (!mlx5e_vxlan_allowed(priv->mdev))
2100 return;
2101
2102 mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2103}
2104
2105static void mlx5e_del_vxlan_port(struct net_device *netdev,
2106 sa_family_t sa_family, __be16 port)
2107{
2108 struct mlx5e_priv *priv = netdev_priv(netdev);
2109
2110 if (!mlx5e_vxlan_allowed(priv->mdev))
2111 return;
2112
2113 mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2114}
2115
2116static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2117 struct sk_buff *skb,
2118 netdev_features_t features)
2119{
2120 struct udphdr *udph;
2121 u16 proto;
2122 u16 port = 0;
2123
2124 switch (vlan_get_protocol(skb)) {
2125 case htons(ETH_P_IP):
2126 proto = ip_hdr(skb)->protocol;
2127 break;
2128 case htons(ETH_P_IPV6):
2129 proto = ipv6_hdr(skb)->nexthdr;
2130 break;
2131 default:
2132 goto out;
2133 }
2134
2135 if (proto == IPPROTO_UDP) {
2136 udph = udp_hdr(skb);
2137 port = be16_to_cpu(udph->dest);
2138 }
2139
2140 /* Verify if UDP port is being offloaded by HW */
2141 if (port && mlx5e_vxlan_lookup_port(priv, port))
2142 return features;
2143
2144out:
2145 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2146 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2147}
2148
2149static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2150 struct net_device *netdev,
2151 netdev_features_t features)
2152{
2153 struct mlx5e_priv *priv = netdev_priv(netdev);
2154
2155 features = vlan_features_check(skb, features);
2156 features = vxlan_features_check(skb, features);
2157
2158 /* Validate if the tunneled packet is being offloaded by HW */
2159 if (skb->encapsulation &&
2160 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2161 return mlx5e_vxlan_features_check(priv, skb, features);
2162
2163 return features;
2164}
2165
b0eed40e 2166static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 2167 .ndo_open = mlx5e_open,
2168 .ndo_stop = mlx5e_close,
2169 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2170 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2171 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 2172 .ndo_get_stats64 = mlx5e_get_stats,
2173 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2174 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 2175 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2176 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 2177 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 2178 .ndo_change_mtu = mlx5e_change_mtu,
2179 .ndo_do_ioctl = mlx5e_ioctl,
2180};
2181
2182static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2183 .ndo_open = mlx5e_open,
2184 .ndo_stop = mlx5e_close,
2185 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2186 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2187 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 2188 .ndo_get_stats64 = mlx5e_get_stats,
2189 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2190 .ndo_set_mac_address = mlx5e_set_mac,
2191 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2192 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2193 .ndo_set_features = mlx5e_set_features,
2194 .ndo_change_mtu = mlx5e_change_mtu,
2195 .ndo_do_ioctl = mlx5e_ioctl,
b3f63c3d
MF		 2196 .ndo_add_vxlan_port = mlx5e_add_vxlan_port,
2197 .ndo_del_vxlan_port = mlx5e_del_vxlan_port,
2198 .ndo_features_check = mlx5e_features_check,
b0eed40e
SM		 2199 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2200 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2201 .ndo_get_vf_config = mlx5e_get_vf_config,
2202 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2203 .ndo_get_vf_stats = mlx5e_get_vf_stats,
f62b8bb8
AV		 2204};
2205
2206static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2207{
2208 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2209 return -ENOTSUPP;
2210 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2211 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2212 !MLX5_CAP_ETH(mdev, csum_cap) ||
2213 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2214 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 2215 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2216 MLX5_CAP_FLOWTABLE(mdev,
2217 flow_table_properties_nic_receive.max_ft_level)
2218 < 3) {
f62b8bb8
AV		 2219 mlx5_core_warn(mdev,
2220 "Not creating net device, some required device capabilities are missing\n");
2221 return -ENOTSUPP;
2222 }
66189961
TT		 2223 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2224 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 2225 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2226 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 2227
f62b8bb8
AV		 2228 return 0;
2229}
2230
58d52291
AS		 2231u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2232{
2233 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2234
2235 return bf_buf_size -
2236 sizeof(struct mlx5e_tx_wqe) +
2237 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2238}
2239
08fb1dac
SM		 2240#ifdef CONFIG_MLX5_CORE_EN_DCB
2241static void mlx5e_ets_init(struct mlx5e_priv *priv)
2242{
2243 int i;
2244
2245 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2246 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2247 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2248 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2249 priv->params.ets.prio_tc[i] = i;
2250 }
2251
2252 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2253 priv->params.ets.prio_tc[0] = 1;
2254 priv->params.ets.prio_tc[1] = 0;
2255}
2256#endif
2257
85082dba
TT		 2258void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
2259 int num_channels)
2260{
2261 int i;
2262
2263 for (i = 0; i < len; i++)
2264 indirection_rqt[i] = i % num_channels;
2265}
2266
f62b8bb8
AV		 2267static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2268 struct net_device *netdev,
936896e9 2269 int num_channels)
f62b8bb8
AV		 2270{
2271 struct mlx5e_priv *priv = netdev_priv(netdev);
2272
2273 priv->params.log_sq_size =
2274 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2275 priv->params.log_rq_size =
2276 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2277 priv->params.rx_cq_moderation_usec =
2278 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2279 priv->params.rx_cq_moderation_pkts =
2280 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2281 priv->params.tx_cq_moderation_usec =
2282 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2283 priv->params.tx_cq_moderation_pkts =
2284 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 2285 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
f62b8bb8
AV		 2286 priv->params.min_rx_wqes =
2287 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
f62b8bb8 2288 priv->params.num_tc = 1;
2be6967c 2289 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 2290
57afead5
AS		 2291 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2292 sizeof(priv->params.toeplitz_hash_key));
2293
85082dba
TT		 2294 mlx5e_build_default_indir_rqt(priv->params.indirection_rqt,
2295 MLX5E_INDIR_RQT_SIZE, num_channels);
2d75b2bc 2296
f62b8bb8
AV		 2297 priv->params.lro_wqe_sz =
2298 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2299
2300 priv->mdev = mdev;
2301 priv->netdev = netdev;
936896e9 2302 priv->params.num_channels = num_channels;
08fb1dac
SM		 2303
2304#ifdef CONFIG_MLX5_CORE_EN_DCB
2305 mlx5e_ets_init(priv);
2306#endif
f62b8bb8 2307
f62b8bb8
AV		 2308 mutex_init(&priv->state_lock);
2309
2310 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2311 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2312 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2313}
2314
2315static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2316{
2317 struct mlx5e_priv *priv = netdev_priv(netdev);
2318
e1d7d349 2319 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 2320 if (is_zero_ether_addr(netdev->dev_addr) &&
2321 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2322 eth_hw_addr_random(netdev);
2323 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2324 }
f62b8bb8
AV		 2325}
2326
2327static void mlx5e_build_netdev(struct net_device *netdev)
2328{
2329 struct mlx5e_priv *priv = netdev_priv(netdev);
2330 struct mlx5_core_dev *mdev = priv->mdev;
2331
2332 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2333
08fb1dac 2334 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 2335 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac
SM		 2336#ifdef CONFIG_MLX5_CORE_EN_DCB
2337 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2338#endif
2339 } else {
b0eed40e 2340 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 2341 }
66e49ded 2342
f62b8bb8
AV		 2343 netdev->watchdog_timeo = 15 * HZ;
2344
2345 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2346
12be4b21 2347 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 2348 netdev->vlan_features |= NETIF_F_IP_CSUM;
2349 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2350 netdev->vlan_features |= NETIF_F_GRO;
2351 netdev->vlan_features |= NETIF_F_TSO;
2352 netdev->vlan_features |= NETIF_F_TSO6;
2353 netdev->vlan_features |= NETIF_F_RXCSUM;
2354 netdev->vlan_features |= NETIF_F_RXHASH;
2355
2356 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2357 netdev->vlan_features |= NETIF_F_LRO;
2358
2359 netdev->hw_features = netdev->vlan_features;
e4cf27bd 2360 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 2361 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2362 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2363
b3f63c3d
MF		 2364 if (mlx5e_vxlan_allowed(mdev)) {
2365 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2366 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2367 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2368 netdev->hw_enc_features |= NETIF_F_TSO;
2369 netdev->hw_enc_features |= NETIF_F_TSO6;
2370 netdev->hw_enc_features |= NETIF_F_RXHASH;
2371 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2372 }
2373
f62b8bb8
AV		 2374 netdev->features = netdev->hw_features;
2375 if (!priv->params.lro_en)
2376 netdev->features &= ~NETIF_F_LRO;
2377
2378 netdev->features |= NETIF_F_HIGHDMA;
2379
2380 netdev->priv_flags |= IFF_UNICAST_FLT;
2381
2382 mlx5e_set_netdev_dev_addr(netdev);
2383}
2384
2385static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2386 struct mlx5_core_mr *mr)
2387{
2388 struct mlx5_core_dev *mdev = priv->mdev;
2389 struct mlx5_create_mkey_mbox_in *in;
2390 int err;
2391
2392 in = mlx5_vzalloc(sizeof(*in));
2393 if (!in)
2394 return -ENOMEM;
2395
2396 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2397 MLX5_PERM_LOCAL_READ |
2398 MLX5_ACCESS_MODE_PA;
2399 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2400 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2401
2402 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2403 NULL);
2404
2405 kvfree(in);
2406
2407 return err;
2408}
2409
2410static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2411{
2412 struct net_device *netdev;
2413 struct mlx5e_priv *priv;
3435ab59 2414 int nch = mlx5e_get_max_num_channels(mdev);
f62b8bb8
AV		 2415 int err;
2416
2417 if (mlx5e_check_required_hca_cap(mdev))
2418 return NULL;
2419
08fb1dac
SM		 2420 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2421 nch * MLX5E_MAX_NUM_TC,
2422 nch);
f62b8bb8
AV		 2423 if (!netdev) {
2424 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2425 return NULL;
2426 }
2427
936896e9 2428 mlx5e_build_netdev_priv(mdev, netdev, nch);
f62b8bb8
AV		 2429 mlx5e_build_netdev(netdev);
2430
2431 netif_carrier_off(netdev);
2432
2433 priv = netdev_priv(netdev);
2434
0ba42241 2435 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
f62b8bb8 2436 if (err) {
1f2a3003 2437 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
f62b8bb8
AV		 2438 goto err_free_netdev;
2439 }
2440
2441 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2442 if (err) {
1f2a3003 2443 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
f62b8bb8
AV		 2444 goto err_unmap_free_uar;
2445 }
2446
8d7f9ecb 2447 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3191e05f 2448 if (err) {
1f2a3003 2449 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3191e05f
AS		 2450 goto err_dealloc_pd;
2451 }
2452
f62b8bb8
AV		 2453 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2454 if (err) {
1f2a3003 2455 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3191e05f 2456 goto err_dealloc_transport_domain;
f62b8bb8
AV		 2457 }
2458
40ab6a6e 2459 err = mlx5e_create_tises(priv);
5c50368f 2460 if (err) {
40ab6a6e 2461 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
5c50368f
AS		 2462 goto err_destroy_mkey;
2463 }
2464
2465 err = mlx5e_open_drop_rq(priv);
2466 if (err) {
2467 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
40ab6a6e 2468 goto err_destroy_tises;
5c50368f
AS		 2469 }
2470
40ab6a6e 2471 err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f 2472 if (err) {
40ab6a6e 2473 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
5c50368f
AS		 2474 goto err_close_drop_rq;
2475 }
2476
40ab6a6e 2477 err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
5c50368f 2478 if (err) {
40ab6a6e
AS		 2479 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2480 goto err_destroy_rqt_indir;
5c50368f
AS		 2481 }
2482
40ab6a6e 2483 err = mlx5e_create_tirs(priv);
5c50368f 2484 if (err) {
40ab6a6e
AS		 2485 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2486 goto err_destroy_rqt_single;
5c50368f
AS		 2487 }
2488
40ab6a6e 2489 err = mlx5e_create_flow_tables(priv);
5c50368f 2490 if (err) {
40ab6a6e
AS		 2491 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2492 goto err_destroy_tirs;
5c50368f
AS		 2493 }
2494
2495 mlx5e_init_eth_addr(priv);
2496
b3f63c3d
MF		 2497 mlx5e_vxlan_init(priv);
2498
08fb1dac
SM		 2499#ifdef CONFIG_MLX5_CORE_EN_DCB
2500 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2501#endif
2502
f62b8bb8
AV		 2503 err = register_netdev(netdev);
2504 if (err) {
1f2a3003 2505 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
40ab6a6e 2506 goto err_destroy_flow_tables;
f62b8bb8
AV		 2507 }
2508
b3f63c3d
MF		 2509 if (mlx5e_vxlan_allowed(mdev))
2510 vxlan_get_rx_port(netdev);
2511
f62b8bb8 2512 mlx5e_enable_async_events(priv);
9b37b07f 2513 schedule_work(&priv->set_rx_mode_work);
f62b8bb8
AV		 2514
2515 return priv;
2516
40ab6a6e
AS		 2517err_destroy_flow_tables:
2518 mlx5e_destroy_flow_tables(priv);
5c50368f 2519
40ab6a6e
AS		 2520err_destroy_tirs:
2521 mlx5e_destroy_tirs(priv);
5c50368f 2522
40ab6a6e
AS		 2523err_destroy_rqt_single:
2524 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
5c50368f 2525
40ab6a6e
AS		 2526err_destroy_rqt_indir:
2527 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f
AS		 2528
2529err_close_drop_rq:
2530 mlx5e_close_drop_rq(priv);
2531
40ab6a6e
AS		 2532err_destroy_tises:
2533 mlx5e_destroy_tises(priv);
5c50368f 2534
f62b8bb8
AV		 2535err_destroy_mkey:
2536 mlx5_core_destroy_mkey(mdev, &priv->mr);
2537
3191e05f 2538err_dealloc_transport_domain:
8d7f9ecb 2539 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3191e05f 2540
f62b8bb8
AV		 2541err_dealloc_pd:
2542 mlx5_core_dealloc_pd(mdev, priv->pdn);
2543
2544err_unmap_free_uar:
2545 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2546
2547err_free_netdev:
2548 free_netdev(netdev);
2549
2550 return NULL;
2551}
2552
2553static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2554{
2555 struct mlx5e_priv *priv = vpriv;
2556 struct net_device *netdev = priv->netdev;
2557
9b37b07f
AS		 2558 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2559
2560 schedule_work(&priv->set_rx_mode_work);
1cefa326
AS		 2561 mlx5e_disable_async_events(priv);
2562 flush_scheduled_work();
f62b8bb8 2563 unregister_netdev(netdev);
b3f63c3d 2564 mlx5e_vxlan_cleanup(priv);
40ab6a6e
AS		 2565 mlx5e_destroy_flow_tables(priv);
2566 mlx5e_destroy_tirs(priv);
2567 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2568 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f 2569 mlx5e_close_drop_rq(priv);
40ab6a6e 2570 mlx5e_destroy_tises(priv);
f62b8bb8 2571 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
8d7f9ecb 2572 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
f62b8bb8
AV		 2573 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2574 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
f62b8bb8
AV		 2575 free_netdev(netdev);
2576}
2577
2578static void *mlx5e_get_netdev(void *vpriv)
2579{
2580 struct mlx5e_priv *priv = vpriv;
2581
2582 return priv->netdev;
2583}
2584
2585static struct mlx5_interface mlx5e_interface = {
2586 .add = mlx5e_create_netdev,
2587 .remove = mlx5e_destroy_netdev,
2588 .event = mlx5e_async_event,
2589 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
2590 .get_dev = mlx5e_get_netdev,
2591};
2592
2593void mlx5e_init(void)
2594{
2595 mlx5_register_interface(&mlx5e_interface);
2596}
2597
2598void mlx5e_cleanup(void)
2599{
2600 mlx5_unregister_interface(&mlx5e_interface);
2601}
Linux kernel - Deliverables
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