Documentation/devicetree/bindings/net/mediatek-net.txt

   1 MediaTek Frame Engine Ethernet controller
   2 =========================================
   3
   4 The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
   5 have dual GMAC each represented by a child node..
   6
   7 * Ethernet controller node
   8
   9 Required properties:
  10 - compatible: Should be "mediatek,mt7623-eth"
  11 - reg: Address and length of the register set for the device
  12 - interrupts: Should contain the frame engines interrupt
  13 - clocks: the clock used by the core
  14 - clock-names: the names of the clock listed in the clocks property. These are
  15         "ethif", "esw", "gp2", "gp1"
  16 - power-domains: phandle to the power domain that the ethernet is part of
  17 - resets: Should contain a phandle to the ethsys reset signal
  18 - reset-names: Should contain the reset signal name "eth"
  19 - mediatek,ethsys: phandle to the syscon node that handles the port setup
  20 - mediatek,pctl: phandle to the syscon node that handles the ports slew rate
  21         and driver current
  22
  23 Optional properties:
  24 - interrupt-parent: Should be the phandle for the interrupt controller
  25   that services interrupts for this device
  26
  27
  28 * Ethernet MAC node
  29
  30 Required properties:
  31 - compatible: Should be "mediatek,eth-mac"
  32 - reg: The number of the MAC
  33 - phy-handle: see ethernet.txt file in the same directory.
  34
  35 Example:
  36
  37 eth: ethernet@1b100000 {
  38         compatible = "mediatek,mt7623-eth";
  39         reg = <0 0x1b100000 0 0x20000>;
  40         clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
  41                  <&ethsys CLK_ETHSYS_ESW>,
  42                  <&ethsys CLK_ETHSYS_GP2>,
  43                  <&ethsys CLK_ETHSYS_GP1>;
  44         clock-names = "ethif", "esw", "gp2", "gp1";
  45         interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
  46         power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
  47         resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
  48         reset-names = "eth";
  49         mediatek,ethsys = <&ethsys>;
  50         mediatek,pctl = <&syscfg_pctl_a>;
  51         #address-cells = <1>;
  52         #size-cells = <0>;
  53
  54         gmac1: mac@0 {
  55                 compatible = "mediatek,eth-mac";
  56                 reg = <0>;
  57                 phy-handle = <&phy0>;
  58         };
  59
  60         gmac2: mac@1 {
  61                 compatible = "mediatek,eth-mac";
  62                 reg = <1>;
  63                 phy-handle = <&phy1>;
  64         };
  65
  66         mdio-bus {
  67                 phy0: ethernet-phy@0 {
  68                         reg = <0>;
  69                         phy-mode = "rgmii";
  70                 };
  71
  72                 phy1: ethernet-phy@1 {
  73                         reg = <1>;
  74                         phy-mode = "rgmii";
  75                 };
  76         };
  77 };