arch/arc/Kconfig

   1 #
   2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3 #
   4 # This program is free software; you can redistribute it and/or modify
   5 # it under the terms of the GNU General Public License version 2 as
   6 # published by the Free Software Foundation.
   7 #
   8
   9 config ARC
  10         def_bool y
  11         select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
  12         select BUILDTIME_EXTABLE_SORT
  13         select COMMON_CLK
  14         select CLONE_BACKWARDS
  15         select GENERIC_ATOMIC64
  16         select GENERIC_CLOCKEVENTS
  17         select GENERIC_FIND_FIRST_BIT
  18         # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
  19         select GENERIC_IRQ_SHOW
  20         select GENERIC_PCI_IOMAP
  21         select GENERIC_PENDING_IRQ if SMP
  22         select GENERIC_SMP_IDLE_THREAD
  23         select HAVE_ARCH_KGDB
  24         select HAVE_ARCH_TRACEHOOK
  25         select HAVE_FUTEX_CMPXCHG
  26         select HAVE_IOREMAP_PROT
  27         select HAVE_KPROBES
  28         select HAVE_KRETPROBES
  29         select HAVE_MEMBLOCK
  30         select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
  31         select HAVE_OPROFILE
  32         select HAVE_PERF_EVENTS
  33         select IRQ_DOMAIN
  34         select MODULES_USE_ELF_RELA
  35         select NO_BOOTMEM
  36         select OF
  37         select OF_EARLY_FLATTREE
  38         select OF_RESERVED_MEM
  39         select PERF_USE_VMALLOC
  40         select HAVE_DEBUG_STACKOVERFLOW
  41         select HAVE_GENERIC_DMA_COHERENT
  42
  43 config MIGHT_HAVE_PCI
  44         bool
  45
  46 config TRACE_IRQFLAGS_SUPPORT
  47         def_bool y
  48
  49 config LOCKDEP_SUPPORT
  50         def_bool y
  51
  52 config SCHED_OMIT_FRAME_POINTER
  53         def_bool y
  54
  55 config GENERIC_CSUM
  56         def_bool y
  57
  58 config RWSEM_GENERIC_SPINLOCK
  59         def_bool y
  60
  61 config ARCH_FLATMEM_ENABLE
  62         def_bool y
  63
  64 config MMU
  65         def_bool y
  66
  67 config NO_IOPORT_MAP
  68         def_bool y
  69
  70 config GENERIC_CALIBRATE_DELAY
  71         def_bool y
  72
  73 config GENERIC_HWEIGHT
  74         def_bool y
  75
  76 config STACKTRACE_SUPPORT
  77         def_bool y
  78         select STACKTRACE
  79
  80 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
  81         def_bool y
  82         depends on ARC_MMU_V4
  83
  84 source "init/Kconfig"
  85 source "kernel/Kconfig.freezer"
  86
  87 menu "ARC Architecture Configuration"
  88
  89 menu "ARC Platform/SoC/Board"
  90
  91 source "arch/arc/plat-sim/Kconfig"
  92 source "arch/arc/plat-tb10x/Kconfig"
  93 source "arch/arc/plat-axs10x/Kconfig"
  94 #New platform adds here
  95
  96 endmenu
  97
  98 choice
  99         prompt "ARC Instruction Set"
 100         default ISA_ARCOMPACT
 101
 102 config ISA_ARCOMPACT
 103         bool "ARCompact ISA"
 104         help
 105           The original ARC ISA of ARC600/700 cores
 106
 107 config ISA_ARCV2
 108         bool "ARC ISA v2"
 109         help
 110           ISA for the Next Generation ARC-HS cores
 111
 112 endchoice
 113
 114 menu "ARC CPU Configuration"
 115
 116 choice
 117         prompt "ARC Core"
 118         default ARC_CPU_770 if ISA_ARCOMPACT
 119         default ARC_CPU_HS if ISA_ARCV2
 120
 121 if ISA_ARCOMPACT
 122
 123 config ARC_CPU_750D
 124         bool "ARC750D"
 125         select ARC_CANT_LLSC
 126         help
 127           Support for ARC750 core
 128
 129 config ARC_CPU_770
 130         bool "ARC770"
 131         select ARC_HAS_SWAPE
 132         help
 133           Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
 134           This core has a bunch of cool new features:
 135           -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
 136                    Shared Address Spaces (for sharing TLB entires in MMU)
 137           -Caches: New Prog Model, Region Flush
 138           -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
 139
 140 endif   #ISA_ARCOMPACT
 141
 142 config ARC_CPU_HS
 143         bool "ARC-HS"
 144         depends on ISA_ARCV2
 145         help
 146           Support for ARC HS38x Cores based on ARCv2 ISA
 147           The notable features are:
 148             - SMP configurations of upto 4 core with coherency
 149             - Optional L2 Cache and IO-Coherency
 150             - Revised Interrupt Architecture (multiple priorites, reg banks,
 151                 auto stack switch, auto regfile save/restore)
 152             - MMUv4 (PIPT dcache, Huge Pages)
 153             - Instructions for
 154                 * 64bit load/store: LDD, STD
 155                 * Hardware assisted divide/remainder: DIV, REM
 156                 * Function prologue/epilogue: ENTER_S, LEAVE_S
 157                 * IRQ enable/disable: CLRI, SETI
 158                 * pop count: FFS, FLS
 159                 * SETcc, BMSKN, XBFU...
 160
 161 endchoice
 162
 163 config CPU_BIG_ENDIAN
 164         bool "Enable Big Endian Mode"
 165         default n
 166         help
 167           Build kernel for Big Endian Mode of ARC CPU
 168
 169 config SMP
 170         bool "Symmetric Multi-Processing"
 171         default n
 172         select ARC_HAS_COH_CACHES if ISA_ARCV2
 173         select ARC_MCIP if ISA_ARCV2
 174         help
 175           This enables support for systems with more than one CPU.
 176
 177 if SMP
 178
 179 config ARC_HAS_COH_CACHES
 180         def_bool n
 181
 182 config ARC_HAS_REENTRANT_IRQ_LV2
 183         def_bool n
 184
 185 config ARC_MCIP
 186         bool "ARConnect Multicore IP (MCIP) Support "
 187         depends on ISA_ARCV2
 188         help
 189           This IP block enables SMP in ARC-HS38 cores.
 190           It provides for cross-core interrupts, multi-core debug
 191           hardware semaphores, shared memory,....
 192
 193 config NR_CPUS
 194         int "Maximum number of CPUs (2-4096)"
 195         range 2 4096
 196         default "4"
 197
 198 config ARC_SMP_HALT_ON_RESET
 199         bool "Enable Halt-on-reset boot mode"
 200         default y if ARC_UBOOT_SUPPORT
 201         help
 202           In SMP configuration cores can be configured as Halt-on-reset
 203           or they could all start at same time. For Halt-on-reset, non
 204           masters are parked until Master kicks them so they can start of
 205           at designated entry point. For other case, all jump to common
 206           entry point and spin wait for Master's signal.
 207
 208 endif   #SMP
 209
 210 menuconfig ARC_CACHE
 211         bool "Enable Cache Support"
 212         default y
 213         # if SMP, cache enabled ONLY if ARC implementation has cache coherency
 214         depends on !SMP || ARC_HAS_COH_CACHES
 215
 216 if ARC_CACHE
 217
 218 config ARC_CACHE_LINE_SHIFT
 219         int "Cache Line Length (as power of 2)"
 220         range 5 7
 221         default "6"
 222         help
 223           Starting with ARC700 4.9, Cache line length is configurable,
 224           This option specifies "N", with Line-len = 2 power N
 225           So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
 226           Linux only supports same line lengths for I and D caches.
 227
 228 config ARC_HAS_ICACHE
 229         bool "Use Instruction Cache"
 230         default y
 231
 232 config ARC_HAS_DCACHE
 233         bool "Use Data Cache"
 234         default y
 235
 236 config ARC_CACHE_PAGES
 237         bool "Per Page Cache Control"
 238         default y
 239         depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
 240         help
 241           This can be used to over-ride the global I/D Cache Enable on a
 242           per-page basis (but only for pages accessed via MMU such as
 243           Kernel Virtual address or User Virtual Address)
 244           TLB entries have a per-page Cache Enable Bit.
 245           Note that Global I/D ENABLE + Per Page DISABLE works but corollary
 246           Global DISABLE + Per Page ENABLE won't work
 247
 248 config ARC_CACHE_VIPT_ALIASING
 249         bool "Support VIPT Aliasing D$"
 250         depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
 251         default n
 252
 253 endif   #ARC_CACHE
 254
 255 config ARC_HAS_ICCM
 256         bool "Use ICCM"
 257         help
 258           Single Cycle RAMS to store Fast Path Code
 259         default n
 260
 261 config ARC_ICCM_SZ
 262         int "ICCM Size in KB"
 263         default "64"
 264         depends on ARC_HAS_ICCM
 265
 266 config ARC_HAS_DCCM
 267         bool "Use DCCM"
 268         help
 269           Single Cycle RAMS to store Fast Path Data
 270         default n
 271
 272 config ARC_DCCM_SZ
 273         int "DCCM Size in KB"
 274         default "64"
 275         depends on ARC_HAS_DCCM
 276
 277 config ARC_DCCM_BASE
 278         hex "DCCM map address"
 279         default "0xA0000000"
 280         depends on ARC_HAS_DCCM
 281
 282 choice
 283         prompt "MMU Version"
 284         default ARC_MMU_V3 if ARC_CPU_770
 285         default ARC_MMU_V2 if ARC_CPU_750D
 286         default ARC_MMU_V4 if ARC_CPU_HS
 287
 288 if ISA_ARCOMPACT
 289
 290 config ARC_MMU_V1
 291         bool "MMU v1"
 292         help
 293           Orig ARC700 MMU
 294
 295 config ARC_MMU_V2
 296         bool "MMU v2"
 297         help
 298           Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
 299           when 2 D-TLB and 1 I-TLB entries index into same 2way set.
 300
 301 config ARC_MMU_V3
 302         bool "MMU v3"
 303         depends on ARC_CPU_770
 304         help
 305           Introduced with ARC700 4.10: New Features
 306           Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
 307           Shared Address Spaces (SASID)
 308
 309 endif
 310
 311 config ARC_MMU_V4
 312         bool "MMU v4"
 313         depends on ISA_ARCV2
 314
 315 endchoice
 316
 317
 318 choice
 319         prompt "MMU Page Size"
 320         default ARC_PAGE_SIZE_8K
 321
 322 config ARC_PAGE_SIZE_8K
 323         bool "8KB"
 324         help
 325           Choose between 8k vs 16k
 326
 327 config ARC_PAGE_SIZE_16K
 328         bool "16KB"
 329         depends on ARC_MMU_V3 || ARC_MMU_V4
 330
 331 config ARC_PAGE_SIZE_4K
 332         bool "4KB"
 333         depends on ARC_MMU_V3 || ARC_MMU_V4
 334
 335 endchoice
 336
 337 choice
 338         prompt "MMU Super Page Size"
 339         depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
 340         default ARC_HUGEPAGE_2M
 341
 342 config ARC_HUGEPAGE_2M
 343         bool "2MB"
 344
 345 config ARC_HUGEPAGE_16M
 346         bool "16MB"
 347
 348 endchoice
 349
 350 if ISA_ARCOMPACT
 351
 352 config ARC_COMPACT_IRQ_LEVELS
 353         bool "ARCompact IRQ Priorities: High(2)/Low(1)"
 354         default n
 355         # Timer HAS to be high priority, for any other high priority config
 356         select ARC_IRQ3_LV2
 357         # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
 358         depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
 359
 360 if ARC_COMPACT_IRQ_LEVELS
 361
 362 config ARC_IRQ3_LV2
 363         bool
 364
 365 config ARC_IRQ5_LV2
 366         bool
 367
 368 config ARC_IRQ6_LV2
 369         bool
 370
 371 endif   #ARC_COMPACT_IRQ_LEVELS
 372
 373 config ARC_FPU_SAVE_RESTORE
 374         bool "Enable FPU state persistence across context switch"
 375         default n
 376         help
 377           Double Precision Floating Point unit had dedictaed regs which
 378           need to be saved/restored across context-switch.
 379           Note that ARC FPU is overly simplistic, unlike say x86, which has
 380           hardware pieces to allow software to conditionally save/restore,
 381           based on actual usage of FPU by a task. Thus our implemn does
 382           this for all tasks in system.
 383
 384 endif   #ISA_ARCOMPACT
 385
 386 config ARC_CANT_LLSC
 387         def_bool n
 388
 389 config ARC_HAS_LLSC
 390         bool "Insn: LLOCK/SCOND (efficient atomic ops)"
 391         default y
 392         depends on !ARC_CANT_LLSC
 393
 394 config ARC_STAR_9000923308
 395         bool "Workaround for llock/scond livelock"
 396         default n
 397         depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
 398
 399 config ARC_HAS_SWAPE
 400         bool "Insn: SWAPE (endian-swap)"
 401         default y
 402
 403 if ISA_ARCV2
 404
 405 config ARC_HAS_LL64
 406         bool "Insn: 64bit LDD/STD"
 407         help
 408           Enable gcc to generate 64-bit load/store instructions
 409           ISA mandates even/odd registers to allow encoding of two
 410           dest operands with 2 possible source operands.
 411         default y
 412
 413 config ARC_HAS_DIV_REM
 414         bool "Insn: div, divu, rem, remu"
 415         default y
 416
 417 config ARC_HAS_RTC
 418         bool "Local 64-bit r/o cycle counter"
 419         default n
 420         depends on !SMP
 421
 422 config ARC_HAS_GFRC
 423         bool "SMP synchronized 64-bit cycle counter"
 424         default y
 425         depends on SMP
 426
 427 config ARC_NUMBER_OF_INTERRUPTS
 428         int "Number of interrupts"
 429         range 8 240
 430         default 32
 431         help
 432           This defines the number of interrupts on the ARCv2HS core.
 433           It affects the size of vector table.
 434           The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
 435           in hardware, it keep things simple for Linux to assume they are always
 436           present.
 437
 438 endif   # ISA_ARCV2
 439
 440 endmenu   # "ARC CPU Configuration"
 441
 442 config LINUX_LINK_BASE
 443         hex "Linux Link Address"
 444         default "0x80000000"
 445         help
 446           ARC700 divides the 32 bit phy address space into two equal halves
 447           -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
 448           -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
 449           Typically Linux kernel is linked at the start of untransalted addr,
 450           hence the default value of 0x8zs.
 451           However some customers have peripherals mapped at this addr, so
 452           Linux needs to be scooted a bit.
 453           If you don't know what the above means, leave this setting alone.
 454           This needs to match memory start address specified in Device Tree
 455
 456 config HIGHMEM
 457         bool "High Memory Support"
 458         help
 459           With ARC 2G:2G address split, only upper 2G is directly addressable by
 460           kernel. Enable this to potentially allow access to rest of 2G and PAE
 461           in future
 462
 463 config ARC_HAS_PAE40
 464         bool "Support for the 40-bit Physical Address Extension"
 465         default n
 466         depends on ISA_ARCV2
 467         help
 468           Enable access to physical memory beyond 4G, only supported on
 469           ARC cores with 40 bit Physical Addressing support
 470
 471 config ARCH_PHYS_ADDR_T_64BIT
 472         def_bool ARC_HAS_PAE40
 473
 474 config ARCH_DMA_ADDR_T_64BIT
 475         bool
 476
 477 config ARC_PLAT_NEEDS_PHYS_TO_DMA
 478         bool
 479
 480 config ARC_CURR_IN_REG
 481         bool "Dedicate Register r25 for current_task pointer"
 482         default y
 483         help
 484           This reserved Register R25 to point to Current Task in
 485           kernel mode. This saves memory access for each such access
 486
 487
 488 config ARC_EMUL_UNALIGNED
 489         bool "Emulate unaligned memory access (userspace only)"
 490         default N
 491         select SYSCTL_ARCH_UNALIGN_NO_WARN
 492         select SYSCTL_ARCH_UNALIGN_ALLOW
 493         depends on ISA_ARCOMPACT
 494         help
 495           This enables misaligned 16 & 32 bit memory access from user space.
 496           Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
 497           potential bugs in code
 498
 499 config HZ
 500         int "Timer Frequency"
 501         default 100
 502
 503 config ARC_METAWARE_HLINK
 504         bool "Support for Metaware debugger assisted Host access"
 505         default n
 506         help
 507           This options allows a Linux userland apps to directly access
 508           host file system (open/creat/read/write etc) with help from
 509           Metaware Debugger. This can come in handy for Linux-host communication
 510           when there is no real usable peripheral such as EMAC.
 511
 512 menuconfig ARC_DBG
 513         bool "ARC debugging"
 514         default y
 515
 516 if ARC_DBG
 517
 518 config ARC_DW2_UNWIND
 519         bool "Enable DWARF specific kernel stack unwind"
 520         default y
 521         select KALLSYMS
 522         help
 523           Compiles the kernel with DWARF unwind information and can be used
 524           to get stack backtraces.
 525
 526           If you say Y here the resulting kernel image will be slightly larger
 527           but not slower, and it will give very useful debugging information.
 528           If you don't debug the kernel, you can say N, but we may not be able
 529           to solve problems without frame unwind information
 530
 531 config ARC_DBG_TLB_PARANOIA
 532         bool "Paranoia Checks in Low Level TLB Handlers"
 533         default n
 534
 535 config ARC_DBG_TLB_MISS_COUNT
 536         bool "Profile TLB Misses"
 537         default n
 538         select DEBUG_FS
 539         help
 540           Counts number of I and D TLB Misses and exports them via Debugfs
 541           The counters can be cleared via Debugfs as well
 542
 543 endif
 544
 545 config ARC_UBOOT_SUPPORT
 546         bool "Support uboot arg Handling"
 547         default n
 548         help
 549           ARC Linux by default checks for uboot provided args as pointers to
 550           external cmdline or DTB. This however breaks in absence of uboot,
 551           when booting from Metaware debugger directly, as the registers are
 552           not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
 553           registers look like uboot args to kernel which then chokes.
 554           So only enable the uboot arg checking/processing if users are sure
 555           of uboot being in play.
 556
 557 config ARC_BUILTIN_DTB_NAME
 558         string "Built in DTB"
 559         help
 560           Set the name of the DTB to embed in the vmlinux binary
 561           Leaving it blank selects the minimal "skeleton" dtb
 562
 563 source "kernel/Kconfig.preempt"
 564
 565 menu "Executable file formats"
 566 source "fs/Kconfig.binfmt"
 567 endmenu
 568
 569 endmenu  # "ARC Architecture Configuration"
 570
 571 source "mm/Kconfig"
 572
 573 config FORCE_MAX_ZONEORDER
 574         int "Maximum zone order"
 575         default "12" if ARC_HUGEPAGE_16M
 576         default "11"
 577
 578 source "net/Kconfig"
 579 source "drivers/Kconfig"
 580
 581 menu "Bus Support"
 582
 583 config PCI
 584         bool "PCI support" if MIGHT_HAVE_PCI
 585         help
 586           PCI is the name of a bus system, i.e., the way the CPU talks to
 587           the other stuff inside your box.  Find out if your board/platform
 588           has PCI.
 589
 590           Note: PCIe support for Synopsys Device will be available only
 591           when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
 592           say Y, otherwise N.
 593
 594 config PCI_SYSCALL
 595         def_bool PCI
 596
 597 source "drivers/pci/Kconfig"
 598
 599 endmenu
 600
 601 source "fs/Kconfig"
 602 source "arch/arc/Kconfig.debug"
 603 source "security/Kconfig"
 604 source "crypto/Kconfig"
 605 source "lib/Kconfig"
 606 source "kernel/power/Kconfig"