arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_DEVMEM_IS_ALLOWED
   6         select ARCH_HAS_ELF_RANDOMIZE
   7         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   8         select ARCH_HAVE_CUSTOM_GPIO_H
   9         select ARCH_HAS_GCOV_PROFILE_ALL
  10         select ARCH_MIGHT_HAVE_PC_PARPORT
  11         select ARCH_SUPPORTS_ATOMIC_RMW
  12         select ARCH_USE_BUILTIN_BSWAP
  13         select ARCH_USE_CMPXCHG_LOCKREF
  14         select ARCH_WANT_IPC_PARSE_VERSION
  15         select BUILDTIME_EXTABLE_SORT if MMU
  16         select CLONE_BACKWARDS
  17         select CPU_PM if (SUSPEND || CPU_IDLE)
  18         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  19         select EDAC_SUPPORT
  20         select EDAC_ATOMIC_SCRUB
  21         select GENERIC_ALLOCATOR
  22         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  23         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  24         select GENERIC_EARLY_IOREMAP
  25         select GENERIC_IDLE_POLL_SETUP
  26         select GENERIC_IRQ_PROBE
  27         select GENERIC_IRQ_SHOW
  28         select GENERIC_IRQ_SHOW_LEVEL
  29         select GENERIC_PCI_IOMAP
  30         select GENERIC_SCHED_CLOCK
  31         select GENERIC_SMP_IDLE_THREAD
  32         select GENERIC_STRNCPY_FROM_USER
  33         select GENERIC_STRNLEN_USER
  34         select HANDLE_DOMAIN_IRQ
  35         select HARDIRQS_SW_RESEND
  36         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  37         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  38         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  39         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  40         select HAVE_ARCH_MMAP_RND_BITS if MMU
  41         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  42         select HAVE_ARCH_TRACEHOOK
  43         select HAVE_ARM_SMCCC if CPU_V7
  44         select HAVE_BPF_JIT
  45         select HAVE_CC_STACKPROTECTOR
  46         select HAVE_CONTEXT_TRACKING
  47         select HAVE_C_RECORDMCOUNT
  48         select HAVE_DEBUG_KMEMLEAK
  49         select HAVE_DMA_API_DEBUG
  50         select HAVE_DMA_CONTIGUOUS if MMU
  51         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  52         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  53         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  54         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  55         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  56         select HAVE_GENERIC_DMA_COHERENT
  57         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  58         select HAVE_IDE if PCI || ISA || PCMCIA
  59         select HAVE_IRQ_TIME_ACCOUNTING
  60         select HAVE_KERNEL_GZIP
  61         select HAVE_KERNEL_LZ4
  62         select HAVE_KERNEL_LZMA
  63         select HAVE_KERNEL_LZO
  64         select HAVE_KERNEL_XZ
  65         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  66         select HAVE_KRETPROBES if (HAVE_KPROBES)
  67         select HAVE_MEMBLOCK
  68         select HAVE_MOD_ARCH_SPECIFIC
  69         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  70         select HAVE_OPTPROBES if !THUMB2_KERNEL
  71         select HAVE_PERF_EVENTS
  72         select HAVE_PERF_REGS
  73         select HAVE_PERF_USER_STACK_DUMP
  74         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  75         select HAVE_REGS_AND_STACK_ACCESS_API
  76         select HAVE_SYSCALL_TRACEPOINTS
  77         select HAVE_UID16
  78         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  79         select IRQ_FORCED_THREADING
  80         select MODULES_USE_ELF_REL
  81         select NO_BOOTMEM
  82         select OF_EARLY_FLATTREE if OF
  83         select OF_RESERVED_MEM if OF
  84         select OLD_SIGACTION
  85         select OLD_SIGSUSPEND3
  86         select PERF_USE_VMALLOC
  87         select RTC_LIB
  88         select SYS_SUPPORTS_APM_EMULATION
  89         # Above selects are sorted alphabetically; please add new ones
  90         # according to that.  Thanks.
  91         help
  92           The ARM series is a line of low-power-consumption RISC chip designs
  93           licensed by ARM Ltd and targeted at embedded applications and
  94           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  95           manufactured, but legacy ARM-based PC hardware remains popular in
  96           Europe.  There is an ARM Linux project with a web page at
  97           <http://www.arm.linux.org.uk/>.
  98
  99 config ARM_HAS_SG_CHAIN
 100         select ARCH_HAS_SG_CHAIN
 101         bool
 102
 103 config NEED_SG_DMA_LENGTH
 104         bool
 105
 106 config ARM_DMA_USE_IOMMU
 107         bool
 108         select ARM_HAS_SG_CHAIN
 109         select NEED_SG_DMA_LENGTH
 110
 111 if ARM_DMA_USE_IOMMU
 112
 113 config ARM_DMA_IOMMU_ALIGNMENT
 114         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 115         range 4 9
 116         default 8
 117         help
 118           DMA mapping framework by default aligns all buffers to the smallest
 119           PAGE_SIZE order which is greater than or equal to the requested buffer
 120           size. This works well for buffers up to a few hundreds kilobytes, but
 121           for larger buffers it just a waste of address space. Drivers which has
 122           relatively small addressing window (like 64Mib) might run out of
 123           virtual space with just a few allocations.
 124
 125           With this parameter you can specify the maximum PAGE_SIZE order for
 126           DMA IOMMU buffers. Larger buffers will be aligned only to this
 127           specified order. The order is expressed as a power of two multiplied
 128           by the PAGE_SIZE.
 129
 130 endif
 131
 132 config MIGHT_HAVE_PCI
 133         bool
 134
 135 config SYS_SUPPORTS_APM_EMULATION
 136         bool
 137
 138 config HAVE_TCM
 139         bool
 140         select GENERIC_ALLOCATOR
 141
 142 config HAVE_PROC_CPU
 143         bool
 144
 145 config NO_IOPORT_MAP
 146         bool
 147
 148 config EISA
 149         bool
 150         ---help---
 151           The Extended Industry Standard Architecture (EISA) bus was
 152           developed as an open alternative to the IBM MicroChannel bus.
 153
 154           The EISA bus provided some of the features of the IBM MicroChannel
 155           bus while maintaining backward compatibility with cards made for
 156           the older ISA bus.  The EISA bus saw limited use between 1988 and
 157           1995 when it was made obsolete by the PCI bus.
 158
 159           Say Y here if you are building a kernel for an EISA-based machine.
 160
 161           Otherwise, say N.
 162
 163 config SBUS
 164         bool
 165
 166 config STACKTRACE_SUPPORT
 167         bool
 168         default y
 169
 170 config LOCKDEP_SUPPORT
 171         bool
 172         default y
 173
 174 config TRACE_IRQFLAGS_SUPPORT
 175         bool
 176         default !CPU_V7M
 177
 178 config RWSEM_XCHGADD_ALGORITHM
 179         bool
 180         default y
 181
 182 config ARCH_HAS_ILOG2_U32
 183         bool
 184
 185 config ARCH_HAS_ILOG2_U64
 186         bool
 187
 188 config ARCH_HAS_BANDGAP
 189         bool
 190
 191 config FIX_EARLYCON_MEM
 192         def_bool y if MMU
 193
 194 config GENERIC_HWEIGHT
 195         bool
 196         default y
 197
 198 config GENERIC_CALIBRATE_DELAY
 199         bool
 200         default y
 201
 202 config ARCH_MAY_HAVE_PC_FDC
 203         bool
 204
 205 config ZONE_DMA
 206         bool
 207
 208 config NEED_DMA_MAP_STATE
 209        def_bool y
 210
 211 config ARCH_SUPPORTS_UPROBES
 212         def_bool y
 213
 214 config ARCH_HAS_DMA_SET_COHERENT_MASK
 215         bool
 216
 217 config GENERIC_ISA_DMA
 218         bool
 219
 220 config FIQ
 221         bool
 222
 223 config NEED_RET_TO_USER
 224         bool
 225
 226 config ARCH_MTD_XIP
 227         bool
 228
 229 config VECTORS_BASE
 230         hex
 231         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 232         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 233         default 0x00000000
 234         help
 235           The base address of exception vectors.  This must be two pages
 236           in size.
 237
 238 config ARM_PATCH_PHYS_VIRT
 239         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 240         default y
 241         depends on !XIP_KERNEL && MMU
 242         depends on !ARCH_REALVIEW || !SPARSEMEM
 243         help
 244           Patch phys-to-virt and virt-to-phys translation functions at
 245           boot and module load time according to the position of the
 246           kernel in system memory.
 247
 248           This can only be used with non-XIP MMU kernels where the base
 249           of physical memory is at a 16MB boundary.
 250
 251           Only disable this option if you know that you do not require
 252           this feature (eg, building a kernel for a single machine) and
 253           you need to shrink the kernel to the minimal size.
 254
 255 config NEED_MACH_IO_H
 256         bool
 257         help
 258           Select this when mach/io.h is required to provide special
 259           definitions for this platform.  The need for mach/io.h should
 260           be avoided when possible.
 261
 262 config NEED_MACH_MEMORY_H
 263         bool
 264         help
 265           Select this when mach/memory.h is required to provide special
 266           definitions for this platform.  The need for mach/memory.h should
 267           be avoided when possible.
 268
 269 config PHYS_OFFSET
 270         hex "Physical address of main memory" if MMU
 271         depends on !ARM_PATCH_PHYS_VIRT
 272         default DRAM_BASE if !MMU
 273         default 0x00000000 if ARCH_EBSA110 || \
 274                         ARCH_FOOTBRIDGE || \
 275                         ARCH_INTEGRATOR || \
 276                         ARCH_IOP13XX || \
 277                         ARCH_KS8695 || \
 278                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 279         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 280         default 0x20000000 if ARCH_S5PV210
 281         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 282         default 0xc0000000 if ARCH_SA1100
 283         help
 284           Please provide the physical address corresponding to the
 285           location of main memory in your system.
 286
 287 config GENERIC_BUG
 288         def_bool y
 289         depends on BUG
 290
 291 config PGTABLE_LEVELS
 292         int
 293         default 3 if ARM_LPAE
 294         default 2
 295
 296 source "init/Kconfig"
 297
 298 source "kernel/Kconfig.freezer"
 299
 300 menu "System Type"
 301
 302 config MMU
 303         bool "MMU-based Paged Memory Management Support"
 304         default y
 305         help
 306           Select if you want MMU-based virtualised addressing space
 307           support by paged memory management. If unsure, say 'Y'.
 308
 309 config ARCH_MMAP_RND_BITS_MIN
 310         default 8
 311
 312 config ARCH_MMAP_RND_BITS_MAX
 313         default 14 if PAGE_OFFSET=0x40000000
 314         default 15 if PAGE_OFFSET=0x80000000
 315         default 16
 316
 317 #
 318 # The "ARM system type" choice list is ordered alphabetically by option
 319 # text.  Please add new entries in the option alphabetic order.
 320 #
 321 choice
 322         prompt "ARM system type"
 323         default ARCH_VERSATILE if !MMU
 324         default ARCH_MULTIPLATFORM if MMU
 325
 326 config ARCH_MULTIPLATFORM
 327         bool "Allow multiple platforms to be selected"
 328         depends on MMU
 329         select ARCH_WANT_OPTIONAL_GPIOLIB
 330         select ARM_HAS_SG_CHAIN
 331         select ARM_PATCH_PHYS_VIRT
 332         select AUTO_ZRELADDR
 333         select CLKSRC_OF
 334         select COMMON_CLK
 335         select GENERIC_CLOCKEVENTS
 336         select MIGHT_HAVE_PCI
 337         select MULTI_IRQ_HANDLER
 338         select SPARSE_IRQ
 339         select USE_OF
 340
 341 config ARM_SINGLE_ARMV7M
 342         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 343         depends on !MMU
 344         select ARCH_WANT_OPTIONAL_GPIOLIB
 345         select ARM_NVIC
 346         select AUTO_ZRELADDR
 347         select CLKSRC_OF
 348         select COMMON_CLK
 349         select CPU_V7M
 350         select GENERIC_CLOCKEVENTS
 351         select NO_IOPORT_MAP
 352         select SPARSE_IRQ
 353         select USE_OF
 354
 355 config ARCH_REALVIEW
 356         bool "ARM Ltd. RealView family"
 357         select ARCH_WANT_OPTIONAL_GPIOLIB
 358         select ARM_AMBA
 359         select ARM_TIMER_SP804
 360         select COMMON_CLK
 361         select COMMON_CLK_VERSATILE
 362         select GENERIC_CLOCKEVENTS
 363         select GPIO_PL061 if GPIOLIB
 364         select ICST
 365         select NEED_MACH_MEMORY_H
 366         select PLAT_VERSATILE
 367         select PLAT_VERSATILE_SCHED_CLOCK
 368         help
 369           This enables support for ARM Ltd RealView boards.
 370
 371 config ARCH_VERSATILE
 372         bool "ARM Ltd. Versatile family"
 373         select ARCH_WANT_OPTIONAL_GPIOLIB
 374         select ARM_AMBA
 375         select ARM_TIMER_SP804
 376         select ARM_VIC
 377         select CLKDEV_LOOKUP
 378         select GENERIC_CLOCKEVENTS
 379         select HAVE_MACH_CLKDEV
 380         select ICST
 381         select PLAT_VERSATILE
 382         select PLAT_VERSATILE_CLOCK
 383         select PLAT_VERSATILE_SCHED_CLOCK
 384         select VERSATILE_FPGA_IRQ
 385         help
 386           This enables support for ARM Ltd Versatile board.
 387
 388 config ARCH_CLPS711X
 389         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 390         select ARCH_REQUIRE_GPIOLIB
 391         select AUTO_ZRELADDR
 392         select CLKSRC_MMIO
 393         select COMMON_CLK
 394         select CPU_ARM720T
 395         select GENERIC_CLOCKEVENTS
 396         select MFD_SYSCON
 397         select SOC_BUS
 398         help
 399           Support for Cirrus Logic 711x/721x/731x based boards.
 400
 401 config ARCH_GEMINI
 402         bool "Cortina Systems Gemini"
 403         select ARCH_REQUIRE_GPIOLIB
 404         select CLKSRC_MMIO
 405         select CPU_FA526
 406         select GENERIC_CLOCKEVENTS
 407         help
 408           Support for the Cortina Systems Gemini family SoCs
 409
 410 config ARCH_EBSA110
 411         bool "EBSA-110"
 412         select ARCH_USES_GETTIMEOFFSET
 413         select CPU_SA110
 414         select ISA
 415         select NEED_MACH_IO_H
 416         select NEED_MACH_MEMORY_H
 417         select NO_IOPORT_MAP
 418         help
 419           This is an evaluation board for the StrongARM processor available
 420           from Digital. It has limited hardware on-board, including an
 421           Ethernet interface, two PCMCIA sockets, two serial ports and a
 422           parallel port.
 423
 424 config ARCH_EP93XX
 425         bool "EP93xx-based"
 426         select ARCH_HAS_HOLES_MEMORYMODEL
 427         select ARCH_REQUIRE_GPIOLIB
 428         select ARM_AMBA
 429         select ARM_PATCH_PHYS_VIRT
 430         select ARM_VIC
 431         select AUTO_ZRELADDR
 432         select CLKDEV_LOOKUP
 433         select CLKSRC_MMIO
 434         select CPU_ARM920T
 435         select GENERIC_CLOCKEVENTS
 436         help
 437           This enables support for the Cirrus EP93xx series of CPUs.
 438
 439 config ARCH_FOOTBRIDGE
 440         bool "FootBridge"
 441         select CPU_SA110
 442         select FOOTBRIDGE
 443         select GENERIC_CLOCKEVENTS
 444         select HAVE_IDE
 445         select NEED_MACH_IO_H if !MMU
 446         select NEED_MACH_MEMORY_H
 447         help
 448           Support for systems based on the DC21285 companion chip
 449           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 450
 451 config ARCH_NETX
 452         bool "Hilscher NetX based"
 453         select ARM_VIC
 454         select CLKSRC_MMIO
 455         select CPU_ARM926T
 456         select GENERIC_CLOCKEVENTS
 457         help
 458           This enables support for systems based on the Hilscher NetX Soc
 459
 460 config ARCH_IOP13XX
 461         bool "IOP13xx-based"
 462         depends on MMU
 463         select CPU_XSC3
 464         select NEED_MACH_MEMORY_H
 465         select NEED_RET_TO_USER
 466         select PCI
 467         select PLAT_IOP
 468         select VMSPLIT_1G
 469         select SPARSE_IRQ
 470         help
 471           Support for Intel's IOP13XX (XScale) family of processors.
 472
 473 config ARCH_IOP32X
 474         bool "IOP32x-based"
 475         depends on MMU
 476         select ARCH_REQUIRE_GPIOLIB
 477         select CPU_XSCALE
 478         select GPIO_IOP
 479         select NEED_RET_TO_USER
 480         select PCI
 481         select PLAT_IOP
 482         help
 483           Support for Intel's 80219 and IOP32X (XScale) family of
 484           processors.
 485
 486 config ARCH_IOP33X
 487         bool "IOP33x-based"
 488         depends on MMU
 489         select ARCH_REQUIRE_GPIOLIB
 490         select CPU_XSCALE
 491         select GPIO_IOP
 492         select NEED_RET_TO_USER
 493         select PCI
 494         select PLAT_IOP
 495         help
 496           Support for Intel's IOP33X (XScale) family of processors.
 497
 498 config ARCH_IXP4XX
 499         bool "IXP4xx-based"
 500         depends on MMU
 501         select ARCH_HAS_DMA_SET_COHERENT_MASK
 502         select ARCH_REQUIRE_GPIOLIB
 503         select ARCH_SUPPORTS_BIG_ENDIAN
 504         select CLKSRC_MMIO
 505         select CPU_XSCALE
 506         select DMABOUNCE if PCI
 507         select GENERIC_CLOCKEVENTS
 508         select MIGHT_HAVE_PCI
 509         select NEED_MACH_IO_H
 510         select USB_EHCI_BIG_ENDIAN_DESC
 511         select USB_EHCI_BIG_ENDIAN_MMIO
 512         help
 513           Support for Intel's IXP4XX (XScale) family of processors.
 514
 515 config ARCH_DOVE
 516         bool "Marvell Dove"
 517         select ARCH_REQUIRE_GPIOLIB
 518         select CPU_PJ4
 519         select GENERIC_CLOCKEVENTS
 520         select MIGHT_HAVE_PCI
 521         select MVEBU_MBUS
 522         select PINCTRL
 523         select PINCTRL_DOVE
 524         select PLAT_ORION_LEGACY
 525         help
 526           Support for the Marvell Dove SoC 88AP510
 527
 528 config ARCH_MV78XX0
 529         bool "Marvell MV78xx0"
 530         select ARCH_REQUIRE_GPIOLIB
 531         select CPU_FEROCEON
 532         select GENERIC_CLOCKEVENTS
 533         select MVEBU_MBUS
 534         select PCI
 535         select PLAT_ORION_LEGACY
 536         help
 537           Support for the following Marvell MV78xx0 series SoCs:
 538           MV781x0, MV782x0.
 539
 540 config ARCH_ORION5X
 541         bool "Marvell Orion"
 542         depends on MMU
 543         select ARCH_REQUIRE_GPIOLIB
 544         select CPU_FEROCEON
 545         select GENERIC_CLOCKEVENTS
 546         select MVEBU_MBUS
 547         select PCI
 548         select PLAT_ORION_LEGACY
 549         select MULTI_IRQ_HANDLER
 550         help
 551           Support for the following Marvell Orion 5x series SoCs:
 552           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 553           Orion-2 (5281), Orion-1-90 (6183).
 554
 555 config ARCH_MMP
 556         bool "Marvell PXA168/910/MMP2"
 557         depends on MMU
 558         select ARCH_REQUIRE_GPIOLIB
 559         select CLKDEV_LOOKUP
 560         select GENERIC_ALLOCATOR
 561         select GENERIC_CLOCKEVENTS
 562         select GPIO_PXA
 563         select IRQ_DOMAIN
 564         select MULTI_IRQ_HANDLER
 565         select PINCTRL
 566         select PLAT_PXA
 567         select SPARSE_IRQ
 568         help
 569           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 570
 571 config ARCH_KS8695
 572         bool "Micrel/Kendin KS8695"
 573         select ARCH_REQUIRE_GPIOLIB
 574         select CLKSRC_MMIO
 575         select CPU_ARM922T
 576         select GENERIC_CLOCKEVENTS
 577         select NEED_MACH_MEMORY_H
 578         help
 579           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 580           System-on-Chip devices.
 581
 582 config ARCH_W90X900
 583         bool "Nuvoton W90X900 CPU"
 584         select ARCH_REQUIRE_GPIOLIB
 585         select CLKDEV_LOOKUP
 586         select CLKSRC_MMIO
 587         select CPU_ARM926T
 588         select GENERIC_CLOCKEVENTS
 589         help
 590           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 591           At present, the w90x900 has been renamed nuc900, regarding
 592           the ARM series product line, you can login the following
 593           link address to know more.
 594
 595           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 596                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 597
 598 config ARCH_LPC32XX
 599         bool "NXP LPC32XX"
 600         select ARCH_REQUIRE_GPIOLIB
 601         select ARM_AMBA
 602         select CLKDEV_LOOKUP
 603         select CLKSRC_MMIO
 604         select CPU_ARM926T
 605         select GENERIC_CLOCKEVENTS
 606         select HAVE_IDE
 607         select USE_OF
 608         help
 609           Support for the NXP LPC32XX family of processors
 610
 611 config ARCH_PXA
 612         bool "PXA2xx/PXA3xx-based"
 613         depends on MMU
 614         select ARCH_MTD_XIP
 615         select ARCH_REQUIRE_GPIOLIB
 616         select ARM_CPU_SUSPEND if PM
 617         select AUTO_ZRELADDR
 618         select COMMON_CLK
 619         select CLKDEV_LOOKUP
 620         select CLKSRC_PXA
 621         select CLKSRC_MMIO
 622         select CLKSRC_OF
 623         select GENERIC_CLOCKEVENTS
 624         select GPIO_PXA
 625         select HAVE_IDE
 626         select IRQ_DOMAIN
 627         select MULTI_IRQ_HANDLER
 628         select PLAT_PXA
 629         select SPARSE_IRQ
 630         help
 631           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 632
 633 config ARCH_RPC
 634         bool "RiscPC"
 635         depends on MMU
 636         select ARCH_ACORN
 637         select ARCH_MAY_HAVE_PC_FDC
 638         select ARCH_SPARSEMEM_ENABLE
 639         select ARCH_USES_GETTIMEOFFSET
 640         select CPU_SA110
 641         select FIQ
 642         select HAVE_IDE
 643         select HAVE_PATA_PLATFORM
 644         select ISA_DMA_API
 645         select NEED_MACH_IO_H
 646         select NEED_MACH_MEMORY_H
 647         select NO_IOPORT_MAP
 648         select VIRT_TO_BUS
 649         help
 650           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 651           CD-ROM interface, serial and parallel port, and the floppy drive.
 652
 653 config ARCH_SA1100
 654         bool "SA1100-based"
 655         select ARCH_MTD_XIP
 656         select ARCH_REQUIRE_GPIOLIB
 657         select ARCH_SPARSEMEM_ENABLE
 658         select CLKDEV_LOOKUP
 659         select CLKSRC_MMIO
 660         select CLKSRC_PXA
 661         select CLKSRC_OF if OF
 662         select CPU_FREQ
 663         select CPU_SA1100
 664         select GENERIC_CLOCKEVENTS
 665         select HAVE_IDE
 666         select IRQ_DOMAIN
 667         select ISA
 668         select MULTI_IRQ_HANDLER
 669         select NEED_MACH_MEMORY_H
 670         select SPARSE_IRQ
 671         help
 672           Support for StrongARM 11x0 based boards.
 673
 674 config ARCH_S3C24XX
 675         bool "Samsung S3C24XX SoCs"
 676         select ARCH_REQUIRE_GPIOLIB
 677         select ATAGS
 678         select CLKDEV_LOOKUP
 679         select CLKSRC_SAMSUNG_PWM
 680         select GENERIC_CLOCKEVENTS
 681         select GPIO_SAMSUNG
 682         select HAVE_S3C2410_I2C if I2C
 683         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 684         select HAVE_S3C_RTC if RTC_CLASS
 685         select MULTI_IRQ_HANDLER
 686         select NEED_MACH_IO_H
 687         select SAMSUNG_ATAGS
 688         help
 689           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 690           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 691           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 692           Samsung SMDK2410 development board (and derivatives).
 693
 694 config ARCH_S3C64XX
 695         bool "Samsung S3C64XX"
 696         select ARCH_REQUIRE_GPIOLIB
 697         select ARM_AMBA
 698         select ARM_VIC
 699         select ATAGS
 700         select CLKDEV_LOOKUP
 701         select CLKSRC_SAMSUNG_PWM
 702         select COMMON_CLK_SAMSUNG
 703         select CPU_V6K
 704         select GENERIC_CLOCKEVENTS
 705         select GPIO_SAMSUNG
 706         select HAVE_S3C2410_I2C if I2C
 707         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 708         select HAVE_TCM
 709         select NO_IOPORT_MAP
 710         select PLAT_SAMSUNG
 711         select PM_GENERIC_DOMAINS if PM
 712         select S3C_DEV_NAND
 713         select S3C_GPIO_TRACK
 714         select SAMSUNG_ATAGS
 715         select SAMSUNG_WAKEMASK
 716         select SAMSUNG_WDT_RESET
 717         help
 718           Samsung S3C64XX series based systems
 719
 720 config ARCH_DAVINCI
 721         bool "TI DaVinci"
 722         select ARCH_HAS_HOLES_MEMORYMODEL
 723         select ARCH_REQUIRE_GPIOLIB
 724         select CLKDEV_LOOKUP
 725         select GENERIC_ALLOCATOR
 726         select GENERIC_CLOCKEVENTS
 727         select GENERIC_IRQ_CHIP
 728         select HAVE_IDE
 729         select USE_OF
 730         select ZONE_DMA
 731         help
 732           Support for TI's DaVinci platform.
 733
 734 config ARCH_OMAP1
 735         bool "TI OMAP1"
 736         depends on MMU
 737         select ARCH_HAS_HOLES_MEMORYMODEL
 738         select ARCH_OMAP
 739         select ARCH_REQUIRE_GPIOLIB
 740         select CLKDEV_LOOKUP
 741         select CLKSRC_MMIO
 742         select GENERIC_CLOCKEVENTS
 743         select GENERIC_IRQ_CHIP
 744         select HAVE_IDE
 745         select IRQ_DOMAIN
 746         select MULTI_IRQ_HANDLER
 747         select NEED_MACH_IO_H if PCCARD
 748         select NEED_MACH_MEMORY_H
 749         select SPARSE_IRQ
 750         help
 751           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 752
 753 endchoice
 754
 755 menu "Multiple platform selection"
 756         depends on ARCH_MULTIPLATFORM
 757
 758 comment "CPU Core family selection"
 759
 760 config ARCH_MULTI_V4
 761         bool "ARMv4 based platforms (FA526)"
 762         depends on !ARCH_MULTI_V6_V7
 763         select ARCH_MULTI_V4_V5
 764         select CPU_FA526
 765
 766 config ARCH_MULTI_V4T
 767         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 768         depends on !ARCH_MULTI_V6_V7
 769         select ARCH_MULTI_V4_V5
 770         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 771                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 772                 CPU_ARM925T || CPU_ARM940T)
 773
 774 config ARCH_MULTI_V5
 775         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 776         depends on !ARCH_MULTI_V6_V7
 777         select ARCH_MULTI_V4_V5
 778         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 779                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 780                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 781
 782 config ARCH_MULTI_V4_V5
 783         bool
 784
 785 config ARCH_MULTI_V6
 786         bool "ARMv6 based platforms (ARM11)"
 787         select ARCH_MULTI_V6_V7
 788         select CPU_V6K
 789
 790 config ARCH_MULTI_V7
 791         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 792         default y
 793         select ARCH_MULTI_V6_V7
 794         select CPU_V7
 795         select HAVE_SMP
 796
 797 config ARCH_MULTI_V6_V7
 798         bool
 799         select MIGHT_HAVE_CACHE_L2X0
 800
 801 config ARCH_MULTI_CPU_AUTO
 802         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 803         select ARCH_MULTI_V5
 804
 805 endmenu
 806
 807 config ARCH_VIRT
 808         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 809         select ARM_AMBA
 810         select ARM_GIC
 811         select ARM_GIC_V2M if PCI_MSI
 812         select ARM_GIC_V3
 813         select ARM_PSCI
 814         select HAVE_ARM_ARCH_TIMER
 815
 816 #
 817 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 818 # Kconfigs may be included either alphabetically (according to the
 819 # plat- suffix) or along side the corresponding mach-* source.
 820 #
 821 source "arch/arm/mach-mvebu/Kconfig"
 822
 823 source "arch/arm/mach-alpine/Kconfig"
 824
 825 source "arch/arm/mach-asm9260/Kconfig"
 826
 827 source "arch/arm/mach-at91/Kconfig"
 828
 829 source "arch/arm/mach-axxia/Kconfig"
 830
 831 source "arch/arm/mach-bcm/Kconfig"
 832
 833 source "arch/arm/mach-berlin/Kconfig"
 834
 835 source "arch/arm/mach-clps711x/Kconfig"
 836
 837 source "arch/arm/mach-cns3xxx/Kconfig"
 838
 839 source "arch/arm/mach-davinci/Kconfig"
 840
 841 source "arch/arm/mach-digicolor/Kconfig"
 842
 843 source "arch/arm/mach-dove/Kconfig"
 844
 845 source "arch/arm/mach-ep93xx/Kconfig"
 846
 847 source "arch/arm/mach-footbridge/Kconfig"
 848
 849 source "arch/arm/mach-gemini/Kconfig"
 850
 851 source "arch/arm/mach-highbank/Kconfig"
 852
 853 source "arch/arm/mach-hisi/Kconfig"
 854
 855 source "arch/arm/mach-integrator/Kconfig"
 856
 857 source "arch/arm/mach-iop32x/Kconfig"
 858
 859 source "arch/arm/mach-iop33x/Kconfig"
 860
 861 source "arch/arm/mach-iop13xx/Kconfig"
 862
 863 source "arch/arm/mach-ixp4xx/Kconfig"
 864
 865 source "arch/arm/mach-keystone/Kconfig"
 866
 867 source "arch/arm/mach-ks8695/Kconfig"
 868
 869 source "arch/arm/mach-meson/Kconfig"
 870
 871 source "arch/arm/mach-moxart/Kconfig"
 872
 873 source "arch/arm/mach-mv78xx0/Kconfig"
 874
 875 source "arch/arm/mach-imx/Kconfig"
 876
 877 source "arch/arm/mach-mediatek/Kconfig"
 878
 879 source "arch/arm/mach-mxs/Kconfig"
 880
 881 source "arch/arm/mach-netx/Kconfig"
 882
 883 source "arch/arm/mach-nomadik/Kconfig"
 884
 885 source "arch/arm/mach-nspire/Kconfig"
 886
 887 source "arch/arm/plat-omap/Kconfig"
 888
 889 source "arch/arm/mach-omap1/Kconfig"
 890
 891 source "arch/arm/mach-omap2/Kconfig"
 892
 893 source "arch/arm/mach-orion5x/Kconfig"
 894
 895 source "arch/arm/mach-picoxcell/Kconfig"
 896
 897 source "arch/arm/mach-pxa/Kconfig"
 898 source "arch/arm/plat-pxa/Kconfig"
 899
 900 source "arch/arm/mach-mmp/Kconfig"
 901
 902 source "arch/arm/mach-qcom/Kconfig"
 903
 904 source "arch/arm/mach-realview/Kconfig"
 905
 906 source "arch/arm/mach-rockchip/Kconfig"
 907
 908 source "arch/arm/mach-sa1100/Kconfig"
 909
 910 source "arch/arm/mach-socfpga/Kconfig"
 911
 912 source "arch/arm/mach-spear/Kconfig"
 913
 914 source "arch/arm/mach-sti/Kconfig"
 915
 916 source "arch/arm/mach-s3c24xx/Kconfig"
 917
 918 source "arch/arm/mach-s3c64xx/Kconfig"
 919
 920 source "arch/arm/mach-s5pv210/Kconfig"
 921
 922 source "arch/arm/mach-exynos/Kconfig"
 923 source "arch/arm/plat-samsung/Kconfig"
 924
 925 source "arch/arm/mach-shmobile/Kconfig"
 926
 927 source "arch/arm/mach-sunxi/Kconfig"
 928
 929 source "arch/arm/mach-prima2/Kconfig"
 930
 931 source "arch/arm/mach-tegra/Kconfig"
 932
 933 source "arch/arm/mach-u300/Kconfig"
 934
 935 source "arch/arm/mach-uniphier/Kconfig"
 936
 937 source "arch/arm/mach-ux500/Kconfig"
 938
 939 source "arch/arm/mach-versatile/Kconfig"
 940
 941 source "arch/arm/mach-vexpress/Kconfig"
 942 source "arch/arm/plat-versatile/Kconfig"
 943
 944 source "arch/arm/mach-vt8500/Kconfig"
 945
 946 source "arch/arm/mach-w90x900/Kconfig"
 947
 948 source "arch/arm/mach-zx/Kconfig"
 949
 950 source "arch/arm/mach-zynq/Kconfig"
 951
 952 # ARMv7-M architecture
 953 config ARCH_EFM32
 954         bool "Energy Micro efm32"
 955         depends on ARM_SINGLE_ARMV7M
 956         select ARCH_REQUIRE_GPIOLIB
 957         help
 958           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 959           processors.
 960
 961 config ARCH_LPC18XX
 962         bool "NXP LPC18xx/LPC43xx"
 963         depends on ARM_SINGLE_ARMV7M
 964         select ARCH_HAS_RESET_CONTROLLER
 965         select ARM_AMBA
 966         select CLKSRC_LPC32XX
 967         select PINCTRL
 968         help
 969           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 970           high performance microcontrollers.
 971
 972 config ARCH_STM32
 973         bool "STMicrolectronics STM32"
 974         depends on ARM_SINGLE_ARMV7M
 975         select ARCH_HAS_RESET_CONTROLLER
 976         select ARMV7M_SYSTICK
 977         select CLKSRC_STM32
 978         select RESET_CONTROLLER
 979         help
 980           Support for STMicroelectronics STM32 processors.
 981
 982 # Definitions to make life easier
 983 config ARCH_ACORN
 984         bool
 985
 986 config PLAT_IOP
 987         bool
 988         select GENERIC_CLOCKEVENTS
 989
 990 config PLAT_ORION
 991         bool
 992         select CLKSRC_MMIO
 993         select COMMON_CLK
 994         select GENERIC_IRQ_CHIP
 995         select IRQ_DOMAIN
 996
 997 config PLAT_ORION_LEGACY
 998         bool
 999         select PLAT_ORION
1000
1001 config PLAT_PXA
1002         bool
1003
1004 config PLAT_VERSATILE
1005         bool
1006
1007 source "arch/arm/firmware/Kconfig"
1008
1009 source arch/arm/mm/Kconfig
1010
1011 config IWMMXT
1012         bool "Enable iWMMXt support"
1013         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1014         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1015         help
1016           Enable support for iWMMXt context switching at run time if
1017           running on a CPU that supports it.
1018
1019 config MULTI_IRQ_HANDLER
1020         bool
1021         help
1022           Allow each machine to specify it's own IRQ handler at run time.
1023
1024 if !MMU
1025 source "arch/arm/Kconfig-nommu"
1026 endif
1027
1028 config PJ4B_ERRATA_4742
1029         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1030         depends on CPU_PJ4B && MACH_ARMADA_370
1031         default y
1032         help
1033           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1034           Event (WFE) IDLE states, a specific timing sensitivity exists between
1035           the retiring WFI/WFE instructions and the newly issued subsequent
1036           instructions.  This sensitivity can result in a CPU hang scenario.
1037           Workaround:
1038           The software must insert either a Data Synchronization Barrier (DSB)
1039           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1040           instruction
1041
1042 config ARM_ERRATA_326103
1043         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1044         depends on CPU_V6
1045         help
1046           Executing a SWP instruction to read-only memory does not set bit 11
1047           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1048           treat the access as a read, preventing a COW from occurring and
1049           causing the faulting task to livelock.
1050
1051 config ARM_ERRATA_411920
1052         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1053         depends on CPU_V6 || CPU_V6K
1054         help
1055           Invalidation of the Instruction Cache operation can
1056           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1057           It does not affect the MPCore. This option enables the ARM Ltd.
1058           recommended workaround.
1059
1060 config ARM_ERRATA_430973
1061         bool "ARM errata: Stale prediction on replaced interworking branch"
1062         depends on CPU_V7
1063         help
1064           This option enables the workaround for the 430973 Cortex-A8
1065           r1p* erratum. If a code sequence containing an ARM/Thumb
1066           interworking branch is replaced with another code sequence at the
1067           same virtual address, whether due to self-modifying code or virtual
1068           to physical address re-mapping, Cortex-A8 does not recover from the
1069           stale interworking branch prediction. This results in Cortex-A8
1070           executing the new code sequence in the incorrect ARM or Thumb state.
1071           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1072           and also flushes the branch target cache at every context switch.
1073           Note that setting specific bits in the ACTLR register may not be
1074           available in non-secure mode.
1075
1076 config ARM_ERRATA_458693
1077         bool "ARM errata: Processor deadlock when a false hazard is created"
1078         depends on CPU_V7
1079         depends on !ARCH_MULTIPLATFORM
1080         help
1081           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1082           erratum. For very specific sequences of memory operations, it is
1083           possible for a hazard condition intended for a cache line to instead
1084           be incorrectly associated with a different cache line. This false
1085           hazard might then cause a processor deadlock. The workaround enables
1086           the L1 caching of the NEON accesses and disables the PLD instruction
1087           in the ACTLR register. Note that setting specific bits in the ACTLR
1088           register may not be available in non-secure mode.
1089
1090 config ARM_ERRATA_460075
1091         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1092         depends on CPU_V7
1093         depends on !ARCH_MULTIPLATFORM
1094         help
1095           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1096           erratum. Any asynchronous access to the L2 cache may encounter a
1097           situation in which recent store transactions to the L2 cache are lost
1098           and overwritten with stale memory contents from external memory. The
1099           workaround disables the write-allocate mode for the L2 cache via the
1100           ACTLR register. Note that setting specific bits in the ACTLR register
1101           may not be available in non-secure mode.
1102
1103 config ARM_ERRATA_742230
1104         bool "ARM errata: DMB operation may be faulty"
1105         depends on CPU_V7 && SMP
1106         depends on !ARCH_MULTIPLATFORM
1107         help
1108           This option enables the workaround for the 742230 Cortex-A9
1109           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1110           between two write operations may not ensure the correct visibility
1111           ordering of the two writes. This workaround sets a specific bit in
1112           the diagnostic register of the Cortex-A9 which causes the DMB
1113           instruction to behave as a DSB, ensuring the correct behaviour of
1114           the two writes.
1115
1116 config ARM_ERRATA_742231
1117         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1118         depends on CPU_V7 && SMP
1119         depends on !ARCH_MULTIPLATFORM
1120         help
1121           This option enables the workaround for the 742231 Cortex-A9
1122           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1123           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1124           accessing some data located in the same cache line, may get corrupted
1125           data due to bad handling of the address hazard when the line gets
1126           replaced from one of the CPUs at the same time as another CPU is
1127           accessing it. This workaround sets specific bits in the diagnostic
1128           register of the Cortex-A9 which reduces the linefill issuing
1129           capabilities of the processor.
1130
1131 config ARM_ERRATA_643719
1132         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1133         depends on CPU_V7 && SMP
1134         default y
1135         help
1136           This option enables the workaround for the 643719 Cortex-A9 (prior to
1137           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1138           register returns zero when it should return one. The workaround
1139           corrects this value, ensuring cache maintenance operations which use
1140           it behave as intended and avoiding data corruption.
1141
1142 config ARM_ERRATA_720789
1143         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1144         depends on CPU_V7
1145         help
1146           This option enables the workaround for the 720789 Cortex-A9 (prior to
1147           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1148           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1149           As a consequence of this erratum, some TLB entries which should be
1150           invalidated are not, resulting in an incoherency in the system page
1151           tables. The workaround changes the TLB flushing routines to invalidate
1152           entries regardless of the ASID.
1153
1154 config ARM_ERRATA_743622
1155         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1156         depends on CPU_V7
1157         depends on !ARCH_MULTIPLATFORM
1158         help
1159           This option enables the workaround for the 743622 Cortex-A9
1160           (r2p*) erratum. Under very rare conditions, a faulty
1161           optimisation in the Cortex-A9 Store Buffer may lead to data
1162           corruption. This workaround sets a specific bit in the diagnostic
1163           register of the Cortex-A9 which disables the Store Buffer
1164           optimisation, preventing the defect from occurring. This has no
1165           visible impact on the overall performance or power consumption of the
1166           processor.
1167
1168 config ARM_ERRATA_751472
1169         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1170         depends on CPU_V7
1171         depends on !ARCH_MULTIPLATFORM
1172         help
1173           This option enables the workaround for the 751472 Cortex-A9 (prior
1174           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1175           completion of a following broadcasted operation if the second
1176           operation is received by a CPU before the ICIALLUIS has completed,
1177           potentially leading to corrupted entries in the cache or TLB.
1178
1179 config ARM_ERRATA_754322
1180         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1181         depends on CPU_V7
1182         help
1183           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1184           r3p*) erratum. A speculative memory access may cause a page table walk
1185           which starts prior to an ASID switch but completes afterwards. This
1186           can populate the micro-TLB with a stale entry which may be hit with
1187           the new ASID. This workaround places two dsb instructions in the mm
1188           switching code so that no page table walks can cross the ASID switch.
1189
1190 config ARM_ERRATA_754327
1191         bool "ARM errata: no automatic Store Buffer drain"
1192         depends on CPU_V7 && SMP
1193         help
1194           This option enables the workaround for the 754327 Cortex-A9 (prior to
1195           r2p0) erratum. The Store Buffer does not have any automatic draining
1196           mechanism and therefore a livelock may occur if an external agent
1197           continuously polls a memory location waiting to observe an update.
1198           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1199           written polling loops from denying visibility of updates to memory.
1200
1201 config ARM_ERRATA_364296
1202         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1203         depends on CPU_V6
1204         help
1205           This options enables the workaround for the 364296 ARM1136
1206           r0p2 erratum (possible cache data corruption with
1207           hit-under-miss enabled). It sets the undocumented bit 31 in
1208           the auxiliary control register and the FI bit in the control
1209           register, thus disabling hit-under-miss without putting the
1210           processor into full low interrupt latency mode. ARM11MPCore
1211           is not affected.
1212
1213 config ARM_ERRATA_764369
1214         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1215         depends on CPU_V7 && SMP
1216         help
1217           This option enables the workaround for erratum 764369
1218           affecting Cortex-A9 MPCore with two or more processors (all
1219           current revisions). Under certain timing circumstances, a data
1220           cache line maintenance operation by MVA targeting an Inner
1221           Shareable memory region may fail to proceed up to either the
1222           Point of Coherency or to the Point of Unification of the
1223           system. This workaround adds a DSB instruction before the
1224           relevant cache maintenance functions and sets a specific bit
1225           in the diagnostic control register of the SCU.
1226
1227 config ARM_ERRATA_775420
1228        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1229        depends on CPU_V7
1230        help
1231          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1232          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1233          operation aborts with MMU exception, it might cause the processor
1234          to deadlock. This workaround puts DSB before executing ISB if
1235          an abort may occur on cache maintenance.
1236
1237 config ARM_ERRATA_798181
1238         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1239         depends on CPU_V7 && SMP
1240         help
1241           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1242           adequately shooting down all use of the old entries. This
1243           option enables the Linux kernel workaround for this erratum
1244           which sends an IPI to the CPUs that are running the same ASID
1245           as the one being invalidated.
1246
1247 config ARM_ERRATA_773022
1248         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1249         depends on CPU_V7
1250         help
1251           This option enables the workaround for the 773022 Cortex-A15
1252           (up to r0p4) erratum. In certain rare sequences of code, the
1253           loop buffer may deliver incorrect instructions. This
1254           workaround disables the loop buffer to avoid the erratum.
1255
1256 endmenu
1257
1258 source "arch/arm/common/Kconfig"
1259
1260 menu "Bus support"
1261
1262 config ISA
1263         bool
1264         help
1265           Find out whether you have ISA slots on your motherboard.  ISA is the
1266           name of a bus system, i.e. the way the CPU talks to the other stuff
1267           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1268           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1269           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1270
1271 # Select ISA DMA controller support
1272 config ISA_DMA
1273         bool
1274         select ISA_DMA_API
1275
1276 # Select ISA DMA interface
1277 config ISA_DMA_API
1278         bool
1279
1280 config PCI
1281         bool "PCI support" if MIGHT_HAVE_PCI
1282         help
1283           Find out whether you have a PCI motherboard. PCI is the name of a
1284           bus system, i.e. the way the CPU talks to the other stuff inside
1285           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1286           VESA. If you have PCI, say Y, otherwise N.
1287
1288 config PCI_DOMAINS
1289         bool
1290         depends on PCI
1291
1292 config PCI_DOMAINS_GENERIC
1293         def_bool PCI_DOMAINS
1294
1295 config PCI_NANOENGINE
1296         bool "BSE nanoEngine PCI support"
1297         depends on SA1100_NANOENGINE
1298         help
1299           Enable PCI on the BSE nanoEngine board.
1300
1301 config PCI_SYSCALL
1302         def_bool PCI
1303
1304 config PCI_HOST_ITE8152
1305         bool
1306         depends on PCI && MACH_ARMCORE
1307         default y
1308         select DMABOUNCE
1309
1310 source "drivers/pci/Kconfig"
1311 source "drivers/pci/pcie/Kconfig"
1312
1313 source "drivers/pcmcia/Kconfig"
1314
1315 endmenu
1316
1317 menu "Kernel Features"
1318
1319 config HAVE_SMP
1320         bool
1321         help
1322           This option should be selected by machines which have an SMP-
1323           capable CPU.
1324
1325           The only effect of this option is to make the SMP-related
1326           options available to the user for configuration.
1327
1328 config SMP
1329         bool "Symmetric Multi-Processing"
1330         depends on CPU_V6K || CPU_V7
1331         depends on GENERIC_CLOCKEVENTS
1332         depends on HAVE_SMP
1333         depends on MMU || ARM_MPU
1334         select IRQ_WORK
1335         help
1336           This enables support for systems with more than one CPU. If you have
1337           a system with only one CPU, say N. If you have a system with more
1338           than one CPU, say Y.
1339
1340           If you say N here, the kernel will run on uni- and multiprocessor
1341           machines, but will use only one CPU of a multiprocessor machine. If
1342           you say Y here, the kernel will run on many, but not all,
1343           uniprocessor machines. On a uniprocessor machine, the kernel
1344           will run faster if you say N here.
1345
1346           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1347           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1348           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1349
1350           If you don't know what to do here, say N.
1351
1352 config SMP_ON_UP
1353         bool "Allow booting SMP kernel on uniprocessor systems"
1354         depends on SMP && !XIP_KERNEL && MMU
1355         default y
1356         help
1357           SMP kernels contain instructions which fail on non-SMP processors.
1358           Enabling this option allows the kernel to modify itself to make
1359           these instructions safe.  Disabling it allows about 1K of space
1360           savings.
1361
1362           If you don't know what to do here, say Y.
1363
1364 config ARM_CPU_TOPOLOGY
1365         bool "Support cpu topology definition"
1366         depends on SMP && CPU_V7
1367         default y
1368         help
1369           Support ARM cpu topology definition. The MPIDR register defines
1370           affinity between processors which is then used to describe the cpu
1371           topology of an ARM System.
1372
1373 config SCHED_MC
1374         bool "Multi-core scheduler support"
1375         depends on ARM_CPU_TOPOLOGY
1376         help
1377           Multi-core scheduler support improves the CPU scheduler's decision
1378           making when dealing with multi-core CPU chips at a cost of slightly
1379           increased overhead in some places. If unsure say N here.
1380
1381 config SCHED_SMT
1382         bool "SMT scheduler support"
1383         depends on ARM_CPU_TOPOLOGY
1384         help
1385           Improves the CPU scheduler's decision making when dealing with
1386           MultiThreading at a cost of slightly increased overhead in some
1387           places. If unsure say N here.
1388
1389 config HAVE_ARM_SCU
1390         bool
1391         help
1392           This option enables support for the ARM system coherency unit
1393
1394 config HAVE_ARM_ARCH_TIMER
1395         bool "Architected timer support"
1396         depends on CPU_V7
1397         select ARM_ARCH_TIMER
1398         select GENERIC_CLOCKEVENTS
1399         help
1400           This option enables support for the ARM architected timer
1401
1402 config HAVE_ARM_TWD
1403         bool
1404         select CLKSRC_OF if OF
1405         help
1406           This options enables support for the ARM timer and watchdog unit
1407
1408 config MCPM
1409         bool "Multi-Cluster Power Management"
1410         depends on CPU_V7 && SMP
1411         help
1412           This option provides the common power management infrastructure
1413           for (multi-)cluster based systems, such as big.LITTLE based
1414           systems.
1415
1416 config MCPM_QUAD_CLUSTER
1417         bool
1418         depends on MCPM
1419         help
1420           To avoid wasting resources unnecessarily, MCPM only supports up
1421           to 2 clusters by default.
1422           Platforms with 3 or 4 clusters that use MCPM must select this
1423           option to allow the additional clusters to be managed.
1424
1425 config BIG_LITTLE
1426         bool "big.LITTLE support (Experimental)"
1427         depends on CPU_V7 && SMP
1428         select MCPM
1429         help
1430           This option enables support selections for the big.LITTLE
1431           system architecture.
1432
1433 config BL_SWITCHER
1434         bool "big.LITTLE switcher support"
1435         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1436         select ARM_CPU_SUSPEND
1437         select CPU_PM
1438         help
1439           The big.LITTLE "switcher" provides the core functionality to
1440           transparently handle transition between a cluster of A15's
1441           and a cluster of A7's in a big.LITTLE system.
1442
1443 config BL_SWITCHER_DUMMY_IF
1444         tristate "Simple big.LITTLE switcher user interface"
1445         depends on BL_SWITCHER && DEBUG_KERNEL
1446         help
1447           This is a simple and dummy char dev interface to control
1448           the big.LITTLE switcher core code.  It is meant for
1449           debugging purposes only.
1450
1451 choice
1452         prompt "Memory split"
1453         depends on MMU
1454         default VMSPLIT_3G
1455         help
1456           Select the desired split between kernel and user memory.
1457
1458           If you are not absolutely sure what you are doing, leave this
1459           option alone!
1460
1461         config VMSPLIT_3G
1462                 bool "3G/1G user/kernel split"
1463         config VMSPLIT_3G_OPT
1464                 bool "3G/1G user/kernel split (for full 1G low memory)"
1465         config VMSPLIT_2G
1466                 bool "2G/2G user/kernel split"
1467         config VMSPLIT_1G
1468                 bool "1G/3G user/kernel split"
1469 endchoice
1470
1471 config PAGE_OFFSET
1472         hex
1473         default PHYS_OFFSET if !MMU
1474         default 0x40000000 if VMSPLIT_1G
1475         default 0x80000000 if VMSPLIT_2G
1476         default 0xB0000000 if VMSPLIT_3G_OPT
1477         default 0xC0000000
1478
1479 config NR_CPUS
1480         int "Maximum number of CPUs (2-32)"
1481         range 2 32
1482         depends on SMP
1483         default "4"
1484
1485 config HOTPLUG_CPU
1486         bool "Support for hot-pluggable CPUs"
1487         depends on SMP
1488         help
1489           Say Y here to experiment with turning CPUs off and on.  CPUs
1490           can be controlled through /sys/devices/system/cpu.
1491
1492 config ARM_PSCI
1493         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1494         depends on HAVE_ARM_SMCCC
1495         select ARM_PSCI_FW
1496         help
1497           Say Y here if you want Linux to communicate with system firmware
1498           implementing the PSCI specification for CPU-centric power
1499           management operations described in ARM document number ARM DEN
1500           0022A ("Power State Coordination Interface System Software on
1501           ARM processors").
1502
1503 # The GPIO number here must be sorted by descending number. In case of
1504 # a multiplatform kernel, we just want the highest value required by the
1505 # selected platforms.
1506 config ARCH_NR_GPIO
1507         int
1508         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1509                 ARCH_ZYNQ
1510         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1511                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1512         default 416 if ARCH_SUNXI
1513         default 392 if ARCH_U8500
1514         default 352 if ARCH_VT8500
1515         default 288 if ARCH_ROCKCHIP
1516         default 264 if MACH_H4700
1517         default 0
1518         help
1519           Maximum number of GPIOs in the system.
1520
1521           If unsure, leave the default value.
1522
1523 source kernel/Kconfig.preempt
1524
1525 config HZ_FIXED
1526         int
1527         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1528                 ARCH_S5PV210 || ARCH_EXYNOS4
1529         default 128 if SOC_AT91RM9200
1530         default 0
1531
1532 choice
1533         depends on HZ_FIXED = 0
1534         prompt "Timer frequency"
1535
1536 config HZ_100
1537         bool "100 Hz"
1538
1539 config HZ_200
1540         bool "200 Hz"
1541
1542 config HZ_250
1543         bool "250 Hz"
1544
1545 config HZ_300
1546         bool "300 Hz"
1547
1548 config HZ_500
1549         bool "500 Hz"
1550
1551 config HZ_1000
1552         bool "1000 Hz"
1553
1554 endchoice
1555
1556 config HZ
1557         int
1558         default HZ_FIXED if HZ_FIXED != 0
1559         default 100 if HZ_100
1560         default 200 if HZ_200
1561         default 250 if HZ_250
1562         default 300 if HZ_300
1563         default 500 if HZ_500
1564         default 1000
1565
1566 config SCHED_HRTICK
1567         def_bool HIGH_RES_TIMERS
1568
1569 config THUMB2_KERNEL
1570         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1571         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1572         default y if CPU_THUMBONLY
1573         select AEABI
1574         select ARM_ASM_UNIFIED
1575         select ARM_UNWIND
1576         help
1577           By enabling this option, the kernel will be compiled in
1578           Thumb-2 mode. A compiler/assembler that understand the unified
1579           ARM-Thumb syntax is needed.
1580
1581           If unsure, say N.
1582
1583 config THUMB2_AVOID_R_ARM_THM_JUMP11
1584         bool "Work around buggy Thumb-2 short branch relocations in gas"
1585         depends on THUMB2_KERNEL && MODULES
1586         default y
1587         help
1588           Various binutils versions can resolve Thumb-2 branches to
1589           locally-defined, preemptible global symbols as short-range "b.n"
1590           branch instructions.
1591
1592           This is a problem, because there's no guarantee the final
1593           destination of the symbol, or any candidate locations for a
1594           trampoline, are within range of the branch.  For this reason, the
1595           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1596           relocation in modules at all, and it makes little sense to add
1597           support.
1598
1599           The symptom is that the kernel fails with an "unsupported
1600           relocation" error when loading some modules.
1601
1602           Until fixed tools are available, passing
1603           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1604           code which hits this problem, at the cost of a bit of extra runtime
1605           stack usage in some cases.
1606
1607           The problem is described in more detail at:
1608               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1609
1610           Only Thumb-2 kernels are affected.
1611
1612           Unless you are sure your tools don't have this problem, say Y.
1613
1614 config ARM_ASM_UNIFIED
1615         bool
1616
1617 config ARM_PATCH_IDIV
1618         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1619         depends on CPU_32v7 && !XIP_KERNEL
1620         default y
1621         help
1622           The ARM compiler inserts calls to __aeabi_idiv() and
1623           __aeabi_uidiv() when it needs to perform division on signed
1624           and unsigned integers. Some v7 CPUs have support for the sdiv
1625           and udiv instructions that can be used to implement those
1626           functions.
1627
1628           Enabling this option allows the kernel to modify itself to
1629           replace the first two instructions of these library functions
1630           with the sdiv or udiv plus "bx lr" instructions when the CPU
1631           it is running on supports them. Typically this will be faster
1632           and less power intensive than running the original library
1633           code to do integer division.
1634
1635 config AEABI
1636         bool "Use the ARM EABI to compile the kernel"
1637         help
1638           This option allows for the kernel to be compiled using the latest
1639           ARM ABI (aka EABI).  This is only useful if you are using a user
1640           space environment that is also compiled with EABI.
1641
1642           Since there are major incompatibilities between the legacy ABI and
1643           EABI, especially with regard to structure member alignment, this
1644           option also changes the kernel syscall calling convention to
1645           disambiguate both ABIs and allow for backward compatibility support
1646           (selected with CONFIG_OABI_COMPAT).
1647
1648           To use this you need GCC version 4.0.0 or later.
1649
1650 config OABI_COMPAT
1651         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1652         depends on AEABI && !THUMB2_KERNEL
1653         help
1654           This option preserves the old syscall interface along with the
1655           new (ARM EABI) one. It also provides a compatibility layer to
1656           intercept syscalls that have structure arguments which layout
1657           in memory differs between the legacy ABI and the new ARM EABI
1658           (only for non "thumb" binaries). This option adds a tiny
1659           overhead to all syscalls and produces a slightly larger kernel.
1660
1661           The seccomp filter system will not be available when this is
1662           selected, since there is no way yet to sensibly distinguish
1663           between calling conventions during filtering.
1664
1665           If you know you'll be using only pure EABI user space then you
1666           can say N here. If this option is not selected and you attempt
1667           to execute a legacy ABI binary then the result will be
1668           UNPREDICTABLE (in fact it can be predicted that it won't work
1669           at all). If in doubt say N.
1670
1671 config ARCH_HAS_HOLES_MEMORYMODEL
1672         bool
1673
1674 config ARCH_SPARSEMEM_ENABLE
1675         bool
1676
1677 config ARCH_SPARSEMEM_DEFAULT
1678         def_bool ARCH_SPARSEMEM_ENABLE
1679
1680 config ARCH_SELECT_MEMORY_MODEL
1681         def_bool ARCH_SPARSEMEM_ENABLE
1682
1683 config HAVE_ARCH_PFN_VALID
1684         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1685
1686 config HAVE_GENERIC_RCU_GUP
1687         def_bool y
1688         depends on ARM_LPAE
1689
1690 config HIGHMEM
1691         bool "High Memory Support"
1692         depends on MMU
1693         help
1694           The address space of ARM processors is only 4 Gigabytes large
1695           and it has to accommodate user address space, kernel address
1696           space as well as some memory mapped IO. That means that, if you
1697           have a large amount of physical memory and/or IO, not all of the
1698           memory can be "permanently mapped" by the kernel. The physical
1699           memory that is not permanently mapped is called "high memory".
1700
1701           Depending on the selected kernel/user memory split, minimum
1702           vmalloc space and actual amount of RAM, you may not need this
1703           option which should result in a slightly faster kernel.
1704
1705           If unsure, say n.
1706
1707 config HIGHPTE
1708         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1709         depends on HIGHMEM
1710         default y
1711         help
1712           The VM uses one page of physical memory for each page table.
1713           For systems with a lot of processes, this can use a lot of
1714           precious low memory, eventually leading to low memory being
1715           consumed by page tables.  Setting this option will allow
1716           user-space 2nd level page tables to reside in high memory.
1717
1718 config CPU_SW_DOMAIN_PAN
1719         bool "Enable use of CPU domains to implement privileged no-access"
1720         depends on MMU && !ARM_LPAE
1721         default y
1722         help
1723           Increase kernel security by ensuring that normal kernel accesses
1724           are unable to access userspace addresses.  This can help prevent
1725           use-after-free bugs becoming an exploitable privilege escalation
1726           by ensuring that magic values (such as LIST_POISON) will always
1727           fault when dereferenced.
1728
1729           CPUs with low-vector mappings use a best-efforts implementation.
1730           Their lower 1MB needs to remain accessible for the vectors, but
1731           the remainder of userspace will become appropriately inaccessible.
1732
1733 config HW_PERF_EVENTS
1734         def_bool y
1735         depends on ARM_PMU
1736
1737 config SYS_SUPPORTS_HUGETLBFS
1738        def_bool y
1739        depends on ARM_LPAE
1740
1741 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1742        def_bool y
1743        depends on ARM_LPAE
1744
1745 config ARCH_WANT_GENERAL_HUGETLB
1746         def_bool y
1747
1748 config ARM_MODULE_PLTS
1749         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1750         depends on MODULES
1751         help
1752           Allocate PLTs when loading modules so that jumps and calls whose
1753           targets are too far away for their relative offsets to be encoded
1754           in the instructions themselves can be bounced via veneers in the
1755           module's PLT. This allows modules to be allocated in the generic
1756           vmalloc area after the dedicated module memory area has been
1757           exhausted. The modules will use slightly more memory, but after
1758           rounding up to page size, the actual memory footprint is usually
1759           the same.
1760
1761           Say y if you are getting out of memory errors while loading modules
1762
1763 source "mm/Kconfig"
1764
1765 config FORCE_MAX_ZONEORDER
1766         int "Maximum zone order"
1767         default "12" if SOC_AM33XX
1768         default "9" if SA1111 || ARCH_EFM32
1769         default "11"
1770         help
1771           The kernel memory allocator divides physically contiguous memory
1772           blocks into "zones", where each zone is a power of two number of
1773           pages.  This option selects the largest power of two that the kernel
1774           keeps in the memory allocator.  If you need to allocate very large
1775           blocks of physically contiguous memory, then you may need to
1776           increase this value.
1777
1778           This config option is actually maximum order plus one. For example,
1779           a value of 11 means that the largest free memory block is 2^10 pages.
1780
1781 config ALIGNMENT_TRAP
1782         bool
1783         depends on CPU_CP15_MMU
1784         default y if !ARCH_EBSA110
1785         select HAVE_PROC_CPU if PROC_FS
1786         help
1787           ARM processors cannot fetch/store information which is not
1788           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1789           address divisible by 4. On 32-bit ARM processors, these non-aligned
1790           fetch/store instructions will be emulated in software if you say
1791           here, which has a severe performance impact. This is necessary for
1792           correct operation of some network protocols. With an IP-only
1793           configuration it is safe to say N, otherwise say Y.
1794
1795 config UACCESS_WITH_MEMCPY
1796         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1797         depends on MMU
1798         default y if CPU_FEROCEON
1799         help
1800           Implement faster copy_to_user and clear_user methods for CPU
1801           cores where a 8-word STM instruction give significantly higher
1802           memory write throughput than a sequence of individual 32bit stores.
1803
1804           A possible side effect is a slight increase in scheduling latency
1805           between threads sharing the same address space if they invoke
1806           such copy operations with large buffers.
1807
1808           However, if the CPU data cache is using a write-allocate mode,
1809           this option is unlikely to provide any performance gain.
1810
1811 config SECCOMP
1812         bool
1813         prompt "Enable seccomp to safely compute untrusted bytecode"
1814         ---help---
1815           This kernel feature is useful for number crunching applications
1816           that may need to compute untrusted bytecode during their
1817           execution. By using pipes or other transports made available to
1818           the process as file descriptors supporting the read/write
1819           syscalls, it's possible to isolate those applications in
1820           their own address space using seccomp. Once seccomp is
1821           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1822           and the task is only allowed to execute a few safe syscalls
1823           defined by each seccomp mode.
1824
1825 config SWIOTLB
1826         def_bool y
1827
1828 config IOMMU_HELPER
1829         def_bool SWIOTLB
1830
1831 config PARAVIRT
1832         bool "Enable paravirtualization code"
1833         help
1834           This changes the kernel so it can modify itself when it is run
1835           under a hypervisor, potentially improving performance significantly
1836           over full virtualization.
1837
1838 config PARAVIRT_TIME_ACCOUNTING
1839         bool "Paravirtual steal time accounting"
1840         select PARAVIRT
1841         default n
1842         help
1843           Select this option to enable fine granularity task steal time
1844           accounting. Time spent executing other tasks in parallel with
1845           the current vCPU is discounted from the vCPU power. To account for
1846           that, there can be a small performance impact.
1847
1848           If in doubt, say N here.
1849
1850 config XEN_DOM0
1851         def_bool y
1852         depends on XEN
1853
1854 config XEN
1855         bool "Xen guest support on ARM"
1856         depends on ARM && AEABI && OF
1857         depends on CPU_V7 && !CPU_V6
1858         depends on !GENERIC_ATOMIC64
1859         depends on MMU
1860         select ARCH_DMA_ADDR_T_64BIT
1861         select ARM_PSCI
1862         select SWIOTLB_XEN
1863         select PARAVIRT
1864         help
1865           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1866
1867 endmenu
1868
1869 menu "Boot options"
1870
1871 config USE_OF
1872         bool "Flattened Device Tree support"
1873         select IRQ_DOMAIN
1874         select OF
1875         help
1876           Include support for flattened device tree machine descriptions.
1877
1878 config ATAGS
1879         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1880         default y
1881         help
1882           This is the traditional way of passing data to the kernel at boot
1883           time. If you are solely relying on the flattened device tree (or
1884           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1885           to remove ATAGS support from your kernel binary.  If unsure,
1886           leave this to y.
1887
1888 config DEPRECATED_PARAM_STRUCT
1889         bool "Provide old way to pass kernel parameters"
1890         depends on ATAGS
1891         help
1892           This was deprecated in 2001 and announced to live on for 5 years.
1893           Some old boot loaders still use this way.
1894
1895 # Compressed boot loader in ROM.  Yes, we really want to ask about
1896 # TEXT and BSS so we preserve their values in the config files.
1897 config ZBOOT_ROM_TEXT
1898         hex "Compressed ROM boot loader base address"
1899         default "0"
1900         help
1901           The physical address at which the ROM-able zImage is to be
1902           placed in the target.  Platforms which normally make use of
1903           ROM-able zImage formats normally set this to a suitable
1904           value in their defconfig file.
1905
1906           If ZBOOT_ROM is not enabled, this has no effect.
1907
1908 config ZBOOT_ROM_BSS
1909         hex "Compressed ROM boot loader BSS address"
1910         default "0"
1911         help
1912           The base address of an area of read/write memory in the target
1913           for the ROM-able zImage which must be available while the
1914           decompressor is running. It must be large enough to hold the
1915           entire decompressed kernel plus an additional 128 KiB.
1916           Platforms which normally make use of ROM-able zImage formats
1917           normally set this to a suitable value in their defconfig file.
1918
1919           If ZBOOT_ROM is not enabled, this has no effect.
1920
1921 config ZBOOT_ROM
1922         bool "Compressed boot loader in ROM/flash"
1923         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1924         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1925         help
1926           Say Y here if you intend to execute your compressed kernel image
1927           (zImage) directly from ROM or flash.  If unsure, say N.
1928
1929 config ARM_APPENDED_DTB
1930         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1931         depends on OF
1932         help
1933           With this option, the boot code will look for a device tree binary
1934           (DTB) appended to zImage
1935           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1936
1937           This is meant as a backward compatibility convenience for those
1938           systems with a bootloader that can't be upgraded to accommodate
1939           the documented boot protocol using a device tree.
1940
1941           Beware that there is very little in terms of protection against
1942           this option being confused by leftover garbage in memory that might
1943           look like a DTB header after a reboot if no actual DTB is appended
1944           to zImage.  Do not leave this option active in a production kernel
1945           if you don't intend to always append a DTB.  Proper passing of the
1946           location into r2 of a bootloader provided DTB is always preferable
1947           to this option.
1948
1949 config ARM_ATAG_DTB_COMPAT
1950         bool "Supplement the appended DTB with traditional ATAG information"
1951         depends on ARM_APPENDED_DTB
1952         help
1953           Some old bootloaders can't be updated to a DTB capable one, yet
1954           they provide ATAGs with memory configuration, the ramdisk address,
1955           the kernel cmdline string, etc.  Such information is dynamically
1956           provided by the bootloader and can't always be stored in a static
1957           DTB.  To allow a device tree enabled kernel to be used with such
1958           bootloaders, this option allows zImage to extract the information
1959           from the ATAG list and store it at run time into the appended DTB.
1960
1961 choice
1962         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1963         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1964
1965 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1966         bool "Use bootloader kernel arguments if available"
1967         help
1968           Uses the command-line options passed by the boot loader instead of
1969           the device tree bootargs property. If the boot loader doesn't provide
1970           any, the device tree bootargs property will be used.
1971
1972 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1973         bool "Extend with bootloader kernel arguments"
1974         help
1975           The command-line arguments provided by the boot loader will be
1976           appended to the the device tree bootargs property.
1977
1978 endchoice
1979
1980 config CMDLINE
1981         string "Default kernel command string"
1982         default ""
1983         help
1984           On some architectures (EBSA110 and CATS), there is currently no way
1985           for the boot loader to pass arguments to the kernel. For these
1986           architectures, you should supply some command-line options at build
1987           time by entering them here. As a minimum, you should specify the
1988           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1989
1990 choice
1991         prompt "Kernel command line type" if CMDLINE != ""
1992         default CMDLINE_FROM_BOOTLOADER
1993         depends on ATAGS
1994
1995 config CMDLINE_FROM_BOOTLOADER
1996         bool "Use bootloader kernel arguments if available"
1997         help
1998           Uses the command-line options passed by the boot loader. If
1999           the boot loader doesn't provide any, the default kernel command
2000           string provided in CMDLINE will be used.
2001
2002 config CMDLINE_EXTEND
2003         bool "Extend bootloader kernel arguments"
2004         help
2005           The command-line arguments provided by the boot loader will be
2006           appended to the default kernel command string.
2007
2008 config CMDLINE_FORCE
2009         bool "Always use the default kernel command string"
2010         help
2011           Always use the default kernel command string, even if the boot
2012           loader passes other arguments to the kernel.
2013           This is useful if you cannot or don't want to change the
2014           command-line options your boot loader passes to the kernel.
2015 endchoice
2016
2017 config XIP_KERNEL
2018         bool "Kernel Execute-In-Place from ROM"
2019         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2020         help
2021           Execute-In-Place allows the kernel to run from non-volatile storage
2022           directly addressable by the CPU, such as NOR flash. This saves RAM
2023           space since the text section of the kernel is not loaded from flash
2024           to RAM.  Read-write sections, such as the data section and stack,
2025           are still copied to RAM.  The XIP kernel is not compressed since
2026           it has to run directly from flash, so it will take more space to
2027           store it.  The flash address used to link the kernel object files,
2028           and for storing it, is configuration dependent. Therefore, if you
2029           say Y here, you must know the proper physical address where to
2030           store the kernel image depending on your own flash memory usage.
2031
2032           Also note that the make target becomes "make xipImage" rather than
2033           "make zImage" or "make Image".  The final kernel binary to put in
2034           ROM memory will be arch/arm/boot/xipImage.
2035
2036           If unsure, say N.
2037
2038 config XIP_PHYS_ADDR
2039         hex "XIP Kernel Physical Location"
2040         depends on XIP_KERNEL
2041         default "0x00080000"
2042         help
2043           This is the physical address in your flash memory the kernel will
2044           be linked for and stored to.  This address is dependent on your
2045           own flash usage.
2046
2047 config KEXEC
2048         bool "Kexec system call (EXPERIMENTAL)"
2049         depends on (!SMP || PM_SLEEP_SMP)
2050         depends on !CPU_V7M
2051         select KEXEC_CORE
2052         help
2053           kexec is a system call that implements the ability to shutdown your
2054           current kernel, and to start another kernel.  It is like a reboot
2055           but it is independent of the system firmware.   And like a reboot
2056           you can start any kernel with it, not just Linux.
2057
2058           It is an ongoing process to be certain the hardware in a machine
2059           is properly shutdown, so do not be surprised if this code does not
2060           initially work for you.
2061
2062 config ATAGS_PROC
2063         bool "Export atags in procfs"
2064         depends on ATAGS && KEXEC
2065         default y
2066         help
2067           Should the atags used to boot the kernel be exported in an "atags"
2068           file in procfs. Useful with kexec.
2069
2070 config CRASH_DUMP
2071         bool "Build kdump crash kernel (EXPERIMENTAL)"
2072         help
2073           Generate crash dump after being started by kexec. This should
2074           be normally only set in special crash dump kernels which are
2075           loaded in the main kernel with kexec-tools into a specially
2076           reserved region and then later executed after a crash by
2077           kdump/kexec. The crash dump kernel must be compiled to a
2078           memory address not used by the main kernel
2079
2080           For more details see Documentation/kdump/kdump.txt
2081
2082 config AUTO_ZRELADDR
2083         bool "Auto calculation of the decompressed kernel image address"
2084         help
2085           ZRELADDR is the physical address where the decompressed kernel
2086           image will be placed. If AUTO_ZRELADDR is selected, the address
2087           will be determined at run-time by masking the current IP with
2088           0xf8000000. This assumes the zImage being placed in the first 128MB
2089           from start of memory.
2090
2091 config EFI_STUB
2092         bool
2093
2094 config EFI
2095         bool "UEFI runtime support"
2096         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2097         select UCS2_STRING
2098         select EFI_PARAMS_FROM_FDT
2099         select EFI_STUB
2100         select EFI_ARMSTUB
2101         select EFI_RUNTIME_WRAPPERS
2102         ---help---
2103           This option provides support for runtime services provided
2104           by UEFI firmware (such as non-volatile variables, realtime
2105           clock, and platform reset). A UEFI stub is also provided to
2106           allow the kernel to be booted as an EFI application. This
2107           is only useful for kernels that may run on systems that have
2108           UEFI firmware.
2109
2110 endmenu
2111
2112 menu "CPU Power Management"
2113
2114 source "drivers/cpufreq/Kconfig"
2115
2116 source "drivers/cpuidle/Kconfig"
2117
2118 endmenu
2119
2120 menu "Floating point emulation"
2121
2122 comment "At least one emulation must be selected"
2123
2124 config FPE_NWFPE
2125         bool "NWFPE math emulation"
2126         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2127         ---help---
2128           Say Y to include the NWFPE floating point emulator in the kernel.
2129           This is necessary to run most binaries. Linux does not currently
2130           support floating point hardware so you need to say Y here even if
2131           your machine has an FPA or floating point co-processor podule.
2132
2133           You may say N here if you are going to load the Acorn FPEmulator
2134           early in the bootup.
2135
2136 config FPE_NWFPE_XP
2137         bool "Support extended precision"
2138         depends on FPE_NWFPE
2139         help
2140           Say Y to include 80-bit support in the kernel floating-point
2141           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2142           Note that gcc does not generate 80-bit operations by default,
2143           so in most cases this option only enlarges the size of the
2144           floating point emulator without any good reason.
2145
2146           You almost surely want to say N here.
2147
2148 config FPE_FASTFPE
2149         bool "FastFPE math emulation (EXPERIMENTAL)"
2150         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2151         ---help---
2152           Say Y here to include the FAST floating point emulator in the kernel.
2153           This is an experimental much faster emulator which now also has full
2154           precision for the mantissa.  It does not support any exceptions.
2155           It is very simple, and approximately 3-6 times faster than NWFPE.
2156
2157           It should be sufficient for most programs.  It may be not suitable
2158           for scientific calculations, but you have to check this for yourself.
2159           If you do not feel you need a faster FP emulation you should better
2160           choose NWFPE.
2161
2162 config VFP
2163         bool "VFP-format floating point maths"
2164         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2165         help
2166           Say Y to include VFP support code in the kernel. This is needed
2167           if your hardware includes a VFP unit.
2168
2169           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2170           release notes and additional status information.
2171
2172           Say N if your target does not have VFP hardware.
2173
2174 config VFPv3
2175         bool
2176         depends on VFP
2177         default y if CPU_V7
2178
2179 config NEON
2180         bool "Advanced SIMD (NEON) Extension support"
2181         depends on VFPv3 && CPU_V7
2182         help
2183           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2184           Extension.
2185
2186 config KERNEL_MODE_NEON
2187         bool "Support for NEON in kernel mode"
2188         depends on NEON && AEABI
2189         help
2190           Say Y to include support for NEON in kernel mode.
2191
2192 endmenu
2193
2194 menu "Userspace binary formats"
2195
2196 source "fs/Kconfig.binfmt"
2197
2198 endmenu
2199
2200 menu "Power management options"
2201
2202 source "kernel/power/Kconfig"
2203
2204 config ARCH_SUSPEND_POSSIBLE
2205         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2206                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2207         def_bool y
2208
2209 config ARM_CPU_SUSPEND
2210         def_bool PM_SLEEP
2211
2212 config ARCH_HIBERNATION_POSSIBLE
2213         bool
2214         depends on MMU
2215         default y if ARCH_SUSPEND_POSSIBLE
2216
2217 endmenu
2218
2219 source "net/Kconfig"
2220
2221 source "drivers/Kconfig"
2222
2223 source "drivers/firmware/Kconfig"
2224
2225 source "fs/Kconfig"
2226
2227 source "arch/arm/Kconfig.debug"
2228
2229 source "security/Kconfig"
2230
2231 source "crypto/Kconfig"
2232 if CRYPTO
2233 source "arch/arm/crypto/Kconfig"
2234 endif
2235
2236 source "lib/Kconfig"
2237
2238 source "arch/arm/kvm/Kconfig"