arch/powerpc/include/asm/book3s/64/hash.h

   1 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_H
   2 #define _ASM_POWERPC_BOOK3S_64_HASH_H
   3 #ifdef __KERNEL__
   4
   5 /*
   6  * Common bits between 4K and 64K pages in a linux-style PTE.
   7  * These match the bits in the (hardware-defined) PowerPC PTE as closely
   8  * as possible. Additional bits may be defined in pgtable-hash64-*.h
   9  *
  10  * Note: We only support user read/write permissions. Supervisor always
  11  * have full read/write to pages above PAGE_OFFSET (pages below that
  12  * always use the user access permissions).
  13  *
  14  * We could create separate kernel read-only if we used the 3 PP bits
  15  * combinations that newer processors provide but we currently don't.
  16  */
  17 #define _PAGE_PTE               0x00001
  18 #define _PAGE_PRESENT           0x00002 /* software: pte contains a translation */
  19 #define _PAGE_BIT_SWAP_TYPE     2
  20 #define _PAGE_USER              0x00004 /* matches one of the PP bits */
  21 #define _PAGE_EXEC              0x00008 /* No execute on POWER4 and newer (we invert) */
  22 #define _PAGE_GUARDED           0x00010
  23 /* We can derive Memory coherence from _PAGE_NO_CACHE */
  24 #define _PAGE_COHERENT          0x0
  25 #define _PAGE_NO_CACHE          0x00020 /* I: cache inhibit */
  26 #define _PAGE_WRITETHRU         0x00040 /* W: cache write-through */
  27 #define _PAGE_DIRTY             0x00080 /* C: page changed */
  28 #define _PAGE_ACCESSED          0x00100 /* R: page referenced */
  29 #define _PAGE_RW                0x00200 /* software: user write access allowed */
  30 #define _PAGE_HASHPTE           0x00400 /* software: pte has an associated HPTE */
  31 #define _PAGE_BUSY              0x00800 /* software: PTE & hash are busy */
  32 #define _PAGE_F_GIX             0x07000 /* full page: hidx bits */
  33 #define _PAGE_F_GIX_SHIFT       12
  34 #define _PAGE_F_SECOND          0x08000 /* Whether to use secondary hash or not */
  35 #define _PAGE_SPECIAL           0x10000 /* software: special page */
  36 #define _PAGE_SOFT_DIRTY        0x20000 /* software: software dirty tracking */
  37
  38 /*
  39  * THP pages can't be special. So use the _PAGE_SPECIAL
  40  */
  41 #define _PAGE_SPLITTING _PAGE_SPECIAL
  42
  43 /*
  44  * We need to differentiate between explicit huge page and THP huge
  45  * page, since THP huge page also need to track real subpage details
  46  */
  47 #define _PAGE_THP_HUGE  _PAGE_4K_PFN
  48
  49 /*
  50  * set of bits not changed in pmd_modify.
  51  */
  52 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS |               \
  53                          _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_SPLITTING | \
  54                          _PAGE_THP_HUGE | _PAGE_PTE | _PAGE_SOFT_DIRTY)
  55
  56 #ifdef CONFIG_PPC_64K_PAGES
  57 #include <asm/book3s/64/hash-64k.h>
  58 #else
  59 #include <asm/book3s/64/hash-4k.h>
  60 #endif
  61
  62 /*
  63  * Size of EA range mapped by our pagetables.
  64  */
  65 #define PGTABLE_EADDR_SIZE      (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
  66                                  PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
  67 #define PGTABLE_RANGE           (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
  68
  69 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
  70 #define PMD_CACHE_INDEX (PMD_INDEX_SIZE + 1)
  71 #else
  72 #define PMD_CACHE_INDEX PMD_INDEX_SIZE
  73 #endif
  74 /*
  75  * Define the address range of the kernel non-linear virtual area
  76  */
  77 #define KERN_VIRT_START ASM_CONST(0xD000000000000000)
  78 #define KERN_VIRT_SIZE  ASM_CONST(0x0000100000000000)
  79
  80 /*
  81  * The vmalloc space starts at the beginning of that region, and
  82  * occupies half of it on hash CPUs and a quarter of it on Book3E
  83  * (we keep a quarter for the virtual memmap)
  84  */
  85 #define VMALLOC_START   KERN_VIRT_START
  86 #define VMALLOC_SIZE    (KERN_VIRT_SIZE >> 1)
  87 #define VMALLOC_END     (VMALLOC_START + VMALLOC_SIZE)
  88
  89 /*
  90  * Region IDs
  91  */
  92 #define REGION_SHIFT            60UL
  93 #define REGION_MASK             (0xfUL << REGION_SHIFT)
  94 #define REGION_ID(ea)           (((unsigned long)(ea)) >> REGION_SHIFT)
  95
  96 #define VMALLOC_REGION_ID       (REGION_ID(VMALLOC_START))
  97 #define KERNEL_REGION_ID        (REGION_ID(PAGE_OFFSET))
  98 #define VMEMMAP_REGION_ID       (0xfUL) /* Server only */
  99 #define USER_REGION_ID          (0UL)
 100
 101 /*
 102  * Defines the address of the vmemap area, in its own region on
 103  * hash table CPUs.
 104  */
 105 #define VMEMMAP_BASE            (VMEMMAP_REGION_ID << REGION_SHIFT)
 106
 107 #ifdef CONFIG_PPC_MM_SLICES
 108 #define HAVE_ARCH_UNMAPPED_AREA
 109 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 110 #endif /* CONFIG_PPC_MM_SLICES */
 111
 112 /* No separate kernel read-only */
 113 #define _PAGE_KERNEL_RW         (_PAGE_RW | _PAGE_DIRTY) /* user access blocked by key */
 114 #define _PAGE_KERNEL_RO          _PAGE_KERNEL_RW
 115 #define _PAGE_KERNEL_RWX        (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
 116
 117 /* Strong Access Ordering */
 118 #define _PAGE_SAO               (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT)
 119
 120 /* No page size encoding in the linux PTE */
 121 #define _PAGE_PSIZE             0
 122
 123 /* PTEIDX nibble */
 124 #define _PTEIDX_SECONDARY       0x8
 125 #define _PTEIDX_GROUP_IX        0x7
 126
 127 /* Hash table based platforms need atomic updates of the linux PTE */
 128 #define PTE_ATOMIC_UPDATES      1
 129 #define _PTE_NONE_MASK  _PAGE_HPTEFLAGS
 130 /*
 131  * The mask convered by the RPN must be a ULL on 32-bit platforms with
 132  * 64-bit PTEs
 133  */
 134 #define PTE_RPN_MASK    (~((1UL << PTE_RPN_SHIFT) - 1))
 135 /*
 136  * _PAGE_CHG_MASK masks of bits that are to be preserved across
 137  * pgprot changes
 138  */
 139 #define _PAGE_CHG_MASK  (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
 140                          _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
 141                          _PAGE_SOFT_DIRTY)
 142 /*
 143  * Mask of bits returned by pte_pgprot()
 144  */
 145 #define PAGE_PROT_BITS  (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
 146                          _PAGE_WRITETHRU | _PAGE_4K_PFN | \
 147                          _PAGE_USER | _PAGE_ACCESSED |  \
 148                          _PAGE_RW |  _PAGE_DIRTY | _PAGE_EXEC | \
 149                          _PAGE_SOFT_DIRTY)
 150 /*
 151  * We define 2 sets of base prot bits, one for basic pages (ie,
 152  * cacheable kernel and user pages) and one for non cacheable
 153  * pages. We always set _PAGE_COHERENT when SMP is enabled or
 154  * the processor might need it for DMA coherency.
 155  */
 156 #define _PAGE_BASE_NC   (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
 157 #define _PAGE_BASE      (_PAGE_BASE_NC | _PAGE_COHERENT)
 158
 159 /* Permission masks used to generate the __P and __S table,
 160  *
 161  * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
 162  *
 163  * Write permissions imply read permissions for now (we could make write-only
 164  * pages on BookE but we don't bother for now). Execute permission control is
 165  * possible on platforms that define _PAGE_EXEC
 166  *
 167  * Note due to the way vm flags are laid out, the bits are XWR
 168  */
 169 #define PAGE_NONE       __pgprot(_PAGE_BASE)
 170 #define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
 171 #define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | \
 172                                  _PAGE_EXEC)
 173 #define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER )
 174 #define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 175 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER )
 176 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 177
 178 #define __P000  PAGE_NONE
 179 #define __P001  PAGE_READONLY
 180 #define __P010  PAGE_COPY
 181 #define __P011  PAGE_COPY
 182 #define __P100  PAGE_READONLY_X
 183 #define __P101  PAGE_READONLY_X
 184 #define __P110  PAGE_COPY_X
 185 #define __P111  PAGE_COPY_X
 186
 187 #define __S000  PAGE_NONE
 188 #define __S001  PAGE_READONLY
 189 #define __S010  PAGE_SHARED
 190 #define __S011  PAGE_SHARED
 191 #define __S100  PAGE_READONLY_X
 192 #define __S101  PAGE_READONLY_X
 193 #define __S110  PAGE_SHARED_X
 194 #define __S111  PAGE_SHARED_X
 195
 196 /* Permission masks used for kernel mappings */
 197 #define PAGE_KERNEL     __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
 198 #define PAGE_KERNEL_NC  __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
 199                                  _PAGE_NO_CACHE)
 200 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
 201                                  _PAGE_NO_CACHE | _PAGE_GUARDED)
 202 #define PAGE_KERNEL_X   __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
 203 #define PAGE_KERNEL_RO  __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
 204 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
 205
 206 /* Protection used for kernel text. We want the debuggers to be able to
 207  * set breakpoints anywhere, so don't write protect the kernel text
 208  * on platforms where such control is possible.
 209  */
 210 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
 211         defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
 212 #define PAGE_KERNEL_TEXT        PAGE_KERNEL_X
 213 #else
 214 #define PAGE_KERNEL_TEXT        PAGE_KERNEL_ROX
 215 #endif
 216
 217 /* Make modules code happy. We don't set RO yet */
 218 #define PAGE_KERNEL_EXEC        PAGE_KERNEL_X
 219 #define PAGE_AGP                (PAGE_KERNEL_NC)
 220
 221 #define PMD_BAD_BITS            (PTE_TABLE_SIZE-1)
 222 #define PUD_BAD_BITS            (PMD_TABLE_SIZE-1)
 223
 224 #ifndef __ASSEMBLY__
 225 #define pmd_bad(pmd)            (!is_kernel_addr(pmd_val(pmd)) \
 226                                  || (pmd_val(pmd) & PMD_BAD_BITS))
 227 #define pmd_page_vaddr(pmd)     (pmd_val(pmd) & ~PMD_MASKED_BITS)
 228
 229 #define pud_bad(pud)            (!is_kernel_addr(pud_val(pud)) \
 230                                  || (pud_val(pud) & PUD_BAD_BITS))
 231 #define pud_page_vaddr(pud)     (pud_val(pud) & ~PUD_MASKED_BITS)
 232
 233 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
 234 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
 235 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
 236
 237 extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
 238                             pte_t *ptep, unsigned long pte, int huge);
 239 extern unsigned long htab_convert_pte_flags(unsigned long pteflags);
 240 /* Atomic PTE updates */
 241 static inline unsigned long pte_update(struct mm_struct *mm,
 242                                        unsigned long addr,
 243                                        pte_t *ptep, unsigned long clr,
 244                                        unsigned long set,
 245                                        int huge)
 246 {
 247         unsigned long old, tmp;
 248
 249         __asm__ __volatile__(
 250         "1:     ldarx   %0,0,%3         # pte_update\n\
 251         andi.   %1,%0,%6\n\
 252         bne-    1b \n\
 253         andc    %1,%0,%4 \n\
 254         or      %1,%1,%7\n\
 255         stdcx.  %1,0,%3 \n\
 256         bne-    1b"
 257         : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
 258         : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY), "r" (set)
 259         : "cc" );
 260         /* huge pages use the old page table lock */
 261         if (!huge)
 262                 assert_pte_locked(mm, addr);
 263
 264         if (old & _PAGE_HASHPTE)
 265                 hpte_need_flush(mm, addr, ptep, old, huge);
 266
 267         return old;
 268 }
 269
 270 static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
 271                                               unsigned long addr, pte_t *ptep)
 272 {
 273         unsigned long old;
 274
 275         if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
 276                 return 0;
 277         old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
 278         return (old & _PAGE_ACCESSED) != 0;
 279 }
 280 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 281 #define ptep_test_and_clear_young(__vma, __addr, __ptep)                   \
 282 ({                                                                         \
 283         int __r;                                                           \
 284         __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
 285         __r;                                                               \
 286 })
 287
 288 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 289 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 290                                       pte_t *ptep)
 291 {
 292
 293         if ((pte_val(*ptep) & _PAGE_RW) == 0)
 294                 return;
 295
 296         pte_update(mm, addr, ptep, _PAGE_RW, 0, 0);
 297 }
 298
 299 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
 300                                            unsigned long addr, pte_t *ptep)
 301 {
 302         if ((pte_val(*ptep) & _PAGE_RW) == 0)
 303                 return;
 304
 305         pte_update(mm, addr, ptep, _PAGE_RW, 0, 1);
 306 }
 307
 308 /*
 309  * We currently remove entries from the hashtable regardless of whether
 310  * the entry was young or dirty. The generic routines only flush if the
 311  * entry was young or dirty which is not good enough.
 312  *
 313  * We should be more intelligent about this but for the moment we override
 314  * these functions and force a tlb flush unconditionally
 315  */
 316 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
 317 #define ptep_clear_flush_young(__vma, __address, __ptep)                \
 318 ({                                                                      \
 319         int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
 320                                                   __ptep);              \
 321         __young;                                                        \
 322 })
 323
 324 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 325 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
 326                                        unsigned long addr, pte_t *ptep)
 327 {
 328         unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
 329         return __pte(old);
 330 }
 331
 332 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
 333                              pte_t * ptep)
 334 {
 335         pte_update(mm, addr, ptep, ~0UL, 0, 0);
 336 }
 337
 338
 339 /* Set the dirty and/or accessed bits atomically in a linux PTE, this
 340  * function doesn't need to flush the hash entry
 341  */
 342 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
 343 {
 344         unsigned long bits = pte_val(entry) &
 345                 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC |
 346                  _PAGE_SOFT_DIRTY);
 347
 348         unsigned long old, tmp;
 349
 350         __asm__ __volatile__(
 351         "1:     ldarx   %0,0,%4\n\
 352                 andi.   %1,%0,%6\n\
 353                 bne-    1b \n\
 354                 or      %0,%3,%0\n\
 355                 stdcx.  %0,0,%4\n\
 356                 bne-    1b"
 357         :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
 358         :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
 359         :"cc");
 360 }
 361
 362 #define __HAVE_ARCH_PTE_SAME
 363 #define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
 364
 365 /* Generic accessors to PTE bits */
 366 static inline int pte_write(pte_t pte)          { return !!(pte_val(pte) & _PAGE_RW);}
 367 static inline int pte_dirty(pte_t pte)          { return !!(pte_val(pte) & _PAGE_DIRTY); }
 368 static inline int pte_young(pte_t pte)          { return !!(pte_val(pte) & _PAGE_ACCESSED); }
 369 static inline int pte_special(pte_t pte)        { return !!(pte_val(pte) & _PAGE_SPECIAL); }
 370 static inline int pte_none(pte_t pte)           { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
 371 static inline pgprot_t pte_pgprot(pte_t pte)    { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
 372
 373 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
 374 static inline bool pte_soft_dirty(pte_t pte)
 375 {
 376         return !!(pte_val(pte) & _PAGE_SOFT_DIRTY);
 377 }
 378 static inline pte_t pte_mksoft_dirty(pte_t pte)
 379 {
 380         return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
 381 }
 382
 383 static inline pte_t pte_clear_soft_dirty(pte_t pte)
 384 {
 385         return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
 386 }
 387 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
 388
 389 #ifdef CONFIG_NUMA_BALANCING
 390 /*
 391  * These work without NUMA balancing but the kernel does not care. See the
 392  * comment in include/asm-generic/pgtable.h . On powerpc, this will only
 393  * work for user pages and always return true for kernel pages.
 394  */
 395 static inline int pte_protnone(pte_t pte)
 396 {
 397         return (pte_val(pte) &
 398                 (_PAGE_PRESENT | _PAGE_USER)) == _PAGE_PRESENT;
 399 }
 400 #endif /* CONFIG_NUMA_BALANCING */
 401
 402 static inline int pte_present(pte_t pte)
 403 {
 404         return pte_val(pte) & _PAGE_PRESENT;
 405 }
 406
 407 /* Conversion functions: convert a page and protection to a page entry,
 408  * and a page entry and page directory to the page they refer to.
 409  *
 410  * Even if PTEs can be unsigned long long, a PFN is always an unsigned
 411  * long for now.
 412  */
 413 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
 414 {
 415         return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
 416                      pgprot_val(pgprot));
 417 }
 418
 419 static inline unsigned long pte_pfn(pte_t pte)
 420 {
 421         return pte_val(pte) >> PTE_RPN_SHIFT;
 422 }
 423
 424 /* Generic modifiers for PTE bits */
 425 static inline pte_t pte_wrprotect(pte_t pte)
 426 {
 427         return __pte(pte_val(pte) & ~_PAGE_RW);
 428 }
 429
 430 static inline pte_t pte_mkclean(pte_t pte)
 431 {
 432         return __pte(pte_val(pte) & ~_PAGE_DIRTY);
 433 }
 434
 435 static inline pte_t pte_mkold(pte_t pte)
 436 {
 437         return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
 438 }
 439
 440 static inline pte_t pte_mkwrite(pte_t pte)
 441 {
 442         return __pte(pte_val(pte) | _PAGE_RW);
 443 }
 444
 445 static inline pte_t pte_mkdirty(pte_t pte)
 446 {
 447         return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
 448 }
 449
 450 static inline pte_t pte_mkyoung(pte_t pte)
 451 {
 452         return __pte(pte_val(pte) | _PAGE_ACCESSED);
 453 }
 454
 455 static inline pte_t pte_mkspecial(pte_t pte)
 456 {
 457         return __pte(pte_val(pte) | _PAGE_SPECIAL);
 458 }
 459
 460 static inline pte_t pte_mkhuge(pte_t pte)
 461 {
 462         return pte;
 463 }
 464
 465 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 466 {
 467         return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
 468 }
 469
 470 /* This low level function performs the actual PTE insertion
 471  * Setting the PTE depends on the MMU type and other factors. It's
 472  * an horrible mess that I'm not going to try to clean up now but
 473  * I'm keeping it in one place rather than spread around
 474  */
 475 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
 476                                 pte_t *ptep, pte_t pte, int percpu)
 477 {
 478         /*
 479          * Anything else just stores the PTE normally. That covers all 64-bit
 480          * cases, and 32-bit non-hash with 32-bit PTEs.
 481          */
 482         *ptep = pte;
 483 }
 484
 485 /*
 486  * Macro to mark a page protection value as "uncacheable".
 487  */
 488
 489 #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
 490                          _PAGE_WRITETHRU)
 491
 492 #define pgprot_noncached pgprot_noncached
 493 static inline pgprot_t pgprot_noncached(pgprot_t prot)
 494 {
 495         return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
 496                         _PAGE_NO_CACHE | _PAGE_GUARDED);
 497 }
 498
 499 #define pgprot_noncached_wc pgprot_noncached_wc
 500 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
 501 {
 502         return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
 503                         _PAGE_NO_CACHE);
 504 }
 505
 506 #define pgprot_cached pgprot_cached
 507 static inline pgprot_t pgprot_cached(pgprot_t prot)
 508 {
 509         return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
 510                         _PAGE_COHERENT);
 511 }
 512
 513 #define pgprot_cached_wthru pgprot_cached_wthru
 514 static inline pgprot_t pgprot_cached_wthru(pgprot_t prot)
 515 {
 516         return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
 517                         _PAGE_COHERENT | _PAGE_WRITETHRU);
 518 }
 519
 520 #define pgprot_cached_noncoherent pgprot_cached_noncoherent
 521 static inline pgprot_t pgprot_cached_noncoherent(pgprot_t prot)
 522 {
 523         return __pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL);
 524 }
 525
 526 #define pgprot_writecombine pgprot_writecombine
 527 static inline pgprot_t pgprot_writecombine(pgprot_t prot)
 528 {
 529         return pgprot_noncached_wc(prot);
 530 }
 531
 532 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 533 extern void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr,
 534                                    pmd_t *pmdp, unsigned long old_pmd);
 535 #else
 536 static inline void hpte_do_hugepage_flush(struct mm_struct *mm,
 537                                           unsigned long addr, pmd_t *pmdp,
 538                                           unsigned long old_pmd)
 539 {
 540         WARN(1, "%s called with THP disabled\n", __func__);
 541 }
 542 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 543
 544 #endif /* !__ASSEMBLY__ */
 545 #endif /* __KERNEL__ */
 546 #endif /* _ASM_POWERPC_BOOK3S_64_HASH_H */