arch/sparc/kernel/pci.c

   1 /* pci.c: UltraSparc PCI controller support.
   2  *
   3  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
   4  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   5  * Copyright (C) 1999 Jakub Jelinek   (jj@ultra.linux.cz)
   6  *
   7  * OF tree based PCI bus probing taken from the PowerPC port
   8  * with minor modifications, see there for credits.
   9  */
  10
  11 #include <linux/export.h>
  12 #include <linux/kernel.h>
  13 #include <linux/string.h>
  14 #include <linux/sched.h>
  15 #include <linux/capability.h>
  16 #include <linux/errno.h>
  17 #include <linux/pci.h>
  18 #include <linux/msi.h>
  19 #include <linux/irq.h>
  20 #include <linux/init.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23
  24 #include <asm/uaccess.h>
  25 #include <asm/pgtable.h>
  26 #include <asm/irq.h>
  27 #include <asm/prom.h>
  28 #include <asm/apb.h>
  29
  30 #include "pci_impl.h"
  31 #include "kernel.h"
  32
  33 /* List of all PCI controllers found in the system. */
  34 struct pci_pbm_info *pci_pbm_root = NULL;
  35
  36 /* Each PBM found gets a unique index. */
  37 int pci_num_pbms = 0;
  38
  39 volatile int pci_poke_in_progress;
  40 volatile int pci_poke_cpu = -1;
  41 volatile int pci_poke_faulted;
  42
  43 static DEFINE_SPINLOCK(pci_poke_lock);
  44
  45 void pci_config_read8(u8 *addr, u8 *ret)
  46 {
  47         unsigned long flags;
  48         u8 byte;
  49
  50         spin_lock_irqsave(&pci_poke_lock, flags);
  51         pci_poke_cpu = smp_processor_id();
  52         pci_poke_in_progress = 1;
  53         pci_poke_faulted = 0;
  54         __asm__ __volatile__("membar #Sync\n\t"
  55                              "lduba [%1] %2, %0\n\t"
  56                              "membar #Sync"
  57                              : "=r" (byte)
  58                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  59                              : "memory");
  60         pci_poke_in_progress = 0;
  61         pci_poke_cpu = -1;
  62         if (!pci_poke_faulted)
  63                 *ret = byte;
  64         spin_unlock_irqrestore(&pci_poke_lock, flags);
  65 }
  66
  67 void pci_config_read16(u16 *addr, u16 *ret)
  68 {
  69         unsigned long flags;
  70         u16 word;
  71
  72         spin_lock_irqsave(&pci_poke_lock, flags);
  73         pci_poke_cpu = smp_processor_id();
  74         pci_poke_in_progress = 1;
  75         pci_poke_faulted = 0;
  76         __asm__ __volatile__("membar #Sync\n\t"
  77                              "lduha [%1] %2, %0\n\t"
  78                              "membar #Sync"
  79                              : "=r" (word)
  80                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  81                              : "memory");
  82         pci_poke_in_progress = 0;
  83         pci_poke_cpu = -1;
  84         if (!pci_poke_faulted)
  85                 *ret = word;
  86         spin_unlock_irqrestore(&pci_poke_lock, flags);
  87 }
  88
  89 void pci_config_read32(u32 *addr, u32 *ret)
  90 {
  91         unsigned long flags;
  92         u32 dword;
  93
  94         spin_lock_irqsave(&pci_poke_lock, flags);
  95         pci_poke_cpu = smp_processor_id();
  96         pci_poke_in_progress = 1;
  97         pci_poke_faulted = 0;
  98         __asm__ __volatile__("membar #Sync\n\t"
  99                              "lduwa [%1] %2, %0\n\t"
 100                              "membar #Sync"
 101                              : "=r" (dword)
 102                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 103                              : "memory");
 104         pci_poke_in_progress = 0;
 105         pci_poke_cpu = -1;
 106         if (!pci_poke_faulted)
 107                 *ret = dword;
 108         spin_unlock_irqrestore(&pci_poke_lock, flags);
 109 }
 110
 111 void pci_config_write8(u8 *addr, u8 val)
 112 {
 113         unsigned long flags;
 114
 115         spin_lock_irqsave(&pci_poke_lock, flags);
 116         pci_poke_cpu = smp_processor_id();
 117         pci_poke_in_progress = 1;
 118         pci_poke_faulted = 0;
 119         __asm__ __volatile__("membar #Sync\n\t"
 120                              "stba %0, [%1] %2\n\t"
 121                              "membar #Sync"
 122                              : /* no outputs */
 123                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 124                              : "memory");
 125         pci_poke_in_progress = 0;
 126         pci_poke_cpu = -1;
 127         spin_unlock_irqrestore(&pci_poke_lock, flags);
 128 }
 129
 130 void pci_config_write16(u16 *addr, u16 val)
 131 {
 132         unsigned long flags;
 133
 134         spin_lock_irqsave(&pci_poke_lock, flags);
 135         pci_poke_cpu = smp_processor_id();
 136         pci_poke_in_progress = 1;
 137         pci_poke_faulted = 0;
 138         __asm__ __volatile__("membar #Sync\n\t"
 139                              "stha %0, [%1] %2\n\t"
 140                              "membar #Sync"
 141                              : /* no outputs */
 142                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 143                              : "memory");
 144         pci_poke_in_progress = 0;
 145         pci_poke_cpu = -1;
 146         spin_unlock_irqrestore(&pci_poke_lock, flags);
 147 }
 148
 149 void pci_config_write32(u32 *addr, u32 val)
 150 {
 151         unsigned long flags;
 152
 153         spin_lock_irqsave(&pci_poke_lock, flags);
 154         pci_poke_cpu = smp_processor_id();
 155         pci_poke_in_progress = 1;
 156         pci_poke_faulted = 0;
 157         __asm__ __volatile__("membar #Sync\n\t"
 158                              "stwa %0, [%1] %2\n\t"
 159                              "membar #Sync"
 160                              : /* no outputs */
 161                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 162                              : "memory");
 163         pci_poke_in_progress = 0;
 164         pci_poke_cpu = -1;
 165         spin_unlock_irqrestore(&pci_poke_lock, flags);
 166 }
 167
 168 static int ofpci_verbose;
 169
 170 static int __init ofpci_debug(char *str)
 171 {
 172         int val = 0;
 173
 174         get_option(&str, &val);
 175         if (val)
 176                 ofpci_verbose = 1;
 177         return 1;
 178 }
 179
 180 __setup("ofpci_debug=", ofpci_debug);
 181
 182 static unsigned long pci_parse_of_flags(u32 addr0)
 183 {
 184         unsigned long flags = 0;
 185
 186         if (addr0 & 0x02000000) {
 187                 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
 188                 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
 189                 if (addr0 & 0x01000000)
 190                         flags |= IORESOURCE_MEM_64
 191                                  | PCI_BASE_ADDRESS_MEM_TYPE_64;
 192                 if (addr0 & 0x40000000)
 193                         flags |= IORESOURCE_PREFETCH
 194                                  | PCI_BASE_ADDRESS_MEM_PREFETCH;
 195         } else if (addr0 & 0x01000000)
 196                 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
 197         return flags;
 198 }
 199
 200 /* The of_device layer has translated all of the assigned-address properties
 201  * into physical address resources, we only have to figure out the register
 202  * mapping.
 203  */
 204 static void pci_parse_of_addrs(struct platform_device *op,
 205                                struct device_node *node,
 206                                struct pci_dev *dev)
 207 {
 208         struct resource *op_res;
 209         const u32 *addrs;
 210         int proplen;
 211
 212         addrs = of_get_property(node, "assigned-addresses", &proplen);
 213         if (!addrs)
 214                 return;
 215         if (ofpci_verbose)
 216                 printk("    parse addresses (%d bytes) @ %p\n",
 217                        proplen, addrs);
 218         op_res = &op->resource[0];
 219         for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
 220                 struct resource *res;
 221                 unsigned long flags;
 222                 int i;
 223
 224                 flags = pci_parse_of_flags(addrs[0]);
 225                 if (!flags)
 226                         continue;
 227                 i = addrs[0] & 0xff;
 228                 if (ofpci_verbose)
 229                         printk("  start: %llx, end: %llx, i: %x\n",
 230                                op_res->start, op_res->end, i);
 231
 232                 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
 233                         res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
 234                 } else if (i == dev->rom_base_reg) {
 235                         res = &dev->resource[PCI_ROM_RESOURCE];
 236                         flags |= IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
 237                 } else {
 238                         printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
 239                         continue;
 240                 }
 241                 res->start = op_res->start;
 242                 res->end = op_res->end;
 243                 res->flags = flags;
 244                 res->name = pci_name(dev);
 245         }
 246 }
 247
 248 static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu,
 249                                   void *stc, void *host_controller,
 250                                   struct platform_device  *op,
 251                                   int numa_node)
 252 {
 253         sd->iommu = iommu;
 254         sd->stc = stc;
 255         sd->host_controller = host_controller;
 256         sd->op = op;
 257         sd->numa_node = numa_node;
 258 }
 259
 260 static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
 261                                          struct device_node *node,
 262                                          struct pci_bus *bus, int devfn)
 263 {
 264         struct dev_archdata *sd;
 265         struct platform_device *op;
 266         struct pci_dev *dev;
 267         const char *type;
 268         u32 class;
 269
 270         dev = pci_alloc_dev(bus);
 271         if (!dev)
 272                 return NULL;
 273
 274         op = of_find_device_by_node(node);
 275         sd = &dev->dev.archdata;
 276         pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op,
 277                               pbm->numa_node);
 278         sd = &op->dev.archdata;
 279         sd->iommu = pbm->iommu;
 280         sd->stc = &pbm->stc;
 281         sd->numa_node = pbm->numa_node;
 282
 283         if (!strcmp(node->name, "ebus"))
 284                 of_propagate_archdata(op);
 285
 286         type = of_get_property(node, "device_type", NULL);
 287         if (type == NULL)
 288                 type = "";
 289
 290         if (ofpci_verbose)
 291                 printk("    create device, devfn: %x, type: %s\n",
 292                        devfn, type);
 293
 294         dev->sysdata = node;
 295         dev->dev.parent = bus->bridge;
 296         dev->dev.bus = &pci_bus_type;
 297         dev->dev.of_node = of_node_get(node);
 298         dev->devfn = devfn;
 299         dev->multifunction = 0;         /* maybe a lie? */
 300         set_pcie_port_type(dev);
 301
 302         pci_dev_assign_slot(dev);
 303         dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
 304         dev->device = of_getintprop_default(node, "device-id", 0xffff);
 305         dev->subsystem_vendor =
 306                 of_getintprop_default(node, "subsystem-vendor-id", 0);
 307         dev->subsystem_device =
 308                 of_getintprop_default(node, "subsystem-id", 0);
 309
 310         dev->cfg_size = pci_cfg_space_size(dev);
 311
 312         /* We can't actually use the firmware value, we have
 313          * to read what is in the register right now.  One
 314          * reason is that in the case of IDE interfaces the
 315          * firmware can sample the value before the the IDE
 316          * interface is programmed into native mode.
 317          */
 318         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
 319         dev->class = class >> 8;
 320         dev->revision = class & 0xff;
 321
 322         dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
 323                 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
 324
 325         if (ofpci_verbose)
 326                 printk("    class: 0x%x device name: %s\n",
 327                        dev->class, pci_name(dev));
 328
 329         /* I have seen IDE devices which will not respond to
 330          * the bmdma simplex check reads if bus mastering is
 331          * disabled.
 332          */
 333         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 334                 pci_set_master(dev);
 335
 336         dev->current_state = PCI_UNKNOWN;       /* unknown power state */
 337         dev->error_state = pci_channel_io_normal;
 338         dev->dma_mask = 0xffffffff;
 339
 340         if (!strcmp(node->name, "pci")) {
 341                 /* a PCI-PCI bridge */
 342                 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
 343                 dev->rom_base_reg = PCI_ROM_ADDRESS1;
 344         } else if (!strcmp(type, "cardbus")) {
 345                 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
 346         } else {
 347                 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
 348                 dev->rom_base_reg = PCI_ROM_ADDRESS;
 349
 350                 dev->irq = sd->op->archdata.irqs[0];
 351                 if (dev->irq == 0xffffffff)
 352                         dev->irq = PCI_IRQ_NONE;
 353         }
 354
 355         pci_parse_of_addrs(sd->op, node, dev);
 356
 357         if (ofpci_verbose)
 358                 printk("    adding to system ...\n");
 359
 360         pci_device_add(dev, bus);
 361
 362         return dev;
 363 }
 364
 365 static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
 366 {
 367         u32 idx, first, last;
 368
 369         first = 8;
 370         last = 0;
 371         for (idx = 0; idx < 8; idx++) {
 372                 if ((map & (1 << idx)) != 0) {
 373                         if (first > idx)
 374                                 first = idx;
 375                         if (last < idx)
 376                                 last = idx;
 377                 }
 378         }
 379
 380         *first_p = first;
 381         *last_p = last;
 382 }
 383
 384 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
 385  * a proper 'ranges' property.
 386  */
 387 static void apb_fake_ranges(struct pci_dev *dev,
 388                             struct pci_bus *bus,
 389                             struct pci_pbm_info *pbm)
 390 {
 391         struct pci_bus_region region;
 392         struct resource *res;
 393         u32 first, last;
 394         u8 map;
 395
 396         pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
 397         apb_calc_first_last(map, &first, &last);
 398         res = bus->resource[0];
 399         res->flags = IORESOURCE_IO;
 400         region.start = (first << 21);
 401         region.end = (last << 21) + ((1 << 21) - 1);
 402         pcibios_bus_to_resource(dev->bus, res, &region);
 403
 404         pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
 405         apb_calc_first_last(map, &first, &last);
 406         res = bus->resource[1];
 407         res->flags = IORESOURCE_MEM;
 408         region.start = (first << 29);
 409         region.end = (last << 29) + ((1 << 29) - 1);
 410         pcibios_bus_to_resource(dev->bus, res, &region);
 411 }
 412
 413 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
 414                             struct device_node *node,
 415                             struct pci_bus *bus);
 416
 417 #define GET_64BIT(prop, i)      ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
 418
 419 static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
 420                                struct device_node *node,
 421                                struct pci_dev *dev)
 422 {
 423         struct pci_bus *bus;
 424         const u32 *busrange, *ranges;
 425         int len, i, simba;
 426         struct pci_bus_region region;
 427         struct resource *res;
 428         unsigned int flags;
 429         u64 size;
 430
 431         if (ofpci_verbose)
 432                 printk("of_scan_pci_bridge(%s)\n", node->full_name);
 433
 434         /* parse bus-range property */
 435         busrange = of_get_property(node, "bus-range", &len);
 436         if (busrange == NULL || len != 8) {
 437                 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
 438                        node->full_name);
 439                 return;
 440         }
 441
 442         if (ofpci_verbose)
 443                 printk("    Bridge bus range [%u --> %u]\n",
 444                        busrange[0], busrange[1]);
 445
 446         ranges = of_get_property(node, "ranges", &len);
 447         simba = 0;
 448         if (ranges == NULL) {
 449                 const char *model = of_get_property(node, "model", NULL);
 450                 if (model && !strcmp(model, "SUNW,simba"))
 451                         simba = 1;
 452         }
 453
 454         bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
 455         if (!bus) {
 456                 printk(KERN_ERR "Failed to create pci bus for %s\n",
 457                        node->full_name);
 458                 return;
 459         }
 460
 461         bus->primary = dev->bus->number;
 462         pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
 463         bus->bridge_ctl = 0;
 464
 465         if (ofpci_verbose)
 466                 printk("    Bridge ranges[%p] simba[%d]\n",
 467                        ranges, simba);
 468
 469         /* parse ranges property, or cook one up by hand for Simba */
 470         /* PCI #address-cells == 3 and #size-cells == 2 always */
 471         res = &dev->resource[PCI_BRIDGE_RESOURCES];
 472         for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
 473                 res->flags = 0;
 474                 bus->resource[i] = res;
 475                 ++res;
 476         }
 477         if (simba) {
 478                 apb_fake_ranges(dev, bus, pbm);
 479                 goto after_ranges;
 480         } else if (ranges == NULL) {
 481                 pci_read_bridge_bases(bus);
 482                 goto after_ranges;
 483         }
 484         i = 1;
 485         for (; len >= 32; len -= 32, ranges += 8) {
 486                 u64 start;
 487
 488                 if (ofpci_verbose)
 489                         printk("    RAW Range[%08x:%08x:%08x:%08x:%08x:%08x:"
 490                                "%08x:%08x]\n",
 491                                ranges[0], ranges[1], ranges[2], ranges[3],
 492                                ranges[4], ranges[5], ranges[6], ranges[7]);
 493
 494                 flags = pci_parse_of_flags(ranges[0]);
 495                 size = GET_64BIT(ranges, 6);
 496                 if (flags == 0 || size == 0)
 497                         continue;
 498
 499                 /* On PCI-Express systems, PCI bridges that have no devices downstream
 500                  * have a bogus size value where the first 32-bit cell is 0xffffffff.
 501                  * This results in a bogus range where start + size overflows.
 502                  *
 503                  * Just skip these otherwise the kernel will complain when the resource
 504                  * tries to be claimed.
 505                  */
 506                 if (size >> 32 == 0xffffffff)
 507                         continue;
 508
 509                 if (flags & IORESOURCE_IO) {
 510                         res = bus->resource[0];
 511                         if (res->flags) {
 512                                 printk(KERN_ERR "PCI: ignoring extra I/O range"
 513                                        " for bridge %s\n", node->full_name);
 514                                 continue;
 515                         }
 516                 } else {
 517                         if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
 518                                 printk(KERN_ERR "PCI: too many memory ranges"
 519                                        " for bridge %s\n", node->full_name);
 520                                 continue;
 521                         }
 522                         res = bus->resource[i];
 523                         ++i;
 524                 }
 525
 526                 res->flags = flags;
 527                 region.start = start = GET_64BIT(ranges, 1);
 528                 region.end = region.start + size - 1;
 529
 530                 if (ofpci_verbose)
 531                         printk("      Using flags[%08x] start[%016llx] size[%016llx]\n",
 532                                flags, start, size);
 533
 534                 pcibios_bus_to_resource(dev->bus, res, &region);
 535         }
 536 after_ranges:
 537         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
 538                 bus->number);
 539         if (ofpci_verbose)
 540                 printk("    bus name: %s\n", bus->name);
 541
 542         pci_of_scan_bus(pbm, node, bus);
 543 }
 544
 545 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
 546                             struct device_node *node,
 547                             struct pci_bus *bus)
 548 {
 549         struct device_node *child;
 550         const u32 *reg;
 551         int reglen, devfn, prev_devfn;
 552         struct pci_dev *dev;
 553
 554         if (ofpci_verbose)
 555                 printk("PCI: scan_bus[%s] bus no %d\n",
 556                        node->full_name, bus->number);
 557
 558         child = NULL;
 559         prev_devfn = -1;
 560         while ((child = of_get_next_child(node, child)) != NULL) {
 561                 if (ofpci_verbose)
 562                         printk("  * %s\n", child->full_name);
 563                 reg = of_get_property(child, "reg", &reglen);
 564                 if (reg == NULL || reglen < 20)
 565                         continue;
 566
 567                 devfn = (reg[0] >> 8) & 0xff;
 568
 569                 /* This is a workaround for some device trees
 570                  * which list PCI devices twice.  On the V100
 571                  * for example, device number 3 is listed twice.
 572                  * Once as "pm" and once again as "lomp".
 573                  */
 574                 if (devfn == prev_devfn)
 575                         continue;
 576                 prev_devfn = devfn;
 577
 578                 /* create a new pci_dev for this device */
 579                 dev = of_create_pci_dev(pbm, child, bus, devfn);
 580                 if (!dev)
 581                         continue;
 582                 if (ofpci_verbose)
 583                         printk("PCI: dev header type: %x\n",
 584                                dev->hdr_type);
 585
 586                 if (pci_is_bridge(dev))
 587                         of_scan_pci_bridge(pbm, child, dev);
 588         }
 589 }
 590
 591 static ssize_t
 592 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
 593 {
 594         struct pci_dev *pdev;
 595         struct device_node *dp;
 596
 597         pdev = to_pci_dev(dev);
 598         dp = pdev->dev.of_node;
 599
 600         return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
 601 }
 602
 603 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
 604
 605 static void pci_bus_register_of_sysfs(struct pci_bus *bus)
 606 {
 607         struct pci_dev *dev;
 608         struct pci_bus *child_bus;
 609         int err;
 610
 611         list_for_each_entry(dev, &bus->devices, bus_list) {
 612                 /* we don't really care if we can create this file or
 613                  * not, but we need to assign the result of the call
 614                  * or the world will fall under alien invasion and
 615                  * everybody will be frozen on a spaceship ready to be
 616                  * eaten on alpha centauri by some green and jelly
 617                  * humanoid.
 618                  */
 619                 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
 620                 (void) err;
 621         }
 622         list_for_each_entry(child_bus, &bus->children, node)
 623                 pci_bus_register_of_sysfs(child_bus);
 624 }
 625
 626 static void pci_claim_bus_resources(struct pci_bus *bus)
 627 {
 628         struct pci_bus *child_bus;
 629         struct pci_dev *dev;
 630
 631         list_for_each_entry(dev, &bus->devices, bus_list) {
 632                 int i;
 633
 634                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 635                         struct resource *r = &dev->resource[i];
 636
 637                         if (r->parent || !r->start || !r->flags)
 638                                 continue;
 639
 640                         if (ofpci_verbose)
 641                                 printk("PCI: Claiming %s: "
 642                                        "Resource %d: %016llx..%016llx [%x]\n",
 643                                        pci_name(dev), i,
 644                                        (unsigned long long)r->start,
 645                                        (unsigned long long)r->end,
 646                                        (unsigned int)r->flags);
 647
 648                         pci_claim_resource(dev, i);
 649                 }
 650         }
 651
 652         list_for_each_entry(child_bus, &bus->children, node)
 653                 pci_claim_bus_resources(child_bus);
 654 }
 655
 656 struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
 657                                  struct device *parent)
 658 {
 659         LIST_HEAD(resources);
 660         struct device_node *node = pbm->op->dev.of_node;
 661         struct pci_bus *bus;
 662
 663         printk("PCI: Scanning PBM %s\n", node->full_name);
 664
 665         pci_add_resource_offset(&resources, &pbm->io_space,
 666                                 pbm->io_space.start);
 667         pci_add_resource_offset(&resources, &pbm->mem_space,
 668                                 pbm->mem_space.start);
 669         if (pbm->mem64_space.flags)
 670                 pci_add_resource_offset(&resources, &pbm->mem64_space,
 671                                         pbm->mem_space.start);
 672         pbm->busn.start = pbm->pci_first_busno;
 673         pbm->busn.end   = pbm->pci_last_busno;
 674         pbm->busn.flags = IORESOURCE_BUS;
 675         pci_add_resource(&resources, &pbm->busn);
 676         bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
 677                                   pbm, &resources);
 678         if (!bus) {
 679                 printk(KERN_ERR "Failed to create bus for %s\n",
 680                        node->full_name);
 681                 pci_free_resource_list(&resources);
 682                 return NULL;
 683         }
 684
 685         pci_of_scan_bus(pbm, node, bus);
 686         pci_bus_register_of_sysfs(bus);
 687
 688         pci_claim_bus_resources(bus);
 689         pci_bus_add_devices(bus);
 690         return bus;
 691 }
 692
 693 void pcibios_fixup_bus(struct pci_bus *pbus)
 694 {
 695 }
 696
 697 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
 698                                 resource_size_t size, resource_size_t align)
 699 {
 700         return res->start;
 701 }
 702
 703 int pcibios_enable_device(struct pci_dev *dev, int mask)
 704 {
 705         u16 cmd, oldcmd;
 706         int i;
 707
 708         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 709         oldcmd = cmd;
 710
 711         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 712                 struct resource *res = &dev->resource[i];
 713
 714                 /* Only set up the requested stuff */
 715                 if (!(mask & (1<<i)))
 716                         continue;
 717
 718                 if (res->flags & IORESOURCE_IO)
 719                         cmd |= PCI_COMMAND_IO;
 720                 if (res->flags & IORESOURCE_MEM)
 721                         cmd |= PCI_COMMAND_MEMORY;
 722         }
 723
 724         if (cmd != oldcmd) {
 725                 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
 726                        pci_name(dev), cmd);
 727                 /* Enable the appropriate bits in the PCI command register.  */
 728                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 729         }
 730         return 0;
 731 }
 732
 733 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
 734
 735 /* If the user uses a host-bridge as the PCI device, he may use
 736  * this to perform a raw mmap() of the I/O or MEM space behind
 737  * that controller.
 738  *
 739  * This can be useful for execution of x86 PCI bios initialization code
 740  * on a PCI card, like the xfree86 int10 stuff does.
 741  */
 742 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
 743                                       enum pci_mmap_state mmap_state)
 744 {
 745         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
 746         unsigned long space_size, user_offset, user_size;
 747
 748         if (mmap_state == pci_mmap_io) {
 749                 space_size = resource_size(&pbm->io_space);
 750         } else {
 751                 space_size = resource_size(&pbm->mem_space);
 752         }
 753
 754         /* Make sure the request is in range. */
 755         user_offset = vma->vm_pgoff << PAGE_SHIFT;
 756         user_size = vma->vm_end - vma->vm_start;
 757
 758         if (user_offset >= space_size ||
 759             (user_offset + user_size) > space_size)
 760                 return -EINVAL;
 761
 762         if (mmap_state == pci_mmap_io) {
 763                 vma->vm_pgoff = (pbm->io_space.start +
 764                                  user_offset) >> PAGE_SHIFT;
 765         } else {
 766                 vma->vm_pgoff = (pbm->mem_space.start +
 767                                  user_offset) >> PAGE_SHIFT;
 768         }
 769
 770         return 0;
 771 }
 772
 773 /* Adjust vm_pgoff of VMA such that it is the physical page offset
 774  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
 775  *
 776  * Basically, the user finds the base address for his device which he wishes
 777  * to mmap.  They read the 32-bit value from the config space base register,
 778  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
 779  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
 780  *
 781  * Returns negative error code on failure, zero on success.
 782  */
 783 static int __pci_mmap_make_offset(struct pci_dev *pdev,
 784                                   struct vm_area_struct *vma,
 785                                   enum pci_mmap_state mmap_state)
 786 {
 787         unsigned long user_paddr, user_size;
 788         int i, err;
 789
 790         /* First compute the physical address in vma->vm_pgoff,
 791          * making sure the user offset is within range in the
 792          * appropriate PCI space.
 793          */
 794         err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
 795         if (err)
 796                 return err;
 797
 798         /* If this is a mapping on a host bridge, any address
 799          * is OK.
 800          */
 801         if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
 802                 return err;
 803
 804         /* Otherwise make sure it's in the range for one of the
 805          * device's resources.
 806          */
 807         user_paddr = vma->vm_pgoff << PAGE_SHIFT;
 808         user_size = vma->vm_end - vma->vm_start;
 809
 810         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 811                 struct resource *rp = &pdev->resource[i];
 812                 resource_size_t aligned_end;
 813
 814                 /* Active? */
 815                 if (!rp->flags)
 816                         continue;
 817
 818                 /* Same type? */
 819                 if (i == PCI_ROM_RESOURCE) {
 820                         if (mmap_state != pci_mmap_mem)
 821                                 continue;
 822                 } else {
 823                         if ((mmap_state == pci_mmap_io &&
 824                              (rp->flags & IORESOURCE_IO) == 0) ||
 825                             (mmap_state == pci_mmap_mem &&
 826                              (rp->flags & IORESOURCE_MEM) == 0))
 827                                 continue;
 828                 }
 829
 830                 /* Align the resource end to the next page address.
 831                  * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
 832                  * because actually we need the address of the next byte
 833                  * after rp->end.
 834                  */
 835                 aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK;
 836
 837                 if ((rp->start <= user_paddr) &&
 838                     (user_paddr + user_size) <= aligned_end)
 839                         break;
 840         }
 841
 842         if (i > PCI_ROM_RESOURCE)
 843                 return -EINVAL;
 844
 845         return 0;
 846 }
 847
 848 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
 849  * device mapping.
 850  */
 851 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
 852                                              enum pci_mmap_state mmap_state)
 853 {
 854         /* Our io_remap_pfn_range takes care of this, do nothing.  */
 855 }
 856
 857 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
 858  * for this architecture.  The region in the process to map is described by vm_start
 859  * and vm_end members of VMA, the base physical address is found in vm_pgoff.
 860  * The pci device structure is provided so that architectures may make mapping
 861  * decisions on a per-device or per-bus basis.
 862  *
 863  * Returns a negative error code on failure, zero on success.
 864  */
 865 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 866                         enum pci_mmap_state mmap_state,
 867                         int write_combine)
 868 {
 869         int ret;
 870
 871         ret = __pci_mmap_make_offset(dev, vma, mmap_state);
 872         if (ret < 0)
 873                 return ret;
 874
 875         __pci_mmap_set_pgprot(dev, vma, mmap_state);
 876
 877         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 878         ret = io_remap_pfn_range(vma, vma->vm_start,
 879                                  vma->vm_pgoff,
 880                                  vma->vm_end - vma->vm_start,
 881                                  vma->vm_page_prot);
 882         if (ret)
 883                 return ret;
 884
 885         return 0;
 886 }
 887
 888 #ifdef CONFIG_NUMA
 889 int pcibus_to_node(struct pci_bus *pbus)
 890 {
 891         struct pci_pbm_info *pbm = pbus->sysdata;
 892
 893         return pbm->numa_node;
 894 }
 895 EXPORT_SYMBOL(pcibus_to_node);
 896 #endif
 897
 898 /* Return the domain number for this pci bus */
 899
 900 int pci_domain_nr(struct pci_bus *pbus)
 901 {
 902         struct pci_pbm_info *pbm = pbus->sysdata;
 903         int ret;
 904
 905         if (!pbm) {
 906                 ret = -ENXIO;
 907         } else {
 908                 ret = pbm->index;
 909         }
 910
 911         return ret;
 912 }
 913 EXPORT_SYMBOL(pci_domain_nr);
 914
 915 #ifdef CONFIG_PCI_MSI
 916 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
 917 {
 918         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
 919         unsigned int irq;
 920
 921         if (!pbm->setup_msi_irq)
 922                 return -EINVAL;
 923
 924         return pbm->setup_msi_irq(&irq, pdev, desc);
 925 }
 926
 927 void arch_teardown_msi_irq(unsigned int irq)
 928 {
 929         struct msi_desc *entry = irq_get_msi_desc(irq);
 930         struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
 931         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
 932
 933         if (pbm->teardown_msi_irq)
 934                 pbm->teardown_msi_irq(irq, pdev);
 935 }
 936 #endif /* !(CONFIG_PCI_MSI) */
 937
 938 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
 939 {
 940         struct pci_dev *ali_isa_bridge;
 941         u8 val;
 942
 943         /* ALI sound chips generate 31-bits of DMA, a special register
 944          * determines what bit 31 is emitted as.
 945          */
 946         ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
 947                                          PCI_DEVICE_ID_AL_M1533,
 948                                          NULL);
 949
 950         pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
 951         if (set_bit)
 952                 val |= 0x01;
 953         else
 954                 val &= ~0x01;
 955         pci_write_config_byte(ali_isa_bridge, 0x7e, val);
 956         pci_dev_put(ali_isa_bridge);
 957 }
 958
 959 int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask)
 960 {
 961         u64 dma_addr_mask;
 962
 963         if (pdev == NULL) {
 964                 dma_addr_mask = 0xffffffff;
 965         } else {
 966                 struct iommu *iommu = pdev->dev.archdata.iommu;
 967
 968                 dma_addr_mask = iommu->dma_addr_mask;
 969
 970                 if (pdev->vendor == PCI_VENDOR_ID_AL &&
 971                     pdev->device == PCI_DEVICE_ID_AL_M5451 &&
 972                     device_mask == 0x7fffffff) {
 973                         ali_sound_dma_hack(pdev,
 974                                            (dma_addr_mask & 0x80000000) != 0);
 975                         return 1;
 976                 }
 977         }
 978
 979         if (device_mask >= (1UL << 32UL))
 980                 return 0;
 981
 982         return (device_mask & dma_addr_mask) == dma_addr_mask;
 983 }
 984
 985 void pci_resource_to_user(const struct pci_dev *pdev, int bar,
 986                           const struct resource *rp, resource_size_t *start,
 987                           resource_size_t *end)
 988 {
 989         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
 990         unsigned long offset;
 991
 992         if (rp->flags & IORESOURCE_IO)
 993                 offset = pbm->io_space.start;
 994         else
 995                 offset = pbm->mem_space.start;
 996
 997         *start = rp->start - offset;
 998         *end = rp->end - offset;
 999 }
1000
1001 void pcibios_set_master(struct pci_dev *dev)
1002 {
1003         /* No special bus mastering setup handling */
1004 }
1005
1006 #ifdef CONFIG_PCI_IOV
1007 int pcibios_add_device(struct pci_dev *dev)
1008 {
1009         struct pci_dev *pdev;
1010
1011         /* Add sriov arch specific initialization here.
1012          * Copy dev_archdata from PF to VF
1013          */
1014         if (dev->is_virtfn) {
1015                 struct dev_archdata *psd;
1016
1017                 pdev = dev->physfn;
1018                 psd = &pdev->dev.archdata;
1019                 pci_init_dev_archdata(&dev->dev.archdata, psd->iommu,
1020                                       psd->stc, psd->host_controller, NULL,
1021                                       psd->numa_node);
1022         }
1023         return 0;
1024 }
1025 #endif /* CONFIG_PCI_IOV */
1026
1027 static int __init pcibios_init(void)
1028 {
1029         pci_dfl_cache_line_size = 64 >> 2;
1030         return 0;
1031 }
1032 subsys_initcall(pcibios_init);
1033
1034 #ifdef CONFIG_SYSFS
1035
1036 #define SLOT_NAME_SIZE  11  /* Max decimal digits + null in u32 */
1037
1038 static void pcie_bus_slot_names(struct pci_bus *pbus)
1039 {
1040         struct pci_dev *pdev;
1041         struct pci_bus *bus;
1042
1043         list_for_each_entry(pdev, &pbus->devices, bus_list) {
1044                 char name[SLOT_NAME_SIZE];
1045                 struct pci_slot *pci_slot;
1046                 const u32 *slot_num;
1047                 int len;
1048
1049                 slot_num = of_get_property(pdev->dev.of_node,
1050                                            "physical-slot#", &len);
1051
1052                 if (slot_num == NULL || len != 4)
1053                         continue;
1054
1055                 snprintf(name, sizeof(name), "%u", slot_num[0]);
1056                 pci_slot = pci_create_slot(pbus, slot_num[0], name, NULL);
1057
1058                 if (IS_ERR(pci_slot))
1059                         pr_err("PCI: pci_create_slot returned %ld.\n",
1060                                PTR_ERR(pci_slot));
1061         }
1062
1063         list_for_each_entry(bus, &pbus->children, node)
1064                 pcie_bus_slot_names(bus);
1065 }
1066
1067 static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus)
1068 {
1069         const struct pci_slot_names {
1070                 u32     slot_mask;
1071                 char    names[0];
1072         } *prop;
1073         const char *sp;
1074         int len, i;
1075         u32 mask;
1076
1077         prop = of_get_property(node, "slot-names", &len);
1078         if (!prop)
1079                 return;
1080
1081         mask = prop->slot_mask;
1082         sp = prop->names;
1083
1084         if (ofpci_verbose)
1085                 printk("PCI: Making slots for [%s] mask[0x%02x]\n",
1086                        node->full_name, mask);
1087
1088         i = 0;
1089         while (mask) {
1090                 struct pci_slot *pci_slot;
1091                 u32 this_bit = 1 << i;
1092
1093                 if (!(mask & this_bit)) {
1094                         i++;
1095                         continue;
1096                 }
1097
1098                 if (ofpci_verbose)
1099                         printk("PCI: Making slot [%s]\n", sp);
1100
1101                 pci_slot = pci_create_slot(bus, i, sp, NULL);
1102                 if (IS_ERR(pci_slot))
1103                         printk(KERN_ERR "PCI: pci_create_slot returned %ld\n",
1104                                PTR_ERR(pci_slot));
1105
1106                 sp += strlen(sp) + 1;
1107                 mask &= ~this_bit;
1108                 i++;
1109         }
1110 }
1111
1112 static int __init of_pci_slot_init(void)
1113 {
1114         struct pci_bus *pbus = NULL;
1115
1116         while ((pbus = pci_find_next_bus(pbus)) != NULL) {
1117                 struct device_node *node;
1118                 struct pci_dev *pdev;
1119
1120                 pdev = list_first_entry(&pbus->devices, struct pci_dev,
1121                                         bus_list);
1122
1123                 if (pdev && pci_is_pcie(pdev)) {
1124                         pcie_bus_slot_names(pbus);
1125                 } else {
1126
1127                         if (pbus->self) {
1128
1129                                 /* PCI->PCI bridge */
1130                                 node = pbus->self->dev.of_node;
1131
1132                         } else {
1133                                 struct pci_pbm_info *pbm = pbus->sysdata;
1134
1135                                 /* Host PCI controller */
1136                                 node = pbm->op->dev.of_node;
1137                         }
1138
1139                         pci_bus_slot_names(node, pbus);
1140                 }
1141         }
1142
1143         return 0;
1144 }
1145 device_initcall(of_pci_slot_init);
1146 #endif