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perf/x86/intel: Add support for PEBSv3 profiling
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_event_intel_ds.c
1 #include <linux/bitops.h>
2 #include <linux/types.h>
3 #include <linux/slab.h>
4
5 #include <asm/perf_event.h>
6 #include <asm/insn.h>
7
8 #include "perf_event.h"
9
10 /* The size of a BTS record in bytes: */
11 #define BTS_RECORD_SIZE 24
12
13 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14 #define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
15 #define PEBS_FIXUP_SIZE PAGE_SIZE
16
17 /*
18 * pebs_record_32 for p4 and core not supported
19
20 struct pebs_record_32 {
21 u32 flags, ip;
22 u32 ax, bc, cx, dx;
23 u32 si, di, bp, sp;
24 };
25
26 */
27
28 union intel_x86_pebs_dse {
29 u64 val;
30 struct {
31 unsigned int ld_dse:4;
32 unsigned int ld_stlb_miss:1;
33 unsigned int ld_locked:1;
34 unsigned int ld_reserved:26;
35 };
36 struct {
37 unsigned int st_l1d_hit:1;
38 unsigned int st_reserved1:3;
39 unsigned int st_stlb_miss:1;
40 unsigned int st_locked:1;
41 unsigned int st_reserved2:26;
42 };
43 };
44
45
46 /*
47 * Map PEBS Load Latency Data Source encodings to generic
48 * memory data source information
49 */
50 #define P(a, b) PERF_MEM_S(a, b)
51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
53
54 static const u64 pebs_data_source[] = {
55 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
56 OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */
57 OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
58 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
59 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
60 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
61 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
62 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
63 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
65 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
66 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
67 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
68 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
69 OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */
70 OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
71 };
72
73 static u64 precise_store_data(u64 status)
74 {
75 union intel_x86_pebs_dse dse;
76 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
77
78 dse.val = status;
79
80 /*
81 * bit 4: TLB access
82 * 1 = stored missed 2nd level TLB
83 *
84 * so it either hit the walker or the OS
85 * otherwise hit 2nd level TLB
86 */
87 if (dse.st_stlb_miss)
88 val |= P(TLB, MISS);
89 else
90 val |= P(TLB, HIT);
91
92 /*
93 * bit 0: hit L1 data cache
94 * if not set, then all we know is that
95 * it missed L1D
96 */
97 if (dse.st_l1d_hit)
98 val |= P(LVL, HIT);
99 else
100 val |= P(LVL, MISS);
101
102 /*
103 * bit 5: Locked prefix
104 */
105 if (dse.st_locked)
106 val |= P(LOCK, LOCKED);
107
108 return val;
109 }
110
111 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
112 {
113 union perf_mem_data_src dse;
114
115 dse.val = PERF_MEM_NA;
116
117 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
118 dse.mem_op = PERF_MEM_OP_STORE;
119 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
120 dse.mem_op = PERF_MEM_OP_LOAD;
121
122 /*
123 * L1 info only valid for following events:
124 *
125 * MEM_UOPS_RETIRED.STLB_MISS_STORES
126 * MEM_UOPS_RETIRED.LOCK_STORES
127 * MEM_UOPS_RETIRED.SPLIT_STORES
128 * MEM_UOPS_RETIRED.ALL_STORES
129 */
130 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
131 if (status & 1)
132 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
133 else
134 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
135 }
136 return dse.val;
137 }
138
139 static u64 load_latency_data(u64 status)
140 {
141 union intel_x86_pebs_dse dse;
142 u64 val;
143 int model = boot_cpu_data.x86_model;
144 int fam = boot_cpu_data.x86;
145
146 dse.val = status;
147
148 /*
149 * use the mapping table for bit 0-3
150 */
151 val = pebs_data_source[dse.ld_dse];
152
153 /*
154 * Nehalem models do not support TLB, Lock infos
155 */
156 if (fam == 0x6 && (model == 26 || model == 30
157 || model == 31 || model == 46)) {
158 val |= P(TLB, NA) | P(LOCK, NA);
159 return val;
160 }
161 /*
162 * bit 4: TLB access
163 * 0 = did not miss 2nd level TLB
164 * 1 = missed 2nd level TLB
165 */
166 if (dse.ld_stlb_miss)
167 val |= P(TLB, MISS) | P(TLB, L2);
168 else
169 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
170
171 /*
172 * bit 5: locked prefix
173 */
174 if (dse.ld_locked)
175 val |= P(LOCK, LOCKED);
176
177 return val;
178 }
179
180 struct pebs_record_core {
181 u64 flags, ip;
182 u64 ax, bx, cx, dx;
183 u64 si, di, bp, sp;
184 u64 r8, r9, r10, r11;
185 u64 r12, r13, r14, r15;
186 };
187
188 struct pebs_record_nhm {
189 u64 flags, ip;
190 u64 ax, bx, cx, dx;
191 u64 si, di, bp, sp;
192 u64 r8, r9, r10, r11;
193 u64 r12, r13, r14, r15;
194 u64 status, dla, dse, lat;
195 };
196
197 /*
198 * Same as pebs_record_nhm, with two additional fields.
199 */
200 struct pebs_record_hsw {
201 u64 flags, ip;
202 u64 ax, bx, cx, dx;
203 u64 si, di, bp, sp;
204 u64 r8, r9, r10, r11;
205 u64 r12, r13, r14, r15;
206 u64 status, dla, dse, lat;
207 u64 real_ip, tsx_tuning;
208 };
209
210 union hsw_tsx_tuning {
211 struct {
212 u32 cycles_last_block : 32,
213 hle_abort : 1,
214 rtm_abort : 1,
215 instruction_abort : 1,
216 non_instruction_abort : 1,
217 retry : 1,
218 data_conflict : 1,
219 capacity_writes : 1,
220 capacity_reads : 1;
221 };
222 u64 value;
223 };
224
225 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
226
227 /* Same as HSW, plus TSC */
228
229 struct pebs_record_skl {
230 u64 flags, ip;
231 u64 ax, bx, cx, dx;
232 u64 si, di, bp, sp;
233 u64 r8, r9, r10, r11;
234 u64 r12, r13, r14, r15;
235 u64 status, dla, dse, lat;
236 u64 real_ip, tsx_tuning;
237 u64 tsc;
238 };
239
240 void init_debug_store_on_cpu(int cpu)
241 {
242 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
243
244 if (!ds)
245 return;
246
247 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
248 (u32)((u64)(unsigned long)ds),
249 (u32)((u64)(unsigned long)ds >> 32));
250 }
251
252 void fini_debug_store_on_cpu(int cpu)
253 {
254 if (!per_cpu(cpu_hw_events, cpu).ds)
255 return;
256
257 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
258 }
259
260 static DEFINE_PER_CPU(void *, insn_buffer);
261
262 static int alloc_pebs_buffer(int cpu)
263 {
264 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
265 int node = cpu_to_node(cpu);
266 int max;
267 void *buffer, *ibuffer;
268
269 if (!x86_pmu.pebs)
270 return 0;
271
272 buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
273 if (unlikely(!buffer))
274 return -ENOMEM;
275
276 /*
277 * HSW+ already provides us the eventing ip; no need to allocate this
278 * buffer then.
279 */
280 if (x86_pmu.intel_cap.pebs_format < 2) {
281 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
282 if (!ibuffer) {
283 kfree(buffer);
284 return -ENOMEM;
285 }
286 per_cpu(insn_buffer, cpu) = ibuffer;
287 }
288
289 max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
290
291 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
292 ds->pebs_index = ds->pebs_buffer_base;
293 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
294 max * x86_pmu.pebs_record_size;
295
296 return 0;
297 }
298
299 static void release_pebs_buffer(int cpu)
300 {
301 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
302
303 if (!ds || !x86_pmu.pebs)
304 return;
305
306 kfree(per_cpu(insn_buffer, cpu));
307 per_cpu(insn_buffer, cpu) = NULL;
308
309 kfree((void *)(unsigned long)ds->pebs_buffer_base);
310 ds->pebs_buffer_base = 0;
311 }
312
313 static int alloc_bts_buffer(int cpu)
314 {
315 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
316 int node = cpu_to_node(cpu);
317 int max, thresh;
318 void *buffer;
319
320 if (!x86_pmu.bts)
321 return 0;
322
323 buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
324 if (unlikely(!buffer)) {
325 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
326 return -ENOMEM;
327 }
328
329 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
330 thresh = max / 16;
331
332 ds->bts_buffer_base = (u64)(unsigned long)buffer;
333 ds->bts_index = ds->bts_buffer_base;
334 ds->bts_absolute_maximum = ds->bts_buffer_base +
335 max * BTS_RECORD_SIZE;
336 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
337 thresh * BTS_RECORD_SIZE;
338
339 return 0;
340 }
341
342 static void release_bts_buffer(int cpu)
343 {
344 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
345
346 if (!ds || !x86_pmu.bts)
347 return;
348
349 kfree((void *)(unsigned long)ds->bts_buffer_base);
350 ds->bts_buffer_base = 0;
351 }
352
353 static int alloc_ds_buffer(int cpu)
354 {
355 int node = cpu_to_node(cpu);
356 struct debug_store *ds;
357
358 ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
359 if (unlikely(!ds))
360 return -ENOMEM;
361
362 per_cpu(cpu_hw_events, cpu).ds = ds;
363
364 return 0;
365 }
366
367 static void release_ds_buffer(int cpu)
368 {
369 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
370
371 if (!ds)
372 return;
373
374 per_cpu(cpu_hw_events, cpu).ds = NULL;
375 kfree(ds);
376 }
377
378 void release_ds_buffers(void)
379 {
380 int cpu;
381
382 if (!x86_pmu.bts && !x86_pmu.pebs)
383 return;
384
385 get_online_cpus();
386 for_each_online_cpu(cpu)
387 fini_debug_store_on_cpu(cpu);
388
389 for_each_possible_cpu(cpu) {
390 release_pebs_buffer(cpu);
391 release_bts_buffer(cpu);
392 release_ds_buffer(cpu);
393 }
394 put_online_cpus();
395 }
396
397 void reserve_ds_buffers(void)
398 {
399 int bts_err = 0, pebs_err = 0;
400 int cpu;
401
402 x86_pmu.bts_active = 0;
403 x86_pmu.pebs_active = 0;
404
405 if (!x86_pmu.bts && !x86_pmu.pebs)
406 return;
407
408 if (!x86_pmu.bts)
409 bts_err = 1;
410
411 if (!x86_pmu.pebs)
412 pebs_err = 1;
413
414 get_online_cpus();
415
416 for_each_possible_cpu(cpu) {
417 if (alloc_ds_buffer(cpu)) {
418 bts_err = 1;
419 pebs_err = 1;
420 }
421
422 if (!bts_err && alloc_bts_buffer(cpu))
423 bts_err = 1;
424
425 if (!pebs_err && alloc_pebs_buffer(cpu))
426 pebs_err = 1;
427
428 if (bts_err && pebs_err)
429 break;
430 }
431
432 if (bts_err) {
433 for_each_possible_cpu(cpu)
434 release_bts_buffer(cpu);
435 }
436
437 if (pebs_err) {
438 for_each_possible_cpu(cpu)
439 release_pebs_buffer(cpu);
440 }
441
442 if (bts_err && pebs_err) {
443 for_each_possible_cpu(cpu)
444 release_ds_buffer(cpu);
445 } else {
446 if (x86_pmu.bts && !bts_err)
447 x86_pmu.bts_active = 1;
448
449 if (x86_pmu.pebs && !pebs_err)
450 x86_pmu.pebs_active = 1;
451
452 for_each_online_cpu(cpu)
453 init_debug_store_on_cpu(cpu);
454 }
455
456 put_online_cpus();
457 }
458
459 /*
460 * BTS
461 */
462
463 struct event_constraint bts_constraint =
464 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
465
466 void intel_pmu_enable_bts(u64 config)
467 {
468 unsigned long debugctlmsr;
469
470 debugctlmsr = get_debugctlmsr();
471
472 debugctlmsr |= DEBUGCTLMSR_TR;
473 debugctlmsr |= DEBUGCTLMSR_BTS;
474 if (config & ARCH_PERFMON_EVENTSEL_INT)
475 debugctlmsr |= DEBUGCTLMSR_BTINT;
476
477 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
478 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
479
480 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
481 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
482
483 update_debugctlmsr(debugctlmsr);
484 }
485
486 void intel_pmu_disable_bts(void)
487 {
488 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
489 unsigned long debugctlmsr;
490
491 if (!cpuc->ds)
492 return;
493
494 debugctlmsr = get_debugctlmsr();
495
496 debugctlmsr &=
497 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
498 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
499
500 update_debugctlmsr(debugctlmsr);
501 }
502
503 int intel_pmu_drain_bts_buffer(void)
504 {
505 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
506 struct debug_store *ds = cpuc->ds;
507 struct bts_record {
508 u64 from;
509 u64 to;
510 u64 flags;
511 };
512 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
513 struct bts_record *at, *top;
514 struct perf_output_handle handle;
515 struct perf_event_header header;
516 struct perf_sample_data data;
517 struct pt_regs regs;
518
519 if (!event)
520 return 0;
521
522 if (!x86_pmu.bts_active)
523 return 0;
524
525 at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
526 top = (struct bts_record *)(unsigned long)ds->bts_index;
527
528 if (top <= at)
529 return 0;
530
531 memset(&regs, 0, sizeof(regs));
532
533 ds->bts_index = ds->bts_buffer_base;
534
535 perf_sample_data_init(&data, 0, event->hw.last_period);
536
537 /*
538 * Prepare a generic sample, i.e. fill in the invariant fields.
539 * We will overwrite the from and to address before we output
540 * the sample.
541 */
542 perf_prepare_sample(&header, &data, event, &regs);
543
544 if (perf_output_begin(&handle, event, header.size * (top - at)))
545 return 1;
546
547 for (; at < top; at++) {
548 data.ip = at->from;
549 data.addr = at->to;
550
551 perf_output_sample(&handle, &header, &data, event);
552 }
553
554 perf_output_end(&handle);
555
556 /* There's new data available. */
557 event->hw.interrupts++;
558 event->pending_kill = POLL_IN;
559 return 1;
560 }
561
562 static inline void intel_pmu_drain_pebs_buffer(void)
563 {
564 struct pt_regs regs;
565
566 x86_pmu.drain_pebs(&regs);
567 }
568
569 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
570 {
571 if (!sched_in)
572 intel_pmu_drain_pebs_buffer();
573 }
574
575 /*
576 * PEBS
577 */
578 struct event_constraint intel_core2_pebs_event_constraints[] = {
579 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
580 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
581 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
582 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
583 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
584 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
585 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
586 EVENT_CONSTRAINT_END
587 };
588
589 struct event_constraint intel_atom_pebs_event_constraints[] = {
590 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
591 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
592 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
593 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
594 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
595 EVENT_CONSTRAINT_END
596 };
597
598 struct event_constraint intel_slm_pebs_event_constraints[] = {
599 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
600 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
601 /* Allow all events as PEBS with no flags */
602 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
603 EVENT_CONSTRAINT_END
604 };
605
606 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
607 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
608 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
609 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
610 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
611 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
612 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
613 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
614 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
615 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
616 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
617 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
618 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
619 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
620 EVENT_CONSTRAINT_END
621 };
622
623 struct event_constraint intel_westmere_pebs_event_constraints[] = {
624 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
625 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
626 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
627 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
628 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
629 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
630 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
631 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
632 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
633 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
634 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
635 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
636 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
637 EVENT_CONSTRAINT_END
638 };
639
640 struct event_constraint intel_snb_pebs_event_constraints[] = {
641 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
642 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
643 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
644 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
645 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
646 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
647 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
648 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
649 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
650 /* Allow all events as PEBS with no flags */
651 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
652 EVENT_CONSTRAINT_END
653 };
654
655 struct event_constraint intel_ivb_pebs_event_constraints[] = {
656 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
657 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
658 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
659 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
660 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
661 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
662 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
663 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
664 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
665 /* Allow all events as PEBS with no flags */
666 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
667 EVENT_CONSTRAINT_END
668 };
669
670 struct event_constraint intel_hsw_pebs_event_constraints[] = {
671 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
672 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
673 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
674 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
675 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
676 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
677 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
678 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
679 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
680 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
681 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
682 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
683 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
684 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
685 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
686 /* Allow all events as PEBS with no flags */
687 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
688 EVENT_CONSTRAINT_END
689 };
690
691 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
692 {
693 struct event_constraint *c;
694
695 if (!event->attr.precise_ip)
696 return NULL;
697
698 if (x86_pmu.pebs_constraints) {
699 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
700 if ((event->hw.config & c->cmask) == c->code) {
701 event->hw.flags |= c->flags;
702 return c;
703 }
704 }
705 }
706
707 return &emptyconstraint;
708 }
709
710 static inline bool pebs_is_enabled(struct cpu_hw_events *cpuc)
711 {
712 return (cpuc->pebs_enabled & ((1ULL << MAX_PEBS_EVENTS) - 1));
713 }
714
715 void intel_pmu_pebs_enable(struct perf_event *event)
716 {
717 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
718 struct hw_perf_event *hwc = &event->hw;
719 struct debug_store *ds = cpuc->ds;
720 bool first_pebs;
721 u64 threshold;
722
723 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
724
725 first_pebs = !pebs_is_enabled(cpuc);
726 cpuc->pebs_enabled |= 1ULL << hwc->idx;
727
728 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
729 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
730 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
731 cpuc->pebs_enabled |= 1ULL << 63;
732
733 /*
734 * When the event is constrained enough we can use a larger
735 * threshold and run the event with less frequent PMI.
736 */
737 if (hwc->flags & PERF_X86_EVENT_FREERUNNING) {
738 threshold = ds->pebs_absolute_maximum -
739 x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
740
741 if (first_pebs)
742 perf_sched_cb_inc(event->ctx->pmu);
743 } else {
744 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
745
746 /*
747 * If not all events can use larger buffer,
748 * roll back to threshold = 1
749 */
750 if (!first_pebs &&
751 (ds->pebs_interrupt_threshold > threshold))
752 perf_sched_cb_dec(event->ctx->pmu);
753 }
754
755 /* Use auto-reload if possible to save a MSR write in the PMI */
756 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
757 ds->pebs_event_reset[hwc->idx] =
758 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
759 }
760
761 if (first_pebs || ds->pebs_interrupt_threshold > threshold)
762 ds->pebs_interrupt_threshold = threshold;
763 }
764
765 void intel_pmu_pebs_disable(struct perf_event *event)
766 {
767 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
768 struct hw_perf_event *hwc = &event->hw;
769 struct debug_store *ds = cpuc->ds;
770
771 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
772
773 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
774 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
775 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
776 cpuc->pebs_enabled &= ~(1ULL << 63);
777
778 if (ds->pebs_interrupt_threshold >
779 ds->pebs_buffer_base + x86_pmu.pebs_record_size) {
780 intel_pmu_drain_pebs_buffer();
781 if (!pebs_is_enabled(cpuc))
782 perf_sched_cb_dec(event->ctx->pmu);
783 }
784
785 if (cpuc->enabled)
786 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
787
788 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
789 }
790
791 void intel_pmu_pebs_enable_all(void)
792 {
793 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
794
795 if (cpuc->pebs_enabled)
796 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
797 }
798
799 void intel_pmu_pebs_disable_all(void)
800 {
801 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
802
803 if (cpuc->pebs_enabled)
804 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
805 }
806
807 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
808 {
809 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
810 unsigned long from = cpuc->lbr_entries[0].from;
811 unsigned long old_to, to = cpuc->lbr_entries[0].to;
812 unsigned long ip = regs->ip;
813 int is_64bit = 0;
814 void *kaddr;
815 int size;
816
817 /*
818 * We don't need to fixup if the PEBS assist is fault like
819 */
820 if (!x86_pmu.intel_cap.pebs_trap)
821 return 1;
822
823 /*
824 * No LBR entry, no basic block, no rewinding
825 */
826 if (!cpuc->lbr_stack.nr || !from || !to)
827 return 0;
828
829 /*
830 * Basic blocks should never cross user/kernel boundaries
831 */
832 if (kernel_ip(ip) != kernel_ip(to))
833 return 0;
834
835 /*
836 * unsigned math, either ip is before the start (impossible) or
837 * the basic block is larger than 1 page (sanity)
838 */
839 if ((ip - to) > PEBS_FIXUP_SIZE)
840 return 0;
841
842 /*
843 * We sampled a branch insn, rewind using the LBR stack
844 */
845 if (ip == to) {
846 set_linear_ip(regs, from);
847 return 1;
848 }
849
850 size = ip - to;
851 if (!kernel_ip(ip)) {
852 int bytes;
853 u8 *buf = this_cpu_read(insn_buffer);
854
855 /* 'size' must fit our buffer, see above */
856 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
857 if (bytes != 0)
858 return 0;
859
860 kaddr = buf;
861 } else {
862 kaddr = (void *)to;
863 }
864
865 do {
866 struct insn insn;
867
868 old_to = to;
869
870 #ifdef CONFIG_X86_64
871 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
872 #endif
873 insn_init(&insn, kaddr, size, is_64bit);
874 insn_get_length(&insn);
875 /*
876 * Make sure there was not a problem decoding the
877 * instruction and getting the length. This is
878 * doubly important because we have an infinite
879 * loop if insn.length=0.
880 */
881 if (!insn.length)
882 break;
883
884 to += insn.length;
885 kaddr += insn.length;
886 size -= insn.length;
887 } while (to < ip);
888
889 if (to == ip) {
890 set_linear_ip(regs, old_to);
891 return 1;
892 }
893
894 /*
895 * Even though we decoded the basic block, the instruction stream
896 * never matched the given IP, either the TO or the IP got corrupted.
897 */
898 return 0;
899 }
900
901 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
902 {
903 if (pebs->tsx_tuning) {
904 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
905 return tsx.cycles_last_block;
906 }
907 return 0;
908 }
909
910 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
911 {
912 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
913
914 /* For RTM XABORTs also log the abort code from AX */
915 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
916 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
917 return txn;
918 }
919
920 static void setup_pebs_sample_data(struct perf_event *event,
921 struct pt_regs *iregs, void *__pebs,
922 struct perf_sample_data *data,
923 struct pt_regs *regs)
924 {
925 #define PERF_X86_EVENT_PEBS_HSW_PREC \
926 (PERF_X86_EVENT_PEBS_ST_HSW | \
927 PERF_X86_EVENT_PEBS_LD_HSW | \
928 PERF_X86_EVENT_PEBS_NA_HSW)
929 /*
930 * We cast to the biggest pebs_record but are careful not to
931 * unconditionally access the 'extra' entries.
932 */
933 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
934 struct pebs_record_skl *pebs = __pebs;
935 u64 sample_type;
936 int fll, fst, dsrc;
937 int fl = event->hw.flags;
938
939 if (pebs == NULL)
940 return;
941
942 sample_type = event->attr.sample_type;
943 dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
944
945 fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
946 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
947
948 perf_sample_data_init(data, 0, event->hw.last_period);
949
950 data->period = event->hw.last_period;
951
952 /*
953 * Use latency for weight (only avail with PEBS-LL)
954 */
955 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
956 data->weight = pebs->lat;
957
958 /*
959 * data.data_src encodes the data source
960 */
961 if (dsrc) {
962 u64 val = PERF_MEM_NA;
963 if (fll)
964 val = load_latency_data(pebs->dse);
965 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
966 val = precise_datala_hsw(event, pebs->dse);
967 else if (fst)
968 val = precise_store_data(pebs->dse);
969 data->data_src.val = val;
970 }
971
972 /*
973 * We use the interrupt regs as a base because the PEBS record
974 * does not contain a full regs set, specifically it seems to
975 * lack segment descriptors, which get used by things like
976 * user_mode().
977 *
978 * In the simple case fix up only the IP and BP,SP regs, for
979 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
980 * A possible PERF_SAMPLE_REGS will have to transfer all regs.
981 */
982 *regs = *iregs;
983 regs->flags = pebs->flags;
984 set_linear_ip(regs, pebs->ip);
985 regs->bp = pebs->bp;
986 regs->sp = pebs->sp;
987
988 if (sample_type & PERF_SAMPLE_REGS_INTR) {
989 regs->ax = pebs->ax;
990 regs->bx = pebs->bx;
991 regs->cx = pebs->cx;
992 regs->dx = pebs->dx;
993 regs->si = pebs->si;
994 regs->di = pebs->di;
995 regs->bp = pebs->bp;
996 regs->sp = pebs->sp;
997
998 regs->flags = pebs->flags;
999 #ifndef CONFIG_X86_32
1000 regs->r8 = pebs->r8;
1001 regs->r9 = pebs->r9;
1002 regs->r10 = pebs->r10;
1003 regs->r11 = pebs->r11;
1004 regs->r12 = pebs->r12;
1005 regs->r13 = pebs->r13;
1006 regs->r14 = pebs->r14;
1007 regs->r15 = pebs->r15;
1008 #endif
1009 }
1010
1011 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
1012 regs->ip = pebs->real_ip;
1013 regs->flags |= PERF_EFLAGS_EXACT;
1014 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
1015 regs->flags |= PERF_EFLAGS_EXACT;
1016 else
1017 regs->flags &= ~PERF_EFLAGS_EXACT;
1018
1019 if ((sample_type & PERF_SAMPLE_ADDR) &&
1020 x86_pmu.intel_cap.pebs_format >= 1)
1021 data->addr = pebs->dla;
1022
1023 if (x86_pmu.intel_cap.pebs_format >= 2) {
1024 /* Only set the TSX weight when no memory weight. */
1025 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1026 data->weight = intel_hsw_weight(pebs);
1027
1028 if (sample_type & PERF_SAMPLE_TRANSACTION)
1029 data->txn = intel_hsw_transaction(pebs);
1030 }
1031
1032 /*
1033 * v3 supplies an accurate time stamp, so we use that
1034 * for the time stamp.
1035 *
1036 * We can only do this for the default trace clock.
1037 */
1038 if (x86_pmu.intel_cap.pebs_format >= 3 &&
1039 event->attr.use_clockid == 0)
1040 data->time = native_sched_clock_from_tsc(pebs->tsc);
1041
1042 if (has_branch_stack(event))
1043 data->br_stack = &cpuc->lbr_stack;
1044 }
1045
1046 static inline void *
1047 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1048 {
1049 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1050 void *at;
1051 u64 pebs_status;
1052
1053 if (base == NULL)
1054 return NULL;
1055
1056 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1057 struct pebs_record_nhm *p = at;
1058
1059 if (test_bit(bit, (unsigned long *)&p->status)) {
1060 /* PEBS v3 has accurate status bits */
1061 if (x86_pmu.intel_cap.pebs_format >= 3)
1062 return at;
1063
1064 if (p->status == (1 << bit))
1065 return at;
1066
1067 /* clear non-PEBS bit and re-check */
1068 pebs_status = p->status & cpuc->pebs_enabled;
1069 pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1;
1070 if (pebs_status == (1 << bit))
1071 return at;
1072 }
1073 }
1074 return NULL;
1075 }
1076
1077 static void __intel_pmu_pebs_event(struct perf_event *event,
1078 struct pt_regs *iregs,
1079 void *base, void *top,
1080 int bit, int count)
1081 {
1082 struct perf_sample_data data;
1083 struct pt_regs regs;
1084 void *at = get_next_pebs_record_by_bit(base, top, bit);
1085
1086 if (!intel_pmu_save_and_restart(event) &&
1087 !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
1088 return;
1089
1090 while (count > 1) {
1091 setup_pebs_sample_data(event, iregs, at, &data, &regs);
1092 perf_event_output(event, &data, &regs);
1093 at += x86_pmu.pebs_record_size;
1094 at = get_next_pebs_record_by_bit(at, top, bit);
1095 count--;
1096 }
1097
1098 setup_pebs_sample_data(event, iregs, at, &data, &regs);
1099
1100 /*
1101 * All but the last records are processed.
1102 * The last one is left to be able to call the overflow handler.
1103 */
1104 if (perf_event_overflow(event, &data, &regs)) {
1105 x86_pmu_stop(event, 0);
1106 return;
1107 }
1108
1109 }
1110
1111 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1112 {
1113 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1114 struct debug_store *ds = cpuc->ds;
1115 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1116 struct pebs_record_core *at, *top;
1117 int n;
1118
1119 if (!x86_pmu.pebs_active)
1120 return;
1121
1122 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1123 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1124
1125 /*
1126 * Whatever else happens, drain the thing
1127 */
1128 ds->pebs_index = ds->pebs_buffer_base;
1129
1130 if (!test_bit(0, cpuc->active_mask))
1131 return;
1132
1133 WARN_ON_ONCE(!event);
1134
1135 if (!event->attr.precise_ip)
1136 return;
1137
1138 n = (top - at) / x86_pmu.pebs_record_size;
1139 if (n <= 0)
1140 return;
1141
1142 __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1143 }
1144
1145 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1146 {
1147 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1148 struct debug_store *ds = cpuc->ds;
1149 struct perf_event *event;
1150 void *base, *at, *top;
1151 short counts[MAX_PEBS_EVENTS] = {};
1152 short error[MAX_PEBS_EVENTS] = {};
1153 int bit, i;
1154
1155 if (!x86_pmu.pebs_active)
1156 return;
1157
1158 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1159 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1160
1161 ds->pebs_index = ds->pebs_buffer_base;
1162
1163 if (unlikely(base >= top))
1164 return;
1165
1166 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1167 struct pebs_record_nhm *p = at;
1168
1169 /* PEBS v3 has accurate status bits */
1170 if (x86_pmu.intel_cap.pebs_format >= 3) {
1171 for_each_set_bit(bit, (unsigned long *)&p->status,
1172 MAX_PEBS_EVENTS)
1173 counts[bit]++;
1174
1175 continue;
1176 }
1177
1178 bit = find_first_bit((unsigned long *)&p->status,
1179 x86_pmu.max_pebs_events);
1180 if (bit >= x86_pmu.max_pebs_events)
1181 continue;
1182 if (!test_bit(bit, cpuc->active_mask))
1183 continue;
1184 /*
1185 * The PEBS hardware does not deal well with the situation
1186 * when events happen near to each other and multiple bits
1187 * are set. But it should happen rarely.
1188 *
1189 * If these events include one PEBS and multiple non-PEBS
1190 * events, it doesn't impact PEBS record. The record will
1191 * be handled normally. (slow path)
1192 *
1193 * If these events include two or more PEBS events, the
1194 * records for the events can be collapsed into a single
1195 * one, and it's not possible to reconstruct all events
1196 * that caused the PEBS record. It's called collision.
1197 * If collision happened, the record will be dropped.
1198 *
1199 */
1200 if (p->status != (1 << bit)) {
1201 u64 pebs_status;
1202
1203 /* slow path */
1204 pebs_status = p->status & cpuc->pebs_enabled;
1205 pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1;
1206 if (pebs_status != (1 << bit)) {
1207 for_each_set_bit(i, (unsigned long *)&pebs_status,
1208 MAX_PEBS_EVENTS)
1209 error[i]++;
1210 continue;
1211 }
1212 }
1213 counts[bit]++;
1214 }
1215
1216 for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1217 if ((counts[bit] == 0) && (error[bit] == 0))
1218 continue;
1219 event = cpuc->events[bit];
1220 WARN_ON_ONCE(!event);
1221 WARN_ON_ONCE(!event->attr.precise_ip);
1222
1223 /* log dropped samples number */
1224 if (error[bit])
1225 perf_log_lost_samples(event, error[bit]);
1226
1227 if (counts[bit]) {
1228 __intel_pmu_pebs_event(event, iregs, base,
1229 top, bit, counts[bit]);
1230 }
1231 }
1232 }
1233
1234 /*
1235 * BTS, PEBS probe and setup
1236 */
1237
1238 void __init intel_ds_init(void)
1239 {
1240 /*
1241 * No support for 32bit formats
1242 */
1243 if (!boot_cpu_has(X86_FEATURE_DTES64))
1244 return;
1245
1246 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1247 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1248 if (x86_pmu.pebs) {
1249 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1250 int format = x86_pmu.intel_cap.pebs_format;
1251
1252 switch (format) {
1253 case 0:
1254 printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1255 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1256 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1257 break;
1258
1259 case 1:
1260 printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1261 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1262 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1263 break;
1264
1265 case 2:
1266 pr_cont("PEBS fmt2%c, ", pebs_type);
1267 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1268 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1269 break;
1270
1271 case 3:
1272 pr_cont("PEBS fmt3%c, ", pebs_type);
1273 x86_pmu.pebs_record_size =
1274 sizeof(struct pebs_record_skl);
1275 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1276 break;
1277
1278 default:
1279 printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1280 x86_pmu.pebs = 0;
1281 }
1282 }
1283 }
1284
1285 void perf_restore_debug_store(void)
1286 {
1287 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1288
1289 if (!x86_pmu.bts && !x86_pmu.pebs)
1290 return;
1291
1292 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1293 }
Linux kernel - Deliverables
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