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x86/irq: Fix do_IRQ() interrupt warning for cpu hotplug retriggered irqs
[deliverable/linux.git] / arch / x86 / kernel / irq.c
1 /*
2 * Common interrupt code for 32 and 64 bit
3 */
4 #include <linux/cpu.h>
5 #include <linux/interrupt.h>
6 #include <linux/kernel_stat.h>
7 #include <linux/of.h>
8 #include <linux/seq_file.h>
9 #include <linux/smp.h>
10 #include <linux/ftrace.h>
11 #include <linux/delay.h>
12 #include <linux/export.h>
13
14 #include <asm/apic.h>
15 #include <asm/io_apic.h>
16 #include <asm/irq.h>
17 #include <asm/idle.h>
18 #include <asm/mce.h>
19 #include <asm/hw_irq.h>
20
21 #define CREATE_TRACE_POINTS
22 #include <asm/trace/irq_vectors.h>
23
24 atomic_t irq_err_count;
25
26 /* Function pointer for generic interrupt vector handling */
27 void (*x86_platform_ipi_callback)(void) = NULL;
28
29 /*
30 * 'what should we do if we get a hw irq event on an illegal vector'.
31 * each architecture has to answer this themselves.
32 */
33 void ack_bad_irq(unsigned int irq)
34 {
35 if (printk_ratelimit())
36 pr_err("unexpected IRQ trap at vector %02x\n", irq);
37
38 /*
39 * Currently unexpected vectors happen only on SMP and APIC.
40 * We _must_ ack these because every local APIC has only N
41 * irq slots per priority level, and a 'hanging, unacked' IRQ
42 * holds up an irq slot - in excessive cases (when multiple
43 * unexpected vectors occur) that might lock up the APIC
44 * completely.
45 * But only ack when the APIC is enabled -AK
46 */
47 ack_APIC_irq();
48 }
49
50 #define irq_stats(x) (&per_cpu(irq_stat, x))
51 /*
52 * /proc/interrupts printing for arch specific interrupts
53 */
54 int arch_show_interrupts(struct seq_file *p, int prec)
55 {
56 int j;
57
58 seq_printf(p, "%*s: ", prec, "NMI");
59 for_each_online_cpu(j)
60 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
61 seq_printf(p, " Non-maskable interrupts\n");
62 #ifdef CONFIG_X86_LOCAL_APIC
63 seq_printf(p, "%*s: ", prec, "LOC");
64 for_each_online_cpu(j)
65 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
66 seq_printf(p, " Local timer interrupts\n");
67
68 seq_printf(p, "%*s: ", prec, "SPU");
69 for_each_online_cpu(j)
70 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
71 seq_printf(p, " Spurious interrupts\n");
72 seq_printf(p, "%*s: ", prec, "PMI");
73 for_each_online_cpu(j)
74 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
75 seq_printf(p, " Performance monitoring interrupts\n");
76 seq_printf(p, "%*s: ", prec, "IWI");
77 for_each_online_cpu(j)
78 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
79 seq_printf(p, " IRQ work interrupts\n");
80 seq_printf(p, "%*s: ", prec, "RTR");
81 for_each_online_cpu(j)
82 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
83 seq_printf(p, " APIC ICR read retries\n");
84 #endif
85 if (x86_platform_ipi_callback) {
86 seq_printf(p, "%*s: ", prec, "PLT");
87 for_each_online_cpu(j)
88 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
89 seq_printf(p, " Platform interrupts\n");
90 }
91 #ifdef CONFIG_SMP
92 seq_printf(p, "%*s: ", prec, "RES");
93 for_each_online_cpu(j)
94 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
95 seq_printf(p, " Rescheduling interrupts\n");
96 seq_printf(p, "%*s: ", prec, "CAL");
97 for_each_online_cpu(j)
98 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count -
99 irq_stats(j)->irq_tlb_count);
100 seq_printf(p, " Function call interrupts\n");
101 seq_printf(p, "%*s: ", prec, "TLB");
102 for_each_online_cpu(j)
103 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
104 seq_printf(p, " TLB shootdowns\n");
105 #endif
106 #ifdef CONFIG_X86_THERMAL_VECTOR
107 seq_printf(p, "%*s: ", prec, "TRM");
108 for_each_online_cpu(j)
109 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
110 seq_printf(p, " Thermal event interrupts\n");
111 #endif
112 #ifdef CONFIG_X86_MCE_THRESHOLD
113 seq_printf(p, "%*s: ", prec, "THR");
114 for_each_online_cpu(j)
115 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
116 seq_printf(p, " Threshold APIC interrupts\n");
117 #endif
118 #ifdef CONFIG_X86_MCE
119 seq_printf(p, "%*s: ", prec, "MCE");
120 for_each_online_cpu(j)
121 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
122 seq_printf(p, " Machine check exceptions\n");
123 seq_printf(p, "%*s: ", prec, "MCP");
124 for_each_online_cpu(j)
125 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
126 seq_printf(p, " Machine check polls\n");
127 #endif
128 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
129 #if defined(CONFIG_X86_IO_APIC)
130 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
131 #endif
132 return 0;
133 }
134
135 /*
136 * /proc/stat helpers
137 */
138 u64 arch_irq_stat_cpu(unsigned int cpu)
139 {
140 u64 sum = irq_stats(cpu)->__nmi_count;
141
142 #ifdef CONFIG_X86_LOCAL_APIC
143 sum += irq_stats(cpu)->apic_timer_irqs;
144 sum += irq_stats(cpu)->irq_spurious_count;
145 sum += irq_stats(cpu)->apic_perf_irqs;
146 sum += irq_stats(cpu)->apic_irq_work_irqs;
147 sum += irq_stats(cpu)->icr_read_retry_count;
148 #endif
149 if (x86_platform_ipi_callback)
150 sum += irq_stats(cpu)->x86_platform_ipis;
151 #ifdef CONFIG_SMP
152 sum += irq_stats(cpu)->irq_resched_count;
153 sum += irq_stats(cpu)->irq_call_count;
154 #endif
155 #ifdef CONFIG_X86_THERMAL_VECTOR
156 sum += irq_stats(cpu)->irq_thermal_count;
157 #endif
158 #ifdef CONFIG_X86_MCE_THRESHOLD
159 sum += irq_stats(cpu)->irq_threshold_count;
160 #endif
161 #ifdef CONFIG_X86_MCE
162 sum += per_cpu(mce_exception_count, cpu);
163 sum += per_cpu(mce_poll_count, cpu);
164 #endif
165 return sum;
166 }
167
168 u64 arch_irq_stat(void)
169 {
170 u64 sum = atomic_read(&irq_err_count);
171 return sum;
172 }
173
174
175 /*
176 * do_IRQ handles all normal device IRQ's (the special
177 * SMP cross-CPU interrupts have their own specific
178 * handlers).
179 */
180 __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
181 {
182 struct pt_regs *old_regs = set_irq_regs(regs);
183
184 /* high bit used in ret_from_ code */
185 unsigned vector = ~regs->orig_ax;
186 unsigned irq;
187
188 irq_enter();
189 exit_idle();
190
191 irq = __this_cpu_read(vector_irq[vector]);
192
193 if (!handle_irq(irq, regs)) {
194 ack_APIC_irq();
195
196 if (irq != VECTOR_RETRIGGERED) {
197 pr_emerg_ratelimited("%s: %d.%d No irq handler for vector (irq %d)\n",
198 __func__, smp_processor_id(),
199 vector, irq);
200 } else {
201 __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
202 }
203 }
204
205 irq_exit();
206
207 set_irq_regs(old_regs);
208 return 1;
209 }
210
211 /*
212 * Handler for X86_PLATFORM_IPI_VECTOR.
213 */
214 void __smp_x86_platform_ipi(void)
215 {
216 inc_irq_stat(x86_platform_ipis);
217
218 if (x86_platform_ipi_callback)
219 x86_platform_ipi_callback();
220 }
221
222 __visible void smp_x86_platform_ipi(struct pt_regs *regs)
223 {
224 struct pt_regs *old_regs = set_irq_regs(regs);
225
226 entering_ack_irq();
227 __smp_x86_platform_ipi();
228 exiting_irq();
229 set_irq_regs(old_regs);
230 }
231
232 #ifdef CONFIG_HAVE_KVM
233 /*
234 * Handler for POSTED_INTERRUPT_VECTOR.
235 */
236 __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
237 {
238 struct pt_regs *old_regs = set_irq_regs(regs);
239
240 ack_APIC_irq();
241
242 irq_enter();
243
244 exit_idle();
245
246 inc_irq_stat(kvm_posted_intr_ipis);
247
248 irq_exit();
249
250 set_irq_regs(old_regs);
251 }
252 #endif
253
254 __visible void smp_trace_x86_platform_ipi(struct pt_regs *regs)
255 {
256 struct pt_regs *old_regs = set_irq_regs(regs);
257
258 entering_ack_irq();
259 trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
260 __smp_x86_platform_ipi();
261 trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
262 exiting_irq();
263 set_irq_regs(old_regs);
264 }
265
266 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
267
268 #ifdef CONFIG_HOTPLUG_CPU
269 /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
270 void fixup_irqs(void)
271 {
272 unsigned int irq, vector;
273 static int warned;
274 struct irq_desc *desc;
275 struct irq_data *data;
276 struct irq_chip *chip;
277
278 for_each_irq_desc(irq, desc) {
279 int break_affinity = 0;
280 int set_affinity = 1;
281 const struct cpumask *affinity;
282
283 if (!desc)
284 continue;
285 if (irq == 2)
286 continue;
287
288 /* interrupt's are disabled at this point */
289 raw_spin_lock(&desc->lock);
290
291 data = irq_desc_get_irq_data(desc);
292 affinity = data->affinity;
293 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
294 cpumask_subset(affinity, cpu_online_mask)) {
295 raw_spin_unlock(&desc->lock);
296 continue;
297 }
298
299 /*
300 * Complete the irq move. This cpu is going down and for
301 * non intr-remapping case, we can't wait till this interrupt
302 * arrives at this cpu before completing the irq move.
303 */
304 irq_force_complete_move(irq);
305
306 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
307 break_affinity = 1;
308 affinity = cpu_online_mask;
309 }
310
311 chip = irq_data_get_irq_chip(data);
312 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
313 chip->irq_mask(data);
314
315 if (chip->irq_set_affinity)
316 chip->irq_set_affinity(data, affinity, true);
317 else if (!(warned++))
318 set_affinity = 0;
319
320 /*
321 * We unmask if the irq was not marked masked by the
322 * core code. That respects the lazy irq disable
323 * behaviour.
324 */
325 if (!irqd_can_move_in_process_context(data) &&
326 !irqd_irq_masked(data) && chip->irq_unmask)
327 chip->irq_unmask(data);
328
329 raw_spin_unlock(&desc->lock);
330
331 if (break_affinity && set_affinity)
332 pr_notice("Broke affinity for irq %i\n", irq);
333 else if (!set_affinity)
334 pr_notice("Cannot set affinity for irq %i\n", irq);
335 }
336
337 /*
338 * We can remove mdelay() and then send spuriuous interrupts to
339 * new cpu targets for all the irqs that were handled previously by
340 * this cpu. While it works, I have seen spurious interrupt messages
341 * (nothing wrong but still...).
342 *
343 * So for now, retain mdelay(1) and check the IRR and then send those
344 * interrupts to new targets as this cpu is already offlined...
345 */
346 mdelay(1);
347
348 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
349 unsigned int irr;
350
351 if (__this_cpu_read(vector_irq[vector]) <= VECTOR_UNDEFINED)
352 continue;
353
354 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
355 if (irr & (1 << (vector % 32))) {
356 irq = __this_cpu_read(vector_irq[vector]);
357
358 desc = irq_to_desc(irq);
359 data = irq_desc_get_irq_data(desc);
360 chip = irq_data_get_irq_chip(data);
361 raw_spin_lock(&desc->lock);
362 if (chip->irq_retrigger) {
363 chip->irq_retrigger(data);
364 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
365 }
366 raw_spin_unlock(&desc->lock);
367 }
368 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
369 __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
370 }
371 }
372 #endif
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